2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 #include "tu_private.h"
30 #include "util/debug.h"
31 #include "util/u_atomic.h"
32 #include "util/format/u_format.h"
33 #include "vk_format.h"
35 #include "drm-uapi/drm_fourcc.h"
40 tu6_plane_count(VkFormat format
)
45 case VK_FORMAT_G8_B8R8_2PLANE_420_UNORM
:
46 case VK_FORMAT_D32_SFLOAT_S8_UINT
:
48 case VK_FORMAT_G8_B8_R8_3PLANE_420_UNORM
:
54 tu6_plane_format(VkFormat format
, uint32_t plane
)
57 case VK_FORMAT_G8_B8R8_2PLANE_420_UNORM
:
58 /* note: with UBWC, and Y plane UBWC is different from R8_UNORM */
59 return plane
? VK_FORMAT_R8G8_UNORM
: VK_FORMAT_R8_UNORM
;
60 case VK_FORMAT_G8_B8_R8_3PLANE_420_UNORM
:
61 return VK_FORMAT_R8_UNORM
;
62 case VK_FORMAT_D32_SFLOAT_S8_UINT
:
63 return plane
? VK_FORMAT_S8_UINT
: VK_FORMAT_D32_SFLOAT
;
70 tu6_plane_index(VkFormat format
, VkImageAspectFlags aspect_mask
)
72 switch (aspect_mask
) {
75 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
77 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
79 case VK_IMAGE_ASPECT_STENCIL_BIT
:
80 return format
== VK_FORMAT_D32_SFLOAT_S8_UINT
;
85 tu_image_create(VkDevice _device
,
86 const VkImageCreateInfo
*pCreateInfo
,
87 const VkAllocationCallbacks
*alloc
,
90 const VkSubresourceLayout
*plane_layouts
)
92 TU_FROM_HANDLE(tu_device
, device
, _device
);
93 struct tu_image
*image
= NULL
;
94 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO
);
96 assert(pCreateInfo
->mipLevels
> 0);
97 assert(pCreateInfo
->arrayLayers
> 0);
98 assert(pCreateInfo
->samples
> 0);
99 assert(pCreateInfo
->extent
.width
> 0);
100 assert(pCreateInfo
->extent
.height
> 0);
101 assert(pCreateInfo
->extent
.depth
> 0);
103 image
= vk_object_zalloc(&device
->vk
, alloc
, sizeof(*image
),
104 VK_OBJECT_TYPE_IMAGE
);
106 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
108 image
->type
= pCreateInfo
->imageType
;
110 image
->vk_format
= pCreateInfo
->format
;
111 image
->tiling
= pCreateInfo
->tiling
;
112 image
->usage
= pCreateInfo
->usage
;
113 image
->flags
= pCreateInfo
->flags
;
114 image
->extent
= pCreateInfo
->extent
;
115 image
->level_count
= pCreateInfo
->mipLevels
;
116 image
->layer_count
= pCreateInfo
->arrayLayers
;
117 image
->samples
= pCreateInfo
->samples
;
119 image
->exclusive
= pCreateInfo
->sharingMode
== VK_SHARING_MODE_EXCLUSIVE
;
120 if (pCreateInfo
->sharingMode
== VK_SHARING_MODE_CONCURRENT
) {
121 for (uint32_t i
= 0; i
< pCreateInfo
->queueFamilyIndexCount
; ++i
)
122 if (pCreateInfo
->pQueueFamilyIndices
[i
] ==
123 VK_QUEUE_FAMILY_EXTERNAL
)
124 image
->queue_family_mask
|= (1u << TU_MAX_QUEUE_FAMILIES
) - 1u;
126 image
->queue_family_mask
|=
127 1u << pCreateInfo
->pQueueFamilyIndices
[i
];
131 vk_find_struct_const(pCreateInfo
->pNext
,
132 EXTERNAL_MEMORY_IMAGE_CREATE_INFO
) != NULL
;
134 enum a6xx_tile_mode tile_mode
= TILE6_3
;
136 !(device
->physical_device
->instance
->debug_flags
& TU_DEBUG_NOUBWC
);
138 /* disable tiling when linear is requested, for YUYV/UYVY, and for mutable
139 * images. Mutable images can be reinterpreted as any other compatible
140 * format, including swapped formats which aren't supported with tiling.
141 * This means that we have to fall back to linear almost always. However
142 * depth and stencil formats cannot be reintepreted as another format, and
143 * cannot be linear with sysmem rendering, so don't fall back for those.
145 * TODO: Be smarter and use usage bits and VK_KHR_image_format_list to
146 * enable tiling and/or UBWC when possible.
148 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
||
149 modifier
== DRM_FORMAT_MOD_LINEAR
||
150 vk_format_description(image
->vk_format
)->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
||
151 (pCreateInfo
->flags
& VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
&&
152 !vk_format_is_depth_or_stencil(image
->vk_format
))) {
153 tile_mode
= TILE6_LINEAR
;
154 ubwc_enabled
= false;
157 /* UBWC is supported for these formats, but NV12 has a special UBWC
158 * format for accessing the Y plane aspect, which isn't implemented
159 * For IYUV, the blob doesn't use UBWC, but it seems to work, but
160 * disable it since we don't know if a special UBWC format is needed
163 * Disable tiling completely, because we set the TILE_ALL bit to
164 * match the blob, however fdl expects the TILE_ALL bit to not be
165 * set for non-UBWC tiled formats
167 if (image
->vk_format
== VK_FORMAT_G8_B8R8_2PLANE_420_UNORM
||
168 image
->vk_format
== VK_FORMAT_G8_B8_R8_3PLANE_420_UNORM
) {
169 tile_mode
= TILE6_LINEAR
;
170 ubwc_enabled
= false;
173 /* don't use UBWC with compressed formats */
174 if (vk_format_is_compressed(image
->vk_format
))
175 ubwc_enabled
= false;
177 /* UBWC can't be used with E5B9G9R9 */
178 if (image
->vk_format
== VK_FORMAT_E5B9G9R9_UFLOAT_PACK32
)
179 ubwc_enabled
= false;
181 /* separate stencil doesn't have a UBWC enable bit */
182 if (image
->vk_format
== VK_FORMAT_S8_UINT
)
183 ubwc_enabled
= false;
185 if (image
->extent
.depth
> 1) {
186 tu_finishme("UBWC with 3D textures");
187 ubwc_enabled
= false;
190 /* Disable UBWC for storage images.
192 * The closed GL driver skips UBWC for storage images (and additionally
193 * uses linear for writeonly images). We seem to have image tiling working
194 * in freedreno in general, so turnip matches that. freedreno also enables
195 * UBWC on images, but it's not really tested due to the lack of
196 * UBWC-enabled mipmaps in freedreno currently. Just match the closed GL
197 * behavior of no UBWC.
199 if (image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
)
200 ubwc_enabled
= false;
202 /* Disable UBWC for D24S8 on A630 in some cases
204 * VK_IMAGE_ASPECT_STENCIL_BIT image view requires to be able to sample
205 * from the stencil component as UINT, however no format allows this
206 * on a630 (the special FMT6_Z24_UINT_S8_UINT format is missing)
208 * It must be sampled as FMT6_8_8_8_8_UINT, which is not UBWC-compatible
210 * Additionally, the special AS_R8G8B8A8 format is broken without UBWC,
211 * so we have to fallback to 8_8_8_8_UNORM when UBWC is disabled
213 if (device
->physical_device
->limited_z24s8
&&
214 image
->vk_format
== VK_FORMAT_D24_UNORM_S8_UINT
&&
215 (image
->usage
& (VK_IMAGE_USAGE_SAMPLED_BIT
| VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))) {
216 ubwc_enabled
= false;
219 /* expect UBWC enabled if we asked for it */
220 assert(modifier
!= DRM_FORMAT_MOD_QCOM_COMPRESSED
|| ubwc_enabled
);
222 for (uint32_t i
= 0; i
< tu6_plane_count(image
->vk_format
); i
++) {
223 struct fdl_layout
*layout
= &image
->layout
[i
];
224 VkFormat format
= tu6_plane_format(image
->vk_format
, i
);
225 uint32_t width0
= pCreateInfo
->extent
.width
;
226 uint32_t height0
= pCreateInfo
->extent
.height
;
229 switch (image
->vk_format
) {
230 case VK_FORMAT_G8_B8R8_2PLANE_420_UNORM
:
231 case VK_FORMAT_G8_B8_R8_3PLANE_420_UNORM
:
232 /* half width/height on chroma planes */
233 width0
= (width0
+ 1) >> 1;
234 height0
= (height0
+ 1) >> 1;
236 case VK_FORMAT_D32_SFLOAT_S8_UINT
:
237 /* no UBWC for separate stencil */
238 ubwc_enabled
= false;
245 struct fdl_explicit_layout plane_layout
;
248 /* only expect simple 2D images for now */
249 if (pCreateInfo
->mipLevels
!= 1 ||
250 pCreateInfo
->arrayLayers
!= 1 ||
251 image
->extent
.depth
!= 1)
254 plane_layout
.offset
= plane_layouts
[i
].offset
;
255 plane_layout
.pitch
= plane_layouts
[i
].rowPitch
;
256 /* note: use plane_layouts[0].arrayPitch to support array formats */
259 layout
->tile_mode
= tile_mode
;
260 layout
->ubwc
= ubwc_enabled
;
262 if (!fdl6_layout(layout
, vk_format_to_pipe_format(format
),
265 pCreateInfo
->extent
.depth
,
266 pCreateInfo
->mipLevels
,
267 pCreateInfo
->arrayLayers
,
268 pCreateInfo
->imageType
== VK_IMAGE_TYPE_3D
,
269 plane_layouts
? &plane_layout
: NULL
)) {
270 assert(plane_layouts
); /* can only fail with explicit layout */
274 /* fdl6_layout can't take explicit offset without explicit pitch
275 * add offset manually for extra layouts for planes
277 if (!plane_layouts
&& i
> 0) {
278 uint32_t offset
= ALIGN_POT(image
->total_size
, 4096);
279 for (int i
= 0; i
< pCreateInfo
->mipLevels
; i
++) {
280 layout
->slices
[i
].offset
+= offset
;
281 layout
->ubwc_slices
[i
].offset
+= offset
;
283 layout
->size
+= offset
;
286 image
->total_size
= MAX2(image
->total_size
, layout
->size
);
289 *pImage
= tu_image_to_handle(image
);
294 vk_object_free(&device
->vk
, alloc
, image
);
295 return vk_error(device
->instance
, VK_ERROR_INVALID_DRM_FORMAT_MODIFIER_PLANE_LAYOUT_EXT
);
299 compose_swizzle(unsigned char *swiz
, const VkComponentMapping
*mapping
)
301 unsigned char src_swiz
[4] = { swiz
[0], swiz
[1], swiz
[2], swiz
[3] };
302 VkComponentSwizzle vk_swiz
[4] = {
303 mapping
->r
, mapping
->g
, mapping
->b
, mapping
->a
305 for (int i
= 0; i
< 4; i
++) {
306 switch (vk_swiz
[i
]) {
307 case VK_COMPONENT_SWIZZLE_IDENTITY
:
308 swiz
[i
] = src_swiz
[i
];
310 case VK_COMPONENT_SWIZZLE_R
...VK_COMPONENT_SWIZZLE_A
:
311 swiz
[i
] = src_swiz
[vk_swiz
[i
] - VK_COMPONENT_SWIZZLE_R
];
313 case VK_COMPONENT_SWIZZLE_ZERO
:
314 swiz
[i
] = A6XX_TEX_ZERO
;
316 case VK_COMPONENT_SWIZZLE_ONE
:
317 swiz
[i
] = A6XX_TEX_ONE
;
320 unreachable("unexpected swizzle");
326 tu6_texswiz(const VkComponentMapping
*comps
,
327 const struct tu_sampler_ycbcr_conversion
*conversion
,
329 VkImageAspectFlagBits aspect_mask
,
332 unsigned char swiz
[4] = {
333 A6XX_TEX_X
, A6XX_TEX_Y
, A6XX_TEX_Z
, A6XX_TEX_W
,
337 case VK_FORMAT_G8B8G8R8_422_UNORM
:
338 case VK_FORMAT_B8G8R8G8_422_UNORM
:
339 case VK_FORMAT_G8_B8R8_2PLANE_420_UNORM
:
340 case VK_FORMAT_G8_B8_R8_3PLANE_420_UNORM
:
341 swiz
[0] = A6XX_TEX_Z
;
342 swiz
[1] = A6XX_TEX_X
;
343 swiz
[2] = A6XX_TEX_Y
;
345 case VK_FORMAT_BC1_RGB_UNORM_BLOCK
:
346 case VK_FORMAT_BC1_RGB_SRGB_BLOCK
:
347 /* same hardware format is used for BC1_RGB / BC1_RGBA */
348 swiz
[3] = A6XX_TEX_ONE
;
350 case VK_FORMAT_D24_UNORM_S8_UINT
:
351 if (aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
) {
353 /* using FMT6_8_8_8_8_UINT */
354 swiz
[0] = A6XX_TEX_W
;
355 swiz
[1] = A6XX_TEX_ZERO
;
357 /* using FMT6_Z24_UINT_S8_UINT */
358 swiz
[0] = A6XX_TEX_Y
;
359 swiz
[1] = A6XX_TEX_ZERO
;
366 compose_swizzle(swiz
, comps
);
368 compose_swizzle(swiz
, &conversion
->components
);
370 return A6XX_TEX_CONST_0_SWIZ_X(swiz
[0]) |
371 A6XX_TEX_CONST_0_SWIZ_Y(swiz
[1]) |
372 A6XX_TEX_CONST_0_SWIZ_Z(swiz
[2]) |
373 A6XX_TEX_CONST_0_SWIZ_W(swiz
[3]);
377 tu_cs_image_ref(struct tu_cs
*cs
, const struct tu_image_view
*iview
, uint32_t layer
)
379 tu_cs_emit(cs
, iview
->PITCH
);
380 tu_cs_emit(cs
, iview
->layer_size
>> 6);
381 tu_cs_emit_qw(cs
, iview
->base_addr
+ iview
->layer_size
* layer
);
385 tu_cs_image_stencil_ref(struct tu_cs
*cs
, const struct tu_image_view
*iview
, uint32_t layer
)
387 tu_cs_emit(cs
, iview
->stencil_PITCH
);
388 tu_cs_emit(cs
, iview
->stencil_layer_size
>> 6);
389 tu_cs_emit_qw(cs
, iview
->stencil_base_addr
+ iview
->stencil_layer_size
* layer
);
393 tu_cs_image_ref_2d(struct tu_cs
*cs
, const struct tu_image_view
*iview
, uint32_t layer
, bool src
)
395 tu_cs_emit_qw(cs
, iview
->base_addr
+ iview
->layer_size
* layer
);
396 /* SP_PS_2D_SRC_PITCH has shifted pitch field */
397 tu_cs_emit(cs
, iview
->PITCH
<< (src
? 9 : 0));
401 tu_cs_image_flag_ref(struct tu_cs
*cs
, const struct tu_image_view
*iview
, uint32_t layer
)
403 tu_cs_emit_qw(cs
, iview
->ubwc_addr
+ iview
->ubwc_layer_size
* layer
);
404 tu_cs_emit(cs
, iview
->FLAG_BUFFER_PITCH
);
408 tu_image_view_init(struct tu_image_view
*iview
,
409 const VkImageViewCreateInfo
*pCreateInfo
,
412 TU_FROM_HANDLE(tu_image
, image
, pCreateInfo
->image
);
413 const VkImageSubresourceRange
*range
= &pCreateInfo
->subresourceRange
;
414 VkFormat format
= pCreateInfo
->format
;
415 VkImageAspectFlagBits aspect_mask
= pCreateInfo
->subresourceRange
.aspectMask
;
417 const struct VkSamplerYcbcrConversionInfo
*ycbcr_conversion
=
418 vk_find_struct_const(pCreateInfo
->pNext
, SAMPLER_YCBCR_CONVERSION_INFO
);
419 const struct tu_sampler_ycbcr_conversion
*conversion
= ycbcr_conversion
?
420 tu_sampler_ycbcr_conversion_from_handle(ycbcr_conversion
->conversion
) : NULL
;
422 switch (image
->type
) {
423 case VK_IMAGE_TYPE_1D
:
424 case VK_IMAGE_TYPE_2D
:
425 assert(range
->baseArrayLayer
+ tu_get_layerCount(image
, range
) <=
428 case VK_IMAGE_TYPE_3D
:
429 assert(range
->baseArrayLayer
+ tu_get_layerCount(image
, range
) <=
430 tu_minify(image
->extent
.depth
, range
->baseMipLevel
));
433 unreachable("bad VkImageType");
436 iview
->image
= image
;
438 memset(iview
->descriptor
, 0, sizeof(iview
->descriptor
));
440 struct fdl_layout
*layout
=
441 &image
->layout
[tu6_plane_index(image
->vk_format
, aspect_mask
)];
443 uint32_t width
= u_minify(layout
->width0
, range
->baseMipLevel
);
444 uint32_t height
= u_minify(layout
->height0
, range
->baseMipLevel
);
445 uint32_t storage_depth
= tu_get_layerCount(image
, range
);
446 if (pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_3D
) {
447 storage_depth
= u_minify(image
->extent
.depth
, range
->baseMipLevel
);
450 uint32_t depth
= storage_depth
;
451 if (pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_CUBE
||
452 pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_CUBE_ARRAY
) {
453 /* Cubes are treated as 2D arrays for storage images, so only divide the
454 * depth by 6 for the texture descriptor.
459 uint64_t base_addr
= image
->bo
->iova
+ image
->bo_offset
+
460 fdl_surface_offset(layout
, range
->baseMipLevel
, range
->baseArrayLayer
);
461 uint64_t ubwc_addr
= image
->bo
->iova
+ image
->bo_offset
+
462 fdl_ubwc_offset(layout
, range
->baseMipLevel
, range
->baseArrayLayer
);
464 uint32_t pitch
= fdl_pitch(layout
, range
->baseMipLevel
);
465 uint32_t ubwc_pitch
= fdl_ubwc_pitch(layout
, range
->baseMipLevel
);
466 uint32_t layer_size
= fdl_layer_stride(layout
, range
->baseMipLevel
);
468 if (aspect_mask
!= VK_IMAGE_ASPECT_COLOR_BIT
)
469 format
= tu6_plane_format(format
, tu6_plane_index(format
, aspect_mask
));
471 struct tu_native_format fmt
= tu6_format_texture(format
, layout
->tile_mode
);
472 /* note: freedreno layout assumes no TILE_ALL bit for non-UBWC
473 * this means smaller mipmap levels have a linear tile mode
475 fmt
.tile_mode
= fdl_tile_mode(layout
, range
->baseMipLevel
);
477 bool ubwc_enabled
= fdl_ubwc_enabled(layout
, range
->baseMipLevel
);
479 bool is_d24s8
= (format
== VK_FORMAT_D24_UNORM_S8_UINT
||
480 format
== VK_FORMAT_X8_D24_UNORM_PACK32
);
482 if (is_d24s8
&& ubwc_enabled
)
483 fmt
.fmt
= FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8
;
485 unsigned fmt_tex
= fmt
.fmt
;
487 if (aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
)
488 fmt_tex
= FMT6_Z24_UNORM_S8_UINT
;
489 if (aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
)
490 fmt_tex
= limited_z24s8
? FMT6_8_8_8_8_UINT
: FMT6_Z24_UINT_S8_UINT
;
491 /* TODO: also use this format with storage descriptor ? */
494 iview
->descriptor
[0] =
495 A6XX_TEX_CONST_0_TILE_MODE(fmt
.tile_mode
) |
496 COND(vk_format_is_srgb(format
), A6XX_TEX_CONST_0_SRGB
) |
497 A6XX_TEX_CONST_0_FMT(fmt_tex
) |
498 A6XX_TEX_CONST_0_SAMPLES(tu_msaa_samples(image
->samples
)) |
499 A6XX_TEX_CONST_0_SWAP(fmt
.swap
) |
500 tu6_texswiz(&pCreateInfo
->components
, conversion
, format
, aspect_mask
, limited_z24s8
) |
501 A6XX_TEX_CONST_0_MIPLVLS(tu_get_levelCount(image
, range
) - 1);
502 iview
->descriptor
[1] = A6XX_TEX_CONST_1_WIDTH(width
) | A6XX_TEX_CONST_1_HEIGHT(height
);
503 iview
->descriptor
[2] =
504 A6XX_TEX_CONST_2_PITCHALIGN(layout
->pitchalign
- 6) |
505 A6XX_TEX_CONST_2_PITCH(pitch
) |
506 A6XX_TEX_CONST_2_TYPE(tu6_tex_type(pCreateInfo
->viewType
, false));
507 iview
->descriptor
[3] = A6XX_TEX_CONST_3_ARRAY_PITCH(layer_size
);
508 iview
->descriptor
[4] = base_addr
;
509 iview
->descriptor
[5] = (base_addr
>> 32) | A6XX_TEX_CONST_5_DEPTH(depth
);
511 if (format
== VK_FORMAT_G8_B8R8_2PLANE_420_UNORM
||
512 format
== VK_FORMAT_G8_B8_R8_3PLANE_420_UNORM
) {
513 /* chroma offset re-uses MIPLVLS bits */
514 assert(tu_get_levelCount(image
, range
) == 1);
516 if (conversion
->chroma_offsets
[0] == VK_CHROMA_LOCATION_MIDPOINT
)
517 iview
->descriptor
[0] |= A6XX_TEX_CONST_0_CHROMA_MIDPOINT_X
;
518 if (conversion
->chroma_offsets
[1] == VK_CHROMA_LOCATION_MIDPOINT
)
519 iview
->descriptor
[0] |= A6XX_TEX_CONST_0_CHROMA_MIDPOINT_Y
;
522 uint64_t base_addr
[3];
524 iview
->descriptor
[3] |= A6XX_TEX_CONST_3_TILE_ALL
;
526 iview
->descriptor
[3] |= A6XX_TEX_CONST_3_FLAG
;
527 /* no separate ubwc base, image must have the expected layout */
528 for (uint32_t i
= 0; i
< 3; i
++) {
529 base_addr
[i
] = image
->bo
->iova
+ image
->bo_offset
+
530 fdl_ubwc_offset(&image
->layout
[i
], range
->baseMipLevel
, range
->baseArrayLayer
);
533 for (uint32_t i
= 0; i
< 3; i
++) {
534 base_addr
[i
] = image
->bo
->iova
+ image
->bo_offset
+
535 fdl_surface_offset(&image
->layout
[i
], range
->baseMipLevel
, range
->baseArrayLayer
);
539 iview
->descriptor
[4] = base_addr
[0];
540 iview
->descriptor
[5] |= base_addr
[0] >> 32;
541 iview
->descriptor
[6] =
542 A6XX_TEX_CONST_6_PLANE_PITCH(fdl_pitch(&image
->layout
[1], range
->baseMipLevel
));
543 iview
->descriptor
[7] = base_addr
[1];
544 iview
->descriptor
[8] = base_addr
[1] >> 32;
545 iview
->descriptor
[9] = base_addr
[2];
546 iview
->descriptor
[10] = base_addr
[2] >> 32;
548 assert(pCreateInfo
->viewType
!= VK_IMAGE_VIEW_TYPE_3D
);
549 assert(!(image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
));
554 uint32_t block_width
, block_height
;
555 fdl6_get_ubwc_blockwidth(layout
, &block_width
, &block_height
);
557 iview
->descriptor
[3] |= A6XX_TEX_CONST_3_FLAG
| A6XX_TEX_CONST_3_TILE_ALL
;
558 iview
->descriptor
[7] = ubwc_addr
;
559 iview
->descriptor
[8] = ubwc_addr
>> 32;
560 iview
->descriptor
[9] |= A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(layout
->ubwc_layer_size
>> 2);
561 iview
->descriptor
[10] |=
562 A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(ubwc_pitch
) |
563 A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW(util_logbase2_ceil(DIV_ROUND_UP(width
, block_width
))) |
564 A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH(util_logbase2_ceil(DIV_ROUND_UP(height
, block_height
)));
567 if (pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_3D
) {
568 iview
->descriptor
[3] |=
569 A6XX_TEX_CONST_3_MIN_LAYERSZ(layout
->slices
[image
->level_count
- 1].size0
);
572 iview
->SP_PS_2D_SRC_INFO
= A6XX_SP_PS_2D_SRC_INFO(
573 .color_format
= fmt
.fmt
,
574 .tile_mode
= fmt
.tile_mode
,
575 .color_swap
= fmt
.swap
,
576 .flags
= ubwc_enabled
,
577 .srgb
= vk_format_is_srgb(format
),
578 .samples
= tu_msaa_samples(image
->samples
),
579 .samples_average
= image
->samples
> 1 &&
580 !vk_format_is_int(format
) &&
581 !vk_format_is_depth_or_stencil(format
),
584 iview
->SP_PS_2D_SRC_SIZE
=
585 A6XX_SP_PS_2D_SRC_SIZE(.width
= width
, .height
= height
).value
;
587 /* note: these have same encoding for MRT and 2D (except 2D PITCH src) */
588 iview
->PITCH
= A6XX_RB_DEPTH_BUFFER_PITCH(pitch
).value
;
589 iview
->FLAG_BUFFER_PITCH
= A6XX_RB_DEPTH_FLAG_BUFFER_PITCH(
590 .pitch
= ubwc_pitch
, .array_pitch
= layout
->ubwc_layer_size
>> 2).value
;
592 iview
->base_addr
= base_addr
;
593 iview
->ubwc_addr
= ubwc_addr
;
594 iview
->layer_size
= layer_size
;
595 iview
->ubwc_layer_size
= layout
->ubwc_layer_size
;
597 /* Don't set fields that are only used for attachments/blit dest if COLOR
600 if (!(fmt
.supported
& FMT_COLOR
))
603 struct tu_native_format cfmt
= tu6_format_color(format
, layout
->tile_mode
);
604 cfmt
.tile_mode
= fmt
.tile_mode
;
606 if (is_d24s8
&& ubwc_enabled
)
607 cfmt
.fmt
= FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8
;
609 if (image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
) {
610 memset(iview
->storage_descriptor
, 0, sizeof(iview
->storage_descriptor
));
612 iview
->storage_descriptor
[0] =
613 A6XX_IBO_0_FMT(fmt
.fmt
) |
614 A6XX_IBO_0_TILE_MODE(fmt
.tile_mode
);
615 iview
->storage_descriptor
[1] =
616 A6XX_IBO_1_WIDTH(width
) |
617 A6XX_IBO_1_HEIGHT(height
);
618 iview
->storage_descriptor
[2] =
619 A6XX_IBO_2_PITCH(pitch
) |
620 A6XX_IBO_2_TYPE(tu6_tex_type(pCreateInfo
->viewType
, true));
621 iview
->storage_descriptor
[3] = A6XX_IBO_3_ARRAY_PITCH(layer_size
);
623 iview
->storage_descriptor
[4] = base_addr
;
624 iview
->storage_descriptor
[5] = (base_addr
>> 32) | A6XX_IBO_5_DEPTH(storage_depth
);
627 iview
->storage_descriptor
[3] |= A6XX_IBO_3_FLAG
| A6XX_IBO_3_UNK27
;
628 iview
->storage_descriptor
[7] |= ubwc_addr
;
629 iview
->storage_descriptor
[8] |= ubwc_addr
>> 32;
630 iview
->storage_descriptor
[9] = A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH(layout
->ubwc_layer_size
>> 2);
631 iview
->storage_descriptor
[10] =
632 A6XX_IBO_10_FLAG_BUFFER_PITCH(ubwc_pitch
);
636 iview
->extent
.width
= width
;
637 iview
->extent
.height
= height
;
638 iview
->need_y2_align
=
639 (fmt
.tile_mode
== TILE6_LINEAR
&& range
->baseMipLevel
!= image
->level_count
- 1);
641 iview
->ubwc_enabled
= ubwc_enabled
;
643 iview
->RB_MRT_BUF_INFO
= A6XX_RB_MRT_BUF_INFO(0,
644 .color_tile_mode
= cfmt
.tile_mode
,
645 .color_format
= cfmt
.fmt
,
646 .color_swap
= cfmt
.swap
).value
;
648 iview
->SP_FS_MRT_REG
= A6XX_SP_FS_MRT_REG(0,
649 .color_format
= cfmt
.fmt
,
650 .color_sint
= vk_format_is_sint(format
),
651 .color_uint
= vk_format_is_uint(format
)).value
;
653 iview
->RB_2D_DST_INFO
= A6XX_RB_2D_DST_INFO(
654 .color_format
= cfmt
.fmt
,
655 .tile_mode
= cfmt
.tile_mode
,
656 .color_swap
= cfmt
.swap
,
657 .flags
= ubwc_enabled
,
658 .srgb
= vk_format_is_srgb(format
)).value
;
660 iview
->RB_BLIT_DST_INFO
= A6XX_RB_BLIT_DST_INFO(
661 .tile_mode
= cfmt
.tile_mode
,
662 .samples
= tu_msaa_samples(iview
->image
->samples
),
663 .color_format
= cfmt
.fmt
,
664 .color_swap
= cfmt
.swap
,
665 .flags
= ubwc_enabled
).value
;
667 if (image
->vk_format
== VK_FORMAT_D32_SFLOAT_S8_UINT
) {
668 layout
= &image
->layout
[1];
669 iview
->stencil_base_addr
= image
->bo
->iova
+ image
->bo_offset
+
670 fdl_surface_offset(layout
, range
->baseMipLevel
, range
->baseArrayLayer
);
671 iview
->stencil_layer_size
= fdl_layer_stride(layout
, range
->baseMipLevel
);
672 iview
->stencil_PITCH
= A6XX_RB_STENCIL_BUFFER_PITCH(fdl_pitch(layout
, range
->baseMipLevel
)).value
;
677 tu_CreateImage(VkDevice device
,
678 const VkImageCreateInfo
*pCreateInfo
,
679 const VkAllocationCallbacks
*pAllocator
,
683 const VkNativeBufferANDROID
*gralloc_info
=
684 vk_find_struct_const(pCreateInfo
->pNext
, NATIVE_BUFFER_ANDROID
);
687 return tu_image_from_gralloc(device
, pCreateInfo
, gralloc_info
,
691 uint64_t modifier
= DRM_FORMAT_MOD_INVALID
;
692 const VkSubresourceLayout
*plane_layouts
= NULL
;
694 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT
) {
695 const VkImageDrmFormatModifierListCreateInfoEXT
*mod_info
=
696 vk_find_struct_const(pCreateInfo
->pNext
,
697 IMAGE_DRM_FORMAT_MODIFIER_LIST_CREATE_INFO_EXT
);
698 const VkImageDrmFormatModifierExplicitCreateInfoEXT
*drm_explicit_info
=
699 vk_find_struct_const(pCreateInfo
->pNext
,
700 IMAGE_DRM_FORMAT_MODIFIER_EXPLICIT_CREATE_INFO_EXT
);
702 assert(mod_info
|| drm_explicit_info
);
705 modifier
= DRM_FORMAT_MOD_LINEAR
;
706 for (unsigned i
= 0; i
< mod_info
->drmFormatModifierCount
; i
++) {
707 if (mod_info
->pDrmFormatModifiers
[i
] == DRM_FORMAT_MOD_QCOM_COMPRESSED
)
708 modifier
= DRM_FORMAT_MOD_QCOM_COMPRESSED
;
711 modifier
= drm_explicit_info
->drmFormatModifier
;
712 assert(modifier
== DRM_FORMAT_MOD_LINEAR
||
713 modifier
== DRM_FORMAT_MOD_QCOM_COMPRESSED
);
714 plane_layouts
= drm_explicit_info
->pPlaneLayouts
;
717 const struct wsi_image_create_info
*wsi_info
=
718 vk_find_struct_const(pCreateInfo
->pNext
, WSI_IMAGE_CREATE_INFO_MESA
);
719 if (wsi_info
&& wsi_info
->scanout
)
720 modifier
= DRM_FORMAT_MOD_LINEAR
;
723 return tu_image_create(device
, pCreateInfo
, pAllocator
, pImage
, modifier
, plane_layouts
);
727 tu_DestroyImage(VkDevice _device
,
729 const VkAllocationCallbacks
*pAllocator
)
731 TU_FROM_HANDLE(tu_device
, device
, _device
);
732 TU_FROM_HANDLE(tu_image
, image
, _image
);
737 if (image
->owned_memory
!= VK_NULL_HANDLE
)
738 tu_FreeMemory(_device
, image
->owned_memory
, pAllocator
);
740 vk_object_free(&device
->vk
, pAllocator
, image
);
744 tu_GetImageSubresourceLayout(VkDevice _device
,
746 const VkImageSubresource
*pSubresource
,
747 VkSubresourceLayout
*pLayout
)
749 TU_FROM_HANDLE(tu_image
, image
, _image
);
751 struct fdl_layout
*layout
=
752 &image
->layout
[tu6_plane_index(image
->vk_format
, pSubresource
->aspectMask
)];
753 const struct fdl_slice
*slice
= layout
->slices
+ pSubresource
->mipLevel
;
756 fdl_surface_offset(layout
, pSubresource
->mipLevel
, pSubresource
->arrayLayer
);
757 pLayout
->size
= slice
->size0
;
758 pLayout
->rowPitch
= fdl_pitch(layout
, pSubresource
->mipLevel
);
759 pLayout
->arrayPitch
= fdl_layer_stride(layout
, pSubresource
->mipLevel
);
760 pLayout
->depthPitch
= slice
->size0
;
762 if (fdl_ubwc_enabled(layout
, pSubresource
->mipLevel
)) {
763 /* UBWC starts at offset 0 */
765 /* UBWC scanout won't match what the kernel wants if we have levels/layers */
766 assert(image
->level_count
== 1 && image
->layer_count
== 1);
770 VkResult
tu_GetImageDrmFormatModifierPropertiesEXT(
773 VkImageDrmFormatModifierPropertiesEXT
* pProperties
)
775 TU_FROM_HANDLE(tu_image
, image
, _image
);
777 assert(pProperties
->sType
==
778 VK_STRUCTURE_TYPE_IMAGE_DRM_FORMAT_MODIFIER_PROPERTIES_EXT
);
780 /* TODO invent a modifier for tiled but not UBWC buffers */
782 if (!image
->layout
[0].tile_mode
)
783 pProperties
->drmFormatModifier
= DRM_FORMAT_MOD_LINEAR
;
784 else if (image
->layout
[0].ubwc_layer_size
)
785 pProperties
->drmFormatModifier
= DRM_FORMAT_MOD_QCOM_COMPRESSED
;
787 pProperties
->drmFormatModifier
= DRM_FORMAT_MOD_INVALID
;
794 tu_CreateImageView(VkDevice _device
,
795 const VkImageViewCreateInfo
*pCreateInfo
,
796 const VkAllocationCallbacks
*pAllocator
,
799 TU_FROM_HANDLE(tu_device
, device
, _device
);
800 struct tu_image_view
*view
;
802 view
= vk_object_alloc(&device
->vk
, pAllocator
, sizeof(*view
),
803 VK_OBJECT_TYPE_IMAGE_VIEW
);
805 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
807 tu_image_view_init(view
, pCreateInfo
, device
->physical_device
->limited_z24s8
);
809 *pView
= tu_image_view_to_handle(view
);
815 tu_DestroyImageView(VkDevice _device
,
817 const VkAllocationCallbacks
*pAllocator
)
819 TU_FROM_HANDLE(tu_device
, device
, _device
);
820 TU_FROM_HANDLE(tu_image_view
, iview
, _iview
);
825 vk_object_free(&device
->vk
, pAllocator
, iview
);
829 tu_buffer_view_init(struct tu_buffer_view
*view
,
830 struct tu_device
*device
,
831 const VkBufferViewCreateInfo
*pCreateInfo
)
833 TU_FROM_HANDLE(tu_buffer
, buffer
, pCreateInfo
->buffer
);
835 view
->buffer
= buffer
;
837 enum VkFormat vfmt
= pCreateInfo
->format
;
838 enum pipe_format pfmt
= vk_format_to_pipe_format(vfmt
);
839 const struct tu_native_format fmt
= tu6_format_texture(vfmt
, TILE6_LINEAR
);
842 if (pCreateInfo
->range
== VK_WHOLE_SIZE
)
843 range
= buffer
->size
- pCreateInfo
->offset
;
845 range
= pCreateInfo
->range
;
846 uint32_t elements
= range
/ util_format_get_blocksize(pfmt
);
848 static const VkComponentMapping components
= {
849 .r
= VK_COMPONENT_SWIZZLE_R
,
850 .g
= VK_COMPONENT_SWIZZLE_G
,
851 .b
= VK_COMPONENT_SWIZZLE_B
,
852 .a
= VK_COMPONENT_SWIZZLE_A
,
855 uint64_t iova
= tu_buffer_iova(buffer
) + pCreateInfo
->offset
;
857 memset(&view
->descriptor
, 0, sizeof(view
->descriptor
));
859 view
->descriptor
[0] =
860 A6XX_TEX_CONST_0_TILE_MODE(TILE6_LINEAR
) |
861 A6XX_TEX_CONST_0_SWAP(fmt
.swap
) |
862 A6XX_TEX_CONST_0_FMT(fmt
.fmt
) |
863 A6XX_TEX_CONST_0_MIPLVLS(0) |
864 tu6_texswiz(&components
, NULL
, vfmt
, VK_IMAGE_ASPECT_COLOR_BIT
, false);
865 COND(vk_format_is_srgb(vfmt
), A6XX_TEX_CONST_0_SRGB
);
866 view
->descriptor
[1] =
867 A6XX_TEX_CONST_1_WIDTH(elements
& MASK(15)) |
868 A6XX_TEX_CONST_1_HEIGHT(elements
>> 15);
869 view
->descriptor
[2] =
870 A6XX_TEX_CONST_2_UNK4
|
871 A6XX_TEX_CONST_2_UNK31
;
872 view
->descriptor
[4] = iova
;
873 view
->descriptor
[5] = iova
>> 32;
877 tu_CreateBufferView(VkDevice _device
,
878 const VkBufferViewCreateInfo
*pCreateInfo
,
879 const VkAllocationCallbacks
*pAllocator
,
882 TU_FROM_HANDLE(tu_device
, device
, _device
);
883 struct tu_buffer_view
*view
;
885 view
= vk_object_alloc(&device
->vk
, pAllocator
, sizeof(*view
),
886 VK_OBJECT_TYPE_BUFFER_VIEW
);
888 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
890 tu_buffer_view_init(view
, device
, pCreateInfo
);
892 *pView
= tu_buffer_view_to_handle(view
);
898 tu_DestroyBufferView(VkDevice _device
,
899 VkBufferView bufferView
,
900 const VkAllocationCallbacks
*pAllocator
)
902 TU_FROM_HANDLE(tu_device
, device
, _device
);
903 TU_FROM_HANDLE(tu_buffer_view
, view
, bufferView
);
908 vk_object_free(&device
->vk
, pAllocator
, view
);