2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 #include "tu_private.h"
30 #include "main/menums.h"
32 #include "nir/nir_builder.h"
33 #include "spirv/nir_spirv.h"
34 #include "util/debug.h"
35 #include "util/mesa-sha1.h"
36 #include "util/u_atomic.h"
37 #include "vk_format.h"
42 struct tu_pipeline_builder
44 struct tu_device
*device
;
45 struct tu_pipeline_cache
*cache
;
46 struct tu_pipeline_layout
*layout
;
47 const VkAllocationCallbacks
*alloc
;
48 const VkGraphicsPipelineCreateInfo
*create_info
;
50 struct tu_shader
*shaders
[MESA_SHADER_STAGES
];
51 uint32_t shader_offsets
[MESA_SHADER_STAGES
];
52 uint32_t binning_vs_offset
;
53 uint32_t shader_total_size
;
55 bool rasterizer_discard
;
56 /* these states are affectd by rasterizer_discard */
57 VkSampleCountFlagBits samples
;
58 bool use_depth_stencil_attachment
;
59 bool use_color_attachments
;
60 uint32_t color_attachment_count
;
61 VkFormat color_attachment_formats
[MAX_RTS
];
64 static enum tu_dynamic_state_bits
65 tu_dynamic_state_bit(VkDynamicState state
)
68 case VK_DYNAMIC_STATE_VIEWPORT
:
69 return TU_DYNAMIC_VIEWPORT
;
70 case VK_DYNAMIC_STATE_SCISSOR
:
71 return TU_DYNAMIC_SCISSOR
;
72 case VK_DYNAMIC_STATE_LINE_WIDTH
:
73 return TU_DYNAMIC_LINE_WIDTH
;
74 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
75 return TU_DYNAMIC_DEPTH_BIAS
;
76 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
77 return TU_DYNAMIC_BLEND_CONSTANTS
;
78 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
79 return TU_DYNAMIC_DEPTH_BOUNDS
;
80 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
81 return TU_DYNAMIC_STENCIL_COMPARE_MASK
;
82 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
83 return TU_DYNAMIC_STENCIL_WRITE_MASK
;
84 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
85 return TU_DYNAMIC_STENCIL_REFERENCE
;
87 unreachable("invalid dynamic state");
92 static gl_shader_stage
93 tu_shader_stage(VkShaderStageFlagBits stage
)
96 case VK_SHADER_STAGE_VERTEX_BIT
:
97 return MESA_SHADER_VERTEX
;
98 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
99 return MESA_SHADER_TESS_CTRL
;
100 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
101 return MESA_SHADER_TESS_EVAL
;
102 case VK_SHADER_STAGE_GEOMETRY_BIT
:
103 return MESA_SHADER_GEOMETRY
;
104 case VK_SHADER_STAGE_FRAGMENT_BIT
:
105 return MESA_SHADER_FRAGMENT
;
106 case VK_SHADER_STAGE_COMPUTE_BIT
:
107 return MESA_SHADER_COMPUTE
;
109 unreachable("invalid VkShaderStageFlagBits");
110 return MESA_SHADER_NONE
;
114 static const VkVertexInputAttributeDescription
*
115 tu_find_vertex_input_attribute(
116 const VkPipelineVertexInputStateCreateInfo
*vi_info
, uint32_t slot
)
118 assert(slot
>= VERT_ATTRIB_GENERIC0
);
119 slot
-= VERT_ATTRIB_GENERIC0
;
120 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
121 if (vi_info
->pVertexAttributeDescriptions
[i
].location
== slot
)
122 return &vi_info
->pVertexAttributeDescriptions
[i
];
127 static const VkVertexInputBindingDescription
*
128 tu_find_vertex_input_binding(
129 const VkPipelineVertexInputStateCreateInfo
*vi_info
,
130 const VkVertexInputAttributeDescription
*vi_attr
)
133 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
134 if (vi_info
->pVertexBindingDescriptions
[i
].binding
== vi_attr
->binding
)
135 return &vi_info
->pVertexBindingDescriptions
[i
];
141 tu_logic_op_reads_dst(VkLogicOp op
)
144 case VK_LOGIC_OP_CLEAR
:
145 case VK_LOGIC_OP_COPY
:
146 case VK_LOGIC_OP_COPY_INVERTED
:
147 case VK_LOGIC_OP_SET
:
155 tu_blend_factor_no_dst_alpha(VkBlendFactor factor
)
157 /* treat dst alpha as 1.0 and avoid reading it */
159 case VK_BLEND_FACTOR_DST_ALPHA
:
160 return VK_BLEND_FACTOR_ONE
;
161 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
162 return VK_BLEND_FACTOR_ZERO
;
168 static enum pc_di_primtype
169 tu6_primtype(VkPrimitiveTopology topology
)
172 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
173 return DI_PT_POINTLIST
;
174 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
175 return DI_PT_LINELIST
;
176 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
177 return DI_PT_LINESTRIP
;
178 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
179 return DI_PT_TRILIST
;
180 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
181 return DI_PT_TRISTRIP
;
182 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
184 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
185 return DI_PT_LINE_ADJ
;
186 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
187 return DI_PT_LINESTRIP_ADJ
;
188 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
189 return DI_PT_TRI_ADJ
;
190 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
191 return DI_PT_TRISTRIP_ADJ
;
192 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
194 unreachable("invalid primitive topology");
199 static enum adreno_compare_func
200 tu6_compare_func(VkCompareOp op
)
203 case VK_COMPARE_OP_NEVER
:
205 case VK_COMPARE_OP_LESS
:
207 case VK_COMPARE_OP_EQUAL
:
209 case VK_COMPARE_OP_LESS_OR_EQUAL
:
211 case VK_COMPARE_OP_GREATER
:
213 case VK_COMPARE_OP_NOT_EQUAL
:
214 return FUNC_NOTEQUAL
;
215 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
217 case VK_COMPARE_OP_ALWAYS
:
220 unreachable("invalid VkCompareOp");
225 static enum adreno_stencil_op
226 tu6_stencil_op(VkStencilOp op
)
229 case VK_STENCIL_OP_KEEP
:
231 case VK_STENCIL_OP_ZERO
:
233 case VK_STENCIL_OP_REPLACE
:
234 return STENCIL_REPLACE
;
235 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
236 return STENCIL_INCR_CLAMP
;
237 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
238 return STENCIL_DECR_CLAMP
;
239 case VK_STENCIL_OP_INVERT
:
240 return STENCIL_INVERT
;
241 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
242 return STENCIL_INCR_WRAP
;
243 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
244 return STENCIL_DECR_WRAP
;
246 unreachable("invalid VkStencilOp");
251 static enum a3xx_rop_code
252 tu6_rop(VkLogicOp op
)
255 case VK_LOGIC_OP_CLEAR
:
257 case VK_LOGIC_OP_AND
:
259 case VK_LOGIC_OP_AND_REVERSE
:
260 return ROP_AND_REVERSE
;
261 case VK_LOGIC_OP_COPY
:
263 case VK_LOGIC_OP_AND_INVERTED
:
264 return ROP_AND_INVERTED
;
265 case VK_LOGIC_OP_NO_OP
:
267 case VK_LOGIC_OP_XOR
:
271 case VK_LOGIC_OP_NOR
:
273 case VK_LOGIC_OP_EQUIVALENT
:
275 case VK_LOGIC_OP_INVERT
:
277 case VK_LOGIC_OP_OR_REVERSE
:
278 return ROP_OR_REVERSE
;
279 case VK_LOGIC_OP_COPY_INVERTED
:
280 return ROP_COPY_INVERTED
;
281 case VK_LOGIC_OP_OR_INVERTED
:
282 return ROP_OR_INVERTED
;
283 case VK_LOGIC_OP_NAND
:
285 case VK_LOGIC_OP_SET
:
288 unreachable("invalid VkLogicOp");
293 static enum adreno_rb_blend_factor
294 tu6_blend_factor(VkBlendFactor factor
)
297 case VK_BLEND_FACTOR_ZERO
:
299 case VK_BLEND_FACTOR_ONE
:
301 case VK_BLEND_FACTOR_SRC_COLOR
:
302 return FACTOR_SRC_COLOR
;
303 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
304 return FACTOR_ONE_MINUS_SRC_COLOR
;
305 case VK_BLEND_FACTOR_DST_COLOR
:
306 return FACTOR_DST_COLOR
;
307 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
308 return FACTOR_ONE_MINUS_DST_COLOR
;
309 case VK_BLEND_FACTOR_SRC_ALPHA
:
310 return FACTOR_SRC_ALPHA
;
311 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
312 return FACTOR_ONE_MINUS_SRC_ALPHA
;
313 case VK_BLEND_FACTOR_DST_ALPHA
:
314 return FACTOR_DST_ALPHA
;
315 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
316 return FACTOR_ONE_MINUS_DST_ALPHA
;
317 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
318 return FACTOR_CONSTANT_COLOR
;
319 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
320 return FACTOR_ONE_MINUS_CONSTANT_COLOR
;
321 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
322 return FACTOR_CONSTANT_ALPHA
;
323 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
324 return FACTOR_ONE_MINUS_CONSTANT_ALPHA
;
325 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
326 return FACTOR_SRC_ALPHA_SATURATE
;
327 case VK_BLEND_FACTOR_SRC1_COLOR
:
328 return FACTOR_SRC1_COLOR
;
329 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
330 return FACTOR_ONE_MINUS_SRC1_COLOR
;
331 case VK_BLEND_FACTOR_SRC1_ALPHA
:
332 return FACTOR_SRC1_ALPHA
;
333 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
334 return FACTOR_ONE_MINUS_SRC1_ALPHA
;
336 unreachable("invalid VkBlendFactor");
341 static enum a3xx_rb_blend_opcode
342 tu6_blend_op(VkBlendOp op
)
345 case VK_BLEND_OP_ADD
:
346 return BLEND_DST_PLUS_SRC
;
347 case VK_BLEND_OP_SUBTRACT
:
348 return BLEND_SRC_MINUS_DST
;
349 case VK_BLEND_OP_REVERSE_SUBTRACT
:
350 return BLEND_DST_MINUS_SRC
;
351 case VK_BLEND_OP_MIN
:
352 return BLEND_MIN_DST_SRC
;
353 case VK_BLEND_OP_MAX
:
354 return BLEND_MAX_DST_SRC
;
356 unreachable("invalid VkBlendOp");
357 return BLEND_DST_PLUS_SRC
;
362 tu6_emit_vs_config(struct tu_cs
*cs
, struct tu_shader
*shader
,
363 const struct ir3_shader_variant
*vs
)
365 uint32_t sp_vs_ctrl
=
366 A6XX_SP_VS_CTRL_REG0_THREADSIZE(FOUR_QUADS
) |
367 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs
->info
.max_reg
+ 1) |
368 A6XX_SP_VS_CTRL_REG0_MERGEDREGS
|
369 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs
->branchstack
);
371 sp_vs_ctrl
|= A6XX_SP_VS_CTRL_REG0_PIXLODENABLE
;
373 uint32_t sp_vs_config
= A6XX_SP_VS_CONFIG_NTEX(shader
->texture_map
.num_desc
) |
374 A6XX_SP_VS_CONFIG_NSAMP(shader
->sampler_map
.num_desc
);
376 sp_vs_config
|= A6XX_SP_VS_CONFIG_ENABLED
;
378 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_VS_CTRL_REG0
, 1);
379 tu_cs_emit(cs
, sp_vs_ctrl
);
381 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_VS_CONFIG
, 2);
382 tu_cs_emit(cs
, sp_vs_config
);
383 tu_cs_emit(cs
, vs
->instrlen
);
385 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_VS_CNTL
, 1);
386 tu_cs_emit(cs
, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(vs
->constlen
, 4)) |
387 A6XX_HLSQ_VS_CNTL_ENABLED
);
391 tu6_emit_hs_config(struct tu_cs
*cs
, struct tu_shader
*shader
,
392 const struct ir3_shader_variant
*hs
)
394 uint32_t sp_hs_config
= 0;
396 sp_hs_config
|= A6XX_SP_HS_CONFIG_ENABLED
;
398 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_HS_UNKNOWN_A831
, 1);
401 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_HS_CONFIG
, 2);
402 tu_cs_emit(cs
, sp_hs_config
);
403 tu_cs_emit(cs
, hs
->instrlen
);
405 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_HS_CNTL
, 1);
406 tu_cs_emit(cs
, A6XX_HLSQ_HS_CNTL_CONSTLEN(align(hs
->constlen
, 4)));
410 tu6_emit_ds_config(struct tu_cs
*cs
, struct tu_shader
*shader
,
411 const struct ir3_shader_variant
*ds
)
413 uint32_t sp_ds_config
= 0;
415 sp_ds_config
|= A6XX_SP_DS_CONFIG_ENABLED
;
417 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_DS_CONFIG
, 2);
418 tu_cs_emit(cs
, sp_ds_config
);
419 tu_cs_emit(cs
, ds
->instrlen
);
421 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_DS_CNTL
, 1);
422 tu_cs_emit(cs
, A6XX_HLSQ_DS_CNTL_CONSTLEN(align(ds
->constlen
, 4)));
426 tu6_emit_gs_config(struct tu_cs
*cs
, struct tu_shader
*shader
,
427 const struct ir3_shader_variant
*gs
)
429 uint32_t sp_gs_config
= 0;
431 sp_gs_config
|= A6XX_SP_GS_CONFIG_ENABLED
;
433 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_UNKNOWN_A871
, 1);
436 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_CONFIG
, 2);
437 tu_cs_emit(cs
, sp_gs_config
);
438 tu_cs_emit(cs
, gs
->instrlen
);
440 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_GS_CNTL
, 1);
441 tu_cs_emit(cs
, A6XX_HLSQ_GS_CNTL_CONSTLEN(align(gs
->constlen
, 4)));
445 tu6_emit_fs_config(struct tu_cs
*cs
, struct tu_shader
*shader
,
446 const struct ir3_shader_variant
*fs
)
448 uint32_t sp_fs_ctrl
=
449 A6XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS
) | 0x1000000 |
450 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs
->info
.max_reg
+ 1) |
451 A6XX_SP_FS_CTRL_REG0_MERGEDREGS
|
452 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs
->branchstack
);
453 if (fs
->total_in
> 0)
454 sp_fs_ctrl
|= A6XX_SP_FS_CTRL_REG0_VARYING
;
456 sp_fs_ctrl
|= A6XX_SP_FS_CTRL_REG0_PIXLODENABLE
;
458 uint32_t sp_fs_config
= A6XX_SP_FS_CONFIG_NTEX(shader
->texture_map
.num_desc
) |
459 A6XX_SP_FS_CONFIG_NSAMP(shader
->sampler_map
.num_desc
) |
460 A6XX_SP_FS_CONFIG_NIBO(fs
->image_mapping
.num_ibo
);
462 sp_fs_config
|= A6XX_SP_FS_CONFIG_ENABLED
;
464 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_UNKNOWN_A9A8
, 1);
467 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_UNKNOWN_AB00
, 1);
470 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_CTRL_REG0
, 1);
471 tu_cs_emit(cs
, sp_fs_ctrl
);
473 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_CONFIG
, 2);
474 tu_cs_emit(cs
, sp_fs_config
);
475 tu_cs_emit(cs
, fs
->instrlen
);
477 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_FS_CNTL
, 1);
478 tu_cs_emit(cs
, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(fs
->constlen
, 4)) |
479 A6XX_HLSQ_FS_CNTL_ENABLED
);
481 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_IBO_COUNT
, 1);
482 tu_cs_emit(cs
, fs
->image_mapping
.num_ibo
);
486 tu6_emit_cs_config(struct tu_cs
*cs
, const struct tu_shader
*shader
,
487 const struct ir3_shader_variant
*v
)
489 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_UPDATE_CNTL
, 1);
490 tu_cs_emit(cs
, 0xff);
492 unsigned constlen
= align(v
->constlen
, 4);
493 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_CS_CNTL
, 1);
494 tu_cs_emit(cs
, A6XX_HLSQ_CS_CNTL_CONSTLEN(constlen
) |
495 A6XX_HLSQ_CS_CNTL_ENABLED
);
497 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_CS_CONFIG
, 2);
498 tu_cs_emit(cs
, A6XX_SP_CS_CONFIG_ENABLED
|
499 A6XX_SP_CS_CONFIG_NIBO(v
->image_mapping
.num_ibo
) |
500 A6XX_SP_CS_CONFIG_NTEX(shader
->texture_map
.num_desc
) |
501 A6XX_SP_CS_CONFIG_NSAMP(shader
->sampler_map
.num_desc
));
502 tu_cs_emit(cs
, v
->instrlen
);
504 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_CS_CTRL_REG0
, 1);
505 tu_cs_emit(cs
, A6XX_SP_CS_CTRL_REG0_THREADSIZE(FOUR_QUADS
) |
506 A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(v
->info
.max_reg
+ 1) |
507 A6XX_SP_CS_CTRL_REG0_MERGEDREGS
|
508 A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(v
->branchstack
) |
509 COND(v
->need_pixlod
, A6XX_SP_CS_CTRL_REG0_PIXLODENABLE
));
511 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_CS_UNKNOWN_A9B1
, 1);
512 tu_cs_emit(cs
, 0x41);
514 uint32_t local_invocation_id
=
515 ir3_find_sysval_regid(v
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
);
516 uint32_t work_group_id
=
517 ir3_find_sysval_regid(v
, SYSTEM_VALUE_WORK_GROUP_ID
);
519 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_CS_CNTL_0
, 2);
521 A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id
) |
522 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
523 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
524 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id
));
525 tu_cs_emit(cs
, 0x2fc); /* HLSQ_CS_UNKNOWN_B998 */
527 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_CS_IBO_COUNT
, 1);
528 tu_cs_emit(cs
, v
->image_mapping
.num_ibo
);
532 tu6_emit_vs_system_values(struct tu_cs
*cs
,
533 const struct ir3_shader_variant
*vs
)
535 const uint32_t vertexid_regid
=
536 ir3_find_sysval_regid(vs
, SYSTEM_VALUE_VERTEX_ID
);
537 const uint32_t instanceid_regid
=
538 ir3_find_sysval_regid(vs
, SYSTEM_VALUE_INSTANCE_ID
);
540 tu_cs_emit_pkt4(cs
, REG_A6XX_VFD_CONTROL_1
, 6);
541 tu_cs_emit(cs
, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid
) |
542 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid
) |
544 tu_cs_emit(cs
, 0x0000fcfc); /* VFD_CONTROL_2 */
545 tu_cs_emit(cs
, 0xfcfcfcfc); /* VFD_CONTROL_3 */
546 tu_cs_emit(cs
, 0x000000fc); /* VFD_CONTROL_4 */
547 tu_cs_emit(cs
, 0x0000fcfc); /* VFD_CONTROL_5 */
548 tu_cs_emit(cs
, 0x00000000); /* VFD_CONTROL_6 */
552 tu6_emit_vpc(struct tu_cs
*cs
,
553 const struct ir3_shader_variant
*vs
,
554 const struct ir3_shader_variant
*fs
,
557 struct ir3_shader_linkage linkage
= { 0 };
558 ir3_link_shaders(&linkage
, vs
, fs
);
560 if (vs
->shader
->stream_output
.num_outputs
&& !binning_pass
)
561 tu_finishme("stream output");
563 BITSET_DECLARE(vpc_var_enables
, 128) = { 0 };
564 for (uint32_t i
= 0; i
< linkage
.cnt
; i
++) {
565 const uint32_t comp_count
= util_last_bit(linkage
.var
[i
].compmask
);
566 for (uint32_t j
= 0; j
< comp_count
; j
++)
567 BITSET_SET(vpc_var_enables
, linkage
.var
[i
].loc
+ j
);
570 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_VAR_DISABLE(0), 4);
571 tu_cs_emit(cs
, ~vpc_var_enables
[0]);
572 tu_cs_emit(cs
, ~vpc_var_enables
[1]);
573 tu_cs_emit(cs
, ~vpc_var_enables
[2]);
574 tu_cs_emit(cs
, ~vpc_var_enables
[3]);
576 /* a6xx finds position/pointsize at the end */
577 const uint32_t position_regid
=
578 ir3_find_output_regid(vs
, VARYING_SLOT_POS
);
579 const uint32_t pointsize_regid
=
580 ir3_find_output_regid(vs
, VARYING_SLOT_PSIZ
);
581 uint32_t pointsize_loc
= 0xff, position_loc
= 0xff;
582 if (position_regid
!= regid(63, 0)) {
583 position_loc
= linkage
.max_loc
;
584 ir3_link_add(&linkage
, position_regid
, 0xf, linkage
.max_loc
);
586 if (pointsize_regid
!= regid(63, 0)) {
587 pointsize_loc
= linkage
.max_loc
;
588 ir3_link_add(&linkage
, pointsize_regid
, 0x1, linkage
.max_loc
);
591 /* map vs outputs to VPC */
592 assert(linkage
.cnt
<= 32);
593 const uint32_t sp_vs_out_count
= (linkage
.cnt
+ 1) / 2;
594 const uint32_t sp_vs_vpc_dst_count
= (linkage
.cnt
+ 3) / 4;
595 uint32_t sp_vs_out
[16];
596 uint32_t sp_vs_vpc_dst
[8];
597 sp_vs_out
[sp_vs_out_count
- 1] = 0;
598 sp_vs_vpc_dst
[sp_vs_vpc_dst_count
- 1] = 0;
599 for (uint32_t i
= 0; i
< linkage
.cnt
; i
++) {
600 ((uint16_t *) sp_vs_out
)[i
] =
601 A6XX_SP_VS_OUT_REG_A_REGID(linkage
.var
[i
].regid
) |
602 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage
.var
[i
].compmask
);
603 ((uint8_t *) sp_vs_vpc_dst
)[i
] =
604 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage
.var
[i
].loc
);
607 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_VS_OUT_REG(0), sp_vs_out_count
);
608 tu_cs_emit_array(cs
, sp_vs_out
, sp_vs_out_count
);
610 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_VS_VPC_DST_REG(0), sp_vs_vpc_dst_count
);
611 tu_cs_emit_array(cs
, sp_vs_vpc_dst
, sp_vs_vpc_dst_count
);
613 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_CNTL_0
, 1);
614 tu_cs_emit(cs
, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs
->total_in
) |
615 (fs
->total_in
> 0 ? A6XX_VPC_CNTL_0_VARYING
: 0) |
618 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_PACK
, 1);
619 tu_cs_emit(cs
, A6XX_VPC_PACK_POSITIONLOC(position_loc
) |
620 A6XX_VPC_PACK_PSIZELOC(pointsize_loc
) |
621 A6XX_VPC_PACK_STRIDE_IN_VPC(linkage
.max_loc
));
623 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_GS_SIV_CNTL
, 1);
624 tu_cs_emit(cs
, 0x0000ffff); /* XXX */
626 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_PRIMITIVE_CNTL
, 1);
627 tu_cs_emit(cs
, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage
.cnt
));
629 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_1
, 1);
630 tu_cs_emit(cs
, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage
.max_loc
) |
631 (vs
->writes_psize
? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE
: 0));
635 tu6_vpc_varying_mode(const struct ir3_shader_variant
*fs
,
637 uint8_t *interp_mode
,
638 uint8_t *ps_repl_mode
)
652 PS_REPL_ONE_MINUS_T
= 3,
655 const uint32_t compmask
= fs
->inputs
[index
].compmask
;
657 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
658 * fourth component occupy three consecutive varying slots
663 if (fs
->inputs
[index
].slot
== VARYING_SLOT_PNTC
) {
664 if (compmask
& 0x1) {
665 *ps_repl_mode
|= PS_REPL_S
<< shift
;
668 if (compmask
& 0x2) {
669 *ps_repl_mode
|= PS_REPL_T
<< shift
;
672 if (compmask
& 0x4) {
673 *interp_mode
|= INTERP_ZERO
<< shift
;
676 if (compmask
& 0x8) {
677 *interp_mode
|= INTERP_ONE
<< 6;
680 } else if ((fs
->inputs
[index
].interpolate
== INTERP_MODE_FLAT
) ||
681 fs
->inputs
[index
].rasterflat
) {
682 for (int i
= 0; i
< 4; i
++) {
683 if (compmask
& (1 << i
)) {
684 *interp_mode
|= INTERP_FLAT
<< shift
;
694 tu6_emit_vpc_varying_modes(struct tu_cs
*cs
,
695 const struct ir3_shader_variant
*fs
,
698 uint32_t interp_modes
[8] = { 0 };
699 uint32_t ps_repl_modes
[8] = { 0 };
703 (i
= ir3_next_varying(fs
, i
)) < (int) fs
->inputs_count
;) {
705 /* get the mode for input i */
707 uint8_t ps_repl_mode
;
709 tu6_vpc_varying_mode(fs
, i
, &interp_mode
, &ps_repl_mode
);
711 /* OR the mode into the array */
712 const uint32_t inloc
= fs
->inputs
[i
].inloc
* 2;
713 uint32_t n
= inloc
/ 32;
714 uint32_t shift
= inloc
% 32;
715 interp_modes
[n
] |= interp_mode
<< shift
;
716 ps_repl_modes
[n
] |= ps_repl_mode
<< shift
;
717 if (shift
+ bits
> 32) {
721 interp_modes
[n
] |= interp_mode
>> shift
;
722 ps_repl_modes
[n
] |= ps_repl_mode
>> shift
;
727 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
728 tu_cs_emit_array(cs
, interp_modes
, 8);
730 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
731 tu_cs_emit_array(cs
, ps_repl_modes
, 8);
735 tu6_emit_fs_inputs(struct tu_cs
*cs
, const struct ir3_shader_variant
*fs
)
737 uint32_t face_regid
, coord_regid
, zwcoord_regid
, samp_id_regid
;
738 uint32_t ij_pix_regid
, ij_samp_regid
, ij_cent_regid
, ij_size_regid
;
739 uint32_t smask_in_regid
;
741 bool sample_shading
= fs
->per_samp
; /* TODO | key->sample_shading; */
742 bool enable_varyings
= fs
->total_in
> 0;
744 samp_id_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_SAMPLE_ID
);
745 smask_in_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_SAMPLE_MASK_IN
);
746 face_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_FRONT_FACE
);
747 coord_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_FRAG_COORD
);
748 zwcoord_regid
= VALIDREG(coord_regid
) ? coord_regid
+ 2 : regid(63, 0);
749 ij_pix_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PIXEL
);
750 ij_samp_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_SAMPLE
);
751 ij_cent_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_CENTROID
);
752 ij_size_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_SIZE
);
754 if (fs
->num_sampler_prefetch
> 0) {
755 assert(VALIDREG(ij_pix_regid
));
756 /* also, it seems like ij_pix is *required* to be r0.x */
757 assert(ij_pix_regid
== regid(0, 0));
760 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_PREFETCH_CNTL
, 1 + fs
->num_sampler_prefetch
);
761 tu_cs_emit(cs
, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs
->num_sampler_prefetch
) |
762 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
764 for (int i
= 0; i
< fs
->num_sampler_prefetch
; i
++) {
765 const struct ir3_sampler_prefetch
*prefetch
= &fs
->sampler_prefetch
[i
];
766 tu_cs_emit(cs
, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch
->src
) |
767 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch
->samp_id
) |
768 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch
->tex_id
) |
769 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch
->dst
) |
770 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch
->wrmask
) |
771 COND(prefetch
->half_precision
, A6XX_SP_FS_PREFETCH_CMD_HALF
) |
772 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch
->cmd
));
775 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_CONTROL_1_REG
, 5);
777 tu_cs_emit(cs
, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid
) |
778 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid
) |
779 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid
) |
780 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid
));
781 tu_cs_emit(cs
, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid
) |
782 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid
) |
784 tu_cs_emit(cs
, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid
) |
785 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid
) |
786 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid
) |
788 tu_cs_emit(cs
, 0xfc);
790 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_UNKNOWN_B980
, 1);
791 tu_cs_emit(cs
, enable_varyings
? 3 : 1);
793 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_UNKNOWN_A982
, 1);
794 tu_cs_emit(cs
, 0); /* XXX */
796 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_UPDATE_CNTL
, 1);
797 tu_cs_emit(cs
, 0xff); /* XXX */
799 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_CNTL
, 1);
801 CONDREG(ij_pix_regid
, A6XX_GRAS_CNTL_VARYING
) |
802 CONDREG(ij_cent_regid
, A6XX_GRAS_CNTL_CENTROID
) |
803 CONDREG(ij_samp_regid
, A6XX_GRAS_CNTL_PERSAMP_VARYING
) |
804 COND(VALIDREG(ij_size_regid
) && !sample_shading
, A6XX_GRAS_CNTL_SIZE
) |
805 COND(VALIDREG(ij_size_regid
) && sample_shading
, A6XX_GRAS_CNTL_SIZE_PERSAMP
) |
807 A6XX_GRAS_CNTL_SIZE
|
808 A6XX_GRAS_CNTL_XCOORD
|
809 A6XX_GRAS_CNTL_YCOORD
|
810 A6XX_GRAS_CNTL_ZCOORD
|
811 A6XX_GRAS_CNTL_WCOORD
) |
812 COND(fs
->frag_face
, A6XX_GRAS_CNTL_SIZE
));
814 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_RENDER_CONTROL0
, 2);
816 CONDREG(ij_pix_regid
, A6XX_RB_RENDER_CONTROL0_VARYING
) |
817 CONDREG(ij_cent_regid
, A6XX_RB_RENDER_CONTROL0_CENTROID
) |
818 CONDREG(ij_samp_regid
, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING
) |
819 COND(enable_varyings
, A6XX_RB_RENDER_CONTROL0_UNK10
) |
820 COND(VALIDREG(ij_size_regid
) && !sample_shading
, A6XX_RB_RENDER_CONTROL0_SIZE
) |
821 COND(VALIDREG(ij_size_regid
) && sample_shading
, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP
) |
823 A6XX_RB_RENDER_CONTROL0_SIZE
|
824 A6XX_RB_RENDER_CONTROL0_XCOORD
|
825 A6XX_RB_RENDER_CONTROL0_YCOORD
|
826 A6XX_RB_RENDER_CONTROL0_ZCOORD
|
827 A6XX_RB_RENDER_CONTROL0_WCOORD
) |
828 COND(fs
->frag_face
, A6XX_RB_RENDER_CONTROL0_SIZE
));
830 CONDREG(smask_in_regid
, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK
) |
831 CONDREG(samp_id_regid
, A6XX_RB_RENDER_CONTROL1_SAMPLEID
) |
832 CONDREG(ij_size_regid
, A6XX_RB_RENDER_CONTROL1_SIZE
) |
833 COND(fs
->frag_face
, A6XX_RB_RENDER_CONTROL1_FACENESS
));
837 tu6_emit_fs_outputs(struct tu_cs
*cs
,
838 const struct ir3_shader_variant
*fs
,
841 uint32_t smask_regid
, posz_regid
;
843 posz_regid
= ir3_find_output_regid(fs
, FRAG_RESULT_DEPTH
);
844 smask_regid
= ir3_find_output_regid(fs
, FRAG_RESULT_SAMPLE_MASK
);
846 uint32_t fragdata_regid
[8];
847 if (fs
->color0_mrt
) {
848 fragdata_regid
[0] = ir3_find_output_regid(fs
, FRAG_RESULT_COLOR
);
849 for (uint32_t i
= 1; i
< ARRAY_SIZE(fragdata_regid
); i
++)
850 fragdata_regid
[i
] = fragdata_regid
[0];
852 for (uint32_t i
= 0; i
< ARRAY_SIZE(fragdata_regid
); i
++)
853 fragdata_regid
[i
] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA0
+ i
);
856 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_OUTPUT_CNTL0
, 2);
857 tu_cs_emit(cs
, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid
) |
858 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid
) |
860 tu_cs_emit(cs
, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count
));
862 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
863 for (uint32_t i
= 0; i
< ARRAY_SIZE(fragdata_regid
); i
++) {
864 // TODO we could have a mix of half and full precision outputs,
865 // we really need to figure out half-precision from IR3_REG_HALF
866 tu_cs_emit(cs
, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid
[i
]) |
867 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION
: 0));
870 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_FS_OUTPUT_CNTL0
, 2);
871 tu_cs_emit(cs
, COND(fs
->writes_pos
, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z
) |
872 COND(fs
->writes_smask
, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK
));
873 tu_cs_emit(cs
, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count
));
875 uint32_t gras_su_depth_plane_cntl
= 0;
876 uint32_t rb_depth_plane_cntl
= 0;
877 if (fs
->no_earlyz
| fs
->writes_pos
) {
878 gras_su_depth_plane_cntl
|= A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
;
879 rb_depth_plane_cntl
|= A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
;
882 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL
, 1);
883 tu_cs_emit(cs
, gras_su_depth_plane_cntl
);
885 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_PLANE_CNTL
, 1);
886 tu_cs_emit(cs
, rb_depth_plane_cntl
);
890 tu6_emit_shader_object(struct tu_cs
*cs
,
891 gl_shader_stage stage
,
892 const struct ir3_shader_variant
*variant
,
893 const struct tu_bo
*binary_bo
,
894 uint32_t binary_offset
)
898 enum a6xx_state_block sb
;
900 case MESA_SHADER_VERTEX
:
901 reg
= REG_A6XX_SP_VS_OBJ_START_LO
;
902 opcode
= CP_LOAD_STATE6_GEOM
;
905 case MESA_SHADER_TESS_CTRL
:
906 reg
= REG_A6XX_SP_HS_OBJ_START_LO
;
907 opcode
= CP_LOAD_STATE6_GEOM
;
910 case MESA_SHADER_TESS_EVAL
:
911 reg
= REG_A6XX_SP_DS_OBJ_START_LO
;
912 opcode
= CP_LOAD_STATE6_GEOM
;
915 case MESA_SHADER_GEOMETRY
:
916 reg
= REG_A6XX_SP_GS_OBJ_START_LO
;
917 opcode
= CP_LOAD_STATE6_GEOM
;
920 case MESA_SHADER_FRAGMENT
:
921 reg
= REG_A6XX_SP_FS_OBJ_START_LO
;
922 opcode
= CP_LOAD_STATE6_FRAG
;
925 case MESA_SHADER_COMPUTE
:
926 reg
= REG_A6XX_SP_CS_OBJ_START_LO
;
927 opcode
= CP_LOAD_STATE6_FRAG
;
931 unreachable("invalid gl_shader_stage");
932 opcode
= CP_LOAD_STATE6_GEOM
;
937 if (!variant
->instrlen
) {
938 tu_cs_emit_pkt4(cs
, reg
, 2);
939 tu_cs_emit_qw(cs
, 0);
943 assert(variant
->type
== stage
);
945 const uint64_t binary_iova
= binary_bo
->iova
+ binary_offset
;
946 assert((binary_iova
& 0x3) == 0);
948 tu_cs_emit_pkt4(cs
, reg
, 2);
949 tu_cs_emit_qw(cs
, binary_iova
);
951 /* always indirect */
952 const bool indirect
= true;
954 tu_cs_emit_pkt7(cs
, opcode
, 3);
955 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(0) |
956 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER
) |
957 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
958 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
959 CP_LOAD_STATE6_0_NUM_UNIT(variant
->instrlen
));
960 tu_cs_emit_qw(cs
, binary_iova
);
962 const void *binary
= binary_bo
->map
+ binary_offset
;
964 tu_cs_emit_pkt7(cs
, opcode
, 3 + variant
->info
.sizedwords
);
965 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(0) |
966 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER
) |
967 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
968 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
969 CP_LOAD_STATE6_0_NUM_UNIT(variant
->instrlen
));
970 tu_cs_emit_qw(cs
, 0);
971 tu_cs_emit_array(cs
, binary
, variant
->info
.sizedwords
);
976 tu6_emit_immediates(struct tu_cs
*cs
, const struct ir3_shader_variant
*v
,
977 uint32_t opcode
, enum a6xx_state_block block
)
983 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
984 uint32_t base
= const_state
->offsets
.immediate
;
985 int size
= const_state
->immediates_count
;
987 /* truncate size to avoid writing constants that shader
990 size
= MIN2(size
+ base
, v
->constlen
) - base
;
995 tu_cs_emit_pkt7(cs
, opcode
, 3 + size
* 4);
996 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(base
) |
997 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
998 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
999 CP_LOAD_STATE6_0_STATE_BLOCK(block
) |
1000 CP_LOAD_STATE6_0_NUM_UNIT(size
));
1001 tu_cs_emit(cs
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
1002 tu_cs_emit(cs
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
1004 for (unsigned i
= 0; i
< size
; i
++) {
1005 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[0]);
1006 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[1]);
1007 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[2]);
1008 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[3]);
1013 tu6_emit_program(struct tu_cs
*cs
,
1014 const struct tu_pipeline_builder
*builder
,
1015 const struct tu_bo
*binary_bo
,
1018 static const struct ir3_shader_variant dummy_variant
= {
1019 .type
= MESA_SHADER_NONE
1021 assert(builder
->shaders
[MESA_SHADER_VERTEX
]);
1022 const struct ir3_shader_variant
*vs
=
1023 &builder
->shaders
[MESA_SHADER_VERTEX
]->variants
[0];
1024 const struct ir3_shader_variant
*hs
=
1025 builder
->shaders
[MESA_SHADER_TESS_CTRL
]
1026 ? &builder
->shaders
[MESA_SHADER_TESS_CTRL
]->variants
[0]
1028 const struct ir3_shader_variant
*ds
=
1029 builder
->shaders
[MESA_SHADER_TESS_EVAL
]
1030 ? &builder
->shaders
[MESA_SHADER_TESS_EVAL
]->variants
[0]
1032 const struct ir3_shader_variant
*gs
=
1033 builder
->shaders
[MESA_SHADER_GEOMETRY
]
1034 ? &builder
->shaders
[MESA_SHADER_GEOMETRY
]->variants
[0]
1036 const struct ir3_shader_variant
*fs
=
1037 builder
->shaders
[MESA_SHADER_FRAGMENT
]
1038 ? &builder
->shaders
[MESA_SHADER_FRAGMENT
]->variants
[0]
1042 vs
= &builder
->shaders
[MESA_SHADER_VERTEX
]->variants
[1];
1043 fs
= &dummy_variant
;
1046 tu6_emit_vs_config(cs
, builder
->shaders
[MESA_SHADER_VERTEX
], vs
);
1047 tu6_emit_hs_config(cs
, builder
->shaders
[MESA_SHADER_TESS_CTRL
], hs
);
1048 tu6_emit_ds_config(cs
, builder
->shaders
[MESA_SHADER_TESS_EVAL
], ds
);
1049 tu6_emit_gs_config(cs
, builder
->shaders
[MESA_SHADER_GEOMETRY
], gs
);
1050 tu6_emit_fs_config(cs
, builder
->shaders
[MESA_SHADER_FRAGMENT
], fs
);
1052 tu6_emit_vs_system_values(cs
, vs
);
1053 tu6_emit_vpc(cs
, vs
, fs
, binning_pass
);
1054 tu6_emit_vpc_varying_modes(cs
, fs
, binning_pass
);
1055 tu6_emit_fs_inputs(cs
, fs
);
1056 tu6_emit_fs_outputs(cs
, fs
, builder
->color_attachment_count
);
1058 tu6_emit_shader_object(cs
, MESA_SHADER_VERTEX
, vs
, binary_bo
,
1059 binning_pass
? builder
->binning_vs_offset
: builder
->shader_offsets
[MESA_SHADER_VERTEX
]);
1061 tu6_emit_shader_object(cs
, MESA_SHADER_FRAGMENT
, fs
, binary_bo
,
1062 builder
->shader_offsets
[MESA_SHADER_FRAGMENT
]);
1064 tu6_emit_immediates(cs
, vs
, CP_LOAD_STATE6_GEOM
, SB6_VS_SHADER
);
1066 tu6_emit_immediates(cs
, fs
, CP_LOAD_STATE6_FRAG
, SB6_FS_SHADER
);
1070 tu6_emit_vertex_input(struct tu_cs
*cs
,
1071 const struct ir3_shader_variant
*vs
,
1072 const VkPipelineVertexInputStateCreateInfo
*vi_info
,
1073 uint8_t bindings
[MAX_VERTEX_ATTRIBS
],
1074 uint16_t strides
[MAX_VERTEX_ATTRIBS
],
1075 uint16_t offsets
[MAX_VERTEX_ATTRIBS
],
1078 uint32_t vfd_decode_idx
= 0;
1080 for (uint32_t i
= 0; i
< vs
->inputs_count
; i
++) {
1081 if (vs
->inputs
[i
].sysval
|| !vs
->inputs
[i
].compmask
)
1084 const VkVertexInputAttributeDescription
*vi_attr
=
1085 tu_find_vertex_input_attribute(vi_info
, vs
->inputs
[i
].slot
);
1086 const VkVertexInputBindingDescription
*vi_binding
=
1087 tu_find_vertex_input_binding(vi_info
, vi_attr
);
1088 assert(vi_attr
&& vi_binding
);
1090 const struct tu_native_format
*format
=
1091 tu6_get_native_format(vi_attr
->format
);
1092 assert(format
&& format
->vtx
>= 0);
1094 uint32_t vfd_decode
= A6XX_VFD_DECODE_INSTR_IDX(vfd_decode_idx
) |
1095 A6XX_VFD_DECODE_INSTR_FORMAT(format
->vtx
) |
1096 A6XX_VFD_DECODE_INSTR_SWAP(format
->swap
) |
1097 A6XX_VFD_DECODE_INSTR_UNK30
;
1098 if (vi_binding
->inputRate
== VK_VERTEX_INPUT_RATE_INSTANCE
)
1099 vfd_decode
|= A6XX_VFD_DECODE_INSTR_INSTANCED
;
1100 if (!vk_format_is_int(vi_attr
->format
))
1101 vfd_decode
|= A6XX_VFD_DECODE_INSTR_FLOAT
;
1103 const uint32_t vfd_decode_step_rate
= 1;
1105 const uint32_t vfd_dest_cntl
=
1106 A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vs
->inputs
[i
].compmask
) |
1107 A6XX_VFD_DEST_CNTL_INSTR_REGID(vs
->inputs
[i
].regid
);
1109 tu_cs_emit_pkt4(cs
, REG_A6XX_VFD_DECODE(vfd_decode_idx
), 2);
1110 tu_cs_emit(cs
, vfd_decode
);
1111 tu_cs_emit(cs
, vfd_decode_step_rate
);
1113 tu_cs_emit_pkt4(cs
, REG_A6XX_VFD_DEST_CNTL(vfd_decode_idx
), 1);
1114 tu_cs_emit(cs
, vfd_dest_cntl
);
1116 bindings
[vfd_decode_idx
] = vi_binding
->binding
;
1117 strides
[vfd_decode_idx
] = vi_binding
->stride
;
1118 offsets
[vfd_decode_idx
] = vi_attr
->offset
;
1121 assert(vfd_decode_idx
<= MAX_VERTEX_ATTRIBS
);
1124 tu_cs_emit_pkt4(cs
, REG_A6XX_VFD_CONTROL_0
, 1);
1126 cs
, A6XX_VFD_CONTROL_0_VTXCNT(vfd_decode_idx
) | (vfd_decode_idx
<< 8));
1128 *count
= vfd_decode_idx
;
1132 tu6_guardband_adj(uint32_t v
)
1135 return (uint32_t)(511.0 - 65.0 * (log2(v
) - 8.0));
1141 tu6_emit_viewport(struct tu_cs
*cs
, const VkViewport
*viewport
)
1145 scales
[0] = viewport
->width
/ 2.0f
;
1146 scales
[1] = viewport
->height
/ 2.0f
;
1147 scales
[2] = viewport
->maxDepth
- viewport
->minDepth
;
1148 offsets
[0] = viewport
->x
+ scales
[0];
1149 offsets
[1] = viewport
->y
+ scales
[1];
1150 offsets
[2] = viewport
->minDepth
;
1154 min
.x
= (int32_t) viewport
->x
;
1155 max
.x
= (int32_t) ceilf(viewport
->x
+ viewport
->width
);
1156 if (viewport
->height
>= 0.0f
) {
1157 min
.y
= (int32_t) viewport
->y
;
1158 max
.y
= (int32_t) ceilf(viewport
->y
+ viewport
->height
);
1160 min
.y
= (int32_t)(viewport
->y
+ viewport
->height
);
1161 max
.y
= (int32_t) ceilf(viewport
->y
);
1163 /* the spec allows viewport->height to be 0.0f */
1166 assert(min
.x
>= 0 && min
.x
< max
.x
);
1167 assert(min
.y
>= 0 && min
.y
< max
.y
);
1169 VkExtent2D guardband_adj
;
1170 guardband_adj
.width
= tu6_guardband_adj(max
.x
- min
.x
);
1171 guardband_adj
.height
= tu6_guardband_adj(max
.y
- min
.y
);
1173 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0
, 6);
1174 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_XOFFSET_0(offsets
[0]));
1175 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_XSCALE_0(scales
[0]));
1176 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_YOFFSET_0(offsets
[1]));
1177 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_YSCALE_0(scales
[1]));
1178 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_ZOFFSET_0(offsets
[2]));
1179 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_ZSCALE_0(scales
[2]));
1181 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0
, 2);
1182 tu_cs_emit(cs
, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(min
.x
) |
1183 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(min
.y
));
1184 tu_cs_emit(cs
, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(max
.x
- 1) |
1185 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(max
.y
- 1));
1187 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ
, 1);
1189 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj
.width
) |
1190 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj
.height
));
1194 tu6_emit_scissor(struct tu_cs
*cs
, const VkRect2D
*scissor
)
1196 const VkOffset2D min
= scissor
->offset
;
1197 const VkOffset2D max
= {
1198 scissor
->offset
.x
+ scissor
->extent
.width
,
1199 scissor
->offset
.y
+ scissor
->extent
.height
,
1202 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0
, 2);
1203 tu_cs_emit(cs
, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(min
.x
) |
1204 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(min
.y
));
1205 tu_cs_emit(cs
, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(max
.x
- 1) |
1206 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(max
.y
- 1));
1210 tu6_emit_gras_unknowns(struct tu_cs
*cs
)
1212 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_UNKNOWN_8000
, 1);
1213 tu_cs_emit(cs
, 0x80);
1214 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_UNKNOWN_8001
, 1);
1215 tu_cs_emit(cs
, 0x0);
1216 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_LAYER_CNTL
, 1);
1217 tu_cs_emit(cs
, 0x0);
1221 tu6_emit_point_size(struct tu_cs
*cs
)
1223 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_POINT_MINMAX
, 2);
1224 tu_cs_emit(cs
, A6XX_GRAS_SU_POINT_MINMAX_MIN(1.0f
/ 16.0f
) |
1225 A6XX_GRAS_SU_POINT_MINMAX_MAX(4092.0f
));
1226 tu_cs_emit(cs
, A6XX_GRAS_SU_POINT_SIZE(1.0f
));
1230 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo
*rast_info
,
1231 VkSampleCountFlagBits samples
)
1233 uint32_t gras_su_cntl
= 0;
1235 if (rast_info
->cullMode
& VK_CULL_MODE_FRONT_BIT
)
1236 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_CULL_FRONT
;
1237 if (rast_info
->cullMode
& VK_CULL_MODE_BACK_BIT
)
1238 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_CULL_BACK
;
1240 if (rast_info
->frontFace
== VK_FRONT_FACE_CLOCKWISE
)
1241 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_FRONT_CW
;
1243 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1245 if (rast_info
->depthBiasEnable
)
1246 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_POLY_OFFSET
;
1248 if (samples
> VK_SAMPLE_COUNT_1_BIT
)
1249 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_MSAA_ENABLE
;
1251 return gras_su_cntl
;
1255 tu6_emit_gras_su_cntl(struct tu_cs
*cs
,
1256 uint32_t gras_su_cntl
,
1259 assert((gras_su_cntl
& A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK
) == 0);
1260 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(line_width
/ 2.0f
);
1262 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_CNTL
, 1);
1263 tu_cs_emit(cs
, gras_su_cntl
);
1267 tu6_emit_depth_bias(struct tu_cs
*cs
,
1268 float constant_factor
,
1272 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE
, 3);
1273 tu_cs_emit(cs
, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor
));
1274 tu_cs_emit(cs
, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor
));
1275 tu_cs_emit(cs
, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp
));
1279 tu6_emit_alpha_control_disable(struct tu_cs
*cs
)
1281 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_ALPHA_CONTROL
, 1);
1286 tu6_emit_depth_control(struct tu_cs
*cs
,
1287 const VkPipelineDepthStencilStateCreateInfo
*ds_info
)
1289 assert(!ds_info
->depthBoundsTestEnable
);
1291 uint32_t rb_depth_cntl
= 0;
1292 if (ds_info
->depthTestEnable
) {
1294 A6XX_RB_DEPTH_CNTL_Z_ENABLE
|
1295 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info
->depthCompareOp
)) |
1296 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE
;
1298 if (ds_info
->depthWriteEnable
)
1299 rb_depth_cntl
|= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE
;
1302 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_CNTL
, 1);
1303 tu_cs_emit(cs
, rb_depth_cntl
);
1307 tu6_emit_stencil_control(struct tu_cs
*cs
,
1308 const VkPipelineDepthStencilStateCreateInfo
*ds_info
)
1310 uint32_t rb_stencil_control
= 0;
1311 if (ds_info
->stencilTestEnable
) {
1312 const VkStencilOpState
*front
= &ds_info
->front
;
1313 const VkStencilOpState
*back
= &ds_info
->back
;
1314 rb_stencil_control
|=
1315 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE
|
1316 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF
|
1317 A6XX_RB_STENCIL_CONTROL_STENCIL_READ
|
1318 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front
->compareOp
)) |
1319 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front
->failOp
)) |
1320 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front
->passOp
)) |
1321 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front
->depthFailOp
)) |
1322 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back
->compareOp
)) |
1323 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back
->failOp
)) |
1324 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back
->passOp
)) |
1325 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back
->depthFailOp
));
1328 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCIL_CONTROL
, 1);
1329 tu_cs_emit(cs
, rb_stencil_control
);
1333 tu6_emit_stencil_compare_mask(struct tu_cs
*cs
, uint32_t front
, uint32_t back
)
1335 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCILMASK
, 1);
1337 cs
, A6XX_RB_STENCILMASK_MASK(front
) | A6XX_RB_STENCILMASK_BFMASK(back
));
1341 tu6_emit_stencil_write_mask(struct tu_cs
*cs
, uint32_t front
, uint32_t back
)
1343 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCILWRMASK
, 1);
1344 tu_cs_emit(cs
, A6XX_RB_STENCILWRMASK_WRMASK(front
) |
1345 A6XX_RB_STENCILWRMASK_BFWRMASK(back
));
1349 tu6_emit_stencil_reference(struct tu_cs
*cs
, uint32_t front
, uint32_t back
)
1351 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCILREF
, 1);
1353 A6XX_RB_STENCILREF_REF(front
) | A6XX_RB_STENCILREF_BFREF(back
));
1357 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState
*att
,
1360 const enum a3xx_rb_blend_opcode color_op
= tu6_blend_op(att
->colorBlendOp
);
1361 const enum adreno_rb_blend_factor src_color_factor
= tu6_blend_factor(
1362 has_alpha
? att
->srcColorBlendFactor
1363 : tu_blend_factor_no_dst_alpha(att
->srcColorBlendFactor
));
1364 const enum adreno_rb_blend_factor dst_color_factor
= tu6_blend_factor(
1365 has_alpha
? att
->dstColorBlendFactor
1366 : tu_blend_factor_no_dst_alpha(att
->dstColorBlendFactor
));
1367 const enum a3xx_rb_blend_opcode alpha_op
= tu6_blend_op(att
->alphaBlendOp
);
1368 const enum adreno_rb_blend_factor src_alpha_factor
=
1369 tu6_blend_factor(att
->srcAlphaBlendFactor
);
1370 const enum adreno_rb_blend_factor dst_alpha_factor
=
1371 tu6_blend_factor(att
->dstAlphaBlendFactor
);
1373 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor
) |
1374 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op
) |
1375 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor
) |
1376 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor
) |
1377 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op
) |
1378 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor
);
1382 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState
*att
,
1383 uint32_t rb_mrt_control_rop
,
1387 uint32_t rb_mrt_control
=
1388 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att
->colorWriteMask
);
1390 /* ignore blending and logic op for integer attachments */
1392 rb_mrt_control
|= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY
);
1393 return rb_mrt_control
;
1396 rb_mrt_control
|= rb_mrt_control_rop
;
1398 if (att
->blendEnable
) {
1399 rb_mrt_control
|= A6XX_RB_MRT_CONTROL_BLEND
;
1402 rb_mrt_control
|= A6XX_RB_MRT_CONTROL_BLEND2
;
1405 return rb_mrt_control
;
1409 tu6_emit_rb_mrt_controls(struct tu_cs
*cs
,
1410 const VkPipelineColorBlendStateCreateInfo
*blend_info
,
1411 const VkFormat attachment_formats
[MAX_RTS
],
1412 uint32_t *blend_enable_mask
)
1414 *blend_enable_mask
= 0;
1416 bool rop_reads_dst
= false;
1417 uint32_t rb_mrt_control_rop
= 0;
1418 if (blend_info
->logicOpEnable
) {
1419 rop_reads_dst
= tu_logic_op_reads_dst(blend_info
->logicOp
);
1420 rb_mrt_control_rop
=
1421 A6XX_RB_MRT_CONTROL_ROP_ENABLE
|
1422 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info
->logicOp
));
1425 for (uint32_t i
= 0; i
< blend_info
->attachmentCount
; i
++) {
1426 const VkPipelineColorBlendAttachmentState
*att
=
1427 &blend_info
->pAttachments
[i
];
1428 const VkFormat format
= attachment_formats
[i
];
1430 uint32_t rb_mrt_control
= 0;
1431 uint32_t rb_mrt_blend_control
= 0;
1432 if (format
!= VK_FORMAT_UNDEFINED
) {
1433 const bool is_int
= vk_format_is_int(format
);
1434 const bool has_alpha
= vk_format_has_alpha(format
);
1437 tu6_rb_mrt_control(att
, rb_mrt_control_rop
, is_int
, has_alpha
);
1438 rb_mrt_blend_control
= tu6_rb_mrt_blend_control(att
, has_alpha
);
1440 if (att
->blendEnable
|| rop_reads_dst
)
1441 *blend_enable_mask
|= 1 << i
;
1444 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_CONTROL(i
), 2);
1445 tu_cs_emit(cs
, rb_mrt_control
);
1446 tu_cs_emit(cs
, rb_mrt_blend_control
);
1449 for (uint32_t i
= blend_info
->attachmentCount
; i
< MAX_RTS
; i
++) {
1450 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_CONTROL(i
), 2);
1457 tu6_emit_blend_control(struct tu_cs
*cs
,
1458 uint32_t blend_enable_mask
,
1459 const VkPipelineMultisampleStateCreateInfo
*msaa_info
)
1461 assert(!msaa_info
->sampleShadingEnable
);
1462 assert(!msaa_info
->alphaToOneEnable
);
1464 uint32_t sp_blend_cntl
= A6XX_SP_BLEND_CNTL_UNK8
;
1465 if (blend_enable_mask
)
1466 sp_blend_cntl
|= A6XX_SP_BLEND_CNTL_ENABLED
;
1467 if (msaa_info
->alphaToCoverageEnable
)
1468 sp_blend_cntl
|= A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE
;
1470 const uint32_t sample_mask
=
1471 msaa_info
->pSampleMask
? *msaa_info
->pSampleMask
1472 : ((1 << msaa_info
->rasterizationSamples
) - 1);
1474 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
1475 uint32_t rb_blend_cntl
=
1476 A6XX_RB_BLEND_CNTL_ENABLE_BLEND(blend_enable_mask
) |
1477 A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND
|
1478 A6XX_RB_BLEND_CNTL_SAMPLE_MASK(sample_mask
);
1479 if (msaa_info
->alphaToCoverageEnable
)
1480 rb_blend_cntl
|= A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE
;
1482 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_BLEND_CNTL
, 1);
1483 tu_cs_emit(cs
, sp_blend_cntl
);
1485 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_BLEND_CNTL
, 1);
1486 tu_cs_emit(cs
, rb_blend_cntl
);
1490 tu6_emit_blend_constants(struct tu_cs
*cs
, const float constants
[4])
1492 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_BLEND_RED_F32
, 4);
1493 tu_cs_emit_array(cs
, (const uint32_t *) constants
, 4);
1497 tu_pipeline_create(struct tu_device
*dev
,
1498 const VkAllocationCallbacks
*pAllocator
,
1499 struct tu_pipeline
**out_pipeline
)
1501 struct tu_pipeline
*pipeline
=
1502 vk_zalloc2(&dev
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
1503 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1505 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1507 tu_cs_init(&pipeline
->cs
, TU_CS_MODE_SUB_STREAM
, 2048);
1509 /* reserve the space now such that tu_cs_begin_sub_stream never fails */
1510 VkResult result
= tu_cs_reserve_space(dev
, &pipeline
->cs
, 2048);
1511 if (result
!= VK_SUCCESS
) {
1512 vk_free2(&dev
->alloc
, pAllocator
, pipeline
);
1516 *out_pipeline
= pipeline
;
1522 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder
*builder
)
1524 const VkPipelineShaderStageCreateInfo
*stage_infos
[MESA_SHADER_STAGES
] = {
1527 for (uint32_t i
= 0; i
< builder
->create_info
->stageCount
; i
++) {
1528 gl_shader_stage stage
=
1529 tu_shader_stage(builder
->create_info
->pStages
[i
].stage
);
1530 stage_infos
[stage
] = &builder
->create_info
->pStages
[i
];
1533 struct tu_shader_compile_options options
;
1534 tu_shader_compile_options_init(&options
, builder
->create_info
);
1536 /* compile shaders in reverse order */
1537 struct tu_shader
*next_stage_shader
= NULL
;
1538 for (gl_shader_stage stage
= MESA_SHADER_STAGES
- 1;
1539 stage
> MESA_SHADER_NONE
; stage
--) {
1540 const VkPipelineShaderStageCreateInfo
*stage_info
= stage_infos
[stage
];
1544 struct tu_shader
*shader
=
1545 tu_shader_create(builder
->device
, stage
, stage_info
, builder
->layout
,
1548 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1551 tu_shader_compile(builder
->device
, shader
, next_stage_shader
,
1552 &options
, builder
->alloc
);
1553 if (result
!= VK_SUCCESS
)
1556 builder
->shaders
[stage
] = shader
;
1557 builder
->shader_offsets
[stage
] = builder
->shader_total_size
;
1558 builder
->shader_total_size
+=
1559 sizeof(uint32_t) * shader
->variants
[0].info
.sizedwords
;
1561 next_stage_shader
= shader
;
1564 if (builder
->shaders
[MESA_SHADER_VERTEX
]->has_binning_pass
) {
1565 const struct tu_shader
*vs
= builder
->shaders
[MESA_SHADER_VERTEX
];
1566 builder
->binning_vs_offset
= builder
->shader_total_size
;
1567 builder
->shader_total_size
+=
1568 sizeof(uint32_t) * vs
->variants
[1].info
.sizedwords
;
1575 tu_pipeline_builder_upload_shaders(struct tu_pipeline_builder
*builder
,
1576 struct tu_pipeline
*pipeline
)
1578 struct tu_bo
*bo
= &pipeline
->program
.binary_bo
;
1581 tu_bo_init_new(builder
->device
, bo
, builder
->shader_total_size
);
1582 if (result
!= VK_SUCCESS
)
1585 result
= tu_bo_map(builder
->device
, bo
);
1586 if (result
!= VK_SUCCESS
)
1589 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
1590 const struct tu_shader
*shader
= builder
->shaders
[i
];
1594 memcpy(bo
->map
+ builder
->shader_offsets
[i
], shader
->binary
,
1595 sizeof(uint32_t) * shader
->variants
[0].info
.sizedwords
);
1598 if (builder
->shaders
[MESA_SHADER_VERTEX
]->has_binning_pass
) {
1599 const struct tu_shader
*vs
= builder
->shaders
[MESA_SHADER_VERTEX
];
1600 memcpy(bo
->map
+ builder
->binning_vs_offset
, vs
->binning_binary
,
1601 sizeof(uint32_t) * vs
->variants
[1].info
.sizedwords
);
1608 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder
*builder
,
1609 struct tu_pipeline
*pipeline
)
1611 const VkPipelineDynamicStateCreateInfo
*dynamic_info
=
1612 builder
->create_info
->pDynamicState
;
1617 for (uint32_t i
= 0; i
< dynamic_info
->dynamicStateCount
; i
++) {
1618 pipeline
->dynamic_state
.mask
|=
1619 tu_dynamic_state_bit(dynamic_info
->pDynamicStates
[i
]);
1624 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder
*builder
,
1625 struct tu_pipeline
*pipeline
)
1627 struct tu_cs prog_cs
;
1628 tu_cs_begin_sub_stream(builder
->device
, &pipeline
->cs
, 512, &prog_cs
);
1629 tu6_emit_program(&prog_cs
, builder
, &pipeline
->program
.binary_bo
, false);
1630 pipeline
->program
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &prog_cs
);
1632 tu_cs_begin_sub_stream(builder
->device
, &pipeline
->cs
, 512, &prog_cs
);
1633 tu6_emit_program(&prog_cs
, builder
, &pipeline
->program
.binary_bo
, true);
1634 pipeline
->program
.binning_state_ib
=
1635 tu_cs_end_sub_stream(&pipeline
->cs
, &prog_cs
);
1637 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
1638 if (!builder
->shaders
[i
])
1641 struct tu_program_descriptor_linkage
*link
= &pipeline
->program
.link
[i
];
1642 struct ir3_shader
*shader
= builder
->shaders
[i
]->variants
[0].shader
;
1644 link
->ubo_state
= shader
->ubo_state
;
1645 link
->const_state
= shader
->const_state
;
1646 link
->constlen
= builder
->shaders
[i
]->variants
[0].constlen
;
1647 link
->texture_map
= builder
->shaders
[i
]->texture_map
;
1648 link
->sampler_map
= builder
->shaders
[i
]->sampler_map
;
1649 link
->ubo_map
= builder
->shaders
[i
]->ubo_map
;
1650 link
->ssbo_map
= builder
->shaders
[i
]->ssbo_map
;
1651 link
->image_mapping
= builder
->shaders
[i
]->variants
[0].image_mapping
;
1656 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder
*builder
,
1657 struct tu_pipeline
*pipeline
)
1659 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1660 builder
->create_info
->pVertexInputState
;
1661 const struct tu_shader
*vs
= builder
->shaders
[MESA_SHADER_VERTEX
];
1664 tu_cs_begin_sub_stream(builder
->device
, &pipeline
->cs
,
1665 MAX_VERTEX_ATTRIBS
* 5 + 2, &vi_cs
);
1666 tu6_emit_vertex_input(&vi_cs
, &vs
->variants
[0], vi_info
,
1667 pipeline
->vi
.bindings
, pipeline
->vi
.strides
,
1668 pipeline
->vi
.offsets
, &pipeline
->vi
.count
);
1669 pipeline
->vi
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &vi_cs
);
1671 if (vs
->has_binning_pass
) {
1672 tu_cs_begin_sub_stream(builder
->device
, &pipeline
->cs
,
1673 MAX_VERTEX_ATTRIBS
* 5 + 2, &vi_cs
);
1674 tu6_emit_vertex_input(
1675 &vi_cs
, &vs
->variants
[1], vi_info
, pipeline
->vi
.binning_bindings
,
1676 pipeline
->vi
.binning_strides
, pipeline
->vi
.binning_offsets
,
1677 &pipeline
->vi
.binning_count
);
1678 pipeline
->vi
.binning_state_ib
=
1679 tu_cs_end_sub_stream(&pipeline
->cs
, &vi_cs
);
1684 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder
*builder
,
1685 struct tu_pipeline
*pipeline
)
1687 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1688 builder
->create_info
->pInputAssemblyState
;
1690 pipeline
->ia
.primtype
= tu6_primtype(ia_info
->topology
);
1691 pipeline
->ia
.primitive_restart
= ia_info
->primitiveRestartEnable
;
1695 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder
*builder
,
1696 struct tu_pipeline
*pipeline
)
1700 * pViewportState is a pointer to an instance of the
1701 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
1702 * pipeline has rasterization disabled."
1704 * We leave the relevant registers stale in that case.
1706 if (builder
->rasterizer_discard
)
1709 const VkPipelineViewportStateCreateInfo
*vp_info
=
1710 builder
->create_info
->pViewportState
;
1713 tu_cs_begin_sub_stream(builder
->device
, &pipeline
->cs
, 15, &vp_cs
);
1715 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_VIEWPORT
)) {
1716 assert(vp_info
->viewportCount
== 1);
1717 tu6_emit_viewport(&vp_cs
, vp_info
->pViewports
);
1720 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_SCISSOR
)) {
1721 assert(vp_info
->scissorCount
== 1);
1722 tu6_emit_scissor(&vp_cs
, vp_info
->pScissors
);
1725 pipeline
->vp
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &vp_cs
);
1729 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder
*builder
,
1730 struct tu_pipeline
*pipeline
)
1732 const VkPipelineRasterizationStateCreateInfo
*rast_info
=
1733 builder
->create_info
->pRasterizationState
;
1735 assert(!rast_info
->depthClampEnable
);
1736 assert(rast_info
->polygonMode
== VK_POLYGON_MODE_FILL
);
1738 struct tu_cs rast_cs
;
1739 tu_cs_begin_sub_stream(builder
->device
, &pipeline
->cs
, 20, &rast_cs
);
1741 /* move to hw ctx init? */
1742 tu6_emit_gras_unknowns(&rast_cs
);
1743 tu6_emit_point_size(&rast_cs
);
1745 const uint32_t gras_su_cntl
=
1746 tu6_gras_su_cntl(rast_info
, builder
->samples
);
1748 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_LINE_WIDTH
))
1749 tu6_emit_gras_su_cntl(&rast_cs
, gras_su_cntl
, rast_info
->lineWidth
);
1751 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_DEPTH_BIAS
)) {
1752 tu6_emit_depth_bias(&rast_cs
, rast_info
->depthBiasConstantFactor
,
1753 rast_info
->depthBiasClamp
,
1754 rast_info
->depthBiasSlopeFactor
);
1757 pipeline
->rast
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &rast_cs
);
1759 pipeline
->rast
.gras_su_cntl
= gras_su_cntl
;
1763 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder
*builder
,
1764 struct tu_pipeline
*pipeline
)
1768 * pDepthStencilState is a pointer to an instance of the
1769 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
1770 * the pipeline has rasterization disabled or if the subpass of the
1771 * render pass the pipeline is created against does not use a
1772 * depth/stencil attachment.
1774 * We disable both depth and stenil tests in those cases.
1776 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info
;
1777 const VkPipelineDepthStencilStateCreateInfo
*ds_info
=
1778 builder
->use_depth_stencil_attachment
1779 ? builder
->create_info
->pDepthStencilState
1783 tu_cs_begin_sub_stream(builder
->device
, &pipeline
->cs
, 12, &ds_cs
);
1785 /* move to hw ctx init? */
1786 tu6_emit_alpha_control_disable(&ds_cs
);
1788 tu6_emit_depth_control(&ds_cs
, ds_info
);
1789 tu6_emit_stencil_control(&ds_cs
, ds_info
);
1791 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_COMPARE_MASK
)) {
1792 tu6_emit_stencil_compare_mask(&ds_cs
, ds_info
->front
.compareMask
,
1793 ds_info
->back
.compareMask
);
1795 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_WRITE_MASK
)) {
1796 tu6_emit_stencil_write_mask(&ds_cs
, ds_info
->front
.writeMask
,
1797 ds_info
->back
.writeMask
);
1799 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_REFERENCE
)) {
1800 tu6_emit_stencil_reference(&ds_cs
, ds_info
->front
.reference
,
1801 ds_info
->back
.reference
);
1804 pipeline
->ds
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &ds_cs
);
1808 tu_pipeline_builder_parse_multisample_and_color_blend(
1809 struct tu_pipeline_builder
*builder
, struct tu_pipeline
*pipeline
)
1813 * pMultisampleState is a pointer to an instance of the
1814 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
1815 * has rasterization disabled.
1819 * pColorBlendState is a pointer to an instance of the
1820 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
1821 * pipeline has rasterization disabled or if the subpass of the render
1822 * pass the pipeline is created against does not use any color
1825 * We leave the relevant registers stale when rasterization is disabled.
1827 if (builder
->rasterizer_discard
)
1830 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info
;
1831 const VkPipelineMultisampleStateCreateInfo
*msaa_info
=
1832 builder
->create_info
->pMultisampleState
;
1833 const VkPipelineColorBlendStateCreateInfo
*blend_info
=
1834 builder
->use_color_attachments
? builder
->create_info
->pColorBlendState
1835 : &dummy_blend_info
;
1837 struct tu_cs blend_cs
;
1838 tu_cs_begin_sub_stream(builder
->device
, &pipeline
->cs
, MAX_RTS
* 3 + 9,
1841 uint32_t blend_enable_mask
;
1842 tu6_emit_rb_mrt_controls(&blend_cs
, blend_info
,
1843 builder
->color_attachment_formats
,
1844 &blend_enable_mask
);
1846 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_BLEND_CONSTANTS
))
1847 tu6_emit_blend_constants(&blend_cs
, blend_info
->blendConstants
);
1849 tu6_emit_blend_control(&blend_cs
, blend_enable_mask
, msaa_info
);
1851 pipeline
->blend
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &blend_cs
);
1855 tu_pipeline_finish(struct tu_pipeline
*pipeline
,
1856 struct tu_device
*dev
,
1857 const VkAllocationCallbacks
*alloc
)
1859 tu_cs_finish(dev
, &pipeline
->cs
);
1861 if (pipeline
->program
.binary_bo
.gem_handle
)
1862 tu_bo_finish(dev
, &pipeline
->program
.binary_bo
);
1866 tu_pipeline_builder_build(struct tu_pipeline_builder
*builder
,
1867 struct tu_pipeline
**pipeline
)
1869 VkResult result
= tu_pipeline_create(builder
->device
, builder
->alloc
,
1871 if (result
!= VK_SUCCESS
)
1874 /* compile and upload shaders */
1875 result
= tu_pipeline_builder_compile_shaders(builder
);
1876 if (result
== VK_SUCCESS
)
1877 result
= tu_pipeline_builder_upload_shaders(builder
, *pipeline
);
1878 if (result
!= VK_SUCCESS
) {
1879 tu_pipeline_finish(*pipeline
, builder
->device
, builder
->alloc
);
1880 vk_free2(&builder
->device
->alloc
, builder
->alloc
, *pipeline
);
1881 *pipeline
= VK_NULL_HANDLE
;
1886 tu_pipeline_builder_parse_dynamic(builder
, *pipeline
);
1887 tu_pipeline_builder_parse_shader_stages(builder
, *pipeline
);
1888 tu_pipeline_builder_parse_vertex_input(builder
, *pipeline
);
1889 tu_pipeline_builder_parse_input_assembly(builder
, *pipeline
);
1890 tu_pipeline_builder_parse_viewport(builder
, *pipeline
);
1891 tu_pipeline_builder_parse_rasterization(builder
, *pipeline
);
1892 tu_pipeline_builder_parse_depth_stencil(builder
, *pipeline
);
1893 tu_pipeline_builder_parse_multisample_and_color_blend(builder
, *pipeline
);
1895 /* we should have reserved enough space upfront such that the CS never
1898 assert((*pipeline
)->cs
.bo_count
== 1);
1904 tu_pipeline_builder_finish(struct tu_pipeline_builder
*builder
)
1906 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
1907 if (!builder
->shaders
[i
])
1909 tu_shader_destroy(builder
->device
, builder
->shaders
[i
], builder
->alloc
);
1914 tu_pipeline_builder_init_graphics(
1915 struct tu_pipeline_builder
*builder
,
1916 struct tu_device
*dev
,
1917 struct tu_pipeline_cache
*cache
,
1918 const VkGraphicsPipelineCreateInfo
*create_info
,
1919 const VkAllocationCallbacks
*alloc
)
1921 TU_FROM_HANDLE(tu_pipeline_layout
, layout
, create_info
->layout
);
1923 *builder
= (struct tu_pipeline_builder
) {
1926 .create_info
= create_info
,
1931 builder
->rasterizer_discard
=
1932 create_info
->pRasterizationState
->rasterizerDiscardEnable
;
1934 if (builder
->rasterizer_discard
) {
1935 builder
->samples
= VK_SAMPLE_COUNT_1_BIT
;
1937 builder
->samples
= create_info
->pMultisampleState
->rasterizationSamples
;
1939 const struct tu_render_pass
*pass
=
1940 tu_render_pass_from_handle(create_info
->renderPass
);
1941 const struct tu_subpass
*subpass
=
1942 &pass
->subpasses
[create_info
->subpass
];
1944 builder
->use_depth_stencil_attachment
=
1945 subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
;
1947 assert(subpass
->color_count
== 0 ||
1948 !create_info
->pColorBlendState
||
1949 subpass
->color_count
== create_info
->pColorBlendState
->attachmentCount
);
1950 builder
->color_attachment_count
= subpass
->color_count
;
1951 for (uint32_t i
= 0; i
< subpass
->color_count
; i
++) {
1952 const uint32_t a
= subpass
->color_attachments
[i
].attachment
;
1953 if (a
== VK_ATTACHMENT_UNUSED
)
1956 builder
->color_attachment_formats
[i
] = pass
->attachments
[a
].format
;
1957 builder
->use_color_attachments
= true;
1963 tu_graphics_pipeline_create(VkDevice device
,
1964 VkPipelineCache pipelineCache
,
1965 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1966 const VkAllocationCallbacks
*pAllocator
,
1967 VkPipeline
*pPipeline
)
1969 TU_FROM_HANDLE(tu_device
, dev
, device
);
1970 TU_FROM_HANDLE(tu_pipeline_cache
, cache
, pipelineCache
);
1972 struct tu_pipeline_builder builder
;
1973 tu_pipeline_builder_init_graphics(&builder
, dev
, cache
,
1974 pCreateInfo
, pAllocator
);
1976 struct tu_pipeline
*pipeline
= NULL
;
1977 VkResult result
= tu_pipeline_builder_build(&builder
, &pipeline
);
1978 tu_pipeline_builder_finish(&builder
);
1980 if (result
== VK_SUCCESS
)
1981 *pPipeline
= tu_pipeline_to_handle(pipeline
);
1989 tu_CreateGraphicsPipelines(VkDevice device
,
1990 VkPipelineCache pipelineCache
,
1992 const VkGraphicsPipelineCreateInfo
*pCreateInfos
,
1993 const VkAllocationCallbacks
*pAllocator
,
1994 VkPipeline
*pPipelines
)
1996 VkResult final_result
= VK_SUCCESS
;
1998 for (uint32_t i
= 0; i
< count
; i
++) {
1999 VkResult result
= tu_graphics_pipeline_create(device
, pipelineCache
,
2000 &pCreateInfos
[i
], pAllocator
,
2003 if (result
!= VK_SUCCESS
)
2004 final_result
= result
;
2007 return final_result
;
2011 tu6_emit_compute_program(struct tu_cs
*cs
,
2012 struct tu_shader
*shader
,
2013 const struct tu_bo
*binary_bo
)
2015 const struct ir3_shader_variant
*v
= &shader
->variants
[0];
2017 tu6_emit_cs_config(cs
, shader
, v
);
2019 /* The compute program is the only one in the pipeline, so 0 offset. */
2020 tu6_emit_shader_object(cs
, MESA_SHADER_COMPUTE
, v
, binary_bo
, 0);
2022 tu6_emit_immediates(cs
, v
, CP_LOAD_STATE6_FRAG
, SB6_CS_SHADER
);
2026 tu_compute_upload_shader(VkDevice device
,
2027 struct tu_pipeline
*pipeline
,
2028 struct tu_shader
*shader
)
2030 TU_FROM_HANDLE(tu_device
, dev
, device
);
2031 struct tu_bo
*bo
= &pipeline
->program
.binary_bo
;
2032 struct ir3_shader_variant
*v
= &shader
->variants
[0];
2034 uint32_t shader_size
= sizeof(uint32_t) * v
->info
.sizedwords
;
2036 tu_bo_init_new(dev
, bo
, shader_size
);
2037 if (result
!= VK_SUCCESS
)
2040 result
= tu_bo_map(dev
, bo
);
2041 if (result
!= VK_SUCCESS
)
2044 memcpy(bo
->map
, shader
->binary
, shader_size
);
2051 tu_compute_pipeline_create(VkDevice device
,
2052 VkPipelineCache _cache
,
2053 const VkComputePipelineCreateInfo
*pCreateInfo
,
2054 const VkAllocationCallbacks
*pAllocator
,
2055 VkPipeline
*pPipeline
)
2057 TU_FROM_HANDLE(tu_device
, dev
, device
);
2058 TU_FROM_HANDLE(tu_pipeline_layout
, layout
, pCreateInfo
->layout
);
2059 const VkPipelineShaderStageCreateInfo
*stage_info
= &pCreateInfo
->stage
;
2062 struct tu_pipeline
*pipeline
;
2064 result
= tu_pipeline_create(dev
, pAllocator
, &pipeline
);
2065 if (result
!= VK_SUCCESS
)
2068 pipeline
->layout
= layout
;
2070 struct tu_shader_compile_options options
;
2071 tu_shader_compile_options_init(&options
, NULL
);
2073 struct tu_shader
*shader
=
2074 tu_shader_create(dev
, MESA_SHADER_COMPUTE
, stage_info
, layout
, pAllocator
);
2076 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2080 result
= tu_shader_compile(dev
, shader
, NULL
, &options
, pAllocator
);
2081 if (result
!= VK_SUCCESS
)
2084 struct tu_program_descriptor_linkage
*link
= &pipeline
->program
.link
[MESA_SHADER_COMPUTE
];
2085 struct ir3_shader_variant
*v
= &shader
->variants
[0];
2087 link
->ubo_state
= v
->shader
->ubo_state
;
2088 link
->const_state
= v
->shader
->const_state
;
2089 link
->constlen
= v
->constlen
;
2090 link
->texture_map
= shader
->texture_map
;
2091 link
->sampler_map
= shader
->sampler_map
;
2092 link
->ubo_map
= shader
->ubo_map
;
2093 link
->ssbo_map
= shader
->ssbo_map
;
2094 link
->image_mapping
= v
->image_mapping
;
2096 result
= tu_compute_upload_shader(device
, pipeline
, shader
);
2097 if (result
!= VK_SUCCESS
)
2100 for (int i
= 0; i
< 3; i
++)
2101 pipeline
->compute
.local_size
[i
] = v
->shader
->nir
->info
.cs
.local_size
[i
];
2103 struct tu_cs prog_cs
;
2104 tu_cs_begin_sub_stream(dev
, &pipeline
->cs
, 512, &prog_cs
);
2105 tu6_emit_compute_program(&prog_cs
, shader
, &pipeline
->program
.binary_bo
);
2106 pipeline
->program
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &prog_cs
);
2108 *pPipeline
= tu_pipeline_to_handle(pipeline
);
2112 tu_shader_destroy(dev
, shader
, pAllocator
);
2113 if (result
!= VK_SUCCESS
) {
2114 tu_pipeline_finish(pipeline
, dev
, pAllocator
);
2115 vk_free2(&dev
->alloc
, pAllocator
, pipeline
);
2122 tu_CreateComputePipelines(VkDevice device
,
2123 VkPipelineCache pipelineCache
,
2125 const VkComputePipelineCreateInfo
*pCreateInfos
,
2126 const VkAllocationCallbacks
*pAllocator
,
2127 VkPipeline
*pPipelines
)
2129 VkResult final_result
= VK_SUCCESS
;
2131 for (uint32_t i
= 0; i
< count
; i
++) {
2132 VkResult result
= tu_compute_pipeline_create(device
, pipelineCache
,
2134 pAllocator
, &pPipelines
[i
]);
2135 if (result
!= VK_SUCCESS
)
2136 final_result
= result
;
2139 return final_result
;
2143 tu_DestroyPipeline(VkDevice _device
,
2144 VkPipeline _pipeline
,
2145 const VkAllocationCallbacks
*pAllocator
)
2147 TU_FROM_HANDLE(tu_device
, dev
, _device
);
2148 TU_FROM_HANDLE(tu_pipeline
, pipeline
, _pipeline
);
2153 tu_pipeline_finish(pipeline
, dev
, pAllocator
);
2154 vk_free2(&dev
->alloc
, pAllocator
, pipeline
);