1e376a120b5566a96ca371e9cf8755ae2fdb5c56
[mesa.git] / src / freedreno / vulkan / tu_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "ir3/ir3_nir.h"
31 #include "main/menums.h"
32 #include "nir/nir.h"
33 #include "nir/nir_builder.h"
34 #include "spirv/nir_spirv.h"
35 #include "util/debug.h"
36 #include "util/mesa-sha1.h"
37 #include "util/u_atomic.h"
38 #include "vk_format.h"
39 #include "vk_util.h"
40
41 #include "tu_cs.h"
42
43 /* Emit IB that preloads the descriptors that the shader uses */
44
45 static inline uint32_t
46 tu6_vkstage2opcode(VkShaderStageFlags stage)
47 {
48 switch (stage) {
49 case VK_SHADER_STAGE_VERTEX_BIT:
50 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
51 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
52 case VK_SHADER_STAGE_GEOMETRY_BIT:
53 return CP_LOAD_STATE6_GEOM;
54 case VK_SHADER_STAGE_FRAGMENT_BIT:
55 case VK_SHADER_STAGE_COMPUTE_BIT:
56 return CP_LOAD_STATE6_FRAG;
57 default:
58 unreachable("bad shader type");
59 }
60 }
61
62 static enum a6xx_state_block
63 tu6_tex_stage2sb(VkShaderStageFlags stage)
64 {
65 switch (stage) {
66 case VK_SHADER_STAGE_VERTEX_BIT:
67 return SB6_VS_TEX;
68 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
69 return SB6_HS_TEX;
70 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
71 return SB6_DS_TEX;
72 case VK_SHADER_STAGE_GEOMETRY_BIT:
73 return SB6_GS_TEX;
74 case VK_SHADER_STAGE_FRAGMENT_BIT:
75 return SB6_FS_TEX;
76 case VK_SHADER_STAGE_COMPUTE_BIT:
77 return SB6_CS_TEX;
78 default:
79 unreachable("bad shader stage");
80 }
81 }
82
83 static enum a6xx_state_block
84 tu6_ubo_stage2sb(VkShaderStageFlags stage)
85 {
86 switch (stage) {
87 case VK_SHADER_STAGE_VERTEX_BIT:
88 return SB6_VS_SHADER;
89 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
90 return SB6_HS_SHADER;
91 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
92 return SB6_DS_SHADER;
93 case VK_SHADER_STAGE_GEOMETRY_BIT:
94 return SB6_GS_SHADER;
95 case VK_SHADER_STAGE_FRAGMENT_BIT:
96 return SB6_FS_SHADER;
97 case VK_SHADER_STAGE_COMPUTE_BIT:
98 return SB6_CS_SHADER;
99 default:
100 unreachable("bad shader stage");
101 }
102 }
103
104 static void
105 emit_load_state(struct tu_cs *cs, unsigned opcode, enum a6xx_state_type st,
106 enum a6xx_state_block sb, unsigned base, unsigned offset,
107 unsigned count)
108 {
109 /* Note: just emit one packet, even if count overflows NUM_UNIT. It's not
110 * clear if emitting more packets will even help anything. Presumably the
111 * descriptor cache is relatively small, and these packets stop doing
112 * anything when there are too many descriptors.
113 */
114 tu_cs_emit_pkt7(cs, opcode, 3);
115 tu_cs_emit(cs,
116 CP_LOAD_STATE6_0_STATE_TYPE(st) |
117 CP_LOAD_STATE6_0_STATE_SRC(SS6_BINDLESS) |
118 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
119 CP_LOAD_STATE6_0_NUM_UNIT(MIN2(count, 1024-1)));
120 tu_cs_emit_qw(cs, offset | (base << 28));
121 }
122
123 static unsigned
124 tu6_load_state_size(struct tu_pipeline_layout *layout, bool compute)
125 {
126 const unsigned load_state_size = 4;
127 unsigned size = 0;
128 for (unsigned i = 0; i < layout->num_sets; i++) {
129 struct tu_descriptor_set_layout *set_layout = layout->set[i].layout;
130 for (unsigned j = 0; j < set_layout->binding_count; j++) {
131 struct tu_descriptor_set_binding_layout *binding = &set_layout->binding[j];
132 unsigned count = 0;
133 /* Note: some users, like amber for example, pass in
134 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
135 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
136 */
137 VkShaderStageFlags stages = compute ?
138 binding->shader_stages & VK_SHADER_STAGE_COMPUTE_BIT :
139 binding->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
140 unsigned stage_count = util_bitcount(stages);
141 switch (binding->type) {
142 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
143 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
144 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
145 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
146 /* IBO-backed resources only need one packet for all graphics stages */
147 if (stages & ~VK_SHADER_STAGE_COMPUTE_BIT)
148 count += 1;
149 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
150 count += 1;
151 break;
152 case VK_DESCRIPTOR_TYPE_SAMPLER:
153 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
154 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
155 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
156 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
157 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
158 /* Textures and UBO's needs a packet for each stage */
159 count = stage_count;
160 break;
161 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
162 /* Because of how we pack combined images and samplers, we
163 * currently can't use one packet for the whole array.
164 */
165 count = stage_count * binding->array_size * 2;
166 break;
167 default:
168 unreachable("bad descriptor type");
169 }
170 size += count * load_state_size;
171 }
172 }
173 return size;
174 }
175
176 static void
177 tu6_emit_load_state(struct tu_pipeline *pipeline, bool compute)
178 {
179 unsigned size = tu6_load_state_size(pipeline->layout, compute);
180 if (size == 0)
181 return;
182
183 struct tu_cs cs;
184 tu_cs_begin_sub_stream(&pipeline->cs, size, &cs);
185
186 struct tu_pipeline_layout *layout = pipeline->layout;
187 for (unsigned i = 0; i < layout->num_sets; i++) {
188 struct tu_descriptor_set_layout *set_layout = layout->set[i].layout;
189 for (unsigned j = 0; j < set_layout->binding_count; j++) {
190 struct tu_descriptor_set_binding_layout *binding = &set_layout->binding[j];
191 unsigned base = i;
192 unsigned offset = binding->offset / 4;
193 /* Note: some users, like amber for example, pass in
194 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
195 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
196 */
197 VkShaderStageFlags stages = compute ?
198 binding->shader_stages & VK_SHADER_STAGE_COMPUTE_BIT :
199 binding->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
200 unsigned count = binding->array_size;
201 if (count == 0 || stages == 0)
202 continue;
203 switch (binding->type) {
204 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
205 base = MAX_SETS;
206 offset = (layout->input_attachment_count +
207 layout->set[i].dynamic_offset_start +
208 binding->dynamic_offset_offset) * A6XX_TEX_CONST_DWORDS;
209 /* fallthrough */
210 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
211 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
212 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
213 /* IBO-backed resources only need one packet for all graphics stages */
214 if (stages & ~VK_SHADER_STAGE_COMPUTE_BIT) {
215 emit_load_state(&cs, CP_LOAD_STATE6, ST6_SHADER, SB6_IBO,
216 base, offset, count);
217 }
218 if (stages & VK_SHADER_STAGE_COMPUTE_BIT) {
219 emit_load_state(&cs, CP_LOAD_STATE6_FRAG, ST6_IBO, SB6_CS_SHADER,
220 base, offset, count);
221 }
222 break;
223 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
224 base = MAX_SETS;
225 offset = (layout->set[i].input_attachment_start +
226 binding->input_attachment_offset) * A6XX_TEX_CONST_DWORDS;
227 case VK_DESCRIPTOR_TYPE_SAMPLER:
228 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
229 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER: {
230 unsigned stage_log2;
231 for_each_bit(stage_log2, stages) {
232 VkShaderStageFlags stage = 1 << stage_log2;
233 emit_load_state(&cs, tu6_vkstage2opcode(stage),
234 binding->type == VK_DESCRIPTOR_TYPE_SAMPLER ?
235 ST6_SHADER : ST6_CONSTANTS,
236 tu6_tex_stage2sb(stage), base, offset, count);
237 }
238 break;
239 }
240 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
241 base = MAX_SETS;
242 offset = (layout->input_attachment_count +
243 layout->set[i].dynamic_offset_start +
244 binding->dynamic_offset_offset) * A6XX_TEX_CONST_DWORDS;
245 /* fallthrough */
246 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER: {
247 unsigned stage_log2;
248 for_each_bit(stage_log2, stages) {
249 VkShaderStageFlags stage = 1 << stage_log2;
250 emit_load_state(&cs, tu6_vkstage2opcode(stage), ST6_UBO,
251 tu6_ubo_stage2sb(stage), base, offset, count);
252 }
253 break;
254 }
255 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER: {
256 unsigned stage_log2;
257 for_each_bit(stage_log2, stages) {
258 VkShaderStageFlags stage = 1 << stage_log2;
259 /* TODO: We could emit less CP_LOAD_STATE6 if we used
260 * struct-of-arrays instead of array-of-structs.
261 */
262 for (unsigned i = 0; i < count; i++) {
263 unsigned tex_offset = offset + 2 * i * A6XX_TEX_CONST_DWORDS;
264 unsigned sam_offset = offset + (2 * i + 1) * A6XX_TEX_CONST_DWORDS;
265 emit_load_state(&cs, tu6_vkstage2opcode(stage),
266 ST6_CONSTANTS, tu6_tex_stage2sb(stage),
267 base, tex_offset, 1);
268 emit_load_state(&cs, tu6_vkstage2opcode(stage),
269 ST6_SHADER, tu6_tex_stage2sb(stage),
270 base, sam_offset, 1);
271 }
272 }
273 break;
274 }
275 default:
276 unreachable("bad descriptor type");
277 }
278 }
279 }
280
281 pipeline->load_state.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &cs);
282 }
283
284 struct tu_pipeline_builder
285 {
286 struct tu_device *device;
287 struct tu_pipeline_cache *cache;
288 struct tu_pipeline_layout *layout;
289 const VkAllocationCallbacks *alloc;
290 const VkGraphicsPipelineCreateInfo *create_info;
291
292 struct tu_shader *shaders[MESA_SHADER_STAGES];
293 uint32_t shader_offsets[MESA_SHADER_STAGES];
294 uint32_t binning_vs_offset;
295 uint32_t shader_total_size;
296
297 bool rasterizer_discard;
298 /* these states are affectd by rasterizer_discard */
299 VkSampleCountFlagBits samples;
300 bool use_color_attachments;
301 uint32_t color_attachment_count;
302 VkFormat color_attachment_formats[MAX_RTS];
303 VkFormat depth_attachment_format;
304 };
305
306 static enum tu_dynamic_state_bits
307 tu_dynamic_state_bit(VkDynamicState state)
308 {
309 switch (state) {
310 case VK_DYNAMIC_STATE_VIEWPORT:
311 return TU_DYNAMIC_VIEWPORT;
312 case VK_DYNAMIC_STATE_SCISSOR:
313 return TU_DYNAMIC_SCISSOR;
314 case VK_DYNAMIC_STATE_LINE_WIDTH:
315 return TU_DYNAMIC_LINE_WIDTH;
316 case VK_DYNAMIC_STATE_DEPTH_BIAS:
317 return TU_DYNAMIC_DEPTH_BIAS;
318 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
319 return TU_DYNAMIC_BLEND_CONSTANTS;
320 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
321 return TU_DYNAMIC_DEPTH_BOUNDS;
322 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
323 return TU_DYNAMIC_STENCIL_COMPARE_MASK;
324 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
325 return TU_DYNAMIC_STENCIL_WRITE_MASK;
326 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
327 return TU_DYNAMIC_STENCIL_REFERENCE;
328 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
329 return TU_DYNAMIC_SAMPLE_LOCATIONS;
330 default:
331 unreachable("invalid dynamic state");
332 return 0;
333 }
334 }
335
336 static gl_shader_stage
337 tu_shader_stage(VkShaderStageFlagBits stage)
338 {
339 switch (stage) {
340 case VK_SHADER_STAGE_VERTEX_BIT:
341 return MESA_SHADER_VERTEX;
342 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
343 return MESA_SHADER_TESS_CTRL;
344 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
345 return MESA_SHADER_TESS_EVAL;
346 case VK_SHADER_STAGE_GEOMETRY_BIT:
347 return MESA_SHADER_GEOMETRY;
348 case VK_SHADER_STAGE_FRAGMENT_BIT:
349 return MESA_SHADER_FRAGMENT;
350 case VK_SHADER_STAGE_COMPUTE_BIT:
351 return MESA_SHADER_COMPUTE;
352 default:
353 unreachable("invalid VkShaderStageFlagBits");
354 return MESA_SHADER_NONE;
355 }
356 }
357
358 static bool
359 tu_logic_op_reads_dst(VkLogicOp op)
360 {
361 switch (op) {
362 case VK_LOGIC_OP_CLEAR:
363 case VK_LOGIC_OP_COPY:
364 case VK_LOGIC_OP_COPY_INVERTED:
365 case VK_LOGIC_OP_SET:
366 return false;
367 default:
368 return true;
369 }
370 }
371
372 static VkBlendFactor
373 tu_blend_factor_no_dst_alpha(VkBlendFactor factor)
374 {
375 /* treat dst alpha as 1.0 and avoid reading it */
376 switch (factor) {
377 case VK_BLEND_FACTOR_DST_ALPHA:
378 return VK_BLEND_FACTOR_ONE;
379 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
380 return VK_BLEND_FACTOR_ZERO;
381 default:
382 return factor;
383 }
384 }
385
386 static enum pc_di_primtype
387 tu6_primtype(VkPrimitiveTopology topology)
388 {
389 switch (topology) {
390 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
391 return DI_PT_POINTLIST;
392 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
393 return DI_PT_LINELIST;
394 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
395 return DI_PT_LINESTRIP;
396 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
397 return DI_PT_TRILIST;
398 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
399 return DI_PT_TRISTRIP;
400 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
401 return DI_PT_TRIFAN;
402 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
403 return DI_PT_LINE_ADJ;
404 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
405 return DI_PT_LINESTRIP_ADJ;
406 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
407 return DI_PT_TRI_ADJ;
408 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
409 return DI_PT_TRISTRIP_ADJ;
410 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
411 default:
412 unreachable("invalid primitive topology");
413 return DI_PT_NONE;
414 }
415 }
416
417 static enum adreno_compare_func
418 tu6_compare_func(VkCompareOp op)
419 {
420 switch (op) {
421 case VK_COMPARE_OP_NEVER:
422 return FUNC_NEVER;
423 case VK_COMPARE_OP_LESS:
424 return FUNC_LESS;
425 case VK_COMPARE_OP_EQUAL:
426 return FUNC_EQUAL;
427 case VK_COMPARE_OP_LESS_OR_EQUAL:
428 return FUNC_LEQUAL;
429 case VK_COMPARE_OP_GREATER:
430 return FUNC_GREATER;
431 case VK_COMPARE_OP_NOT_EQUAL:
432 return FUNC_NOTEQUAL;
433 case VK_COMPARE_OP_GREATER_OR_EQUAL:
434 return FUNC_GEQUAL;
435 case VK_COMPARE_OP_ALWAYS:
436 return FUNC_ALWAYS;
437 default:
438 unreachable("invalid VkCompareOp");
439 return FUNC_NEVER;
440 }
441 }
442
443 static enum adreno_stencil_op
444 tu6_stencil_op(VkStencilOp op)
445 {
446 switch (op) {
447 case VK_STENCIL_OP_KEEP:
448 return STENCIL_KEEP;
449 case VK_STENCIL_OP_ZERO:
450 return STENCIL_ZERO;
451 case VK_STENCIL_OP_REPLACE:
452 return STENCIL_REPLACE;
453 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
454 return STENCIL_INCR_CLAMP;
455 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
456 return STENCIL_DECR_CLAMP;
457 case VK_STENCIL_OP_INVERT:
458 return STENCIL_INVERT;
459 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
460 return STENCIL_INCR_WRAP;
461 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
462 return STENCIL_DECR_WRAP;
463 default:
464 unreachable("invalid VkStencilOp");
465 return STENCIL_KEEP;
466 }
467 }
468
469 static enum a3xx_rop_code
470 tu6_rop(VkLogicOp op)
471 {
472 switch (op) {
473 case VK_LOGIC_OP_CLEAR:
474 return ROP_CLEAR;
475 case VK_LOGIC_OP_AND:
476 return ROP_AND;
477 case VK_LOGIC_OP_AND_REVERSE:
478 return ROP_AND_REVERSE;
479 case VK_LOGIC_OP_COPY:
480 return ROP_COPY;
481 case VK_LOGIC_OP_AND_INVERTED:
482 return ROP_AND_INVERTED;
483 case VK_LOGIC_OP_NO_OP:
484 return ROP_NOOP;
485 case VK_LOGIC_OP_XOR:
486 return ROP_XOR;
487 case VK_LOGIC_OP_OR:
488 return ROP_OR;
489 case VK_LOGIC_OP_NOR:
490 return ROP_NOR;
491 case VK_LOGIC_OP_EQUIVALENT:
492 return ROP_EQUIV;
493 case VK_LOGIC_OP_INVERT:
494 return ROP_INVERT;
495 case VK_LOGIC_OP_OR_REVERSE:
496 return ROP_OR_REVERSE;
497 case VK_LOGIC_OP_COPY_INVERTED:
498 return ROP_COPY_INVERTED;
499 case VK_LOGIC_OP_OR_INVERTED:
500 return ROP_OR_INVERTED;
501 case VK_LOGIC_OP_NAND:
502 return ROP_NAND;
503 case VK_LOGIC_OP_SET:
504 return ROP_SET;
505 default:
506 unreachable("invalid VkLogicOp");
507 return ROP_NOOP;
508 }
509 }
510
511 static enum adreno_rb_blend_factor
512 tu6_blend_factor(VkBlendFactor factor)
513 {
514 switch (factor) {
515 case VK_BLEND_FACTOR_ZERO:
516 return FACTOR_ZERO;
517 case VK_BLEND_FACTOR_ONE:
518 return FACTOR_ONE;
519 case VK_BLEND_FACTOR_SRC_COLOR:
520 return FACTOR_SRC_COLOR;
521 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
522 return FACTOR_ONE_MINUS_SRC_COLOR;
523 case VK_BLEND_FACTOR_DST_COLOR:
524 return FACTOR_DST_COLOR;
525 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
526 return FACTOR_ONE_MINUS_DST_COLOR;
527 case VK_BLEND_FACTOR_SRC_ALPHA:
528 return FACTOR_SRC_ALPHA;
529 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
530 return FACTOR_ONE_MINUS_SRC_ALPHA;
531 case VK_BLEND_FACTOR_DST_ALPHA:
532 return FACTOR_DST_ALPHA;
533 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
534 return FACTOR_ONE_MINUS_DST_ALPHA;
535 case VK_BLEND_FACTOR_CONSTANT_COLOR:
536 return FACTOR_CONSTANT_COLOR;
537 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
538 return FACTOR_ONE_MINUS_CONSTANT_COLOR;
539 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
540 return FACTOR_CONSTANT_ALPHA;
541 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
542 return FACTOR_ONE_MINUS_CONSTANT_ALPHA;
543 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
544 return FACTOR_SRC_ALPHA_SATURATE;
545 case VK_BLEND_FACTOR_SRC1_COLOR:
546 return FACTOR_SRC1_COLOR;
547 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
548 return FACTOR_ONE_MINUS_SRC1_COLOR;
549 case VK_BLEND_FACTOR_SRC1_ALPHA:
550 return FACTOR_SRC1_ALPHA;
551 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
552 return FACTOR_ONE_MINUS_SRC1_ALPHA;
553 default:
554 unreachable("invalid VkBlendFactor");
555 return FACTOR_ZERO;
556 }
557 }
558
559 static enum a3xx_rb_blend_opcode
560 tu6_blend_op(VkBlendOp op)
561 {
562 switch (op) {
563 case VK_BLEND_OP_ADD:
564 return BLEND_DST_PLUS_SRC;
565 case VK_BLEND_OP_SUBTRACT:
566 return BLEND_SRC_MINUS_DST;
567 case VK_BLEND_OP_REVERSE_SUBTRACT:
568 return BLEND_DST_MINUS_SRC;
569 case VK_BLEND_OP_MIN:
570 return BLEND_MIN_DST_SRC;
571 case VK_BLEND_OP_MAX:
572 return BLEND_MAX_DST_SRC;
573 default:
574 unreachable("invalid VkBlendOp");
575 return BLEND_DST_PLUS_SRC;
576 }
577 }
578
579 static uint32_t
580 emit_xs_config(const struct ir3_shader_variant *sh)
581 {
582 if (sh->instrlen) {
583 return A6XX_SP_VS_CONFIG_ENABLED |
584 COND(sh->bindless_tex, A6XX_SP_VS_CONFIG_BINDLESS_TEX) |
585 COND(sh->bindless_samp, A6XX_SP_VS_CONFIG_BINDLESS_SAMP) |
586 COND(sh->bindless_ibo, A6XX_SP_VS_CONFIG_BINDLESS_IBO) |
587 COND(sh->bindless_ubo, A6XX_SP_VS_CONFIG_BINDLESS_UBO);
588 } else {
589 return 0;
590 }
591 }
592
593 static void
594 tu6_emit_vs_config(struct tu_cs *cs, struct tu_shader *shader,
595 const struct ir3_shader_variant *vs)
596 {
597 uint32_t sp_vs_ctrl =
598 A6XX_SP_VS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
599 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs->info.max_reg + 1) |
600 A6XX_SP_VS_CTRL_REG0_MERGEDREGS |
601 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs->branchstack);
602 if (vs->need_pixlod)
603 sp_vs_ctrl |= A6XX_SP_VS_CTRL_REG0_PIXLODENABLE;
604 if (vs->need_fine_derivatives)
605 sp_vs_ctrl |= A6XX_SP_VS_CTRL_REG0_DIFF_FINE;
606
607 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_CTRL_REG0, 1);
608 tu_cs_emit(cs, sp_vs_ctrl);
609
610 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_CONFIG, 2);
611 tu_cs_emit(cs, emit_xs_config(vs));
612 tu_cs_emit(cs, vs->instrlen);
613
614 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_VS_CNTL, 1);
615 tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(vs->constlen, 4)) |
616 A6XX_HLSQ_VS_CNTL_ENABLED);
617 }
618
619 static void
620 tu6_emit_hs_config(struct tu_cs *cs, struct tu_shader *shader,
621 const struct ir3_shader_variant *hs)
622 {
623 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
624 tu_cs_emit(cs, 0);
625
626 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_CONFIG, 2);
627 tu_cs_emit(cs, emit_xs_config(hs));
628 tu_cs_emit(cs, hs->instrlen);
629
630 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_HS_CNTL, 1);
631 tu_cs_emit(cs, A6XX_HLSQ_HS_CNTL_CONSTLEN(align(hs->constlen, 4)));
632 }
633
634 static void
635 tu6_emit_ds_config(struct tu_cs *cs, struct tu_shader *shader,
636 const struct ir3_shader_variant *ds)
637 {
638 tu_cs_emit_pkt4(cs, REG_A6XX_SP_DS_CONFIG, 2);
639 tu_cs_emit(cs, emit_xs_config(ds));
640 tu_cs_emit(cs, ds->instrlen);
641
642 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_DS_CNTL, 1);
643 tu_cs_emit(cs, A6XX_HLSQ_DS_CNTL_CONSTLEN(align(ds->constlen, 4)));
644 }
645
646 static void
647 tu6_emit_gs_config(struct tu_cs *cs, struct tu_shader *shader,
648 const struct ir3_shader_variant *gs)
649 {
650 bool has_gs = gs->type != MESA_SHADER_NONE;
651 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_PRIM_SIZE, 1);
652 tu_cs_emit(cs, 0);
653
654 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CONFIG, 2);
655 tu_cs_emit(cs, emit_xs_config(gs));
656 tu_cs_emit(cs, gs->instrlen);
657
658 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_GS_CNTL, 1);
659 tu_cs_emit(cs, COND(has_gs, A6XX_HLSQ_GS_CNTL_ENABLED) |
660 A6XX_HLSQ_GS_CNTL_CONSTLEN(align(gs->constlen, 4)));
661 }
662
663 static void
664 tu6_emit_fs_config(struct tu_cs *cs, struct tu_shader *shader,
665 const struct ir3_shader_variant *fs)
666 {
667 uint32_t sp_fs_ctrl =
668 A6XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) | 0x1000000 |
669 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs->info.max_reg + 1) |
670 A6XX_SP_FS_CTRL_REG0_MERGEDREGS |
671 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs->branchstack);
672 if (fs->total_in > 0)
673 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_VARYING;
674 if (fs->need_pixlod)
675 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_PIXLODENABLE;
676 if (fs->need_fine_derivatives)
677 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_DIFF_FINE;
678
679 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_CTRL_REG0, 1);
680 tu_cs_emit(cs, sp_fs_ctrl);
681
682 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_CONFIG, 2);
683 tu_cs_emit(cs, emit_xs_config(fs));
684 tu_cs_emit(cs, fs->instrlen);
685
686 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_FS_CNTL, 1);
687 tu_cs_emit(cs, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(fs->constlen, 4)) |
688 A6XX_HLSQ_FS_CNTL_ENABLED);
689 }
690
691 static void
692 tu6_emit_cs_config(struct tu_cs *cs, const struct tu_shader *shader,
693 const struct ir3_shader_variant *v)
694 {
695 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
696 tu_cs_emit(cs, 0xff);
697
698 unsigned constlen = align(v->constlen, 4);
699 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL, 1);
700 tu_cs_emit(cs, A6XX_HLSQ_CS_CNTL_CONSTLEN(constlen) |
701 A6XX_HLSQ_CS_CNTL_ENABLED);
702
703 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_CONFIG, 2);
704 tu_cs_emit(cs, emit_xs_config(v));
705 tu_cs_emit(cs, v->instrlen);
706
707 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_CTRL_REG0, 1);
708 tu_cs_emit(cs, A6XX_SP_CS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
709 A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(v->info.max_reg + 1) |
710 A6XX_SP_CS_CTRL_REG0_MERGEDREGS |
711 A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(v->branchstack) |
712 COND(v->need_pixlod, A6XX_SP_CS_CTRL_REG0_PIXLODENABLE) |
713 COND(v->need_fine_derivatives, A6XX_SP_CS_CTRL_REG0_DIFF_FINE));
714
715 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_UNKNOWN_A9B1, 1);
716 tu_cs_emit(cs, 0x41);
717
718 uint32_t local_invocation_id =
719 ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
720 uint32_t work_group_id =
721 ir3_find_sysval_regid(v, SYSTEM_VALUE_WORK_GROUP_ID);
722
723 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL_0, 2);
724 tu_cs_emit(cs,
725 A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) |
726 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
727 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
728 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
729 tu_cs_emit(cs, 0x2fc); /* HLSQ_CS_UNKNOWN_B998 */
730 }
731
732 static void
733 tu6_emit_vs_system_values(struct tu_cs *cs,
734 const struct ir3_shader_variant *vs,
735 const struct ir3_shader_variant *gs,
736 bool primid_passthru)
737 {
738 const uint32_t vertexid_regid =
739 ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
740 const uint32_t instanceid_regid =
741 ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
742 const uint32_t primitiveid_regid = gs->type != MESA_SHADER_NONE ?
743 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID) :
744 regid(63, 0);
745 const uint32_t gsheader_regid = gs->type != MESA_SHADER_NONE ?
746 ir3_find_sysval_regid(gs, SYSTEM_VALUE_GS_HEADER_IR3) :
747 regid(63, 0);
748
749 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_1, 6);
750 tu_cs_emit(cs, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid) |
751 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid) |
752 A6XX_VFD_CONTROL_1_REGID4PRIMID(primitiveid_regid) |
753 0xfc000000);
754 tu_cs_emit(cs, 0x0000fcfc); /* VFD_CONTROL_2 */
755 tu_cs_emit(cs, 0xfcfcfcfc); /* VFD_CONTROL_3 */
756 tu_cs_emit(cs, 0x000000fc); /* VFD_CONTROL_4 */
757 tu_cs_emit(cs, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gsheader_regid) |
758 0xfc00); /* VFD_CONTROL_5 */
759 tu_cs_emit(cs, COND(primid_passthru, A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU)); /* VFD_CONTROL_6 */
760 }
761
762 /* Add any missing varyings needed for stream-out. Otherwise varyings not
763 * used by fragment shader will be stripped out.
764 */
765 static void
766 tu6_link_streamout(struct ir3_shader_linkage *l,
767 const struct ir3_shader_variant *v)
768 {
769 const struct ir3_stream_output_info *info = &v->shader->stream_output;
770
771 /*
772 * First, any stream-out varyings not already in linkage map (ie. also
773 * consumed by frag shader) need to be added:
774 */
775 for (unsigned i = 0; i < info->num_outputs; i++) {
776 const struct ir3_stream_output *out = &info->output[i];
777 unsigned compmask =
778 (1 << (out->num_components + out->start_component)) - 1;
779 unsigned k = out->register_index;
780 unsigned idx, nextloc = 0;
781
782 /* psize/pos need to be the last entries in linkage map, and will
783 * get added link_stream_out, so skip over them:
784 */
785 if (v->outputs[k].slot == VARYING_SLOT_PSIZ ||
786 v->outputs[k].slot == VARYING_SLOT_POS)
787 continue;
788
789 for (idx = 0; idx < l->cnt; idx++) {
790 if (l->var[idx].regid == v->outputs[k].regid)
791 break;
792 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
793 }
794
795 /* add if not already in linkage map: */
796 if (idx == l->cnt)
797 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
798
799 /* expand component-mask if needed, ie streaming out all components
800 * but frag shader doesn't consume all components:
801 */
802 if (compmask & ~l->var[idx].compmask) {
803 l->var[idx].compmask |= compmask;
804 l->max_loc = MAX2(l->max_loc, l->var[idx].loc +
805 util_last_bit(l->var[idx].compmask));
806 }
807 }
808 }
809
810 static void
811 tu6_setup_streamout(const struct ir3_shader_variant *v,
812 struct ir3_shader_linkage *l, struct tu_streamout_state *tf)
813 {
814 const struct ir3_stream_output_info *info = &v->shader->stream_output;
815
816 memset(tf, 0, sizeof(*tf));
817
818 tf->prog_count = align(l->max_loc, 2) / 2;
819
820 debug_assert(tf->prog_count < ARRAY_SIZE(tf->prog));
821
822 /* set stride info to the streamout state */
823 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++)
824 tf->stride[i] = info->stride[i];
825
826 for (unsigned i = 0; i < info->num_outputs; i++) {
827 const struct ir3_stream_output *out = &info->output[i];
828 unsigned k = out->register_index;
829 unsigned idx;
830
831 /* Skip it, if there's an unused reg in the middle of outputs. */
832 if (v->outputs[k].regid == INVALID_REG)
833 continue;
834
835 tf->ncomp[out->output_buffer] += out->num_components;
836
837 /* linkage map sorted by order frag shader wants things, so
838 * a bit less ideal here..
839 */
840 for (idx = 0; idx < l->cnt; idx++)
841 if (l->var[idx].regid == v->outputs[k].regid)
842 break;
843
844 debug_assert(idx < l->cnt);
845
846 for (unsigned j = 0; j < out->num_components; j++) {
847 unsigned c = j + out->start_component;
848 unsigned loc = l->var[idx].loc + c;
849 unsigned off = j + out->dst_offset; /* in dwords */
850
851 if (loc & 1) {
852 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
853 A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
854 A6XX_VPC_SO_PROG_B_OFF(off * 4);
855 } else {
856 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
857 A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
858 A6XX_VPC_SO_PROG_A_OFF(off * 4);
859 }
860 }
861 }
862
863 tf->vpc_so_buf_cntl = A6XX_VPC_SO_BUF_CNTL_ENABLE |
864 COND(tf->ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
865 COND(tf->ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
866 COND(tf->ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
867 COND(tf->ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3);
868 }
869
870 static void
871 tu6_emit_const(struct tu_cs *cs, uint32_t opcode, uint32_t base,
872 enum a6xx_state_block block, uint32_t offset,
873 uint32_t size, uint32_t *dwords) {
874 assert(size % 4 == 0);
875
876 tu_cs_emit_pkt7(cs, opcode, 3 + size);
877 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
878 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
879 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
880 CP_LOAD_STATE6_0_STATE_BLOCK(block) |
881 CP_LOAD_STATE6_0_NUM_UNIT(size / 4));
882
883 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
884 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
885 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
886
887 tu_cs_emit_array(cs, dwords, size);
888 }
889
890 static void
891 tu6_emit_link_map(struct tu_cs *cs,
892 const struct ir3_shader_variant *producer,
893 const struct ir3_shader_variant *consumer) {
894 const struct ir3_const_state *const_state = &consumer->shader->const_state;
895 uint32_t base = const_state->offsets.primitive_map;
896 uint32_t patch_locs[MAX_VARYING] = { }, num_loc;
897 num_loc = ir3_link_geometry_stages(producer, consumer, patch_locs);
898 int size = DIV_ROUND_UP(num_loc, 4);
899
900 size = (MIN2(size + base, consumer->constlen) - base) * 4;
901 if (size <= 0)
902 return;
903
904 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, base, SB6_GS_SHADER, 0, size,
905 patch_locs);
906 }
907
908 static uint16_t
909 gl_primitive_to_tess(uint16_t primitive) {
910 switch (primitive) {
911 case GL_POINTS:
912 return TESS_POINTS;
913 case GL_LINE_STRIP:
914 return TESS_LINES;
915 case GL_TRIANGLE_STRIP:
916 return TESS_CW_TRIS;
917 default:
918 unreachable("");
919 }
920 }
921
922 static void
923 tu6_emit_vpc(struct tu_cs *cs,
924 const struct ir3_shader_variant *vs,
925 const struct ir3_shader_variant *gs,
926 const struct ir3_shader_variant *fs,
927 bool binning_pass,
928 struct tu_streamout_state *tf)
929 {
930 bool has_gs = gs->type != MESA_SHADER_NONE;
931 const struct ir3_shader_variant *last_shader = has_gs ? gs : vs;
932 struct ir3_shader_linkage linkage = { 0 };
933 ir3_link_shaders(&linkage, last_shader, fs, true);
934
935 if (last_shader->shader->stream_output.num_outputs)
936 tu6_link_streamout(&linkage, last_shader);
937
938 /* We do this after linking shaders in order to know whether PrimID
939 * passthrough needs to be enabled.
940 */
941 bool primid_passthru = linkage.primid_loc != 0xff;
942 tu6_emit_vs_system_values(cs, vs, gs, primid_passthru);
943
944 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VAR_DISABLE(0), 4);
945 tu_cs_emit(cs, ~linkage.varmask[0]);
946 tu_cs_emit(cs, ~linkage.varmask[1]);
947 tu_cs_emit(cs, ~linkage.varmask[2]);
948 tu_cs_emit(cs, ~linkage.varmask[3]);
949
950 /* a6xx finds position/pointsize at the end */
951 const uint32_t position_regid =
952 ir3_find_output_regid(last_shader, VARYING_SLOT_POS);
953 const uint32_t pointsize_regid =
954 ir3_find_output_regid(last_shader, VARYING_SLOT_PSIZ);
955 const uint32_t layer_regid = has_gs ?
956 ir3_find_output_regid(gs, VARYING_SLOT_LAYER) : regid(63, 0);
957
958 uint32_t pointsize_loc = 0xff, position_loc = 0xff, layer_loc = 0xff;
959 if (layer_regid != regid(63, 0)) {
960 layer_loc = linkage.max_loc;
961 ir3_link_add(&linkage, layer_regid, 0x1, linkage.max_loc);
962 }
963 if (position_regid != regid(63, 0)) {
964 position_loc = linkage.max_loc;
965 ir3_link_add(&linkage, position_regid, 0xf, linkage.max_loc);
966 }
967 if (pointsize_regid != regid(63, 0)) {
968 pointsize_loc = linkage.max_loc;
969 ir3_link_add(&linkage, pointsize_regid, 0x1, linkage.max_loc);
970 }
971
972 if (last_shader->shader->stream_output.num_outputs)
973 tu6_setup_streamout(last_shader, &linkage, tf);
974
975 /* map outputs of the last shader to VPC */
976 assert(linkage.cnt <= 32);
977 const uint32_t sp_out_count = DIV_ROUND_UP(linkage.cnt, 2);
978 const uint32_t sp_vpc_dst_count = DIV_ROUND_UP(linkage.cnt, 4);
979 uint32_t sp_out[16];
980 uint32_t sp_vpc_dst[8];
981 for (uint32_t i = 0; i < linkage.cnt; i++) {
982 ((uint16_t *) sp_out)[i] =
983 A6XX_SP_VS_OUT_REG_A_REGID(linkage.var[i].regid) |
984 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage.var[i].compmask);
985 ((uint8_t *) sp_vpc_dst)[i] =
986 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage.var[i].loc);
987 }
988
989 if (has_gs)
990 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_OUT_REG(0), sp_out_count);
991 else
992 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_OUT_REG(0), sp_out_count);
993 tu_cs_emit_array(cs, sp_out, sp_out_count);
994
995 if (has_gs)
996 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_VPC_DST_REG(0), sp_vpc_dst_count);
997 else
998 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_VPC_DST_REG(0), sp_vpc_dst_count);
999 tu_cs_emit_array(cs, sp_vpc_dst, sp_vpc_dst_count);
1000
1001 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMID_CNTL, 1);
1002 tu_cs_emit(cs, COND(primid_passthru, A6XX_PC_PRIMID_CNTL_PRIMID_PASSTHRU));
1003
1004 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_CNTL_0, 1);
1005 tu_cs_emit(cs, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs->total_in) |
1006 (fs->total_in > 0 ? A6XX_VPC_CNTL_0_VARYING : 0) |
1007 A6XX_VPC_CNTL_0_PRIMIDLOC(linkage.primid_loc) |
1008 A6XX_VPC_CNTL_0_UNKLOC(0xff));
1009
1010 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK, 1);
1011 tu_cs_emit(cs, A6XX_VPC_PACK_POSITIONLOC(position_loc) |
1012 A6XX_VPC_PACK_PSIZELOC(pointsize_loc) |
1013 A6XX_VPC_PACK_STRIDE_IN_VPC(linkage.max_loc));
1014
1015 if (has_gs) {
1016 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CTRL_REG0, 1);
1017 tu_cs_emit(cs, A6XX_SP_GS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
1018 A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(gs->info.max_reg + 1) |
1019 A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(gs->branchstack) |
1020 COND(gs->need_pixlod, A6XX_SP_GS_CTRL_REG0_PIXLODENABLE));
1021
1022 tu6_emit_link_map(cs, vs, gs);
1023
1024 uint32_t primitive_regid =
1025 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID);
1026 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK_GS, 1);
1027 tu_cs_emit(cs, A6XX_VPC_PACK_GS_POSITIONLOC(position_loc) |
1028 A6XX_VPC_PACK_GS_PSIZELOC(pointsize_loc) |
1029 A6XX_VPC_PACK_GS_STRIDE_IN_VPC(linkage.max_loc));
1030
1031 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9105, 1);
1032 tu_cs_emit(cs, A6XX_VPC_UNKNOWN_9105_LAYERLOC(layer_loc) | 0xff00);
1033
1034 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_809C, 1);
1035 tu_cs_emit(cs, CONDREG(layer_regid,
1036 A6XX_GRAS_UNKNOWN_809C_GS_WRITES_LAYER));
1037
1038 uint32_t flags_regid = ir3_find_output_regid(gs,
1039 VARYING_SLOT_GS_VERTEX_FLAGS_IR3);
1040
1041 tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL_GS, 1);
1042 tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT(linkage.cnt) |
1043 A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID(flags_regid));
1044
1045 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_2, 1);
1046 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC(linkage.max_loc) |
1047 CONDREG(pointsize_regid, A6XX_PC_PRIMITIVE_CNTL_2_PSIZE) |
1048 CONDREG(layer_regid, A6XX_PC_PRIMITIVE_CNTL_2_LAYER) |
1049 CONDREG(primitive_regid, A6XX_PC_PRIMITIVE_CNTL_2_PRIMITIVE_ID));
1050
1051 uint32_t vertices_out = gs->shader->nir->info.gs.vertices_out - 1;
1052 uint16_t output =
1053 gl_primitive_to_tess(gs->shader->nir->info.gs.output_primitive);
1054 uint32_t invocations = gs->shader->nir->info.gs.invocations - 1;
1055 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_5, 1);
1056 tu_cs_emit(cs,
1057 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(vertices_out) |
1058 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output) |
1059 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(invocations));
1060
1061 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_3, 1);
1062 tu_cs_emit(cs, 0);
1063
1064 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8003, 1);
1065 tu_cs_emit(cs, 0);
1066
1067 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9100, 1);
1068 tu_cs_emit(cs, 0xff);
1069
1070 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9102, 1);
1071 tu_cs_emit(cs, 0xffff00);
1072
1073 /* Size of per-primitive alloction in ldlw memory in vec4s. */
1074 uint32_t vec4_size =
1075 gs->shader->nir->info.gs.vertices_in *
1076 DIV_ROUND_UP(vs->shader->output_size, 4);
1077 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
1078 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size));
1079
1080 tu_cs_emit_pkt4(cs, REG_A6XX_PC_UNKNOWN_9B07, 1);
1081 tu_cs_emit(cs, 0);
1082
1083 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_PRIM_SIZE, 1);
1084 tu_cs_emit(cs, vs->shader->output_size);
1085 }
1086
1087 tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
1088 tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage.cnt));
1089
1090 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
1091 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage.max_loc) |
1092 (last_shader->writes_psize ? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE : 0));
1093 }
1094
1095 static int
1096 tu6_vpc_varying_mode(const struct ir3_shader_variant *fs,
1097 uint32_t index,
1098 uint8_t *interp_mode,
1099 uint8_t *ps_repl_mode)
1100 {
1101 enum
1102 {
1103 INTERP_SMOOTH = 0,
1104 INTERP_FLAT = 1,
1105 INTERP_ZERO = 2,
1106 INTERP_ONE = 3,
1107 };
1108 enum
1109 {
1110 PS_REPL_NONE = 0,
1111 PS_REPL_S = 1,
1112 PS_REPL_T = 2,
1113 PS_REPL_ONE_MINUS_T = 3,
1114 };
1115
1116 const uint32_t compmask = fs->inputs[index].compmask;
1117
1118 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
1119 * fourth component occupy three consecutive varying slots
1120 */
1121 int shift = 0;
1122 *interp_mode = 0;
1123 *ps_repl_mode = 0;
1124 if (fs->inputs[index].slot == VARYING_SLOT_PNTC) {
1125 if (compmask & 0x1) {
1126 *ps_repl_mode |= PS_REPL_S << shift;
1127 shift += 2;
1128 }
1129 if (compmask & 0x2) {
1130 *ps_repl_mode |= PS_REPL_T << shift;
1131 shift += 2;
1132 }
1133 if (compmask & 0x4) {
1134 *interp_mode |= INTERP_ZERO << shift;
1135 shift += 2;
1136 }
1137 if (compmask & 0x8) {
1138 *interp_mode |= INTERP_ONE << 6;
1139 shift += 2;
1140 }
1141 } else if ((fs->inputs[index].interpolate == INTERP_MODE_FLAT) ||
1142 fs->inputs[index].rasterflat) {
1143 for (int i = 0; i < 4; i++) {
1144 if (compmask & (1 << i)) {
1145 *interp_mode |= INTERP_FLAT << shift;
1146 shift += 2;
1147 }
1148 }
1149 }
1150
1151 return shift;
1152 }
1153
1154 static void
1155 tu6_emit_vpc_varying_modes(struct tu_cs *cs,
1156 const struct ir3_shader_variant *fs,
1157 bool binning_pass)
1158 {
1159 uint32_t interp_modes[8] = { 0 };
1160 uint32_t ps_repl_modes[8] = { 0 };
1161
1162 if (!binning_pass) {
1163 for (int i = -1;
1164 (i = ir3_next_varying(fs, i)) < (int) fs->inputs_count;) {
1165
1166 /* get the mode for input i */
1167 uint8_t interp_mode;
1168 uint8_t ps_repl_mode;
1169 const int bits =
1170 tu6_vpc_varying_mode(fs, i, &interp_mode, &ps_repl_mode);
1171
1172 /* OR the mode into the array */
1173 const uint32_t inloc = fs->inputs[i].inloc * 2;
1174 uint32_t n = inloc / 32;
1175 uint32_t shift = inloc % 32;
1176 interp_modes[n] |= interp_mode << shift;
1177 ps_repl_modes[n] |= ps_repl_mode << shift;
1178 if (shift + bits > 32) {
1179 n++;
1180 shift = 32 - shift;
1181
1182 interp_modes[n] |= interp_mode >> shift;
1183 ps_repl_modes[n] |= ps_repl_mode >> shift;
1184 }
1185 }
1186 }
1187
1188 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
1189 tu_cs_emit_array(cs, interp_modes, 8);
1190
1191 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
1192 tu_cs_emit_array(cs, ps_repl_modes, 8);
1193 }
1194
1195 static void
1196 tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
1197 {
1198 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
1199 uint32_t ij_pix_regid, ij_samp_regid, ij_cent_regid, ij_size_regid;
1200 uint32_t smask_in_regid;
1201
1202 bool sample_shading = fs->per_samp; /* TODO | key->sample_shading; */
1203 bool enable_varyings = fs->total_in > 0;
1204
1205 samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
1206 smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
1207 face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
1208 coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
1209 zwcoord_regid = VALIDREG(coord_regid) ? coord_regid + 2 : regid(63, 0);
1210 ij_pix_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
1211 ij_samp_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE);
1212 ij_cent_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID);
1213 ij_size_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE);
1214
1215 if (fs->num_sampler_prefetch > 0) {
1216 assert(VALIDREG(ij_pix_regid));
1217 /* also, it seems like ij_pix is *required* to be r0.x */
1218 assert(ij_pix_regid == regid(0, 0));
1219 }
1220
1221 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
1222 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
1223 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
1224 0x7000); // XXX);
1225 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
1226 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
1227 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch->src) |
1228 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch->samp_id) |
1229 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch->tex_id) |
1230 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch->dst) |
1231 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch->wrmask) |
1232 COND(prefetch->half_precision, A6XX_SP_FS_PREFETCH_CMD_HALF) |
1233 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch->cmd));
1234 }
1235
1236 if (fs->num_sampler_prefetch > 0) {
1237 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(0), fs->num_sampler_prefetch);
1238 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
1239 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
1240 tu_cs_emit(cs,
1241 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(prefetch->samp_bindless_id) |
1242 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(prefetch->tex_bindless_id));
1243 }
1244 }
1245
1246 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
1247 tu_cs_emit(cs, 0x7);
1248 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
1249 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
1250 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
1251 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid));
1252 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid) |
1253 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid) |
1254 0xfc00fc00);
1255 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
1256 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
1257 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid) |
1258 0x0000fc00);
1259 tu_cs_emit(cs, 0xfc);
1260
1261 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
1262 tu_cs_emit(cs, enable_varyings ? 3 : 1);
1263
1264 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
1265 tu_cs_emit(cs, 0xff); /* XXX */
1266
1267 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CNTL, 1);
1268 tu_cs_emit(cs,
1269 CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_VARYING) |
1270 CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_CENTROID) |
1271 CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
1272 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
1273 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
1274 COND(fs->frag_coord,
1275 A6XX_GRAS_CNTL_SIZE |
1276 A6XX_GRAS_CNTL_XCOORD |
1277 A6XX_GRAS_CNTL_YCOORD |
1278 A6XX_GRAS_CNTL_ZCOORD |
1279 A6XX_GRAS_CNTL_WCOORD) |
1280 COND(fs->frag_face, A6XX_GRAS_CNTL_SIZE));
1281
1282 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CONTROL0, 2);
1283 tu_cs_emit(cs,
1284 CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_VARYING) |
1285 CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_CENTROID) |
1286 CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING) |
1287 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
1288 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
1289 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
1290 COND(fs->frag_coord,
1291 A6XX_RB_RENDER_CONTROL0_SIZE |
1292 A6XX_RB_RENDER_CONTROL0_XCOORD |
1293 A6XX_RB_RENDER_CONTROL0_YCOORD |
1294 A6XX_RB_RENDER_CONTROL0_ZCOORD |
1295 A6XX_RB_RENDER_CONTROL0_WCOORD) |
1296 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE));
1297 tu_cs_emit(cs,
1298 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
1299 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
1300 CONDREG(ij_size_regid, A6XX_RB_RENDER_CONTROL1_SIZE) |
1301 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
1302
1303 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CNTL, 1);
1304 tu_cs_emit(cs, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
1305
1306 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8101, 1);
1307 tu_cs_emit(cs, COND(sample_shading, 0x6)); // XXX
1308
1309 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
1310 tu_cs_emit(cs, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
1311 }
1312
1313 static void
1314 tu6_emit_fs_outputs(struct tu_cs *cs,
1315 const struct ir3_shader_variant *fs,
1316 uint32_t mrt_count)
1317 {
1318 uint32_t smask_regid, posz_regid;
1319
1320 posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
1321 smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
1322
1323 uint32_t fragdata_regid[8];
1324 if (fs->color0_mrt) {
1325 fragdata_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
1326 for (uint32_t i = 1; i < ARRAY_SIZE(fragdata_regid); i++)
1327 fragdata_regid[i] = fragdata_regid[0];
1328 } else {
1329 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++)
1330 fragdata_regid[i] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0 + i);
1331 }
1332
1333 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_CNTL0, 2);
1334 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
1335 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
1336 0xfc000000);
1337 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count));
1338
1339 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
1340 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++) {
1341 // TODO we could have a mix of half and full precision outputs,
1342 // we really need to figure out half-precision from IR3_REG_HALF
1343 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid[i]) |
1344 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION : 0));
1345 }
1346
1347 tu_cs_emit_pkt4(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
1348 tu_cs_emit(cs, COND(fs->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
1349 COND(fs->writes_smask, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK));
1350 tu_cs_emit(cs, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count));
1351
1352 uint32_t gras_su_depth_plane_cntl = 0;
1353 uint32_t rb_depth_plane_cntl = 0;
1354 if (fs->no_earlyz || fs->writes_pos) {
1355 gras_su_depth_plane_cntl |= A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
1356 rb_depth_plane_cntl |= A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
1357 }
1358
1359 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
1360 tu_cs_emit(cs, gras_su_depth_plane_cntl);
1361
1362 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
1363 tu_cs_emit(cs, rb_depth_plane_cntl);
1364 }
1365
1366 static void
1367 tu6_emit_shader_object(struct tu_cs *cs,
1368 gl_shader_stage stage,
1369 const struct ir3_shader_variant *variant,
1370 const struct tu_bo *binary_bo,
1371 uint32_t binary_offset)
1372 {
1373 uint16_t reg;
1374 uint8_t opcode;
1375 enum a6xx_state_block sb;
1376 switch (stage) {
1377 case MESA_SHADER_VERTEX:
1378 reg = REG_A6XX_SP_VS_OBJ_START_LO;
1379 opcode = CP_LOAD_STATE6_GEOM;
1380 sb = SB6_VS_SHADER;
1381 break;
1382 case MESA_SHADER_TESS_CTRL:
1383 reg = REG_A6XX_SP_HS_OBJ_START_LO;
1384 opcode = CP_LOAD_STATE6_GEOM;
1385 sb = SB6_HS_SHADER;
1386 break;
1387 case MESA_SHADER_TESS_EVAL:
1388 reg = REG_A6XX_SP_DS_OBJ_START_LO;
1389 opcode = CP_LOAD_STATE6_GEOM;
1390 sb = SB6_DS_SHADER;
1391 break;
1392 case MESA_SHADER_GEOMETRY:
1393 reg = REG_A6XX_SP_GS_OBJ_START_LO;
1394 opcode = CP_LOAD_STATE6_GEOM;
1395 sb = SB6_GS_SHADER;
1396 break;
1397 case MESA_SHADER_FRAGMENT:
1398 reg = REG_A6XX_SP_FS_OBJ_START_LO;
1399 opcode = CP_LOAD_STATE6_FRAG;
1400 sb = SB6_FS_SHADER;
1401 break;
1402 case MESA_SHADER_COMPUTE:
1403 reg = REG_A6XX_SP_CS_OBJ_START_LO;
1404 opcode = CP_LOAD_STATE6_FRAG;
1405 sb = SB6_CS_SHADER;
1406 break;
1407 default:
1408 unreachable("invalid gl_shader_stage");
1409 opcode = CP_LOAD_STATE6_GEOM;
1410 sb = SB6_VS_SHADER;
1411 break;
1412 }
1413
1414 if (!variant->instrlen) {
1415 tu_cs_emit_pkt4(cs, reg, 2);
1416 tu_cs_emit_qw(cs, 0);
1417 return;
1418 }
1419
1420 assert(variant->type == stage);
1421
1422 const uint64_t binary_iova = binary_bo->iova + binary_offset;
1423 assert((binary_iova & 0xf) == 0);
1424 /* note: it looks like HW might try to read a few instructions beyond the instrlen size
1425 * of the shader. this could be a potential source of problems at some point
1426 * possibly this doesn't happen if shader iova is aligned enough (to 4k for example)
1427 */
1428
1429 tu_cs_emit_pkt4(cs, reg, 2);
1430 tu_cs_emit_qw(cs, binary_iova);
1431
1432 /* always indirect */
1433 const bool indirect = true;
1434 if (indirect) {
1435 tu_cs_emit_pkt7(cs, opcode, 3);
1436 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
1437 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
1438 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
1439 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
1440 CP_LOAD_STATE6_0_NUM_UNIT(variant->instrlen));
1441 tu_cs_emit_qw(cs, binary_iova);
1442 } else {
1443 const void *binary = binary_bo->map + binary_offset;
1444
1445 tu_cs_emit_pkt7(cs, opcode, 3 + variant->info.sizedwords);
1446 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
1447 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
1448 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
1449 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
1450 CP_LOAD_STATE6_0_NUM_UNIT(variant->instrlen));
1451 tu_cs_emit_qw(cs, 0);
1452 tu_cs_emit_array(cs, binary, variant->info.sizedwords);
1453 }
1454 }
1455
1456 static void
1457 tu6_emit_immediates(struct tu_cs *cs, const struct ir3_shader_variant *v,
1458 uint32_t opcode, enum a6xx_state_block block)
1459 {
1460 /* dummy variant */
1461 if (!v->shader)
1462 return;
1463
1464 const struct ir3_const_state *const_state = &v->shader->const_state;
1465 uint32_t base = const_state->offsets.immediate;
1466 int size = const_state->immediates_count;
1467
1468 /* truncate size to avoid writing constants that shader
1469 * does not use:
1470 */
1471 size = MIN2(size + base, v->constlen) - base;
1472
1473 if (size <= 0)
1474 return;
1475
1476 tu_cs_emit_pkt7(cs, opcode, 3 + size * 4);
1477 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
1478 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
1479 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
1480 CP_LOAD_STATE6_0_STATE_BLOCK(block) |
1481 CP_LOAD_STATE6_0_NUM_UNIT(size));
1482 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
1483 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
1484
1485 for (unsigned i = 0; i < size; i++) {
1486 tu_cs_emit(cs, const_state->immediates[i].val[0]);
1487 tu_cs_emit(cs, const_state->immediates[i].val[1]);
1488 tu_cs_emit(cs, const_state->immediates[i].val[2]);
1489 tu_cs_emit(cs, const_state->immediates[i].val[3]);
1490 }
1491 }
1492
1493 static void
1494 tu6_emit_geometry_consts(struct tu_cs *cs,
1495 const struct ir3_shader_variant *vs,
1496 const struct ir3_shader_variant *gs) {
1497 unsigned num_vertices = gs->shader->nir->info.gs.vertices_in;
1498
1499 uint32_t params[4] = {
1500 vs->shader->output_size * num_vertices * 4, /* primitive stride */
1501 vs->shader->output_size * 4, /* vertex stride */
1502 0,
1503 0,
1504 };
1505 uint32_t vs_base = vs->shader->const_state.offsets.primitive_param;
1506 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, vs_base, SB6_VS_SHADER, 0,
1507 ARRAY_SIZE(params), params);
1508
1509 uint32_t gs_base = gs->shader->const_state.offsets.primitive_param;
1510 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, gs_base, SB6_GS_SHADER, 0,
1511 ARRAY_SIZE(params), params);
1512 }
1513
1514 static void
1515 tu6_emit_program(struct tu_cs *cs,
1516 const struct tu_pipeline_builder *builder,
1517 const struct tu_bo *binary_bo,
1518 bool binning_pass,
1519 struct tu_streamout_state *tf)
1520 {
1521 static const struct ir3_shader_variant dummy_variant = {
1522 .type = MESA_SHADER_NONE
1523 };
1524 assert(builder->shaders[MESA_SHADER_VERTEX]);
1525 const struct ir3_shader_variant *vs =
1526 &builder->shaders[MESA_SHADER_VERTEX]->variants[0];
1527 const struct ir3_shader_variant *hs =
1528 builder->shaders[MESA_SHADER_TESS_CTRL]
1529 ? &builder->shaders[MESA_SHADER_TESS_CTRL]->variants[0]
1530 : &dummy_variant;
1531 const struct ir3_shader_variant *ds =
1532 builder->shaders[MESA_SHADER_TESS_EVAL]
1533 ? &builder->shaders[MESA_SHADER_TESS_EVAL]->variants[0]
1534 : &dummy_variant;
1535 const struct ir3_shader_variant *gs =
1536 builder->shaders[MESA_SHADER_GEOMETRY]
1537 ? &builder->shaders[MESA_SHADER_GEOMETRY]->variants[0]
1538 : &dummy_variant;
1539 const struct ir3_shader_variant *fs =
1540 builder->shaders[MESA_SHADER_FRAGMENT]
1541 ? &builder->shaders[MESA_SHADER_FRAGMENT]->variants[0]
1542 : &dummy_variant;
1543 bool has_gs = gs->type != MESA_SHADER_NONE;
1544
1545 if (binning_pass) {
1546 /* if we have streamout, use full VS in binning pass, as the
1547 * binning pass VS will have outputs on other than position/psize
1548 * stripped out:
1549 */
1550 if (vs->shader->stream_output.num_outputs == 0)
1551 vs = &builder->shaders[MESA_SHADER_VERTEX]->variants[1];
1552 fs = &dummy_variant;
1553 }
1554
1555 tu6_emit_vs_config(cs, builder->shaders[MESA_SHADER_VERTEX], vs);
1556 tu6_emit_hs_config(cs, builder->shaders[MESA_SHADER_TESS_CTRL], hs);
1557 tu6_emit_ds_config(cs, builder->shaders[MESA_SHADER_TESS_EVAL], ds);
1558 tu6_emit_gs_config(cs, builder->shaders[MESA_SHADER_GEOMETRY], gs);
1559 tu6_emit_fs_config(cs, builder->shaders[MESA_SHADER_FRAGMENT], fs);
1560
1561 tu6_emit_vpc(cs, vs, gs, fs, binning_pass, tf);
1562 tu6_emit_vpc_varying_modes(cs, fs, binning_pass);
1563 tu6_emit_fs_inputs(cs, fs);
1564 tu6_emit_fs_outputs(cs, fs, builder->color_attachment_count);
1565
1566 tu6_emit_shader_object(cs, MESA_SHADER_VERTEX, vs, binary_bo,
1567 binning_pass ? builder->binning_vs_offset : builder->shader_offsets[MESA_SHADER_VERTEX]);
1568 if (has_gs)
1569 tu6_emit_shader_object(cs, MESA_SHADER_GEOMETRY, gs, binary_bo,
1570 builder->shader_offsets[MESA_SHADER_GEOMETRY]);
1571 tu6_emit_shader_object(cs, MESA_SHADER_FRAGMENT, fs, binary_bo,
1572 builder->shader_offsets[MESA_SHADER_FRAGMENT]);
1573
1574 tu6_emit_immediates(cs, vs, CP_LOAD_STATE6_GEOM, SB6_VS_SHADER);
1575 if (has_gs) {
1576 tu6_emit_immediates(cs, gs, CP_LOAD_STATE6_GEOM, SB6_GS_SHADER);
1577 tu6_emit_geometry_consts(cs, vs, gs);
1578 }
1579 if (!binning_pass)
1580 tu6_emit_immediates(cs, fs, CP_LOAD_STATE6_FRAG, SB6_FS_SHADER);
1581 }
1582
1583 static void
1584 tu6_emit_vertex_input(struct tu_cs *cs,
1585 const struct ir3_shader_variant *vs,
1586 const VkPipelineVertexInputStateCreateInfo *info,
1587 uint8_t bindings[MAX_VERTEX_ATTRIBS],
1588 uint32_t *count)
1589 {
1590 uint32_t vfd_fetch_idx = 0;
1591 uint32_t vfd_decode_idx = 0;
1592 uint32_t binding_instanced = 0; /* bitmask of instanced bindings */
1593
1594 for (uint32_t i = 0; i < info->vertexBindingDescriptionCount; i++) {
1595 const VkVertexInputBindingDescription *binding =
1596 &info->pVertexBindingDescriptions[i];
1597
1598 tu_cs_emit_regs(cs,
1599 A6XX_VFD_FETCH_STRIDE(vfd_fetch_idx, binding->stride));
1600
1601 if (binding->inputRate == VK_VERTEX_INPUT_RATE_INSTANCE)
1602 binding_instanced |= 1 << binding->binding;
1603
1604 bindings[vfd_fetch_idx] = binding->binding;
1605 vfd_fetch_idx++;
1606 }
1607
1608 /* TODO: emit all VFD_DECODE/VFD_DEST_CNTL in same (two) pkt4 */
1609
1610 for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
1611 const VkVertexInputAttributeDescription *attr =
1612 &info->pVertexAttributeDescriptions[i];
1613 uint32_t binding_idx, input_idx;
1614
1615 for (binding_idx = 0; binding_idx < vfd_fetch_idx; binding_idx++) {
1616 if (bindings[binding_idx] == attr->binding)
1617 break;
1618 }
1619 assert(binding_idx < vfd_fetch_idx);
1620
1621 for (input_idx = 0; input_idx < vs->inputs_count; input_idx++) {
1622 if ((vs->inputs[input_idx].slot - VERT_ATTRIB_GENERIC0) == attr->location)
1623 break;
1624 }
1625
1626 /* attribute not used, skip it */
1627 if (input_idx == vs->inputs_count)
1628 continue;
1629
1630 const struct tu_native_format format = tu6_format_vtx(attr->format);
1631 tu_cs_emit_regs(cs,
1632 A6XX_VFD_DECODE_INSTR(vfd_decode_idx,
1633 .idx = binding_idx,
1634 .offset = attr->offset,
1635 .instanced = binding_instanced & (1 << attr->binding),
1636 .format = format.fmt,
1637 .swap = format.swap,
1638 .unk30 = 1,
1639 ._float = !vk_format_is_int(attr->format)),
1640 A6XX_VFD_DECODE_STEP_RATE(vfd_decode_idx, 1));
1641
1642 tu_cs_emit_regs(cs,
1643 A6XX_VFD_DEST_CNTL_INSTR(vfd_decode_idx,
1644 .writemask = vs->inputs[input_idx].compmask,
1645 .regid = vs->inputs[input_idx].regid));
1646
1647 vfd_decode_idx++;
1648 }
1649
1650 tu_cs_emit_regs(cs,
1651 A6XX_VFD_CONTROL_0(
1652 .fetch_cnt = vfd_fetch_idx,
1653 .decode_cnt = vfd_decode_idx));
1654
1655 *count = vfd_fetch_idx;
1656 }
1657
1658 static uint32_t
1659 tu6_guardband_adj(uint32_t v)
1660 {
1661 if (v > 256)
1662 return (uint32_t)(511.0 - 65.0 * (log2(v) - 8.0));
1663 else
1664 return 511;
1665 }
1666
1667 void
1668 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport)
1669 {
1670 float offsets[3];
1671 float scales[3];
1672 scales[0] = viewport->width / 2.0f;
1673 scales[1] = viewport->height / 2.0f;
1674 scales[2] = viewport->maxDepth - viewport->minDepth;
1675 offsets[0] = viewport->x + scales[0];
1676 offsets[1] = viewport->y + scales[1];
1677 offsets[2] = viewport->minDepth;
1678
1679 VkOffset2D min;
1680 VkOffset2D max;
1681 min.x = (int32_t) viewport->x;
1682 max.x = (int32_t) ceilf(viewport->x + viewport->width);
1683 if (viewport->height >= 0.0f) {
1684 min.y = (int32_t) viewport->y;
1685 max.y = (int32_t) ceilf(viewport->y + viewport->height);
1686 } else {
1687 min.y = (int32_t)(viewport->y + viewport->height);
1688 max.y = (int32_t) ceilf(viewport->y);
1689 }
1690 /* the spec allows viewport->height to be 0.0f */
1691 if (min.y == max.y)
1692 max.y++;
1693 assert(min.x >= 0 && min.x < max.x);
1694 assert(min.y >= 0 && min.y < max.y);
1695
1696 VkExtent2D guardband_adj;
1697 guardband_adj.width = tu6_guardband_adj(max.x - min.x);
1698 guardband_adj.height = tu6_guardband_adj(max.y - min.y);
1699
1700 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0, 6);
1701 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XOFFSET_0(offsets[0]).value);
1702 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XSCALE_0(scales[0]).value);
1703 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YOFFSET_0(offsets[1]).value);
1704 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YSCALE_0(scales[1]).value);
1705 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZOFFSET_0(offsets[2]).value);
1706 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZSCALE_0(scales[2]).value);
1707
1708 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
1709 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(min.x) |
1710 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(min.y));
1711 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(max.x - 1) |
1712 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(max.y - 1));
1713
1714 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
1715 tu_cs_emit(cs,
1716 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj.width) |
1717 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj.height));
1718
1719 float z_clamp_min = MIN2(viewport->minDepth, viewport->maxDepth);
1720 float z_clamp_max = MAX2(viewport->minDepth, viewport->maxDepth);
1721
1722 tu_cs_emit_regs(cs,
1723 A6XX_GRAS_CL_Z_CLAMP_MIN(z_clamp_min),
1724 A6XX_GRAS_CL_Z_CLAMP_MAX(z_clamp_max));
1725
1726 tu_cs_emit_regs(cs,
1727 A6XX_RB_Z_CLAMP_MIN(z_clamp_min),
1728 A6XX_RB_Z_CLAMP_MAX(z_clamp_max));
1729 }
1730
1731 void
1732 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor)
1733 {
1734 const VkOffset2D min = scissor->offset;
1735 const VkOffset2D max = {
1736 scissor->offset.x + scissor->extent.width,
1737 scissor->offset.y + scissor->extent.height,
1738 };
1739
1740 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
1741 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(min.x) |
1742 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(min.y));
1743 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(max.x - 1) |
1744 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(max.y - 1));
1745 }
1746
1747 void
1748 tu6_emit_sample_locations(struct tu_cs *cs, const VkSampleLocationsInfoEXT *samp_loc)
1749 {
1750 if (!samp_loc) {
1751 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CONFIG, 1);
1752 tu_cs_emit(cs, 0);
1753
1754 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CONFIG, 1);
1755 tu_cs_emit(cs, 0);
1756
1757 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_SAMPLE_CONFIG, 1);
1758 tu_cs_emit(cs, 0);
1759 return;
1760 }
1761
1762 assert(samp_loc->sampleLocationsPerPixel == samp_loc->sampleLocationsCount);
1763 assert(samp_loc->sampleLocationGridSize.width == 1);
1764 assert(samp_loc->sampleLocationGridSize.height == 1);
1765
1766 uint32_t sample_config =
1767 A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE;
1768 uint32_t sample_locations = 0;
1769 for (uint32_t i = 0; i < samp_loc->sampleLocationsCount; i++) {
1770 sample_locations |=
1771 (A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(samp_loc->pSampleLocations[i].x) |
1772 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(samp_loc->pSampleLocations[i].y)) << i*8;
1773 }
1774
1775 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CONFIG, 2);
1776 tu_cs_emit(cs, sample_config);
1777 tu_cs_emit(cs, sample_locations);
1778
1779 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CONFIG, 2);
1780 tu_cs_emit(cs, sample_config);
1781 tu_cs_emit(cs, sample_locations);
1782
1783 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_SAMPLE_CONFIG, 2);
1784 tu_cs_emit(cs, sample_config);
1785 tu_cs_emit(cs, sample_locations);
1786 }
1787
1788 static void
1789 tu6_emit_gras_unknowns(struct tu_cs *cs)
1790 {
1791 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8001, 1);
1792 tu_cs_emit(cs, 0x0);
1793 }
1794
1795 static void
1796 tu6_emit_point_size(struct tu_cs *cs)
1797 {
1798 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POINT_MINMAX, 2);
1799 tu_cs_emit(cs, A6XX_GRAS_SU_POINT_MINMAX_MIN(1.0f / 16.0f) |
1800 A6XX_GRAS_SU_POINT_MINMAX_MAX(4092.0f));
1801 tu_cs_emit(cs, A6XX_GRAS_SU_POINT_SIZE(1.0f).value);
1802 }
1803
1804 static uint32_t
1805 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo *rast_info,
1806 VkSampleCountFlagBits samples)
1807 {
1808 uint32_t gras_su_cntl = 0;
1809
1810 if (rast_info->cullMode & VK_CULL_MODE_FRONT_BIT)
1811 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_FRONT;
1812 if (rast_info->cullMode & VK_CULL_MODE_BACK_BIT)
1813 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_BACK;
1814
1815 if (rast_info->frontFace == VK_FRONT_FACE_CLOCKWISE)
1816 gras_su_cntl |= A6XX_GRAS_SU_CNTL_FRONT_CW;
1817
1818 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1819
1820 if (rast_info->depthBiasEnable)
1821 gras_su_cntl |= A6XX_GRAS_SU_CNTL_POLY_OFFSET;
1822
1823 if (samples > VK_SAMPLE_COUNT_1_BIT)
1824 gras_su_cntl |= A6XX_GRAS_SU_CNTL_MSAA_ENABLE;
1825
1826 return gras_su_cntl;
1827 }
1828
1829 void
1830 tu6_emit_gras_su_cntl(struct tu_cs *cs,
1831 uint32_t gras_su_cntl,
1832 float line_width)
1833 {
1834 assert((gras_su_cntl & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK) == 0);
1835 gras_su_cntl |= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(line_width / 2.0f);
1836
1837 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_CNTL, 1);
1838 tu_cs_emit(cs, gras_su_cntl);
1839 }
1840
1841 void
1842 tu6_emit_depth_bias(struct tu_cs *cs,
1843 float constant_factor,
1844 float clamp,
1845 float slope_factor)
1846 {
1847 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
1848 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor).value);
1849 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor).value);
1850 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp).value);
1851 }
1852
1853 static void
1854 tu6_emit_alpha_control_disable(struct tu_cs *cs)
1855 {
1856 tu_cs_emit_pkt4(cs, REG_A6XX_RB_ALPHA_CONTROL, 1);
1857 tu_cs_emit(cs, 0);
1858 }
1859
1860 static void
1861 tu6_emit_depth_control(struct tu_cs *cs,
1862 const VkPipelineDepthStencilStateCreateInfo *ds_info,
1863 const VkPipelineRasterizationStateCreateInfo *rast_info)
1864 {
1865 assert(!ds_info->depthBoundsTestEnable);
1866
1867 uint32_t rb_depth_cntl = 0;
1868 if (ds_info->depthTestEnable) {
1869 rb_depth_cntl |=
1870 A6XX_RB_DEPTH_CNTL_Z_ENABLE |
1871 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) |
1872 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
1873
1874 if (rast_info->depthClampEnable)
1875 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE;
1876
1877 if (ds_info->depthWriteEnable)
1878 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
1879 }
1880
1881 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_CNTL, 1);
1882 tu_cs_emit(cs, rb_depth_cntl);
1883 }
1884
1885 static void
1886 tu6_emit_stencil_control(struct tu_cs *cs,
1887 const VkPipelineDepthStencilStateCreateInfo *ds_info)
1888 {
1889 uint32_t rb_stencil_control = 0;
1890 if (ds_info->stencilTestEnable) {
1891 const VkStencilOpState *front = &ds_info->front;
1892 const VkStencilOpState *back = &ds_info->back;
1893 rb_stencil_control |=
1894 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
1895 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
1896 A6XX_RB_STENCIL_CONTROL_STENCIL_READ |
1897 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front->compareOp)) |
1898 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front->failOp)) |
1899 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front->passOp)) |
1900 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front->depthFailOp)) |
1901 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back->compareOp)) |
1902 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back->failOp)) |
1903 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back->passOp)) |
1904 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back->depthFailOp));
1905 }
1906
1907 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_CONTROL, 1);
1908 tu_cs_emit(cs, rb_stencil_control);
1909 }
1910
1911 void
1912 tu6_emit_stencil_compare_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1913 {
1914 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILMASK, 1);
1915 tu_cs_emit(
1916 cs, A6XX_RB_STENCILMASK_MASK(front) | A6XX_RB_STENCILMASK_BFMASK(back));
1917 }
1918
1919 void
1920 tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1921 {
1922 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILWRMASK, 1);
1923 tu_cs_emit(cs, A6XX_RB_STENCILWRMASK_WRMASK(front) |
1924 A6XX_RB_STENCILWRMASK_BFWRMASK(back));
1925 }
1926
1927 void
1928 tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back)
1929 {
1930 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILREF, 1);
1931 tu_cs_emit(cs,
1932 A6XX_RB_STENCILREF_REF(front) | A6XX_RB_STENCILREF_BFREF(back));
1933 }
1934
1935 static uint32_t
1936 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState *att,
1937 bool has_alpha)
1938 {
1939 const enum a3xx_rb_blend_opcode color_op = tu6_blend_op(att->colorBlendOp);
1940 const enum adreno_rb_blend_factor src_color_factor = tu6_blend_factor(
1941 has_alpha ? att->srcColorBlendFactor
1942 : tu_blend_factor_no_dst_alpha(att->srcColorBlendFactor));
1943 const enum adreno_rb_blend_factor dst_color_factor = tu6_blend_factor(
1944 has_alpha ? att->dstColorBlendFactor
1945 : tu_blend_factor_no_dst_alpha(att->dstColorBlendFactor));
1946 const enum a3xx_rb_blend_opcode alpha_op = tu6_blend_op(att->alphaBlendOp);
1947 const enum adreno_rb_blend_factor src_alpha_factor =
1948 tu6_blend_factor(att->srcAlphaBlendFactor);
1949 const enum adreno_rb_blend_factor dst_alpha_factor =
1950 tu6_blend_factor(att->dstAlphaBlendFactor);
1951
1952 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor) |
1953 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op) |
1954 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor) |
1955 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor) |
1956 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op) |
1957 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor);
1958 }
1959
1960 static uint32_t
1961 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState *att,
1962 uint32_t rb_mrt_control_rop,
1963 bool is_int,
1964 bool has_alpha)
1965 {
1966 uint32_t rb_mrt_control =
1967 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att->colorWriteMask);
1968
1969 /* ignore blending and logic op for integer attachments */
1970 if (is_int) {
1971 rb_mrt_control |= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
1972 return rb_mrt_control;
1973 }
1974
1975 rb_mrt_control |= rb_mrt_control_rop;
1976
1977 if (att->blendEnable) {
1978 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND;
1979
1980 if (has_alpha)
1981 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND2;
1982 }
1983
1984 return rb_mrt_control;
1985 }
1986
1987 static void
1988 tu6_emit_rb_mrt_controls(struct tu_cs *cs,
1989 const VkPipelineColorBlendStateCreateInfo *blend_info,
1990 const VkFormat attachment_formats[MAX_RTS],
1991 uint32_t *blend_enable_mask)
1992 {
1993 *blend_enable_mask = 0;
1994
1995 bool rop_reads_dst = false;
1996 uint32_t rb_mrt_control_rop = 0;
1997 if (blend_info->logicOpEnable) {
1998 rop_reads_dst = tu_logic_op_reads_dst(blend_info->logicOp);
1999 rb_mrt_control_rop =
2000 A6XX_RB_MRT_CONTROL_ROP_ENABLE |
2001 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info->logicOp));
2002 }
2003
2004 for (uint32_t i = 0; i < blend_info->attachmentCount; i++) {
2005 const VkPipelineColorBlendAttachmentState *att =
2006 &blend_info->pAttachments[i];
2007 const VkFormat format = attachment_formats[i];
2008
2009 uint32_t rb_mrt_control = 0;
2010 uint32_t rb_mrt_blend_control = 0;
2011 if (format != VK_FORMAT_UNDEFINED) {
2012 const bool is_int = vk_format_is_int(format);
2013 const bool has_alpha = vk_format_has_alpha(format);
2014
2015 rb_mrt_control =
2016 tu6_rb_mrt_control(att, rb_mrt_control_rop, is_int, has_alpha);
2017 rb_mrt_blend_control = tu6_rb_mrt_blend_control(att, has_alpha);
2018
2019 if (att->blendEnable || rop_reads_dst)
2020 *blend_enable_mask |= 1 << i;
2021 }
2022
2023 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
2024 tu_cs_emit(cs, rb_mrt_control);
2025 tu_cs_emit(cs, rb_mrt_blend_control);
2026 }
2027 }
2028
2029 static void
2030 tu6_emit_blend_control(struct tu_cs *cs,
2031 uint32_t blend_enable_mask,
2032 const VkPipelineMultisampleStateCreateInfo *msaa_info)
2033 {
2034 assert(!msaa_info->alphaToOneEnable);
2035
2036 uint32_t sp_blend_cntl = A6XX_SP_BLEND_CNTL_UNK8;
2037 if (blend_enable_mask)
2038 sp_blend_cntl |= A6XX_SP_BLEND_CNTL_ENABLED;
2039 if (msaa_info->alphaToCoverageEnable)
2040 sp_blend_cntl |= A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE;
2041
2042 const uint32_t sample_mask =
2043 msaa_info->pSampleMask ? *msaa_info->pSampleMask
2044 : ((1 << msaa_info->rasterizationSamples) - 1);
2045
2046 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
2047 uint32_t rb_blend_cntl =
2048 A6XX_RB_BLEND_CNTL_ENABLE_BLEND(blend_enable_mask) |
2049 A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND |
2050 A6XX_RB_BLEND_CNTL_SAMPLE_MASK(sample_mask);
2051 if (msaa_info->alphaToCoverageEnable)
2052 rb_blend_cntl |= A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE;
2053
2054 tu_cs_emit_pkt4(cs, REG_A6XX_SP_BLEND_CNTL, 1);
2055 tu_cs_emit(cs, sp_blend_cntl);
2056
2057 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_CNTL, 1);
2058 tu_cs_emit(cs, rb_blend_cntl);
2059 }
2060
2061 void
2062 tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4])
2063 {
2064 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_RED_F32, 4);
2065 tu_cs_emit_array(cs, (const uint32_t *) constants, 4);
2066 }
2067
2068 static VkResult
2069 tu_pipeline_create(struct tu_device *dev,
2070 struct tu_pipeline_layout *layout,
2071 bool compute,
2072 const VkAllocationCallbacks *pAllocator,
2073 struct tu_pipeline **out_pipeline)
2074 {
2075 struct tu_pipeline *pipeline =
2076 vk_zalloc2(&dev->alloc, pAllocator, sizeof(*pipeline), 8,
2077 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2078 if (!pipeline)
2079 return VK_ERROR_OUT_OF_HOST_MEMORY;
2080
2081 tu_cs_init(&pipeline->cs, dev, TU_CS_MODE_SUB_STREAM, 2048);
2082
2083 /* Reserve the space now such that tu_cs_begin_sub_stream never fails. Note
2084 * that LOAD_STATE can potentially take up a large amount of space so we
2085 * calculate its size explicitly.
2086 */
2087 unsigned load_state_size = tu6_load_state_size(layout, compute);
2088 VkResult result = tu_cs_reserve_space(&pipeline->cs, 2048 + load_state_size);
2089 if (result != VK_SUCCESS) {
2090 vk_free2(&dev->alloc, pAllocator, pipeline);
2091 return result;
2092 }
2093
2094 *out_pipeline = pipeline;
2095
2096 return VK_SUCCESS;
2097 }
2098
2099 static VkResult
2100 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder)
2101 {
2102 const VkPipelineShaderStageCreateInfo *stage_infos[MESA_SHADER_STAGES] = {
2103 NULL
2104 };
2105 for (uint32_t i = 0; i < builder->create_info->stageCount; i++) {
2106 gl_shader_stage stage =
2107 tu_shader_stage(builder->create_info->pStages[i].stage);
2108 stage_infos[stage] = &builder->create_info->pStages[i];
2109 }
2110
2111 struct tu_shader_compile_options options;
2112 tu_shader_compile_options_init(&options, builder->create_info);
2113
2114 /* compile shaders in reverse order */
2115 struct tu_shader *next_stage_shader = NULL;
2116 for (gl_shader_stage stage = MESA_SHADER_STAGES - 1;
2117 stage > MESA_SHADER_NONE; stage--) {
2118 const VkPipelineShaderStageCreateInfo *stage_info = stage_infos[stage];
2119 if (!stage_info)
2120 continue;
2121
2122 struct tu_shader *shader =
2123 tu_shader_create(builder->device, stage, stage_info, builder->layout,
2124 builder->alloc);
2125 if (!shader)
2126 return VK_ERROR_OUT_OF_HOST_MEMORY;
2127
2128 VkResult result =
2129 tu_shader_compile(builder->device, shader, next_stage_shader,
2130 &options, builder->alloc);
2131 if (result != VK_SUCCESS)
2132 return result;
2133
2134 builder->shaders[stage] = shader;
2135 builder->shader_offsets[stage] = builder->shader_total_size;
2136 builder->shader_total_size +=
2137 sizeof(uint32_t) * shader->variants[0].info.sizedwords;
2138
2139 next_stage_shader = shader;
2140 }
2141
2142 if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
2143 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
2144 const struct ir3_shader_variant *variant;
2145
2146 if (vs->ir3_shader.stream_output.num_outputs)
2147 variant = &vs->variants[0];
2148 else
2149 variant = &vs->variants[1];
2150
2151 builder->binning_vs_offset = builder->shader_total_size;
2152 builder->shader_total_size +=
2153 sizeof(uint32_t) * variant->info.sizedwords;
2154 }
2155
2156 return VK_SUCCESS;
2157 }
2158
2159 static VkResult
2160 tu_pipeline_builder_upload_shaders(struct tu_pipeline_builder *builder,
2161 struct tu_pipeline *pipeline)
2162 {
2163 struct tu_bo *bo = &pipeline->program.binary_bo;
2164
2165 VkResult result =
2166 tu_bo_init_new(builder->device, bo, builder->shader_total_size);
2167 if (result != VK_SUCCESS)
2168 return result;
2169
2170 result = tu_bo_map(builder->device, bo);
2171 if (result != VK_SUCCESS)
2172 return result;
2173
2174 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
2175 const struct tu_shader *shader = builder->shaders[i];
2176 if (!shader)
2177 continue;
2178
2179 memcpy(bo->map + builder->shader_offsets[i], shader->binary,
2180 sizeof(uint32_t) * shader->variants[0].info.sizedwords);
2181 }
2182
2183 if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
2184 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
2185 const struct ir3_shader_variant *variant;
2186 void *bin;
2187
2188 if (vs->ir3_shader.stream_output.num_outputs) {
2189 variant = &vs->variants[0];
2190 bin = vs->binary;
2191 } else {
2192 variant = &vs->variants[1];
2193 bin = vs->binning_binary;
2194 }
2195
2196 memcpy(bo->map + builder->binning_vs_offset, bin,
2197 sizeof(uint32_t) * variant->info.sizedwords);
2198 }
2199
2200 return VK_SUCCESS;
2201 }
2202
2203 static void
2204 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
2205 struct tu_pipeline *pipeline)
2206 {
2207 const VkPipelineDynamicStateCreateInfo *dynamic_info =
2208 builder->create_info->pDynamicState;
2209
2210 if (!dynamic_info)
2211 return;
2212
2213 for (uint32_t i = 0; i < dynamic_info->dynamicStateCount; i++) {
2214 pipeline->dynamic_state.mask |=
2215 tu_dynamic_state_bit(dynamic_info->pDynamicStates[i]);
2216 }
2217 }
2218
2219 static void
2220 tu_pipeline_set_linkage(struct tu_program_descriptor_linkage *link,
2221 struct tu_shader *shader,
2222 struct ir3_shader_variant *v)
2223 {
2224 link->ubo_state = v->shader->ubo_state;
2225 link->const_state = v->shader->const_state;
2226 link->constlen = v->constlen;
2227 link->push_consts = shader->push_consts;
2228 }
2229
2230 static void
2231 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder *builder,
2232 struct tu_pipeline *pipeline)
2233 {
2234 struct tu_cs prog_cs;
2235 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2236 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, false, &pipeline->streamout);
2237 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2238
2239 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2240 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, true, &pipeline->streamout);
2241 pipeline->program.binning_state_ib =
2242 tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2243
2244 VkShaderStageFlags stages = 0;
2245 for (unsigned i = 0; i < builder->create_info->stageCount; i++) {
2246 stages |= builder->create_info->pStages[i].stage;
2247 }
2248 pipeline->active_stages = stages;
2249
2250 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2251 if (!builder->shaders[i])
2252 continue;
2253
2254 tu_pipeline_set_linkage(&pipeline->program.link[i],
2255 builder->shaders[i],
2256 &builder->shaders[i]->variants[0]);
2257 }
2258
2259 if (builder->shaders[MESA_SHADER_FRAGMENT]) {
2260 memcpy(pipeline->program.input_attachment_idx,
2261 builder->shaders[MESA_SHADER_FRAGMENT]->attachment_idx,
2262 sizeof(pipeline->program.input_attachment_idx));
2263 }
2264 }
2265
2266 static void
2267 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder *builder,
2268 struct tu_pipeline *pipeline)
2269 {
2270 const VkPipelineVertexInputStateCreateInfo *vi_info =
2271 builder->create_info->pVertexInputState;
2272 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
2273
2274 struct tu_cs vi_cs;
2275 tu_cs_begin_sub_stream(&pipeline->cs,
2276 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
2277 tu6_emit_vertex_input(&vi_cs, &vs->variants[0], vi_info,
2278 pipeline->vi.bindings, &pipeline->vi.count);
2279 pipeline->vi.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
2280
2281 if (vs->has_binning_pass) {
2282 tu_cs_begin_sub_stream(&pipeline->cs,
2283 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
2284 tu6_emit_vertex_input(
2285 &vi_cs, &vs->variants[1], vi_info, pipeline->vi.binning_bindings,
2286 &pipeline->vi.binning_count);
2287 pipeline->vi.binning_state_ib =
2288 tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
2289 }
2290 }
2291
2292 static void
2293 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder *builder,
2294 struct tu_pipeline *pipeline)
2295 {
2296 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
2297 builder->create_info->pInputAssemblyState;
2298
2299 pipeline->ia.primtype = tu6_primtype(ia_info->topology);
2300 pipeline->ia.primitive_restart = ia_info->primitiveRestartEnable;
2301 }
2302
2303 static void
2304 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder *builder,
2305 struct tu_pipeline *pipeline)
2306 {
2307 /* The spec says:
2308 *
2309 * pViewportState is a pointer to an instance of the
2310 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
2311 * pipeline has rasterization disabled."
2312 *
2313 * We leave the relevant registers stale in that case.
2314 */
2315 if (builder->rasterizer_discard)
2316 return;
2317
2318 const VkPipelineViewportStateCreateInfo *vp_info =
2319 builder->create_info->pViewportState;
2320
2321 struct tu_cs vp_cs;
2322 tu_cs_begin_sub_stream(&pipeline->cs, 21, &vp_cs);
2323
2324 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_VIEWPORT)) {
2325 assert(vp_info->viewportCount == 1);
2326 tu6_emit_viewport(&vp_cs, vp_info->pViewports);
2327 }
2328
2329 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_SCISSOR)) {
2330 assert(vp_info->scissorCount == 1);
2331 tu6_emit_scissor(&vp_cs, vp_info->pScissors);
2332 }
2333
2334 pipeline->vp.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vp_cs);
2335 }
2336
2337 static void
2338 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder,
2339 struct tu_pipeline *pipeline)
2340 {
2341 const VkPipelineRasterizationStateCreateInfo *rast_info =
2342 builder->create_info->pRasterizationState;
2343
2344 assert(rast_info->polygonMode == VK_POLYGON_MODE_FILL);
2345
2346 struct tu_cs rast_cs;
2347 tu_cs_begin_sub_stream(&pipeline->cs, 20, &rast_cs);
2348
2349
2350 tu_cs_emit_regs(&rast_cs,
2351 A6XX_GRAS_CL_CNTL(
2352 .znear_clip_disable = rast_info->depthClampEnable,
2353 .zfar_clip_disable = rast_info->depthClampEnable,
2354 .unk5 = rast_info->depthClampEnable,
2355 .zero_gb_scale_z = 1,
2356 .vp_clip_code_ignore = 1));
2357 /* move to hw ctx init? */
2358 tu6_emit_gras_unknowns(&rast_cs);
2359 tu6_emit_point_size(&rast_cs);
2360
2361 const uint32_t gras_su_cntl =
2362 tu6_gras_su_cntl(rast_info, builder->samples);
2363
2364 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH))
2365 tu6_emit_gras_su_cntl(&rast_cs, gras_su_cntl, rast_info->lineWidth);
2366
2367 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_DEPTH_BIAS)) {
2368 tu6_emit_depth_bias(&rast_cs, rast_info->depthBiasConstantFactor,
2369 rast_info->depthBiasClamp,
2370 rast_info->depthBiasSlopeFactor);
2371 }
2372
2373 pipeline->rast.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &rast_cs);
2374
2375 pipeline->rast.gras_su_cntl = gras_su_cntl;
2376 }
2377
2378 static void
2379 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
2380 struct tu_pipeline *pipeline)
2381 {
2382 /* The spec says:
2383 *
2384 * pDepthStencilState is a pointer to an instance of the
2385 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
2386 * the pipeline has rasterization disabled or if the subpass of the
2387 * render pass the pipeline is created against does not use a
2388 * depth/stencil attachment.
2389 *
2390 * Disable both depth and stencil tests if there is no ds attachment,
2391 * Disable depth test if ds attachment is S8_UINT, since S8_UINT defines
2392 * only the separate stencil attachment
2393 */
2394 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info;
2395 const VkPipelineDepthStencilStateCreateInfo *ds_info =
2396 builder->depth_attachment_format != VK_FORMAT_UNDEFINED
2397 ? builder->create_info->pDepthStencilState
2398 : &dummy_ds_info;
2399 const VkPipelineDepthStencilStateCreateInfo *ds_info_depth =
2400 builder->depth_attachment_format != VK_FORMAT_S8_UINT
2401 ? ds_info : &dummy_ds_info;
2402
2403 struct tu_cs ds_cs;
2404 tu_cs_begin_sub_stream(&pipeline->cs, 12, &ds_cs);
2405
2406 /* move to hw ctx init? */
2407 tu6_emit_alpha_control_disable(&ds_cs);
2408
2409 tu6_emit_depth_control(&ds_cs, ds_info_depth,
2410 builder->create_info->pRasterizationState);
2411 tu6_emit_stencil_control(&ds_cs, ds_info);
2412
2413 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
2414 tu6_emit_stencil_compare_mask(&ds_cs, ds_info->front.compareMask,
2415 ds_info->back.compareMask);
2416 }
2417 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
2418 tu6_emit_stencil_write_mask(&ds_cs, ds_info->front.writeMask,
2419 ds_info->back.writeMask);
2420 }
2421 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
2422 tu6_emit_stencil_reference(&ds_cs, ds_info->front.reference,
2423 ds_info->back.reference);
2424 }
2425
2426 pipeline->ds.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &ds_cs);
2427 }
2428
2429 static void
2430 tu_pipeline_builder_parse_multisample_and_color_blend(
2431 struct tu_pipeline_builder *builder, struct tu_pipeline *pipeline)
2432 {
2433 /* The spec says:
2434 *
2435 * pMultisampleState is a pointer to an instance of the
2436 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
2437 * has rasterization disabled.
2438 *
2439 * Also,
2440 *
2441 * pColorBlendState is a pointer to an instance of the
2442 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
2443 * pipeline has rasterization disabled or if the subpass of the render
2444 * pass the pipeline is created against does not use any color
2445 * attachments.
2446 *
2447 * We leave the relevant registers stale when rasterization is disabled.
2448 */
2449 if (builder->rasterizer_discard)
2450 return;
2451
2452 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info;
2453 const VkPipelineMultisampleStateCreateInfo *msaa_info =
2454 builder->create_info->pMultisampleState;
2455 const VkPipelineColorBlendStateCreateInfo *blend_info =
2456 builder->use_color_attachments ? builder->create_info->pColorBlendState
2457 : &dummy_blend_info;
2458
2459 struct tu_cs blend_cs;
2460 tu_cs_begin_sub_stream(&pipeline->cs, MAX_RTS * 3 + 18, &blend_cs);
2461
2462 uint32_t blend_enable_mask;
2463 tu6_emit_rb_mrt_controls(&blend_cs, blend_info,
2464 builder->color_attachment_formats,
2465 &blend_enable_mask);
2466
2467 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_BLEND_CONSTANTS))
2468 tu6_emit_blend_constants(&blend_cs, blend_info->blendConstants);
2469
2470 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_SAMPLE_LOCATIONS)) {
2471 const struct VkPipelineSampleLocationsStateCreateInfoEXT *sample_locations =
2472 vk_find_struct_const(msaa_info->pNext, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
2473 const VkSampleLocationsInfoEXT *samp_loc = NULL;
2474
2475 if (sample_locations && sample_locations->sampleLocationsEnable)
2476 samp_loc = &sample_locations->sampleLocationsInfo;
2477
2478 tu6_emit_sample_locations(&blend_cs, samp_loc);
2479 }
2480
2481 tu6_emit_blend_control(&blend_cs, blend_enable_mask, msaa_info);
2482
2483 pipeline->blend.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &blend_cs);
2484 }
2485
2486 static void
2487 tu_pipeline_finish(struct tu_pipeline *pipeline,
2488 struct tu_device *dev,
2489 const VkAllocationCallbacks *alloc)
2490 {
2491 tu_cs_finish(&pipeline->cs);
2492
2493 if (pipeline->program.binary_bo.gem_handle)
2494 tu_bo_finish(dev, &pipeline->program.binary_bo);
2495 }
2496
2497 static VkResult
2498 tu_pipeline_builder_build(struct tu_pipeline_builder *builder,
2499 struct tu_pipeline **pipeline)
2500 {
2501 VkResult result = tu_pipeline_create(builder->device, builder->layout,
2502 false, builder->alloc, pipeline);
2503 if (result != VK_SUCCESS)
2504 return result;
2505
2506 (*pipeline)->layout = builder->layout;
2507
2508 /* compile and upload shaders */
2509 result = tu_pipeline_builder_compile_shaders(builder);
2510 if (result == VK_SUCCESS)
2511 result = tu_pipeline_builder_upload_shaders(builder, *pipeline);
2512 if (result != VK_SUCCESS) {
2513 tu_pipeline_finish(*pipeline, builder->device, builder->alloc);
2514 vk_free2(&builder->device->alloc, builder->alloc, *pipeline);
2515 *pipeline = VK_NULL_HANDLE;
2516
2517 return result;
2518 }
2519
2520 tu_pipeline_builder_parse_dynamic(builder, *pipeline);
2521 tu_pipeline_builder_parse_shader_stages(builder, *pipeline);
2522 tu_pipeline_builder_parse_vertex_input(builder, *pipeline);
2523 tu_pipeline_builder_parse_input_assembly(builder, *pipeline);
2524 tu_pipeline_builder_parse_viewport(builder, *pipeline);
2525 tu_pipeline_builder_parse_rasterization(builder, *pipeline);
2526 tu_pipeline_builder_parse_depth_stencil(builder, *pipeline);
2527 tu_pipeline_builder_parse_multisample_and_color_blend(builder, *pipeline);
2528 tu6_emit_load_state(*pipeline, false);
2529
2530 /* we should have reserved enough space upfront such that the CS never
2531 * grows
2532 */
2533 assert((*pipeline)->cs.bo_count == 1);
2534
2535 return VK_SUCCESS;
2536 }
2537
2538 static void
2539 tu_pipeline_builder_finish(struct tu_pipeline_builder *builder)
2540 {
2541 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
2542 if (!builder->shaders[i])
2543 continue;
2544 tu_shader_destroy(builder->device, builder->shaders[i], builder->alloc);
2545 }
2546 }
2547
2548 static void
2549 tu_pipeline_builder_init_graphics(
2550 struct tu_pipeline_builder *builder,
2551 struct tu_device *dev,
2552 struct tu_pipeline_cache *cache,
2553 const VkGraphicsPipelineCreateInfo *create_info,
2554 const VkAllocationCallbacks *alloc)
2555 {
2556 TU_FROM_HANDLE(tu_pipeline_layout, layout, create_info->layout);
2557
2558 *builder = (struct tu_pipeline_builder) {
2559 .device = dev,
2560 .cache = cache,
2561 .create_info = create_info,
2562 .alloc = alloc,
2563 .layout = layout,
2564 };
2565
2566 builder->rasterizer_discard =
2567 create_info->pRasterizationState->rasterizerDiscardEnable;
2568
2569 if (builder->rasterizer_discard) {
2570 builder->samples = VK_SAMPLE_COUNT_1_BIT;
2571 } else {
2572 builder->samples = create_info->pMultisampleState->rasterizationSamples;
2573
2574 const struct tu_render_pass *pass =
2575 tu_render_pass_from_handle(create_info->renderPass);
2576 const struct tu_subpass *subpass =
2577 &pass->subpasses[create_info->subpass];
2578
2579 const uint32_t a = subpass->depth_stencil_attachment.attachment;
2580 builder->depth_attachment_format = (a != VK_ATTACHMENT_UNUSED) ?
2581 pass->attachments[a].format : VK_FORMAT_UNDEFINED;
2582
2583 assert(subpass->color_count == 0 ||
2584 !create_info->pColorBlendState ||
2585 subpass->color_count == create_info->pColorBlendState->attachmentCount);
2586 builder->color_attachment_count = subpass->color_count;
2587 for (uint32_t i = 0; i < subpass->color_count; i++) {
2588 const uint32_t a = subpass->color_attachments[i].attachment;
2589 if (a == VK_ATTACHMENT_UNUSED)
2590 continue;
2591
2592 builder->color_attachment_formats[i] = pass->attachments[a].format;
2593 builder->use_color_attachments = true;
2594 }
2595 }
2596 }
2597
2598 static VkResult
2599 tu_graphics_pipeline_create(VkDevice device,
2600 VkPipelineCache pipelineCache,
2601 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2602 const VkAllocationCallbacks *pAllocator,
2603 VkPipeline *pPipeline)
2604 {
2605 TU_FROM_HANDLE(tu_device, dev, device);
2606 TU_FROM_HANDLE(tu_pipeline_cache, cache, pipelineCache);
2607
2608 struct tu_pipeline_builder builder;
2609 tu_pipeline_builder_init_graphics(&builder, dev, cache,
2610 pCreateInfo, pAllocator);
2611
2612 struct tu_pipeline *pipeline = NULL;
2613 VkResult result = tu_pipeline_builder_build(&builder, &pipeline);
2614 tu_pipeline_builder_finish(&builder);
2615
2616 if (result == VK_SUCCESS)
2617 *pPipeline = tu_pipeline_to_handle(pipeline);
2618 else
2619 *pPipeline = VK_NULL_HANDLE;
2620
2621 return result;
2622 }
2623
2624 VkResult
2625 tu_CreateGraphicsPipelines(VkDevice device,
2626 VkPipelineCache pipelineCache,
2627 uint32_t count,
2628 const VkGraphicsPipelineCreateInfo *pCreateInfos,
2629 const VkAllocationCallbacks *pAllocator,
2630 VkPipeline *pPipelines)
2631 {
2632 VkResult final_result = VK_SUCCESS;
2633
2634 for (uint32_t i = 0; i < count; i++) {
2635 VkResult result = tu_graphics_pipeline_create(device, pipelineCache,
2636 &pCreateInfos[i], pAllocator,
2637 &pPipelines[i]);
2638
2639 if (result != VK_SUCCESS)
2640 final_result = result;
2641 }
2642
2643 return final_result;
2644 }
2645
2646 static void
2647 tu6_emit_compute_program(struct tu_cs *cs,
2648 struct tu_shader *shader,
2649 const struct tu_bo *binary_bo)
2650 {
2651 const struct ir3_shader_variant *v = &shader->variants[0];
2652
2653 tu6_emit_cs_config(cs, shader, v);
2654
2655 /* The compute program is the only one in the pipeline, so 0 offset. */
2656 tu6_emit_shader_object(cs, MESA_SHADER_COMPUTE, v, binary_bo, 0);
2657
2658 tu6_emit_immediates(cs, v, CP_LOAD_STATE6_FRAG, SB6_CS_SHADER);
2659 }
2660
2661 static VkResult
2662 tu_compute_upload_shader(VkDevice device,
2663 struct tu_pipeline *pipeline,
2664 struct tu_shader *shader)
2665 {
2666 TU_FROM_HANDLE(tu_device, dev, device);
2667 struct tu_bo *bo = &pipeline->program.binary_bo;
2668 struct ir3_shader_variant *v = &shader->variants[0];
2669
2670 uint32_t shader_size = sizeof(uint32_t) * v->info.sizedwords;
2671 VkResult result =
2672 tu_bo_init_new(dev, bo, shader_size);
2673 if (result != VK_SUCCESS)
2674 return result;
2675
2676 result = tu_bo_map(dev, bo);
2677 if (result != VK_SUCCESS)
2678 return result;
2679
2680 memcpy(bo->map, shader->binary, shader_size);
2681
2682 return VK_SUCCESS;
2683 }
2684
2685
2686 static VkResult
2687 tu_compute_pipeline_create(VkDevice device,
2688 VkPipelineCache _cache,
2689 const VkComputePipelineCreateInfo *pCreateInfo,
2690 const VkAllocationCallbacks *pAllocator,
2691 VkPipeline *pPipeline)
2692 {
2693 TU_FROM_HANDLE(tu_device, dev, device);
2694 TU_FROM_HANDLE(tu_pipeline_layout, layout, pCreateInfo->layout);
2695 const VkPipelineShaderStageCreateInfo *stage_info = &pCreateInfo->stage;
2696 VkResult result;
2697
2698 struct tu_pipeline *pipeline;
2699
2700 *pPipeline = VK_NULL_HANDLE;
2701
2702 result = tu_pipeline_create(dev, layout, true, pAllocator, &pipeline);
2703 if (result != VK_SUCCESS)
2704 return result;
2705
2706 pipeline->layout = layout;
2707
2708 struct tu_shader_compile_options options;
2709 tu_shader_compile_options_init(&options, NULL);
2710
2711 struct tu_shader *shader =
2712 tu_shader_create(dev, MESA_SHADER_COMPUTE, stage_info, layout, pAllocator);
2713 if (!shader) {
2714 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2715 goto fail;
2716 }
2717
2718 result = tu_shader_compile(dev, shader, NULL, &options, pAllocator);
2719 if (result != VK_SUCCESS)
2720 goto fail;
2721
2722 struct ir3_shader_variant *v = &shader->variants[0];
2723
2724 tu_pipeline_set_linkage(&pipeline->program.link[MESA_SHADER_COMPUTE],
2725 shader, v);
2726
2727 result = tu_compute_upload_shader(device, pipeline, shader);
2728 if (result != VK_SUCCESS)
2729 goto fail;
2730
2731 for (int i = 0; i < 3; i++)
2732 pipeline->compute.local_size[i] = v->shader->nir->info.cs.local_size[i];
2733
2734 struct tu_cs prog_cs;
2735 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2736 tu6_emit_compute_program(&prog_cs, shader, &pipeline->program.binary_bo);
2737 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2738
2739 tu6_emit_load_state(pipeline, true);
2740
2741 *pPipeline = tu_pipeline_to_handle(pipeline);
2742 return VK_SUCCESS;
2743
2744 fail:
2745 if (shader)
2746 tu_shader_destroy(dev, shader, pAllocator);
2747
2748 tu_pipeline_finish(pipeline, dev, pAllocator);
2749 vk_free2(&dev->alloc, pAllocator, pipeline);
2750
2751 return result;
2752 }
2753
2754 VkResult
2755 tu_CreateComputePipelines(VkDevice device,
2756 VkPipelineCache pipelineCache,
2757 uint32_t count,
2758 const VkComputePipelineCreateInfo *pCreateInfos,
2759 const VkAllocationCallbacks *pAllocator,
2760 VkPipeline *pPipelines)
2761 {
2762 VkResult final_result = VK_SUCCESS;
2763
2764 for (uint32_t i = 0; i < count; i++) {
2765 VkResult result = tu_compute_pipeline_create(device, pipelineCache,
2766 &pCreateInfos[i],
2767 pAllocator, &pPipelines[i]);
2768 if (result != VK_SUCCESS)
2769 final_result = result;
2770 }
2771
2772 return final_result;
2773 }
2774
2775 void
2776 tu_DestroyPipeline(VkDevice _device,
2777 VkPipeline _pipeline,
2778 const VkAllocationCallbacks *pAllocator)
2779 {
2780 TU_FROM_HANDLE(tu_device, dev, _device);
2781 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
2782
2783 if (!_pipeline)
2784 return;
2785
2786 tu_pipeline_finish(pipeline, dev, pAllocator);
2787 vk_free2(&dev->alloc, pAllocator, pipeline);
2788 }