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freedreno/a6xx: Add multiview registers
[mesa.git] / src / freedreno / vulkan / tu_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "common/freedreno_guardband.h"
29 #include "tu_private.h"
30
31 #include "ir3/ir3_nir.h"
32 #include "main/menums.h"
33 #include "nir/nir.h"
34 #include "nir/nir_builder.h"
35 #include "spirv/nir_spirv.h"
36 #include "util/debug.h"
37 #include "util/mesa-sha1.h"
38 #include "util/u_atomic.h"
39 #include "vk_format.h"
40 #include "vk_util.h"
41
42 #include "tu_cs.h"
43
44 /* Emit IB that preloads the descriptors that the shader uses */
45
46 static void
47 emit_load_state(struct tu_cs *cs, unsigned opcode, enum a6xx_state_type st,
48 enum a6xx_state_block sb, unsigned base, unsigned offset,
49 unsigned count)
50 {
51 /* Note: just emit one packet, even if count overflows NUM_UNIT. It's not
52 * clear if emitting more packets will even help anything. Presumably the
53 * descriptor cache is relatively small, and these packets stop doing
54 * anything when there are too many descriptors.
55 */
56 tu_cs_emit_pkt7(cs, opcode, 3);
57 tu_cs_emit(cs,
58 CP_LOAD_STATE6_0_STATE_TYPE(st) |
59 CP_LOAD_STATE6_0_STATE_SRC(SS6_BINDLESS) |
60 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
61 CP_LOAD_STATE6_0_NUM_UNIT(MIN2(count, 1024-1)));
62 tu_cs_emit_qw(cs, offset | (base << 28));
63 }
64
65 static unsigned
66 tu6_load_state_size(struct tu_pipeline *pipeline, bool compute)
67 {
68 const unsigned load_state_size = 4;
69 unsigned size = 0;
70 for (unsigned i = 0; i < pipeline->layout->num_sets; i++) {
71 if (pipeline && !(pipeline->active_desc_sets & (1u << i)))
72 continue;
73
74 struct tu_descriptor_set_layout *set_layout = pipeline->layout->set[i].layout;
75 for (unsigned j = 0; j < set_layout->binding_count; j++) {
76 struct tu_descriptor_set_binding_layout *binding = &set_layout->binding[j];
77 unsigned count = 0;
78 /* Note: some users, like amber for example, pass in
79 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
80 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
81 */
82 VkShaderStageFlags stages = compute ?
83 binding->shader_stages & VK_SHADER_STAGE_COMPUTE_BIT :
84 binding->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
85 unsigned stage_count = util_bitcount(stages);
86
87 if (!binding->array_size)
88 continue;
89
90 switch (binding->type) {
91 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
92 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
93 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
94 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
95 /* IBO-backed resources only need one packet for all graphics stages */
96 if (stages & ~VK_SHADER_STAGE_COMPUTE_BIT)
97 count += 1;
98 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
99 count += 1;
100 break;
101 case VK_DESCRIPTOR_TYPE_SAMPLER:
102 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
103 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
104 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
105 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
106 /* Textures and UBO's needs a packet for each stage */
107 count = stage_count;
108 break;
109 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
110 /* Because of how we pack combined images and samplers, we
111 * currently can't use one packet for the whole array.
112 */
113 count = stage_count * binding->array_size * 2;
114 break;
115 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
116 break;
117 default:
118 unreachable("bad descriptor type");
119 }
120 size += count * load_state_size;
121 }
122 }
123 return size;
124 }
125
126 static void
127 tu6_emit_load_state(struct tu_pipeline *pipeline, bool compute)
128 {
129 unsigned size = tu6_load_state_size(pipeline, compute);
130 if (size == 0)
131 return;
132
133 struct tu_cs cs;
134 tu_cs_begin_sub_stream(&pipeline->cs, size, &cs);
135
136 struct tu_pipeline_layout *layout = pipeline->layout;
137 for (unsigned i = 0; i < layout->num_sets; i++) {
138 /* From 13.2.7. Descriptor Set Binding:
139 *
140 * A compatible descriptor set must be bound for all set numbers that
141 * any shaders in a pipeline access, at the time that a draw or
142 * dispatch command is recorded to execute using that pipeline.
143 * However, if none of the shaders in a pipeline statically use any
144 * bindings with a particular set number, then no descriptor set need
145 * be bound for that set number, even if the pipeline layout includes
146 * a non-trivial descriptor set layout for that set number.
147 *
148 * This means that descriptor sets unused by the pipeline may have a
149 * garbage or 0 BINDLESS_BASE register, which will cause context faults
150 * when prefetching descriptors from these sets. Skip prefetching for
151 * descriptors from them to avoid this. This is also an optimization,
152 * since these prefetches would be useless.
153 */
154 if (!(pipeline->active_desc_sets & (1u << i)))
155 continue;
156
157 struct tu_descriptor_set_layout *set_layout = layout->set[i].layout;
158 for (unsigned j = 0; j < set_layout->binding_count; j++) {
159 struct tu_descriptor_set_binding_layout *binding = &set_layout->binding[j];
160 unsigned base = i;
161 unsigned offset = binding->offset / 4;
162 /* Note: some users, like amber for example, pass in
163 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
164 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
165 */
166 VkShaderStageFlags stages = compute ?
167 binding->shader_stages & VK_SHADER_STAGE_COMPUTE_BIT :
168 binding->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
169 unsigned count = binding->array_size;
170 if (count == 0 || stages == 0)
171 continue;
172 switch (binding->type) {
173 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
174 base = MAX_SETS;
175 offset = (layout->set[i].dynamic_offset_start +
176 binding->dynamic_offset_offset) * A6XX_TEX_CONST_DWORDS;
177 /* fallthrough */
178 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
179 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
180 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
181 /* IBO-backed resources only need one packet for all graphics stages */
182 if (stages & ~VK_SHADER_STAGE_COMPUTE_BIT) {
183 emit_load_state(&cs, CP_LOAD_STATE6, ST6_SHADER, SB6_IBO,
184 base, offset, count);
185 }
186 if (stages & VK_SHADER_STAGE_COMPUTE_BIT) {
187 emit_load_state(&cs, CP_LOAD_STATE6_FRAG, ST6_IBO, SB6_CS_SHADER,
188 base, offset, count);
189 }
190 break;
191 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
192 /* nothing - input attachment doesn't use bindless */
193 break;
194 case VK_DESCRIPTOR_TYPE_SAMPLER:
195 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
196 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER: {
197 tu_foreach_stage(stage, stages) {
198 emit_load_state(&cs, tu6_stage2opcode(stage),
199 binding->type == VK_DESCRIPTOR_TYPE_SAMPLER ?
200 ST6_SHADER : ST6_CONSTANTS,
201 tu6_stage2texsb(stage), base, offset, count);
202 }
203 break;
204 }
205 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
206 base = MAX_SETS;
207 offset = (layout->set[i].dynamic_offset_start +
208 binding->dynamic_offset_offset) * A6XX_TEX_CONST_DWORDS;
209 /* fallthrough */
210 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER: {
211 tu_foreach_stage(stage, stages) {
212 emit_load_state(&cs, tu6_stage2opcode(stage), ST6_UBO,
213 tu6_stage2shadersb(stage), base, offset, count);
214 }
215 break;
216 }
217 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER: {
218 tu_foreach_stage(stage, stages) {
219 /* TODO: We could emit less CP_LOAD_STATE6 if we used
220 * struct-of-arrays instead of array-of-structs.
221 */
222 for (unsigned i = 0; i < count; i++) {
223 unsigned tex_offset = offset + 2 * i * A6XX_TEX_CONST_DWORDS;
224 unsigned sam_offset = offset + (2 * i + 1) * A6XX_TEX_CONST_DWORDS;
225 emit_load_state(&cs, tu6_stage2opcode(stage),
226 ST6_CONSTANTS, tu6_stage2texsb(stage),
227 base, tex_offset, 1);
228 emit_load_state(&cs, tu6_stage2opcode(stage),
229 ST6_SHADER, tu6_stage2texsb(stage),
230 base, sam_offset, 1);
231 }
232 }
233 break;
234 }
235 default:
236 unreachable("bad descriptor type");
237 }
238 }
239 }
240
241 pipeline->load_state = tu_cs_end_draw_state(&pipeline->cs, &cs);
242 }
243
244 struct tu_pipeline_builder
245 {
246 struct tu_device *device;
247 struct tu_pipeline_cache *cache;
248 struct tu_pipeline_layout *layout;
249 const VkAllocationCallbacks *alloc;
250 const VkGraphicsPipelineCreateInfo *create_info;
251
252 struct tu_shader *shaders[MESA_SHADER_STAGES];
253 struct ir3_shader_variant *variants[MESA_SHADER_STAGES];
254 struct ir3_shader_variant *binning_variant;
255 uint64_t shader_iova[MESA_SHADER_STAGES];
256 uint64_t binning_vs_iova;
257
258 bool rasterizer_discard;
259 /* these states are affectd by rasterizer_discard */
260 VkSampleCountFlagBits samples;
261 bool use_color_attachments;
262 bool use_dual_src_blend;
263 uint32_t color_attachment_count;
264 VkFormat color_attachment_formats[MAX_RTS];
265 VkFormat depth_attachment_format;
266 uint32_t render_components;
267 };
268
269 static bool
270 tu_logic_op_reads_dst(VkLogicOp op)
271 {
272 switch (op) {
273 case VK_LOGIC_OP_CLEAR:
274 case VK_LOGIC_OP_COPY:
275 case VK_LOGIC_OP_COPY_INVERTED:
276 case VK_LOGIC_OP_SET:
277 return false;
278 default:
279 return true;
280 }
281 }
282
283 static VkBlendFactor
284 tu_blend_factor_no_dst_alpha(VkBlendFactor factor)
285 {
286 /* treat dst alpha as 1.0 and avoid reading it */
287 switch (factor) {
288 case VK_BLEND_FACTOR_DST_ALPHA:
289 return VK_BLEND_FACTOR_ONE;
290 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
291 return VK_BLEND_FACTOR_ZERO;
292 default:
293 return factor;
294 }
295 }
296
297 static bool tu_blend_factor_is_dual_src(VkBlendFactor factor)
298 {
299 switch (factor) {
300 case VK_BLEND_FACTOR_SRC1_COLOR:
301 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
302 case VK_BLEND_FACTOR_SRC1_ALPHA:
303 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
304 return true;
305 default:
306 return false;
307 }
308 }
309
310 static bool
311 tu_blend_state_is_dual_src(const VkPipelineColorBlendStateCreateInfo *info)
312 {
313 if (!info)
314 return false;
315
316 for (unsigned i = 0; i < info->attachmentCount; i++) {
317 const VkPipelineColorBlendAttachmentState *blend = &info->pAttachments[i];
318 if (tu_blend_factor_is_dual_src(blend->srcColorBlendFactor) ||
319 tu_blend_factor_is_dual_src(blend->dstColorBlendFactor) ||
320 tu_blend_factor_is_dual_src(blend->srcAlphaBlendFactor) ||
321 tu_blend_factor_is_dual_src(blend->dstAlphaBlendFactor))
322 return true;
323 }
324
325 return false;
326 }
327
328 void
329 tu6_emit_xs_config(struct tu_cs *cs,
330 gl_shader_stage stage, /* xs->type, but xs may be NULL */
331 const struct ir3_shader_variant *xs,
332 uint64_t binary_iova)
333 {
334 static const struct xs_config {
335 uint16_t reg_sp_xs_ctrl;
336 uint16_t reg_sp_xs_config;
337 uint16_t reg_hlsq_xs_ctrl;
338 uint16_t reg_sp_vs_obj_start;
339 } xs_config[] = {
340 [MESA_SHADER_VERTEX] = {
341 REG_A6XX_SP_VS_CTRL_REG0,
342 REG_A6XX_SP_VS_CONFIG,
343 REG_A6XX_HLSQ_VS_CNTL,
344 REG_A6XX_SP_VS_OBJ_START_LO,
345 },
346 [MESA_SHADER_TESS_CTRL] = {
347 REG_A6XX_SP_HS_CTRL_REG0,
348 REG_A6XX_SP_HS_CONFIG,
349 REG_A6XX_HLSQ_HS_CNTL,
350 REG_A6XX_SP_HS_OBJ_START_LO,
351 },
352 [MESA_SHADER_TESS_EVAL] = {
353 REG_A6XX_SP_DS_CTRL_REG0,
354 REG_A6XX_SP_DS_CONFIG,
355 REG_A6XX_HLSQ_DS_CNTL,
356 REG_A6XX_SP_DS_OBJ_START_LO,
357 },
358 [MESA_SHADER_GEOMETRY] = {
359 REG_A6XX_SP_GS_CTRL_REG0,
360 REG_A6XX_SP_GS_CONFIG,
361 REG_A6XX_HLSQ_GS_CNTL,
362 REG_A6XX_SP_GS_OBJ_START_LO,
363 },
364 [MESA_SHADER_FRAGMENT] = {
365 REG_A6XX_SP_FS_CTRL_REG0,
366 REG_A6XX_SP_FS_CONFIG,
367 REG_A6XX_HLSQ_FS_CNTL,
368 REG_A6XX_SP_FS_OBJ_START_LO,
369 },
370 [MESA_SHADER_COMPUTE] = {
371 REG_A6XX_SP_CS_CTRL_REG0,
372 REG_A6XX_SP_CS_CONFIG,
373 REG_A6XX_HLSQ_CS_CNTL,
374 REG_A6XX_SP_CS_OBJ_START_LO,
375 },
376 };
377 const struct xs_config *cfg = &xs_config[stage];
378
379 if (!xs) {
380 /* shader stage disabled */
381 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_config, 1);
382 tu_cs_emit(cs, 0);
383
384 tu_cs_emit_pkt4(cs, cfg->reg_hlsq_xs_ctrl, 1);
385 tu_cs_emit(cs, 0);
386 return;
387 }
388
389 bool is_fs = xs->type == MESA_SHADER_FRAGMENT;
390 enum a3xx_threadsize threadsize = FOUR_QUADS;
391
392 /* TODO:
393 * the "threadsize" field may have nothing to do with threadsize,
394 * use a value that matches the blob until it is figured out
395 */
396 if (xs->type == MESA_SHADER_GEOMETRY)
397 threadsize = TWO_QUADS;
398
399 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_ctrl, 1);
400 tu_cs_emit(cs,
401 A6XX_SP_VS_CTRL_REG0_THREADSIZE(threadsize) |
402 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(xs->info.max_reg + 1) |
403 A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(xs->info.max_half_reg + 1) |
404 COND(xs->mergedregs, A6XX_SP_VS_CTRL_REG0_MERGEDREGS) |
405 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(xs->branchstack) |
406 COND(xs->need_pixlod, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE) |
407 COND(xs->need_fine_derivatives, A6XX_SP_VS_CTRL_REG0_DIFF_FINE) |
408 /* only fragment shader sets VARYING bit */
409 COND(xs->total_in && is_fs, A6XX_SP_FS_CTRL_REG0_VARYING) |
410 /* unknown bit, seems unnecessary */
411 COND(is_fs, 0x1000000));
412
413 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_config, 2);
414 tu_cs_emit(cs, A6XX_SP_VS_CONFIG_ENABLED |
415 COND(xs->bindless_tex, A6XX_SP_VS_CONFIG_BINDLESS_TEX) |
416 COND(xs->bindless_samp, A6XX_SP_VS_CONFIG_BINDLESS_SAMP) |
417 COND(xs->bindless_ibo, A6XX_SP_VS_CONFIG_BINDLESS_IBO) |
418 COND(xs->bindless_ubo, A6XX_SP_VS_CONFIG_BINDLESS_UBO) |
419 A6XX_SP_VS_CONFIG_NTEX(xs->num_samp) |
420 A6XX_SP_VS_CONFIG_NSAMP(xs->num_samp));
421 tu_cs_emit(cs, xs->instrlen);
422
423 tu_cs_emit_pkt4(cs, cfg->reg_hlsq_xs_ctrl, 1);
424 tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(xs->constlen) |
425 A6XX_HLSQ_VS_CNTL_ENABLED);
426
427 /* emit program binary
428 * binary_iova should be aligned to 1 instrlen unit (128 bytes)
429 */
430
431 assert((binary_iova & 0x7f) == 0);
432
433 tu_cs_emit_pkt4(cs, cfg->reg_sp_vs_obj_start, 2);
434 tu_cs_emit_qw(cs, binary_iova);
435
436 tu_cs_emit_pkt7(cs, tu6_stage2opcode(stage), 3);
437 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
438 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
439 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
440 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(stage)) |
441 CP_LOAD_STATE6_0_NUM_UNIT(xs->instrlen));
442 tu_cs_emit_qw(cs, binary_iova);
443
444 /* emit immediates */
445
446 const struct ir3_const_state *const_state = ir3_const_state(xs);
447 uint32_t base = const_state->offsets.immediate;
448 int size = DIV_ROUND_UP(const_state->immediates_count, 4);
449
450 /* truncate size to avoid writing constants that shader
451 * does not use:
452 */
453 size = MIN2(size + base, xs->constlen) - base;
454
455 if (size <= 0)
456 return;
457
458 tu_cs_emit_pkt7(cs, tu6_stage2opcode(stage), 3 + size * 4);
459 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
460 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
461 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
462 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(stage)) |
463 CP_LOAD_STATE6_0_NUM_UNIT(size));
464 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
465 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
466
467 tu_cs_emit_array(cs, const_state->immediates, size * 4);
468 }
469
470 static void
471 tu6_emit_cs_config(struct tu_cs *cs, const struct tu_shader *shader,
472 const struct ir3_shader_variant *v,
473 uint32_t binary_iova)
474 {
475 tu_cs_emit_regs(cs, A6XX_HLSQ_INVALIDATE_CMD(
476 .cs_state = true,
477 .cs_ibo = true));
478
479 tu6_emit_xs_config(cs, MESA_SHADER_COMPUTE, v, binary_iova);
480
481 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_UNKNOWN_A9B1, 1);
482 tu_cs_emit(cs, 0x41);
483
484 uint32_t local_invocation_id =
485 ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
486 uint32_t work_group_id =
487 ir3_find_sysval_regid(v, SYSTEM_VALUE_WORK_GROUP_ID);
488
489 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL_0, 2);
490 tu_cs_emit(cs,
491 A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) |
492 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
493 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
494 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
495 tu_cs_emit(cs, 0x2fc); /* HLSQ_CS_UNKNOWN_B998 */
496 }
497
498 static void
499 tu6_emit_vs_system_values(struct tu_cs *cs,
500 const struct ir3_shader_variant *vs,
501 const struct ir3_shader_variant *hs,
502 const struct ir3_shader_variant *ds,
503 const struct ir3_shader_variant *gs,
504 bool primid_passthru)
505 {
506 const uint32_t vertexid_regid =
507 ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
508 const uint32_t instanceid_regid =
509 ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
510 const uint32_t tess_coord_x_regid = hs ?
511 ir3_find_sysval_regid(ds, SYSTEM_VALUE_TESS_COORD) :
512 regid(63, 0);
513 const uint32_t tess_coord_y_regid = VALIDREG(tess_coord_x_regid) ?
514 tess_coord_x_regid + 1 :
515 regid(63, 0);
516 const uint32_t hs_patch_regid = hs ?
517 ir3_find_sysval_regid(hs, SYSTEM_VALUE_PRIMITIVE_ID) :
518 regid(63, 0);
519 const uint32_t ds_patch_regid = hs ?
520 ir3_find_sysval_regid(ds, SYSTEM_VALUE_PRIMITIVE_ID) :
521 regid(63, 0);
522 const uint32_t hs_invocation_regid = hs ?
523 ir3_find_sysval_regid(hs, SYSTEM_VALUE_TCS_HEADER_IR3) :
524 regid(63, 0);
525 const uint32_t primitiveid_regid = gs ?
526 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID) :
527 regid(63, 0);
528 const uint32_t gsheader_regid = gs ?
529 ir3_find_sysval_regid(gs, SYSTEM_VALUE_GS_HEADER_IR3) :
530 regid(63, 0);
531
532 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_1, 6);
533 tu_cs_emit(cs, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid) |
534 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid) |
535 A6XX_VFD_CONTROL_1_REGID4PRIMID(primitiveid_regid) |
536 0xfc000000);
537 tu_cs_emit(cs, A6XX_VFD_CONTROL_2_REGID_HSPATCHID(hs_patch_regid) |
538 A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(hs_invocation_regid));
539 tu_cs_emit(cs, A6XX_VFD_CONTROL_3_REGID_DSPATCHID(ds_patch_regid) |
540 A6XX_VFD_CONTROL_3_REGID_TESSX(tess_coord_x_regid) |
541 A6XX_VFD_CONTROL_3_REGID_TESSY(tess_coord_y_regid) |
542 0xfc);
543 tu_cs_emit(cs, 0x000000fc); /* VFD_CONTROL_4 */
544 tu_cs_emit(cs, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gsheader_regid) |
545 0xfc00); /* VFD_CONTROL_5 */
546 tu_cs_emit(cs, COND(primid_passthru, A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU)); /* VFD_CONTROL_6 */
547 }
548
549 /* Add any missing varyings needed for stream-out. Otherwise varyings not
550 * used by fragment shader will be stripped out.
551 */
552 static void
553 tu6_link_streamout(struct ir3_shader_linkage *l,
554 const struct ir3_shader_variant *v)
555 {
556 const struct ir3_stream_output_info *info = &v->shader->stream_output;
557
558 /*
559 * First, any stream-out varyings not already in linkage map (ie. also
560 * consumed by frag shader) need to be added:
561 */
562 for (unsigned i = 0; i < info->num_outputs; i++) {
563 const struct ir3_stream_output *out = &info->output[i];
564 unsigned compmask =
565 (1 << (out->num_components + out->start_component)) - 1;
566 unsigned k = out->register_index;
567 unsigned idx, nextloc = 0;
568
569 /* psize/pos need to be the last entries in linkage map, and will
570 * get added link_stream_out, so skip over them:
571 */
572 if (v->outputs[k].slot == VARYING_SLOT_PSIZ ||
573 v->outputs[k].slot == VARYING_SLOT_POS)
574 continue;
575
576 for (idx = 0; idx < l->cnt; idx++) {
577 if (l->var[idx].regid == v->outputs[k].regid)
578 break;
579 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
580 }
581
582 /* add if not already in linkage map: */
583 if (idx == l->cnt)
584 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
585
586 /* expand component-mask if needed, ie streaming out all components
587 * but frag shader doesn't consume all components:
588 */
589 if (compmask & ~l->var[idx].compmask) {
590 l->var[idx].compmask |= compmask;
591 l->max_loc = MAX2(l->max_loc, l->var[idx].loc +
592 util_last_bit(l->var[idx].compmask));
593 }
594 }
595 }
596
597 static void
598 tu6_setup_streamout(struct tu_cs *cs,
599 const struct ir3_shader_variant *v,
600 struct ir3_shader_linkage *l)
601 {
602 const struct ir3_stream_output_info *info = &v->shader->stream_output;
603 uint32_t prog[IR3_MAX_SO_OUTPUTS * 2] = {};
604 uint32_t ncomp[IR3_MAX_SO_BUFFERS] = {};
605 uint32_t prog_count = align(l->max_loc, 2) / 2;
606
607 /* TODO: streamout state should be in a non-GMEM draw state */
608
609 /* no streamout: */
610 if (info->num_outputs == 0) {
611 tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 4);
612 tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
613 tu_cs_emit(cs, 0);
614 tu_cs_emit(cs, REG_A6XX_VPC_SO_BUF_CNTL);
615 tu_cs_emit(cs, 0);
616 return;
617 }
618
619 /* is there something to do with info->stride[i]? */
620
621 for (unsigned i = 0; i < info->num_outputs; i++) {
622 const struct ir3_stream_output *out = &info->output[i];
623 unsigned k = out->register_index;
624 unsigned idx;
625
626 /* Skip it, if there's an unused reg in the middle of outputs. */
627 if (v->outputs[k].regid == INVALID_REG)
628 continue;
629
630 ncomp[out->output_buffer] += out->num_components;
631
632 /* linkage map sorted by order frag shader wants things, so
633 * a bit less ideal here..
634 */
635 for (idx = 0; idx < l->cnt; idx++)
636 if (l->var[idx].regid == v->outputs[k].regid)
637 break;
638
639 debug_assert(idx < l->cnt);
640
641 for (unsigned j = 0; j < out->num_components; j++) {
642 unsigned c = j + out->start_component;
643 unsigned loc = l->var[idx].loc + c;
644 unsigned off = j + out->dst_offset; /* in dwords */
645
646 if (loc & 1) {
647 prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
648 A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
649 A6XX_VPC_SO_PROG_B_OFF(off * 4);
650 } else {
651 prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
652 A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
653 A6XX_VPC_SO_PROG_A_OFF(off * 4);
654 }
655 }
656 }
657
658 tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 12 + 2 * prog_count);
659 tu_cs_emit(cs, REG_A6XX_VPC_SO_BUF_CNTL);
660 tu_cs_emit(cs, A6XX_VPC_SO_BUF_CNTL_ENABLE |
661 COND(ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
662 COND(ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
663 COND(ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
664 COND(ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3));
665 for (uint32_t i = 0; i < 4; i++) {
666 tu_cs_emit(cs, REG_A6XX_VPC_SO_NCOMP(i));
667 tu_cs_emit(cs, ncomp[i]);
668 }
669 /* note: "VPC_SO_CNTL" write seems to be responsible for resetting the SO_PROG */
670 tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
671 tu_cs_emit(cs, A6XX_VPC_SO_CNTL_ENABLE);
672 for (uint32_t i = 0; i < prog_count; i++) {
673 tu_cs_emit(cs, REG_A6XX_VPC_SO_PROG);
674 tu_cs_emit(cs, prog[i]);
675 }
676 }
677
678 static void
679 tu6_emit_const(struct tu_cs *cs, uint32_t opcode, uint32_t base,
680 enum a6xx_state_block block, uint32_t offset,
681 uint32_t size, uint32_t *dwords) {
682 assert(size % 4 == 0);
683
684 tu_cs_emit_pkt7(cs, opcode, 3 + size);
685 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
686 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
687 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
688 CP_LOAD_STATE6_0_STATE_BLOCK(block) |
689 CP_LOAD_STATE6_0_NUM_UNIT(size / 4));
690
691 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
692 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
693 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
694
695 tu_cs_emit_array(cs, dwords, size);
696 }
697
698 static void
699 tu6_emit_link_map(struct tu_cs *cs,
700 const struct ir3_shader_variant *producer,
701 const struct ir3_shader_variant *consumer,
702 enum a6xx_state_block sb)
703 {
704 const struct ir3_const_state *const_state = ir3_const_state(consumer);
705 uint32_t base = const_state->offsets.primitive_map;
706 uint32_t patch_locs[MAX_VARYING] = { }, num_loc;
707 num_loc = ir3_link_geometry_stages(producer, consumer, patch_locs);
708 int size = DIV_ROUND_UP(num_loc, 4);
709
710 size = (MIN2(size + base, consumer->constlen) - base) * 4;
711 if (size <= 0)
712 return;
713
714 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, base, sb, 0, size,
715 patch_locs);
716 }
717
718 static uint16_t
719 gl_primitive_to_tess(uint16_t primitive) {
720 switch (primitive) {
721 case GL_POINTS:
722 return TESS_POINTS;
723 case GL_LINE_STRIP:
724 return TESS_LINES;
725 case GL_TRIANGLE_STRIP:
726 return TESS_CW_TRIS;
727 default:
728 unreachable("");
729 }
730 }
731
732 void
733 tu6_emit_vpc(struct tu_cs *cs,
734 const struct ir3_shader_variant *vs,
735 const struct ir3_shader_variant *hs,
736 const struct ir3_shader_variant *ds,
737 const struct ir3_shader_variant *gs,
738 const struct ir3_shader_variant *fs,
739 uint32_t patch_control_points,
740 bool vshs_workgroup)
741 {
742 /* note: doesn't compile as static because of the array regs.. */
743 const struct reg_config {
744 uint16_t reg_sp_xs_out_reg;
745 uint16_t reg_sp_xs_vpc_dst_reg;
746 uint16_t reg_vpc_xs_pack;
747 uint16_t reg_vpc_xs_clip_cntl;
748 uint16_t reg_gras_xs_cl_cntl;
749 uint16_t reg_pc_xs_out_cntl;
750 uint16_t reg_sp_xs_primitive_cntl;
751 uint16_t reg_vpc_xs_layer_cntl;
752 uint16_t reg_gras_xs_layer_cntl;
753 } reg_config[] = {
754 [MESA_SHADER_VERTEX] = {
755 REG_A6XX_SP_VS_OUT_REG(0),
756 REG_A6XX_SP_VS_VPC_DST_REG(0),
757 REG_A6XX_VPC_VS_PACK,
758 REG_A6XX_VPC_VS_CLIP_CNTL,
759 REG_A6XX_GRAS_VS_CL_CNTL,
760 REG_A6XX_PC_VS_OUT_CNTL,
761 REG_A6XX_SP_VS_PRIMITIVE_CNTL,
762 REG_A6XX_VPC_VS_LAYER_CNTL,
763 REG_A6XX_GRAS_VS_LAYER_CNTL
764 },
765 [MESA_SHADER_TESS_EVAL] = {
766 REG_A6XX_SP_DS_OUT_REG(0),
767 REG_A6XX_SP_DS_VPC_DST_REG(0),
768 REG_A6XX_VPC_DS_PACK,
769 REG_A6XX_VPC_DS_CLIP_CNTL,
770 REG_A6XX_GRAS_DS_CL_CNTL,
771 REG_A6XX_PC_DS_OUT_CNTL,
772 REG_A6XX_SP_DS_PRIMITIVE_CNTL,
773 REG_A6XX_VPC_DS_LAYER_CNTL,
774 REG_A6XX_GRAS_DS_LAYER_CNTL
775 },
776 [MESA_SHADER_GEOMETRY] = {
777 REG_A6XX_SP_GS_OUT_REG(0),
778 REG_A6XX_SP_GS_VPC_DST_REG(0),
779 REG_A6XX_VPC_GS_PACK,
780 REG_A6XX_VPC_GS_CLIP_CNTL,
781 REG_A6XX_GRAS_GS_CL_CNTL,
782 REG_A6XX_PC_GS_OUT_CNTL,
783 REG_A6XX_SP_GS_PRIMITIVE_CNTL,
784 REG_A6XX_VPC_GS_LAYER_CNTL,
785 REG_A6XX_GRAS_GS_LAYER_CNTL
786 },
787 };
788
789 const struct ir3_shader_variant *last_shader;
790 if (gs) {
791 last_shader = gs;
792 } else if (hs) {
793 last_shader = ds;
794 } else {
795 last_shader = vs;
796 }
797
798 const struct reg_config *cfg = &reg_config[last_shader->type];
799
800 struct ir3_shader_linkage linkage = { .primid_loc = 0xff };
801 if (fs)
802 ir3_link_shaders(&linkage, last_shader, fs, true);
803
804 if (last_shader->shader->stream_output.num_outputs)
805 tu6_link_streamout(&linkage, last_shader);
806
807 /* We do this after linking shaders in order to know whether PrimID
808 * passthrough needs to be enabled.
809 */
810 bool primid_passthru = linkage.primid_loc != 0xff;
811 tu6_emit_vs_system_values(cs, vs, hs, ds, gs, primid_passthru);
812
813 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VAR_DISABLE(0), 4);
814 tu_cs_emit(cs, ~linkage.varmask[0]);
815 tu_cs_emit(cs, ~linkage.varmask[1]);
816 tu_cs_emit(cs, ~linkage.varmask[2]);
817 tu_cs_emit(cs, ~linkage.varmask[3]);
818
819 /* a6xx finds position/pointsize at the end */
820 const uint32_t position_regid =
821 ir3_find_output_regid(last_shader, VARYING_SLOT_POS);
822 const uint32_t pointsize_regid =
823 ir3_find_output_regid(last_shader, VARYING_SLOT_PSIZ);
824 const uint32_t layer_regid =
825 ir3_find_output_regid(last_shader, VARYING_SLOT_LAYER);
826 uint32_t primitive_regid = gs ?
827 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID) : regid(63, 0);
828 uint32_t flags_regid = gs ?
829 ir3_find_output_regid(gs, VARYING_SLOT_GS_VERTEX_FLAGS_IR3) : 0;
830
831 uint32_t pointsize_loc = 0xff, position_loc = 0xff, layer_loc = 0xff;
832 if (layer_regid != regid(63, 0)) {
833 layer_loc = linkage.max_loc;
834 ir3_link_add(&linkage, layer_regid, 0x1, linkage.max_loc);
835 }
836 if (position_regid != regid(63, 0)) {
837 position_loc = linkage.max_loc;
838 ir3_link_add(&linkage, position_regid, 0xf, linkage.max_loc);
839 }
840 if (pointsize_regid != regid(63, 0)) {
841 pointsize_loc = linkage.max_loc;
842 ir3_link_add(&linkage, pointsize_regid, 0x1, linkage.max_loc);
843 }
844
845 tu6_setup_streamout(cs, last_shader, &linkage);
846
847 /* The GPU hangs on some models when there are no outputs (xs_pack::CNT),
848 * at least when a DS is the last stage, so add a dummy output to keep it
849 * happy if there aren't any. We do this late in order to avoid emitting
850 * any unused code and make sure that optimizations don't remove it.
851 */
852 if (linkage.cnt == 0)
853 ir3_link_add(&linkage, 0, 0x1, linkage.max_loc);
854
855 /* map outputs of the last shader to VPC */
856 assert(linkage.cnt <= 32);
857 const uint32_t sp_out_count = DIV_ROUND_UP(linkage.cnt, 2);
858 const uint32_t sp_vpc_dst_count = DIV_ROUND_UP(linkage.cnt, 4);
859 uint32_t sp_out[16];
860 uint32_t sp_vpc_dst[8];
861 for (uint32_t i = 0; i < linkage.cnt; i++) {
862 ((uint16_t *) sp_out)[i] =
863 A6XX_SP_VS_OUT_REG_A_REGID(linkage.var[i].regid) |
864 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage.var[i].compmask);
865 ((uint8_t *) sp_vpc_dst)[i] =
866 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage.var[i].loc);
867 }
868
869 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_out_reg, sp_out_count);
870 tu_cs_emit_array(cs, sp_out, sp_out_count);
871
872 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_vpc_dst_reg, sp_vpc_dst_count);
873 tu_cs_emit_array(cs, sp_vpc_dst, sp_vpc_dst_count);
874
875 tu_cs_emit_pkt4(cs, cfg->reg_vpc_xs_pack, 1);
876 tu_cs_emit(cs, A6XX_VPC_VS_PACK_POSITIONLOC(position_loc) |
877 A6XX_VPC_VS_PACK_PSIZELOC(pointsize_loc) |
878 A6XX_VPC_VS_PACK_STRIDE_IN_VPC(linkage.max_loc));
879
880 tu_cs_emit_pkt4(cs, cfg->reg_vpc_xs_clip_cntl, 1);
881 tu_cs_emit(cs, 0xffff00);
882
883 tu_cs_emit_pkt4(cs, cfg->reg_gras_xs_cl_cntl, 1);
884 tu_cs_emit(cs, 0);
885
886 tu_cs_emit_pkt4(cs, cfg->reg_pc_xs_out_cntl, 1);
887 tu_cs_emit(cs, A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(linkage.max_loc) |
888 CONDREG(pointsize_regid, A6XX_PC_VS_OUT_CNTL_PSIZE) |
889 CONDREG(layer_regid, A6XX_PC_VS_OUT_CNTL_LAYER) |
890 CONDREG(primitive_regid, A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID));
891
892 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_primitive_cntl, 1);
893 tu_cs_emit(cs, A6XX_SP_VS_PRIMITIVE_CNTL_OUT(linkage.cnt) |
894 A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(flags_regid));
895
896 tu_cs_emit_pkt4(cs, cfg->reg_vpc_xs_layer_cntl, 1);
897 tu_cs_emit(cs, A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(layer_loc) | 0xff00);
898
899 tu_cs_emit_pkt4(cs, cfg->reg_gras_xs_layer_cntl, 1);
900 tu_cs_emit(cs, CONDREG(layer_regid, A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER));
901
902 tu_cs_emit_regs(cs, A6XX_PC_PRIMID_PASSTHRU(primid_passthru));
903
904 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_CNTL_0, 1);
905 tu_cs_emit(cs, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs ? fs->total_in : 0) |
906 COND(fs && fs->total_in, A6XX_VPC_CNTL_0_VARYING) |
907 A6XX_VPC_CNTL_0_PRIMIDLOC(linkage.primid_loc) |
908 A6XX_VPC_CNTL_0_VIEWIDLOC(0xff));
909
910 if (hs) {
911 shader_info *hs_info = &hs->shader->nir->info;
912 uint32_t unknown_a831 = vs->output_size;
913
914 tu_cs_emit_pkt4(cs, REG_A6XX_PC_TESS_NUM_VERTEX, 1);
915 tu_cs_emit(cs, hs_info->tess.tcs_vertices_out);
916
917 /* Total attribute slots in HS incoming patch. */
918 tu_cs_emit_pkt4(cs, REG_A6XX_PC_HS_INPUT_SIZE, 1);
919 tu_cs_emit(cs, patch_control_points * vs->output_size / 4);
920
921 /* for A650 this value seems to be local memory size per wave */
922 if (vshs_workgroup) {
923 const uint32_t wavesize = 64;
924 /* note: if HS is really just the VS extended, then this
925 * should be by MAX2(patch_control_points, hs_info->tess.tcs_vertices_out)
926 * however that doesn't match the blob, and fails some dEQP tests.
927 */
928 uint32_t prims_per_wave = wavesize / hs_info->tess.tcs_vertices_out;
929 uint32_t total_size = vs->output_size * patch_control_points * prims_per_wave;
930 unknown_a831 = DIV_ROUND_UP(total_size, wavesize);
931 }
932
933 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
934 tu_cs_emit(cs, unknown_a831);
935
936 /* In SPIR-V generated from GLSL, the tessellation primitive params are
937 * are specified in the tess eval shader, but in SPIR-V generated from
938 * HLSL, they are specified in the tess control shader. */
939 shader_info *tess_info =
940 ds->shader->nir->info.tess.spacing == TESS_SPACING_UNSPECIFIED ?
941 &hs->shader->nir->info : &ds->shader->nir->info;
942 tu_cs_emit_pkt4(cs, REG_A6XX_PC_TESS_CNTL, 1);
943 uint32_t output;
944 if (tess_info->tess.point_mode)
945 output = TESS_POINTS;
946 else if (tess_info->tess.primitive_mode == GL_ISOLINES)
947 output = TESS_LINES;
948 else if (tess_info->tess.ccw)
949 output = TESS_CCW_TRIS;
950 else
951 output = TESS_CW_TRIS;
952
953 enum a6xx_tess_spacing spacing;
954 switch (tess_info->tess.spacing) {
955 case TESS_SPACING_EQUAL:
956 spacing = TESS_EQUAL;
957 break;
958 case TESS_SPACING_FRACTIONAL_ODD:
959 spacing = TESS_FRACTIONAL_ODD;
960 break;
961 case TESS_SPACING_FRACTIONAL_EVEN:
962 spacing = TESS_FRACTIONAL_EVEN;
963 break;
964 case TESS_SPACING_UNSPECIFIED:
965 default:
966 unreachable("invalid tess spacing");
967 }
968 tu_cs_emit(cs, A6XX_PC_TESS_CNTL_SPACING(spacing) |
969 A6XX_PC_TESS_CNTL_OUTPUT(output));
970
971 tu6_emit_link_map(cs, vs, hs, SB6_HS_SHADER);
972 tu6_emit_link_map(cs, hs, ds, SB6_DS_SHADER);
973 }
974
975
976 if (gs) {
977 uint32_t vertices_out, invocations, output, vec4_size;
978 /* this detects the tu_clear_blit path, which doesn't set ->nir */
979 if (gs->shader->nir) {
980 if (hs) {
981 tu6_emit_link_map(cs, ds, gs, SB6_GS_SHADER);
982 } else {
983 tu6_emit_link_map(cs, vs, gs, SB6_GS_SHADER);
984 }
985 vertices_out = gs->shader->nir->info.gs.vertices_out - 1;
986 output = gl_primitive_to_tess(gs->shader->nir->info.gs.output_primitive);
987 invocations = gs->shader->nir->info.gs.invocations - 1;
988 /* Size of per-primitive alloction in ldlw memory in vec4s. */
989 vec4_size = gs->shader->nir->info.gs.vertices_in *
990 DIV_ROUND_UP(vs->output_size, 4);
991 } else {
992 vertices_out = 3;
993 output = TESS_CW_TRIS;
994 invocations = 0;
995 vec4_size = 0;
996 }
997
998 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_5, 1);
999 tu_cs_emit(cs,
1000 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(vertices_out) |
1001 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output) |
1002 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(invocations));
1003
1004 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_3, 1);
1005 tu_cs_emit(cs, 0);
1006
1007 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9100, 1);
1008 tu_cs_emit(cs, 0xff);
1009
1010 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
1011 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size));
1012
1013 tu_cs_emit_pkt4(cs, REG_A6XX_PC_MULTIVIEW_CNTL, 1);
1014 tu_cs_emit(cs, 0);
1015
1016 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_PRIM_SIZE, 1);
1017 tu_cs_emit(cs, vs->output_size);
1018 }
1019 }
1020
1021 static int
1022 tu6_vpc_varying_mode(const struct ir3_shader_variant *fs,
1023 uint32_t index,
1024 uint8_t *interp_mode,
1025 uint8_t *ps_repl_mode)
1026 {
1027 enum
1028 {
1029 INTERP_SMOOTH = 0,
1030 INTERP_FLAT = 1,
1031 INTERP_ZERO = 2,
1032 INTERP_ONE = 3,
1033 };
1034 enum
1035 {
1036 PS_REPL_NONE = 0,
1037 PS_REPL_S = 1,
1038 PS_REPL_T = 2,
1039 PS_REPL_ONE_MINUS_T = 3,
1040 };
1041
1042 const uint32_t compmask = fs->inputs[index].compmask;
1043
1044 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
1045 * fourth component occupy three consecutive varying slots
1046 */
1047 int shift = 0;
1048 *interp_mode = 0;
1049 *ps_repl_mode = 0;
1050 if (fs->inputs[index].slot == VARYING_SLOT_PNTC) {
1051 if (compmask & 0x1) {
1052 *ps_repl_mode |= PS_REPL_S << shift;
1053 shift += 2;
1054 }
1055 if (compmask & 0x2) {
1056 *ps_repl_mode |= PS_REPL_T << shift;
1057 shift += 2;
1058 }
1059 if (compmask & 0x4) {
1060 *interp_mode |= INTERP_ZERO << shift;
1061 shift += 2;
1062 }
1063 if (compmask & 0x8) {
1064 *interp_mode |= INTERP_ONE << 6;
1065 shift += 2;
1066 }
1067 } else if ((fs->inputs[index].interpolate == INTERP_MODE_FLAT) ||
1068 fs->inputs[index].rasterflat) {
1069 for (int i = 0; i < 4; i++) {
1070 if (compmask & (1 << i)) {
1071 *interp_mode |= INTERP_FLAT << shift;
1072 shift += 2;
1073 }
1074 }
1075 }
1076
1077 return shift;
1078 }
1079
1080 static void
1081 tu6_emit_vpc_varying_modes(struct tu_cs *cs,
1082 const struct ir3_shader_variant *fs)
1083 {
1084 uint32_t interp_modes[8] = { 0 };
1085 uint32_t ps_repl_modes[8] = { 0 };
1086
1087 if (fs) {
1088 for (int i = -1;
1089 (i = ir3_next_varying(fs, i)) < (int) fs->inputs_count;) {
1090
1091 /* get the mode for input i */
1092 uint8_t interp_mode;
1093 uint8_t ps_repl_mode;
1094 const int bits =
1095 tu6_vpc_varying_mode(fs, i, &interp_mode, &ps_repl_mode);
1096
1097 /* OR the mode into the array */
1098 const uint32_t inloc = fs->inputs[i].inloc * 2;
1099 uint32_t n = inloc / 32;
1100 uint32_t shift = inloc % 32;
1101 interp_modes[n] |= interp_mode << shift;
1102 ps_repl_modes[n] |= ps_repl_mode << shift;
1103 if (shift + bits > 32) {
1104 n++;
1105 shift = 32 - shift;
1106
1107 interp_modes[n] |= interp_mode >> shift;
1108 ps_repl_modes[n] |= ps_repl_mode >> shift;
1109 }
1110 }
1111 }
1112
1113 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
1114 tu_cs_emit_array(cs, interp_modes, 8);
1115
1116 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
1117 tu_cs_emit_array(cs, ps_repl_modes, 8);
1118 }
1119
1120 void
1121 tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
1122 {
1123 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
1124 uint32_t ij_regid[IJ_COUNT];
1125 uint32_t smask_in_regid;
1126
1127 bool sample_shading = fs->per_samp | fs->key.sample_shading;
1128 bool enable_varyings = fs->total_in > 0;
1129
1130 samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
1131 smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
1132 face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
1133 coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
1134 zwcoord_regid = VALIDREG(coord_regid) ? coord_regid + 2 : regid(63, 0);
1135 for (unsigned i = 0; i < ARRAY_SIZE(ij_regid); i++)
1136 ij_regid[i] = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL + i);
1137
1138 if (VALIDREG(ij_regid[IJ_LINEAR_SAMPLE]))
1139 tu_finishme("linear sample varying");
1140
1141 if (VALIDREG(ij_regid[IJ_LINEAR_CENTROID]))
1142 tu_finishme("linear centroid varying");
1143
1144 if (fs->num_sampler_prefetch > 0) {
1145 assert(VALIDREG(ij_regid[IJ_PERSP_PIXEL]));
1146 /* also, it seems like ij_pix is *required* to be r0.x */
1147 assert(ij_regid[IJ_PERSP_PIXEL] == regid(0, 0));
1148 }
1149
1150 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
1151 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
1152 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
1153 0x7000); // XXX);
1154 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
1155 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
1156 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch->src) |
1157 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch->samp_id) |
1158 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch->tex_id) |
1159 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch->dst) |
1160 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch->wrmask) |
1161 COND(prefetch->half_precision, A6XX_SP_FS_PREFETCH_CMD_HALF) |
1162 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch->cmd));
1163 }
1164
1165 if (fs->num_sampler_prefetch > 0) {
1166 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(0), fs->num_sampler_prefetch);
1167 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
1168 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
1169 tu_cs_emit(cs,
1170 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(prefetch->samp_bindless_id) |
1171 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(prefetch->tex_bindless_id));
1172 }
1173 }
1174
1175 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
1176 tu_cs_emit(cs, 0x7);
1177 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
1178 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
1179 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
1180 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_regid[IJ_PERSP_SIZE]));
1181 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(ij_regid[IJ_PERSP_PIXEL]) |
1182 A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(ij_regid[IJ_LINEAR_PIXEL]) |
1183 A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(ij_regid[IJ_PERSP_CENTROID]) |
1184 A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(ij_regid[IJ_LINEAR_CENTROID]));
1185 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
1186 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
1187 A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(ij_regid[IJ_PERSP_SAMPLE]) |
1188 A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(ij_regid[IJ_LINEAR_SAMPLE]));
1189 tu_cs_emit(cs, 0xfc);
1190
1191 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
1192 tu_cs_emit(cs, enable_varyings ? 3 : 1);
1193
1194 bool need_size = fs->frag_face || fs->fragcoord_compmask != 0;
1195 bool need_size_persamp = false;
1196 if (VALIDREG(ij_regid[IJ_PERSP_SIZE])) {
1197 if (sample_shading)
1198 need_size_persamp = true;
1199 else
1200 need_size = true;
1201 }
1202 if (VALIDREG(ij_regid[IJ_LINEAR_PIXEL]))
1203 need_size = true;
1204
1205 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CNTL, 1);
1206 tu_cs_emit(cs,
1207 CONDREG(ij_regid[IJ_PERSP_PIXEL], A6XX_GRAS_CNTL_IJ_PERSP_PIXEL) |
1208 CONDREG(ij_regid[IJ_PERSP_CENTROID], A6XX_GRAS_CNTL_IJ_PERSP_CENTROID) |
1209 CONDREG(ij_regid[IJ_PERSP_SAMPLE], A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE) |
1210 COND(need_size, A6XX_GRAS_CNTL_SIZE) |
1211 COND(need_size_persamp, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
1212 COND(fs->fragcoord_compmask != 0, A6XX_GRAS_CNTL_COORD_MASK(fs->fragcoord_compmask)));
1213
1214 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CONTROL0, 2);
1215 tu_cs_emit(cs,
1216 CONDREG(ij_regid[IJ_PERSP_PIXEL], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL) |
1217 CONDREG(ij_regid[IJ_PERSP_CENTROID], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID) |
1218 CONDREG(ij_regid[IJ_PERSP_SAMPLE], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE) |
1219 COND(need_size, A6XX_RB_RENDER_CONTROL0_SIZE) |
1220 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
1221 COND(need_size_persamp, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
1222 COND(fs->fragcoord_compmask != 0,
1223 A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs->fragcoord_compmask)));
1224 tu_cs_emit(cs,
1225 /* these two bits (UNK4/UNK5) relate to fragcoord
1226 * without them, fragcoord is the same for all samples
1227 */
1228 COND(sample_shading, A6XX_RB_RENDER_CONTROL1_UNK4) |
1229 COND(sample_shading, A6XX_RB_RENDER_CONTROL1_UNK5) |
1230 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
1231 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
1232 CONDREG(ij_regid[IJ_PERSP_SIZE], A6XX_RB_RENDER_CONTROL1_SIZE) |
1233 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
1234
1235 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CNTL, 1);
1236 tu_cs_emit(cs, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
1237
1238 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8101, 1);
1239 tu_cs_emit(cs, COND(sample_shading, 0x6)); // XXX
1240
1241 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
1242 tu_cs_emit(cs, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
1243 }
1244
1245 static void
1246 tu6_emit_fs_outputs(struct tu_cs *cs,
1247 const struct ir3_shader_variant *fs,
1248 uint32_t mrt_count, bool dual_src_blend,
1249 uint32_t render_components,
1250 bool is_s8_uint)
1251 {
1252 uint32_t smask_regid, posz_regid, stencilref_regid;
1253
1254 posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
1255 smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
1256 stencilref_regid = ir3_find_output_regid(fs, FRAG_RESULT_STENCIL);
1257
1258 uint32_t fragdata_regid[8];
1259 if (fs->color0_mrt) {
1260 fragdata_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
1261 for (uint32_t i = 1; i < ARRAY_SIZE(fragdata_regid); i++)
1262 fragdata_regid[i] = fragdata_regid[0];
1263 } else {
1264 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++)
1265 fragdata_regid[i] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0 + i);
1266 }
1267
1268 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_CNTL0, 2);
1269 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
1270 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
1271 A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(stencilref_regid) |
1272 COND(dual_src_blend, A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE));
1273 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count));
1274
1275 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
1276 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++) {
1277 // TODO we could have a mix of half and full precision outputs,
1278 // we really need to figure out half-precision from IR3_REG_HALF
1279 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid[i]) |
1280 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION : 0));
1281 }
1282
1283 tu_cs_emit_regs(cs,
1284 A6XX_SP_FS_RENDER_COMPONENTS(.dword = render_components));
1285
1286 tu_cs_emit_pkt4(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
1287 tu_cs_emit(cs, COND(fs->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
1288 COND(fs->writes_smask, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK) |
1289 COND(fs->writes_stencilref, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF) |
1290 COND(dual_src_blend, A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE));
1291 tu_cs_emit(cs, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count));
1292
1293 tu_cs_emit_regs(cs,
1294 A6XX_RB_RENDER_COMPONENTS(.dword = render_components));
1295
1296 enum a6xx_ztest_mode zmode;
1297
1298 if (fs->no_earlyz || fs->has_kill || fs->writes_pos || fs->writes_stencilref || is_s8_uint) {
1299 zmode = A6XX_LATE_Z;
1300 } else {
1301 zmode = A6XX_EARLY_Z;
1302 }
1303
1304 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
1305 tu_cs_emit(cs, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(zmode));
1306
1307 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
1308 tu_cs_emit(cs, A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(zmode));
1309 }
1310
1311 static void
1312 tu6_emit_geom_tess_consts(struct tu_cs *cs,
1313 const struct ir3_shader_variant *vs,
1314 const struct ir3_shader_variant *hs,
1315 const struct ir3_shader_variant *ds,
1316 const struct ir3_shader_variant *gs,
1317 uint32_t cps_per_patch)
1318 {
1319 uint32_t num_vertices =
1320 hs ? cps_per_patch : gs->shader->nir->info.gs.vertices_in;
1321
1322 uint32_t vs_params[4] = {
1323 vs->output_size * num_vertices * 4, /* vs primitive stride */
1324 vs->output_size * 4, /* vs vertex stride */
1325 0,
1326 0,
1327 };
1328 uint32_t vs_base = ir3_const_state(vs)->offsets.primitive_param;
1329 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, vs_base, SB6_VS_SHADER, 0,
1330 ARRAY_SIZE(vs_params), vs_params);
1331
1332 if (hs) {
1333 assert(ds->type != MESA_SHADER_NONE);
1334 uint32_t hs_params[4] = {
1335 vs->output_size * num_vertices * 4, /* hs primitive stride */
1336 vs->output_size * 4, /* hs vertex stride */
1337 hs->output_size,
1338 cps_per_patch,
1339 };
1340
1341 uint32_t hs_base = hs->const_state->offsets.primitive_param;
1342 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, hs_base, SB6_HS_SHADER, 0,
1343 ARRAY_SIZE(hs_params), hs_params);
1344 if (gs)
1345 num_vertices = gs->shader->nir->info.gs.vertices_in;
1346
1347 uint32_t ds_params[4] = {
1348 ds->output_size * num_vertices * 4, /* ds primitive stride */
1349 ds->output_size * 4, /* ds vertex stride */
1350 hs->output_size, /* hs vertex stride (dwords) */
1351 hs->shader->nir->info.tess.tcs_vertices_out
1352 };
1353
1354 uint32_t ds_base = ds->const_state->offsets.primitive_param;
1355 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, ds_base, SB6_DS_SHADER, 0,
1356 ARRAY_SIZE(ds_params), ds_params);
1357 }
1358
1359 if (gs) {
1360 const struct ir3_shader_variant *prev = ds ? ds : vs;
1361 uint32_t gs_params[4] = {
1362 prev->output_size * num_vertices * 4, /* gs primitive stride */
1363 prev->output_size * 4, /* gs vertex stride */
1364 0,
1365 0,
1366 };
1367 uint32_t gs_base = gs->const_state->offsets.primitive_param;
1368 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, gs_base, SB6_GS_SHADER, 0,
1369 ARRAY_SIZE(gs_params), gs_params);
1370 }
1371 }
1372
1373 static void
1374 tu6_emit_program(struct tu_cs *cs,
1375 struct tu_pipeline_builder *builder,
1376 bool binning_pass)
1377 {
1378 const struct ir3_shader_variant *vs = builder->variants[MESA_SHADER_VERTEX];
1379 const struct ir3_shader_variant *bs = builder->binning_variant;
1380 const struct ir3_shader_variant *hs = builder->variants[MESA_SHADER_TESS_CTRL];
1381 const struct ir3_shader_variant *ds = builder->variants[MESA_SHADER_TESS_EVAL];
1382 const struct ir3_shader_variant *gs = builder->variants[MESA_SHADER_GEOMETRY];
1383 const struct ir3_shader_variant *fs = builder->variants[MESA_SHADER_FRAGMENT];
1384 gl_shader_stage stage = MESA_SHADER_VERTEX;
1385 uint32_t cps_per_patch = builder->create_info->pTessellationState ?
1386 builder->create_info->pTessellationState->patchControlPoints : 0;
1387
1388 STATIC_ASSERT(MESA_SHADER_VERTEX == 0);
1389
1390 tu_cs_emit_regs(cs, A6XX_HLSQ_INVALIDATE_CMD(
1391 .vs_state = true,
1392 .hs_state = true,
1393 .ds_state = true,
1394 .gs_state = true,
1395 .fs_state = true,
1396 .gfx_ibo = true));
1397
1398 /* Don't use the binning pass variant when GS is present because we don't
1399 * support compiling correct binning pass variants with GS.
1400 */
1401 if (binning_pass && !gs) {
1402 vs = bs;
1403 tu6_emit_xs_config(cs, stage, bs, builder->binning_vs_iova);
1404 stage++;
1405 }
1406
1407 for (; stage < ARRAY_SIZE(builder->shaders); stage++) {
1408 const struct ir3_shader_variant *xs = builder->variants[stage];
1409
1410 if (stage == MESA_SHADER_FRAGMENT && binning_pass)
1411 fs = xs = NULL;
1412
1413 tu6_emit_xs_config(cs, stage, xs, builder->shader_iova[stage]);
1414 }
1415
1416 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
1417 tu_cs_emit(cs, 0);
1418
1419 tu6_emit_vpc(cs, vs, hs, ds, gs, fs, cps_per_patch,
1420 builder->device->physical_device->gpu_id == 650);
1421 tu6_emit_vpc_varying_modes(cs, fs);
1422
1423 if (fs) {
1424 tu6_emit_fs_inputs(cs, fs);
1425 tu6_emit_fs_outputs(cs, fs, builder->color_attachment_count,
1426 builder->use_dual_src_blend,
1427 builder->render_components,
1428 builder->depth_attachment_format == VK_FORMAT_S8_UINT);
1429 } else {
1430 /* TODO: check if these can be skipped if fs is disabled */
1431 struct ir3_shader_variant dummy_variant = {};
1432 tu6_emit_fs_inputs(cs, &dummy_variant);
1433 tu6_emit_fs_outputs(cs, &dummy_variant, builder->color_attachment_count,
1434 builder->use_dual_src_blend,
1435 builder->render_components,
1436 builder->depth_attachment_format == VK_FORMAT_S8_UINT);
1437 }
1438
1439 if (gs || hs) {
1440 tu6_emit_geom_tess_consts(cs, vs, hs, ds, gs, cps_per_patch);
1441 }
1442 }
1443
1444 static void
1445 tu6_emit_vertex_input(struct tu_cs *cs,
1446 const struct ir3_shader_variant *vs,
1447 const VkPipelineVertexInputStateCreateInfo *info,
1448 uint32_t *bindings_used)
1449 {
1450 uint32_t vfd_decode_idx = 0;
1451 uint32_t binding_instanced = 0; /* bitmask of instanced bindings */
1452 uint32_t step_rate[MAX_VBS];
1453
1454 for (uint32_t i = 0; i < info->vertexBindingDescriptionCount; i++) {
1455 const VkVertexInputBindingDescription *binding =
1456 &info->pVertexBindingDescriptions[i];
1457
1458 tu_cs_emit_regs(cs,
1459 A6XX_VFD_FETCH_STRIDE(binding->binding, binding->stride));
1460
1461 if (binding->inputRate == VK_VERTEX_INPUT_RATE_INSTANCE)
1462 binding_instanced |= 1 << binding->binding;
1463
1464 *bindings_used |= 1 << binding->binding;
1465 step_rate[binding->binding] = 1;
1466 }
1467
1468 const VkPipelineVertexInputDivisorStateCreateInfoEXT *div_state =
1469 vk_find_struct_const(info->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
1470 if (div_state) {
1471 for (uint32_t i = 0; i < div_state->vertexBindingDivisorCount; i++) {
1472 const VkVertexInputBindingDivisorDescriptionEXT *desc =
1473 &div_state->pVertexBindingDivisors[i];
1474 step_rate[desc->binding] = desc->divisor;
1475 }
1476 }
1477
1478 /* TODO: emit all VFD_DECODE/VFD_DEST_CNTL in same (two) pkt4 */
1479
1480 for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
1481 const VkVertexInputAttributeDescription *attr =
1482 &info->pVertexAttributeDescriptions[i];
1483 uint32_t input_idx;
1484
1485 assert(*bindings_used & BIT(attr->binding));
1486
1487 for (input_idx = 0; input_idx < vs->inputs_count; input_idx++) {
1488 if ((vs->inputs[input_idx].slot - VERT_ATTRIB_GENERIC0) == attr->location)
1489 break;
1490 }
1491
1492 /* attribute not used, skip it */
1493 if (input_idx == vs->inputs_count)
1494 continue;
1495
1496 const struct tu_native_format format = tu6_format_vtx(attr->format);
1497 tu_cs_emit_regs(cs,
1498 A6XX_VFD_DECODE_INSTR(vfd_decode_idx,
1499 .idx = attr->binding,
1500 .offset = attr->offset,
1501 .instanced = binding_instanced & (1 << attr->binding),
1502 .format = format.fmt,
1503 .swap = format.swap,
1504 .unk30 = 1,
1505 ._float = !vk_format_is_int(attr->format)),
1506 A6XX_VFD_DECODE_STEP_RATE(vfd_decode_idx, step_rate[attr->binding]));
1507
1508 tu_cs_emit_regs(cs,
1509 A6XX_VFD_DEST_CNTL_INSTR(vfd_decode_idx,
1510 .writemask = vs->inputs[input_idx].compmask,
1511 .regid = vs->inputs[input_idx].regid));
1512
1513 vfd_decode_idx++;
1514 }
1515
1516 tu_cs_emit_regs(cs,
1517 A6XX_VFD_CONTROL_0(
1518 .fetch_cnt = vfd_decode_idx, /* decode_cnt for binning pass ? */
1519 .decode_cnt = vfd_decode_idx));
1520 }
1521
1522 void
1523 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport)
1524 {
1525 float offsets[3];
1526 float scales[3];
1527 scales[0] = viewport->width / 2.0f;
1528 scales[1] = viewport->height / 2.0f;
1529 scales[2] = viewport->maxDepth - viewport->minDepth;
1530 offsets[0] = viewport->x + scales[0];
1531 offsets[1] = viewport->y + scales[1];
1532 offsets[2] = viewport->minDepth;
1533
1534 VkOffset2D min;
1535 VkOffset2D max;
1536 min.x = (int32_t) viewport->x;
1537 max.x = (int32_t) ceilf(viewport->x + viewport->width);
1538 if (viewport->height >= 0.0f) {
1539 min.y = (int32_t) viewport->y;
1540 max.y = (int32_t) ceilf(viewport->y + viewport->height);
1541 } else {
1542 min.y = (int32_t)(viewport->y + viewport->height);
1543 max.y = (int32_t) ceilf(viewport->y);
1544 }
1545 /* the spec allows viewport->height to be 0.0f */
1546 if (min.y == max.y)
1547 max.y++;
1548 assert(min.x >= 0 && min.x < max.x);
1549 assert(min.y >= 0 && min.y < max.y);
1550
1551 VkExtent2D guardband_adj;
1552 guardband_adj.width = fd_calc_guardband(offsets[0], scales[0], false);
1553 guardband_adj.height = fd_calc_guardband(offsets[1], scales[1], false);
1554
1555 tu_cs_emit_regs(cs,
1556 A6XX_GRAS_CL_VPORT_XOFFSET(0, offsets[0]),
1557 A6XX_GRAS_CL_VPORT_XSCALE(0, scales[0]),
1558 A6XX_GRAS_CL_VPORT_YOFFSET(0, offsets[1]),
1559 A6XX_GRAS_CL_VPORT_YSCALE(0, scales[1]),
1560 A6XX_GRAS_CL_VPORT_ZOFFSET(0, offsets[2]),
1561 A6XX_GRAS_CL_VPORT_ZSCALE(0, scales[2]));
1562
1563 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(0), 2);
1564 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(min.x) |
1565 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(min.y));
1566 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(max.x - 1) |
1567 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(max.y - 1));
1568
1569 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
1570 tu_cs_emit(cs,
1571 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj.width) |
1572 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj.height));
1573
1574 float z_clamp_min = MIN2(viewport->minDepth, viewport->maxDepth);
1575 float z_clamp_max = MAX2(viewport->minDepth, viewport->maxDepth);
1576
1577 tu_cs_emit_regs(cs,
1578 A6XX_GRAS_CL_Z_CLAMP_MIN(0, z_clamp_min),
1579 A6XX_GRAS_CL_Z_CLAMP_MAX(0, z_clamp_max));
1580
1581 tu_cs_emit_regs(cs,
1582 A6XX_RB_Z_CLAMP_MIN(z_clamp_min),
1583 A6XX_RB_Z_CLAMP_MAX(z_clamp_max));
1584 }
1585
1586 void
1587 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor)
1588 {
1589 VkOffset2D min = scissor->offset;
1590 VkOffset2D max = {
1591 scissor->offset.x + scissor->extent.width,
1592 scissor->offset.y + scissor->extent.height,
1593 };
1594
1595 /* special case for empty scissor with max == 0 to avoid overflow */
1596 if (max.x == 0)
1597 min.x = max.x = 1;
1598 if (max.y == 0)
1599 min.y = max.y = 1;
1600
1601 /* avoid overflow with large scissor
1602 * note the max will be limited to min - 1, so that empty scissor works
1603 */
1604 uint32_t scissor_max = BITFIELD_MASK(15);
1605 min.x = MIN2(scissor_max, min.x);
1606 min.y = MIN2(scissor_max, min.y);
1607 max.x = MIN2(scissor_max, max.x);
1608 max.y = MIN2(scissor_max, max.y);
1609
1610 tu_cs_emit_regs(cs,
1611 A6XX_GRAS_SC_SCREEN_SCISSOR_TL(0, .x = min.x, .y = min.y),
1612 A6XX_GRAS_SC_SCREEN_SCISSOR_BR(0, .x = max.x - 1, .y = max.y - 1));
1613 }
1614
1615 void
1616 tu6_emit_sample_locations(struct tu_cs *cs, const VkSampleLocationsInfoEXT *samp_loc)
1617 {
1618 if (!samp_loc) {
1619 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CONFIG, 1);
1620 tu_cs_emit(cs, 0);
1621
1622 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CONFIG, 1);
1623 tu_cs_emit(cs, 0);
1624
1625 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_SAMPLE_CONFIG, 1);
1626 tu_cs_emit(cs, 0);
1627 return;
1628 }
1629
1630 assert(samp_loc->sampleLocationsPerPixel == samp_loc->sampleLocationsCount);
1631 assert(samp_loc->sampleLocationGridSize.width == 1);
1632 assert(samp_loc->sampleLocationGridSize.height == 1);
1633
1634 uint32_t sample_config =
1635 A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE;
1636 uint32_t sample_locations = 0;
1637 for (uint32_t i = 0; i < samp_loc->sampleLocationsCount; i++) {
1638 sample_locations |=
1639 (A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(samp_loc->pSampleLocations[i].x) |
1640 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(samp_loc->pSampleLocations[i].y)) << i*8;
1641 }
1642
1643 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CONFIG, 2);
1644 tu_cs_emit(cs, sample_config);
1645 tu_cs_emit(cs, sample_locations);
1646
1647 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CONFIG, 2);
1648 tu_cs_emit(cs, sample_config);
1649 tu_cs_emit(cs, sample_locations);
1650
1651 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_SAMPLE_CONFIG, 2);
1652 tu_cs_emit(cs, sample_config);
1653 tu_cs_emit(cs, sample_locations);
1654 }
1655
1656 static uint32_t
1657 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo *rast_info,
1658 VkSampleCountFlagBits samples)
1659 {
1660 uint32_t gras_su_cntl = 0;
1661
1662 if (rast_info->cullMode & VK_CULL_MODE_FRONT_BIT)
1663 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_FRONT;
1664 if (rast_info->cullMode & VK_CULL_MODE_BACK_BIT)
1665 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_BACK;
1666
1667 if (rast_info->frontFace == VK_FRONT_FACE_CLOCKWISE)
1668 gras_su_cntl |= A6XX_GRAS_SU_CNTL_FRONT_CW;
1669
1670 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1671
1672 if (rast_info->depthBiasEnable)
1673 gras_su_cntl |= A6XX_GRAS_SU_CNTL_POLY_OFFSET;
1674
1675 if (samples > VK_SAMPLE_COUNT_1_BIT)
1676 gras_su_cntl |= A6XX_GRAS_SU_CNTL_MSAA_ENABLE;
1677
1678 return gras_su_cntl;
1679 }
1680
1681 void
1682 tu6_emit_depth_bias(struct tu_cs *cs,
1683 float constant_factor,
1684 float clamp,
1685 float slope_factor)
1686 {
1687 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
1688 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor).value);
1689 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor).value);
1690 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp).value);
1691 }
1692
1693 static void
1694 tu6_emit_depth_control(struct tu_cs *cs,
1695 const VkPipelineDepthStencilStateCreateInfo *ds_info,
1696 const VkPipelineRasterizationStateCreateInfo *rast_info)
1697 {
1698 uint32_t rb_depth_cntl = 0;
1699 if (ds_info->depthTestEnable) {
1700 rb_depth_cntl |=
1701 A6XX_RB_DEPTH_CNTL_Z_ENABLE |
1702 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) |
1703 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE; /* TODO: don't set for ALWAYS/NEVER */
1704
1705 if (rast_info->depthClampEnable)
1706 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE;
1707
1708 if (ds_info->depthWriteEnable)
1709 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
1710 }
1711
1712 if (ds_info->depthBoundsTestEnable)
1713 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE | A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
1714
1715 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_CNTL, 1);
1716 tu_cs_emit(cs, rb_depth_cntl);
1717 }
1718
1719 static void
1720 tu6_emit_stencil_control(struct tu_cs *cs,
1721 const VkPipelineDepthStencilStateCreateInfo *ds_info)
1722 {
1723 uint32_t rb_stencil_control = 0;
1724 if (ds_info->stencilTestEnable) {
1725 const VkStencilOpState *front = &ds_info->front;
1726 const VkStencilOpState *back = &ds_info->back;
1727 rb_stencil_control |=
1728 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
1729 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
1730 A6XX_RB_STENCIL_CONTROL_STENCIL_READ |
1731 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front->compareOp)) |
1732 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front->failOp)) |
1733 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front->passOp)) |
1734 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front->depthFailOp)) |
1735 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back->compareOp)) |
1736 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back->failOp)) |
1737 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back->passOp)) |
1738 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back->depthFailOp));
1739 }
1740
1741 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_CONTROL, 1);
1742 tu_cs_emit(cs, rb_stencil_control);
1743 }
1744
1745 static uint32_t
1746 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState *att,
1747 bool has_alpha)
1748 {
1749 const enum a3xx_rb_blend_opcode color_op = tu6_blend_op(att->colorBlendOp);
1750 const enum adreno_rb_blend_factor src_color_factor = tu6_blend_factor(
1751 has_alpha ? att->srcColorBlendFactor
1752 : tu_blend_factor_no_dst_alpha(att->srcColorBlendFactor));
1753 const enum adreno_rb_blend_factor dst_color_factor = tu6_blend_factor(
1754 has_alpha ? att->dstColorBlendFactor
1755 : tu_blend_factor_no_dst_alpha(att->dstColorBlendFactor));
1756 const enum a3xx_rb_blend_opcode alpha_op = tu6_blend_op(att->alphaBlendOp);
1757 const enum adreno_rb_blend_factor src_alpha_factor =
1758 tu6_blend_factor(att->srcAlphaBlendFactor);
1759 const enum adreno_rb_blend_factor dst_alpha_factor =
1760 tu6_blend_factor(att->dstAlphaBlendFactor);
1761
1762 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor) |
1763 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op) |
1764 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor) |
1765 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor) |
1766 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op) |
1767 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor);
1768 }
1769
1770 static uint32_t
1771 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState *att,
1772 uint32_t rb_mrt_control_rop,
1773 bool is_int,
1774 bool has_alpha)
1775 {
1776 uint32_t rb_mrt_control =
1777 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att->colorWriteMask);
1778
1779 /* ignore blending and logic op for integer attachments */
1780 if (is_int) {
1781 rb_mrt_control |= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
1782 return rb_mrt_control;
1783 }
1784
1785 rb_mrt_control |= rb_mrt_control_rop;
1786
1787 if (att->blendEnable) {
1788 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND;
1789
1790 if (has_alpha)
1791 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND2;
1792 }
1793
1794 return rb_mrt_control;
1795 }
1796
1797 static void
1798 tu6_emit_rb_mrt_controls(struct tu_cs *cs,
1799 const VkPipelineColorBlendStateCreateInfo *blend_info,
1800 const VkFormat attachment_formats[MAX_RTS],
1801 uint32_t *blend_enable_mask)
1802 {
1803 *blend_enable_mask = 0;
1804
1805 bool rop_reads_dst = false;
1806 uint32_t rb_mrt_control_rop = 0;
1807 if (blend_info->logicOpEnable) {
1808 rop_reads_dst = tu_logic_op_reads_dst(blend_info->logicOp);
1809 rb_mrt_control_rop =
1810 A6XX_RB_MRT_CONTROL_ROP_ENABLE |
1811 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info->logicOp));
1812 }
1813
1814 for (uint32_t i = 0; i < blend_info->attachmentCount; i++) {
1815 const VkPipelineColorBlendAttachmentState *att =
1816 &blend_info->pAttachments[i];
1817 const VkFormat format = attachment_formats[i];
1818
1819 uint32_t rb_mrt_control = 0;
1820 uint32_t rb_mrt_blend_control = 0;
1821 if (format != VK_FORMAT_UNDEFINED) {
1822 const bool is_int = vk_format_is_int(format);
1823 const bool has_alpha = vk_format_has_alpha(format);
1824
1825 rb_mrt_control =
1826 tu6_rb_mrt_control(att, rb_mrt_control_rop, is_int, has_alpha);
1827 rb_mrt_blend_control = tu6_rb_mrt_blend_control(att, has_alpha);
1828
1829 if (att->blendEnable || rop_reads_dst)
1830 *blend_enable_mask |= 1 << i;
1831 }
1832
1833 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
1834 tu_cs_emit(cs, rb_mrt_control);
1835 tu_cs_emit(cs, rb_mrt_blend_control);
1836 }
1837 }
1838
1839 static void
1840 tu6_emit_blend_control(struct tu_cs *cs,
1841 uint32_t blend_enable_mask,
1842 bool dual_src_blend,
1843 const VkPipelineMultisampleStateCreateInfo *msaa_info)
1844 {
1845 const uint32_t sample_mask =
1846 msaa_info->pSampleMask ? (*msaa_info->pSampleMask & 0xffff)
1847 : ((1 << msaa_info->rasterizationSamples) - 1);
1848
1849 tu_cs_emit_regs(cs,
1850 A6XX_SP_BLEND_CNTL(.enabled = blend_enable_mask,
1851 .dual_color_in_enable = dual_src_blend,
1852 .alpha_to_coverage = msaa_info->alphaToCoverageEnable,
1853 .unk8 = true));
1854
1855 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
1856 tu_cs_emit_regs(cs,
1857 A6XX_RB_BLEND_CNTL(.enable_blend = blend_enable_mask,
1858 .independent_blend = true,
1859 .sample_mask = sample_mask,
1860 .dual_color_in_enable = dual_src_blend,
1861 .alpha_to_coverage = msaa_info->alphaToCoverageEnable,
1862 .alpha_to_one = msaa_info->alphaToOneEnable));
1863 }
1864
1865 static VkResult
1866 tu_pipeline_allocate_cs(struct tu_device *dev,
1867 struct tu_pipeline *pipeline,
1868 struct tu_pipeline_builder *builder,
1869 struct ir3_shader_variant *compute)
1870 {
1871 uint32_t size = 2048 + tu6_load_state_size(pipeline, compute);
1872
1873 /* graphics case: */
1874 if (builder) {
1875 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
1876 if (builder->variants[i])
1877 size += builder->variants[i]->info.sizedwords;
1878 }
1879
1880 size += builder->binning_variant->info.sizedwords;
1881 } else {
1882 size += compute->info.sizedwords;
1883 }
1884
1885 tu_cs_init(&pipeline->cs, dev, TU_CS_MODE_SUB_STREAM, size);
1886
1887 /* Reserve the space now such that tu_cs_begin_sub_stream never fails. Note
1888 * that LOAD_STATE can potentially take up a large amount of space so we
1889 * calculate its size explicitly.
1890 */
1891 return tu_cs_reserve_space(&pipeline->cs, size);
1892 }
1893
1894 static void
1895 tu_pipeline_shader_key_init(struct ir3_shader_key *key,
1896 const VkGraphicsPipelineCreateInfo *pipeline_info)
1897 {
1898 for (uint32_t i = 0; i < pipeline_info->stageCount; i++) {
1899 if (pipeline_info->pStages[i].stage == VK_SHADER_STAGE_GEOMETRY_BIT) {
1900 key->has_gs = true;
1901 break;
1902 }
1903 }
1904
1905 if (pipeline_info->pRasterizationState->rasterizerDiscardEnable)
1906 return;
1907
1908 const VkPipelineMultisampleStateCreateInfo *msaa_info = pipeline_info->pMultisampleState;
1909 const struct VkPipelineSampleLocationsStateCreateInfoEXT *sample_locations =
1910 vk_find_struct_const(msaa_info->pNext, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1911 if (msaa_info->rasterizationSamples > 1 ||
1912 /* also set msaa key when sample location is not the default
1913 * since this affects varying interpolation */
1914 (sample_locations && sample_locations->sampleLocationsEnable)) {
1915 key->msaa = true;
1916 }
1917
1918 /* note: not actually used by ir3, just checked in tu6_emit_fs_inputs */
1919 if (msaa_info->sampleShadingEnable)
1920 key->sample_shading = true;
1921
1922 /* We set this after we compile to NIR because we need the prim mode */
1923 key->tessellation = IR3_TESS_NONE;
1924 }
1925
1926 static uint32_t
1927 tu6_get_tessmode(struct tu_shader* shader)
1928 {
1929 uint32_t primitive_mode = shader->ir3_shader->nir->info.tess.primitive_mode;
1930 switch (primitive_mode) {
1931 case GL_ISOLINES:
1932 return IR3_TESS_ISOLINES;
1933 case GL_TRIANGLES:
1934 return IR3_TESS_TRIANGLES;
1935 case GL_QUADS:
1936 return IR3_TESS_QUADS;
1937 case GL_NONE:
1938 return IR3_TESS_NONE;
1939 default:
1940 unreachable("bad tessmode");
1941 }
1942 }
1943
1944 static uint64_t
1945 tu_upload_variant(struct tu_pipeline *pipeline,
1946 const struct ir3_shader_variant *variant)
1947 {
1948 struct tu_cs_memory memory;
1949
1950 if (!variant)
1951 return 0;
1952
1953 /* this expects to get enough alignment because shaders are allocated first
1954 * and sizedwords is always aligned correctly
1955 * note: an assert in tu6_emit_xs_config validates the alignment
1956 */
1957 tu_cs_alloc(&pipeline->cs, variant->info.sizedwords, 1, &memory);
1958
1959 memcpy(memory.map, variant->bin, sizeof(uint32_t) * variant->info.sizedwords);
1960 return memory.iova;
1961 }
1962
1963 static VkResult
1964 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder,
1965 struct tu_pipeline *pipeline)
1966 {
1967 const struct ir3_compiler *compiler = builder->device->compiler;
1968 const VkPipelineShaderStageCreateInfo *stage_infos[MESA_SHADER_STAGES] = {
1969 NULL
1970 };
1971 for (uint32_t i = 0; i < builder->create_info->stageCount; i++) {
1972 gl_shader_stage stage =
1973 vk_to_mesa_shader_stage(builder->create_info->pStages[i].stage);
1974 stage_infos[stage] = &builder->create_info->pStages[i];
1975 }
1976
1977 struct ir3_shader_key key = {};
1978 tu_pipeline_shader_key_init(&key, builder->create_info);
1979
1980 for (gl_shader_stage stage = MESA_SHADER_VERTEX;
1981 stage < MESA_SHADER_STAGES; stage++) {
1982 const VkPipelineShaderStageCreateInfo *stage_info = stage_infos[stage];
1983 if (!stage_info && stage != MESA_SHADER_FRAGMENT)
1984 continue;
1985
1986 struct tu_shader *shader =
1987 tu_shader_create(builder->device, stage, stage_info, builder->layout,
1988 builder->alloc);
1989 if (!shader)
1990 return VK_ERROR_OUT_OF_HOST_MEMORY;
1991
1992 /* In SPIR-V generated from GLSL, the primitive mode is specified in the
1993 * tessellation evaluation shader, but in SPIR-V generated from HLSL,
1994 * the mode is specified in the tessellation control shader. */
1995 if ((stage == MESA_SHADER_TESS_EVAL || stage == MESA_SHADER_TESS_CTRL) &&
1996 key.tessellation == IR3_TESS_NONE) {
1997 key.tessellation = tu6_get_tessmode(shader);
1998 }
1999
2000 builder->shaders[stage] = shader;
2001 }
2002
2003 struct tu_shader *gs = builder->shaders[MESA_SHADER_GEOMETRY];
2004 key.layer_zero =
2005 !gs || !(gs->ir3_shader->nir->info.outputs_written & VARYING_SLOT_LAYER);
2006
2007 pipeline->tess.patch_type = key.tessellation;
2008
2009 for (gl_shader_stage stage = MESA_SHADER_VERTEX;
2010 stage < MESA_SHADER_STAGES; stage++) {
2011 if (!builder->shaders[stage])
2012 continue;
2013
2014 bool created;
2015 builder->variants[stage] =
2016 ir3_shader_get_variant(builder->shaders[stage]->ir3_shader,
2017 &key, false, &created);
2018 if (!builder->variants[stage])
2019 return VK_ERROR_OUT_OF_HOST_MEMORY;
2020 }
2021
2022 uint32_t safe_constlens = ir3_trim_constlen(builder->variants, compiler);
2023
2024 key.safe_constlen = true;
2025
2026 for (gl_shader_stage stage = MESA_SHADER_VERTEX;
2027 stage < MESA_SHADER_STAGES; stage++) {
2028 if (!builder->shaders[stage])
2029 continue;
2030
2031 if (safe_constlens & (1 << stage)) {
2032 bool created;
2033 builder->variants[stage] =
2034 ir3_shader_get_variant(builder->shaders[stage]->ir3_shader,
2035 &key, false, &created);
2036 if (!builder->variants[stage])
2037 return VK_ERROR_OUT_OF_HOST_MEMORY;
2038 }
2039 }
2040
2041 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
2042 struct ir3_shader_variant *variant;
2043
2044 if (vs->ir3_shader->stream_output.num_outputs ||
2045 !ir3_has_binning_vs(&key)) {
2046 variant = builder->variants[MESA_SHADER_VERTEX];
2047 } else {
2048 bool created;
2049 key.safe_constlen = !!(safe_constlens & (1 << MESA_SHADER_VERTEX));
2050 variant = ir3_shader_get_variant(vs->ir3_shader, &key,
2051 true, &created);
2052 if (!variant)
2053 return VK_ERROR_OUT_OF_HOST_MEMORY;
2054 }
2055
2056 builder->binning_variant = variant;
2057
2058 return VK_SUCCESS;
2059 }
2060
2061 static void
2062 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
2063 struct tu_pipeline *pipeline)
2064 {
2065 const VkPipelineDynamicStateCreateInfo *dynamic_info =
2066 builder->create_info->pDynamicState;
2067
2068 if (!dynamic_info)
2069 return;
2070
2071 for (uint32_t i = 0; i < dynamic_info->dynamicStateCount; i++) {
2072 VkDynamicState state = dynamic_info->pDynamicStates[i];
2073 switch (state) {
2074 case VK_DYNAMIC_STATE_VIEWPORT ... VK_DYNAMIC_STATE_STENCIL_REFERENCE:
2075 pipeline->dynamic_state_mask |= BIT(state);
2076 break;
2077 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
2078 pipeline->dynamic_state_mask |= BIT(TU_DYNAMIC_STATE_SAMPLE_LOCATIONS);
2079 break;
2080 default:
2081 assert(!"unsupported dynamic state");
2082 break;
2083 }
2084 }
2085 }
2086
2087 static void
2088 tu_pipeline_set_linkage(struct tu_program_descriptor_linkage *link,
2089 struct tu_shader *shader,
2090 struct ir3_shader_variant *v)
2091 {
2092 link->const_state = *ir3_const_state(v);
2093 link->constlen = v->constlen;
2094 link->push_consts = shader->push_consts;
2095 }
2096
2097 static void
2098 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder *builder,
2099 struct tu_pipeline *pipeline)
2100 {
2101 struct tu_cs prog_cs;
2102 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2103 tu6_emit_program(&prog_cs, builder, false);
2104 pipeline->program.state = tu_cs_end_draw_state(&pipeline->cs, &prog_cs);
2105
2106 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2107 tu6_emit_program(&prog_cs, builder, true);
2108 pipeline->program.binning_state = tu_cs_end_draw_state(&pipeline->cs, &prog_cs);
2109
2110 VkShaderStageFlags stages = 0;
2111 for (unsigned i = 0; i < builder->create_info->stageCount; i++) {
2112 stages |= builder->create_info->pStages[i].stage;
2113 }
2114 pipeline->active_stages = stages;
2115
2116 uint32_t desc_sets = 0;
2117 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2118 if (!builder->shaders[i])
2119 continue;
2120
2121 tu_pipeline_set_linkage(&pipeline->program.link[i],
2122 builder->shaders[i],
2123 builder->variants[i]);
2124 desc_sets |= builder->shaders[i]->active_desc_sets;
2125 }
2126 pipeline->active_desc_sets = desc_sets;
2127 }
2128
2129 static void
2130 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder *builder,
2131 struct tu_pipeline *pipeline)
2132 {
2133 const VkPipelineVertexInputStateCreateInfo *vi_info =
2134 builder->create_info->pVertexInputState;
2135 const struct ir3_shader_variant *vs = builder->variants[MESA_SHADER_VERTEX];
2136 const struct ir3_shader_variant *bs = builder->binning_variant;
2137
2138 struct tu_cs vi_cs;
2139 tu_cs_begin_sub_stream(&pipeline->cs,
2140 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
2141 tu6_emit_vertex_input(&vi_cs, vs, vi_info,
2142 &pipeline->vi.bindings_used);
2143 pipeline->vi.state = tu_cs_end_draw_state(&pipeline->cs, &vi_cs);
2144
2145 if (bs) {
2146 tu_cs_begin_sub_stream(&pipeline->cs,
2147 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
2148 tu6_emit_vertex_input(
2149 &vi_cs, bs, vi_info, &pipeline->vi.bindings_used);
2150 pipeline->vi.binning_state =
2151 tu_cs_end_draw_state(&pipeline->cs, &vi_cs);
2152 }
2153 }
2154
2155 static void
2156 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder *builder,
2157 struct tu_pipeline *pipeline)
2158 {
2159 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
2160 builder->create_info->pInputAssemblyState;
2161
2162 pipeline->ia.primtype = tu6_primtype(ia_info->topology);
2163 pipeline->ia.primitive_restart = ia_info->primitiveRestartEnable;
2164 }
2165
2166 static bool
2167 tu_pipeline_static_state(struct tu_pipeline *pipeline, struct tu_cs *cs,
2168 uint32_t id, uint32_t size)
2169 {
2170 assert(id < ARRAY_SIZE(pipeline->dynamic_state));
2171
2172 if (pipeline->dynamic_state_mask & BIT(id))
2173 return false;
2174
2175 pipeline->dynamic_state[id] = tu_cs_draw_state(&pipeline->cs, cs, size);
2176 return true;
2177 }
2178
2179 static void
2180 tu_pipeline_builder_parse_tessellation(struct tu_pipeline_builder *builder,
2181 struct tu_pipeline *pipeline)
2182 {
2183 const VkPipelineTessellationStateCreateInfo *tess_info =
2184 builder->create_info->pTessellationState;
2185
2186 if (!tess_info)
2187 return;
2188
2189 assert(pipeline->ia.primtype == DI_PT_PATCHES0);
2190 assert(tess_info->patchControlPoints <= 32);
2191 pipeline->ia.primtype += tess_info->patchControlPoints;
2192 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_info =
2193 vk_find_struct_const(tess_info->pNext, PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
2194 pipeline->tess.upper_left_domain_origin = !domain_info ||
2195 domain_info->domainOrigin == VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT;
2196 const struct ir3_shader_variant *hs = builder->variants[MESA_SHADER_TESS_CTRL];
2197 const struct ir3_shader_variant *ds = builder->variants[MESA_SHADER_TESS_EVAL];
2198 pipeline->tess.param_stride = hs->output_size * 4;
2199 pipeline->tess.hs_bo_regid = hs->const_state->offsets.primitive_param + 1;
2200 pipeline->tess.ds_bo_regid = ds->const_state->offsets.primitive_param + 1;
2201 }
2202
2203 static void
2204 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder *builder,
2205 struct tu_pipeline *pipeline)
2206 {
2207 /* The spec says:
2208 *
2209 * pViewportState is a pointer to an instance of the
2210 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
2211 * pipeline has rasterization disabled."
2212 *
2213 * We leave the relevant registers stale in that case.
2214 */
2215 if (builder->rasterizer_discard)
2216 return;
2217
2218 const VkPipelineViewportStateCreateInfo *vp_info =
2219 builder->create_info->pViewportState;
2220
2221 struct tu_cs cs;
2222
2223 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_VIEWPORT, 18))
2224 tu6_emit_viewport(&cs, vp_info->pViewports);
2225
2226 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_SCISSOR, 3))
2227 tu6_emit_scissor(&cs, vp_info->pScissors);
2228 }
2229
2230 static void
2231 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder,
2232 struct tu_pipeline *pipeline)
2233 {
2234 const VkPipelineRasterizationStateCreateInfo *rast_info =
2235 builder->create_info->pRasterizationState;
2236
2237 enum a6xx_polygon_mode mode = tu6_polygon_mode(rast_info->polygonMode);
2238
2239 bool depth_clip_disable = rast_info->depthClampEnable;
2240
2241 const VkPipelineRasterizationDepthClipStateCreateInfoEXT *depth_clip_state =
2242 vk_find_struct_const(rast_info, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT);
2243 if (depth_clip_state)
2244 depth_clip_disable = !depth_clip_state->depthClipEnable;
2245
2246 struct tu_cs cs;
2247 pipeline->rast_state = tu_cs_draw_state(&pipeline->cs, &cs, 9);
2248
2249 tu_cs_emit_regs(&cs,
2250 A6XX_GRAS_CL_CNTL(
2251 .znear_clip_disable = depth_clip_disable,
2252 .zfar_clip_disable = depth_clip_disable,
2253 /* TODO should this be depth_clip_disable instead? */
2254 .unk5 = rast_info->depthClampEnable,
2255 .zero_gb_scale_z = 1,
2256 .vp_clip_code_ignore = 1));
2257
2258 tu_cs_emit_regs(&cs,
2259 A6XX_VPC_POLYGON_MODE(mode));
2260
2261 tu_cs_emit_regs(&cs,
2262 A6XX_PC_POLYGON_MODE(mode));
2263
2264 /* move to hw ctx init? */
2265 tu_cs_emit_regs(&cs,
2266 A6XX_GRAS_SU_POINT_MINMAX(.min = 1.0f / 16.0f, .max = 4092.0f),
2267 A6XX_GRAS_SU_POINT_SIZE(1.0f));
2268
2269 pipeline->gras_su_cntl =
2270 tu6_gras_su_cntl(rast_info, builder->samples);
2271
2272 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_LINE_WIDTH, 2)) {
2273 pipeline->gras_su_cntl |=
2274 A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(rast_info->lineWidth / 2.0f);
2275 tu_cs_emit_regs(&cs, A6XX_GRAS_SU_CNTL(.dword = pipeline->gras_su_cntl));
2276 }
2277
2278 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_DEPTH_BIAS, 4)) {
2279 tu6_emit_depth_bias(&cs, rast_info->depthBiasConstantFactor,
2280 rast_info->depthBiasClamp,
2281 rast_info->depthBiasSlopeFactor);
2282 }
2283
2284 }
2285
2286 static void
2287 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
2288 struct tu_pipeline *pipeline)
2289 {
2290 /* The spec says:
2291 *
2292 * pDepthStencilState is a pointer to an instance of the
2293 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
2294 * the pipeline has rasterization disabled or if the subpass of the
2295 * render pass the pipeline is created against does not use a
2296 * depth/stencil attachment.
2297 *
2298 * Disable both depth and stencil tests if there is no ds attachment,
2299 * Disable depth test if ds attachment is S8_UINT, since S8_UINT defines
2300 * only the separate stencil attachment
2301 */
2302 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info;
2303 const VkPipelineDepthStencilStateCreateInfo *ds_info =
2304 builder->depth_attachment_format != VK_FORMAT_UNDEFINED
2305 ? builder->create_info->pDepthStencilState
2306 : &dummy_ds_info;
2307 const VkPipelineDepthStencilStateCreateInfo *ds_info_depth =
2308 builder->depth_attachment_format != VK_FORMAT_S8_UINT
2309 ? ds_info : &dummy_ds_info;
2310
2311 struct tu_cs cs;
2312 pipeline->ds_state = tu_cs_draw_state(&pipeline->cs, &cs, 6);
2313
2314 /* move to hw ctx init? */
2315 tu_cs_emit_regs(&cs, A6XX_RB_ALPHA_CONTROL());
2316 tu6_emit_depth_control(&cs, ds_info_depth,
2317 builder->create_info->pRasterizationState);
2318 tu6_emit_stencil_control(&cs, ds_info);
2319
2320 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_DEPTH_BOUNDS, 3)) {
2321 tu_cs_emit_regs(&cs,
2322 A6XX_RB_Z_BOUNDS_MIN(ds_info->minDepthBounds),
2323 A6XX_RB_Z_BOUNDS_MAX(ds_info->maxDepthBounds));
2324 }
2325
2326 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK, 2)) {
2327 tu_cs_emit_regs(&cs, A6XX_RB_STENCILMASK(.mask = ds_info->front.compareMask & 0xff,
2328 .bfmask = ds_info->back.compareMask & 0xff));
2329 }
2330
2331 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_STENCIL_WRITE_MASK, 2)) {
2332 tu_cs_emit_regs(&cs, A6XX_RB_STENCILWRMASK(.wrmask = ds_info->front.writeMask & 0xff,
2333 .bfwrmask = ds_info->back.writeMask & 0xff));
2334 }
2335
2336 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_STENCIL_REFERENCE, 2)) {
2337 tu_cs_emit_regs(&cs, A6XX_RB_STENCILREF(.ref = ds_info->front.reference & 0xff,
2338 .bfref = ds_info->back.reference & 0xff));
2339 }
2340 }
2341
2342 static void
2343 tu_pipeline_builder_parse_multisample_and_color_blend(
2344 struct tu_pipeline_builder *builder, struct tu_pipeline *pipeline)
2345 {
2346 /* The spec says:
2347 *
2348 * pMultisampleState is a pointer to an instance of the
2349 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
2350 * has rasterization disabled.
2351 *
2352 * Also,
2353 *
2354 * pColorBlendState is a pointer to an instance of the
2355 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
2356 * pipeline has rasterization disabled or if the subpass of the render
2357 * pass the pipeline is created against does not use any color
2358 * attachments.
2359 *
2360 * We leave the relevant registers stale when rasterization is disabled.
2361 */
2362 if (builder->rasterizer_discard)
2363 return;
2364
2365 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info;
2366 const VkPipelineMultisampleStateCreateInfo *msaa_info =
2367 builder->create_info->pMultisampleState;
2368 const VkPipelineColorBlendStateCreateInfo *blend_info =
2369 builder->use_color_attachments ? builder->create_info->pColorBlendState
2370 : &dummy_blend_info;
2371
2372 struct tu_cs cs;
2373 pipeline->blend_state =
2374 tu_cs_draw_state(&pipeline->cs, &cs, blend_info->attachmentCount * 3 + 4);
2375
2376 uint32_t blend_enable_mask;
2377 tu6_emit_rb_mrt_controls(&cs, blend_info,
2378 builder->color_attachment_formats,
2379 &blend_enable_mask);
2380
2381 tu6_emit_blend_control(&cs, blend_enable_mask,
2382 builder->use_dual_src_blend, msaa_info);
2383
2384 assert(cs.cur == cs.end); /* validate draw state size */
2385
2386 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_BLEND_CONSTANTS, 5)) {
2387 tu_cs_emit_pkt4(&cs, REG_A6XX_RB_BLEND_RED_F32, 4);
2388 tu_cs_emit_array(&cs, (const uint32_t *) blend_info->blendConstants, 4);
2389 }
2390
2391 const struct VkPipelineSampleLocationsStateCreateInfoEXT *sample_locations =
2392 vk_find_struct_const(msaa_info->pNext, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
2393 const VkSampleLocationsInfoEXT *samp_loc = NULL;
2394
2395 if (sample_locations && sample_locations->sampleLocationsEnable)
2396 samp_loc = &sample_locations->sampleLocationsInfo;
2397
2398 if (tu_pipeline_static_state(pipeline, &cs, TU_DYNAMIC_STATE_SAMPLE_LOCATIONS,
2399 samp_loc ? 9 : 6)) {
2400 tu6_emit_sample_locations(&cs, samp_loc);
2401 }
2402 }
2403
2404 static void
2405 tu_pipeline_finish(struct tu_pipeline *pipeline,
2406 struct tu_device *dev,
2407 const VkAllocationCallbacks *alloc)
2408 {
2409 tu_cs_finish(&pipeline->cs);
2410 }
2411
2412 static VkResult
2413 tu_pipeline_builder_build(struct tu_pipeline_builder *builder,
2414 struct tu_pipeline **pipeline)
2415 {
2416 VkResult result;
2417
2418 *pipeline = vk_object_zalloc(&builder->device->vk, builder->alloc,
2419 sizeof(**pipeline), VK_OBJECT_TYPE_PIPELINE);
2420 if (!*pipeline)
2421 return VK_ERROR_OUT_OF_HOST_MEMORY;
2422
2423 (*pipeline)->layout = builder->layout;
2424
2425 /* compile and upload shaders */
2426 result = tu_pipeline_builder_compile_shaders(builder, *pipeline);
2427 if (result != VK_SUCCESS) {
2428 vk_object_free(&builder->device->vk, builder->alloc, *pipeline);
2429 return result;
2430 }
2431
2432 result = tu_pipeline_allocate_cs(builder->device, *pipeline, builder, NULL);
2433 if (result != VK_SUCCESS) {
2434 vk_object_free(&builder->device->vk, builder->alloc, *pipeline);
2435 return result;
2436 }
2437
2438 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
2439 builder->shader_iova[i] = tu_upload_variant(*pipeline, builder->variants[i]);
2440
2441 builder->binning_vs_iova =
2442 tu_upload_variant(*pipeline, builder->binning_variant);
2443
2444 tu_pipeline_builder_parse_dynamic(builder, *pipeline);
2445 tu_pipeline_builder_parse_shader_stages(builder, *pipeline);
2446 tu_pipeline_builder_parse_vertex_input(builder, *pipeline);
2447 tu_pipeline_builder_parse_input_assembly(builder, *pipeline);
2448 tu_pipeline_builder_parse_tessellation(builder, *pipeline);
2449 tu_pipeline_builder_parse_viewport(builder, *pipeline);
2450 tu_pipeline_builder_parse_rasterization(builder, *pipeline);
2451 tu_pipeline_builder_parse_depth_stencil(builder, *pipeline);
2452 tu_pipeline_builder_parse_multisample_and_color_blend(builder, *pipeline);
2453 tu6_emit_load_state(*pipeline, false);
2454
2455 /* we should have reserved enough space upfront such that the CS never
2456 * grows
2457 */
2458 assert((*pipeline)->cs.bo_count == 1);
2459
2460 return VK_SUCCESS;
2461 }
2462
2463 static void
2464 tu_pipeline_builder_finish(struct tu_pipeline_builder *builder)
2465 {
2466 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
2467 if (!builder->shaders[i])
2468 continue;
2469 tu_shader_destroy(builder->device, builder->shaders[i], builder->alloc);
2470 }
2471 }
2472
2473 static void
2474 tu_pipeline_builder_init_graphics(
2475 struct tu_pipeline_builder *builder,
2476 struct tu_device *dev,
2477 struct tu_pipeline_cache *cache,
2478 const VkGraphicsPipelineCreateInfo *create_info,
2479 const VkAllocationCallbacks *alloc)
2480 {
2481 TU_FROM_HANDLE(tu_pipeline_layout, layout, create_info->layout);
2482
2483 *builder = (struct tu_pipeline_builder) {
2484 .device = dev,
2485 .cache = cache,
2486 .create_info = create_info,
2487 .alloc = alloc,
2488 .layout = layout,
2489 };
2490
2491 builder->rasterizer_discard =
2492 create_info->pRasterizationState->rasterizerDiscardEnable;
2493
2494 if (builder->rasterizer_discard) {
2495 builder->samples = VK_SAMPLE_COUNT_1_BIT;
2496 } else {
2497 builder->samples = create_info->pMultisampleState->rasterizationSamples;
2498
2499 const struct tu_render_pass *pass =
2500 tu_render_pass_from_handle(create_info->renderPass);
2501 const struct tu_subpass *subpass =
2502 &pass->subpasses[create_info->subpass];
2503
2504 const uint32_t a = subpass->depth_stencil_attachment.attachment;
2505 builder->depth_attachment_format = (a != VK_ATTACHMENT_UNUSED) ?
2506 pass->attachments[a].format : VK_FORMAT_UNDEFINED;
2507
2508 assert(subpass->color_count == 0 ||
2509 !create_info->pColorBlendState ||
2510 subpass->color_count == create_info->pColorBlendState->attachmentCount);
2511 builder->color_attachment_count = subpass->color_count;
2512 for (uint32_t i = 0; i < subpass->color_count; i++) {
2513 const uint32_t a = subpass->color_attachments[i].attachment;
2514 if (a == VK_ATTACHMENT_UNUSED)
2515 continue;
2516
2517 builder->color_attachment_formats[i] = pass->attachments[a].format;
2518 builder->use_color_attachments = true;
2519 builder->render_components |= 0xf << (i * 4);
2520 }
2521
2522 if (tu_blend_state_is_dual_src(create_info->pColorBlendState)) {
2523 builder->color_attachment_count++;
2524 builder->use_dual_src_blend = true;
2525 /* dual source blending has an extra fs output in the 2nd slot */
2526 if (subpass->color_attachments[0].attachment != VK_ATTACHMENT_UNUSED)
2527 builder->render_components |= 0xf << 4;
2528 }
2529 }
2530 }
2531
2532 static VkResult
2533 tu_graphics_pipeline_create(VkDevice device,
2534 VkPipelineCache pipelineCache,
2535 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2536 const VkAllocationCallbacks *pAllocator,
2537 VkPipeline *pPipeline)
2538 {
2539 TU_FROM_HANDLE(tu_device, dev, device);
2540 TU_FROM_HANDLE(tu_pipeline_cache, cache, pipelineCache);
2541
2542 struct tu_pipeline_builder builder;
2543 tu_pipeline_builder_init_graphics(&builder, dev, cache,
2544 pCreateInfo, pAllocator);
2545
2546 struct tu_pipeline *pipeline = NULL;
2547 VkResult result = tu_pipeline_builder_build(&builder, &pipeline);
2548 tu_pipeline_builder_finish(&builder);
2549
2550 if (result == VK_SUCCESS)
2551 *pPipeline = tu_pipeline_to_handle(pipeline);
2552 else
2553 *pPipeline = VK_NULL_HANDLE;
2554
2555 return result;
2556 }
2557
2558 VkResult
2559 tu_CreateGraphicsPipelines(VkDevice device,
2560 VkPipelineCache pipelineCache,
2561 uint32_t count,
2562 const VkGraphicsPipelineCreateInfo *pCreateInfos,
2563 const VkAllocationCallbacks *pAllocator,
2564 VkPipeline *pPipelines)
2565 {
2566 VkResult final_result = VK_SUCCESS;
2567
2568 for (uint32_t i = 0; i < count; i++) {
2569 VkResult result = tu_graphics_pipeline_create(device, pipelineCache,
2570 &pCreateInfos[i], pAllocator,
2571 &pPipelines[i]);
2572
2573 if (result != VK_SUCCESS)
2574 final_result = result;
2575 }
2576
2577 return final_result;
2578 }
2579
2580 static VkResult
2581 tu_compute_pipeline_create(VkDevice device,
2582 VkPipelineCache _cache,
2583 const VkComputePipelineCreateInfo *pCreateInfo,
2584 const VkAllocationCallbacks *pAllocator,
2585 VkPipeline *pPipeline)
2586 {
2587 TU_FROM_HANDLE(tu_device, dev, device);
2588 TU_FROM_HANDLE(tu_pipeline_layout, layout, pCreateInfo->layout);
2589 const VkPipelineShaderStageCreateInfo *stage_info = &pCreateInfo->stage;
2590 VkResult result;
2591
2592 struct tu_pipeline *pipeline;
2593
2594 *pPipeline = VK_NULL_HANDLE;
2595
2596 pipeline = vk_object_zalloc(&dev->vk, pAllocator, sizeof(*pipeline),
2597 VK_OBJECT_TYPE_PIPELINE);
2598 if (!pipeline)
2599 return VK_ERROR_OUT_OF_HOST_MEMORY;
2600
2601 pipeline->layout = layout;
2602
2603 struct ir3_shader_key key = {};
2604
2605 struct tu_shader *shader =
2606 tu_shader_create(dev, MESA_SHADER_COMPUTE, stage_info, layout, pAllocator);
2607 if (!shader) {
2608 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2609 goto fail;
2610 }
2611
2612 pipeline->active_desc_sets = shader->active_desc_sets;
2613
2614 bool created;
2615 struct ir3_shader_variant *v =
2616 ir3_shader_get_variant(shader->ir3_shader, &key, false, &created);
2617 if (!v) {
2618 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2619 goto fail;
2620 }
2621
2622 tu_pipeline_set_linkage(&pipeline->program.link[MESA_SHADER_COMPUTE],
2623 shader, v);
2624
2625 result = tu_pipeline_allocate_cs(dev, pipeline, NULL, v);
2626 if (result != VK_SUCCESS)
2627 goto fail;
2628
2629 uint64_t shader_iova = tu_upload_variant(pipeline, v);
2630
2631 for (int i = 0; i < 3; i++)
2632 pipeline->compute.local_size[i] = v->shader->nir->info.cs.local_size[i];
2633
2634 struct tu_cs prog_cs;
2635 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2636 tu6_emit_cs_config(&prog_cs, shader, v, shader_iova);
2637 pipeline->program.state = tu_cs_end_draw_state(&pipeline->cs, &prog_cs);
2638
2639 tu6_emit_load_state(pipeline, true);
2640
2641 *pPipeline = tu_pipeline_to_handle(pipeline);
2642 return VK_SUCCESS;
2643
2644 fail:
2645 if (shader)
2646 tu_shader_destroy(dev, shader, pAllocator);
2647
2648 vk_object_free(&dev->vk, pAllocator, pipeline);
2649
2650 return result;
2651 }
2652
2653 VkResult
2654 tu_CreateComputePipelines(VkDevice device,
2655 VkPipelineCache pipelineCache,
2656 uint32_t count,
2657 const VkComputePipelineCreateInfo *pCreateInfos,
2658 const VkAllocationCallbacks *pAllocator,
2659 VkPipeline *pPipelines)
2660 {
2661 VkResult final_result = VK_SUCCESS;
2662
2663 for (uint32_t i = 0; i < count; i++) {
2664 VkResult result = tu_compute_pipeline_create(device, pipelineCache,
2665 &pCreateInfos[i],
2666 pAllocator, &pPipelines[i]);
2667 if (result != VK_SUCCESS)
2668 final_result = result;
2669 }
2670
2671 return final_result;
2672 }
2673
2674 void
2675 tu_DestroyPipeline(VkDevice _device,
2676 VkPipeline _pipeline,
2677 const VkAllocationCallbacks *pAllocator)
2678 {
2679 TU_FROM_HANDLE(tu_device, dev, _device);
2680 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
2681
2682 if (!_pipeline)
2683 return;
2684
2685 tu_pipeline_finish(pipeline, dev, pAllocator);
2686 vk_object_free(&dev->vk, pAllocator, pipeline);
2687 }