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tu: Implement multiview pipeline state
[mesa.git] / src / freedreno / vulkan / tu_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "common/freedreno_guardband.h"
29 #include "tu_private.h"
30
31 #include "ir3/ir3_nir.h"
32 #include "main/menums.h"
33 #include "nir/nir.h"
34 #include "nir/nir_builder.h"
35 #include "spirv/nir_spirv.h"
36 #include "util/debug.h"
37 #include "util/mesa-sha1.h"
38 #include "util/u_atomic.h"
39 #include "vk_format.h"
40 #include "vk_util.h"
41
42 #include "tu_cs.h"
43
44 /* Emit IB that preloads the descriptors that the shader uses */
45
46 static void
47 emit_load_state(struct tu_cs *cs, unsigned opcode, enum a6xx_state_type st,
48 enum a6xx_state_block sb, unsigned base, unsigned offset,
49 unsigned count)
50 {
51 /* Note: just emit one packet, even if count overflows NUM_UNIT. It's not
52 * clear if emitting more packets will even help anything. Presumably the
53 * descriptor cache is relatively small, and these packets stop doing
54 * anything when there are too many descriptors.
55 */
56 tu_cs_emit_pkt7(cs, opcode, 3);
57 tu_cs_emit(cs,
58 CP_LOAD_STATE6_0_STATE_TYPE(st) |
59 CP_LOAD_STATE6_0_STATE_SRC(SS6_BINDLESS) |
60 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
61 CP_LOAD_STATE6_0_NUM_UNIT(MIN2(count, 1024-1)));
62 tu_cs_emit_qw(cs, offset | (base << 28));
63 }
64
65 static unsigned
66 tu6_load_state_size(struct tu_pipeline *pipeline, bool compute)
67 {
68 const unsigned load_state_size = 4;
69 unsigned size = 0;
70 for (unsigned i = 0; i < pipeline->layout->num_sets; i++) {
71 if (pipeline && !(pipeline->active_desc_sets & (1u << i)))
72 continue;
73
74 struct tu_descriptor_set_layout *set_layout = pipeline->layout->set[i].layout;
75 for (unsigned j = 0; j < set_layout->binding_count; j++) {
76 struct tu_descriptor_set_binding_layout *binding = &set_layout->binding[j];
77 unsigned count = 0;
78 /* Note: some users, like amber for example, pass in
79 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
80 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
81 */
82 VkShaderStageFlags stages = compute ?
83 binding->shader_stages & VK_SHADER_STAGE_COMPUTE_BIT :
84 binding->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
85 unsigned stage_count = util_bitcount(stages);
86
87 if (!binding->array_size)
88 continue;
89
90 switch (binding->type) {
91 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
92 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
93 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
94 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
95 /* IBO-backed resources only need one packet for all graphics stages */
96 if (stages & ~VK_SHADER_STAGE_COMPUTE_BIT)
97 count += 1;
98 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
99 count += 1;
100 break;
101 case VK_DESCRIPTOR_TYPE_SAMPLER:
102 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
103 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
104 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
105 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
106 /* Textures and UBO's needs a packet for each stage */
107 count = stage_count;
108 break;
109 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
110 /* Because of how we pack combined images and samplers, we
111 * currently can't use one packet for the whole array.
112 */
113 count = stage_count * binding->array_size * 2;
114 break;
115 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
116 break;
117 default:
118 unreachable("bad descriptor type");
119 }
120 size += count * load_state_size;
121 }
122 }
123 return size;
124 }
125
126 static void
127 tu6_emit_load_state(struct tu_pipeline *pipeline, bool compute)
128 {
129 unsigned size = tu6_load_state_size(pipeline, compute);
130 if (size == 0)
131 return;
132
133 struct tu_cs cs;
134 tu_cs_begin_sub_stream(&pipeline->cs, size, &cs);
135
136 struct tu_pipeline_layout *layout = pipeline->layout;
137 for (unsigned i = 0; i < layout->num_sets; i++) {
138 /* From 13.2.7. Descriptor Set Binding:
139 *
140 * A compatible descriptor set must be bound for all set numbers that
141 * any shaders in a pipeline access, at the time that a draw or
142 * dispatch command is recorded to execute using that pipeline.
143 * However, if none of the shaders in a pipeline statically use any
144 * bindings with a particular set number, then no descriptor set need
145 * be bound for that set number, even if the pipeline layout includes
146 * a non-trivial descriptor set layout for that set number.
147 *
148 * This means that descriptor sets unused by the pipeline may have a
149 * garbage or 0 BINDLESS_BASE register, which will cause context faults
150 * when prefetching descriptors from these sets. Skip prefetching for
151 * descriptors from them to avoid this. This is also an optimization,
152 * since these prefetches would be useless.
153 */
154 if (!(pipeline->active_desc_sets & (1u << i)))
155 continue;
156
157 struct tu_descriptor_set_layout *set_layout = layout->set[i].layout;
158 for (unsigned j = 0; j < set_layout->binding_count; j++) {
159 struct tu_descriptor_set_binding_layout *binding = &set_layout->binding[j];
160 unsigned base = i;
161 unsigned offset = binding->offset / 4;
162 /* Note: some users, like amber for example, pass in
163 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
164 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
165 */
166 VkShaderStageFlags stages = compute ?
167 binding->shader_stages & VK_SHADER_STAGE_COMPUTE_BIT :
168 binding->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
169 unsigned count = binding->array_size;
170 if (count == 0 || stages == 0)
171 continue;
172 switch (binding->type) {
173 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
174 base = MAX_SETS;
175 offset = (layout->set[i].dynamic_offset_start +
176 binding->dynamic_offset_offset) * A6XX_TEX_CONST_DWORDS;
177 /* fallthrough */
178 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
179 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
180 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
181 /* IBO-backed resources only need one packet for all graphics stages */
182 if (stages & ~VK_SHADER_STAGE_COMPUTE_BIT) {
183 emit_load_state(&cs, CP_LOAD_STATE6, ST6_SHADER, SB6_IBO,
184 base, offset, count);
185 }
186 if (stages & VK_SHADER_STAGE_COMPUTE_BIT) {
187 emit_load_state(&cs, CP_LOAD_STATE6_FRAG, ST6_IBO, SB6_CS_SHADER,
188 base, offset, count);
189 }
190 break;
191 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
192 /* nothing - input attachment doesn't use bindless */
193 break;
194 case VK_DESCRIPTOR_TYPE_SAMPLER:
195 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
196 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER: {
197 tu_foreach_stage(stage, stages) {
198 emit_load_state(&cs, tu6_stage2opcode(stage),
199 binding->type == VK_DESCRIPTOR_TYPE_SAMPLER ?
200 ST6_SHADER : ST6_CONSTANTS,
201 tu6_stage2texsb(stage), base, offset, count);
202 }
203 break;
204 }
205 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
206 base = MAX_SETS;
207 offset = (layout->set[i].dynamic_offset_start +
208 binding->dynamic_offset_offset) * A6XX_TEX_CONST_DWORDS;
209 /* fallthrough */
210 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER: {
211 tu_foreach_stage(stage, stages) {
212 emit_load_state(&cs, tu6_stage2opcode(stage), ST6_UBO,
213 tu6_stage2shadersb(stage), base, offset, count);
214 }
215 break;
216 }
217 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER: {
218 tu_foreach_stage(stage, stages) {
219 /* TODO: We could emit less CP_LOAD_STATE6 if we used
220 * struct-of-arrays instead of array-of-structs.
221 */
222 for (unsigned i = 0; i < count; i++) {
223 unsigned tex_offset = offset + 2 * i * A6XX_TEX_CONST_DWORDS;
224 unsigned sam_offset = offset + (2 * i + 1) * A6XX_TEX_CONST_DWORDS;
225 emit_load_state(&cs, tu6_stage2opcode(stage),
226 ST6_CONSTANTS, tu6_stage2texsb(stage),
227 base, tex_offset, 1);
228 emit_load_state(&cs, tu6_stage2opcode(stage),
229 ST6_SHADER, tu6_stage2texsb(stage),
230 base, sam_offset, 1);
231 }
232 }
233 break;
234 }
235 default:
236 unreachable("bad descriptor type");
237 }
238 }
239 }
240
241 pipeline->load_state = tu_cs_end_draw_state(&pipeline->cs, &cs);
242 }
243
244 struct tu_pipeline_builder
245 {
246 struct tu_device *device;
247 struct tu_pipeline_cache *cache;
248 struct tu_pipeline_layout *layout;
249 const VkAllocationCallbacks *alloc;
250 const VkGraphicsPipelineCreateInfo *create_info;
251
252 struct tu_shader *shaders[MESA_SHADER_STAGES];
253 struct ir3_shader_variant *variants[MESA_SHADER_STAGES];
254 struct ir3_shader_variant *binning_variant;
255 uint64_t shader_iova[MESA_SHADER_STAGES];
256 uint64_t binning_vs_iova;
257
258 bool rasterizer_discard;
259 /* these states are affectd by rasterizer_discard */
260 VkSampleCountFlagBits samples;
261 bool use_color_attachments;
262 bool use_dual_src_blend;
263 uint32_t color_attachment_count;
264 VkFormat color_attachment_formats[MAX_RTS];
265 VkFormat depth_attachment_format;
266 uint32_t render_components;
267 uint32_t multiview_mask;
268 };
269
270 static bool
271 tu_logic_op_reads_dst(VkLogicOp op)
272 {
273 switch (op) {
274 case VK_LOGIC_OP_CLEAR:
275 case VK_LOGIC_OP_COPY:
276 case VK_LOGIC_OP_COPY_INVERTED:
277 case VK_LOGIC_OP_SET:
278 return false;
279 default:
280 return true;
281 }
282 }
283
284 static VkBlendFactor
285 tu_blend_factor_no_dst_alpha(VkBlendFactor factor)
286 {
287 /* treat dst alpha as 1.0 and avoid reading it */
288 switch (factor) {
289 case VK_BLEND_FACTOR_DST_ALPHA:
290 return VK_BLEND_FACTOR_ONE;
291 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
292 return VK_BLEND_FACTOR_ZERO;
293 default:
294 return factor;
295 }
296 }
297
298 static bool tu_blend_factor_is_dual_src(VkBlendFactor factor)
299 {
300 switch (factor) {
301 case VK_BLEND_FACTOR_SRC1_COLOR:
302 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
303 case VK_BLEND_FACTOR_SRC1_ALPHA:
304 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
305 return true;
306 default:
307 return false;
308 }
309 }
310
311 static bool
312 tu_blend_state_is_dual_src(const VkPipelineColorBlendStateCreateInfo *info)
313 {
314 if (!info)
315 return false;
316
317 for (unsigned i = 0; i < info->attachmentCount; i++) {
318 const VkPipelineColorBlendAttachmentState *blend = &info->pAttachments[i];
319 if (tu_blend_factor_is_dual_src(blend->srcColorBlendFactor) ||
320 tu_blend_factor_is_dual_src(blend->dstColorBlendFactor) ||
321 tu_blend_factor_is_dual_src(blend->srcAlphaBlendFactor) ||
322 tu_blend_factor_is_dual_src(blend->dstAlphaBlendFactor))
323 return true;
324 }
325
326 return false;
327 }
328
329 void
330 tu6_emit_xs_config(struct tu_cs *cs,
331 gl_shader_stage stage, /* xs->type, but xs may be NULL */
332 const struct ir3_shader_variant *xs,
333 uint64_t binary_iova)
334 {
335 static const struct xs_config {
336 uint16_t reg_sp_xs_ctrl;
337 uint16_t reg_sp_xs_config;
338 uint16_t reg_hlsq_xs_ctrl;
339 uint16_t reg_sp_vs_obj_start;
340 } xs_config[] = {
341 [MESA_SHADER_VERTEX] = {
342 REG_A6XX_SP_VS_CTRL_REG0,
343 REG_A6XX_SP_VS_CONFIG,
344 REG_A6XX_HLSQ_VS_CNTL,
345 REG_A6XX_SP_VS_OBJ_START_LO,
346 },
347 [MESA_SHADER_TESS_CTRL] = {
348 REG_A6XX_SP_HS_CTRL_REG0,
349 REG_A6XX_SP_HS_CONFIG,
350 REG_A6XX_HLSQ_HS_CNTL,
351 REG_A6XX_SP_HS_OBJ_START_LO,
352 },
353 [MESA_SHADER_TESS_EVAL] = {
354 REG_A6XX_SP_DS_CTRL_REG0,
355 REG_A6XX_SP_DS_CONFIG,
356 REG_A6XX_HLSQ_DS_CNTL,
357 REG_A6XX_SP_DS_OBJ_START_LO,
358 },
359 [MESA_SHADER_GEOMETRY] = {
360 REG_A6XX_SP_GS_CTRL_REG0,
361 REG_A6XX_SP_GS_CONFIG,
362 REG_A6XX_HLSQ_GS_CNTL,
363 REG_A6XX_SP_GS_OBJ_START_LO,
364 },
365 [MESA_SHADER_FRAGMENT] = {
366 REG_A6XX_SP_FS_CTRL_REG0,
367 REG_A6XX_SP_FS_CONFIG,
368 REG_A6XX_HLSQ_FS_CNTL,
369 REG_A6XX_SP_FS_OBJ_START_LO,
370 },
371 [MESA_SHADER_COMPUTE] = {
372 REG_A6XX_SP_CS_CTRL_REG0,
373 REG_A6XX_SP_CS_CONFIG,
374 REG_A6XX_HLSQ_CS_CNTL,
375 REG_A6XX_SP_CS_OBJ_START_LO,
376 },
377 };
378 const struct xs_config *cfg = &xs_config[stage];
379
380 if (!xs) {
381 /* shader stage disabled */
382 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_config, 1);
383 tu_cs_emit(cs, 0);
384
385 tu_cs_emit_pkt4(cs, cfg->reg_hlsq_xs_ctrl, 1);
386 tu_cs_emit(cs, 0);
387 return;
388 }
389
390 bool is_fs = xs->type == MESA_SHADER_FRAGMENT;
391 enum a3xx_threadsize threadsize = FOUR_QUADS;
392
393 /* TODO:
394 * the "threadsize" field may have nothing to do with threadsize,
395 * use a value that matches the blob until it is figured out
396 */
397 if (xs->type == MESA_SHADER_GEOMETRY)
398 threadsize = TWO_QUADS;
399
400 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_ctrl, 1);
401 tu_cs_emit(cs,
402 A6XX_SP_VS_CTRL_REG0_THREADSIZE(threadsize) |
403 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(xs->info.max_reg + 1) |
404 A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(xs->info.max_half_reg + 1) |
405 COND(xs->mergedregs, A6XX_SP_VS_CTRL_REG0_MERGEDREGS) |
406 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(xs->branchstack) |
407 COND(xs->need_pixlod, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE) |
408 COND(xs->need_fine_derivatives, A6XX_SP_VS_CTRL_REG0_DIFF_FINE) |
409 /* only fragment shader sets VARYING bit */
410 COND(xs->total_in && is_fs, A6XX_SP_FS_CTRL_REG0_VARYING) |
411 /* unknown bit, seems unnecessary */
412 COND(is_fs, 0x1000000));
413
414 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_config, 2);
415 tu_cs_emit(cs, A6XX_SP_VS_CONFIG_ENABLED |
416 COND(xs->bindless_tex, A6XX_SP_VS_CONFIG_BINDLESS_TEX) |
417 COND(xs->bindless_samp, A6XX_SP_VS_CONFIG_BINDLESS_SAMP) |
418 COND(xs->bindless_ibo, A6XX_SP_VS_CONFIG_BINDLESS_IBO) |
419 COND(xs->bindless_ubo, A6XX_SP_VS_CONFIG_BINDLESS_UBO) |
420 A6XX_SP_VS_CONFIG_NTEX(xs->num_samp) |
421 A6XX_SP_VS_CONFIG_NSAMP(xs->num_samp));
422 tu_cs_emit(cs, xs->instrlen);
423
424 tu_cs_emit_pkt4(cs, cfg->reg_hlsq_xs_ctrl, 1);
425 tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(xs->constlen) |
426 A6XX_HLSQ_VS_CNTL_ENABLED);
427
428 /* emit program binary
429 * binary_iova should be aligned to 1 instrlen unit (128 bytes)
430 */
431
432 assert((binary_iova & 0x7f) == 0);
433
434 tu_cs_emit_pkt4(cs, cfg->reg_sp_vs_obj_start, 2);
435 tu_cs_emit_qw(cs, binary_iova);
436
437 tu_cs_emit_pkt7(cs, tu6_stage2opcode(stage), 3);
438 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
439 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
440 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
441 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(stage)) |
442 CP_LOAD_STATE6_0_NUM_UNIT(xs->instrlen));
443 tu_cs_emit_qw(cs, binary_iova);
444
445 /* emit immediates */
446
447 const struct ir3_const_state *const_state = ir3_const_state(xs);
448 uint32_t base = const_state->offsets.immediate;
449 int size = DIV_ROUND_UP(const_state->immediates_count, 4);
450
451 /* truncate size to avoid writing constants that shader
452 * does not use:
453 */
454 size = MIN2(size + base, xs->constlen) - base;
455
456 if (size <= 0)
457 return;
458
459 tu_cs_emit_pkt7(cs, tu6_stage2opcode(stage), 3 + size * 4);
460 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
461 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
462 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
463 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(stage)) |
464 CP_LOAD_STATE6_0_NUM_UNIT(size));
465 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
466 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
467
468 tu_cs_emit_array(cs, const_state->immediates, size * 4);
469 }
470
471 static void
472 tu6_emit_cs_config(struct tu_cs *cs, const struct tu_shader *shader,
473 const struct ir3_shader_variant *v,
474 uint32_t binary_iova)
475 {
476 tu_cs_emit_regs(cs, A6XX_HLSQ_INVALIDATE_CMD(
477 .cs_state = true,
478 .cs_ibo = true));
479
480 tu6_emit_xs_config(cs, MESA_SHADER_COMPUTE, v, binary_iova);
481
482 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_UNKNOWN_A9B1, 1);
483 tu_cs_emit(cs, 0x41);
484
485 uint32_t local_invocation_id =
486 ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
487 uint32_t work_group_id =
488 ir3_find_sysval_regid(v, SYSTEM_VALUE_WORK_GROUP_ID);
489
490 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL_0, 2);
491 tu_cs_emit(cs,
492 A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) |
493 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
494 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
495 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
496 tu_cs_emit(cs, 0x2fc); /* HLSQ_CS_UNKNOWN_B998 */
497 }
498
499 static void
500 tu6_emit_vs_system_values(struct tu_cs *cs,
501 const struct ir3_shader_variant *vs,
502 const struct ir3_shader_variant *hs,
503 const struct ir3_shader_variant *ds,
504 const struct ir3_shader_variant *gs,
505 bool primid_passthru)
506 {
507 const uint32_t vertexid_regid =
508 ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
509 const uint32_t instanceid_regid =
510 ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
511 const uint32_t tess_coord_x_regid = hs ?
512 ir3_find_sysval_regid(ds, SYSTEM_VALUE_TESS_COORD) :
513 regid(63, 0);
514 const uint32_t tess_coord_y_regid = VALIDREG(tess_coord_x_regid) ?
515 tess_coord_x_regid + 1 :
516 regid(63, 0);
517 const uint32_t hs_patch_regid = hs ?
518 ir3_find_sysval_regid(hs, SYSTEM_VALUE_PRIMITIVE_ID) :
519 regid(63, 0);
520 const uint32_t ds_patch_regid = hs ?
521 ir3_find_sysval_regid(ds, SYSTEM_VALUE_PRIMITIVE_ID) :
522 regid(63, 0);
523 const uint32_t hs_invocation_regid = hs ?
524 ir3_find_sysval_regid(hs, SYSTEM_VALUE_TCS_HEADER_IR3) :
525 regid(63, 0);
526 const uint32_t primitiveid_regid = gs ?
527 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID) :
528 regid(63, 0);
529 const uint32_t gsheader_regid = gs ?
530 ir3_find_sysval_regid(gs, SYSTEM_VALUE_GS_HEADER_IR3) :
531 regid(63, 0);
532
533 /* Note: we currently don't support multiview with tess or GS. If we did,
534 * and the HW actually works, then we'd have to somehow share this across
535 * stages. Note that the blob doesn't support this either.
536 */
537 const uint32_t viewid_regid =
538 ir3_find_sysval_regid(vs, SYSTEM_VALUE_VIEW_INDEX);
539
540 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_1, 6);
541 tu_cs_emit(cs, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid) |
542 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid) |
543 A6XX_VFD_CONTROL_1_REGID4PRIMID(primitiveid_regid) |
544 A6XX_VFD_CONTROL_1_REGID4VIEWID(viewid_regid));
545 tu_cs_emit(cs, A6XX_VFD_CONTROL_2_REGID_HSPATCHID(hs_patch_regid) |
546 A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(hs_invocation_regid));
547 tu_cs_emit(cs, A6XX_VFD_CONTROL_3_REGID_DSPATCHID(ds_patch_regid) |
548 A6XX_VFD_CONTROL_3_REGID_TESSX(tess_coord_x_regid) |
549 A6XX_VFD_CONTROL_3_REGID_TESSY(tess_coord_y_regid) |
550 0xfc);
551 tu_cs_emit(cs, 0x000000fc); /* VFD_CONTROL_4 */
552 tu_cs_emit(cs, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gsheader_regid) |
553 0xfc00); /* VFD_CONTROL_5 */
554 tu_cs_emit(cs, COND(primid_passthru, A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU)); /* VFD_CONTROL_6 */
555 }
556
557 /* Add any missing varyings needed for stream-out. Otherwise varyings not
558 * used by fragment shader will be stripped out.
559 */
560 static void
561 tu6_link_streamout(struct ir3_shader_linkage *l,
562 const struct ir3_shader_variant *v)
563 {
564 const struct ir3_stream_output_info *info = &v->shader->stream_output;
565
566 /*
567 * First, any stream-out varyings not already in linkage map (ie. also
568 * consumed by frag shader) need to be added:
569 */
570 for (unsigned i = 0; i < info->num_outputs; i++) {
571 const struct ir3_stream_output *out = &info->output[i];
572 unsigned compmask =
573 (1 << (out->num_components + out->start_component)) - 1;
574 unsigned k = out->register_index;
575 unsigned idx, nextloc = 0;
576
577 /* psize/pos need to be the last entries in linkage map, and will
578 * get added link_stream_out, so skip over them:
579 */
580 if (v->outputs[k].slot == VARYING_SLOT_PSIZ ||
581 v->outputs[k].slot == VARYING_SLOT_POS)
582 continue;
583
584 for (idx = 0; idx < l->cnt; idx++) {
585 if (l->var[idx].regid == v->outputs[k].regid)
586 break;
587 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
588 }
589
590 /* add if not already in linkage map: */
591 if (idx == l->cnt)
592 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
593
594 /* expand component-mask if needed, ie streaming out all components
595 * but frag shader doesn't consume all components:
596 */
597 if (compmask & ~l->var[idx].compmask) {
598 l->var[idx].compmask |= compmask;
599 l->max_loc = MAX2(l->max_loc, l->var[idx].loc +
600 util_last_bit(l->var[idx].compmask));
601 }
602 }
603 }
604
605 static void
606 tu6_setup_streamout(struct tu_cs *cs,
607 const struct ir3_shader_variant *v,
608 struct ir3_shader_linkage *l)
609 {
610 const struct ir3_stream_output_info *info = &v->shader->stream_output;
611 uint32_t prog[IR3_MAX_SO_OUTPUTS * 2] = {};
612 uint32_t ncomp[IR3_MAX_SO_BUFFERS] = {};
613 uint32_t prog_count = align(l->max_loc, 2) / 2;
614
615 /* TODO: streamout state should be in a non-GMEM draw state */
616
617 /* no streamout: */
618 if (info->num_outputs == 0) {
619 tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 4);
620 tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
621 tu_cs_emit(cs, 0);
622 tu_cs_emit(cs, REG_A6XX_VPC_SO_BUF_CNTL);
623 tu_cs_emit(cs, 0);
624 return;
625 }
626
627 /* is there something to do with info->stride[i]? */
628
629 for (unsigned i = 0; i < info->num_outputs; i++) {
630 const struct ir3_stream_output *out = &info->output[i];
631 unsigned k = out->register_index;
632 unsigned idx;
633
634 /* Skip it, if there's an unused reg in the middle of outputs. */
635 if (v->outputs[k].regid == INVALID_REG)
636 continue;
637
638 ncomp[out->output_buffer] += out->num_components;
639
640 /* linkage map sorted by order frag shader wants things, so
641 * a bit less ideal here..
642 */
643 for (idx = 0; idx < l->cnt; idx++)
644 if (l->var[idx].regid == v->outputs[k].regid)
645 break;
646
647 debug_assert(idx < l->cnt);
648
649 for (unsigned j = 0; j < out->num_components; j++) {
650 unsigned c = j + out->start_component;
651 unsigned loc = l->var[idx].loc + c;
652 unsigned off = j + out->dst_offset; /* in dwords */
653
654 if (loc & 1) {
655 prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
656 A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
657 A6XX_VPC_SO_PROG_B_OFF(off * 4);
658 } else {
659 prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
660 A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
661 A6XX_VPC_SO_PROG_A_OFF(off * 4);
662 }
663 }
664 }
665
666 tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 12 + 2 * prog_count);
667 tu_cs_emit(cs, REG_A6XX_VPC_SO_BUF_CNTL);
668 tu_cs_emit(cs, A6XX_VPC_SO_BUF_CNTL_ENABLE |
669 COND(ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
670 COND(ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
671 COND(ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
672 COND(ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3));
673 for (uint32_t i = 0; i < 4; i++) {
674 tu_cs_emit(cs, REG_A6XX_VPC_SO_NCOMP(i));
675 tu_cs_emit(cs, ncomp[i]);
676 }
677 /* note: "VPC_SO_CNTL" write seems to be responsible for resetting the SO_PROG */
678 tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
679 tu_cs_emit(cs, A6XX_VPC_SO_CNTL_ENABLE);
680 for (uint32_t i = 0; i < prog_count; i++) {
681 tu_cs_emit(cs, REG_A6XX_VPC_SO_PROG);
682 tu_cs_emit(cs, prog[i]);
683 }
684 }
685
686 static void
687 tu6_emit_const(struct tu_cs *cs, uint32_t opcode, uint32_t base,
688 enum a6xx_state_block block, uint32_t offset,
689 uint32_t size, uint32_t *dwords) {
690 assert(size % 4 == 0);
691
692 tu_cs_emit_pkt7(cs, opcode, 3 + size);
693 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
694 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
695 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
696 CP_LOAD_STATE6_0_STATE_BLOCK(block) |
697 CP_LOAD_STATE6_0_NUM_UNIT(size / 4));
698
699 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
700 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
701 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
702
703 tu_cs_emit_array(cs, dwords, size);
704 }
705
706 static void
707 tu6_emit_link_map(struct tu_cs *cs,
708 const struct ir3_shader_variant *producer,
709 const struct ir3_shader_variant *consumer,
710 enum a6xx_state_block sb)
711 {
712 const struct ir3_const_state *const_state = ir3_const_state(consumer);
713 uint32_t base = const_state->offsets.primitive_map;
714 uint32_t patch_locs[MAX_VARYING] = { }, num_loc;
715 num_loc = ir3_link_geometry_stages(producer, consumer, patch_locs);
716 int size = DIV_ROUND_UP(num_loc, 4);
717
718 size = (MIN2(size + base, consumer->constlen) - base) * 4;
719 if (size <= 0)
720 return;
721
722 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, base, sb, 0, size,
723 patch_locs);
724 }
725
726 static uint16_t
727 gl_primitive_to_tess(uint16_t primitive) {
728 switch (primitive) {
729 case GL_POINTS:
730 return TESS_POINTS;
731 case GL_LINE_STRIP:
732 return TESS_LINES;
733 case GL_TRIANGLE_STRIP:
734 return TESS_CW_TRIS;
735 default:
736 unreachable("");
737 }
738 }
739
740 void
741 tu6_emit_vpc(struct tu_cs *cs,
742 const struct ir3_shader_variant *vs,
743 const struct ir3_shader_variant *hs,
744 const struct ir3_shader_variant *ds,
745 const struct ir3_shader_variant *gs,
746 const struct ir3_shader_variant *fs,
747 uint32_t patch_control_points,
748 bool vshs_workgroup)
749 {
750 /* note: doesn't compile as static because of the array regs.. */
751 const struct reg_config {
752 uint16_t reg_sp_xs_out_reg;
753 uint16_t reg_sp_xs_vpc_dst_reg;
754 uint16_t reg_vpc_xs_pack;
755 uint16_t reg_vpc_xs_clip_cntl;
756 uint16_t reg_gras_xs_cl_cntl;
757 uint16_t reg_pc_xs_out_cntl;
758 uint16_t reg_sp_xs_primitive_cntl;
759 uint16_t reg_vpc_xs_layer_cntl;
760 uint16_t reg_gras_xs_layer_cntl;
761 } reg_config[] = {
762 [MESA_SHADER_VERTEX] = {
763 REG_A6XX_SP_VS_OUT_REG(0),
764 REG_A6XX_SP_VS_VPC_DST_REG(0),
765 REG_A6XX_VPC_VS_PACK,
766 REG_A6XX_VPC_VS_CLIP_CNTL,
767 REG_A6XX_GRAS_VS_CL_CNTL,
768 REG_A6XX_PC_VS_OUT_CNTL,
769 REG_A6XX_SP_VS_PRIMITIVE_CNTL,
770 REG_A6XX_VPC_VS_LAYER_CNTL,
771 REG_A6XX_GRAS_VS_LAYER_CNTL
772 },
773 [MESA_SHADER_TESS_EVAL] = {
774 REG_A6XX_SP_DS_OUT_REG(0),
775 REG_A6XX_SP_DS_VPC_DST_REG(0),
776 REG_A6XX_VPC_DS_PACK,
777 REG_A6XX_VPC_DS_CLIP_CNTL,
778 REG_A6XX_GRAS_DS_CL_CNTL,
779 REG_A6XX_PC_DS_OUT_CNTL,
780 REG_A6XX_SP_DS_PRIMITIVE_CNTL,
781 REG_A6XX_VPC_DS_LAYER_CNTL,
782 REG_A6XX_GRAS_DS_LAYER_CNTL
783 },
784 [MESA_SHADER_GEOMETRY] = {
785 REG_A6XX_SP_GS_OUT_REG(0),
786 REG_A6XX_SP_GS_VPC_DST_REG(0),
787 REG_A6XX_VPC_GS_PACK,
788 REG_A6XX_VPC_GS_CLIP_CNTL,
789 REG_A6XX_GRAS_GS_CL_CNTL,
790 REG_A6XX_PC_GS_OUT_CNTL,
791 REG_A6XX_SP_GS_PRIMITIVE_CNTL,
792 REG_A6XX_VPC_GS_LAYER_CNTL,
793 REG_A6XX_GRAS_GS_LAYER_CNTL
794 },
795 };
796
797 const struct ir3_shader_variant *last_shader;
798 if (gs) {
799 last_shader = gs;
800 } else if (hs) {
801 last_shader = ds;
802 } else {
803 last_shader = vs;
804 }
805
806 const struct reg_config *cfg = &reg_config[last_shader->type];
807
808 struct ir3_shader_linkage linkage = { .primid_loc = 0xff };
809 if (fs)
810 ir3_link_shaders(&linkage, last_shader, fs, true);
811
812 if (last_shader->shader->stream_output.num_outputs)
813 tu6_link_streamout(&linkage, last_shader);
814
815 /* We do this after linking shaders in order to know whether PrimID
816 * passthrough needs to be enabled.
817 */
818 bool primid_passthru = linkage.primid_loc != 0xff;
819 tu6_emit_vs_system_values(cs, vs, hs, ds, gs, primid_passthru);
820
821 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VAR_DISABLE(0), 4);
822 tu_cs_emit(cs, ~linkage.varmask[0]);
823 tu_cs_emit(cs, ~linkage.varmask[1]);
824 tu_cs_emit(cs, ~linkage.varmask[2]);
825 tu_cs_emit(cs, ~linkage.varmask[3]);
826
827 /* a6xx finds position/pointsize at the end */
828 const uint32_t position_regid =
829 ir3_find_output_regid(last_shader, VARYING_SLOT_POS);
830 const uint32_t pointsize_regid =
831 ir3_find_output_regid(last_shader, VARYING_SLOT_PSIZ);
832 const uint32_t layer_regid =
833 ir3_find_output_regid(last_shader, VARYING_SLOT_LAYER);
834 uint32_t primitive_regid = gs ?
835 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID) : regid(63, 0);
836 uint32_t flags_regid = gs ?
837 ir3_find_output_regid(gs, VARYING_SLOT_GS_VERTEX_FLAGS_IR3) : 0;
838
839 uint32_t pointsize_loc = 0xff, position_loc = 0xff, layer_loc = 0xff;
840 if (layer_regid != regid(63, 0)) {
841 layer_loc = linkage.max_loc;
842 ir3_link_add(&linkage, layer_regid, 0x1, linkage.max_loc);
843 }
844 if (position_regid != regid(63, 0)) {
845 position_loc = linkage.max_loc;
846 ir3_link_add(&linkage, position_regid, 0xf, linkage.max_loc);
847 }
848 if (pointsize_regid != regid(63, 0)) {
849 pointsize_loc = linkage.max_loc;
850 ir3_link_add(&linkage, pointsize_regid, 0x1, linkage.max_loc);
851 }
852
853 tu6_setup_streamout(cs, last_shader, &linkage);
854
855 /* The GPU hangs on some models when there are no outputs (xs_pack::CNT),
856 * at least when a DS is the last stage, so add a dummy output to keep it
857 * happy if there aren't any. We do this late in order to avoid emitting
858 * any unused code and make sure that optimizations don't remove it.
859 */
860 if (linkage.cnt == 0)
861 ir3_link_add(&linkage, 0, 0x1, linkage.max_loc);
862
863 /* map outputs of the last shader to VPC */
864 assert(linkage.cnt <= 32);
865 const uint32_t sp_out_count = DIV_ROUND_UP(linkage.cnt, 2);
866 const uint32_t sp_vpc_dst_count = DIV_ROUND_UP(linkage.cnt, 4);
867 uint32_t sp_out[16];
868 uint32_t sp_vpc_dst[8];
869 for (uint32_t i = 0; i < linkage.cnt; i++) {
870 ((uint16_t *) sp_out)[i] =
871 A6XX_SP_VS_OUT_REG_A_REGID(linkage.var[i].regid) |
872 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage.var[i].compmask);
873 ((uint8_t *) sp_vpc_dst)[i] =
874 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage.var[i].loc);
875 }
876
877 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_out_reg, sp_out_count);
878 tu_cs_emit_array(cs, sp_out, sp_out_count);
879
880 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_vpc_dst_reg, sp_vpc_dst_count);
881 tu_cs_emit_array(cs, sp_vpc_dst, sp_vpc_dst_count);
882
883 tu_cs_emit_pkt4(cs, cfg->reg_vpc_xs_pack, 1);
884 tu_cs_emit(cs, A6XX_VPC_VS_PACK_POSITIONLOC(position_loc) |
885 A6XX_VPC_VS_PACK_PSIZELOC(pointsize_loc) |
886 A6XX_VPC_VS_PACK_STRIDE_IN_VPC(linkage.max_loc));
887
888 tu_cs_emit_pkt4(cs, cfg->reg_vpc_xs_clip_cntl, 1);
889 tu_cs_emit(cs, 0xffff00);
890
891 tu_cs_emit_pkt4(cs, cfg->reg_gras_xs_cl_cntl, 1);
892 tu_cs_emit(cs, 0);
893
894 tu_cs_emit_pkt4(cs, cfg->reg_pc_xs_out_cntl, 1);
895 tu_cs_emit(cs, A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(linkage.max_loc) |
896 CONDREG(pointsize_regid, A6XX_PC_VS_OUT_CNTL_PSIZE) |
897 CONDREG(layer_regid, A6XX_PC_VS_OUT_CNTL_LAYER) |
898 CONDREG(primitive_regid, A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID));
899
900 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_primitive_cntl, 1);
901 tu_cs_emit(cs, A6XX_SP_VS_PRIMITIVE_CNTL_OUT(linkage.cnt) |
902 A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(flags_regid));
903
904 tu_cs_emit_pkt4(cs, cfg->reg_vpc_xs_layer_cntl, 1);
905 tu_cs_emit(cs, A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(layer_loc) | 0xff00);
906
907 tu_cs_emit_pkt4(cs, cfg->reg_gras_xs_layer_cntl, 1);
908 tu_cs_emit(cs, CONDREG(layer_regid, A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER));
909
910 tu_cs_emit_regs(cs, A6XX_PC_PRIMID_PASSTHRU(primid_passthru));
911
912 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_CNTL_0, 1);
913 tu_cs_emit(cs, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs ? fs->total_in : 0) |
914 COND(fs && fs->total_in, A6XX_VPC_CNTL_0_VARYING) |
915 A6XX_VPC_CNTL_0_PRIMIDLOC(linkage.primid_loc) |
916 A6XX_VPC_CNTL_0_VIEWIDLOC(linkage.viewid_loc));
917
918 if (hs) {
919 shader_info *hs_info = &hs->shader->nir->info;
920 uint32_t unknown_a831 = vs->output_size;
921
922 tu_cs_emit_pkt4(cs, REG_A6XX_PC_TESS_NUM_VERTEX, 1);
923 tu_cs_emit(cs, hs_info->tess.tcs_vertices_out);
924
925 /* Total attribute slots in HS incoming patch. */
926 tu_cs_emit_pkt4(cs, REG_A6XX_PC_HS_INPUT_SIZE, 1);
927 tu_cs_emit(cs, patch_control_points * vs->output_size / 4);
928
929 /* for A650 this value seems to be local memory size per wave */
930 if (vshs_workgroup) {
931 const uint32_t wavesize = 64;
932 /* note: if HS is really just the VS extended, then this
933 * should be by MAX2(patch_control_points, hs_info->tess.tcs_vertices_out)
934 * however that doesn't match the blob, and fails some dEQP tests.
935 */
936 uint32_t prims_per_wave = wavesize / hs_info->tess.tcs_vertices_out;
937 uint32_t total_size = vs->output_size * patch_control_points * prims_per_wave;
938 unknown_a831 = DIV_ROUND_UP(total_size, wavesize);
939 }
940
941 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
942 tu_cs_emit(cs, unknown_a831);
943
944 /* In SPIR-V generated from GLSL, the tessellation primitive params are
945 * are specified in the tess eval shader, but in SPIR-V generated from
946 * HLSL, they are specified in the tess control shader. */
947 shader_info *tess_info =
948 ds->shader->nir->info.tess.spacing == TESS_SPACING_UNSPECIFIED ?
949 &hs->shader->nir->info : &ds->shader->nir->info;
950 tu_cs_emit_pkt4(cs, REG_A6XX_PC_TESS_CNTL, 1);
951 uint32_t output;
952 if (tess_info->tess.point_mode)
953 output = TESS_POINTS;
954 else if (tess_info->tess.primitive_mode == GL_ISOLINES)
955 output = TESS_LINES;
956 else if (tess_info->tess.ccw)
957 output = TESS_CCW_TRIS;
958 else
959 output = TESS_CW_TRIS;
960
961 enum a6xx_tess_spacing spacing;
962 switch (tess_info->tess.spacing) {
963 case TESS_SPACING_EQUAL:
964 spacing = TESS_EQUAL;
965 break;
966 case TESS_SPACING_FRACTIONAL_ODD:
967 spacing = TESS_FRACTIONAL_ODD;
968 break;
969 case TESS_SPACING_FRACTIONAL_EVEN:
970 spacing = TESS_FRACTIONAL_EVEN;
971 break;
972 case TESS_SPACING_UNSPECIFIED:
973 default:
974 unreachable("invalid tess spacing");
975 }
976 tu_cs_emit(cs, A6XX_PC_TESS_CNTL_SPACING(spacing) |
977 A6XX_PC_TESS_CNTL_OUTPUT(output));
978
979 tu6_emit_link_map(cs, vs, hs, SB6_HS_SHADER);
980 tu6_emit_link_map(cs, hs, ds, SB6_DS_SHADER);
981 }
982
983
984 if (gs) {
985 uint32_t vertices_out, invocations, output, vec4_size;
986 /* this detects the tu_clear_blit path, which doesn't set ->nir */
987 if (gs->shader->nir) {
988 if (hs) {
989 tu6_emit_link_map(cs, ds, gs, SB6_GS_SHADER);
990 } else {
991 tu6_emit_link_map(cs, vs, gs, SB6_GS_SHADER);
992 }
993 vertices_out = gs->shader->nir->info.gs.vertices_out - 1;
994 output = gl_primitive_to_tess(gs->shader->nir->info.gs.output_primitive);
995 invocations = gs->shader->nir->info.gs.invocations - 1;
996 /* Size of per-primitive alloction in ldlw memory in vec4s. */
997 vec4_size = gs->shader->nir->info.gs.vertices_in *
998 DIV_ROUND_UP(vs->output_size, 4);
999 } else {
1000 vertices_out = 3;
1001 output = TESS_CW_TRIS;
1002 invocations = 0;
1003 vec4_size = 0;
1004 }
1005
1006 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_5, 1);
1007 tu_cs_emit(cs,
1008 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(vertices_out) |
1009 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output) |
1010 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(invocations));
1011
1012 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_3, 1);
1013 tu_cs_emit(cs, 0);
1014
1015 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9100, 1);
1016 tu_cs_emit(cs, 0xff);
1017
1018 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
1019 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size));
1020
1021 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_PRIM_SIZE, 1);
1022 tu_cs_emit(cs, vs->output_size);
1023 }
1024 }
1025
1026 static int
1027 tu6_vpc_varying_mode(const struct ir3_shader_variant *fs,
1028 uint32_t index,
1029 uint8_t *interp_mode,
1030 uint8_t *ps_repl_mode)
1031 {
1032 enum
1033 {
1034 INTERP_SMOOTH = 0,
1035 INTERP_FLAT = 1,
1036 INTERP_ZERO = 2,
1037 INTERP_ONE = 3,
1038 };
1039 enum
1040 {
1041 PS_REPL_NONE = 0,
1042 PS_REPL_S = 1,
1043 PS_REPL_T = 2,
1044 PS_REPL_ONE_MINUS_T = 3,
1045 };
1046
1047 const uint32_t compmask = fs->inputs[index].compmask;
1048
1049 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
1050 * fourth component occupy three consecutive varying slots
1051 */
1052 int shift = 0;
1053 *interp_mode = 0;
1054 *ps_repl_mode = 0;
1055 if (fs->inputs[index].slot == VARYING_SLOT_PNTC) {
1056 if (compmask & 0x1) {
1057 *ps_repl_mode |= PS_REPL_S << shift;
1058 shift += 2;
1059 }
1060 if (compmask & 0x2) {
1061 *ps_repl_mode |= PS_REPL_T << shift;
1062 shift += 2;
1063 }
1064 if (compmask & 0x4) {
1065 *interp_mode |= INTERP_ZERO << shift;
1066 shift += 2;
1067 }
1068 if (compmask & 0x8) {
1069 *interp_mode |= INTERP_ONE << 6;
1070 shift += 2;
1071 }
1072 } else if ((fs->inputs[index].interpolate == INTERP_MODE_FLAT) ||
1073 fs->inputs[index].rasterflat) {
1074 for (int i = 0; i < 4; i++) {
1075 if (compmask & (1 << i)) {
1076 *interp_mode |= INTERP_FLAT << shift;
1077 shift += 2;
1078 }
1079 }
1080 }
1081
1082 return shift;
1083 }
1084
1085 static void
1086 tu6_emit_vpc_varying_modes(struct tu_cs *cs,
1087 const struct ir3_shader_variant *fs)
1088 {
1089 uint32_t interp_modes[8] = { 0 };
1090 uint32_t ps_repl_modes[8] = { 0 };
1091
1092 if (fs) {
1093 for (int i = -1;
1094 (i = ir3_next_varying(fs, i)) < (int) fs->inputs_count;) {
1095
1096 /* get the mode for input i */
1097 uint8_t interp_mode;
1098 uint8_t ps_repl_mode;
1099 const int bits =
1100 tu6_vpc_varying_mode(fs, i, &interp_mode, &ps_repl_mode);
1101
1102 /* OR the mode into the array */
1103 const uint32_t inloc = fs->inputs[i].inloc * 2;
1104 uint32_t n = inloc / 32;
1105 uint32_t shift = inloc % 32;
1106 interp_modes[n] |= interp_mode << shift;
1107 ps_repl_modes[n] |= ps_repl_mode << shift;
1108 if (shift + bits > 32) {
1109 n++;
1110 shift = 32 - shift;
1111
1112 interp_modes[n] |= interp_mode >> shift;
1113 ps_repl_modes[n] |= ps_repl_mode >> shift;
1114 }
1115 }
1116 }
1117
1118 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
1119 tu_cs_emit_array(cs, interp_modes, 8);
1120
1121 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
1122 tu_cs_emit_array(cs, ps_repl_modes, 8);
1123 }
1124
1125 void
1126 tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
1127 {
1128 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
1129 uint32_t ij_regid[IJ_COUNT];
1130 uint32_t smask_in_regid;
1131
1132 bool sample_shading = fs->per_samp | fs->key.sample_shading;
1133 bool enable_varyings = fs->total_in > 0;
1134
1135 samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
1136 smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
1137 face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
1138 coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
1139 zwcoord_regid = VALIDREG(coord_regid) ? coord_regid + 2 : regid(63, 0);
1140 for (unsigned i = 0; i < ARRAY_SIZE(ij_regid); i++)
1141 ij_regid[i] = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL + i);
1142
1143 if (VALIDREG(ij_regid[IJ_LINEAR_SAMPLE]))
1144 tu_finishme("linear sample varying");
1145
1146 if (VALIDREG(ij_regid[IJ_LINEAR_CENTROID]))
1147 tu_finishme("linear centroid varying");
1148
1149 if (fs->num_sampler_prefetch > 0) {
1150 assert(VALIDREG(ij_regid[IJ_PERSP_PIXEL]));
1151 /* also, it seems like ij_pix is *required* to be r0.x */
1152 assert(ij_regid[IJ_PERSP_PIXEL] == regid(0, 0));
1153 }
1154
1155 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
1156 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
1157 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
1158 0x7000); // XXX);
1159 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
1160 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
1161 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch->src) |
1162 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch->samp_id) |
1163 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch->tex_id) |
1164 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch->dst) |
1165 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch->wrmask) |
1166 COND(prefetch->half_precision, A6XX_SP_FS_PREFETCH_CMD_HALF) |
1167 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch->cmd));
1168 }
1169
1170 if (fs->num_sampler_prefetch > 0) {
1171 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(0), fs->num_sampler_prefetch);
1172 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
1173 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
1174 tu_cs_emit(cs,
1175 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(prefetch->samp_bindless_id) |
1176 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(prefetch->tex_bindless_id));
1177 }
1178 }
1179
1180 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
1181 tu_cs_emit(cs, 0x7);
1182 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
1183 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
1184 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
1185 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_regid[IJ_PERSP_SIZE]));
1186 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(ij_regid[IJ_PERSP_PIXEL]) |
1187 A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(ij_regid[IJ_LINEAR_PIXEL]) |
1188 A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(ij_regid[IJ_PERSP_CENTROID]) |
1189 A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(ij_regid[IJ_LINEAR_CENTROID]));
1190 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
1191 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
1192 A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(ij_regid[IJ_PERSP_SAMPLE]) |
1193 A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(ij_regid[IJ_LINEAR_SAMPLE]));
1194 tu_cs_emit(cs, 0xfc);
1195
1196 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
1197 tu_cs_emit(cs, enable_varyings ? 3 : 1);
1198
1199 bool need_size = fs->frag_face || fs->fragcoord_compmask != 0;
1200 bool need_size_persamp = false;
1201 if (VALIDREG(ij_regid[IJ_PERSP_SIZE])) {
1202 if (sample_shading)
1203 need_size_persamp = true;
1204 else
1205 need_size = true;
1206 }
1207 if (VALIDREG(ij_regid[IJ_LINEAR_PIXEL]))
1208 need_size = true;
1209
1210 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CNTL, 1);
1211 tu_cs_emit(cs,
1212 CONDREG(ij_regid[IJ_PERSP_PIXEL], A6XX_GRAS_CNTL_IJ_PERSP_PIXEL) |
1213 CONDREG(ij_regid[IJ_PERSP_CENTROID], A6XX_GRAS_CNTL_IJ_PERSP_CENTROID) |
1214 CONDREG(ij_regid[IJ_PERSP_SAMPLE], A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE) |
1215 COND(need_size, A6XX_GRAS_CNTL_SIZE) |
1216 COND(need_size_persamp, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
1217 COND(fs->fragcoord_compmask != 0, A6XX_GRAS_CNTL_COORD_MASK(fs->fragcoord_compmask)));
1218
1219 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CONTROL0, 2);
1220 tu_cs_emit(cs,
1221 CONDREG(ij_regid[IJ_PERSP_PIXEL], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL) |
1222 CONDREG(ij_regid[IJ_PERSP_CENTROID], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID) |
1223 CONDREG(ij_regid[IJ_PERSP_SAMPLE], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE) |
1224 COND(need_size, A6XX_RB_RENDER_CONTROL0_SIZE) |
1225 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
1226 COND(need_size_persamp, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
1227 COND(fs->fragcoord_compmask != 0,
1228 A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs->fragcoord_compmask)));
1229 tu_cs_emit(cs,
1230 /* these two bits (UNK4/UNK5) relate to fragcoord
1231 * without them, fragcoord is the same for all samples
1232 */
1233 COND(sample_shading, A6XX_RB_RENDER_CONTROL1_UNK4) |
1234 COND(sample_shading, A6XX_RB_RENDER_CONTROL1_UNK5) |
1235 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
1236 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
1237 CONDREG(ij_regid[IJ_PERSP_SIZE], A6XX_RB_RENDER_CONTROL1_SIZE) |
1238 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
1239
1240 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CNTL, 1);
1241 tu_cs_emit(cs, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
1242
1243 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8101, 1);
1244 tu_cs_emit(cs, COND(sample_shading, 0x6)); // XXX
1245
1246 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
1247 tu_cs_emit(cs, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
1248 }
1249
1250 static void
1251 tu6_emit_fs_outputs(struct tu_cs *cs,
1252 const struct ir3_shader_variant *fs,
1253 uint32_t mrt_count, bool dual_src_blend,
1254 uint32_t render_components,
1255 bool is_s8_uint)
1256 {
1257 uint32_t smask_regid, posz_regid, stencilref_regid;
1258
1259 posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
1260 smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
1261 stencilref_regid = ir3_find_output_regid(fs, FRAG_RESULT_STENCIL);
1262
1263 uint32_t fragdata_regid[8];
1264 if (fs->color0_mrt) {
1265 fragdata_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
1266 for (uint32_t i = 1; i < ARRAY_SIZE(fragdata_regid); i++)
1267 fragdata_regid[i] = fragdata_regid[0];
1268 } else {
1269 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++)
1270 fragdata_regid[i] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0 + i);
1271 }
1272
1273 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_CNTL0, 2);
1274 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
1275 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
1276 A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(stencilref_regid) |
1277 COND(dual_src_blend, A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE));
1278 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count));
1279
1280 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
1281 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++) {
1282 // TODO we could have a mix of half and full precision outputs,
1283 // we really need to figure out half-precision from IR3_REG_HALF
1284 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid[i]) |
1285 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION : 0));
1286 }
1287
1288 tu_cs_emit_regs(cs,
1289 A6XX_SP_FS_RENDER_COMPONENTS(.dword = render_components));
1290
1291 tu_cs_emit_pkt4(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
1292 tu_cs_emit(cs, COND(fs->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
1293 COND(fs->writes_smask, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK) |
1294 COND(fs->writes_stencilref, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF) |
1295 COND(dual_src_blend, A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE));
1296 tu_cs_emit(cs, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count));
1297
1298 tu_cs_emit_regs(cs,
1299 A6XX_RB_RENDER_COMPONENTS(.dword = render_components));
1300
1301 enum a6xx_ztest_mode zmode;
1302
1303 if (fs->no_earlyz || fs->has_kill || fs->writes_pos || fs->writes_stencilref || is_s8_uint) {
1304 zmode = A6XX_LATE_Z;
1305 } else {
1306 zmode = A6XX_EARLY_Z;
1307 }
1308
1309 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
1310 tu_cs_emit(cs, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(zmode));
1311
1312 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
1313 tu_cs_emit(cs, A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(zmode));
1314 }
1315
1316 static void
1317 tu6_emit_geom_tess_consts(struct tu_cs *cs,
1318 const struct ir3_shader_variant *vs,
1319 const struct ir3_shader_variant *hs,
1320 const struct ir3_shader_variant *ds,
1321 const struct ir3_shader_variant *gs,
1322 uint32_t cps_per_patch)
1323 {
1324 uint32_t num_vertices =
1325 hs ? cps_per_patch : gs->shader->nir->info.gs.vertices_in;
1326
1327 uint32_t vs_params[4] = {
1328 vs->output_size * num_vertices * 4, /* vs primitive stride */
1329 vs->output_size * 4, /* vs vertex stride */
1330 0,
1331 0,
1332 };
1333 uint32_t vs_base = ir3_const_state(vs)->offsets.primitive_param;
1334 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, vs_base, SB6_VS_SHADER, 0,
1335 ARRAY_SIZE(vs_params), vs_params);
1336
1337 if (hs) {
1338 assert(ds->type != MESA_SHADER_NONE);
1339 uint32_t hs_params[4] = {
1340 vs->output_size * num_vertices * 4, /* hs primitive stride */
1341 vs->output_size * 4, /* hs vertex stride */
1342 hs->output_size,
1343 cps_per_patch,
1344 };
1345
1346 uint32_t hs_base = hs->const_state->offsets.primitive_param;
1347 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, hs_base, SB6_HS_SHADER, 0,
1348 ARRAY_SIZE(hs_params), hs_params);
1349 if (gs)
1350 num_vertices = gs->shader->nir->info.gs.vertices_in;
1351
1352 uint32_t ds_params[4] = {
1353 ds->output_size * num_vertices * 4, /* ds primitive stride */
1354 ds->output_size * 4, /* ds vertex stride */
1355 hs->output_size, /* hs vertex stride (dwords) */
1356 hs->shader->nir->info.tess.tcs_vertices_out
1357 };
1358
1359 uint32_t ds_base = ds->const_state->offsets.primitive_param;
1360 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, ds_base, SB6_DS_SHADER, 0,
1361 ARRAY_SIZE(ds_params), ds_params);
1362 }
1363
1364 if (gs) {
1365 const struct ir3_shader_variant *prev = ds ? ds : vs;
1366 uint32_t gs_params[4] = {
1367 prev->output_size * num_vertices * 4, /* gs primitive stride */
1368 prev->output_size * 4, /* gs vertex stride */
1369 0,
1370 0,
1371 };
1372 uint32_t gs_base = gs->const_state->offsets.primitive_param;
1373 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, gs_base, SB6_GS_SHADER, 0,
1374 ARRAY_SIZE(gs_params), gs_params);
1375 }
1376 }
1377
1378 static void
1379 tu6_emit_program(struct tu_cs *cs,
1380 struct tu_pipeline_builder *builder,
1381 bool binning_pass)
1382 {
1383 const struct ir3_shader_variant *vs = builder->variants[MESA_SHADER_VERTEX];
1384 const struct ir3_shader_variant *bs = builder->binning_variant;
1385 const struct ir3_shader_variant *hs = builder->variants[MESA_SHADER_TESS_CTRL];
1386 const struct ir3_shader_variant *ds = builder->variants[MESA_SHADER_TESS_EVAL];
1387 const struct ir3_shader_variant *gs = builder->variants[MESA_SHADER_GEOMETRY];
1388 const struct ir3_shader_variant *fs = builder->variants[MESA_SHADER_FRAGMENT];
1389 gl_shader_stage stage = MESA_SHADER_VERTEX;
1390 uint32_t cps_per_patch = builder->create_info->pTessellationState ?
1391 builder->create_info->pTessellationState->patchControlPoints : 0;
1392
1393 STATIC_ASSERT(MESA_SHADER_VERTEX == 0);
1394
1395 tu_cs_emit_regs(cs, A6XX_HLSQ_INVALIDATE_CMD(
1396 .vs_state = true,
1397 .hs_state = true,
1398 .ds_state = true,
1399 .gs_state = true,
1400 .fs_state = true,
1401 .gfx_ibo = true));
1402
1403 /* Don't use the binning pass variant when GS is present because we don't
1404 * support compiling correct binning pass variants with GS.
1405 */
1406 if (binning_pass && !gs) {
1407 vs = bs;
1408 tu6_emit_xs_config(cs, stage, bs, builder->binning_vs_iova);
1409 stage++;
1410 }
1411
1412 for (; stage < ARRAY_SIZE(builder->shaders); stage++) {
1413 const struct ir3_shader_variant *xs = builder->variants[stage];
1414
1415 if (stage == MESA_SHADER_FRAGMENT && binning_pass)
1416 fs = xs = NULL;
1417
1418 tu6_emit_xs_config(cs, stage, xs, builder->shader_iova[stage]);
1419 }
1420
1421 if (!binning_pass) {
1422 uint32_t multiview_views = util_logbase2(builder->multiview_mask) + 1;
1423 uint32_t multiview_cntl = builder->multiview_mask ?
1424 A6XX_PC_MULTIVIEW_CNTL_ENABLE |
1425 A6XX_PC_MULTIVIEW_CNTL_VIEWS(multiview_views) |
1426 A6XX_PC_MULTIVIEW_CNTL_DISABLEMULTIPOS /* TODO multi-pos output */
1427 : 0;
1428
1429 /* Copy what the blob does here. This will emit an extra 0x3f
1430 * CP_EVENT_WRITE when multiview is disabled. I'm not exactly sure what
1431 * this is working around yet.
1432 */
1433 tu_cs_emit_pkt7(cs, CP_REG_WRITE, 3);
1434 tu_cs_emit(cs, CP_REG_WRITE_0_TRACKER(UNK_EVENT_WRITE));
1435 tu_cs_emit(cs, REG_A6XX_PC_MULTIVIEW_CNTL);
1436 tu_cs_emit(cs, multiview_cntl);
1437
1438 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_MULTIVIEW_CNTL, 1);
1439 tu_cs_emit(cs, multiview_cntl);
1440
1441 if (multiview_cntl &&
1442 builder->device->physical_device->supports_multiview_mask) {
1443 tu_cs_emit_pkt4(cs, REG_A6XX_PC_MULTIVIEW_MASK, 1);
1444 tu_cs_emit(cs, builder->multiview_mask);
1445 }
1446 }
1447
1448 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
1449 tu_cs_emit(cs, 0);
1450
1451 tu6_emit_vpc(cs, vs, hs, ds, gs, fs, cps_per_patch,
1452 builder->device->physical_device->gpu_id == 650);
1453 tu6_emit_vpc_varying_modes(cs, fs);
1454
1455 if (fs) {
1456 tu6_emit_fs_inputs(cs, fs);
1457 tu6_emit_fs_outputs(cs, fs, builder->color_attachment_count,
1458 builder->use_dual_src_blend,
1459 builder->render_components,
1460 builder->depth_attachment_format == VK_FORMAT_S8_UINT);
1461 } else {
1462 /* TODO: check if these can be skipped if fs is disabled */
1463 struct ir3_shader_variant dummy_variant = {};
1464 tu6_emit_fs_inputs(cs, &dummy_variant);
1465 tu6_emit_fs_outputs(cs, &dummy_variant, builder->color_attachment_count,
1466 builder->use_dual_src_blend,
1467 builder->render_components,
1468 builder->depth_attachment_format == VK_FORMAT_S8_UINT);
1469 }
1470
1471 if (gs || hs) {
1472 tu6_emit_geom_tess_consts(cs, vs, hs, ds, gs, cps_per_patch);
1473 }
1474 }
1475
1476 static void
1477 tu6_emit_vertex_input(struct tu_cs *cs,
1478 const struct ir3_shader_variant *vs,
1479 const VkPipelineVertexInputStateCreateInfo *info,
1480 uint32_t *bindings_used)
1481 {
1482 uint32_t vfd_decode_idx = 0;
1483 uint32_t binding_instanced = 0; /* bitmask of instanced bindings */
1484 uint32_t step_rate[MAX_VBS];
1485
1486 for (uint32_t i = 0; i < info->vertexBindingDescriptionCount; i++) {
1487 const VkVertexInputBindingDescription *binding =
1488 &info->pVertexBindingDescriptions[i];
1489
1490 tu_cs_emit_regs(cs,
1491 A6XX_VFD_FETCH_STRIDE(binding->binding, binding->stride));
1492
1493 if (binding->inputRate == VK_VERTEX_INPUT_RATE_INSTANCE)
1494 binding_instanced |= 1 << binding->binding;
1495
1496 *bindings_used |= 1 << binding->binding;
1497 step_rate[binding->binding] = 1;
1498 }
1499
1500 const VkPipelineVertexInputDivisorStateCreateInfoEXT *div_state =
1501 vk_find_struct_const(info->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
1502 if (div_state) {
1503 for (uint32_t i = 0; i < div_state->vertexBindingDivisorCount; i++) {
1504 const VkVertexInputBindingDivisorDescriptionEXT *desc =
1505 &div_state->pVertexBindingDivisors[i];
1506 step_rate[desc->binding] = desc->divisor;
1507 }
1508 }
1509
1510 /* TODO: emit all VFD_DECODE/VFD_DEST_CNTL in same (two) pkt4 */
1511
1512 for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
1513 const VkVertexInputAttributeDescription *attr =
1514 &info->pVertexAttributeDescriptions[i];
1515 uint32_t input_idx;
1516
1517 assert(*bindings_used & BIT(attr->binding));
1518
1519 for (input_idx = 0; input_idx < vs->inputs_count; input_idx++) {
1520 if ((vs->inputs[input_idx].slot - VERT_ATTRIB_GENERIC0) == attr->location)
1521 break;
1522 }
1523
1524 /* attribute not used, skip it */
1525 if (input_idx == vs->inputs_count)
1526 continue;
1527
1528 const struct tu_native_format format = tu6_format_vtx(attr->format);
1529 tu_cs_emit_regs(cs,
1530 A6XX_VFD_DECODE_INSTR(vfd_decode_idx,
1531 .idx = attr->binding,
1532 .offset = attr->offset,
1533 .instanced = binding_instanced & (1 << attr->binding),
1534 .format = format.fmt,
1535 .swap = format.swap,
1536 .unk30 = 1,
1537 ._float = !vk_format_is_int(attr->format)),
1538 A6XX_VFD_DECODE_STEP_RATE(vfd_decode_idx, step_rate[attr->binding]));
1539
1540 tu_cs_emit_regs(cs,
1541 A6XX_VFD_DEST_CNTL_INSTR(vfd_decode_idx,
1542 .writemask = vs->inputs[input_idx].compmask,
1543 .regid = vs->inputs[input_idx].regid));
1544
1545 vfd_decode_idx++;
1546 }
1547
1548 tu_cs_emit_regs(cs,
1549 A6XX_VFD_CONTROL_0(
1550 .fetch_cnt = vfd_decode_idx, /* decode_cnt for binning pass ? */
1551 .decode_cnt = vfd_decode_idx));
1552 }
1553
1554 void
1555 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport)
1556 {
1557 float offsets[3];
1558 float scales[3];
1559 scales[0] = viewport->width / 2.0f;
1560 scales[1] = viewport->height / 2.0f;
1561 scales[2] = viewport->maxDepth - viewport->minDepth;
1562 offsets[0] = viewport->x + scales[0];
1563 offsets[1] = viewport->y + scales[1];
1564 offsets[2] = viewport->minDepth;
1565
1566 VkOffset2D min;
1567 VkOffset2D max;
1568 min.x = (int32_t) viewport->x;
1569 max.x = (int32_t) ceilf(viewport->x + viewport->width);
1570 if (viewport->height >= 0.0f) {
1571 min.y = (int32_t) viewport->y;
1572 max.y = (int32_t) ceilf(viewport->y + viewport->height);
1573 } else {
1574 min.y = (int32_t)(viewport->y + viewport->height);
1575 max.y = (int32_t) ceilf(viewport->y);
1576 }
1577 /* the spec allows viewport->height to be 0.0f */
1578 if (min.y == max.y)
1579 max.y++;
1580 assert(min.x >= 0 && min.x < max.x);
1581 assert(min.y >= 0 && min.y < max.y);
1582
1583 VkExtent2D guardband_adj;
1584 guardband_adj.width = fd_calc_guardband(offsets[0], scales[0], false);
1585 guardband_adj.height = fd_calc_guardband(offsets[1], scales[1], false);
1586
1587 tu_cs_emit_regs(cs,
1588 A6XX_GRAS_CL_VPORT_XOFFSET(0, offsets[0]),
1589 A6XX_GRAS_CL_VPORT_XSCALE(0, scales[0]),
1590 A6XX_GRAS_CL_VPORT_YOFFSET(0, offsets[1]),
1591 A6XX_GRAS_CL_VPORT_YSCALE(0, scales[1]),
1592 A6XX_GRAS_CL_VPORT_ZOFFSET(0, offsets[2]),
1593 A6XX_GRAS_CL_VPORT_ZSCALE(0, scales[2]));
1594
1595 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(0), 2);
1596 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(min.x) |
1597 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(min.y));
1598 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(max.x - 1) |
1599 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(max.y - 1));
1600
1601 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
1602 tu_cs_emit(cs,
1603 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj.width) |
1604 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj.height));
1605
1606 float z_clamp_min = MIN2(viewport->minDepth, viewport->maxDepth);
1607 float z_clamp_max = MAX2(viewport->minDepth, viewport->maxDepth);
1608
1609 tu_cs_emit_regs(cs,
1610 A6XX_GRAS_CL_Z_CLAMP_MIN(0, z_clamp_min),
1611 A6XX_GRAS_CL_Z_CLAMP_MAX(0, z_clamp_max));
1612
1613 tu_cs_emit_regs(cs,
1614 A6XX_RB_Z_CLAMP_MIN(z_clamp_min),
1615 A6XX_RB_Z_CLAMP_MAX(z_clamp_max));
1616 }
1617
1618 void
1619 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor)
1620 {
1621 VkOffset2D min = scissor->offset;
1622 VkOffset2D max = {
1623 scissor->offset.x + scissor->extent.width,
1624 scissor->offset.y + scissor->extent.height,
1625 };
1626
1627 /* special case for empty scissor with max == 0 to avoid overflow */
1628 if (max.x == 0)
1629 min.x = max.x = 1;
1630 if (max.y == 0)
1631 min.y = max.y = 1;
1632
1633 /* avoid overflow with large scissor
1634 * note the max will be limited to min - 1, so that empty scissor works
1635 */
1636 uint32_t scissor_max = BITFIELD_MASK(15);
1637 min.x = MIN2(scissor_max, min.x);
1638 min.y = MIN2(scissor_max, min.y);
1639 max.x = MIN2(scissor_max, max.x);
1640 max.y = MIN2(scissor_max, max.y);
1641
1642 tu_cs_emit_regs(cs,
1643 A6XX_GRAS_SC_SCREEN_SCISSOR_TL(0, .x = min.x, .y = min.y),
1644 A6XX_GRAS_SC_SCREEN_SCISSOR_BR(0, .x = max.x - 1, .y = max.y - 1));
1645 }
1646
1647 void
1648 tu6_emit_sample_locations(struct tu_cs *cs, const VkSampleLocationsInfoEXT *samp_loc)
1649 {
1650 if (!samp_loc) {
1651 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CONFIG, 1);
1652 tu_cs_emit(cs, 0);
1653
1654 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CONFIG, 1);
1655 tu_cs_emit(cs, 0);
1656
1657 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_SAMPLE_CONFIG, 1);
1658 tu_cs_emit(cs, 0);
1659 return;
1660 }
1661
1662 assert(samp_loc->sampleLocationsPerPixel == samp_loc->sampleLocationsCount);
1663 assert(samp_loc->sampleLocationGridSize.width == 1);
1664 assert(samp_loc->sampleLocationGridSize.height == 1);
1665
1666 uint32_t sample_config =
1667 A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE;
1668 uint32_t sample_locations = 0;
1669 for (uint32_t i = 0; i < samp_loc->sampleLocationsCount; i++) {
1670 sample_locations |=
1671 (A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(samp_loc->pSampleLocations[i].x) |
1672 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(samp_loc->pSampleLocations[i].y)) << i*8;
1673 }
1674
1675 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CONFIG, 2);
1676 tu_cs_emit(cs, sample_config);
1677 tu_cs_emit(cs, sample_locations);
1678
1679 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CONFIG, 2);
1680 tu_cs_emit(cs, sample_config);
1681 tu_cs_emit(cs, sample_locations);
1682
1683 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_SAMPLE_CONFIG, 2);
1684 tu_cs_emit(cs, sample_config);
1685 tu_cs_emit(cs, sample_locations);
1686 }
1687
1688 static uint32_t
1689 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo *rast_info,
1690 VkSampleCountFlagBits samples,
1691 bool multiview)
1692 {
1693 uint32_t gras_su_cntl = 0;
1694
1695 if (rast_info->cullMode & VK_CULL_MODE_FRONT_BIT)
1696 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_FRONT;
1697 if (rast_info->cullMode & VK_CULL_MODE_BACK_BIT)
1698 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_BACK;
1699
1700 if (rast_info->frontFace == VK_FRONT_FACE_CLOCKWISE)
1701 gras_su_cntl |= A6XX_GRAS_SU_CNTL_FRONT_CW;
1702
1703 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1704
1705 if (rast_info->depthBiasEnable)
1706 gras_su_cntl |= A6XX_GRAS_SU_CNTL_POLY_OFFSET;
1707
1708 if (samples > VK_SAMPLE_COUNT_1_BIT)
1709 gras_su_cntl |= A6XX_GRAS_SU_CNTL_MSAA_ENABLE;
1710
1711 if (multiview) {
1712 gras_su_cntl |=
1713 A6XX_GRAS_SU_CNTL_UNK17 |
1714 A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE;
1715 }
1716
1717 return gras_su_cntl;
1718 }
1719
1720 void
1721 tu6_emit_depth_bias(struct tu_cs *cs,
1722 float constant_factor,
1723 float clamp,
1724 float slope_factor)
1725 {
1726 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
1727 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor).value);
1728 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor).value);
1729 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp).value);
1730 }
1731
1732 static void
1733 tu6_emit_depth_control(struct tu_cs *cs,
1734 const VkPipelineDepthStencilStateCreateInfo *ds_info,
1735 const VkPipelineRasterizationStateCreateInfo *rast_info)
1736 {
1737 uint32_t rb_depth_cntl = 0;
1738 if (ds_info->depthTestEnable) {
1739 rb_depth_cntl |=
1740 A6XX_RB_DEPTH_CNTL_Z_ENABLE |
1741 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) |
1742 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE; /* TODO: don't set for ALWAYS/NEVER */
1743
1744 if (rast_info->depthClampEnable)
1745 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE;
1746
1747 if (ds_info->depthWriteEnable)
1748 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
1749 }
1750
1751 if (ds_info->depthBoundsTestEnable)
1752 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE | A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
1753
1754 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_CNTL, 1);
1755 tu_cs_emit(cs, rb_depth_cntl);
1756 }
1757
1758 static void
1759 tu6_emit_stencil_control(struct tu_cs *cs,
1760 const VkPipelineDepthStencilStateCreateInfo *ds_info)
1761 {
1762 uint32_t rb_stencil_control = 0;
1763 if (ds_info->stencilTestEnable) {
1764 const VkStencilOpState *front = &ds_info->front;
1765 const VkStencilOpState *back = &ds_info->back;
1766 rb_stencil_control |=
1767 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
1768 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
1769 A6XX_RB_STENCIL_CONTROL_STENCIL_READ |
1770 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front->compareOp)) |
1771 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front->failOp)) |
1772 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front->passOp)) |
1773 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front->depthFailOp)) |
1774 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back->compareOp)) |
1775 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back->failOp)) |
1776 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back->passOp)) |
1777 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back->depthFailOp));
1778 }
1779
1780 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_CONTROL, 1);
1781 tu_cs_emit(cs, rb_stencil_control);
1782 }
1783
1784 static uint32_t
1785 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState *att,
1786 bool has_alpha)
1787 {
1788 const enum a3xx_rb_blend_opcode color_op = tu6_blend_op(att->colorBlendOp);
1789 const enum adreno_rb_blend_factor src_color_factor = tu6_blend_factor(
1790 has_alpha ? att->srcColorBlendFactor
1791 : tu_blend_factor_no_dst_alpha(att->srcColorBlendFactor));
1792 const enum adreno_rb_blend_factor dst_color_factor = tu6_blend_factor(
1793 has_alpha ? att->dstColorBlendFactor
1794 : tu_blend_factor_no_dst_alpha(att->dstColorBlendFactor));
1795 const enum a3xx_rb_blend_opcode alpha_op = tu6_blend_op(att->alphaBlendOp);
1796 const enum adreno_rb_blend_factor src_alpha_factor =
1797 tu6_blend_factor(att->srcAlphaBlendFactor);
1798 const enum adreno_rb_blend_factor dst_alpha_factor =
1799 tu6_blend_factor(att->dstAlphaBlendFactor);
1800
1801 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor) |
1802 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op) |
1803 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor) |
1804 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor) |
1805 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op) |
1806 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor);
1807 }
1808
1809 static uint32_t
1810 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState *att,
1811 uint32_t rb_mrt_control_rop,
1812 bool is_int,
1813 bool has_alpha)
1814 {
1815 uint32_t rb_mrt_control =
1816 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att->colorWriteMask);
1817
1818 /* ignore blending and logic op for integer attachments */
1819 if (is_int) {
1820 rb_mrt_control |= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
1821 return rb_mrt_control;
1822 }
1823
1824 rb_mrt_control |= rb_mrt_control_rop;
1825
1826 if (att->blendEnable) {
1827 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND;
1828
1829 if (has_alpha)
1830 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND2;
1831 }
1832
1833 return rb_mrt_control;
1834 }
1835
1836 static void
1837 tu6_emit_rb_mrt_controls(struct tu_cs *cs,
1838 const VkPipelineColorBlendStateCreateInfo *blend_info,
1839 const VkFormat attachment_formats[MAX_RTS],
1840 uint32_t *blend_enable_mask)
1841 {
1842 *blend_enable_mask = 0;
1843
1844 bool rop_reads_dst = false;
1845 uint32_t rb_mrt_control_rop = 0;
1846 if (blend_info->logicOpEnable) {
1847 rop_reads_dst = tu_logic_op_reads_dst(blend_info->logicOp);
1848 rb_mrt_control_rop =
1849 A6XX_RB_MRT_CONTROL_ROP_ENABLE |
1850 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info->logicOp));
1851 }
1852
1853 for (uint32_t i = 0; i < blend_info->attachmentCount; i++) {
1854 const VkPipelineColorBlendAttachmentState *att =
1855 &blend_info->pAttachments[i];
1856 const VkFormat format = attachment_formats[i];
1857
1858 uint32_t rb_mrt_control = 0;
1859 uint32_t rb_mrt_blend_control = 0;
1860 if (format != VK_FORMAT_UNDEFINED) {
1861 const bool is_int = vk_format_is_int(format);
1862 const bool has_alpha = vk_format_has_alpha(format);
1863
1864 rb_mrt_control =
1865 tu6_rb_mrt_control(att, rb_mrt_control_rop, is_int, has_alpha);
1866 rb_mrt_blend_control = tu6_rb_mrt_blend_control(att, has_alpha);
1867
1868 if (att->blendEnable || rop_reads_dst)
1869 *blend_enable_mask |= 1 << i;
1870 }
1871
1872 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
1873 tu_cs_emit(cs, rb_mrt_control);
1874 tu_cs_emit(cs, rb_mrt_blend_control);
1875 }
1876 }
1877
1878 static void
1879 tu6_emit_blend_control(struct tu_cs *cs,
1880 uint32_t blend_enable_mask,
1881 bool dual_src_blend,
1882 const VkPipelineMultisampleStateCreateInfo *msaa_info)
1883 {
1884 const uint32_t sample_mask =
1885 msaa_info->pSampleMask ? (*msaa_info->pSampleMask & 0xffff)
1886 : ((1 << msaa_info->rasterizationSamples) - 1);
1887
1888 tu_cs_emit_regs(cs,
1889 A6XX_SP_BLEND_CNTL(.enabled = blend_enable_mask,
1890 .dual_color_in_enable = dual_src_blend,
1891 .alpha_to_coverage = msaa_info->alphaToCoverageEnable,
1892 .unk8 = true));
1893
1894 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
1895 tu_cs_emit_regs(cs,
1896 A6XX_RB_BLEND_CNTL(.enable_blend = blend_enable_mask,
1897 .independent_blend = true,
1898 .sample_mask = sample_mask,
1899 .dual_color_in_enable = dual_src_blend,
1900 .alpha_to_coverage = msaa_info->alphaToCoverageEnable,
1901 .alpha_to_one = msaa_info->alphaToOneEnable));
1902 }
1903
1904 static VkResult
1905 tu_pipeline_allocate_cs(struct tu_device *dev,
1906 struct tu_pipeline *pipeline,
1907 struct tu_pipeline_builder *builder,
1908 struct ir3_shader_variant *compute)
1909 {
1910 uint32_t size = 2048 + tu6_load_state_size(pipeline, compute);
1911
1912 /* graphics case: */
1913 if (builder) {
1914 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
1915 if (builder->variants[i])
1916 size += builder->variants[i]->info.sizedwords;
1917 }
1918
1919 size += builder->binning_variant->info.sizedwords;
1920 } else {
1921 size += compute->info.sizedwords;
1922 }
1923
1924 tu_cs_init(&pipeline->cs, dev, TU_CS_MODE_SUB_STREAM, size);
1925
1926 /* Reserve the space now such that tu_cs_begin_sub_stream never fails. Note
1927 * that LOAD_STATE can potentially take up a large amount of space so we
1928 * calculate its size explicitly.
1929 */
1930 return tu_cs_reserve_space(&pipeline->cs, size);
1931 }
1932
1933 static void
1934 tu_pipeline_shader_key_init(struct ir3_shader_key *key,
1935 const VkGraphicsPipelineCreateInfo *pipeline_info)
1936 {
1937 for (uint32_t i = 0; i < pipeline_info->stageCount; i++) {
1938 if (pipeline_info->pStages[i].stage == VK_SHADER_STAGE_GEOMETRY_BIT) {
1939 key->has_gs = true;
1940 break;
1941 }
1942 }
1943
1944 if (pipeline_info->pRasterizationState->rasterizerDiscardEnable)
1945 return;
1946
1947 const VkPipelineMultisampleStateCreateInfo *msaa_info = pipeline_info->pMultisampleState;
1948 const struct VkPipelineSampleLocationsStateCreateInfoEXT *sample_locations =
1949 vk_find_struct_const(msaa_info->pNext, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1950 if (msaa_info->rasterizationSamples > 1 ||
1951 /* also set msaa key when sample location is not the default
1952 * since this affects varying interpolation */
1953 (sample_locations && sample_locations->sampleLocationsEnable)) {
1954 key->msaa = true;
1955 }
1956
1957 /* note: not actually used by ir3, just checked in tu6_emit_fs_inputs */
1958 if (msaa_info->sampleShadingEnable)
1959 key->sample_shading = true;
1960
1961 /* We set this after we compile to NIR because we need the prim mode */
1962 key->tessellation = IR3_TESS_NONE;
1963 }
1964
1965 static uint32_t
1966 tu6_get_tessmode(struct tu_shader* shader)
1967 {
1968 uint32_t primitive_mode = shader->ir3_shader->nir->info.tess.primitive_mode;
1969 switch (primitive_mode) {
1970 case GL_ISOLINES:
1971 return IR3_TESS_ISOLINES;
1972 case GL_TRIANGLES:
1973 return IR3_TESS_TRIANGLES;
1974 case GL_QUADS:
1975 return IR3_TESS_QUADS;
1976 case GL_NONE:
1977 return IR3_TESS_NONE;
1978 default:
1979 unreachable("bad tessmode");
1980 }
1981 }
1982
1983 static uint64_t
1984 tu_upload_variant(struct tu_pipeline *pipeline,
1985 const struct ir3_shader_variant *variant)
1986 {
1987 struct tu_cs_memory memory;
1988
1989 if (!variant)
1990 return 0;
1991
1992 /* this expects to get enough alignment because shaders are allocated first
1993 * and sizedwords is always aligned correctly
1994 * note: an assert in tu6_emit_xs_config validates the alignment
1995 */
1996 tu_cs_alloc(&pipeline->cs, variant->info.sizedwords, 1, &memory);
1997
1998 memcpy(memory.map, variant->bin, sizeof(uint32_t) * variant->info.sizedwords);
1999 return memory.iova;
2000 }
2001
2002 static VkResult
2003 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder,
2004 struct tu_pipeline *pipeline)
2005 {
2006 const struct ir3_compiler *compiler = builder->device->compiler;
2007 const VkPipelineShaderStageCreateInfo *stage_infos[MESA_SHADER_STAGES] = {
2008 NULL
2009 };
2010 for (uint32_t i = 0; i < builder->create_info->stageCount; i++) {
2011 gl_shader_stage stage =
2012 vk_to_mesa_shader_stage(builder->create_info->pStages[i].stage);
2013 stage_infos[stage] = &builder->create_info->pStages[i];
2014 }
2015
2016 struct ir3_shader_key key = {};
2017 tu_pipeline_shader_key_init(&key, builder->create_info);
2018
2019 for (gl_shader_stage stage = MESA_SHADER_VERTEX;
2020 stage < MESA_SHADER_STAGES; stage++) {
2021 const VkPipelineShaderStageCreateInfo *stage_info = stage_infos[stage];
2022 if (!stage_info && stage != MESA_SHADER_FRAGMENT)
2023 continue;
2024
2025 struct tu_shader *shader =
2026 tu_shader_create(builder->device, stage, stage_info, builder->multiview_mask,
2027 builder->layout, builder->alloc);
2028 if (!shader)
2029 return VK_ERROR_OUT_OF_HOST_MEMORY;
2030
2031 /* In SPIR-V generated from GLSL, the primitive mode is specified in the
2032 * tessellation evaluation shader, but in SPIR-V generated from HLSL,
2033 * the mode is specified in the tessellation control shader. */
2034 if ((stage == MESA_SHADER_TESS_EVAL || stage == MESA_SHADER_TESS_CTRL) &&
2035 key.tessellation == IR3_TESS_NONE) {
2036 key.tessellation = tu6_get_tessmode(shader);
2037 }
2038
2039 builder->shaders[stage] = shader;
2040 }
2041
2042 struct tu_shader *gs = builder->shaders[MESA_SHADER_GEOMETRY];
2043 key.layer_zero =
2044 !gs || !(gs->ir3_shader->nir->info.outputs_written & VARYING_SLOT_LAYER);
2045
2046 pipeline->tess.patch_type = key.tessellation;
2047
2048 for (gl_shader_stage stage = MESA_SHADER_VERTEX;
2049 stage < MESA_SHADER_STAGES; stage++) {
2050 if (!builder->shaders[stage])
2051 continue;
2052
2053 bool created;
2054 builder->variants[stage] =
2055 ir3_shader_get_variant(builder->shaders[stage]->ir3_shader,
2056 &key, false, &created);
2057 if (!builder->variants[stage])
2058 return VK_ERROR_OUT_OF_HOST_MEMORY;
2059 }
2060
2061 uint32_t safe_constlens = ir3_trim_constlen(builder->variants, compiler);
2062
2063 key.safe_constlen = true;
2064
2065 for (gl_shader_stage stage = MESA_SHADER_VERTEX;
2066 stage < MESA_SHADER_STAGES; stage++) {
2067 if (!builder->shaders[stage])
2068 continue;
2069
2070 if (safe_constlens & (1 << stage)) {
2071 bool created;
2072 builder->variants[stage] =
2073 ir3_shader_get_variant(builder->shaders[stage]->ir3_shader,
2074 &key, false, &created);
2075 if (!builder->variants[stage])
2076 return VK_ERROR_OUT_OF_HOST_MEMORY;
2077 }
2078 }
2079
2080 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
2081 struct ir3_shader_variant *variant;
2082
2083 if (vs->ir3_shader->stream_output.num_outputs ||
2084 !ir3_has_binning_vs(&key)) {
2085 variant = builder->variants[MESA_SHADER_VERTEX];
2086 } else {
2087 bool created;
2088 key.safe_constlen = !!(safe_constlens & (1 << MESA_SHADER_VERTEX));
2089 variant = ir3_shader_get_variant(vs->ir3_shader, &key,
2090 true, &created);
2091 if (!variant)
2092 return VK_ERROR_OUT_OF_HOST_MEMORY;
2093 }
2094
2095 builder->binning_variant = variant;
2096
2097 return VK_SUCCESS;
2098 }
2099
2100 static void
2101 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
2102 struct tu_pipeline *pipeline)
2103 {
2104 const VkPipelineDynamicStateCreateInfo *dynamic_info =
2105 builder->create_info->pDynamicState;
2106
2107 if (!dynamic_info)
2108 return;
2109
2110 for (uint32_t i = 0; i < dynamic_info->dynamicStateCount; i++) {
2111 VkDynamicState state = dynamic_info->pDynamicStates[i];
2112 switch (state) {
2113 case VK_DYNAMIC_STATE_VIEWPORT ... VK_DYNAMIC_STATE_STENCIL_REFERENCE:
2114 pipeline->dynamic_state_mask |= BIT(state);
2115 break;
2116 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
2117 pipeline->dynamic_state_mask |= BIT(TU_DYNAMIC_STATE_SAMPLE_LOCATIONS);
2118 break;
2119 default:
2120 assert(!"unsupported dynamic state");
2121 break;
2122 }
2123 }
2124 }
2125
2126 static void
2127 tu_pipeline_set_linkage(struct tu_program_descriptor_linkage *link,
2128 struct tu_shader *shader,
2129 struct ir3_shader_variant *v)
2130 {
2131 link->const_state = *ir3_const_state(v);
2132 link->constlen = v->constlen;
2133 link->push_consts = shader->push_consts;
2134 }
2135
2136 static void
2137 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder *builder,
2138 struct tu_pipeline *pipeline)
2139 {
2140 struct tu_cs prog_cs;
2141 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2142 tu6_emit_program(&prog_cs, builder, false);
2143 pipeline->program.state = tu_cs_end_draw_state(&pipeline->cs, &prog_cs);
2144
2145 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2146 tu6_emit_program(&prog_cs, builder, true);
2147 pipeline->program.binning_state = tu_cs_end_draw_state(&pipeline->cs, &prog_cs);
2148
2149 VkShaderStageFlags stages = 0;
2150 for (unsigned i = 0; i < builder->create_info->stageCount; i++) {
2151 stages |= builder->create_info->pStages[i].stage;
2152 }
2153 pipeline->active_stages = stages;
2154
2155 uint32_t desc_sets = 0;
2156 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2157 if (!builder->shaders[i])
2158 continue;
2159
2160 tu_pipeline_set_linkage(&pipeline->program.link[i],
2161 builder->shaders[i],
2162 builder->variants[i]);
2163 desc_sets |= builder->shaders[i]->active_desc_sets;
2164 }
2165 pipeline->active_desc_sets = desc_sets;
2166 }
2167
2168 static void
2169 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder *builder,
2170 struct tu_pipeline *pipeline)
2171 {
2172 const VkPipelineVertexInputStateCreateInfo *vi_info =
2173 builder->create_info->pVertexInputState;
2174 const struct ir3_shader_variant *vs = builder->variants[MESA_SHADER_VERTEX];
2175 const struct ir3_shader_variant *bs = builder->binning_variant;
2176
2177 struct tu_cs vi_cs;
2178 tu_cs_begin_sub_stream(&pipeline->cs,
2179 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
2180 tu6_emit_vertex_input(&vi_cs, vs, vi_info,
2181 &pipeline->vi.bindings_used);
2182 pipeline->vi.state = tu_cs_end_draw_state(&pipeline->cs, &vi_cs);
2183
2184 if (bs) {
2185 tu_cs_begin_sub_stream(&pipeline->cs,
2186 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
2187 tu6_emit_vertex_input(
2188 &vi_cs, bs, vi_info, &pipeline->vi.bindings_used);
2189 pipeline->vi.binning_state =
2190 tu_cs_end_draw_state(&pipeline->cs, &vi_cs);
2191 }
2192 }
2193
2194 static void
2195 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder *builder,
2196 struct tu_pipeline *pipeline)
2197 {
2198 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
2199 builder->create_info->pInputAssemblyState;
2200
2201 pipeline->ia.primtype = tu6_primtype(ia_info->topology);
2202 pipeline->ia.primitive_restart = ia_info->primitiveRestartEnable;
2203 }
2204
2205 static bool
2206 tu_pipeline_static_state(struct tu_pipeline *pipeline, struct tu_cs *cs,
2207 uint32_t id, uint32_t size)
2208 {
2209 assert(id < ARRAY_SIZE(pipeline->dynamic_state));
2210
2211 if (pipeline->dynamic_state_mask & BIT(id))
2212 return false;
2213
2214 pipeline->dynamic_state[id] = tu_cs_draw_state(&pipeline->cs, cs, size);
2215 return true;
2216 }
2217
2218 static void
2219 tu_pipeline_builder_parse_tessellation(struct tu_pipeline_builder *builder,
2220 struct tu_pipeline *pipeline)
2221 {
2222 const VkPipelineTessellationStateCreateInfo *tess_info =
2223 builder->create_info->pTessellationState;
2224
2225 if (!tess_info)
2226 return;
2227
2228 assert(pipeline->ia.primtype == DI_PT_PATCHES0);
2229 assert(tess_info->patchControlPoints <= 32);
2230 pipeline->ia.primtype += tess_info->patchControlPoints;
2231 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_info =
2232 vk_find_struct_const(tess_info->pNext, PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
2233 pipeline->tess.upper_left_domain_origin = !domain_info ||
2234 domain_info->domainOrigin == VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT;
2235 const struct ir3_shader_variant *hs = builder->variants[MESA_SHADER_TESS_CTRL];
2236 const struct ir3_shader_variant *ds = builder->variants[MESA_SHADER_TESS_EVAL];
2237 pipeline->tess.param_stride = hs->output_size * 4;
2238 pipeline->tess.hs_bo_regid = hs->const_state->offsets.primitive_param + 1;
2239 pipeline->tess.ds_bo_regid = ds->const_state->offsets.primitive_param + 1;
2240 }
2241
2242 static void
2243 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder *builder,
2244 struct tu_pipeline *pipeline)
2245 {
2246 /* The spec says:
2247 *
2248 * pViewportState is a pointer to an instance of the
2249 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
2250 * pipeline has rasterization disabled."
2251 *
2252 * We leave the relevant registers stale in that case.
2253 */
2254 if (builder->rasterizer_discard)
2255 return;
2256
2257 const VkPipelineViewportStateCreateInfo *vp_info =
2258 builder->create_info->pViewportState;
2259
2260 struct tu_cs cs;
2261
2262 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_VIEWPORT, 18))
2263 tu6_emit_viewport(&cs, vp_info->pViewports);
2264
2265 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_SCISSOR, 3))
2266 tu6_emit_scissor(&cs, vp_info->pScissors);
2267 }
2268
2269 static void
2270 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder,
2271 struct tu_pipeline *pipeline)
2272 {
2273 const VkPipelineRasterizationStateCreateInfo *rast_info =
2274 builder->create_info->pRasterizationState;
2275
2276 enum a6xx_polygon_mode mode = tu6_polygon_mode(rast_info->polygonMode);
2277
2278 bool depth_clip_disable = rast_info->depthClampEnable;
2279
2280 const VkPipelineRasterizationDepthClipStateCreateInfoEXT *depth_clip_state =
2281 vk_find_struct_const(rast_info, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT);
2282 if (depth_clip_state)
2283 depth_clip_disable = !depth_clip_state->depthClipEnable;
2284
2285 struct tu_cs cs;
2286 pipeline->rast_state = tu_cs_draw_state(&pipeline->cs, &cs, 9);
2287
2288 tu_cs_emit_regs(&cs,
2289 A6XX_GRAS_CL_CNTL(
2290 .znear_clip_disable = depth_clip_disable,
2291 .zfar_clip_disable = depth_clip_disable,
2292 /* TODO should this be depth_clip_disable instead? */
2293 .unk5 = rast_info->depthClampEnable,
2294 .zero_gb_scale_z = 1,
2295 .vp_clip_code_ignore = 1));
2296
2297 tu_cs_emit_regs(&cs,
2298 A6XX_VPC_POLYGON_MODE(mode));
2299
2300 tu_cs_emit_regs(&cs,
2301 A6XX_PC_POLYGON_MODE(mode));
2302
2303 /* move to hw ctx init? */
2304 tu_cs_emit_regs(&cs,
2305 A6XX_GRAS_SU_POINT_MINMAX(.min = 1.0f / 16.0f, .max = 4092.0f),
2306 A6XX_GRAS_SU_POINT_SIZE(1.0f));
2307
2308 pipeline->gras_su_cntl =
2309 tu6_gras_su_cntl(rast_info, builder->samples, builder->multiview_mask != 0);
2310
2311 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_LINE_WIDTH, 2)) {
2312 pipeline->gras_su_cntl |=
2313 A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(rast_info->lineWidth / 2.0f);
2314 tu_cs_emit_regs(&cs, A6XX_GRAS_SU_CNTL(.dword = pipeline->gras_su_cntl));
2315 }
2316
2317 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_DEPTH_BIAS, 4)) {
2318 tu6_emit_depth_bias(&cs, rast_info->depthBiasConstantFactor,
2319 rast_info->depthBiasClamp,
2320 rast_info->depthBiasSlopeFactor);
2321 }
2322
2323 }
2324
2325 static void
2326 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
2327 struct tu_pipeline *pipeline)
2328 {
2329 /* The spec says:
2330 *
2331 * pDepthStencilState is a pointer to an instance of the
2332 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
2333 * the pipeline has rasterization disabled or if the subpass of the
2334 * render pass the pipeline is created against does not use a
2335 * depth/stencil attachment.
2336 *
2337 * Disable both depth and stencil tests if there is no ds attachment,
2338 * Disable depth test if ds attachment is S8_UINT, since S8_UINT defines
2339 * only the separate stencil attachment
2340 */
2341 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info;
2342 const VkPipelineDepthStencilStateCreateInfo *ds_info =
2343 builder->depth_attachment_format != VK_FORMAT_UNDEFINED
2344 ? builder->create_info->pDepthStencilState
2345 : &dummy_ds_info;
2346 const VkPipelineDepthStencilStateCreateInfo *ds_info_depth =
2347 builder->depth_attachment_format != VK_FORMAT_S8_UINT
2348 ? ds_info : &dummy_ds_info;
2349
2350 struct tu_cs cs;
2351 pipeline->ds_state = tu_cs_draw_state(&pipeline->cs, &cs, 6);
2352
2353 /* move to hw ctx init? */
2354 tu_cs_emit_regs(&cs, A6XX_RB_ALPHA_CONTROL());
2355 tu6_emit_depth_control(&cs, ds_info_depth,
2356 builder->create_info->pRasterizationState);
2357 tu6_emit_stencil_control(&cs, ds_info);
2358
2359 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_DEPTH_BOUNDS, 3)) {
2360 tu_cs_emit_regs(&cs,
2361 A6XX_RB_Z_BOUNDS_MIN(ds_info->minDepthBounds),
2362 A6XX_RB_Z_BOUNDS_MAX(ds_info->maxDepthBounds));
2363 }
2364
2365 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK, 2)) {
2366 tu_cs_emit_regs(&cs, A6XX_RB_STENCILMASK(.mask = ds_info->front.compareMask & 0xff,
2367 .bfmask = ds_info->back.compareMask & 0xff));
2368 }
2369
2370 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_STENCIL_WRITE_MASK, 2)) {
2371 tu_cs_emit_regs(&cs, A6XX_RB_STENCILWRMASK(.wrmask = ds_info->front.writeMask & 0xff,
2372 .bfwrmask = ds_info->back.writeMask & 0xff));
2373 }
2374
2375 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_STENCIL_REFERENCE, 2)) {
2376 tu_cs_emit_regs(&cs, A6XX_RB_STENCILREF(.ref = ds_info->front.reference & 0xff,
2377 .bfref = ds_info->back.reference & 0xff));
2378 }
2379 }
2380
2381 static void
2382 tu_pipeline_builder_parse_multisample_and_color_blend(
2383 struct tu_pipeline_builder *builder, struct tu_pipeline *pipeline)
2384 {
2385 /* The spec says:
2386 *
2387 * pMultisampleState is a pointer to an instance of the
2388 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
2389 * has rasterization disabled.
2390 *
2391 * Also,
2392 *
2393 * pColorBlendState is a pointer to an instance of the
2394 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
2395 * pipeline has rasterization disabled or if the subpass of the render
2396 * pass the pipeline is created against does not use any color
2397 * attachments.
2398 *
2399 * We leave the relevant registers stale when rasterization is disabled.
2400 */
2401 if (builder->rasterizer_discard)
2402 return;
2403
2404 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info;
2405 const VkPipelineMultisampleStateCreateInfo *msaa_info =
2406 builder->create_info->pMultisampleState;
2407 const VkPipelineColorBlendStateCreateInfo *blend_info =
2408 builder->use_color_attachments ? builder->create_info->pColorBlendState
2409 : &dummy_blend_info;
2410
2411 struct tu_cs cs;
2412 pipeline->blend_state =
2413 tu_cs_draw_state(&pipeline->cs, &cs, blend_info->attachmentCount * 3 + 4);
2414
2415 uint32_t blend_enable_mask;
2416 tu6_emit_rb_mrt_controls(&cs, blend_info,
2417 builder->color_attachment_formats,
2418 &blend_enable_mask);
2419
2420 tu6_emit_blend_control(&cs, blend_enable_mask,
2421 builder->use_dual_src_blend, msaa_info);
2422
2423 assert(cs.cur == cs.end); /* validate draw state size */
2424
2425 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_BLEND_CONSTANTS, 5)) {
2426 tu_cs_emit_pkt4(&cs, REG_A6XX_RB_BLEND_RED_F32, 4);
2427 tu_cs_emit_array(&cs, (const uint32_t *) blend_info->blendConstants, 4);
2428 }
2429
2430 const struct VkPipelineSampleLocationsStateCreateInfoEXT *sample_locations =
2431 vk_find_struct_const(msaa_info->pNext, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
2432 const VkSampleLocationsInfoEXT *samp_loc = NULL;
2433
2434 if (sample_locations && sample_locations->sampleLocationsEnable)
2435 samp_loc = &sample_locations->sampleLocationsInfo;
2436
2437 if (tu_pipeline_static_state(pipeline, &cs, TU_DYNAMIC_STATE_SAMPLE_LOCATIONS,
2438 samp_loc ? 9 : 6)) {
2439 tu6_emit_sample_locations(&cs, samp_loc);
2440 }
2441 }
2442
2443 static void
2444 tu_pipeline_finish(struct tu_pipeline *pipeline,
2445 struct tu_device *dev,
2446 const VkAllocationCallbacks *alloc)
2447 {
2448 tu_cs_finish(&pipeline->cs);
2449 }
2450
2451 static VkResult
2452 tu_pipeline_builder_build(struct tu_pipeline_builder *builder,
2453 struct tu_pipeline **pipeline)
2454 {
2455 VkResult result;
2456
2457 *pipeline = vk_object_zalloc(&builder->device->vk, builder->alloc,
2458 sizeof(**pipeline), VK_OBJECT_TYPE_PIPELINE);
2459 if (!*pipeline)
2460 return VK_ERROR_OUT_OF_HOST_MEMORY;
2461
2462 (*pipeline)->layout = builder->layout;
2463
2464 /* compile and upload shaders */
2465 result = tu_pipeline_builder_compile_shaders(builder, *pipeline);
2466 if (result != VK_SUCCESS) {
2467 vk_object_free(&builder->device->vk, builder->alloc, *pipeline);
2468 return result;
2469 }
2470
2471 result = tu_pipeline_allocate_cs(builder->device, *pipeline, builder, NULL);
2472 if (result != VK_SUCCESS) {
2473 vk_object_free(&builder->device->vk, builder->alloc, *pipeline);
2474 return result;
2475 }
2476
2477 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
2478 builder->shader_iova[i] = tu_upload_variant(*pipeline, builder->variants[i]);
2479
2480 builder->binning_vs_iova =
2481 tu_upload_variant(*pipeline, builder->binning_variant);
2482
2483 tu_pipeline_builder_parse_dynamic(builder, *pipeline);
2484 tu_pipeline_builder_parse_shader_stages(builder, *pipeline);
2485 tu_pipeline_builder_parse_vertex_input(builder, *pipeline);
2486 tu_pipeline_builder_parse_input_assembly(builder, *pipeline);
2487 tu_pipeline_builder_parse_tessellation(builder, *pipeline);
2488 tu_pipeline_builder_parse_viewport(builder, *pipeline);
2489 tu_pipeline_builder_parse_rasterization(builder, *pipeline);
2490 tu_pipeline_builder_parse_depth_stencil(builder, *pipeline);
2491 tu_pipeline_builder_parse_multisample_and_color_blend(builder, *pipeline);
2492 tu6_emit_load_state(*pipeline, false);
2493
2494 /* we should have reserved enough space upfront such that the CS never
2495 * grows
2496 */
2497 assert((*pipeline)->cs.bo_count == 1);
2498
2499 return VK_SUCCESS;
2500 }
2501
2502 static void
2503 tu_pipeline_builder_finish(struct tu_pipeline_builder *builder)
2504 {
2505 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
2506 if (!builder->shaders[i])
2507 continue;
2508 tu_shader_destroy(builder->device, builder->shaders[i], builder->alloc);
2509 }
2510 }
2511
2512 static void
2513 tu_pipeline_builder_init_graphics(
2514 struct tu_pipeline_builder *builder,
2515 struct tu_device *dev,
2516 struct tu_pipeline_cache *cache,
2517 const VkGraphicsPipelineCreateInfo *create_info,
2518 const VkAllocationCallbacks *alloc)
2519 {
2520 TU_FROM_HANDLE(tu_pipeline_layout, layout, create_info->layout);
2521
2522 *builder = (struct tu_pipeline_builder) {
2523 .device = dev,
2524 .cache = cache,
2525 .create_info = create_info,
2526 .alloc = alloc,
2527 .layout = layout,
2528 };
2529
2530 const struct tu_render_pass *pass =
2531 tu_render_pass_from_handle(create_info->renderPass);
2532 const struct tu_subpass *subpass =
2533 &pass->subpasses[create_info->subpass];
2534
2535 builder->multiview_mask = subpass->multiview_mask;
2536
2537 builder->rasterizer_discard =
2538 create_info->pRasterizationState->rasterizerDiscardEnable;
2539
2540 if (builder->rasterizer_discard) {
2541 builder->samples = VK_SAMPLE_COUNT_1_BIT;
2542 } else {
2543 builder->samples = create_info->pMultisampleState->rasterizationSamples;
2544
2545 const uint32_t a = subpass->depth_stencil_attachment.attachment;
2546 builder->depth_attachment_format = (a != VK_ATTACHMENT_UNUSED) ?
2547 pass->attachments[a].format : VK_FORMAT_UNDEFINED;
2548
2549 assert(subpass->color_count == 0 ||
2550 !create_info->pColorBlendState ||
2551 subpass->color_count == create_info->pColorBlendState->attachmentCount);
2552 builder->color_attachment_count = subpass->color_count;
2553 for (uint32_t i = 0; i < subpass->color_count; i++) {
2554 const uint32_t a = subpass->color_attachments[i].attachment;
2555 if (a == VK_ATTACHMENT_UNUSED)
2556 continue;
2557
2558 builder->color_attachment_formats[i] = pass->attachments[a].format;
2559 builder->use_color_attachments = true;
2560 builder->render_components |= 0xf << (i * 4);
2561 }
2562
2563 if (tu_blend_state_is_dual_src(create_info->pColorBlendState)) {
2564 builder->color_attachment_count++;
2565 builder->use_dual_src_blend = true;
2566 /* dual source blending has an extra fs output in the 2nd slot */
2567 if (subpass->color_attachments[0].attachment != VK_ATTACHMENT_UNUSED)
2568 builder->render_components |= 0xf << 4;
2569 }
2570 }
2571 }
2572
2573 static VkResult
2574 tu_graphics_pipeline_create(VkDevice device,
2575 VkPipelineCache pipelineCache,
2576 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2577 const VkAllocationCallbacks *pAllocator,
2578 VkPipeline *pPipeline)
2579 {
2580 TU_FROM_HANDLE(tu_device, dev, device);
2581 TU_FROM_HANDLE(tu_pipeline_cache, cache, pipelineCache);
2582
2583 struct tu_pipeline_builder builder;
2584 tu_pipeline_builder_init_graphics(&builder, dev, cache,
2585 pCreateInfo, pAllocator);
2586
2587 struct tu_pipeline *pipeline = NULL;
2588 VkResult result = tu_pipeline_builder_build(&builder, &pipeline);
2589 tu_pipeline_builder_finish(&builder);
2590
2591 if (result == VK_SUCCESS)
2592 *pPipeline = tu_pipeline_to_handle(pipeline);
2593 else
2594 *pPipeline = VK_NULL_HANDLE;
2595
2596 return result;
2597 }
2598
2599 VkResult
2600 tu_CreateGraphicsPipelines(VkDevice device,
2601 VkPipelineCache pipelineCache,
2602 uint32_t count,
2603 const VkGraphicsPipelineCreateInfo *pCreateInfos,
2604 const VkAllocationCallbacks *pAllocator,
2605 VkPipeline *pPipelines)
2606 {
2607 VkResult final_result = VK_SUCCESS;
2608
2609 for (uint32_t i = 0; i < count; i++) {
2610 VkResult result = tu_graphics_pipeline_create(device, pipelineCache,
2611 &pCreateInfos[i], pAllocator,
2612 &pPipelines[i]);
2613
2614 if (result != VK_SUCCESS)
2615 final_result = result;
2616 }
2617
2618 return final_result;
2619 }
2620
2621 static VkResult
2622 tu_compute_pipeline_create(VkDevice device,
2623 VkPipelineCache _cache,
2624 const VkComputePipelineCreateInfo *pCreateInfo,
2625 const VkAllocationCallbacks *pAllocator,
2626 VkPipeline *pPipeline)
2627 {
2628 TU_FROM_HANDLE(tu_device, dev, device);
2629 TU_FROM_HANDLE(tu_pipeline_layout, layout, pCreateInfo->layout);
2630 const VkPipelineShaderStageCreateInfo *stage_info = &pCreateInfo->stage;
2631 VkResult result;
2632
2633 struct tu_pipeline *pipeline;
2634
2635 *pPipeline = VK_NULL_HANDLE;
2636
2637 pipeline = vk_object_zalloc(&dev->vk, pAllocator, sizeof(*pipeline),
2638 VK_OBJECT_TYPE_PIPELINE);
2639 if (!pipeline)
2640 return VK_ERROR_OUT_OF_HOST_MEMORY;
2641
2642 pipeline->layout = layout;
2643
2644 struct ir3_shader_key key = {};
2645
2646 struct tu_shader *shader =
2647 tu_shader_create(dev, MESA_SHADER_COMPUTE, stage_info, 0, layout, pAllocator);
2648 if (!shader) {
2649 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2650 goto fail;
2651 }
2652
2653 pipeline->active_desc_sets = shader->active_desc_sets;
2654
2655 bool created;
2656 struct ir3_shader_variant *v =
2657 ir3_shader_get_variant(shader->ir3_shader, &key, false, &created);
2658 if (!v) {
2659 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2660 goto fail;
2661 }
2662
2663 tu_pipeline_set_linkage(&pipeline->program.link[MESA_SHADER_COMPUTE],
2664 shader, v);
2665
2666 result = tu_pipeline_allocate_cs(dev, pipeline, NULL, v);
2667 if (result != VK_SUCCESS)
2668 goto fail;
2669
2670 uint64_t shader_iova = tu_upload_variant(pipeline, v);
2671
2672 for (int i = 0; i < 3; i++)
2673 pipeline->compute.local_size[i] = v->shader->nir->info.cs.local_size[i];
2674
2675 struct tu_cs prog_cs;
2676 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2677 tu6_emit_cs_config(&prog_cs, shader, v, shader_iova);
2678 pipeline->program.state = tu_cs_end_draw_state(&pipeline->cs, &prog_cs);
2679
2680 tu6_emit_load_state(pipeline, true);
2681
2682 *pPipeline = tu_pipeline_to_handle(pipeline);
2683 return VK_SUCCESS;
2684
2685 fail:
2686 if (shader)
2687 tu_shader_destroy(dev, shader, pAllocator);
2688
2689 vk_object_free(&dev->vk, pAllocator, pipeline);
2690
2691 return result;
2692 }
2693
2694 VkResult
2695 tu_CreateComputePipelines(VkDevice device,
2696 VkPipelineCache pipelineCache,
2697 uint32_t count,
2698 const VkComputePipelineCreateInfo *pCreateInfos,
2699 const VkAllocationCallbacks *pAllocator,
2700 VkPipeline *pPipelines)
2701 {
2702 VkResult final_result = VK_SUCCESS;
2703
2704 for (uint32_t i = 0; i < count; i++) {
2705 VkResult result = tu_compute_pipeline_create(device, pipelineCache,
2706 &pCreateInfos[i],
2707 pAllocator, &pPipelines[i]);
2708 if (result != VK_SUCCESS)
2709 final_result = result;
2710 }
2711
2712 return final_result;
2713 }
2714
2715 void
2716 tu_DestroyPipeline(VkDevice _device,
2717 VkPipeline _pipeline,
2718 const VkAllocationCallbacks *pAllocator)
2719 {
2720 TU_FROM_HANDLE(tu_device, dev, _device);
2721 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
2722
2723 if (!_pipeline)
2724 return;
2725
2726 tu_pipeline_finish(pipeline, dev, pAllocator);
2727 vk_object_free(&dev->vk, pAllocator, pipeline);
2728 }