2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 #include "tu_private.h"
30 #include "ir3/ir3_nir.h"
31 #include "main/menums.h"
33 #include "nir/nir_builder.h"
34 #include "spirv/nir_spirv.h"
35 #include "util/debug.h"
36 #include "util/mesa-sha1.h"
37 #include "util/u_atomic.h"
38 #include "vk_format.h"
43 /* Emit IB that preloads the descriptors that the shader uses */
45 static inline uint32_t
46 tu6_vkstage2opcode(VkShaderStageFlags stage
)
49 case VK_SHADER_STAGE_VERTEX_BIT
:
50 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
51 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
52 case VK_SHADER_STAGE_GEOMETRY_BIT
:
53 return CP_LOAD_STATE6_GEOM
;
54 case VK_SHADER_STAGE_FRAGMENT_BIT
:
55 case VK_SHADER_STAGE_COMPUTE_BIT
:
56 return CP_LOAD_STATE6_FRAG
;
58 unreachable("bad shader type");
62 static enum a6xx_state_block
63 tu6_tex_stage2sb(VkShaderStageFlags stage
)
66 case VK_SHADER_STAGE_VERTEX_BIT
:
68 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
70 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
72 case VK_SHADER_STAGE_GEOMETRY_BIT
:
74 case VK_SHADER_STAGE_FRAGMENT_BIT
:
76 case VK_SHADER_STAGE_COMPUTE_BIT
:
79 unreachable("bad shader stage");
83 static enum a6xx_state_block
84 tu6_ubo_stage2sb(VkShaderStageFlags stage
)
87 case VK_SHADER_STAGE_VERTEX_BIT
:
89 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
91 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
93 case VK_SHADER_STAGE_GEOMETRY_BIT
:
95 case VK_SHADER_STAGE_FRAGMENT_BIT
:
97 case VK_SHADER_STAGE_COMPUTE_BIT
:
100 unreachable("bad shader stage");
105 emit_load_state(struct tu_cs
*cs
, unsigned opcode
, enum a6xx_state_type st
,
106 enum a6xx_state_block sb
, unsigned base
, unsigned offset
,
109 /* Note: just emit one packet, even if count overflows NUM_UNIT. It's not
110 * clear if emitting more packets will even help anything. Presumably the
111 * descriptor cache is relatively small, and these packets stop doing
112 * anything when there are too many descriptors.
114 tu_cs_emit_pkt7(cs
, opcode
, 3);
116 CP_LOAD_STATE6_0_STATE_TYPE(st
) |
117 CP_LOAD_STATE6_0_STATE_SRC(SS6_BINDLESS
) |
118 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
119 CP_LOAD_STATE6_0_NUM_UNIT(MIN2(count
, 1024-1)));
120 tu_cs_emit_qw(cs
, offset
| (base
<< 28));
124 tu6_load_state_size(struct tu_pipeline_layout
*layout
, bool compute
)
126 const unsigned load_state_size
= 4;
128 for (unsigned i
= 0; i
< layout
->num_sets
; i
++) {
129 struct tu_descriptor_set_layout
*set_layout
= layout
->set
[i
].layout
;
130 for (unsigned j
= 0; j
< set_layout
->binding_count
; j
++) {
131 struct tu_descriptor_set_binding_layout
*binding
= &set_layout
->binding
[j
];
133 /* Note: some users, like amber for example, pass in
134 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
135 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
137 VkShaderStageFlags stages
= compute
?
138 binding
->shader_stages
& VK_SHADER_STAGE_COMPUTE_BIT
:
139 binding
->shader_stages
& VK_SHADER_STAGE_ALL_GRAPHICS
;
140 unsigned stage_count
= util_bitcount(stages
);
141 switch (binding
->type
) {
142 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
143 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
144 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
:
145 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
146 /* IBO-backed resources only need one packet for all graphics stages */
147 if (stages
& ~VK_SHADER_STAGE_COMPUTE_BIT
)
149 if (stages
& VK_SHADER_STAGE_COMPUTE_BIT
)
152 case VK_DESCRIPTOR_TYPE_SAMPLER
:
153 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
154 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
155 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
156 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
157 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
158 /* Textures and UBO's needs a packet for each stage */
161 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
162 /* Because of how we pack combined images and samplers, we
163 * currently can't use one packet for the whole array.
165 count
= stage_count
* binding
->array_size
* 2;
168 unreachable("bad descriptor type");
170 size
+= count
* load_state_size
;
177 tu6_emit_load_state(struct tu_pipeline
*pipeline
, bool compute
)
179 unsigned size
= tu6_load_state_size(pipeline
->layout
, compute
);
184 tu_cs_begin_sub_stream(&pipeline
->cs
, size
, &cs
);
186 struct tu_pipeline_layout
*layout
= pipeline
->layout
;
187 for (unsigned i
= 0; i
< layout
->num_sets
; i
++) {
188 struct tu_descriptor_set_layout
*set_layout
= layout
->set
[i
].layout
;
189 for (unsigned j
= 0; j
< set_layout
->binding_count
; j
++) {
190 struct tu_descriptor_set_binding_layout
*binding
= &set_layout
->binding
[j
];
192 unsigned offset
= binding
->offset
/ 4;
193 /* Note: some users, like amber for example, pass in
194 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
195 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
197 VkShaderStageFlags stages
= compute
?
198 binding
->shader_stages
& VK_SHADER_STAGE_COMPUTE_BIT
:
199 binding
->shader_stages
& VK_SHADER_STAGE_ALL_GRAPHICS
;
200 unsigned count
= binding
->array_size
;
201 if (count
== 0 || stages
== 0)
203 switch (binding
->type
) {
204 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
206 offset
= (layout
->input_attachment_count
+
207 layout
->set
[i
].dynamic_offset_start
+
208 binding
->dynamic_offset_offset
) * A6XX_TEX_CONST_DWORDS
;
210 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
211 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
:
212 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
213 /* IBO-backed resources only need one packet for all graphics stages */
214 if (stages
& ~VK_SHADER_STAGE_COMPUTE_BIT
) {
215 emit_load_state(&cs
, CP_LOAD_STATE6
, ST6_SHADER
, SB6_IBO
,
216 base
, offset
, count
);
218 if (stages
& VK_SHADER_STAGE_COMPUTE_BIT
) {
219 emit_load_state(&cs
, CP_LOAD_STATE6_FRAG
, ST6_IBO
, SB6_CS_SHADER
,
220 base
, offset
, count
);
223 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
225 offset
= (layout
->set
[i
].input_attachment_start
+
226 binding
->input_attachment_offset
) * A6XX_TEX_CONST_DWORDS
;
227 case VK_DESCRIPTOR_TYPE_SAMPLER
:
228 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
229 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
: {
231 for_each_bit(stage_log2
, stages
) {
232 VkShaderStageFlags stage
= 1 << stage_log2
;
233 emit_load_state(&cs
, tu6_vkstage2opcode(stage
),
234 binding
->type
== VK_DESCRIPTOR_TYPE_SAMPLER
?
235 ST6_SHADER
: ST6_CONSTANTS
,
236 tu6_tex_stage2sb(stage
), base
, offset
, count
);
240 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
242 offset
= (layout
->input_attachment_count
+
243 layout
->set
[i
].dynamic_offset_start
+
244 binding
->dynamic_offset_offset
) * A6XX_TEX_CONST_DWORDS
;
246 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
: {
248 for_each_bit(stage_log2
, stages
) {
249 VkShaderStageFlags stage
= 1 << stage_log2
;
250 emit_load_state(&cs
, tu6_vkstage2opcode(stage
), ST6_UBO
,
251 tu6_ubo_stage2sb(stage
), base
, offset
, count
);
255 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
: {
257 for_each_bit(stage_log2
, stages
) {
258 VkShaderStageFlags stage
= 1 << stage_log2
;
259 /* TODO: We could emit less CP_LOAD_STATE6 if we used
260 * struct-of-arrays instead of array-of-structs.
262 for (unsigned i
= 0; i
< count
; i
++) {
263 unsigned tex_offset
= offset
+ 2 * i
* A6XX_TEX_CONST_DWORDS
;
264 unsigned sam_offset
= offset
+ (2 * i
+ 1) * A6XX_TEX_CONST_DWORDS
;
265 emit_load_state(&cs
, tu6_vkstage2opcode(stage
),
266 ST6_CONSTANTS
, tu6_tex_stage2sb(stage
),
267 base
, tex_offset
, 1);
268 emit_load_state(&cs
, tu6_vkstage2opcode(stage
),
269 ST6_SHADER
, tu6_tex_stage2sb(stage
),
270 base
, sam_offset
, 1);
276 unreachable("bad descriptor type");
281 pipeline
->load_state
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &cs
);
284 struct tu_pipeline_builder
286 struct tu_device
*device
;
287 struct tu_pipeline_cache
*cache
;
288 struct tu_pipeline_layout
*layout
;
289 const VkAllocationCallbacks
*alloc
;
290 const VkGraphicsPipelineCreateInfo
*create_info
;
292 struct tu_shader
*shaders
[MESA_SHADER_STAGES
];
293 uint32_t shader_offsets
[MESA_SHADER_STAGES
];
294 uint32_t binning_vs_offset
;
295 uint32_t shader_total_size
;
297 bool rasterizer_discard
;
298 /* these states are affectd by rasterizer_discard */
299 VkSampleCountFlagBits samples
;
300 bool use_color_attachments
;
301 uint32_t color_attachment_count
;
302 VkFormat color_attachment_formats
[MAX_RTS
];
303 VkFormat depth_attachment_format
;
306 static enum tu_dynamic_state_bits
307 tu_dynamic_state_bit(VkDynamicState state
)
310 case VK_DYNAMIC_STATE_VIEWPORT
:
311 return TU_DYNAMIC_VIEWPORT
;
312 case VK_DYNAMIC_STATE_SCISSOR
:
313 return TU_DYNAMIC_SCISSOR
;
314 case VK_DYNAMIC_STATE_LINE_WIDTH
:
315 return TU_DYNAMIC_LINE_WIDTH
;
316 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
317 return TU_DYNAMIC_DEPTH_BIAS
;
318 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
319 return TU_DYNAMIC_BLEND_CONSTANTS
;
320 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
321 return TU_DYNAMIC_DEPTH_BOUNDS
;
322 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
323 return TU_DYNAMIC_STENCIL_COMPARE_MASK
;
324 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
325 return TU_DYNAMIC_STENCIL_WRITE_MASK
;
326 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
327 return TU_DYNAMIC_STENCIL_REFERENCE
;
328 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT
:
329 return TU_DYNAMIC_SAMPLE_LOCATIONS
;
331 unreachable("invalid dynamic state");
336 static gl_shader_stage
337 tu_shader_stage(VkShaderStageFlagBits stage
)
340 case VK_SHADER_STAGE_VERTEX_BIT
:
341 return MESA_SHADER_VERTEX
;
342 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
343 return MESA_SHADER_TESS_CTRL
;
344 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
345 return MESA_SHADER_TESS_EVAL
;
346 case VK_SHADER_STAGE_GEOMETRY_BIT
:
347 return MESA_SHADER_GEOMETRY
;
348 case VK_SHADER_STAGE_FRAGMENT_BIT
:
349 return MESA_SHADER_FRAGMENT
;
350 case VK_SHADER_STAGE_COMPUTE_BIT
:
351 return MESA_SHADER_COMPUTE
;
353 unreachable("invalid VkShaderStageFlagBits");
354 return MESA_SHADER_NONE
;
359 tu_logic_op_reads_dst(VkLogicOp op
)
362 case VK_LOGIC_OP_CLEAR
:
363 case VK_LOGIC_OP_COPY
:
364 case VK_LOGIC_OP_COPY_INVERTED
:
365 case VK_LOGIC_OP_SET
:
373 tu_blend_factor_no_dst_alpha(VkBlendFactor factor
)
375 /* treat dst alpha as 1.0 and avoid reading it */
377 case VK_BLEND_FACTOR_DST_ALPHA
:
378 return VK_BLEND_FACTOR_ONE
;
379 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
380 return VK_BLEND_FACTOR_ZERO
;
386 static enum pc_di_primtype
387 tu6_primtype(VkPrimitiveTopology topology
)
390 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
391 return DI_PT_POINTLIST
;
392 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
393 return DI_PT_LINELIST
;
394 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
395 return DI_PT_LINESTRIP
;
396 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
397 return DI_PT_TRILIST
;
398 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
399 return DI_PT_TRISTRIP
;
400 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
402 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
403 return DI_PT_LINE_ADJ
;
404 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
405 return DI_PT_LINESTRIP_ADJ
;
406 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
407 return DI_PT_TRI_ADJ
;
408 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
409 return DI_PT_TRISTRIP_ADJ
;
410 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
412 unreachable("invalid primitive topology");
417 static enum adreno_compare_func
418 tu6_compare_func(VkCompareOp op
)
421 case VK_COMPARE_OP_NEVER
:
423 case VK_COMPARE_OP_LESS
:
425 case VK_COMPARE_OP_EQUAL
:
427 case VK_COMPARE_OP_LESS_OR_EQUAL
:
429 case VK_COMPARE_OP_GREATER
:
431 case VK_COMPARE_OP_NOT_EQUAL
:
432 return FUNC_NOTEQUAL
;
433 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
435 case VK_COMPARE_OP_ALWAYS
:
438 unreachable("invalid VkCompareOp");
443 static enum adreno_stencil_op
444 tu6_stencil_op(VkStencilOp op
)
447 case VK_STENCIL_OP_KEEP
:
449 case VK_STENCIL_OP_ZERO
:
451 case VK_STENCIL_OP_REPLACE
:
452 return STENCIL_REPLACE
;
453 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
454 return STENCIL_INCR_CLAMP
;
455 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
456 return STENCIL_DECR_CLAMP
;
457 case VK_STENCIL_OP_INVERT
:
458 return STENCIL_INVERT
;
459 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
460 return STENCIL_INCR_WRAP
;
461 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
462 return STENCIL_DECR_WRAP
;
464 unreachable("invalid VkStencilOp");
469 static enum a3xx_rop_code
470 tu6_rop(VkLogicOp op
)
473 case VK_LOGIC_OP_CLEAR
:
475 case VK_LOGIC_OP_AND
:
477 case VK_LOGIC_OP_AND_REVERSE
:
478 return ROP_AND_REVERSE
;
479 case VK_LOGIC_OP_COPY
:
481 case VK_LOGIC_OP_AND_INVERTED
:
482 return ROP_AND_INVERTED
;
483 case VK_LOGIC_OP_NO_OP
:
485 case VK_LOGIC_OP_XOR
:
489 case VK_LOGIC_OP_NOR
:
491 case VK_LOGIC_OP_EQUIVALENT
:
493 case VK_LOGIC_OP_INVERT
:
495 case VK_LOGIC_OP_OR_REVERSE
:
496 return ROP_OR_REVERSE
;
497 case VK_LOGIC_OP_COPY_INVERTED
:
498 return ROP_COPY_INVERTED
;
499 case VK_LOGIC_OP_OR_INVERTED
:
500 return ROP_OR_INVERTED
;
501 case VK_LOGIC_OP_NAND
:
503 case VK_LOGIC_OP_SET
:
506 unreachable("invalid VkLogicOp");
511 static enum adreno_rb_blend_factor
512 tu6_blend_factor(VkBlendFactor factor
)
515 case VK_BLEND_FACTOR_ZERO
:
517 case VK_BLEND_FACTOR_ONE
:
519 case VK_BLEND_FACTOR_SRC_COLOR
:
520 return FACTOR_SRC_COLOR
;
521 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
522 return FACTOR_ONE_MINUS_SRC_COLOR
;
523 case VK_BLEND_FACTOR_DST_COLOR
:
524 return FACTOR_DST_COLOR
;
525 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
526 return FACTOR_ONE_MINUS_DST_COLOR
;
527 case VK_BLEND_FACTOR_SRC_ALPHA
:
528 return FACTOR_SRC_ALPHA
;
529 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
530 return FACTOR_ONE_MINUS_SRC_ALPHA
;
531 case VK_BLEND_FACTOR_DST_ALPHA
:
532 return FACTOR_DST_ALPHA
;
533 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
534 return FACTOR_ONE_MINUS_DST_ALPHA
;
535 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
536 return FACTOR_CONSTANT_COLOR
;
537 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
538 return FACTOR_ONE_MINUS_CONSTANT_COLOR
;
539 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
540 return FACTOR_CONSTANT_ALPHA
;
541 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
542 return FACTOR_ONE_MINUS_CONSTANT_ALPHA
;
543 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
544 return FACTOR_SRC_ALPHA_SATURATE
;
545 case VK_BLEND_FACTOR_SRC1_COLOR
:
546 return FACTOR_SRC1_COLOR
;
547 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
548 return FACTOR_ONE_MINUS_SRC1_COLOR
;
549 case VK_BLEND_FACTOR_SRC1_ALPHA
:
550 return FACTOR_SRC1_ALPHA
;
551 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
552 return FACTOR_ONE_MINUS_SRC1_ALPHA
;
554 unreachable("invalid VkBlendFactor");
559 static enum a3xx_rb_blend_opcode
560 tu6_blend_op(VkBlendOp op
)
563 case VK_BLEND_OP_ADD
:
564 return BLEND_DST_PLUS_SRC
;
565 case VK_BLEND_OP_SUBTRACT
:
566 return BLEND_SRC_MINUS_DST
;
567 case VK_BLEND_OP_REVERSE_SUBTRACT
:
568 return BLEND_DST_MINUS_SRC
;
569 case VK_BLEND_OP_MIN
:
570 return BLEND_MIN_DST_SRC
;
571 case VK_BLEND_OP_MAX
:
572 return BLEND_MAX_DST_SRC
;
574 unreachable("invalid VkBlendOp");
575 return BLEND_DST_PLUS_SRC
;
580 emit_xs_config(const struct ir3_shader_variant
*sh
)
583 return A6XX_SP_VS_CONFIG_ENABLED
|
584 COND(sh
->bindless_tex
, A6XX_SP_VS_CONFIG_BINDLESS_TEX
) |
585 COND(sh
->bindless_samp
, A6XX_SP_VS_CONFIG_BINDLESS_SAMP
) |
586 COND(sh
->bindless_ibo
, A6XX_SP_VS_CONFIG_BINDLESS_IBO
) |
587 COND(sh
->bindless_ubo
, A6XX_SP_VS_CONFIG_BINDLESS_UBO
);
594 tu6_emit_vs_config(struct tu_cs
*cs
, struct tu_shader
*shader
,
595 const struct ir3_shader_variant
*vs
)
597 uint32_t sp_vs_ctrl
=
598 A6XX_SP_VS_CTRL_REG0_THREADSIZE(FOUR_QUADS
) |
599 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs
->info
.max_reg
+ 1) |
600 A6XX_SP_VS_CTRL_REG0_MERGEDREGS
|
601 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs
->branchstack
);
603 sp_vs_ctrl
|= A6XX_SP_VS_CTRL_REG0_PIXLODENABLE
;
604 if (vs
->need_fine_derivatives
)
605 sp_vs_ctrl
|= A6XX_SP_VS_CTRL_REG0_DIFF_FINE
;
607 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_VS_CTRL_REG0
, 1);
608 tu_cs_emit(cs
, sp_vs_ctrl
);
610 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_VS_CONFIG
, 2);
611 tu_cs_emit(cs
, emit_xs_config(vs
));
612 tu_cs_emit(cs
, vs
->instrlen
);
614 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_VS_CNTL
, 1);
615 tu_cs_emit(cs
, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(vs
->constlen
, 4)) |
616 A6XX_HLSQ_VS_CNTL_ENABLED
);
620 tu6_emit_hs_config(struct tu_cs
*cs
, struct tu_shader
*shader
,
621 const struct ir3_shader_variant
*hs
)
623 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_HS_UNKNOWN_A831
, 1);
626 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_HS_CONFIG
, 2);
627 tu_cs_emit(cs
, emit_xs_config(hs
));
628 tu_cs_emit(cs
, hs
->instrlen
);
630 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_HS_CNTL
, 1);
631 tu_cs_emit(cs
, A6XX_HLSQ_HS_CNTL_CONSTLEN(align(hs
->constlen
, 4)));
635 tu6_emit_ds_config(struct tu_cs
*cs
, struct tu_shader
*shader
,
636 const struct ir3_shader_variant
*ds
)
638 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_DS_CONFIG
, 2);
639 tu_cs_emit(cs
, emit_xs_config(ds
));
640 tu_cs_emit(cs
, ds
->instrlen
);
642 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_DS_CNTL
, 1);
643 tu_cs_emit(cs
, A6XX_HLSQ_DS_CNTL_CONSTLEN(align(ds
->constlen
, 4)));
647 tu6_emit_gs_config(struct tu_cs
*cs
, struct tu_shader
*shader
,
648 const struct ir3_shader_variant
*gs
)
650 bool has_gs
= gs
->type
!= MESA_SHADER_NONE
;
651 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_UNKNOWN_A871
, 1);
654 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_CONFIG
, 2);
655 tu_cs_emit(cs
, emit_xs_config(gs
));
656 tu_cs_emit(cs
, gs
->instrlen
);
658 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_GS_CNTL
, 1);
659 tu_cs_emit(cs
, COND(has_gs
, A6XX_HLSQ_GS_CNTL_ENABLED
) |
660 A6XX_HLSQ_GS_CNTL_CONSTLEN(align(gs
->constlen
, 4)));
664 tu6_emit_fs_config(struct tu_cs
*cs
, struct tu_shader
*shader
,
665 const struct ir3_shader_variant
*fs
)
667 uint32_t sp_fs_ctrl
=
668 A6XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS
) | 0x1000000 |
669 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs
->info
.max_reg
+ 1) |
670 A6XX_SP_FS_CTRL_REG0_MERGEDREGS
|
671 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs
->branchstack
);
672 if (fs
->total_in
> 0)
673 sp_fs_ctrl
|= A6XX_SP_FS_CTRL_REG0_VARYING
;
675 sp_fs_ctrl
|= A6XX_SP_FS_CTRL_REG0_PIXLODENABLE
;
676 if (fs
->need_fine_derivatives
)
677 sp_fs_ctrl
|= A6XX_SP_FS_CTRL_REG0_DIFF_FINE
;
679 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_CTRL_REG0
, 1);
680 tu_cs_emit(cs
, sp_fs_ctrl
);
682 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_CONFIG
, 2);
683 tu_cs_emit(cs
, emit_xs_config(fs
));
684 tu_cs_emit(cs
, fs
->instrlen
);
686 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_FS_CNTL
, 1);
687 tu_cs_emit(cs
, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(fs
->constlen
, 4)) |
688 A6XX_HLSQ_FS_CNTL_ENABLED
);
692 tu6_emit_cs_config(struct tu_cs
*cs
, const struct tu_shader
*shader
,
693 const struct ir3_shader_variant
*v
)
695 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_UPDATE_CNTL
, 1);
696 tu_cs_emit(cs
, 0xff);
698 unsigned constlen
= align(v
->constlen
, 4);
699 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_CS_CNTL
, 1);
700 tu_cs_emit(cs
, A6XX_HLSQ_CS_CNTL_CONSTLEN(constlen
) |
701 A6XX_HLSQ_CS_CNTL_ENABLED
);
703 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_CS_CONFIG
, 2);
704 tu_cs_emit(cs
, emit_xs_config(v
));
705 tu_cs_emit(cs
, v
->instrlen
);
707 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_CS_CTRL_REG0
, 1);
708 tu_cs_emit(cs
, A6XX_SP_CS_CTRL_REG0_THREADSIZE(FOUR_QUADS
) |
709 A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(v
->info
.max_reg
+ 1) |
710 A6XX_SP_CS_CTRL_REG0_MERGEDREGS
|
711 A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(v
->branchstack
) |
712 COND(v
->need_pixlod
, A6XX_SP_CS_CTRL_REG0_PIXLODENABLE
) |
713 COND(v
->need_fine_derivatives
, A6XX_SP_CS_CTRL_REG0_DIFF_FINE
));
715 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_CS_UNKNOWN_A9B1
, 1);
716 tu_cs_emit(cs
, 0x41);
718 uint32_t local_invocation_id
=
719 ir3_find_sysval_regid(v
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
);
720 uint32_t work_group_id
=
721 ir3_find_sysval_regid(v
, SYSTEM_VALUE_WORK_GROUP_ID
);
723 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_CS_CNTL_0
, 2);
725 A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id
) |
726 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
727 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
728 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id
));
729 tu_cs_emit(cs
, 0x2fc); /* HLSQ_CS_UNKNOWN_B998 */
733 tu6_emit_vs_system_values(struct tu_cs
*cs
,
734 const struct ir3_shader_variant
*vs
,
735 const struct ir3_shader_variant
*gs
)
737 const uint32_t vertexid_regid
=
738 ir3_find_sysval_regid(vs
, SYSTEM_VALUE_VERTEX_ID
);
739 const uint32_t instanceid_regid
=
740 ir3_find_sysval_regid(vs
, SYSTEM_VALUE_INSTANCE_ID
);
741 const uint32_t primitiveid_regid
= gs
->type
!= MESA_SHADER_NONE
?
742 ir3_find_sysval_regid(gs
, SYSTEM_VALUE_PRIMITIVE_ID
) :
744 const uint32_t gsheader_regid
= gs
->type
!= MESA_SHADER_NONE
?
745 ir3_find_sysval_regid(gs
, SYSTEM_VALUE_GS_HEADER_IR3
) :
748 tu_cs_emit_pkt4(cs
, REG_A6XX_VFD_CONTROL_1
, 6);
749 tu_cs_emit(cs
, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid
) |
750 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid
) |
751 A6XX_VFD_CONTROL_1_REGID4PRIMID(primitiveid_regid
) |
753 tu_cs_emit(cs
, 0x0000fcfc); /* VFD_CONTROL_2 */
754 tu_cs_emit(cs
, 0xfcfcfcfc); /* VFD_CONTROL_3 */
755 tu_cs_emit(cs
, 0x000000fc); /* VFD_CONTROL_4 */
756 tu_cs_emit(cs
, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gsheader_regid
) |
757 0xfc00); /* VFD_CONTROL_5 */
758 tu_cs_emit(cs
, 0x00000000); /* VFD_CONTROL_6 */
761 /* Add any missing varyings needed for stream-out. Otherwise varyings not
762 * used by fragment shader will be stripped out.
765 tu6_link_streamout(struct ir3_shader_linkage
*l
,
766 const struct ir3_shader_variant
*v
)
768 const struct ir3_stream_output_info
*info
= &v
->shader
->stream_output
;
771 * First, any stream-out varyings not already in linkage map (ie. also
772 * consumed by frag shader) need to be added:
774 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
775 const struct ir3_stream_output
*out
= &info
->output
[i
];
777 (1 << (out
->num_components
+ out
->start_component
)) - 1;
778 unsigned k
= out
->register_index
;
779 unsigned idx
, nextloc
= 0;
781 /* psize/pos need to be the last entries in linkage map, and will
782 * get added link_stream_out, so skip over them:
784 if (v
->outputs
[k
].slot
== VARYING_SLOT_PSIZ
||
785 v
->outputs
[k
].slot
== VARYING_SLOT_POS
)
788 for (idx
= 0; idx
< l
->cnt
; idx
++) {
789 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
791 nextloc
= MAX2(nextloc
, l
->var
[idx
].loc
+ 4);
794 /* add if not already in linkage map: */
796 ir3_link_add(l
, v
->outputs
[k
].regid
, compmask
, nextloc
);
798 /* expand component-mask if needed, ie streaming out all components
799 * but frag shader doesn't consume all components:
801 if (compmask
& ~l
->var
[idx
].compmask
) {
802 l
->var
[idx
].compmask
|= compmask
;
803 l
->max_loc
= MAX2(l
->max_loc
, l
->var
[idx
].loc
+
804 util_last_bit(l
->var
[idx
].compmask
));
810 tu6_setup_streamout(const struct ir3_shader_variant
*v
,
811 struct ir3_shader_linkage
*l
, struct tu_streamout_state
*tf
)
813 const struct ir3_stream_output_info
*info
= &v
->shader
->stream_output
;
815 memset(tf
, 0, sizeof(*tf
));
817 tf
->prog_count
= align(l
->max_loc
, 2) / 2;
819 debug_assert(tf
->prog_count
< ARRAY_SIZE(tf
->prog
));
821 /* set stride info to the streamout state */
822 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++)
823 tf
->stride
[i
] = info
->stride
[i
];
825 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
826 const struct ir3_stream_output
*out
= &info
->output
[i
];
827 unsigned k
= out
->register_index
;
830 /* Skip it, if there's an unused reg in the middle of outputs. */
831 if (v
->outputs
[k
].regid
== INVALID_REG
)
834 tf
->ncomp
[out
->output_buffer
] += out
->num_components
;
836 /* linkage map sorted by order frag shader wants things, so
837 * a bit less ideal here..
839 for (idx
= 0; idx
< l
->cnt
; idx
++)
840 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
843 debug_assert(idx
< l
->cnt
);
845 for (unsigned j
= 0; j
< out
->num_components
; j
++) {
846 unsigned c
= j
+ out
->start_component
;
847 unsigned loc
= l
->var
[idx
].loc
+ c
;
848 unsigned off
= j
+ out
->dst_offset
; /* in dwords */
851 tf
->prog
[loc
/2] |= A6XX_VPC_SO_PROG_B_EN
|
852 A6XX_VPC_SO_PROG_B_BUF(out
->output_buffer
) |
853 A6XX_VPC_SO_PROG_B_OFF(off
* 4);
855 tf
->prog
[loc
/2] |= A6XX_VPC_SO_PROG_A_EN
|
856 A6XX_VPC_SO_PROG_A_BUF(out
->output_buffer
) |
857 A6XX_VPC_SO_PROG_A_OFF(off
* 4);
862 tf
->vpc_so_buf_cntl
= A6XX_VPC_SO_BUF_CNTL_ENABLE
|
863 COND(tf
->ncomp
[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0
) |
864 COND(tf
->ncomp
[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1
) |
865 COND(tf
->ncomp
[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2
) |
866 COND(tf
->ncomp
[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3
);
870 tu6_emit_const(struct tu_cs
*cs
, uint32_t opcode
, uint32_t base
,
871 enum a6xx_state_block block
, uint32_t offset
,
872 uint32_t size
, uint32_t *dwords
) {
873 assert(size
% 4 == 0);
875 tu_cs_emit_pkt7(cs
, opcode
, 3 + size
);
876 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(base
) |
877 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
878 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
879 CP_LOAD_STATE6_0_STATE_BLOCK(block
) |
880 CP_LOAD_STATE6_0_NUM_UNIT(size
/ 4));
882 tu_cs_emit(cs
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
883 tu_cs_emit(cs
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
884 dwords
= (uint32_t *)&((uint8_t *)dwords
)[offset
];
886 tu_cs_emit_array(cs
, dwords
, size
);
890 tu6_emit_link_map(struct tu_cs
*cs
,
891 const struct ir3_shader_variant
*producer
,
892 const struct ir3_shader_variant
*consumer
) {
893 const struct ir3_const_state
*const_state
= &consumer
->shader
->const_state
;
894 uint32_t base
= const_state
->offsets
.primitive_map
;
895 uint32_t patch_locs
[MAX_VARYING
] = { }, num_loc
;
896 num_loc
= ir3_link_geometry_stages(producer
, consumer
, patch_locs
);
897 int size
= DIV_ROUND_UP(num_loc
, 4);
899 size
= (MIN2(size
+ base
, consumer
->constlen
) - base
) * 4;
901 tu6_emit_const(cs
, CP_LOAD_STATE6_GEOM
, base
, SB6_GS_SHADER
, 0, size
,
906 gl_primitive_to_tess(uint16_t primitive
) {
912 case GL_TRIANGLE_STRIP
:
920 tu6_emit_vpc(struct tu_cs
*cs
,
921 const struct ir3_shader_variant
*vs
,
922 const struct ir3_shader_variant
*gs
,
923 const struct ir3_shader_variant
*fs
,
925 struct tu_streamout_state
*tf
)
927 bool has_gs
= gs
->type
!= MESA_SHADER_NONE
;
928 const struct ir3_shader_variant
*last_shader
= has_gs
? gs
: vs
;
929 struct ir3_shader_linkage linkage
= { 0 };
930 ir3_link_shaders(&linkage
, last_shader
, fs
);
932 if (last_shader
->shader
->stream_output
.num_outputs
)
933 tu6_link_streamout(&linkage
, last_shader
);
935 BITSET_DECLARE(vpc_var_enables
, 128) = { 0 };
936 for (uint32_t i
= 0; i
< linkage
.cnt
; i
++) {
937 const uint32_t comp_count
= util_last_bit(linkage
.var
[i
].compmask
);
938 for (uint32_t j
= 0; j
< comp_count
; j
++)
939 BITSET_SET(vpc_var_enables
, linkage
.var
[i
].loc
+ j
);
942 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_VAR_DISABLE(0), 4);
943 tu_cs_emit(cs
, ~vpc_var_enables
[0]);
944 tu_cs_emit(cs
, ~vpc_var_enables
[1]);
945 tu_cs_emit(cs
, ~vpc_var_enables
[2]);
946 tu_cs_emit(cs
, ~vpc_var_enables
[3]);
948 /* a6xx finds position/pointsize at the end */
949 const uint32_t position_regid
=
950 ir3_find_output_regid(last_shader
, VARYING_SLOT_POS
);
951 const uint32_t pointsize_regid
=
952 ir3_find_output_regid(last_shader
, VARYING_SLOT_PSIZ
);
953 const uint32_t layer_regid
= has_gs
?
954 ir3_find_output_regid(gs
, VARYING_SLOT_LAYER
) : regid(63, 0);
956 uint32_t pointsize_loc
= 0xff, position_loc
= 0xff, layer_loc
= 0xff;
957 if (layer_regid
!= regid(63, 0)) {
958 layer_loc
= linkage
.max_loc
;
959 ir3_link_add(&linkage
, layer_regid
, 0x1, linkage
.max_loc
);
961 if (position_regid
!= regid(63, 0)) {
962 position_loc
= linkage
.max_loc
;
963 ir3_link_add(&linkage
, position_regid
, 0xf, linkage
.max_loc
);
965 if (pointsize_regid
!= regid(63, 0)) {
966 pointsize_loc
= linkage
.max_loc
;
967 ir3_link_add(&linkage
, pointsize_regid
, 0x1, linkage
.max_loc
);
970 if (last_shader
->shader
->stream_output
.num_outputs
)
971 tu6_setup_streamout(last_shader
, &linkage
, tf
);
973 /* map outputs of the last shader to VPC */
974 assert(linkage
.cnt
<= 32);
975 const uint32_t sp_out_count
= DIV_ROUND_UP(linkage
.cnt
, 2);
976 const uint32_t sp_vpc_dst_count
= DIV_ROUND_UP(linkage
.cnt
, 4);
978 uint32_t sp_vpc_dst
[8];
979 for (uint32_t i
= 0; i
< linkage
.cnt
; i
++) {
980 ((uint16_t *) sp_out
)[i
] =
981 A6XX_SP_VS_OUT_REG_A_REGID(linkage
.var
[i
].regid
) |
982 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage
.var
[i
].compmask
);
983 ((uint8_t *) sp_vpc_dst
)[i
] =
984 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage
.var
[i
].loc
);
988 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_OUT_REG(0), sp_out_count
);
990 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_VS_OUT_REG(0), sp_out_count
);
991 tu_cs_emit_array(cs
, sp_out
, sp_out_count
);
994 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_VPC_DST_REG(0), sp_vpc_dst_count
);
996 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_VS_VPC_DST_REG(0), sp_vpc_dst_count
);
997 tu_cs_emit_array(cs
, sp_vpc_dst
, sp_vpc_dst_count
);
999 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_CNTL_0
, 1);
1000 tu_cs_emit(cs
, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs
->total_in
) |
1001 (fs
->total_in
> 0 ? A6XX_VPC_CNTL_0_VARYING
: 0) |
1004 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_PACK
, 1);
1005 tu_cs_emit(cs
, A6XX_VPC_PACK_POSITIONLOC(position_loc
) |
1006 A6XX_VPC_PACK_PSIZELOC(pointsize_loc
) |
1007 A6XX_VPC_PACK_STRIDE_IN_VPC(linkage
.max_loc
));
1010 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_CTRL_REG0
, 1);
1011 tu_cs_emit(cs
, A6XX_SP_GS_CTRL_REG0_THREADSIZE(TWO_QUADS
) |
1012 A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(gs
->info
.max_reg
+ 1) |
1013 A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(gs
->branchstack
) |
1014 COND(gs
->need_pixlod
, A6XX_SP_GS_CTRL_REG0_PIXLODENABLE
));
1016 tu6_emit_link_map(cs
, vs
, gs
);
1018 uint32_t primitive_regid
=
1019 ir3_find_sysval_regid(gs
, SYSTEM_VALUE_PRIMITIVE_ID
);
1020 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_PACK_GS
, 1);
1021 tu_cs_emit(cs
, A6XX_VPC_PACK_GS_POSITIONLOC(position_loc
) |
1022 A6XX_VPC_PACK_GS_PSIZELOC(pointsize_loc
) |
1023 A6XX_VPC_PACK_GS_STRIDE_IN_VPC(linkage
.max_loc
));
1025 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_UNKNOWN_9105
, 1);
1026 tu_cs_emit(cs
, A6XX_VPC_UNKNOWN_9105_LAYERLOC(layer_loc
) | 0xff00);
1028 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_UNKNOWN_809C
, 1);
1029 tu_cs_emit(cs
, CONDREG(layer_regid
,
1030 A6XX_GRAS_UNKNOWN_809C_GS_WRITES_LAYER
));
1032 uint32_t flags_regid
= ir3_find_output_regid(gs
,
1033 VARYING_SLOT_GS_VERTEX_FLAGS_IR3
);
1035 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_PRIMITIVE_CNTL_GS
, 1);
1036 tu_cs_emit(cs
, A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT(linkage
.cnt
) |
1037 A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID(flags_regid
));
1039 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_2
, 1);
1040 tu_cs_emit(cs
, A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC(linkage
.max_loc
) |
1041 CONDREG(pointsize_regid
, A6XX_PC_PRIMITIVE_CNTL_2_PSIZE
) |
1042 CONDREG(layer_regid
, A6XX_PC_PRIMITIVE_CNTL_2_LAYER
) |
1043 CONDREG(primitive_regid
, A6XX_PC_PRIMITIVE_CNTL_2_PRIMITIVE_ID
));
1045 uint32_t vertices_out
= gs
->shader
->nir
->info
.gs
.vertices_out
- 1;
1047 gl_primitive_to_tess(gs
->shader
->nir
->info
.gs
.output_primitive
);
1048 uint32_t invocations
= gs
->shader
->nir
->info
.gs
.invocations
- 1;
1049 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_5
, 1);
1051 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(vertices_out
) |
1052 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output
) |
1053 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(invocations
));
1055 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_3
, 1);
1058 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_UNKNOWN_8003
, 1);
1061 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_UNKNOWN_9100
, 1);
1062 tu_cs_emit(cs
, 0xff);
1064 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_UNKNOWN_9102
, 1);
1065 tu_cs_emit(cs
, 0xffff00);
1067 /* Size of per-primitive alloction in ldlw memory in vec4s. */
1068 uint32_t vec4_size
=
1069 gs
->shader
->nir
->info
.gs
.vertices_in
*
1070 DIV_ROUND_UP(vs
->shader
->output_size
, 4);
1071 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_6
, 1);
1072 tu_cs_emit(cs
, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size
));
1074 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_UNKNOWN_9B07
, 1);
1077 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_UNKNOWN_A871
, 1);
1078 tu_cs_emit(cs
, vs
->shader
->output_size
);
1081 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_PRIMITIVE_CNTL
, 1);
1082 tu_cs_emit(cs
, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage
.cnt
));
1084 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_1
, 1);
1085 tu_cs_emit(cs
, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage
.max_loc
) |
1086 (last_shader
->writes_psize
? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE
: 0));
1090 tu6_vpc_varying_mode(const struct ir3_shader_variant
*fs
,
1092 uint8_t *interp_mode
,
1093 uint8_t *ps_repl_mode
)
1107 PS_REPL_ONE_MINUS_T
= 3,
1110 const uint32_t compmask
= fs
->inputs
[index
].compmask
;
1112 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
1113 * fourth component occupy three consecutive varying slots
1118 if (fs
->inputs
[index
].slot
== VARYING_SLOT_PNTC
) {
1119 if (compmask
& 0x1) {
1120 *ps_repl_mode
|= PS_REPL_S
<< shift
;
1123 if (compmask
& 0x2) {
1124 *ps_repl_mode
|= PS_REPL_T
<< shift
;
1127 if (compmask
& 0x4) {
1128 *interp_mode
|= INTERP_ZERO
<< shift
;
1131 if (compmask
& 0x8) {
1132 *interp_mode
|= INTERP_ONE
<< 6;
1135 } else if ((fs
->inputs
[index
].interpolate
== INTERP_MODE_FLAT
) ||
1136 fs
->inputs
[index
].rasterflat
) {
1137 for (int i
= 0; i
< 4; i
++) {
1138 if (compmask
& (1 << i
)) {
1139 *interp_mode
|= INTERP_FLAT
<< shift
;
1149 tu6_emit_vpc_varying_modes(struct tu_cs
*cs
,
1150 const struct ir3_shader_variant
*fs
,
1153 uint32_t interp_modes
[8] = { 0 };
1154 uint32_t ps_repl_modes
[8] = { 0 };
1156 if (!binning_pass
) {
1158 (i
= ir3_next_varying(fs
, i
)) < (int) fs
->inputs_count
;) {
1160 /* get the mode for input i */
1161 uint8_t interp_mode
;
1162 uint8_t ps_repl_mode
;
1164 tu6_vpc_varying_mode(fs
, i
, &interp_mode
, &ps_repl_mode
);
1166 /* OR the mode into the array */
1167 const uint32_t inloc
= fs
->inputs
[i
].inloc
* 2;
1168 uint32_t n
= inloc
/ 32;
1169 uint32_t shift
= inloc
% 32;
1170 interp_modes
[n
] |= interp_mode
<< shift
;
1171 ps_repl_modes
[n
] |= ps_repl_mode
<< shift
;
1172 if (shift
+ bits
> 32) {
1176 interp_modes
[n
] |= interp_mode
>> shift
;
1177 ps_repl_modes
[n
] |= ps_repl_mode
>> shift
;
1182 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
1183 tu_cs_emit_array(cs
, interp_modes
, 8);
1185 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
1186 tu_cs_emit_array(cs
, ps_repl_modes
, 8);
1190 tu6_emit_fs_inputs(struct tu_cs
*cs
, const struct ir3_shader_variant
*fs
)
1192 uint32_t face_regid
, coord_regid
, zwcoord_regid
, samp_id_regid
;
1193 uint32_t ij_pix_regid
, ij_samp_regid
, ij_cent_regid
, ij_size_regid
;
1194 uint32_t smask_in_regid
;
1196 bool sample_shading
= fs
->per_samp
; /* TODO | key->sample_shading; */
1197 bool enable_varyings
= fs
->total_in
> 0;
1199 samp_id_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_SAMPLE_ID
);
1200 smask_in_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_SAMPLE_MASK_IN
);
1201 face_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_FRONT_FACE
);
1202 coord_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_FRAG_COORD
);
1203 zwcoord_regid
= VALIDREG(coord_regid
) ? coord_regid
+ 2 : regid(63, 0);
1204 ij_pix_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
);
1205 ij_samp_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE
);
1206 ij_cent_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID
);
1207 ij_size_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE
);
1209 if (fs
->num_sampler_prefetch
> 0) {
1210 assert(VALIDREG(ij_pix_regid
));
1211 /* also, it seems like ij_pix is *required* to be r0.x */
1212 assert(ij_pix_regid
== regid(0, 0));
1215 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_PREFETCH_CNTL
, 1 + fs
->num_sampler_prefetch
);
1216 tu_cs_emit(cs
, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs
->num_sampler_prefetch
) |
1217 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
1219 for (int i
= 0; i
< fs
->num_sampler_prefetch
; i
++) {
1220 const struct ir3_sampler_prefetch
*prefetch
= &fs
->sampler_prefetch
[i
];
1221 tu_cs_emit(cs
, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch
->src
) |
1222 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch
->samp_id
) |
1223 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch
->tex_id
) |
1224 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch
->dst
) |
1225 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch
->wrmask
) |
1226 COND(prefetch
->half_precision
, A6XX_SP_FS_PREFETCH_CMD_HALF
) |
1227 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch
->cmd
));
1230 if (fs
->num_sampler_prefetch
> 0) {
1231 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(0), fs
->num_sampler_prefetch
);
1232 for (int i
= 0; i
< fs
->num_sampler_prefetch
; i
++) {
1233 const struct ir3_sampler_prefetch
*prefetch
= &fs
->sampler_prefetch
[i
];
1235 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(prefetch
->samp_bindless_id
) |
1236 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(prefetch
->tex_bindless_id
));
1240 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_CONTROL_1_REG
, 5);
1241 tu_cs_emit(cs
, 0x7);
1242 tu_cs_emit(cs
, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid
) |
1243 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid
) |
1244 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid
) |
1245 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid
));
1246 tu_cs_emit(cs
, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid
) |
1247 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid
) |
1249 tu_cs_emit(cs
, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid
) |
1250 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid
) |
1251 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid
) |
1253 tu_cs_emit(cs
, 0xfc);
1255 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_UNKNOWN_B980
, 1);
1256 tu_cs_emit(cs
, enable_varyings
? 3 : 1);
1258 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_UPDATE_CNTL
, 1);
1259 tu_cs_emit(cs
, 0xff); /* XXX */
1261 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_CNTL
, 1);
1263 CONDREG(ij_pix_regid
, A6XX_GRAS_CNTL_VARYING
) |
1264 CONDREG(ij_cent_regid
, A6XX_GRAS_CNTL_CENTROID
) |
1265 CONDREG(ij_samp_regid
, A6XX_GRAS_CNTL_PERSAMP_VARYING
) |
1266 COND(VALIDREG(ij_size_regid
) && !sample_shading
, A6XX_GRAS_CNTL_SIZE
) |
1267 COND(VALIDREG(ij_size_regid
) && sample_shading
, A6XX_GRAS_CNTL_SIZE_PERSAMP
) |
1268 COND(fs
->frag_coord
,
1269 A6XX_GRAS_CNTL_SIZE
|
1270 A6XX_GRAS_CNTL_XCOORD
|
1271 A6XX_GRAS_CNTL_YCOORD
|
1272 A6XX_GRAS_CNTL_ZCOORD
|
1273 A6XX_GRAS_CNTL_WCOORD
) |
1274 COND(fs
->frag_face
, A6XX_GRAS_CNTL_SIZE
));
1276 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_RENDER_CONTROL0
, 2);
1278 CONDREG(ij_pix_regid
, A6XX_RB_RENDER_CONTROL0_VARYING
) |
1279 CONDREG(ij_cent_regid
, A6XX_RB_RENDER_CONTROL0_CENTROID
) |
1280 CONDREG(ij_samp_regid
, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING
) |
1281 COND(enable_varyings
, A6XX_RB_RENDER_CONTROL0_UNK10
) |
1282 COND(VALIDREG(ij_size_regid
) && !sample_shading
, A6XX_RB_RENDER_CONTROL0_SIZE
) |
1283 COND(VALIDREG(ij_size_regid
) && sample_shading
, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP
) |
1284 COND(fs
->frag_coord
,
1285 A6XX_RB_RENDER_CONTROL0_SIZE
|
1286 A6XX_RB_RENDER_CONTROL0_XCOORD
|
1287 A6XX_RB_RENDER_CONTROL0_YCOORD
|
1288 A6XX_RB_RENDER_CONTROL0_ZCOORD
|
1289 A6XX_RB_RENDER_CONTROL0_WCOORD
) |
1290 COND(fs
->frag_face
, A6XX_RB_RENDER_CONTROL0_SIZE
));
1292 CONDREG(smask_in_regid
, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK
) |
1293 CONDREG(samp_id_regid
, A6XX_RB_RENDER_CONTROL1_SAMPLEID
) |
1294 CONDREG(ij_size_regid
, A6XX_RB_RENDER_CONTROL1_SIZE
) |
1295 COND(fs
->frag_face
, A6XX_RB_RENDER_CONTROL1_FACENESS
));
1297 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_SAMPLE_CNTL
, 1);
1298 tu_cs_emit(cs
, COND(sample_shading
, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE
));
1300 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_UNKNOWN_8101
, 1);
1301 tu_cs_emit(cs
, COND(sample_shading
, 0x6)); // XXX
1303 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SAMPLE_CNTL
, 1);
1304 tu_cs_emit(cs
, COND(sample_shading
, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE
));
1308 tu6_emit_fs_outputs(struct tu_cs
*cs
,
1309 const struct ir3_shader_variant
*fs
,
1312 uint32_t smask_regid
, posz_regid
;
1314 posz_regid
= ir3_find_output_regid(fs
, FRAG_RESULT_DEPTH
);
1315 smask_regid
= ir3_find_output_regid(fs
, FRAG_RESULT_SAMPLE_MASK
);
1317 uint32_t fragdata_regid
[8];
1318 if (fs
->color0_mrt
) {
1319 fragdata_regid
[0] = ir3_find_output_regid(fs
, FRAG_RESULT_COLOR
);
1320 for (uint32_t i
= 1; i
< ARRAY_SIZE(fragdata_regid
); i
++)
1321 fragdata_regid
[i
] = fragdata_regid
[0];
1323 for (uint32_t i
= 0; i
< ARRAY_SIZE(fragdata_regid
); i
++)
1324 fragdata_regid
[i
] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA0
+ i
);
1327 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_OUTPUT_CNTL0
, 2);
1328 tu_cs_emit(cs
, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid
) |
1329 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid
) |
1331 tu_cs_emit(cs
, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count
));
1333 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
1334 for (uint32_t i
= 0; i
< ARRAY_SIZE(fragdata_regid
); i
++) {
1335 // TODO we could have a mix of half and full precision outputs,
1336 // we really need to figure out half-precision from IR3_REG_HALF
1337 tu_cs_emit(cs
, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid
[i
]) |
1338 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION
: 0));
1341 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_FS_OUTPUT_CNTL0
, 2);
1342 tu_cs_emit(cs
, COND(fs
->writes_pos
, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z
) |
1343 COND(fs
->writes_smask
, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK
));
1344 tu_cs_emit(cs
, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count
));
1346 uint32_t gras_su_depth_plane_cntl
= 0;
1347 uint32_t rb_depth_plane_cntl
= 0;
1348 if (fs
->no_earlyz
|| fs
->writes_pos
) {
1349 gras_su_depth_plane_cntl
|= A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
;
1350 rb_depth_plane_cntl
|= A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
;
1353 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL
, 1);
1354 tu_cs_emit(cs
, gras_su_depth_plane_cntl
);
1356 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_PLANE_CNTL
, 1);
1357 tu_cs_emit(cs
, rb_depth_plane_cntl
);
1361 tu6_emit_shader_object(struct tu_cs
*cs
,
1362 gl_shader_stage stage
,
1363 const struct ir3_shader_variant
*variant
,
1364 const struct tu_bo
*binary_bo
,
1365 uint32_t binary_offset
)
1369 enum a6xx_state_block sb
;
1371 case MESA_SHADER_VERTEX
:
1372 reg
= REG_A6XX_SP_VS_OBJ_START_LO
;
1373 opcode
= CP_LOAD_STATE6_GEOM
;
1376 case MESA_SHADER_TESS_CTRL
:
1377 reg
= REG_A6XX_SP_HS_OBJ_START_LO
;
1378 opcode
= CP_LOAD_STATE6_GEOM
;
1381 case MESA_SHADER_TESS_EVAL
:
1382 reg
= REG_A6XX_SP_DS_OBJ_START_LO
;
1383 opcode
= CP_LOAD_STATE6_GEOM
;
1386 case MESA_SHADER_GEOMETRY
:
1387 reg
= REG_A6XX_SP_GS_OBJ_START_LO
;
1388 opcode
= CP_LOAD_STATE6_GEOM
;
1391 case MESA_SHADER_FRAGMENT
:
1392 reg
= REG_A6XX_SP_FS_OBJ_START_LO
;
1393 opcode
= CP_LOAD_STATE6_FRAG
;
1396 case MESA_SHADER_COMPUTE
:
1397 reg
= REG_A6XX_SP_CS_OBJ_START_LO
;
1398 opcode
= CP_LOAD_STATE6_FRAG
;
1402 unreachable("invalid gl_shader_stage");
1403 opcode
= CP_LOAD_STATE6_GEOM
;
1408 if (!variant
->instrlen
) {
1409 tu_cs_emit_pkt4(cs
, reg
, 2);
1410 tu_cs_emit_qw(cs
, 0);
1414 assert(variant
->type
== stage
);
1416 const uint64_t binary_iova
= binary_bo
->iova
+ binary_offset
;
1417 assert((binary_iova
& 0xf) == 0);
1418 /* note: it looks like HW might try to read a few instructions beyond the instrlen size
1419 * of the shader. this could be a potential source of problems at some point
1420 * possibly this doesn't happen if shader iova is aligned enough (to 4k for example)
1423 tu_cs_emit_pkt4(cs
, reg
, 2);
1424 tu_cs_emit_qw(cs
, binary_iova
);
1426 /* always indirect */
1427 const bool indirect
= true;
1429 tu_cs_emit_pkt7(cs
, opcode
, 3);
1430 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(0) |
1431 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER
) |
1432 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
1433 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
1434 CP_LOAD_STATE6_0_NUM_UNIT(variant
->instrlen
));
1435 tu_cs_emit_qw(cs
, binary_iova
);
1437 const void *binary
= binary_bo
->map
+ binary_offset
;
1439 tu_cs_emit_pkt7(cs
, opcode
, 3 + variant
->info
.sizedwords
);
1440 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(0) |
1441 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER
) |
1442 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
1443 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
1444 CP_LOAD_STATE6_0_NUM_UNIT(variant
->instrlen
));
1445 tu_cs_emit_qw(cs
, 0);
1446 tu_cs_emit_array(cs
, binary
, variant
->info
.sizedwords
);
1451 tu6_emit_immediates(struct tu_cs
*cs
, const struct ir3_shader_variant
*v
,
1452 uint32_t opcode
, enum a6xx_state_block block
)
1458 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
1459 uint32_t base
= const_state
->offsets
.immediate
;
1460 int size
= const_state
->immediates_count
;
1462 /* truncate size to avoid writing constants that shader
1465 size
= MIN2(size
+ base
, v
->constlen
) - base
;
1470 tu_cs_emit_pkt7(cs
, opcode
, 3 + size
* 4);
1471 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(base
) |
1472 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
1473 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
1474 CP_LOAD_STATE6_0_STATE_BLOCK(block
) |
1475 CP_LOAD_STATE6_0_NUM_UNIT(size
));
1476 tu_cs_emit(cs
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
1477 tu_cs_emit(cs
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
1479 for (unsigned i
= 0; i
< size
; i
++) {
1480 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[0]);
1481 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[1]);
1482 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[2]);
1483 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[3]);
1488 tu6_emit_geometry_consts(struct tu_cs
*cs
,
1489 const struct ir3_shader_variant
*vs
,
1490 const struct ir3_shader_variant
*gs
) {
1491 unsigned num_vertices
= gs
->shader
->nir
->info
.gs
.vertices_in
;
1493 uint32_t params
[4] = {
1494 vs
->shader
->output_size
* num_vertices
* 4, /* primitive stride */
1495 vs
->shader
->output_size
* 4, /* vertex stride */
1499 uint32_t vs_base
= vs
->shader
->const_state
.offsets
.primitive_param
;
1500 tu6_emit_const(cs
, CP_LOAD_STATE6_GEOM
, vs_base
, SB6_VS_SHADER
, 0,
1501 ARRAY_SIZE(params
), params
);
1503 uint32_t gs_base
= gs
->shader
->const_state
.offsets
.primitive_param
;
1504 tu6_emit_const(cs
, CP_LOAD_STATE6_GEOM
, gs_base
, SB6_GS_SHADER
, 0,
1505 ARRAY_SIZE(params
), params
);
1509 tu6_emit_program(struct tu_cs
*cs
,
1510 const struct tu_pipeline_builder
*builder
,
1511 const struct tu_bo
*binary_bo
,
1513 struct tu_streamout_state
*tf
)
1515 static const struct ir3_shader_variant dummy_variant
= {
1516 .type
= MESA_SHADER_NONE
1518 assert(builder
->shaders
[MESA_SHADER_VERTEX
]);
1519 const struct ir3_shader_variant
*vs
=
1520 &builder
->shaders
[MESA_SHADER_VERTEX
]->variants
[0];
1521 const struct ir3_shader_variant
*hs
=
1522 builder
->shaders
[MESA_SHADER_TESS_CTRL
]
1523 ? &builder
->shaders
[MESA_SHADER_TESS_CTRL
]->variants
[0]
1525 const struct ir3_shader_variant
*ds
=
1526 builder
->shaders
[MESA_SHADER_TESS_EVAL
]
1527 ? &builder
->shaders
[MESA_SHADER_TESS_EVAL
]->variants
[0]
1529 const struct ir3_shader_variant
*gs
=
1530 builder
->shaders
[MESA_SHADER_GEOMETRY
]
1531 ? &builder
->shaders
[MESA_SHADER_GEOMETRY
]->variants
[0]
1533 const struct ir3_shader_variant
*fs
=
1534 builder
->shaders
[MESA_SHADER_FRAGMENT
]
1535 ? &builder
->shaders
[MESA_SHADER_FRAGMENT
]->variants
[0]
1537 bool has_gs
= gs
->type
!= MESA_SHADER_NONE
;
1540 /* if we have streamout, use full VS in binning pass, as the
1541 * binning pass VS will have outputs on other than position/psize
1544 if (vs
->shader
->stream_output
.num_outputs
== 0)
1545 vs
= &builder
->shaders
[MESA_SHADER_VERTEX
]->variants
[1];
1546 fs
= &dummy_variant
;
1549 tu6_emit_vs_config(cs
, builder
->shaders
[MESA_SHADER_VERTEX
], vs
);
1550 tu6_emit_hs_config(cs
, builder
->shaders
[MESA_SHADER_TESS_CTRL
], hs
);
1551 tu6_emit_ds_config(cs
, builder
->shaders
[MESA_SHADER_TESS_EVAL
], ds
);
1552 tu6_emit_gs_config(cs
, builder
->shaders
[MESA_SHADER_GEOMETRY
], gs
);
1553 tu6_emit_fs_config(cs
, builder
->shaders
[MESA_SHADER_FRAGMENT
], fs
);
1555 tu6_emit_vs_system_values(cs
, vs
, gs
);
1556 tu6_emit_vpc(cs
, vs
, gs
, fs
, binning_pass
, tf
);
1557 tu6_emit_vpc_varying_modes(cs
, fs
, binning_pass
);
1558 tu6_emit_fs_inputs(cs
, fs
);
1559 tu6_emit_fs_outputs(cs
, fs
, builder
->color_attachment_count
);
1561 tu6_emit_shader_object(cs
, MESA_SHADER_VERTEX
, vs
, binary_bo
,
1562 binning_pass
? builder
->binning_vs_offset
: builder
->shader_offsets
[MESA_SHADER_VERTEX
]);
1564 tu6_emit_shader_object(cs
, MESA_SHADER_GEOMETRY
, gs
, binary_bo
,
1565 builder
->shader_offsets
[MESA_SHADER_GEOMETRY
]);
1566 tu6_emit_shader_object(cs
, MESA_SHADER_FRAGMENT
, fs
, binary_bo
,
1567 builder
->shader_offsets
[MESA_SHADER_FRAGMENT
]);
1569 tu6_emit_immediates(cs
, vs
, CP_LOAD_STATE6_GEOM
, SB6_VS_SHADER
);
1571 tu6_emit_immediates(cs
, gs
, CP_LOAD_STATE6_GEOM
, SB6_GS_SHADER
);
1572 tu6_emit_geometry_consts(cs
, vs
, gs
);
1575 tu6_emit_immediates(cs
, fs
, CP_LOAD_STATE6_FRAG
, SB6_FS_SHADER
);
1579 tu6_emit_vertex_input(struct tu_cs
*cs
,
1580 const struct ir3_shader_variant
*vs
,
1581 const VkPipelineVertexInputStateCreateInfo
*info
,
1582 uint8_t bindings
[MAX_VERTEX_ATTRIBS
],
1585 uint32_t vfd_fetch_idx
= 0;
1586 uint32_t vfd_decode_idx
= 0;
1587 uint32_t binding_instanced
= 0; /* bitmask of instanced bindings */
1589 for (uint32_t i
= 0; i
< info
->vertexBindingDescriptionCount
; i
++) {
1590 const VkVertexInputBindingDescription
*binding
=
1591 &info
->pVertexBindingDescriptions
[i
];
1594 A6XX_VFD_FETCH_STRIDE(vfd_fetch_idx
, binding
->stride
));
1596 if (binding
->inputRate
== VK_VERTEX_INPUT_RATE_INSTANCE
)
1597 binding_instanced
|= 1 << binding
->binding
;
1599 bindings
[vfd_fetch_idx
] = binding
->binding
;
1603 /* TODO: emit all VFD_DECODE/VFD_DEST_CNTL in same (two) pkt4 */
1605 for (uint32_t i
= 0; i
< info
->vertexAttributeDescriptionCount
; i
++) {
1606 const VkVertexInputAttributeDescription
*attr
=
1607 &info
->pVertexAttributeDescriptions
[i
];
1608 uint32_t binding_idx
, input_idx
;
1610 for (binding_idx
= 0; binding_idx
< vfd_fetch_idx
; binding_idx
++) {
1611 if (bindings
[binding_idx
] == attr
->binding
)
1614 assert(binding_idx
< vfd_fetch_idx
);
1616 for (input_idx
= 0; input_idx
< vs
->inputs_count
; input_idx
++) {
1617 if ((vs
->inputs
[input_idx
].slot
- VERT_ATTRIB_GENERIC0
) == attr
->location
)
1621 /* attribute not used, skip it */
1622 if (input_idx
== vs
->inputs_count
)
1625 const struct tu_native_format format
= tu6_format_vtx(attr
->format
);
1627 A6XX_VFD_DECODE_INSTR(vfd_decode_idx
,
1629 .offset
= attr
->offset
,
1630 .instanced
= binding_instanced
& (1 << attr
->binding
),
1631 .format
= format
.fmt
,
1632 .swap
= format
.swap
,
1634 ._float
= !vk_format_is_int(attr
->format
)),
1635 A6XX_VFD_DECODE_STEP_RATE(vfd_decode_idx
, 1));
1638 A6XX_VFD_DEST_CNTL_INSTR(vfd_decode_idx
,
1639 .writemask
= vs
->inputs
[input_idx
].compmask
,
1640 .regid
= vs
->inputs
[input_idx
].regid
));
1647 .fetch_cnt
= vfd_fetch_idx
,
1648 .decode_cnt
= vfd_decode_idx
));
1650 *count
= vfd_fetch_idx
;
1654 tu6_guardband_adj(uint32_t v
)
1657 return (uint32_t)(511.0 - 65.0 * (log2(v
) - 8.0));
1663 tu6_emit_viewport(struct tu_cs
*cs
, const VkViewport
*viewport
)
1667 scales
[0] = viewport
->width
/ 2.0f
;
1668 scales
[1] = viewport
->height
/ 2.0f
;
1669 scales
[2] = viewport
->maxDepth
- viewport
->minDepth
;
1670 offsets
[0] = viewport
->x
+ scales
[0];
1671 offsets
[1] = viewport
->y
+ scales
[1];
1672 offsets
[2] = viewport
->minDepth
;
1676 min
.x
= (int32_t) viewport
->x
;
1677 max
.x
= (int32_t) ceilf(viewport
->x
+ viewport
->width
);
1678 if (viewport
->height
>= 0.0f
) {
1679 min
.y
= (int32_t) viewport
->y
;
1680 max
.y
= (int32_t) ceilf(viewport
->y
+ viewport
->height
);
1682 min
.y
= (int32_t)(viewport
->y
+ viewport
->height
);
1683 max
.y
= (int32_t) ceilf(viewport
->y
);
1685 /* the spec allows viewport->height to be 0.0f */
1688 assert(min
.x
>= 0 && min
.x
< max
.x
);
1689 assert(min
.y
>= 0 && min
.y
< max
.y
);
1691 VkExtent2D guardband_adj
;
1692 guardband_adj
.width
= tu6_guardband_adj(max
.x
- min
.x
);
1693 guardband_adj
.height
= tu6_guardband_adj(max
.y
- min
.y
);
1695 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0
, 6);
1696 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_XOFFSET_0(offsets
[0]).value
);
1697 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_XSCALE_0(scales
[0]).value
);
1698 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_YOFFSET_0(offsets
[1]).value
);
1699 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_YSCALE_0(scales
[1]).value
);
1700 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_ZOFFSET_0(offsets
[2]).value
);
1701 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_ZSCALE_0(scales
[2]).value
);
1703 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0
, 2);
1704 tu_cs_emit(cs
, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(min
.x
) |
1705 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(min
.y
));
1706 tu_cs_emit(cs
, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(max
.x
- 1) |
1707 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(max
.y
- 1));
1709 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ
, 1);
1711 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj
.width
) |
1712 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj
.height
));
1714 float z_clamp_min
= MIN2(viewport
->minDepth
, viewport
->maxDepth
);
1715 float z_clamp_max
= MAX2(viewport
->minDepth
, viewport
->maxDepth
);
1718 A6XX_GRAS_CL_Z_CLAMP_MIN(z_clamp_min
),
1719 A6XX_GRAS_CL_Z_CLAMP_MAX(z_clamp_max
));
1722 A6XX_RB_Z_CLAMP_MIN(z_clamp_min
),
1723 A6XX_RB_Z_CLAMP_MAX(z_clamp_max
));
1727 tu6_emit_scissor(struct tu_cs
*cs
, const VkRect2D
*scissor
)
1729 const VkOffset2D min
= scissor
->offset
;
1730 const VkOffset2D max
= {
1731 scissor
->offset
.x
+ scissor
->extent
.width
,
1732 scissor
->offset
.y
+ scissor
->extent
.height
,
1735 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0
, 2);
1736 tu_cs_emit(cs
, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(min
.x
) |
1737 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(min
.y
));
1738 tu_cs_emit(cs
, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(max
.x
- 1) |
1739 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(max
.y
- 1));
1743 tu6_emit_sample_locations(struct tu_cs
*cs
, const VkSampleLocationsInfoEXT
*samp_loc
)
1746 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SAMPLE_CONFIG
, 1);
1749 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_SAMPLE_CONFIG
, 1);
1752 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_TP_SAMPLE_CONFIG
, 1);
1757 assert(samp_loc
->sampleLocationsPerPixel
== samp_loc
->sampleLocationsCount
);
1758 assert(samp_loc
->sampleLocationGridSize
.width
== 1);
1759 assert(samp_loc
->sampleLocationGridSize
.height
== 1);
1761 uint32_t sample_config
=
1762 A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE
;
1763 uint32_t sample_locations
= 0;
1764 for (uint32_t i
= 0; i
< samp_loc
->sampleLocationsCount
; i
++) {
1766 (A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(samp_loc
->pSampleLocations
[i
].x
) |
1767 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(samp_loc
->pSampleLocations
[i
].y
)) << i
*8;
1770 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SAMPLE_CONFIG
, 2);
1771 tu_cs_emit(cs
, sample_config
);
1772 tu_cs_emit(cs
, sample_locations
);
1774 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_SAMPLE_CONFIG
, 2);
1775 tu_cs_emit(cs
, sample_config
);
1776 tu_cs_emit(cs
, sample_locations
);
1778 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_TP_SAMPLE_CONFIG
, 2);
1779 tu_cs_emit(cs
, sample_config
);
1780 tu_cs_emit(cs
, sample_locations
);
1784 tu6_emit_gras_unknowns(struct tu_cs
*cs
)
1786 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_UNKNOWN_8001
, 1);
1787 tu_cs_emit(cs
, 0x0);
1791 tu6_emit_point_size(struct tu_cs
*cs
)
1793 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_POINT_MINMAX
, 2);
1794 tu_cs_emit(cs
, A6XX_GRAS_SU_POINT_MINMAX_MIN(1.0f
/ 16.0f
) |
1795 A6XX_GRAS_SU_POINT_MINMAX_MAX(4092.0f
));
1796 tu_cs_emit(cs
, A6XX_GRAS_SU_POINT_SIZE(1.0f
).value
);
1800 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo
*rast_info
,
1801 VkSampleCountFlagBits samples
)
1803 uint32_t gras_su_cntl
= 0;
1805 if (rast_info
->cullMode
& VK_CULL_MODE_FRONT_BIT
)
1806 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_CULL_FRONT
;
1807 if (rast_info
->cullMode
& VK_CULL_MODE_BACK_BIT
)
1808 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_CULL_BACK
;
1810 if (rast_info
->frontFace
== VK_FRONT_FACE_CLOCKWISE
)
1811 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_FRONT_CW
;
1813 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1815 if (rast_info
->depthBiasEnable
)
1816 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_POLY_OFFSET
;
1818 if (samples
> VK_SAMPLE_COUNT_1_BIT
)
1819 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_MSAA_ENABLE
;
1821 return gras_su_cntl
;
1825 tu6_emit_gras_su_cntl(struct tu_cs
*cs
,
1826 uint32_t gras_su_cntl
,
1829 assert((gras_su_cntl
& A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK
) == 0);
1830 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(line_width
/ 2.0f
);
1832 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_CNTL
, 1);
1833 tu_cs_emit(cs
, gras_su_cntl
);
1837 tu6_emit_depth_bias(struct tu_cs
*cs
,
1838 float constant_factor
,
1842 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE
, 3);
1843 tu_cs_emit(cs
, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor
).value
);
1844 tu_cs_emit(cs
, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor
).value
);
1845 tu_cs_emit(cs
, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp
).value
);
1849 tu6_emit_alpha_control_disable(struct tu_cs
*cs
)
1851 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_ALPHA_CONTROL
, 1);
1856 tu6_emit_depth_control(struct tu_cs
*cs
,
1857 const VkPipelineDepthStencilStateCreateInfo
*ds_info
,
1858 const VkPipelineRasterizationStateCreateInfo
*rast_info
)
1860 assert(!ds_info
->depthBoundsTestEnable
);
1862 uint32_t rb_depth_cntl
= 0;
1863 if (ds_info
->depthTestEnable
) {
1865 A6XX_RB_DEPTH_CNTL_Z_ENABLE
|
1866 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info
->depthCompareOp
)) |
1867 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE
;
1869 if (rast_info
->depthClampEnable
)
1870 rb_depth_cntl
|= A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE
;
1872 if (ds_info
->depthWriteEnable
)
1873 rb_depth_cntl
|= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE
;
1876 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_CNTL
, 1);
1877 tu_cs_emit(cs
, rb_depth_cntl
);
1881 tu6_emit_stencil_control(struct tu_cs
*cs
,
1882 const VkPipelineDepthStencilStateCreateInfo
*ds_info
)
1884 uint32_t rb_stencil_control
= 0;
1885 if (ds_info
->stencilTestEnable
) {
1886 const VkStencilOpState
*front
= &ds_info
->front
;
1887 const VkStencilOpState
*back
= &ds_info
->back
;
1888 rb_stencil_control
|=
1889 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE
|
1890 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF
|
1891 A6XX_RB_STENCIL_CONTROL_STENCIL_READ
|
1892 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front
->compareOp
)) |
1893 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front
->failOp
)) |
1894 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front
->passOp
)) |
1895 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front
->depthFailOp
)) |
1896 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back
->compareOp
)) |
1897 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back
->failOp
)) |
1898 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back
->passOp
)) |
1899 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back
->depthFailOp
));
1902 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCIL_CONTROL
, 1);
1903 tu_cs_emit(cs
, rb_stencil_control
);
1907 tu6_emit_stencil_compare_mask(struct tu_cs
*cs
, uint32_t front
, uint32_t back
)
1909 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCILMASK
, 1);
1911 cs
, A6XX_RB_STENCILMASK_MASK(front
) | A6XX_RB_STENCILMASK_BFMASK(back
));
1915 tu6_emit_stencil_write_mask(struct tu_cs
*cs
, uint32_t front
, uint32_t back
)
1917 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCILWRMASK
, 1);
1918 tu_cs_emit(cs
, A6XX_RB_STENCILWRMASK_WRMASK(front
) |
1919 A6XX_RB_STENCILWRMASK_BFWRMASK(back
));
1923 tu6_emit_stencil_reference(struct tu_cs
*cs
, uint32_t front
, uint32_t back
)
1925 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCILREF
, 1);
1927 A6XX_RB_STENCILREF_REF(front
) | A6XX_RB_STENCILREF_BFREF(back
));
1931 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState
*att
,
1934 const enum a3xx_rb_blend_opcode color_op
= tu6_blend_op(att
->colorBlendOp
);
1935 const enum adreno_rb_blend_factor src_color_factor
= tu6_blend_factor(
1936 has_alpha
? att
->srcColorBlendFactor
1937 : tu_blend_factor_no_dst_alpha(att
->srcColorBlendFactor
));
1938 const enum adreno_rb_blend_factor dst_color_factor
= tu6_blend_factor(
1939 has_alpha
? att
->dstColorBlendFactor
1940 : tu_blend_factor_no_dst_alpha(att
->dstColorBlendFactor
));
1941 const enum a3xx_rb_blend_opcode alpha_op
= tu6_blend_op(att
->alphaBlendOp
);
1942 const enum adreno_rb_blend_factor src_alpha_factor
=
1943 tu6_blend_factor(att
->srcAlphaBlendFactor
);
1944 const enum adreno_rb_blend_factor dst_alpha_factor
=
1945 tu6_blend_factor(att
->dstAlphaBlendFactor
);
1947 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor
) |
1948 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op
) |
1949 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor
) |
1950 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor
) |
1951 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op
) |
1952 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor
);
1956 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState
*att
,
1957 uint32_t rb_mrt_control_rop
,
1961 uint32_t rb_mrt_control
=
1962 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att
->colorWriteMask
);
1964 /* ignore blending and logic op for integer attachments */
1966 rb_mrt_control
|= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY
);
1967 return rb_mrt_control
;
1970 rb_mrt_control
|= rb_mrt_control_rop
;
1972 if (att
->blendEnable
) {
1973 rb_mrt_control
|= A6XX_RB_MRT_CONTROL_BLEND
;
1976 rb_mrt_control
|= A6XX_RB_MRT_CONTROL_BLEND2
;
1979 return rb_mrt_control
;
1983 tu6_emit_rb_mrt_controls(struct tu_cs
*cs
,
1984 const VkPipelineColorBlendStateCreateInfo
*blend_info
,
1985 const VkFormat attachment_formats
[MAX_RTS
],
1986 uint32_t *blend_enable_mask
)
1988 *blend_enable_mask
= 0;
1990 bool rop_reads_dst
= false;
1991 uint32_t rb_mrt_control_rop
= 0;
1992 if (blend_info
->logicOpEnable
) {
1993 rop_reads_dst
= tu_logic_op_reads_dst(blend_info
->logicOp
);
1994 rb_mrt_control_rop
=
1995 A6XX_RB_MRT_CONTROL_ROP_ENABLE
|
1996 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info
->logicOp
));
1999 for (uint32_t i
= 0; i
< blend_info
->attachmentCount
; i
++) {
2000 const VkPipelineColorBlendAttachmentState
*att
=
2001 &blend_info
->pAttachments
[i
];
2002 const VkFormat format
= attachment_formats
[i
];
2004 uint32_t rb_mrt_control
= 0;
2005 uint32_t rb_mrt_blend_control
= 0;
2006 if (format
!= VK_FORMAT_UNDEFINED
) {
2007 const bool is_int
= vk_format_is_int(format
);
2008 const bool has_alpha
= vk_format_has_alpha(format
);
2011 tu6_rb_mrt_control(att
, rb_mrt_control_rop
, is_int
, has_alpha
);
2012 rb_mrt_blend_control
= tu6_rb_mrt_blend_control(att
, has_alpha
);
2014 if (att
->blendEnable
|| rop_reads_dst
)
2015 *blend_enable_mask
|= 1 << i
;
2018 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_CONTROL(i
), 2);
2019 tu_cs_emit(cs
, rb_mrt_control
);
2020 tu_cs_emit(cs
, rb_mrt_blend_control
);
2025 tu6_emit_blend_control(struct tu_cs
*cs
,
2026 uint32_t blend_enable_mask
,
2027 const VkPipelineMultisampleStateCreateInfo
*msaa_info
)
2029 assert(!msaa_info
->alphaToOneEnable
);
2031 uint32_t sp_blend_cntl
= A6XX_SP_BLEND_CNTL_UNK8
;
2032 if (blend_enable_mask
)
2033 sp_blend_cntl
|= A6XX_SP_BLEND_CNTL_ENABLED
;
2034 if (msaa_info
->alphaToCoverageEnable
)
2035 sp_blend_cntl
|= A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE
;
2037 const uint32_t sample_mask
=
2038 msaa_info
->pSampleMask
? *msaa_info
->pSampleMask
2039 : ((1 << msaa_info
->rasterizationSamples
) - 1);
2041 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
2042 uint32_t rb_blend_cntl
=
2043 A6XX_RB_BLEND_CNTL_ENABLE_BLEND(blend_enable_mask
) |
2044 A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND
|
2045 A6XX_RB_BLEND_CNTL_SAMPLE_MASK(sample_mask
);
2046 if (msaa_info
->alphaToCoverageEnable
)
2047 rb_blend_cntl
|= A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE
;
2049 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_BLEND_CNTL
, 1);
2050 tu_cs_emit(cs
, sp_blend_cntl
);
2052 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_BLEND_CNTL
, 1);
2053 tu_cs_emit(cs
, rb_blend_cntl
);
2057 tu6_emit_blend_constants(struct tu_cs
*cs
, const float constants
[4])
2059 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_BLEND_RED_F32
, 4);
2060 tu_cs_emit_array(cs
, (const uint32_t *) constants
, 4);
2064 tu_pipeline_create(struct tu_device
*dev
,
2065 struct tu_pipeline_layout
*layout
,
2067 const VkAllocationCallbacks
*pAllocator
,
2068 struct tu_pipeline
**out_pipeline
)
2070 struct tu_pipeline
*pipeline
=
2071 vk_zalloc2(&dev
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
2072 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2074 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2076 tu_cs_init(&pipeline
->cs
, dev
, TU_CS_MODE_SUB_STREAM
, 2048);
2078 /* Reserve the space now such that tu_cs_begin_sub_stream never fails. Note
2079 * that LOAD_STATE can potentially take up a large amount of space so we
2080 * calculate its size explicitly.
2082 unsigned load_state_size
= tu6_load_state_size(layout
, compute
);
2083 VkResult result
= tu_cs_reserve_space(&pipeline
->cs
, 2048 + load_state_size
);
2084 if (result
!= VK_SUCCESS
) {
2085 vk_free2(&dev
->alloc
, pAllocator
, pipeline
);
2089 *out_pipeline
= pipeline
;
2095 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder
*builder
)
2097 const VkPipelineShaderStageCreateInfo
*stage_infos
[MESA_SHADER_STAGES
] = {
2100 for (uint32_t i
= 0; i
< builder
->create_info
->stageCount
; i
++) {
2101 gl_shader_stage stage
=
2102 tu_shader_stage(builder
->create_info
->pStages
[i
].stage
);
2103 stage_infos
[stage
] = &builder
->create_info
->pStages
[i
];
2106 struct tu_shader_compile_options options
;
2107 tu_shader_compile_options_init(&options
, builder
->create_info
);
2109 /* compile shaders in reverse order */
2110 struct tu_shader
*next_stage_shader
= NULL
;
2111 for (gl_shader_stage stage
= MESA_SHADER_STAGES
- 1;
2112 stage
> MESA_SHADER_NONE
; stage
--) {
2113 const VkPipelineShaderStageCreateInfo
*stage_info
= stage_infos
[stage
];
2117 struct tu_shader
*shader
=
2118 tu_shader_create(builder
->device
, stage
, stage_info
, builder
->layout
,
2121 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2124 tu_shader_compile(builder
->device
, shader
, next_stage_shader
,
2125 &options
, builder
->alloc
);
2126 if (result
!= VK_SUCCESS
)
2129 builder
->shaders
[stage
] = shader
;
2130 builder
->shader_offsets
[stage
] = builder
->shader_total_size
;
2131 builder
->shader_total_size
+=
2132 sizeof(uint32_t) * shader
->variants
[0].info
.sizedwords
;
2134 next_stage_shader
= shader
;
2137 if (builder
->shaders
[MESA_SHADER_VERTEX
]->has_binning_pass
) {
2138 const struct tu_shader
*vs
= builder
->shaders
[MESA_SHADER_VERTEX
];
2139 const struct ir3_shader_variant
*variant
;
2141 if (vs
->ir3_shader
.stream_output
.num_outputs
)
2142 variant
= &vs
->variants
[0];
2144 variant
= &vs
->variants
[1];
2146 builder
->binning_vs_offset
= builder
->shader_total_size
;
2147 builder
->shader_total_size
+=
2148 sizeof(uint32_t) * variant
->info
.sizedwords
;
2155 tu_pipeline_builder_upload_shaders(struct tu_pipeline_builder
*builder
,
2156 struct tu_pipeline
*pipeline
)
2158 struct tu_bo
*bo
= &pipeline
->program
.binary_bo
;
2161 tu_bo_init_new(builder
->device
, bo
, builder
->shader_total_size
);
2162 if (result
!= VK_SUCCESS
)
2165 result
= tu_bo_map(builder
->device
, bo
);
2166 if (result
!= VK_SUCCESS
)
2169 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2170 const struct tu_shader
*shader
= builder
->shaders
[i
];
2174 memcpy(bo
->map
+ builder
->shader_offsets
[i
], shader
->binary
,
2175 sizeof(uint32_t) * shader
->variants
[0].info
.sizedwords
);
2178 if (builder
->shaders
[MESA_SHADER_VERTEX
]->has_binning_pass
) {
2179 const struct tu_shader
*vs
= builder
->shaders
[MESA_SHADER_VERTEX
];
2180 const struct ir3_shader_variant
*variant
;
2183 if (vs
->ir3_shader
.stream_output
.num_outputs
) {
2184 variant
= &vs
->variants
[0];
2187 variant
= &vs
->variants
[1];
2188 bin
= vs
->binning_binary
;
2191 memcpy(bo
->map
+ builder
->binning_vs_offset
, bin
,
2192 sizeof(uint32_t) * variant
->info
.sizedwords
);
2199 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder
*builder
,
2200 struct tu_pipeline
*pipeline
)
2202 const VkPipelineDynamicStateCreateInfo
*dynamic_info
=
2203 builder
->create_info
->pDynamicState
;
2208 for (uint32_t i
= 0; i
< dynamic_info
->dynamicStateCount
; i
++) {
2209 pipeline
->dynamic_state
.mask
|=
2210 tu_dynamic_state_bit(dynamic_info
->pDynamicStates
[i
]);
2215 tu_pipeline_set_linkage(struct tu_program_descriptor_linkage
*link
,
2216 struct tu_shader
*shader
,
2217 struct ir3_shader_variant
*v
)
2219 link
->ubo_state
= v
->shader
->ubo_state
;
2220 link
->const_state
= v
->shader
->const_state
;
2221 link
->constlen
= v
->constlen
;
2222 link
->push_consts
= shader
->push_consts
;
2226 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder
*builder
,
2227 struct tu_pipeline
*pipeline
)
2229 struct tu_cs prog_cs
;
2230 tu_cs_begin_sub_stream(&pipeline
->cs
, 512, &prog_cs
);
2231 tu6_emit_program(&prog_cs
, builder
, &pipeline
->program
.binary_bo
, false, &pipeline
->streamout
);
2232 pipeline
->program
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &prog_cs
);
2234 tu_cs_begin_sub_stream(&pipeline
->cs
, 512, &prog_cs
);
2235 tu6_emit_program(&prog_cs
, builder
, &pipeline
->program
.binary_bo
, true, &pipeline
->streamout
);
2236 pipeline
->program
.binning_state_ib
=
2237 tu_cs_end_sub_stream(&pipeline
->cs
, &prog_cs
);
2239 VkShaderStageFlags stages
= 0;
2240 for (unsigned i
= 0; i
< builder
->create_info
->stageCount
; i
++) {
2241 stages
|= builder
->create_info
->pStages
[i
].stage
;
2243 pipeline
->active_stages
= stages
;
2245 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2246 if (!builder
->shaders
[i
])
2249 tu_pipeline_set_linkage(&pipeline
->program
.link
[i
],
2250 builder
->shaders
[i
],
2251 &builder
->shaders
[i
]->variants
[0]);
2254 if (builder
->shaders
[MESA_SHADER_FRAGMENT
]) {
2255 memcpy(pipeline
->program
.input_attachment_idx
,
2256 builder
->shaders
[MESA_SHADER_FRAGMENT
]->attachment_idx
,
2257 sizeof(pipeline
->program
.input_attachment_idx
));
2262 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder
*builder
,
2263 struct tu_pipeline
*pipeline
)
2265 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
2266 builder
->create_info
->pVertexInputState
;
2267 const struct tu_shader
*vs
= builder
->shaders
[MESA_SHADER_VERTEX
];
2270 tu_cs_begin_sub_stream(&pipeline
->cs
,
2271 MAX_VERTEX_ATTRIBS
* 7 + 2, &vi_cs
);
2272 tu6_emit_vertex_input(&vi_cs
, &vs
->variants
[0], vi_info
,
2273 pipeline
->vi
.bindings
, &pipeline
->vi
.count
);
2274 pipeline
->vi
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &vi_cs
);
2276 if (vs
->has_binning_pass
) {
2277 tu_cs_begin_sub_stream(&pipeline
->cs
,
2278 MAX_VERTEX_ATTRIBS
* 7 + 2, &vi_cs
);
2279 tu6_emit_vertex_input(
2280 &vi_cs
, &vs
->variants
[1], vi_info
, pipeline
->vi
.binning_bindings
,
2281 &pipeline
->vi
.binning_count
);
2282 pipeline
->vi
.binning_state_ib
=
2283 tu_cs_end_sub_stream(&pipeline
->cs
, &vi_cs
);
2288 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder
*builder
,
2289 struct tu_pipeline
*pipeline
)
2291 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
2292 builder
->create_info
->pInputAssemblyState
;
2294 pipeline
->ia
.primtype
= tu6_primtype(ia_info
->topology
);
2295 pipeline
->ia
.primitive_restart
= ia_info
->primitiveRestartEnable
;
2299 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder
*builder
,
2300 struct tu_pipeline
*pipeline
)
2304 * pViewportState is a pointer to an instance of the
2305 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
2306 * pipeline has rasterization disabled."
2308 * We leave the relevant registers stale in that case.
2310 if (builder
->rasterizer_discard
)
2313 const VkPipelineViewportStateCreateInfo
*vp_info
=
2314 builder
->create_info
->pViewportState
;
2317 tu_cs_begin_sub_stream(&pipeline
->cs
, 21, &vp_cs
);
2319 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_VIEWPORT
)) {
2320 assert(vp_info
->viewportCount
== 1);
2321 tu6_emit_viewport(&vp_cs
, vp_info
->pViewports
);
2324 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_SCISSOR
)) {
2325 assert(vp_info
->scissorCount
== 1);
2326 tu6_emit_scissor(&vp_cs
, vp_info
->pScissors
);
2329 pipeline
->vp
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &vp_cs
);
2333 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder
*builder
,
2334 struct tu_pipeline
*pipeline
)
2336 const VkPipelineRasterizationStateCreateInfo
*rast_info
=
2337 builder
->create_info
->pRasterizationState
;
2339 assert(rast_info
->polygonMode
== VK_POLYGON_MODE_FILL
);
2341 struct tu_cs rast_cs
;
2342 tu_cs_begin_sub_stream(&pipeline
->cs
, 20, &rast_cs
);
2345 tu_cs_emit_regs(&rast_cs
,
2347 .znear_clip_disable
= rast_info
->depthClampEnable
,
2348 .zfar_clip_disable
= rast_info
->depthClampEnable
,
2349 .unk5
= rast_info
->depthClampEnable
,
2350 .zero_gb_scale_z
= 1,
2351 .vp_clip_code_ignore
= 1));
2352 /* move to hw ctx init? */
2353 tu6_emit_gras_unknowns(&rast_cs
);
2354 tu6_emit_point_size(&rast_cs
);
2356 const uint32_t gras_su_cntl
=
2357 tu6_gras_su_cntl(rast_info
, builder
->samples
);
2359 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_LINE_WIDTH
))
2360 tu6_emit_gras_su_cntl(&rast_cs
, gras_su_cntl
, rast_info
->lineWidth
);
2362 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_DEPTH_BIAS
)) {
2363 tu6_emit_depth_bias(&rast_cs
, rast_info
->depthBiasConstantFactor
,
2364 rast_info
->depthBiasClamp
,
2365 rast_info
->depthBiasSlopeFactor
);
2368 pipeline
->rast
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &rast_cs
);
2370 pipeline
->rast
.gras_su_cntl
= gras_su_cntl
;
2374 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder
*builder
,
2375 struct tu_pipeline
*pipeline
)
2379 * pDepthStencilState is a pointer to an instance of the
2380 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
2381 * the pipeline has rasterization disabled or if the subpass of the
2382 * render pass the pipeline is created against does not use a
2383 * depth/stencil attachment.
2385 * Disable both depth and stencil tests if there is no ds attachment,
2386 * Disable depth test if ds attachment is S8_UINT, since S8_UINT defines
2387 * only the separate stencil attachment
2389 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info
;
2390 const VkPipelineDepthStencilStateCreateInfo
*ds_info
=
2391 builder
->depth_attachment_format
!= VK_FORMAT_UNDEFINED
2392 ? builder
->create_info
->pDepthStencilState
2394 const VkPipelineDepthStencilStateCreateInfo
*ds_info_depth
=
2395 builder
->depth_attachment_format
!= VK_FORMAT_S8_UINT
2396 ? ds_info
: &dummy_ds_info
;
2399 tu_cs_begin_sub_stream(&pipeline
->cs
, 12, &ds_cs
);
2401 /* move to hw ctx init? */
2402 tu6_emit_alpha_control_disable(&ds_cs
);
2404 tu6_emit_depth_control(&ds_cs
, ds_info_depth
,
2405 builder
->create_info
->pRasterizationState
);
2406 tu6_emit_stencil_control(&ds_cs
, ds_info
);
2408 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_COMPARE_MASK
)) {
2409 tu6_emit_stencil_compare_mask(&ds_cs
, ds_info
->front
.compareMask
,
2410 ds_info
->back
.compareMask
);
2412 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_WRITE_MASK
)) {
2413 tu6_emit_stencil_write_mask(&ds_cs
, ds_info
->front
.writeMask
,
2414 ds_info
->back
.writeMask
);
2416 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_REFERENCE
)) {
2417 tu6_emit_stencil_reference(&ds_cs
, ds_info
->front
.reference
,
2418 ds_info
->back
.reference
);
2421 pipeline
->ds
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &ds_cs
);
2425 tu_pipeline_builder_parse_multisample_and_color_blend(
2426 struct tu_pipeline_builder
*builder
, struct tu_pipeline
*pipeline
)
2430 * pMultisampleState is a pointer to an instance of the
2431 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
2432 * has rasterization disabled.
2436 * pColorBlendState is a pointer to an instance of the
2437 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
2438 * pipeline has rasterization disabled or if the subpass of the render
2439 * pass the pipeline is created against does not use any color
2442 * We leave the relevant registers stale when rasterization is disabled.
2444 if (builder
->rasterizer_discard
)
2447 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info
;
2448 const VkPipelineMultisampleStateCreateInfo
*msaa_info
=
2449 builder
->create_info
->pMultisampleState
;
2450 const VkPipelineColorBlendStateCreateInfo
*blend_info
=
2451 builder
->use_color_attachments
? builder
->create_info
->pColorBlendState
2452 : &dummy_blend_info
;
2454 struct tu_cs blend_cs
;
2455 tu_cs_begin_sub_stream(&pipeline
->cs
, MAX_RTS
* 3 + 9, &blend_cs
);
2457 uint32_t blend_enable_mask
;
2458 tu6_emit_rb_mrt_controls(&blend_cs
, blend_info
,
2459 builder
->color_attachment_formats
,
2460 &blend_enable_mask
);
2462 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_BLEND_CONSTANTS
))
2463 tu6_emit_blend_constants(&blend_cs
, blend_info
->blendConstants
);
2465 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_SAMPLE_LOCATIONS
)) {
2466 const struct VkPipelineSampleLocationsStateCreateInfoEXT
*sample_locations
=
2467 vk_find_struct_const(msaa_info
->pNext
, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
);
2468 const VkSampleLocationsInfoEXT
*samp_loc
= NULL
;
2470 if (sample_locations
&& sample_locations
->sampleLocationsEnable
)
2471 samp_loc
= &sample_locations
->sampleLocationsInfo
;
2473 tu6_emit_sample_locations(&blend_cs
, samp_loc
);
2476 tu6_emit_blend_control(&blend_cs
, blend_enable_mask
, msaa_info
);
2478 pipeline
->blend
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &blend_cs
);
2482 tu_pipeline_finish(struct tu_pipeline
*pipeline
,
2483 struct tu_device
*dev
,
2484 const VkAllocationCallbacks
*alloc
)
2486 tu_cs_finish(&pipeline
->cs
);
2488 if (pipeline
->program
.binary_bo
.gem_handle
)
2489 tu_bo_finish(dev
, &pipeline
->program
.binary_bo
);
2493 tu_pipeline_builder_build(struct tu_pipeline_builder
*builder
,
2494 struct tu_pipeline
**pipeline
)
2496 VkResult result
= tu_pipeline_create(builder
->device
, builder
->layout
,
2497 false, builder
->alloc
, pipeline
);
2498 if (result
!= VK_SUCCESS
)
2501 (*pipeline
)->layout
= builder
->layout
;
2503 /* compile and upload shaders */
2504 result
= tu_pipeline_builder_compile_shaders(builder
);
2505 if (result
== VK_SUCCESS
)
2506 result
= tu_pipeline_builder_upload_shaders(builder
, *pipeline
);
2507 if (result
!= VK_SUCCESS
) {
2508 tu_pipeline_finish(*pipeline
, builder
->device
, builder
->alloc
);
2509 vk_free2(&builder
->device
->alloc
, builder
->alloc
, *pipeline
);
2510 *pipeline
= VK_NULL_HANDLE
;
2515 tu_pipeline_builder_parse_dynamic(builder
, *pipeline
);
2516 tu_pipeline_builder_parse_shader_stages(builder
, *pipeline
);
2517 tu_pipeline_builder_parse_vertex_input(builder
, *pipeline
);
2518 tu_pipeline_builder_parse_input_assembly(builder
, *pipeline
);
2519 tu_pipeline_builder_parse_viewport(builder
, *pipeline
);
2520 tu_pipeline_builder_parse_rasterization(builder
, *pipeline
);
2521 tu_pipeline_builder_parse_depth_stencil(builder
, *pipeline
);
2522 tu_pipeline_builder_parse_multisample_and_color_blend(builder
, *pipeline
);
2523 tu6_emit_load_state(*pipeline
, false);
2525 /* we should have reserved enough space upfront such that the CS never
2528 assert((*pipeline
)->cs
.bo_count
== 1);
2534 tu_pipeline_builder_finish(struct tu_pipeline_builder
*builder
)
2536 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2537 if (!builder
->shaders
[i
])
2539 tu_shader_destroy(builder
->device
, builder
->shaders
[i
], builder
->alloc
);
2544 tu_pipeline_builder_init_graphics(
2545 struct tu_pipeline_builder
*builder
,
2546 struct tu_device
*dev
,
2547 struct tu_pipeline_cache
*cache
,
2548 const VkGraphicsPipelineCreateInfo
*create_info
,
2549 const VkAllocationCallbacks
*alloc
)
2551 TU_FROM_HANDLE(tu_pipeline_layout
, layout
, create_info
->layout
);
2553 *builder
= (struct tu_pipeline_builder
) {
2556 .create_info
= create_info
,
2561 builder
->rasterizer_discard
=
2562 create_info
->pRasterizationState
->rasterizerDiscardEnable
;
2564 if (builder
->rasterizer_discard
) {
2565 builder
->samples
= VK_SAMPLE_COUNT_1_BIT
;
2567 builder
->samples
= create_info
->pMultisampleState
->rasterizationSamples
;
2569 const struct tu_render_pass
*pass
=
2570 tu_render_pass_from_handle(create_info
->renderPass
);
2571 const struct tu_subpass
*subpass
=
2572 &pass
->subpasses
[create_info
->subpass
];
2574 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
2575 builder
->depth_attachment_format
= (a
!= VK_ATTACHMENT_UNUSED
) ?
2576 pass
->attachments
[a
].format
: VK_FORMAT_UNDEFINED
;
2578 assert(subpass
->color_count
== 0 ||
2579 !create_info
->pColorBlendState
||
2580 subpass
->color_count
== create_info
->pColorBlendState
->attachmentCount
);
2581 builder
->color_attachment_count
= subpass
->color_count
;
2582 for (uint32_t i
= 0; i
< subpass
->color_count
; i
++) {
2583 const uint32_t a
= subpass
->color_attachments
[i
].attachment
;
2584 if (a
== VK_ATTACHMENT_UNUSED
)
2587 builder
->color_attachment_formats
[i
] = pass
->attachments
[a
].format
;
2588 builder
->use_color_attachments
= true;
2594 tu_graphics_pipeline_create(VkDevice device
,
2595 VkPipelineCache pipelineCache
,
2596 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2597 const VkAllocationCallbacks
*pAllocator
,
2598 VkPipeline
*pPipeline
)
2600 TU_FROM_HANDLE(tu_device
, dev
, device
);
2601 TU_FROM_HANDLE(tu_pipeline_cache
, cache
, pipelineCache
);
2603 struct tu_pipeline_builder builder
;
2604 tu_pipeline_builder_init_graphics(&builder
, dev
, cache
,
2605 pCreateInfo
, pAllocator
);
2607 struct tu_pipeline
*pipeline
= NULL
;
2608 VkResult result
= tu_pipeline_builder_build(&builder
, &pipeline
);
2609 tu_pipeline_builder_finish(&builder
);
2611 if (result
== VK_SUCCESS
)
2612 *pPipeline
= tu_pipeline_to_handle(pipeline
);
2614 *pPipeline
= VK_NULL_HANDLE
;
2620 tu_CreateGraphicsPipelines(VkDevice device
,
2621 VkPipelineCache pipelineCache
,
2623 const VkGraphicsPipelineCreateInfo
*pCreateInfos
,
2624 const VkAllocationCallbacks
*pAllocator
,
2625 VkPipeline
*pPipelines
)
2627 VkResult final_result
= VK_SUCCESS
;
2629 for (uint32_t i
= 0; i
< count
; i
++) {
2630 VkResult result
= tu_graphics_pipeline_create(device
, pipelineCache
,
2631 &pCreateInfos
[i
], pAllocator
,
2634 if (result
!= VK_SUCCESS
)
2635 final_result
= result
;
2638 return final_result
;
2642 tu6_emit_compute_program(struct tu_cs
*cs
,
2643 struct tu_shader
*shader
,
2644 const struct tu_bo
*binary_bo
)
2646 const struct ir3_shader_variant
*v
= &shader
->variants
[0];
2648 tu6_emit_cs_config(cs
, shader
, v
);
2650 /* The compute program is the only one in the pipeline, so 0 offset. */
2651 tu6_emit_shader_object(cs
, MESA_SHADER_COMPUTE
, v
, binary_bo
, 0);
2653 tu6_emit_immediates(cs
, v
, CP_LOAD_STATE6_FRAG
, SB6_CS_SHADER
);
2657 tu_compute_upload_shader(VkDevice device
,
2658 struct tu_pipeline
*pipeline
,
2659 struct tu_shader
*shader
)
2661 TU_FROM_HANDLE(tu_device
, dev
, device
);
2662 struct tu_bo
*bo
= &pipeline
->program
.binary_bo
;
2663 struct ir3_shader_variant
*v
= &shader
->variants
[0];
2665 uint32_t shader_size
= sizeof(uint32_t) * v
->info
.sizedwords
;
2667 tu_bo_init_new(dev
, bo
, shader_size
);
2668 if (result
!= VK_SUCCESS
)
2671 result
= tu_bo_map(dev
, bo
);
2672 if (result
!= VK_SUCCESS
)
2675 memcpy(bo
->map
, shader
->binary
, shader_size
);
2682 tu_compute_pipeline_create(VkDevice device
,
2683 VkPipelineCache _cache
,
2684 const VkComputePipelineCreateInfo
*pCreateInfo
,
2685 const VkAllocationCallbacks
*pAllocator
,
2686 VkPipeline
*pPipeline
)
2688 TU_FROM_HANDLE(tu_device
, dev
, device
);
2689 TU_FROM_HANDLE(tu_pipeline_layout
, layout
, pCreateInfo
->layout
);
2690 const VkPipelineShaderStageCreateInfo
*stage_info
= &pCreateInfo
->stage
;
2693 struct tu_pipeline
*pipeline
;
2695 *pPipeline
= VK_NULL_HANDLE
;
2697 result
= tu_pipeline_create(dev
, layout
, true, pAllocator
, &pipeline
);
2698 if (result
!= VK_SUCCESS
)
2701 pipeline
->layout
= layout
;
2703 struct tu_shader_compile_options options
;
2704 tu_shader_compile_options_init(&options
, NULL
);
2706 struct tu_shader
*shader
=
2707 tu_shader_create(dev
, MESA_SHADER_COMPUTE
, stage_info
, layout
, pAllocator
);
2709 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2713 result
= tu_shader_compile(dev
, shader
, NULL
, &options
, pAllocator
);
2714 if (result
!= VK_SUCCESS
)
2717 struct ir3_shader_variant
*v
= &shader
->variants
[0];
2719 tu_pipeline_set_linkage(&pipeline
->program
.link
[MESA_SHADER_COMPUTE
],
2722 result
= tu_compute_upload_shader(device
, pipeline
, shader
);
2723 if (result
!= VK_SUCCESS
)
2726 for (int i
= 0; i
< 3; i
++)
2727 pipeline
->compute
.local_size
[i
] = v
->shader
->nir
->info
.cs
.local_size
[i
];
2729 struct tu_cs prog_cs
;
2730 tu_cs_begin_sub_stream(&pipeline
->cs
, 512, &prog_cs
);
2731 tu6_emit_compute_program(&prog_cs
, shader
, &pipeline
->program
.binary_bo
);
2732 pipeline
->program
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &prog_cs
);
2734 tu6_emit_load_state(pipeline
, true);
2736 *pPipeline
= tu_pipeline_to_handle(pipeline
);
2741 tu_shader_destroy(dev
, shader
, pAllocator
);
2743 tu_pipeline_finish(pipeline
, dev
, pAllocator
);
2744 vk_free2(&dev
->alloc
, pAllocator
, pipeline
);
2750 tu_CreateComputePipelines(VkDevice device
,
2751 VkPipelineCache pipelineCache
,
2753 const VkComputePipelineCreateInfo
*pCreateInfos
,
2754 const VkAllocationCallbacks
*pAllocator
,
2755 VkPipeline
*pPipelines
)
2757 VkResult final_result
= VK_SUCCESS
;
2759 for (uint32_t i
= 0; i
< count
; i
++) {
2760 VkResult result
= tu_compute_pipeline_create(device
, pipelineCache
,
2762 pAllocator
, &pPipelines
[i
]);
2763 if (result
!= VK_SUCCESS
)
2764 final_result
= result
;
2767 return final_result
;
2771 tu_DestroyPipeline(VkDevice _device
,
2772 VkPipeline _pipeline
,
2773 const VkAllocationCallbacks
*pAllocator
)
2775 TU_FROM_HANDLE(tu_device
, dev
, _device
);
2776 TU_FROM_HANDLE(tu_pipeline
, pipeline
, _pipeline
);
2781 tu_pipeline_finish(pipeline
, dev
, pAllocator
);
2782 vk_free2(&dev
->alloc
, pAllocator
, pipeline
);