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compiler: rename SYSTEM_VALUE_VARYING_COORD
[mesa.git] / src / freedreno / vulkan / tu_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "main/menums.h"
31 #include "nir/nir.h"
32 #include "nir/nir_builder.h"
33 #include "spirv/nir_spirv.h"
34 #include "util/debug.h"
35 #include "util/mesa-sha1.h"
36 #include "util/u_atomic.h"
37 #include "vk_format.h"
38 #include "vk_util.h"
39
40 #include "tu_cs.h"
41
42 struct tu_pipeline_builder
43 {
44 struct tu_device *device;
45 struct tu_pipeline_cache *cache;
46 const VkAllocationCallbacks *alloc;
47 const VkGraphicsPipelineCreateInfo *create_info;
48
49 struct tu_shader *shaders[MESA_SHADER_STAGES];
50 uint32_t shader_offsets[MESA_SHADER_STAGES];
51 uint32_t binning_vs_offset;
52 uint32_t shader_total_size;
53
54 bool rasterizer_discard;
55 /* these states are affectd by rasterizer_discard */
56 VkSampleCountFlagBits samples;
57 bool use_depth_stencil_attachment;
58 bool use_color_attachments;
59 uint32_t color_attachment_count;
60 VkFormat color_attachment_formats[MAX_RTS];
61 };
62
63 static enum tu_dynamic_state_bits
64 tu_dynamic_state_bit(VkDynamicState state)
65 {
66 switch (state) {
67 case VK_DYNAMIC_STATE_VIEWPORT:
68 return TU_DYNAMIC_VIEWPORT;
69 case VK_DYNAMIC_STATE_SCISSOR:
70 return TU_DYNAMIC_SCISSOR;
71 case VK_DYNAMIC_STATE_LINE_WIDTH:
72 return TU_DYNAMIC_LINE_WIDTH;
73 case VK_DYNAMIC_STATE_DEPTH_BIAS:
74 return TU_DYNAMIC_DEPTH_BIAS;
75 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
76 return TU_DYNAMIC_BLEND_CONSTANTS;
77 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
78 return TU_DYNAMIC_DEPTH_BOUNDS;
79 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
80 return TU_DYNAMIC_STENCIL_COMPARE_MASK;
81 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
82 return TU_DYNAMIC_STENCIL_WRITE_MASK;
83 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
84 return TU_DYNAMIC_STENCIL_REFERENCE;
85 default:
86 unreachable("invalid dynamic state");
87 return 0;
88 }
89 }
90
91 static gl_shader_stage
92 tu_shader_stage(VkShaderStageFlagBits stage)
93 {
94 switch (stage) {
95 case VK_SHADER_STAGE_VERTEX_BIT:
96 return MESA_SHADER_VERTEX;
97 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
98 return MESA_SHADER_TESS_CTRL;
99 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
100 return MESA_SHADER_TESS_EVAL;
101 case VK_SHADER_STAGE_GEOMETRY_BIT:
102 return MESA_SHADER_GEOMETRY;
103 case VK_SHADER_STAGE_FRAGMENT_BIT:
104 return MESA_SHADER_FRAGMENT;
105 case VK_SHADER_STAGE_COMPUTE_BIT:
106 return MESA_SHADER_COMPUTE;
107 default:
108 unreachable("invalid VkShaderStageFlagBits");
109 return MESA_SHADER_NONE;
110 }
111 }
112
113 static const VkVertexInputAttributeDescription *
114 tu_find_vertex_input_attribute(
115 const VkPipelineVertexInputStateCreateInfo *vi_info, uint32_t slot)
116 {
117 assert(slot >= VERT_ATTRIB_GENERIC0);
118 slot -= VERT_ATTRIB_GENERIC0;
119 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
120 if (vi_info->pVertexAttributeDescriptions[i].location == slot)
121 return &vi_info->pVertexAttributeDescriptions[i];
122 }
123 return NULL;
124 }
125
126 static const VkVertexInputBindingDescription *
127 tu_find_vertex_input_binding(
128 const VkPipelineVertexInputStateCreateInfo *vi_info,
129 const VkVertexInputAttributeDescription *vi_attr)
130 {
131 assert(vi_attr);
132 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
133 if (vi_info->pVertexBindingDescriptions[i].binding == vi_attr->binding)
134 return &vi_info->pVertexBindingDescriptions[i];
135 }
136 return NULL;
137 }
138
139 static bool
140 tu_logic_op_reads_dst(VkLogicOp op)
141 {
142 switch (op) {
143 case VK_LOGIC_OP_CLEAR:
144 case VK_LOGIC_OP_COPY:
145 case VK_LOGIC_OP_COPY_INVERTED:
146 case VK_LOGIC_OP_SET:
147 return false;
148 default:
149 return true;
150 }
151 }
152
153 static VkBlendFactor
154 tu_blend_factor_no_dst_alpha(VkBlendFactor factor)
155 {
156 /* treat dst alpha as 1.0 and avoid reading it */
157 switch (factor) {
158 case VK_BLEND_FACTOR_DST_ALPHA:
159 return VK_BLEND_FACTOR_ONE;
160 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
161 return VK_BLEND_FACTOR_ZERO;
162 default:
163 return factor;
164 }
165 }
166
167 static enum pc_di_primtype
168 tu6_primtype(VkPrimitiveTopology topology)
169 {
170 switch (topology) {
171 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
172 return DI_PT_POINTLIST;
173 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
174 return DI_PT_LINELIST;
175 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
176 return DI_PT_LINESTRIP;
177 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
178 return DI_PT_TRILIST;
179 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
180 return DI_PT_TRILIST;
181 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
182 return DI_PT_TRIFAN;
183 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
184 return DI_PT_LINE_ADJ;
185 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
186 return DI_PT_LINESTRIP_ADJ;
187 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
188 return DI_PT_TRI_ADJ;
189 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
190 return DI_PT_TRISTRIP_ADJ;
191 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
192 default:
193 unreachable("invalid primitive topology");
194 return DI_PT_NONE;
195 }
196 }
197
198 static enum adreno_compare_func
199 tu6_compare_func(VkCompareOp op)
200 {
201 switch (op) {
202 case VK_COMPARE_OP_NEVER:
203 return FUNC_NEVER;
204 case VK_COMPARE_OP_LESS:
205 return FUNC_LESS;
206 case VK_COMPARE_OP_EQUAL:
207 return FUNC_EQUAL;
208 case VK_COMPARE_OP_LESS_OR_EQUAL:
209 return FUNC_LEQUAL;
210 case VK_COMPARE_OP_GREATER:
211 return FUNC_GREATER;
212 case VK_COMPARE_OP_NOT_EQUAL:
213 return FUNC_NOTEQUAL;
214 case VK_COMPARE_OP_GREATER_OR_EQUAL:
215 return FUNC_GEQUAL;
216 case VK_COMPARE_OP_ALWAYS:
217 return FUNC_ALWAYS;
218 default:
219 unreachable("invalid VkCompareOp");
220 return FUNC_NEVER;
221 }
222 }
223
224 static enum adreno_stencil_op
225 tu6_stencil_op(VkStencilOp op)
226 {
227 switch (op) {
228 case VK_STENCIL_OP_KEEP:
229 return STENCIL_KEEP;
230 case VK_STENCIL_OP_ZERO:
231 return STENCIL_ZERO;
232 case VK_STENCIL_OP_REPLACE:
233 return STENCIL_REPLACE;
234 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
235 return STENCIL_INCR_CLAMP;
236 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
237 return STENCIL_DECR_CLAMP;
238 case VK_STENCIL_OP_INVERT:
239 return STENCIL_INVERT;
240 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
241 return STENCIL_INCR_WRAP;
242 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
243 return STENCIL_DECR_WRAP;
244 default:
245 unreachable("invalid VkStencilOp");
246 return STENCIL_KEEP;
247 }
248 }
249
250 static enum a3xx_rop_code
251 tu6_rop(VkLogicOp op)
252 {
253 switch (op) {
254 case VK_LOGIC_OP_CLEAR:
255 return ROP_CLEAR;
256 case VK_LOGIC_OP_AND:
257 return ROP_AND;
258 case VK_LOGIC_OP_AND_REVERSE:
259 return ROP_AND_REVERSE;
260 case VK_LOGIC_OP_COPY:
261 return ROP_COPY;
262 case VK_LOGIC_OP_AND_INVERTED:
263 return ROP_AND_INVERTED;
264 case VK_LOGIC_OP_NO_OP:
265 return ROP_NOOP;
266 case VK_LOGIC_OP_XOR:
267 return ROP_XOR;
268 case VK_LOGIC_OP_OR:
269 return ROP_OR;
270 case VK_LOGIC_OP_NOR:
271 return ROP_NOR;
272 case VK_LOGIC_OP_EQUIVALENT:
273 return ROP_EQUIV;
274 case VK_LOGIC_OP_INVERT:
275 return ROP_INVERT;
276 case VK_LOGIC_OP_OR_REVERSE:
277 return ROP_OR_REVERSE;
278 case VK_LOGIC_OP_COPY_INVERTED:
279 return ROP_COPY_INVERTED;
280 case VK_LOGIC_OP_OR_INVERTED:
281 return ROP_OR_INVERTED;
282 case VK_LOGIC_OP_NAND:
283 return ROP_NAND;
284 case VK_LOGIC_OP_SET:
285 return ROP_SET;
286 default:
287 unreachable("invalid VkLogicOp");
288 return ROP_NOOP;
289 }
290 }
291
292 static enum adreno_rb_blend_factor
293 tu6_blend_factor(VkBlendFactor factor)
294 {
295 switch (factor) {
296 case VK_BLEND_FACTOR_ZERO:
297 return FACTOR_ZERO;
298 case VK_BLEND_FACTOR_ONE:
299 return FACTOR_ONE;
300 case VK_BLEND_FACTOR_SRC_COLOR:
301 return FACTOR_SRC_COLOR;
302 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
303 return FACTOR_ONE_MINUS_SRC_COLOR;
304 case VK_BLEND_FACTOR_DST_COLOR:
305 return FACTOR_DST_COLOR;
306 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
307 return FACTOR_ONE_MINUS_DST_COLOR;
308 case VK_BLEND_FACTOR_SRC_ALPHA:
309 return FACTOR_SRC_ALPHA;
310 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
311 return FACTOR_ONE_MINUS_SRC_ALPHA;
312 case VK_BLEND_FACTOR_DST_ALPHA:
313 return FACTOR_DST_ALPHA;
314 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
315 return FACTOR_ONE_MINUS_DST_ALPHA;
316 case VK_BLEND_FACTOR_CONSTANT_COLOR:
317 return FACTOR_CONSTANT_COLOR;
318 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
319 return FACTOR_ONE_MINUS_CONSTANT_COLOR;
320 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
321 return FACTOR_CONSTANT_ALPHA;
322 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
323 return FACTOR_ONE_MINUS_CONSTANT_ALPHA;
324 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
325 return FACTOR_SRC_ALPHA_SATURATE;
326 case VK_BLEND_FACTOR_SRC1_COLOR:
327 return FACTOR_SRC1_COLOR;
328 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
329 return FACTOR_ONE_MINUS_SRC1_COLOR;
330 case VK_BLEND_FACTOR_SRC1_ALPHA:
331 return FACTOR_SRC1_ALPHA;
332 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
333 return FACTOR_ONE_MINUS_SRC1_ALPHA;
334 default:
335 unreachable("invalid VkBlendFactor");
336 return FACTOR_ZERO;
337 }
338 }
339
340 static enum a3xx_rb_blend_opcode
341 tu6_blend_op(VkBlendOp op)
342 {
343 switch (op) {
344 case VK_BLEND_OP_ADD:
345 return BLEND_DST_PLUS_SRC;
346 case VK_BLEND_OP_SUBTRACT:
347 return BLEND_SRC_MINUS_DST;
348 case VK_BLEND_OP_REVERSE_SUBTRACT:
349 return BLEND_DST_MINUS_SRC;
350 case VK_BLEND_OP_MIN:
351 return BLEND_MIN_DST_SRC;
352 case VK_BLEND_OP_MAX:
353 return BLEND_MAX_DST_SRC;
354 default:
355 unreachable("invalid VkBlendOp");
356 return BLEND_DST_PLUS_SRC;
357 }
358 }
359
360 static void
361 tu6_emit_vs_config(struct tu_cs *cs, const struct ir3_shader_variant *vs)
362 {
363 uint32_t sp_vs_ctrl =
364 A6XX_SP_VS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
365 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs->info.max_reg + 1) |
366 A6XX_SP_VS_CTRL_REG0_MERGEDREGS |
367 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs->branchstack);
368 if (vs->num_samp)
369 sp_vs_ctrl |= A6XX_SP_VS_CTRL_REG0_PIXLODENABLE;
370
371 uint32_t sp_vs_config = A6XX_SP_VS_CONFIG_NTEX(vs->num_samp) |
372 A6XX_SP_VS_CONFIG_NSAMP(vs->num_samp);
373 if (vs->instrlen)
374 sp_vs_config |= A6XX_SP_VS_CONFIG_ENABLED;
375
376 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_CTRL_REG0, 1);
377 tu_cs_emit(cs, sp_vs_ctrl);
378
379 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_CONFIG, 2);
380 tu_cs_emit(cs, sp_vs_config);
381 tu_cs_emit(cs, vs->instrlen);
382
383 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_VS_CNTL, 1);
384 tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(vs->constlen, 4)) | 0x100);
385 }
386
387 static void
388 tu6_emit_hs_config(struct tu_cs *cs, const struct ir3_shader_variant *hs)
389 {
390 uint32_t sp_hs_config = 0;
391 if (hs->instrlen)
392 sp_hs_config |= A6XX_SP_HS_CONFIG_ENABLED;
393
394 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
395 tu_cs_emit(cs, 0);
396
397 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_CONFIG, 2);
398 tu_cs_emit(cs, sp_hs_config);
399 tu_cs_emit(cs, hs->instrlen);
400
401 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_HS_CNTL, 1);
402 tu_cs_emit(cs, A6XX_HLSQ_HS_CNTL_CONSTLEN(align(hs->constlen, 4)));
403 }
404
405 static void
406 tu6_emit_ds_config(struct tu_cs *cs, const struct ir3_shader_variant *ds)
407 {
408 uint32_t sp_ds_config = 0;
409 if (ds->instrlen)
410 sp_ds_config |= A6XX_SP_DS_CONFIG_ENABLED;
411
412 tu_cs_emit_pkt4(cs, REG_A6XX_SP_DS_CONFIG, 2);
413 tu_cs_emit(cs, sp_ds_config);
414 tu_cs_emit(cs, ds->instrlen);
415
416 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_DS_CNTL, 1);
417 tu_cs_emit(cs, A6XX_HLSQ_DS_CNTL_CONSTLEN(align(ds->constlen, 4)));
418 }
419
420 static void
421 tu6_emit_gs_config(struct tu_cs *cs, const struct ir3_shader_variant *gs)
422 {
423 uint32_t sp_gs_config = 0;
424 if (gs->instrlen)
425 sp_gs_config |= A6XX_SP_GS_CONFIG_ENABLED;
426
427 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
428 tu_cs_emit(cs, 0);
429
430 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CONFIG, 2);
431 tu_cs_emit(cs, sp_gs_config);
432 tu_cs_emit(cs, gs->instrlen);
433
434 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_GS_CNTL, 1);
435 tu_cs_emit(cs, A6XX_HLSQ_GS_CNTL_CONSTLEN(align(gs->constlen, 4)));
436 }
437
438 static void
439 tu6_emit_fs_config(struct tu_cs *cs, const struct ir3_shader_variant *fs)
440 {
441 uint32_t sp_fs_ctrl =
442 A6XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) | 0x1000000 |
443 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs->info.max_reg + 1) |
444 A6XX_SP_FS_CTRL_REG0_MERGEDREGS |
445 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs->branchstack);
446 if (fs->total_in > 0 || fs->frag_coord)
447 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_VARYING;
448 if (fs->num_samp > 0)
449 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_PIXLODENABLE;
450
451 uint32_t sp_fs_config = A6XX_SP_FS_CONFIG_NTEX(fs->num_samp) |
452 A6XX_SP_FS_CONFIG_NSAMP(fs->num_samp);
453 if (fs->instrlen)
454 sp_fs_config |= A6XX_SP_FS_CONFIG_ENABLED;
455
456 tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_A99E, 1);
457 tu_cs_emit(cs, 0x7fc0);
458
459 tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_A9A8, 1);
460 tu_cs_emit(cs, 0);
461
462 tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_AB00, 1);
463 tu_cs_emit(cs, 0x5);
464
465 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_CTRL_REG0, 1);
466 tu_cs_emit(cs, sp_fs_ctrl);
467
468 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_CONFIG, 2);
469 tu_cs_emit(cs, sp_fs_config);
470 tu_cs_emit(cs, fs->instrlen);
471
472 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_FS_CNTL, 1);
473 tu_cs_emit(cs, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(fs->constlen, 4)) | 0x100);
474 }
475
476 static void
477 tu6_emit_vs_system_values(struct tu_cs *cs,
478 const struct ir3_shader_variant *vs)
479 {
480 const uint32_t vertexid_regid =
481 ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE);
482 const uint32_t instanceid_regid =
483 ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
484
485 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_1, 6);
486 tu_cs_emit(cs, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid) |
487 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid) |
488 0xfcfc0000);
489 tu_cs_emit(cs, 0x0000fcfc); /* VFD_CONTROL_2 */
490 tu_cs_emit(cs, 0xfcfcfcfc); /* VFD_CONTROL_3 */
491 tu_cs_emit(cs, 0x000000fc); /* VFD_CONTROL_4 */
492 tu_cs_emit(cs, 0x0000fcfc); /* VFD_CONTROL_5 */
493 tu_cs_emit(cs, 0x00000000); /* VFD_CONTROL_6 */
494 }
495
496 static void
497 tu6_emit_vpc(struct tu_cs *cs,
498 const struct ir3_shader_variant *vs,
499 const struct ir3_shader_variant *fs,
500 bool binning_pass)
501 {
502 struct ir3_shader_linkage linkage = { 0 };
503 ir3_link_shaders(&linkage, vs, fs);
504
505 if (vs->shader->stream_output.num_outputs && !binning_pass)
506 tu_finishme("stream output");
507
508 BITSET_DECLARE(vpc_var_enables, 128) = { 0 };
509 for (uint32_t i = 0; i < linkage.cnt; i++) {
510 const uint32_t comp_count = util_last_bit(linkage.var[i].compmask);
511 for (uint32_t j = 0; j < comp_count; j++)
512 BITSET_SET(vpc_var_enables, linkage.var[i].loc + j);
513 }
514
515 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VAR_DISABLE(0), 4);
516 tu_cs_emit(cs, ~vpc_var_enables[0]);
517 tu_cs_emit(cs, ~vpc_var_enables[1]);
518 tu_cs_emit(cs, ~vpc_var_enables[2]);
519 tu_cs_emit(cs, ~vpc_var_enables[3]);
520
521 /* a6xx finds position/pointsize at the end */
522 const uint32_t position_regid =
523 ir3_find_output_regid(vs, VARYING_SLOT_POS);
524 const uint32_t pointsize_regid =
525 ir3_find_output_regid(vs, VARYING_SLOT_PSIZ);
526 uint32_t pointsize_loc = 0xff;
527 if (position_regid != regid(63, 0))
528 ir3_link_add(&linkage, position_regid, 0xf, linkage.max_loc);
529 if (pointsize_regid != regid(63, 0)) {
530 pointsize_loc = linkage.max_loc;
531 ir3_link_add(&linkage, pointsize_regid, 0x1, linkage.max_loc);
532 }
533
534 /* map vs outputs to VPC */
535 assert(linkage.cnt <= 32);
536 const uint32_t sp_vs_out_count = (linkage.cnt + 1) / 2;
537 const uint32_t sp_vs_vpc_dst_count = (linkage.cnt + 3) / 4;
538 uint32_t sp_vs_out[16];
539 uint32_t sp_vs_vpc_dst[8];
540 sp_vs_out[sp_vs_out_count - 1] = 0;
541 sp_vs_vpc_dst[sp_vs_vpc_dst_count - 1] = 0;
542 for (uint32_t i = 0; i < linkage.cnt; i++) {
543 ((uint16_t *) sp_vs_out)[i] =
544 A6XX_SP_VS_OUT_REG_A_REGID(linkage.var[i].regid) |
545 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage.var[i].compmask);
546 ((uint8_t *) sp_vs_vpc_dst)[i] =
547 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage.var[i].loc);
548 }
549
550 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_OUT_REG(0), sp_vs_out_count);
551 tu_cs_emit_array(cs, sp_vs_out, sp_vs_out_count);
552
553 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_VPC_DST_REG(0), sp_vs_vpc_dst_count);
554 tu_cs_emit_array(cs, sp_vs_vpc_dst, sp_vs_vpc_dst_count);
555
556 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_CNTL_0, 1);
557 tu_cs_emit(cs, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs->total_in) |
558 (fs->total_in > 0 ? A6XX_VPC_CNTL_0_VARYING : 0) |
559 0xff00ff00);
560
561 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK, 1);
562 tu_cs_emit(cs, A6XX_VPC_PACK_NUMNONPOSVAR(fs->total_in) |
563 A6XX_VPC_PACK_PSIZELOC(pointsize_loc) |
564 A6XX_VPC_PACK_STRIDE_IN_VPC(linkage.max_loc));
565
566 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_GS_SIV_CNTL, 1);
567 tu_cs_emit(cs, 0x0000ffff); /* XXX */
568
569 tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
570 tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage.cnt));
571
572 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
573 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage.max_loc) |
574 (vs->writes_psize ? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE : 0));
575 }
576
577 static int
578 tu6_vpc_varying_mode(const struct ir3_shader_variant *fs,
579 uint32_t index,
580 uint8_t *interp_mode,
581 uint8_t *ps_repl_mode)
582 {
583 enum
584 {
585 INTERP_SMOOTH = 0,
586 INTERP_FLAT = 1,
587 INTERP_ZERO = 2,
588 INTERP_ONE = 3,
589 };
590 enum
591 {
592 PS_REPL_NONE = 0,
593 PS_REPL_S = 1,
594 PS_REPL_T = 2,
595 PS_REPL_ONE_MINUS_T = 3,
596 };
597
598 const uint32_t compmask = fs->inputs[index].compmask;
599
600 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
601 * fourth component occupy three consecutive varying slots
602 */
603 int shift = 0;
604 *interp_mode = 0;
605 *ps_repl_mode = 0;
606 if (fs->inputs[index].slot == VARYING_SLOT_PNTC) {
607 if (compmask & 0x1) {
608 *ps_repl_mode |= PS_REPL_S << shift;
609 shift += 2;
610 }
611 if (compmask & 0x2) {
612 *ps_repl_mode |= PS_REPL_T << shift;
613 shift += 2;
614 }
615 if (compmask & 0x4) {
616 *interp_mode |= INTERP_ZERO << shift;
617 shift += 2;
618 }
619 if (compmask & 0x8) {
620 *interp_mode |= INTERP_ONE << 6;
621 shift += 2;
622 }
623 } else if ((fs->inputs[index].interpolate == INTERP_MODE_FLAT) ||
624 fs->inputs[index].rasterflat) {
625 for (int i = 0; i < 4; i++) {
626 if (compmask & (1 << i)) {
627 *interp_mode |= INTERP_FLAT << shift;
628 shift += 2;
629 }
630 }
631 }
632
633 return shift;
634 }
635
636 static void
637 tu6_emit_vpc_varying_modes(struct tu_cs *cs,
638 const struct ir3_shader_variant *fs,
639 bool binning_pass)
640 {
641 uint32_t interp_modes[8] = { 0 };
642 uint32_t ps_repl_modes[8] = { 0 };
643
644 if (!binning_pass) {
645 for (int i = -1;
646 (i = ir3_next_varying(fs, i)) < (int) fs->inputs_count;) {
647
648 /* get the mode for input i */
649 uint8_t interp_mode;
650 uint8_t ps_repl_mode;
651 const int bits =
652 tu6_vpc_varying_mode(fs, i, &interp_mode, &ps_repl_mode);
653
654 /* OR the mode into the array */
655 const uint32_t inloc = fs->inputs[i].inloc * 2;
656 uint32_t n = inloc / 32;
657 uint32_t shift = inloc % 32;
658 interp_modes[n] |= interp_mode << shift;
659 ps_repl_modes[n] |= ps_repl_mode << shift;
660 if (shift + bits > 32) {
661 n++;
662 shift = 32 - shift;
663
664 interp_modes[n] |= interp_mode >> shift;
665 ps_repl_modes[n] |= ps_repl_mode >> shift;
666 }
667 }
668 }
669
670 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
671 tu_cs_emit_array(cs, interp_modes, 8);
672
673 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
674 tu_cs_emit_array(cs, ps_repl_modes, 8);
675 }
676
677 static void
678 tu6_emit_fs_system_values(struct tu_cs *cs,
679 const struct ir3_shader_variant *fs)
680 {
681 const uint32_t frontfacing_regid =
682 ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
683 const uint32_t sampleid_regid =
684 ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
685 const uint32_t samplemaskin_regid =
686 ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
687 const uint32_t fragcoord_xy_regid =
688 ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
689 const uint32_t fragcoord_zw_regid = (fragcoord_xy_regid != regid(63, 0))
690 ? (fragcoord_xy_regid + 2)
691 : fragcoord_xy_regid;
692 const uint32_t varyingcoord_regid =
693 ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PIXEL);
694
695 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
696 tu_cs_emit(cs, 0x7);
697 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(frontfacing_regid) |
698 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(sampleid_regid) |
699 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(samplemaskin_regid) |
700 0xfc000000);
701 tu_cs_emit(cs,
702 A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(varyingcoord_regid) |
703 0xfcfcfc00);
704 tu_cs_emit(cs,
705 A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(fragcoord_xy_regid) |
706 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(fragcoord_zw_regid) |
707 0x0000fcfc);
708 tu_cs_emit(cs, 0xfc);
709 }
710
711 static void
712 tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
713 {
714 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
715 tu_cs_emit(cs, fs->total_in > 0 ? 3 : 1);
716
717 tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_A982, 1);
718 tu_cs_emit(cs, 0); /* XXX */
719
720 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
721 tu_cs_emit(cs, 0xff); /* XXX */
722
723 uint32_t gras_cntl = 0;
724 if (fs->total_in > 0)
725 gras_cntl |= A6XX_GRAS_CNTL_VARYING;
726 if (fs->frag_coord) {
727 gras_cntl |= A6XX_GRAS_CNTL_UNK3 | A6XX_GRAS_CNTL_XCOORD |
728 A6XX_GRAS_CNTL_YCOORD | A6XX_GRAS_CNTL_ZCOORD |
729 A6XX_GRAS_CNTL_WCOORD;
730 }
731
732 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CNTL, 1);
733 tu_cs_emit(cs, gras_cntl);
734
735 uint32_t rb_render_control = 0;
736 if (fs->total_in > 0) {
737 rb_render_control =
738 A6XX_RB_RENDER_CONTROL0_VARYING | A6XX_RB_RENDER_CONTROL0_UNK10;
739 }
740 if (fs->frag_coord) {
741 rb_render_control |=
742 A6XX_RB_RENDER_CONTROL0_UNK3 | A6XX_RB_RENDER_CONTROL0_XCOORD |
743 A6XX_RB_RENDER_CONTROL0_YCOORD | A6XX_RB_RENDER_CONTROL0_ZCOORD |
744 A6XX_RB_RENDER_CONTROL0_WCOORD;
745 }
746
747 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CONTROL0, 2);
748 tu_cs_emit(cs, rb_render_control);
749 tu_cs_emit(cs, (fs->frag_face ? A6XX_RB_RENDER_CONTROL1_FACENESS : 0));
750 }
751
752 static void
753 tu6_emit_fs_outputs(struct tu_cs *cs,
754 const struct ir3_shader_variant *fs,
755 uint32_t mrt_count)
756 {
757 const uint32_t fragdepth_regid =
758 ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
759 uint32_t fragdata_regid[8];
760 if (fs->color0_mrt) {
761 fragdata_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
762 for (uint32_t i = 1; i < ARRAY_SIZE(fragdata_regid); i++)
763 fragdata_regid[i] = fragdata_regid[0];
764 } else {
765 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++)
766 fragdata_regid[i] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0 + i);
767 }
768
769 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_CNTL0, 2);
770 tu_cs_emit(
771 cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(fragdepth_regid) | 0xfcfc0000);
772 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count));
773
774 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
775 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++) {
776 // TODO we could have a mix of half and full precision outputs,
777 // we really need to figure out half-precision from IR3_REG_HALF
778 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid[i]) |
779 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION : 0));
780 }
781
782 tu_cs_emit_pkt4(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
783 tu_cs_emit(cs, fs->writes_pos ? A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z : 0);
784 tu_cs_emit(cs, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count));
785
786 uint32_t gras_su_depth_plane_cntl = 0;
787 uint32_t rb_depth_plane_cntl = 0;
788 if (fs->no_earlyz | fs->writes_pos) {
789 gras_su_depth_plane_cntl |= A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
790 rb_depth_plane_cntl |= A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
791 }
792
793 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
794 tu_cs_emit(cs, gras_su_depth_plane_cntl);
795
796 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
797 tu_cs_emit(cs, rb_depth_plane_cntl);
798 }
799
800 static void
801 tu6_emit_shader_object(struct tu_cs *cs,
802 gl_shader_stage stage,
803 const struct ir3_shader_variant *variant,
804 const struct tu_bo *binary_bo,
805 uint32_t binary_offset)
806 {
807 uint16_t reg;
808 uint8_t opcode;
809 enum a6xx_state_block sb;
810 switch (stage) {
811 case MESA_SHADER_VERTEX:
812 reg = REG_A6XX_SP_VS_OBJ_START_LO;
813 opcode = CP_LOAD_STATE6_GEOM;
814 sb = SB6_VS_SHADER;
815 break;
816 case MESA_SHADER_TESS_CTRL:
817 reg = REG_A6XX_SP_HS_OBJ_START_LO;
818 opcode = CP_LOAD_STATE6_GEOM;
819 sb = SB6_HS_SHADER;
820 break;
821 case MESA_SHADER_TESS_EVAL:
822 reg = REG_A6XX_SP_DS_OBJ_START_LO;
823 opcode = CP_LOAD_STATE6_GEOM;
824 sb = SB6_DS_SHADER;
825 break;
826 case MESA_SHADER_GEOMETRY:
827 reg = REG_A6XX_SP_GS_OBJ_START_LO;
828 opcode = CP_LOAD_STATE6_GEOM;
829 sb = SB6_GS_SHADER;
830 break;
831 case MESA_SHADER_FRAGMENT:
832 reg = REG_A6XX_SP_FS_OBJ_START_LO;
833 opcode = CP_LOAD_STATE6_FRAG;
834 sb = SB6_FS_SHADER;
835 break;
836 case MESA_SHADER_COMPUTE:
837 reg = REG_A6XX_SP_CS_OBJ_START_LO;
838 opcode = CP_LOAD_STATE6_FRAG;
839 sb = SB6_CS_SHADER;
840 break;
841 default:
842 unreachable("invalid gl_shader_stage");
843 opcode = CP_LOAD_STATE6_GEOM;
844 sb = SB6_VS_SHADER;
845 break;
846 }
847
848 if (!variant->instrlen) {
849 tu_cs_emit_pkt4(cs, reg, 2);
850 tu_cs_emit_qw(cs, 0);
851 return;
852 }
853
854 assert(variant->type == stage);
855
856 const uint64_t binary_iova = binary_bo->iova + binary_offset;
857 assert((binary_iova & 0x3) == 0);
858
859 tu_cs_emit_pkt4(cs, reg, 2);
860 tu_cs_emit_qw(cs, binary_iova);
861
862 /* always indirect */
863 const bool indirect = true;
864 if (indirect) {
865 tu_cs_emit_pkt7(cs, opcode, 3);
866 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
867 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
868 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
869 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
870 CP_LOAD_STATE6_0_NUM_UNIT(variant->instrlen));
871 tu_cs_emit_qw(cs, binary_iova);
872 } else {
873 const void *binary = binary_bo->map + binary_offset;
874
875 tu_cs_emit_pkt7(cs, opcode, 3 + variant->info.sizedwords);
876 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
877 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
878 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
879 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
880 CP_LOAD_STATE6_0_NUM_UNIT(variant->instrlen));
881 tu_cs_emit_qw(cs, 0);
882 tu_cs_emit_array(cs, binary, variant->info.sizedwords);
883 }
884 }
885
886 static void
887 tu6_emit_program(struct tu_cs *cs,
888 const struct tu_pipeline_builder *builder,
889 const struct tu_bo *binary_bo,
890 bool binning_pass)
891 {
892 static const struct ir3_shader_variant dummy_variant = {
893 .type = MESA_SHADER_NONE
894 };
895 assert(builder->shaders[MESA_SHADER_VERTEX]);
896 const struct ir3_shader_variant *vs =
897 &builder->shaders[MESA_SHADER_VERTEX]->variants[0];
898 const struct ir3_shader_variant *hs =
899 builder->shaders[MESA_SHADER_TESS_CTRL]
900 ? &builder->shaders[MESA_SHADER_TESS_CTRL]->variants[0]
901 : &dummy_variant;
902 const struct ir3_shader_variant *ds =
903 builder->shaders[MESA_SHADER_TESS_EVAL]
904 ? &builder->shaders[MESA_SHADER_TESS_EVAL]->variants[0]
905 : &dummy_variant;
906 const struct ir3_shader_variant *gs =
907 builder->shaders[MESA_SHADER_GEOMETRY]
908 ? &builder->shaders[MESA_SHADER_GEOMETRY]->variants[0]
909 : &dummy_variant;
910 const struct ir3_shader_variant *fs =
911 builder->shaders[MESA_SHADER_FRAGMENT]
912 ? &builder->shaders[MESA_SHADER_FRAGMENT]->variants[0]
913 : &dummy_variant;
914
915 if (binning_pass) {
916 vs = &builder->shaders[MESA_SHADER_VERTEX]->variants[1];
917 fs = &dummy_variant;
918 }
919
920 tu6_emit_vs_config(cs, vs);
921 tu6_emit_hs_config(cs, hs);
922 tu6_emit_ds_config(cs, ds);
923 tu6_emit_gs_config(cs, gs);
924 tu6_emit_fs_config(cs, fs);
925
926 tu6_emit_vs_system_values(cs, vs);
927 tu6_emit_vpc(cs, vs, fs, binning_pass);
928 tu6_emit_vpc_varying_modes(cs, fs, binning_pass);
929 tu6_emit_fs_system_values(cs, fs);
930 tu6_emit_fs_inputs(cs, fs);
931 tu6_emit_fs_outputs(cs, fs, builder->color_attachment_count);
932
933 tu6_emit_shader_object(cs, MESA_SHADER_VERTEX, vs, binary_bo,
934 builder->shader_offsets[MESA_SHADER_VERTEX]);
935
936 tu6_emit_shader_object(cs, MESA_SHADER_FRAGMENT, fs, binary_bo,
937 builder->shader_offsets[MESA_SHADER_FRAGMENT]);
938 }
939
940 static void
941 tu6_emit_vertex_input(struct tu_cs *cs,
942 const struct ir3_shader_variant *vs,
943 const VkPipelineVertexInputStateCreateInfo *vi_info,
944 uint8_t bindings[MAX_VERTEX_ATTRIBS],
945 uint16_t strides[MAX_VERTEX_ATTRIBS],
946 uint16_t offsets[MAX_VERTEX_ATTRIBS],
947 uint32_t *count)
948 {
949 uint32_t vfd_decode_idx = 0;
950
951 /* why do we go beyond inputs_count? */
952 assert(vs->inputs_count + 1 <= MAX_VERTEX_ATTRIBS);
953 for (uint32_t i = 0; i <= vs->inputs_count; i++) {
954 if (vs->inputs[i].sysval || !vs->inputs[i].compmask)
955 continue;
956
957 const VkVertexInputAttributeDescription *vi_attr =
958 tu_find_vertex_input_attribute(vi_info, vs->inputs[i].slot);
959 const VkVertexInputBindingDescription *vi_binding =
960 tu_find_vertex_input_binding(vi_info, vi_attr);
961 assert(vi_attr && vi_binding);
962
963 const struct tu_native_format *format =
964 tu6_get_native_format(vi_attr->format);
965 assert(format && format->vtx >= 0);
966
967 uint32_t vfd_decode = A6XX_VFD_DECODE_INSTR_IDX(vfd_decode_idx) |
968 A6XX_VFD_DECODE_INSTR_FORMAT(format->vtx) |
969 A6XX_VFD_DECODE_INSTR_SWAP(format->swap) |
970 A6XX_VFD_DECODE_INSTR_UNK30;
971 if (vi_binding->inputRate == VK_VERTEX_INPUT_RATE_INSTANCE)
972 vfd_decode |= A6XX_VFD_DECODE_INSTR_INSTANCED;
973 if (!vk_format_is_int(vi_attr->format))
974 vfd_decode |= A6XX_VFD_DECODE_INSTR_FLOAT;
975
976 const uint32_t vfd_decode_step_rate = 1;
977
978 const uint32_t vfd_dest_cntl =
979 A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vs->inputs[i].compmask) |
980 A6XX_VFD_DEST_CNTL_INSTR_REGID(vs->inputs[i].regid);
981
982 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_DECODE(vfd_decode_idx), 2);
983 tu_cs_emit(cs, vfd_decode);
984 tu_cs_emit(cs, vfd_decode_step_rate);
985
986 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_DEST_CNTL(vfd_decode_idx), 1);
987 tu_cs_emit(cs, vfd_dest_cntl);
988
989 bindings[vfd_decode_idx] = vi_binding->binding;
990 strides[vfd_decode_idx] = vi_binding->stride;
991 offsets[vfd_decode_idx] = vi_attr->offset;
992
993 vfd_decode_idx++;
994 }
995
996 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_0, 1);
997 tu_cs_emit(
998 cs, A6XX_VFD_CONTROL_0_VTXCNT(vfd_decode_idx) | (vfd_decode_idx << 8));
999
1000 *count = vfd_decode_idx;
1001 }
1002
1003 static uint32_t
1004 tu6_guardband_adj(uint32_t v)
1005 {
1006 if (v > 256)
1007 return (uint32_t)(511.0 - 65.0 * (log2(v) - 8.0));
1008 else
1009 return 511;
1010 }
1011
1012 void
1013 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport)
1014 {
1015 float offsets[3];
1016 float scales[3];
1017 scales[0] = viewport->width / 2.0f;
1018 scales[1] = viewport->height / 2.0f;
1019 scales[2] = viewport->maxDepth - viewport->minDepth;
1020 offsets[0] = viewport->x + scales[0];
1021 offsets[1] = viewport->y + scales[1];
1022 offsets[2] = viewport->minDepth;
1023
1024 VkOffset2D min;
1025 VkOffset2D max;
1026 min.x = (int32_t) viewport->x;
1027 max.x = (int32_t) ceilf(viewport->x + viewport->width);
1028 if (viewport->height >= 0.0f) {
1029 min.y = (int32_t) viewport->y;
1030 max.y = (int32_t) ceilf(viewport->y + viewport->height);
1031 } else {
1032 min.y = (int32_t)(viewport->y + viewport->height);
1033 max.y = (int32_t) ceilf(viewport->y);
1034 }
1035 /* the spec allows viewport->height to be 0.0f */
1036 if (min.y == max.y)
1037 max.y++;
1038 assert(min.x >= 0 && min.x < max.x);
1039 assert(min.y >= 0 && min.y < max.y);
1040
1041 VkExtent2D guardband_adj;
1042 guardband_adj.width = tu6_guardband_adj(max.x - min.x);
1043 guardband_adj.height = tu6_guardband_adj(max.y - min.y);
1044
1045 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0, 6);
1046 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XOFFSET_0(offsets[0]));
1047 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XSCALE_0(scales[0]));
1048 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YOFFSET_0(offsets[1]));
1049 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YSCALE_0(scales[1]));
1050 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZOFFSET_0(offsets[2]));
1051 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZSCALE_0(scales[2]));
1052
1053 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
1054 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(min.x) |
1055 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(min.y));
1056 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(max.x - 1) |
1057 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(max.y - 1));
1058
1059 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
1060 tu_cs_emit(cs,
1061 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj.width) |
1062 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj.height));
1063 }
1064
1065 void
1066 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor)
1067 {
1068 const VkOffset2D min = scissor->offset;
1069 const VkOffset2D max = {
1070 scissor->offset.x + scissor->extent.width,
1071 scissor->offset.y + scissor->extent.height,
1072 };
1073
1074 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
1075 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(min.x) |
1076 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(min.y));
1077 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(max.x - 1) |
1078 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(max.y - 1));
1079 }
1080
1081 static void
1082 tu6_emit_gras_unknowns(struct tu_cs *cs)
1083 {
1084 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8000, 1);
1085 tu_cs_emit(cs, 0x80);
1086 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8001, 1);
1087 tu_cs_emit(cs, 0x0);
1088 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8004, 1);
1089 tu_cs_emit(cs, 0x0);
1090 }
1091
1092 static void
1093 tu6_emit_point_size(struct tu_cs *cs)
1094 {
1095 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POINT_MINMAX, 2);
1096 tu_cs_emit(cs, A6XX_GRAS_SU_POINT_MINMAX_MIN(1.0f / 16.0f) |
1097 A6XX_GRAS_SU_POINT_MINMAX_MAX(4092.0f));
1098 tu_cs_emit(cs, A6XX_GRAS_SU_POINT_SIZE(1.0f));
1099 }
1100
1101 static uint32_t
1102 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo *rast_info,
1103 VkSampleCountFlagBits samples)
1104 {
1105 uint32_t gras_su_cntl = 0;
1106
1107 if (rast_info->cullMode & VK_CULL_MODE_FRONT_BIT)
1108 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_FRONT;
1109 if (rast_info->cullMode & VK_CULL_MODE_BACK_BIT)
1110 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_BACK;
1111
1112 if (rast_info->frontFace == VK_FRONT_FACE_CLOCKWISE)
1113 gras_su_cntl |= A6XX_GRAS_SU_CNTL_FRONT_CW;
1114
1115 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1116
1117 if (rast_info->depthBiasEnable)
1118 gras_su_cntl |= A6XX_GRAS_SU_CNTL_POLY_OFFSET;
1119
1120 if (samples > VK_SAMPLE_COUNT_1_BIT)
1121 gras_su_cntl |= A6XX_GRAS_SU_CNTL_MSAA_ENABLE;
1122
1123 return gras_su_cntl;
1124 }
1125
1126 void
1127 tu6_emit_gras_su_cntl(struct tu_cs *cs,
1128 uint32_t gras_su_cntl,
1129 float line_width)
1130 {
1131 assert((gras_su_cntl & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK) == 0);
1132 gras_su_cntl |= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(line_width / 2.0f);
1133
1134 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_CNTL, 1);
1135 tu_cs_emit(cs, gras_su_cntl);
1136 }
1137
1138 void
1139 tu6_emit_depth_bias(struct tu_cs *cs,
1140 float constant_factor,
1141 float clamp,
1142 float slope_factor)
1143 {
1144 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
1145 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor));
1146 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor));
1147 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp));
1148 }
1149
1150 static void
1151 tu6_emit_alpha_control_disable(struct tu_cs *cs)
1152 {
1153 tu_cs_emit_pkt4(cs, REG_A6XX_RB_ALPHA_CONTROL, 1);
1154 tu_cs_emit(cs, 0);
1155 }
1156
1157 static void
1158 tu6_emit_depth_control(struct tu_cs *cs,
1159 const VkPipelineDepthStencilStateCreateInfo *ds_info)
1160 {
1161 assert(!ds_info->depthBoundsTestEnable);
1162
1163 uint32_t rb_depth_cntl = 0;
1164 if (ds_info->depthTestEnable) {
1165 rb_depth_cntl |=
1166 A6XX_RB_DEPTH_CNTL_Z_ENABLE |
1167 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) |
1168 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
1169
1170 if (ds_info->depthWriteEnable)
1171 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
1172 }
1173
1174 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_CNTL, 1);
1175 tu_cs_emit(cs, rb_depth_cntl);
1176 }
1177
1178 static void
1179 tu6_emit_stencil_control(struct tu_cs *cs,
1180 const VkPipelineDepthStencilStateCreateInfo *ds_info)
1181 {
1182 uint32_t rb_stencil_control = 0;
1183 if (ds_info->stencilTestEnable) {
1184 const VkStencilOpState *front = &ds_info->front;
1185 const VkStencilOpState *back = &ds_info->back;
1186 rb_stencil_control |=
1187 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
1188 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
1189 A6XX_RB_STENCIL_CONTROL_STENCIL_READ |
1190 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front->compareOp)) |
1191 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front->failOp)) |
1192 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front->passOp)) |
1193 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front->depthFailOp)) |
1194 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back->compareOp)) |
1195 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back->failOp)) |
1196 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back->passOp)) |
1197 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back->depthFailOp));
1198 }
1199
1200 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_CONTROL, 1);
1201 tu_cs_emit(cs, rb_stencil_control);
1202 }
1203
1204 void
1205 tu6_emit_stencil_compare_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1206 {
1207 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILMASK, 1);
1208 tu_cs_emit(
1209 cs, A6XX_RB_STENCILMASK_MASK(front) | A6XX_RB_STENCILMASK_BFMASK(back));
1210 }
1211
1212 void
1213 tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1214 {
1215 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILWRMASK, 1);
1216 tu_cs_emit(cs, A6XX_RB_STENCILWRMASK_WRMASK(front) |
1217 A6XX_RB_STENCILWRMASK_BFWRMASK(back));
1218 }
1219
1220 void
1221 tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back)
1222 {
1223 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILREF, 1);
1224 tu_cs_emit(cs,
1225 A6XX_RB_STENCILREF_REF(front) | A6XX_RB_STENCILREF_BFREF(back));
1226 }
1227
1228 static uint32_t
1229 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState *att,
1230 bool has_alpha)
1231 {
1232 const enum a3xx_rb_blend_opcode color_op = tu6_blend_op(att->colorBlendOp);
1233 const enum adreno_rb_blend_factor src_color_factor = tu6_blend_factor(
1234 has_alpha ? att->srcColorBlendFactor
1235 : tu_blend_factor_no_dst_alpha(att->srcColorBlendFactor));
1236 const enum adreno_rb_blend_factor dst_color_factor = tu6_blend_factor(
1237 has_alpha ? att->dstColorBlendFactor
1238 : tu_blend_factor_no_dst_alpha(att->dstColorBlendFactor));
1239 const enum a3xx_rb_blend_opcode alpha_op = tu6_blend_op(att->alphaBlendOp);
1240 const enum adreno_rb_blend_factor src_alpha_factor =
1241 tu6_blend_factor(att->srcAlphaBlendFactor);
1242 const enum adreno_rb_blend_factor dst_alpha_factor =
1243 tu6_blend_factor(att->dstAlphaBlendFactor);
1244
1245 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor) |
1246 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op) |
1247 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor) |
1248 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor) |
1249 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op) |
1250 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor);
1251 }
1252
1253 static uint32_t
1254 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState *att,
1255 uint32_t rb_mrt_control_rop,
1256 bool is_int,
1257 bool has_alpha)
1258 {
1259 uint32_t rb_mrt_control =
1260 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att->colorWriteMask);
1261
1262 /* ignore blending and logic op for integer attachments */
1263 if (is_int) {
1264 rb_mrt_control |= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
1265 return rb_mrt_control;
1266 }
1267
1268 rb_mrt_control |= rb_mrt_control_rop;
1269
1270 if (att->blendEnable) {
1271 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND;
1272
1273 if (has_alpha)
1274 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND2;
1275 }
1276
1277 return rb_mrt_control;
1278 }
1279
1280 static void
1281 tu6_emit_rb_mrt_controls(struct tu_cs *cs,
1282 const VkPipelineColorBlendStateCreateInfo *blend_info,
1283 const VkFormat attachment_formats[MAX_RTS],
1284 uint32_t *blend_enable_mask)
1285 {
1286 *blend_enable_mask = 0;
1287
1288 bool rop_reads_dst = false;
1289 uint32_t rb_mrt_control_rop = 0;
1290 if (blend_info->logicOpEnable) {
1291 rop_reads_dst = tu_logic_op_reads_dst(blend_info->logicOp);
1292 rb_mrt_control_rop =
1293 A6XX_RB_MRT_CONTROL_ROP_ENABLE |
1294 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info->logicOp));
1295 }
1296
1297 for (uint32_t i = 0; i < blend_info->attachmentCount; i++) {
1298 const VkPipelineColorBlendAttachmentState *att =
1299 &blend_info->pAttachments[i];
1300 const VkFormat format = attachment_formats[i];
1301
1302 uint32_t rb_mrt_control = 0;
1303 uint32_t rb_mrt_blend_control = 0;
1304 if (format != VK_FORMAT_UNDEFINED) {
1305 const bool is_int = vk_format_is_int(format);
1306 const bool has_alpha = vk_format_has_alpha(format);
1307
1308 rb_mrt_control =
1309 tu6_rb_mrt_control(att, rb_mrt_control_rop, is_int, has_alpha);
1310 rb_mrt_blend_control = tu6_rb_mrt_blend_control(att, has_alpha);
1311
1312 if (att->blendEnable || rop_reads_dst)
1313 *blend_enable_mask |= 1 << i;
1314 }
1315
1316 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
1317 tu_cs_emit(cs, rb_mrt_control);
1318 tu_cs_emit(cs, rb_mrt_blend_control);
1319 }
1320
1321 for (uint32_t i = blend_info->attachmentCount; i < MAX_RTS; i++) {
1322 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
1323 tu_cs_emit(cs, 0);
1324 tu_cs_emit(cs, 0);
1325 }
1326 }
1327
1328 static void
1329 tu6_emit_blend_control(struct tu_cs *cs,
1330 uint32_t blend_enable_mask,
1331 const VkPipelineMultisampleStateCreateInfo *msaa_info)
1332 {
1333 assert(!msaa_info->sampleShadingEnable);
1334 assert(!msaa_info->alphaToOneEnable);
1335
1336 uint32_t sp_blend_cntl = A6XX_SP_BLEND_CNTL_UNK8;
1337 if (blend_enable_mask)
1338 sp_blend_cntl |= A6XX_SP_BLEND_CNTL_ENABLED;
1339 if (msaa_info->alphaToCoverageEnable)
1340 sp_blend_cntl |= A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE;
1341
1342 const uint32_t sample_mask =
1343 msaa_info->pSampleMask ? *msaa_info->pSampleMask
1344 : ((1 << msaa_info->rasterizationSamples) - 1);
1345
1346 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
1347 uint32_t rb_blend_cntl =
1348 A6XX_RB_BLEND_CNTL_ENABLE_BLEND(blend_enable_mask) |
1349 A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND |
1350 A6XX_RB_BLEND_CNTL_SAMPLE_MASK(sample_mask);
1351 if (msaa_info->alphaToCoverageEnable)
1352 rb_blend_cntl |= A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE;
1353
1354 tu_cs_emit_pkt4(cs, REG_A6XX_SP_BLEND_CNTL, 1);
1355 tu_cs_emit(cs, sp_blend_cntl);
1356
1357 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_CNTL, 1);
1358 tu_cs_emit(cs, rb_blend_cntl);
1359 }
1360
1361 void
1362 tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4])
1363 {
1364 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_RED_F32, 4);
1365 tu_cs_emit_array(cs, (const uint32_t *) constants, 4);
1366 }
1367
1368 static VkResult
1369 tu_pipeline_builder_create_pipeline(struct tu_pipeline_builder *builder,
1370 struct tu_pipeline **out_pipeline)
1371 {
1372 struct tu_device *dev = builder->device;
1373
1374 struct tu_pipeline *pipeline =
1375 vk_zalloc2(&dev->alloc, builder->alloc, sizeof(*pipeline), 8,
1376 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1377 if (!pipeline)
1378 return VK_ERROR_OUT_OF_HOST_MEMORY;
1379
1380 tu_cs_init(&pipeline->cs, TU_CS_MODE_SUB_STREAM, 2048);
1381
1382 /* reserve the space now such that tu_cs_begin_sub_stream never fails */
1383 VkResult result = tu_cs_reserve_space(dev, &pipeline->cs, 2048);
1384 if (result != VK_SUCCESS) {
1385 vk_free2(&dev->alloc, builder->alloc, pipeline);
1386 return result;
1387 }
1388
1389 *out_pipeline = pipeline;
1390
1391 return VK_SUCCESS;
1392 }
1393
1394 static VkResult
1395 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder)
1396 {
1397 const VkPipelineShaderStageCreateInfo *stage_infos[MESA_SHADER_STAGES] = {
1398 NULL
1399 };
1400 for (uint32_t i = 0; i < builder->create_info->stageCount; i++) {
1401 gl_shader_stage stage =
1402 tu_shader_stage(builder->create_info->pStages[i].stage);
1403 stage_infos[stage] = &builder->create_info->pStages[i];
1404 }
1405
1406 struct tu_shader_compile_options options;
1407 tu_shader_compile_options_init(&options, builder->create_info);
1408
1409 /* compile shaders in reverse order */
1410 struct tu_shader *next_stage_shader = NULL;
1411 for (gl_shader_stage stage = MESA_SHADER_STAGES - 1;
1412 stage > MESA_SHADER_NONE; stage--) {
1413 const VkPipelineShaderStageCreateInfo *stage_info = stage_infos[stage];
1414 if (!stage_info)
1415 continue;
1416
1417 struct tu_shader *shader =
1418 tu_shader_create(builder->device, stage, stage_info, builder->alloc);
1419 if (!shader)
1420 return VK_ERROR_OUT_OF_HOST_MEMORY;
1421
1422 VkResult result =
1423 tu_shader_compile(builder->device, shader, next_stage_shader,
1424 &options, builder->alloc);
1425 if (result != VK_SUCCESS)
1426 return result;
1427
1428 builder->shaders[stage] = shader;
1429 builder->shader_offsets[stage] = builder->shader_total_size;
1430 builder->shader_total_size +=
1431 sizeof(uint32_t) * shader->variants[0].info.sizedwords;
1432
1433 next_stage_shader = shader;
1434 }
1435
1436 if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
1437 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1438 builder->binning_vs_offset = builder->shader_total_size;
1439 builder->shader_total_size +=
1440 sizeof(uint32_t) * vs->variants[1].info.sizedwords;
1441 }
1442
1443 return VK_SUCCESS;
1444 }
1445
1446 static VkResult
1447 tu_pipeline_builder_upload_shaders(struct tu_pipeline_builder *builder,
1448 struct tu_pipeline *pipeline)
1449 {
1450 struct tu_bo *bo = &pipeline->program.binary_bo;
1451
1452 VkResult result =
1453 tu_bo_init_new(builder->device, bo, builder->shader_total_size);
1454 if (result != VK_SUCCESS)
1455 return result;
1456
1457 result = tu_bo_map(builder->device, bo);
1458 if (result != VK_SUCCESS)
1459 return result;
1460
1461 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
1462 const struct tu_shader *shader = builder->shaders[i];
1463 if (!shader)
1464 continue;
1465
1466 memcpy(bo->map + builder->shader_offsets[i], shader->binary,
1467 sizeof(uint32_t) * shader->variants[0].info.sizedwords);
1468 }
1469
1470 if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
1471 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1472 memcpy(bo->map + builder->binning_vs_offset, vs->binning_binary,
1473 sizeof(uint32_t) * vs->variants[1].info.sizedwords);
1474 }
1475
1476 return VK_SUCCESS;
1477 }
1478
1479 static void
1480 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
1481 struct tu_pipeline *pipeline)
1482 {
1483 const VkPipelineDynamicStateCreateInfo *dynamic_info =
1484 builder->create_info->pDynamicState;
1485
1486 if (!dynamic_info)
1487 return;
1488
1489 for (uint32_t i = 0; i < dynamic_info->dynamicStateCount; i++) {
1490 pipeline->dynamic_state.mask |=
1491 tu_dynamic_state_bit(dynamic_info->pDynamicStates[i]);
1492 }
1493 }
1494
1495 static void
1496 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder *builder,
1497 struct tu_pipeline *pipeline)
1498 {
1499 struct tu_cs prog_cs;
1500 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 512, &prog_cs);
1501 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, false);
1502 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
1503
1504 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 512, &prog_cs);
1505 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, true);
1506 pipeline->program.binning_state_ib =
1507 tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
1508 }
1509
1510 static void
1511 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder *builder,
1512 struct tu_pipeline *pipeline)
1513 {
1514 const VkPipelineVertexInputStateCreateInfo *vi_info =
1515 builder->create_info->pVertexInputState;
1516 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1517
1518 struct tu_cs vi_cs;
1519 tu_cs_begin_sub_stream(builder->device, &pipeline->cs,
1520 MAX_VERTEX_ATTRIBS * 5 + 2, &vi_cs);
1521 tu6_emit_vertex_input(&vi_cs, &vs->variants[0], vi_info,
1522 pipeline->vi.bindings, pipeline->vi.strides,
1523 pipeline->vi.offsets, &pipeline->vi.count);
1524 pipeline->vi.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
1525
1526 if (vs->has_binning_pass) {
1527 tu_cs_begin_sub_stream(builder->device, &pipeline->cs,
1528 MAX_VERTEX_ATTRIBS * 5 + 2, &vi_cs);
1529 tu6_emit_vertex_input(
1530 &vi_cs, &vs->variants[1], vi_info, pipeline->vi.binning_bindings,
1531 pipeline->vi.binning_strides, pipeline->vi.binning_offsets,
1532 &pipeline->vi.binning_count);
1533 pipeline->vi.binning_state_ib =
1534 tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
1535 }
1536 }
1537
1538 static void
1539 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder *builder,
1540 struct tu_pipeline *pipeline)
1541 {
1542 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1543 builder->create_info->pInputAssemblyState;
1544
1545 pipeline->ia.primtype = tu6_primtype(ia_info->topology);
1546 pipeline->ia.primitive_restart = ia_info->primitiveRestartEnable;
1547 }
1548
1549 static void
1550 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder *builder,
1551 struct tu_pipeline *pipeline)
1552 {
1553 /* The spec says:
1554 *
1555 * pViewportState is a pointer to an instance of the
1556 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
1557 * pipeline has rasterization disabled."
1558 *
1559 * We leave the relevant registers stale in that case.
1560 */
1561 if (builder->rasterizer_discard)
1562 return;
1563
1564 const VkPipelineViewportStateCreateInfo *vp_info =
1565 builder->create_info->pViewportState;
1566
1567 struct tu_cs vp_cs;
1568 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 15, &vp_cs);
1569
1570 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_VIEWPORT)) {
1571 assert(vp_info->viewportCount == 1);
1572 tu6_emit_viewport(&vp_cs, vp_info->pViewports);
1573 }
1574
1575 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_SCISSOR)) {
1576 assert(vp_info->scissorCount == 1);
1577 tu6_emit_scissor(&vp_cs, vp_info->pScissors);
1578 }
1579
1580 pipeline->vp.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vp_cs);
1581 }
1582
1583 static void
1584 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder,
1585 struct tu_pipeline *pipeline)
1586 {
1587 const VkPipelineRasterizationStateCreateInfo *rast_info =
1588 builder->create_info->pRasterizationState;
1589
1590 assert(!rast_info->depthClampEnable);
1591 assert(rast_info->polygonMode == VK_POLYGON_MODE_FILL);
1592
1593 struct tu_cs rast_cs;
1594 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 20, &rast_cs);
1595
1596 /* move to hw ctx init? */
1597 tu6_emit_gras_unknowns(&rast_cs);
1598 tu6_emit_point_size(&rast_cs);
1599
1600 const uint32_t gras_su_cntl =
1601 tu6_gras_su_cntl(rast_info, builder->samples);
1602
1603 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH))
1604 tu6_emit_gras_su_cntl(&rast_cs, gras_su_cntl, rast_info->lineWidth);
1605
1606 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_DEPTH_BIAS)) {
1607 tu6_emit_depth_bias(&rast_cs, rast_info->depthBiasConstantFactor,
1608 rast_info->depthBiasClamp,
1609 rast_info->depthBiasSlopeFactor);
1610 }
1611
1612 pipeline->rast.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &rast_cs);
1613
1614 pipeline->rast.gras_su_cntl = gras_su_cntl;
1615 }
1616
1617 static void
1618 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
1619 struct tu_pipeline *pipeline)
1620 {
1621 /* The spec says:
1622 *
1623 * pDepthStencilState is a pointer to an instance of the
1624 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
1625 * the pipeline has rasterization disabled or if the subpass of the
1626 * render pass the pipeline is created against does not use a
1627 * depth/stencil attachment.
1628 *
1629 * We disable both depth and stenil tests in those cases.
1630 */
1631 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info;
1632 const VkPipelineDepthStencilStateCreateInfo *ds_info =
1633 builder->use_depth_stencil_attachment
1634 ? builder->create_info->pDepthStencilState
1635 : &dummy_ds_info;
1636
1637 struct tu_cs ds_cs;
1638 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 12, &ds_cs);
1639
1640 /* move to hw ctx init? */
1641 tu6_emit_alpha_control_disable(&ds_cs);
1642
1643 tu6_emit_depth_control(&ds_cs, ds_info);
1644 tu6_emit_stencil_control(&ds_cs, ds_info);
1645
1646 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
1647 tu6_emit_stencil_compare_mask(&ds_cs, ds_info->front.compareMask,
1648 ds_info->back.compareMask);
1649 }
1650 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
1651 tu6_emit_stencil_write_mask(&ds_cs, ds_info->front.writeMask,
1652 ds_info->back.writeMask);
1653 }
1654 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
1655 tu6_emit_stencil_reference(&ds_cs, ds_info->front.reference,
1656 ds_info->back.reference);
1657 }
1658
1659 pipeline->ds.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &ds_cs);
1660 }
1661
1662 static void
1663 tu_pipeline_builder_parse_multisample_and_color_blend(
1664 struct tu_pipeline_builder *builder, struct tu_pipeline *pipeline)
1665 {
1666 /* The spec says:
1667 *
1668 * pMultisampleState is a pointer to an instance of the
1669 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
1670 * has rasterization disabled.
1671 *
1672 * Also,
1673 *
1674 * pColorBlendState is a pointer to an instance of the
1675 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
1676 * pipeline has rasterization disabled or if the subpass of the render
1677 * pass the pipeline is created against does not use any color
1678 * attachments.
1679 *
1680 * We leave the relevant registers stale when rasterization is disabled.
1681 */
1682 if (builder->rasterizer_discard)
1683 return;
1684
1685 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info;
1686 const VkPipelineMultisampleStateCreateInfo *msaa_info =
1687 builder->create_info->pMultisampleState;
1688 const VkPipelineColorBlendStateCreateInfo *blend_info =
1689 builder->use_color_attachments ? builder->create_info->pColorBlendState
1690 : &dummy_blend_info;
1691
1692 struct tu_cs blend_cs;
1693 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, MAX_RTS * 3 + 9,
1694 &blend_cs);
1695
1696 uint32_t blend_enable_mask;
1697 tu6_emit_rb_mrt_controls(&blend_cs, blend_info,
1698 builder->color_attachment_formats,
1699 &blend_enable_mask);
1700
1701 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_BLEND_CONSTANTS))
1702 tu6_emit_blend_constants(&blend_cs, blend_info->blendConstants);
1703
1704 tu6_emit_blend_control(&blend_cs, blend_enable_mask, msaa_info);
1705
1706 pipeline->blend.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &blend_cs);
1707 }
1708
1709 static void
1710 tu_pipeline_finish(struct tu_pipeline *pipeline,
1711 struct tu_device *dev,
1712 const VkAllocationCallbacks *alloc)
1713 {
1714 tu_cs_finish(dev, &pipeline->cs);
1715
1716 if (pipeline->program.binary_bo.gem_handle)
1717 tu_bo_finish(dev, &pipeline->program.binary_bo);
1718 }
1719
1720 static VkResult
1721 tu_pipeline_builder_build(struct tu_pipeline_builder *builder,
1722 struct tu_pipeline **pipeline)
1723 {
1724 VkResult result = tu_pipeline_builder_create_pipeline(builder, pipeline);
1725 if (result != VK_SUCCESS)
1726 return result;
1727
1728 /* compile and upload shaders */
1729 result = tu_pipeline_builder_compile_shaders(builder);
1730 if (result == VK_SUCCESS)
1731 result = tu_pipeline_builder_upload_shaders(builder, *pipeline);
1732 if (result != VK_SUCCESS) {
1733 tu_pipeline_finish(*pipeline, builder->device, builder->alloc);
1734 vk_free2(&builder->device->alloc, builder->alloc, *pipeline);
1735 *pipeline = VK_NULL_HANDLE;
1736
1737 return result;
1738 }
1739
1740 tu_pipeline_builder_parse_dynamic(builder, *pipeline);
1741 tu_pipeline_builder_parse_shader_stages(builder, *pipeline);
1742 tu_pipeline_builder_parse_vertex_input(builder, *pipeline);
1743 tu_pipeline_builder_parse_input_assembly(builder, *pipeline);
1744 tu_pipeline_builder_parse_viewport(builder, *pipeline);
1745 tu_pipeline_builder_parse_rasterization(builder, *pipeline);
1746 tu_pipeline_builder_parse_depth_stencil(builder, *pipeline);
1747 tu_pipeline_builder_parse_multisample_and_color_blend(builder, *pipeline);
1748
1749 /* we should have reserved enough space upfront such that the CS never
1750 * grows
1751 */
1752 assert((*pipeline)->cs.bo_count == 1);
1753
1754 return VK_SUCCESS;
1755 }
1756
1757 static void
1758 tu_pipeline_builder_finish(struct tu_pipeline_builder *builder)
1759 {
1760 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
1761 if (!builder->shaders[i])
1762 continue;
1763 tu_shader_destroy(builder->device, builder->shaders[i], builder->alloc);
1764 }
1765 }
1766
1767 static void
1768 tu_pipeline_builder_init_graphics(
1769 struct tu_pipeline_builder *builder,
1770 struct tu_device *dev,
1771 struct tu_pipeline_cache *cache,
1772 const VkGraphicsPipelineCreateInfo *create_info,
1773 const VkAllocationCallbacks *alloc)
1774 {
1775 *builder = (struct tu_pipeline_builder) {
1776 .device = dev,
1777 .cache = cache,
1778 .create_info = create_info,
1779 .alloc = alloc,
1780 };
1781
1782 builder->rasterizer_discard =
1783 create_info->pRasterizationState->rasterizerDiscardEnable;
1784
1785 if (builder->rasterizer_discard) {
1786 builder->samples = VK_SAMPLE_COUNT_1_BIT;
1787 } else {
1788 builder->samples = create_info->pMultisampleState->rasterizationSamples;
1789
1790 const struct tu_render_pass *pass =
1791 tu_render_pass_from_handle(create_info->renderPass);
1792 const struct tu_subpass *subpass =
1793 &pass->subpasses[create_info->subpass];
1794
1795 builder->use_depth_stencil_attachment =
1796 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED;
1797
1798 assert(subpass->color_count ==
1799 create_info->pColorBlendState->attachmentCount);
1800 builder->color_attachment_count = subpass->color_count;
1801 for (uint32_t i = 0; i < subpass->color_count; i++) {
1802 const uint32_t a = subpass->color_attachments[i].attachment;
1803 if (a == VK_ATTACHMENT_UNUSED)
1804 continue;
1805
1806 builder->color_attachment_formats[i] = pass->attachments[a].format;
1807 builder->use_color_attachments = true;
1808 }
1809 }
1810 }
1811
1812 VkResult
1813 tu_CreateGraphicsPipelines(VkDevice device,
1814 VkPipelineCache pipelineCache,
1815 uint32_t count,
1816 const VkGraphicsPipelineCreateInfo *pCreateInfos,
1817 const VkAllocationCallbacks *pAllocator,
1818 VkPipeline *pPipelines)
1819 {
1820 TU_FROM_HANDLE(tu_device, dev, device);
1821 TU_FROM_HANDLE(tu_pipeline_cache, cache, pipelineCache);
1822
1823 for (uint32_t i = 0; i < count; i++) {
1824 struct tu_pipeline_builder builder;
1825 tu_pipeline_builder_init_graphics(&builder, dev, cache,
1826 &pCreateInfos[i], pAllocator);
1827
1828 struct tu_pipeline *pipeline;
1829 VkResult result = tu_pipeline_builder_build(&builder, &pipeline);
1830 tu_pipeline_builder_finish(&builder);
1831
1832 if (result != VK_SUCCESS) {
1833 for (uint32_t j = 0; j < i; j++) {
1834 tu_DestroyPipeline(device, pPipelines[j], pAllocator);
1835 pPipelines[j] = VK_NULL_HANDLE;
1836 }
1837
1838 return result;
1839 }
1840
1841 pPipelines[i] = tu_pipeline_to_handle(pipeline);
1842 }
1843
1844 return VK_SUCCESS;
1845 }
1846
1847 static VkResult
1848 tu_compute_pipeline_create(VkDevice _device,
1849 VkPipelineCache _cache,
1850 const VkComputePipelineCreateInfo *pCreateInfo,
1851 const VkAllocationCallbacks *pAllocator,
1852 VkPipeline *pPipeline)
1853 {
1854 return VK_SUCCESS;
1855 }
1856
1857 VkResult
1858 tu_CreateComputePipelines(VkDevice _device,
1859 VkPipelineCache pipelineCache,
1860 uint32_t count,
1861 const VkComputePipelineCreateInfo *pCreateInfos,
1862 const VkAllocationCallbacks *pAllocator,
1863 VkPipeline *pPipelines)
1864 {
1865 VkResult result = VK_SUCCESS;
1866
1867 unsigned i = 0;
1868 for (; i < count; i++) {
1869 VkResult r;
1870 r = tu_compute_pipeline_create(_device, pipelineCache, &pCreateInfos[i],
1871 pAllocator, &pPipelines[i]);
1872 if (r != VK_SUCCESS) {
1873 result = r;
1874 pPipelines[i] = VK_NULL_HANDLE;
1875 }
1876 }
1877
1878 return result;
1879 }
1880
1881 void
1882 tu_DestroyPipeline(VkDevice _device,
1883 VkPipeline _pipeline,
1884 const VkAllocationCallbacks *pAllocator)
1885 {
1886 TU_FROM_HANDLE(tu_device, dev, _device);
1887 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
1888
1889 if (!_pipeline)
1890 return;
1891
1892 tu_pipeline_finish(pipeline, dev, pAllocator);
1893 vk_free2(&dev->alloc, pAllocator, pipeline);
1894 }