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freedreno/registers: Update with GS, HS and DS registers
[mesa.git] / src / freedreno / vulkan / tu_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "main/menums.h"
31 #include "nir/nir.h"
32 #include "nir/nir_builder.h"
33 #include "spirv/nir_spirv.h"
34 #include "util/debug.h"
35 #include "util/mesa-sha1.h"
36 #include "util/u_atomic.h"
37 #include "vk_format.h"
38 #include "vk_util.h"
39
40 #include "tu_cs.h"
41
42 struct tu_pipeline_builder
43 {
44 struct tu_device *device;
45 struct tu_pipeline_cache *cache;
46 const VkAllocationCallbacks *alloc;
47 const VkGraphicsPipelineCreateInfo *create_info;
48
49 struct tu_shader *shaders[MESA_SHADER_STAGES];
50 uint32_t shader_offsets[MESA_SHADER_STAGES];
51 uint32_t binning_vs_offset;
52 uint32_t shader_total_size;
53
54 bool rasterizer_discard;
55 /* these states are affectd by rasterizer_discard */
56 VkSampleCountFlagBits samples;
57 bool use_depth_stencil_attachment;
58 bool use_color_attachments;
59 uint32_t color_attachment_count;
60 VkFormat color_attachment_formats[MAX_RTS];
61 };
62
63 static enum tu_dynamic_state_bits
64 tu_dynamic_state_bit(VkDynamicState state)
65 {
66 switch (state) {
67 case VK_DYNAMIC_STATE_VIEWPORT:
68 return TU_DYNAMIC_VIEWPORT;
69 case VK_DYNAMIC_STATE_SCISSOR:
70 return TU_DYNAMIC_SCISSOR;
71 case VK_DYNAMIC_STATE_LINE_WIDTH:
72 return TU_DYNAMIC_LINE_WIDTH;
73 case VK_DYNAMIC_STATE_DEPTH_BIAS:
74 return TU_DYNAMIC_DEPTH_BIAS;
75 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
76 return TU_DYNAMIC_BLEND_CONSTANTS;
77 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
78 return TU_DYNAMIC_DEPTH_BOUNDS;
79 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
80 return TU_DYNAMIC_STENCIL_COMPARE_MASK;
81 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
82 return TU_DYNAMIC_STENCIL_WRITE_MASK;
83 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
84 return TU_DYNAMIC_STENCIL_REFERENCE;
85 default:
86 unreachable("invalid dynamic state");
87 return 0;
88 }
89 }
90
91 static gl_shader_stage
92 tu_shader_stage(VkShaderStageFlagBits stage)
93 {
94 switch (stage) {
95 case VK_SHADER_STAGE_VERTEX_BIT:
96 return MESA_SHADER_VERTEX;
97 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
98 return MESA_SHADER_TESS_CTRL;
99 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
100 return MESA_SHADER_TESS_EVAL;
101 case VK_SHADER_STAGE_GEOMETRY_BIT:
102 return MESA_SHADER_GEOMETRY;
103 case VK_SHADER_STAGE_FRAGMENT_BIT:
104 return MESA_SHADER_FRAGMENT;
105 case VK_SHADER_STAGE_COMPUTE_BIT:
106 return MESA_SHADER_COMPUTE;
107 default:
108 unreachable("invalid VkShaderStageFlagBits");
109 return MESA_SHADER_NONE;
110 }
111 }
112
113 static const VkVertexInputAttributeDescription *
114 tu_find_vertex_input_attribute(
115 const VkPipelineVertexInputStateCreateInfo *vi_info, uint32_t slot)
116 {
117 assert(slot >= VERT_ATTRIB_GENERIC0);
118 slot -= VERT_ATTRIB_GENERIC0;
119 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
120 if (vi_info->pVertexAttributeDescriptions[i].location == slot)
121 return &vi_info->pVertexAttributeDescriptions[i];
122 }
123 return NULL;
124 }
125
126 static const VkVertexInputBindingDescription *
127 tu_find_vertex_input_binding(
128 const VkPipelineVertexInputStateCreateInfo *vi_info,
129 const VkVertexInputAttributeDescription *vi_attr)
130 {
131 assert(vi_attr);
132 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
133 if (vi_info->pVertexBindingDescriptions[i].binding == vi_attr->binding)
134 return &vi_info->pVertexBindingDescriptions[i];
135 }
136 return NULL;
137 }
138
139 static bool
140 tu_logic_op_reads_dst(VkLogicOp op)
141 {
142 switch (op) {
143 case VK_LOGIC_OP_CLEAR:
144 case VK_LOGIC_OP_COPY:
145 case VK_LOGIC_OP_COPY_INVERTED:
146 case VK_LOGIC_OP_SET:
147 return false;
148 default:
149 return true;
150 }
151 }
152
153 static VkBlendFactor
154 tu_blend_factor_no_dst_alpha(VkBlendFactor factor)
155 {
156 /* treat dst alpha as 1.0 and avoid reading it */
157 switch (factor) {
158 case VK_BLEND_FACTOR_DST_ALPHA:
159 return VK_BLEND_FACTOR_ONE;
160 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
161 return VK_BLEND_FACTOR_ZERO;
162 default:
163 return factor;
164 }
165 }
166
167 static enum pc_di_primtype
168 tu6_primtype(VkPrimitiveTopology topology)
169 {
170 switch (topology) {
171 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
172 return DI_PT_POINTLIST;
173 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
174 return DI_PT_LINELIST;
175 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
176 return DI_PT_LINESTRIP;
177 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
178 return DI_PT_TRILIST;
179 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
180 return DI_PT_TRISTRIP;
181 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
182 return DI_PT_TRIFAN;
183 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
184 return DI_PT_LINE_ADJ;
185 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
186 return DI_PT_LINESTRIP_ADJ;
187 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
188 return DI_PT_TRI_ADJ;
189 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
190 return DI_PT_TRISTRIP_ADJ;
191 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
192 default:
193 unreachable("invalid primitive topology");
194 return DI_PT_NONE;
195 }
196 }
197
198 static enum adreno_compare_func
199 tu6_compare_func(VkCompareOp op)
200 {
201 switch (op) {
202 case VK_COMPARE_OP_NEVER:
203 return FUNC_NEVER;
204 case VK_COMPARE_OP_LESS:
205 return FUNC_LESS;
206 case VK_COMPARE_OP_EQUAL:
207 return FUNC_EQUAL;
208 case VK_COMPARE_OP_LESS_OR_EQUAL:
209 return FUNC_LEQUAL;
210 case VK_COMPARE_OP_GREATER:
211 return FUNC_GREATER;
212 case VK_COMPARE_OP_NOT_EQUAL:
213 return FUNC_NOTEQUAL;
214 case VK_COMPARE_OP_GREATER_OR_EQUAL:
215 return FUNC_GEQUAL;
216 case VK_COMPARE_OP_ALWAYS:
217 return FUNC_ALWAYS;
218 default:
219 unreachable("invalid VkCompareOp");
220 return FUNC_NEVER;
221 }
222 }
223
224 static enum adreno_stencil_op
225 tu6_stencil_op(VkStencilOp op)
226 {
227 switch (op) {
228 case VK_STENCIL_OP_KEEP:
229 return STENCIL_KEEP;
230 case VK_STENCIL_OP_ZERO:
231 return STENCIL_ZERO;
232 case VK_STENCIL_OP_REPLACE:
233 return STENCIL_REPLACE;
234 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
235 return STENCIL_INCR_CLAMP;
236 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
237 return STENCIL_DECR_CLAMP;
238 case VK_STENCIL_OP_INVERT:
239 return STENCIL_INVERT;
240 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
241 return STENCIL_INCR_WRAP;
242 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
243 return STENCIL_DECR_WRAP;
244 default:
245 unreachable("invalid VkStencilOp");
246 return STENCIL_KEEP;
247 }
248 }
249
250 static enum a3xx_rop_code
251 tu6_rop(VkLogicOp op)
252 {
253 switch (op) {
254 case VK_LOGIC_OP_CLEAR:
255 return ROP_CLEAR;
256 case VK_LOGIC_OP_AND:
257 return ROP_AND;
258 case VK_LOGIC_OP_AND_REVERSE:
259 return ROP_AND_REVERSE;
260 case VK_LOGIC_OP_COPY:
261 return ROP_COPY;
262 case VK_LOGIC_OP_AND_INVERTED:
263 return ROP_AND_INVERTED;
264 case VK_LOGIC_OP_NO_OP:
265 return ROP_NOOP;
266 case VK_LOGIC_OP_XOR:
267 return ROP_XOR;
268 case VK_LOGIC_OP_OR:
269 return ROP_OR;
270 case VK_LOGIC_OP_NOR:
271 return ROP_NOR;
272 case VK_LOGIC_OP_EQUIVALENT:
273 return ROP_EQUIV;
274 case VK_LOGIC_OP_INVERT:
275 return ROP_INVERT;
276 case VK_LOGIC_OP_OR_REVERSE:
277 return ROP_OR_REVERSE;
278 case VK_LOGIC_OP_COPY_INVERTED:
279 return ROP_COPY_INVERTED;
280 case VK_LOGIC_OP_OR_INVERTED:
281 return ROP_OR_INVERTED;
282 case VK_LOGIC_OP_NAND:
283 return ROP_NAND;
284 case VK_LOGIC_OP_SET:
285 return ROP_SET;
286 default:
287 unreachable("invalid VkLogicOp");
288 return ROP_NOOP;
289 }
290 }
291
292 static enum adreno_rb_blend_factor
293 tu6_blend_factor(VkBlendFactor factor)
294 {
295 switch (factor) {
296 case VK_BLEND_FACTOR_ZERO:
297 return FACTOR_ZERO;
298 case VK_BLEND_FACTOR_ONE:
299 return FACTOR_ONE;
300 case VK_BLEND_FACTOR_SRC_COLOR:
301 return FACTOR_SRC_COLOR;
302 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
303 return FACTOR_ONE_MINUS_SRC_COLOR;
304 case VK_BLEND_FACTOR_DST_COLOR:
305 return FACTOR_DST_COLOR;
306 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
307 return FACTOR_ONE_MINUS_DST_COLOR;
308 case VK_BLEND_FACTOR_SRC_ALPHA:
309 return FACTOR_SRC_ALPHA;
310 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
311 return FACTOR_ONE_MINUS_SRC_ALPHA;
312 case VK_BLEND_FACTOR_DST_ALPHA:
313 return FACTOR_DST_ALPHA;
314 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
315 return FACTOR_ONE_MINUS_DST_ALPHA;
316 case VK_BLEND_FACTOR_CONSTANT_COLOR:
317 return FACTOR_CONSTANT_COLOR;
318 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
319 return FACTOR_ONE_MINUS_CONSTANT_COLOR;
320 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
321 return FACTOR_CONSTANT_ALPHA;
322 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
323 return FACTOR_ONE_MINUS_CONSTANT_ALPHA;
324 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
325 return FACTOR_SRC_ALPHA_SATURATE;
326 case VK_BLEND_FACTOR_SRC1_COLOR:
327 return FACTOR_SRC1_COLOR;
328 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
329 return FACTOR_ONE_MINUS_SRC1_COLOR;
330 case VK_BLEND_FACTOR_SRC1_ALPHA:
331 return FACTOR_SRC1_ALPHA;
332 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
333 return FACTOR_ONE_MINUS_SRC1_ALPHA;
334 default:
335 unreachable("invalid VkBlendFactor");
336 return FACTOR_ZERO;
337 }
338 }
339
340 static enum a3xx_rb_blend_opcode
341 tu6_blend_op(VkBlendOp op)
342 {
343 switch (op) {
344 case VK_BLEND_OP_ADD:
345 return BLEND_DST_PLUS_SRC;
346 case VK_BLEND_OP_SUBTRACT:
347 return BLEND_SRC_MINUS_DST;
348 case VK_BLEND_OP_REVERSE_SUBTRACT:
349 return BLEND_DST_MINUS_SRC;
350 case VK_BLEND_OP_MIN:
351 return BLEND_MIN_DST_SRC;
352 case VK_BLEND_OP_MAX:
353 return BLEND_MAX_DST_SRC;
354 default:
355 unreachable("invalid VkBlendOp");
356 return BLEND_DST_PLUS_SRC;
357 }
358 }
359
360 static void
361 tu6_emit_vs_config(struct tu_cs *cs, const struct ir3_shader_variant *vs)
362 {
363 uint32_t sp_vs_ctrl =
364 A6XX_SP_VS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
365 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs->info.max_reg + 1) |
366 A6XX_SP_VS_CTRL_REG0_MERGEDREGS |
367 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs->branchstack);
368 if (vs->need_pixlod)
369 sp_vs_ctrl |= A6XX_SP_VS_CTRL_REG0_PIXLODENABLE;
370
371 uint32_t sp_vs_config = A6XX_SP_VS_CONFIG_NTEX(vs->num_samp) |
372 A6XX_SP_VS_CONFIG_NSAMP(vs->num_samp);
373 if (vs->instrlen)
374 sp_vs_config |= A6XX_SP_VS_CONFIG_ENABLED;
375
376 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_CTRL_REG0, 1);
377 tu_cs_emit(cs, sp_vs_ctrl);
378
379 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_CONFIG, 2);
380 tu_cs_emit(cs, sp_vs_config);
381 tu_cs_emit(cs, vs->instrlen);
382
383 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_VS_CNTL, 1);
384 tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(vs->constlen, 4)) |
385 A6XX_HLSQ_VS_CNTL_ENABLED);
386 }
387
388 static void
389 tu6_emit_hs_config(struct tu_cs *cs, const struct ir3_shader_variant *hs)
390 {
391 uint32_t sp_hs_config = 0;
392 if (hs->instrlen)
393 sp_hs_config |= A6XX_SP_HS_CONFIG_ENABLED;
394
395 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
396 tu_cs_emit(cs, 0);
397
398 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_CONFIG, 2);
399 tu_cs_emit(cs, sp_hs_config);
400 tu_cs_emit(cs, hs->instrlen);
401
402 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_HS_CNTL, 1);
403 tu_cs_emit(cs, A6XX_HLSQ_HS_CNTL_CONSTLEN(align(hs->constlen, 4)));
404 }
405
406 static void
407 tu6_emit_ds_config(struct tu_cs *cs, const struct ir3_shader_variant *ds)
408 {
409 uint32_t sp_ds_config = 0;
410 if (ds->instrlen)
411 sp_ds_config |= A6XX_SP_DS_CONFIG_ENABLED;
412
413 tu_cs_emit_pkt4(cs, REG_A6XX_SP_DS_CONFIG, 2);
414 tu_cs_emit(cs, sp_ds_config);
415 tu_cs_emit(cs, ds->instrlen);
416
417 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_DS_CNTL, 1);
418 tu_cs_emit(cs, A6XX_HLSQ_DS_CNTL_CONSTLEN(align(ds->constlen, 4)));
419 }
420
421 static void
422 tu6_emit_gs_config(struct tu_cs *cs, const struct ir3_shader_variant *gs)
423 {
424 uint32_t sp_gs_config = 0;
425 if (gs->instrlen)
426 sp_gs_config |= A6XX_SP_GS_CONFIG_ENABLED;
427
428 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
429 tu_cs_emit(cs, 0);
430
431 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CONFIG, 2);
432 tu_cs_emit(cs, sp_gs_config);
433 tu_cs_emit(cs, gs->instrlen);
434
435 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_GS_CNTL, 1);
436 tu_cs_emit(cs, A6XX_HLSQ_GS_CNTL_CONSTLEN(align(gs->constlen, 4)));
437 }
438
439 static void
440 tu6_emit_fs_config(struct tu_cs *cs, const struct ir3_shader_variant *fs)
441 {
442 uint32_t sp_fs_ctrl =
443 A6XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) | 0x1000000 |
444 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs->info.max_reg + 1) |
445 A6XX_SP_FS_CTRL_REG0_MERGEDREGS |
446 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs->branchstack);
447 if (fs->total_in > 0 || fs->frag_coord)
448 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_VARYING;
449 if (fs->need_pixlod)
450 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_PIXLODENABLE;
451
452 uint32_t sp_fs_config = A6XX_SP_FS_CONFIG_NTEX(fs->num_samp) |
453 A6XX_SP_FS_CONFIG_NSAMP(fs->num_samp);
454 if (fs->instrlen)
455 sp_fs_config |= A6XX_SP_FS_CONFIG_ENABLED;
456
457 tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_A99E, 1);
458 tu_cs_emit(cs, 0);
459
460 tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_A9A8, 1);
461 tu_cs_emit(cs, 0);
462
463 tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_AB00, 1);
464 tu_cs_emit(cs, 0x5);
465
466 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_CTRL_REG0, 1);
467 tu_cs_emit(cs, sp_fs_ctrl);
468
469 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_CONFIG, 2);
470 tu_cs_emit(cs, sp_fs_config);
471 tu_cs_emit(cs, fs->instrlen);
472
473 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_FS_CNTL, 1);
474 tu_cs_emit(cs, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(fs->constlen, 4)) |
475 A6XX_HLSQ_FS_CNTL_ENABLED);
476 }
477
478 static void
479 tu6_emit_vs_system_values(struct tu_cs *cs,
480 const struct ir3_shader_variant *vs)
481 {
482 const uint32_t vertexid_regid =
483 ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
484 const uint32_t instanceid_regid =
485 ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
486
487 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_1, 6);
488 tu_cs_emit(cs, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid) |
489 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid) |
490 0xfcfc0000);
491 tu_cs_emit(cs, 0x0000fcfc); /* VFD_CONTROL_2 */
492 tu_cs_emit(cs, 0xfcfcfcfc); /* VFD_CONTROL_3 */
493 tu_cs_emit(cs, 0x000000fc); /* VFD_CONTROL_4 */
494 tu_cs_emit(cs, 0x0000fcfc); /* VFD_CONTROL_5 */
495 tu_cs_emit(cs, 0x00000000); /* VFD_CONTROL_6 */
496 }
497
498 static void
499 tu6_emit_vpc(struct tu_cs *cs,
500 const struct ir3_shader_variant *vs,
501 const struct ir3_shader_variant *fs,
502 bool binning_pass)
503 {
504 struct ir3_shader_linkage linkage = { 0 };
505 ir3_link_shaders(&linkage, vs, fs);
506
507 if (vs->shader->stream_output.num_outputs && !binning_pass)
508 tu_finishme("stream output");
509
510 BITSET_DECLARE(vpc_var_enables, 128) = { 0 };
511 for (uint32_t i = 0; i < linkage.cnt; i++) {
512 const uint32_t comp_count = util_last_bit(linkage.var[i].compmask);
513 for (uint32_t j = 0; j < comp_count; j++)
514 BITSET_SET(vpc_var_enables, linkage.var[i].loc + j);
515 }
516
517 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VAR_DISABLE(0), 4);
518 tu_cs_emit(cs, ~vpc_var_enables[0]);
519 tu_cs_emit(cs, ~vpc_var_enables[1]);
520 tu_cs_emit(cs, ~vpc_var_enables[2]);
521 tu_cs_emit(cs, ~vpc_var_enables[3]);
522
523 /* a6xx finds position/pointsize at the end */
524 const uint32_t position_regid =
525 ir3_find_output_regid(vs, VARYING_SLOT_POS);
526 const uint32_t pointsize_regid =
527 ir3_find_output_regid(vs, VARYING_SLOT_PSIZ);
528 uint32_t pointsize_loc = 0xff, position_loc = 0xff;
529 if (position_regid != regid(63, 0)) {
530 position_loc = linkage.max_loc;
531 ir3_link_add(&linkage, position_regid, 0xf, linkage.max_loc);
532 }
533 if (pointsize_regid != regid(63, 0)) {
534 pointsize_loc = linkage.max_loc;
535 ir3_link_add(&linkage, pointsize_regid, 0x1, linkage.max_loc);
536 }
537
538 /* map vs outputs to VPC */
539 assert(linkage.cnt <= 32);
540 const uint32_t sp_vs_out_count = (linkage.cnt + 1) / 2;
541 const uint32_t sp_vs_vpc_dst_count = (linkage.cnt + 3) / 4;
542 uint32_t sp_vs_out[16];
543 uint32_t sp_vs_vpc_dst[8];
544 sp_vs_out[sp_vs_out_count - 1] = 0;
545 sp_vs_vpc_dst[sp_vs_vpc_dst_count - 1] = 0;
546 for (uint32_t i = 0; i < linkage.cnt; i++) {
547 ((uint16_t *) sp_vs_out)[i] =
548 A6XX_SP_VS_OUT_REG_A_REGID(linkage.var[i].regid) |
549 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage.var[i].compmask);
550 ((uint8_t *) sp_vs_vpc_dst)[i] =
551 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage.var[i].loc);
552 }
553
554 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_OUT_REG(0), sp_vs_out_count);
555 tu_cs_emit_array(cs, sp_vs_out, sp_vs_out_count);
556
557 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_VPC_DST_REG(0), sp_vs_vpc_dst_count);
558 tu_cs_emit_array(cs, sp_vs_vpc_dst, sp_vs_vpc_dst_count);
559
560 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_CNTL_0, 1);
561 tu_cs_emit(cs, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs->total_in) |
562 (fs->total_in > 0 ? A6XX_VPC_CNTL_0_VARYING : 0) |
563 0xff00ff00);
564
565 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK, 1);
566 tu_cs_emit(cs, A6XX_VPC_PACK_POSITIONLOC(position_loc) |
567 A6XX_VPC_PACK_PSIZELOC(pointsize_loc) |
568 A6XX_VPC_PACK_STRIDE_IN_VPC(linkage.max_loc));
569
570 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_GS_SIV_CNTL, 1);
571 tu_cs_emit(cs, 0x0000ffff); /* XXX */
572
573 tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
574 tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage.cnt));
575
576 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
577 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage.max_loc) |
578 (vs->writes_psize ? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE : 0));
579 }
580
581 static int
582 tu6_vpc_varying_mode(const struct ir3_shader_variant *fs,
583 uint32_t index,
584 uint8_t *interp_mode,
585 uint8_t *ps_repl_mode)
586 {
587 enum
588 {
589 INTERP_SMOOTH = 0,
590 INTERP_FLAT = 1,
591 INTERP_ZERO = 2,
592 INTERP_ONE = 3,
593 };
594 enum
595 {
596 PS_REPL_NONE = 0,
597 PS_REPL_S = 1,
598 PS_REPL_T = 2,
599 PS_REPL_ONE_MINUS_T = 3,
600 };
601
602 const uint32_t compmask = fs->inputs[index].compmask;
603
604 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
605 * fourth component occupy three consecutive varying slots
606 */
607 int shift = 0;
608 *interp_mode = 0;
609 *ps_repl_mode = 0;
610 if (fs->inputs[index].slot == VARYING_SLOT_PNTC) {
611 if (compmask & 0x1) {
612 *ps_repl_mode |= PS_REPL_S << shift;
613 shift += 2;
614 }
615 if (compmask & 0x2) {
616 *ps_repl_mode |= PS_REPL_T << shift;
617 shift += 2;
618 }
619 if (compmask & 0x4) {
620 *interp_mode |= INTERP_ZERO << shift;
621 shift += 2;
622 }
623 if (compmask & 0x8) {
624 *interp_mode |= INTERP_ONE << 6;
625 shift += 2;
626 }
627 } else if ((fs->inputs[index].interpolate == INTERP_MODE_FLAT) ||
628 fs->inputs[index].rasterflat) {
629 for (int i = 0; i < 4; i++) {
630 if (compmask & (1 << i)) {
631 *interp_mode |= INTERP_FLAT << shift;
632 shift += 2;
633 }
634 }
635 }
636
637 return shift;
638 }
639
640 static void
641 tu6_emit_vpc_varying_modes(struct tu_cs *cs,
642 const struct ir3_shader_variant *fs,
643 bool binning_pass)
644 {
645 uint32_t interp_modes[8] = { 0 };
646 uint32_t ps_repl_modes[8] = { 0 };
647
648 if (!binning_pass) {
649 for (int i = -1;
650 (i = ir3_next_varying(fs, i)) < (int) fs->inputs_count;) {
651
652 /* get the mode for input i */
653 uint8_t interp_mode;
654 uint8_t ps_repl_mode;
655 const int bits =
656 tu6_vpc_varying_mode(fs, i, &interp_mode, &ps_repl_mode);
657
658 /* OR the mode into the array */
659 const uint32_t inloc = fs->inputs[i].inloc * 2;
660 uint32_t n = inloc / 32;
661 uint32_t shift = inloc % 32;
662 interp_modes[n] |= interp_mode << shift;
663 ps_repl_modes[n] |= ps_repl_mode << shift;
664 if (shift + bits > 32) {
665 n++;
666 shift = 32 - shift;
667
668 interp_modes[n] |= interp_mode >> shift;
669 ps_repl_modes[n] |= ps_repl_mode >> shift;
670 }
671 }
672 }
673
674 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
675 tu_cs_emit_array(cs, interp_modes, 8);
676
677 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
678 tu_cs_emit_array(cs, ps_repl_modes, 8);
679 }
680
681 #define VALIDREG(r) ((r) != regid(63,0))
682 #define CONDREG(r, val) COND(VALIDREG(r), (val))
683
684 static void
685 tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
686 {
687 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
688 uint32_t ij_pix_regid, ij_samp_regid, ij_cent_regid, ij_size_regid;
689 uint32_t smask_in_regid;
690
691 bool sample_shading = fs->per_samp; /* TODO | key->sample_shading; */
692 bool enable_varyings = fs->total_in > 0;
693
694 samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
695 smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
696 face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
697 coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
698 zwcoord_regid = VALIDREG(coord_regid) ? coord_regid + 2 : regid(63, 0);
699 ij_pix_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PIXEL);
700 ij_samp_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_SAMPLE);
701 ij_cent_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_CENTROID);
702 ij_size_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_SIZE);
703
704 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
705 tu_cs_emit(cs, 0x7);
706 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
707 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
708 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
709 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid));
710 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid) |
711 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid) |
712 0xfc00fc00);
713 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
714 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
715 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid) |
716 0x0000fc00);
717 tu_cs_emit(cs, 0xfc);
718
719 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
720 tu_cs_emit(cs, enable_varyings ? 3 : 1);
721
722 tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_A982, 1);
723 tu_cs_emit(cs, 0); /* XXX */
724
725 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
726 tu_cs_emit(cs, 0xff); /* XXX */
727
728 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CNTL, 1);
729 tu_cs_emit(cs,
730 CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_VARYING) |
731 CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_CENTROID) |
732 CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
733 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
734 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
735 COND(fs->frag_coord,
736 A6XX_GRAS_CNTL_SIZE |
737 A6XX_GRAS_CNTL_XCOORD |
738 A6XX_GRAS_CNTL_YCOORD |
739 A6XX_GRAS_CNTL_ZCOORD |
740 A6XX_GRAS_CNTL_WCOORD) |
741 COND(fs->frag_face, A6XX_GRAS_CNTL_SIZE));
742
743 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CONTROL0, 2);
744 tu_cs_emit(cs,
745 CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_VARYING) |
746 CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_CENTROID) |
747 CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING) |
748 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
749 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
750 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
751 COND(fs->frag_coord,
752 A6XX_RB_RENDER_CONTROL0_SIZE |
753 A6XX_RB_RENDER_CONTROL0_XCOORD |
754 A6XX_RB_RENDER_CONTROL0_YCOORD |
755 A6XX_RB_RENDER_CONTROL0_ZCOORD |
756 A6XX_RB_RENDER_CONTROL0_WCOORD) |
757 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE));
758 tu_cs_emit(cs,
759 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
760 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
761 CONDREG(ij_size_regid, A6XX_RB_RENDER_CONTROL1_SIZE) |
762 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
763 }
764
765 static void
766 tu6_emit_fs_outputs(struct tu_cs *cs,
767 const struct ir3_shader_variant *fs,
768 uint32_t mrt_count)
769 {
770 uint32_t smask_regid, posz_regid;
771
772 posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
773 smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
774
775 uint32_t fragdata_regid[8];
776 if (fs->color0_mrt) {
777 fragdata_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
778 for (uint32_t i = 1; i < ARRAY_SIZE(fragdata_regid); i++)
779 fragdata_regid[i] = fragdata_regid[0];
780 } else {
781 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++)
782 fragdata_regid[i] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0 + i);
783 }
784
785 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_CNTL0, 2);
786 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
787 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
788 0xfc000000);
789 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count));
790
791 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
792 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++) {
793 // TODO we could have a mix of half and full precision outputs,
794 // we really need to figure out half-precision from IR3_REG_HALF
795 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid[i]) |
796 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION : 0));
797 }
798
799 tu_cs_emit_pkt4(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
800 tu_cs_emit(cs, fs->writes_pos ? A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z : 0);
801 tu_cs_emit(cs, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count));
802
803 uint32_t gras_su_depth_plane_cntl = 0;
804 uint32_t rb_depth_plane_cntl = 0;
805 if (fs->no_earlyz | fs->writes_pos) {
806 gras_su_depth_plane_cntl |= A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
807 rb_depth_plane_cntl |= A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
808 }
809
810 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
811 tu_cs_emit(cs, gras_su_depth_plane_cntl);
812
813 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
814 tu_cs_emit(cs, rb_depth_plane_cntl);
815 }
816
817 static void
818 tu6_emit_shader_object(struct tu_cs *cs,
819 gl_shader_stage stage,
820 const struct ir3_shader_variant *variant,
821 const struct tu_bo *binary_bo,
822 uint32_t binary_offset)
823 {
824 uint16_t reg;
825 uint8_t opcode;
826 enum a6xx_state_block sb;
827 switch (stage) {
828 case MESA_SHADER_VERTEX:
829 reg = REG_A6XX_SP_VS_OBJ_START_LO;
830 opcode = CP_LOAD_STATE6_GEOM;
831 sb = SB6_VS_SHADER;
832 break;
833 case MESA_SHADER_TESS_CTRL:
834 reg = REG_A6XX_SP_HS_OBJ_START_LO;
835 opcode = CP_LOAD_STATE6_GEOM;
836 sb = SB6_HS_SHADER;
837 break;
838 case MESA_SHADER_TESS_EVAL:
839 reg = REG_A6XX_SP_DS_OBJ_START_LO;
840 opcode = CP_LOAD_STATE6_GEOM;
841 sb = SB6_DS_SHADER;
842 break;
843 case MESA_SHADER_GEOMETRY:
844 reg = REG_A6XX_SP_GS_OBJ_START_LO;
845 opcode = CP_LOAD_STATE6_GEOM;
846 sb = SB6_GS_SHADER;
847 break;
848 case MESA_SHADER_FRAGMENT:
849 reg = REG_A6XX_SP_FS_OBJ_START_LO;
850 opcode = CP_LOAD_STATE6_FRAG;
851 sb = SB6_FS_SHADER;
852 break;
853 case MESA_SHADER_COMPUTE:
854 reg = REG_A6XX_SP_CS_OBJ_START_LO;
855 opcode = CP_LOAD_STATE6_FRAG;
856 sb = SB6_CS_SHADER;
857 break;
858 default:
859 unreachable("invalid gl_shader_stage");
860 opcode = CP_LOAD_STATE6_GEOM;
861 sb = SB6_VS_SHADER;
862 break;
863 }
864
865 if (!variant->instrlen) {
866 tu_cs_emit_pkt4(cs, reg, 2);
867 tu_cs_emit_qw(cs, 0);
868 return;
869 }
870
871 assert(variant->type == stage);
872
873 const uint64_t binary_iova = binary_bo->iova + binary_offset;
874 assert((binary_iova & 0x3) == 0);
875
876 tu_cs_emit_pkt4(cs, reg, 2);
877 tu_cs_emit_qw(cs, binary_iova);
878
879 /* always indirect */
880 const bool indirect = true;
881 if (indirect) {
882 tu_cs_emit_pkt7(cs, opcode, 3);
883 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
884 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
885 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
886 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
887 CP_LOAD_STATE6_0_NUM_UNIT(variant->instrlen));
888 tu_cs_emit_qw(cs, binary_iova);
889 } else {
890 const void *binary = binary_bo->map + binary_offset;
891
892 tu_cs_emit_pkt7(cs, opcode, 3 + variant->info.sizedwords);
893 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
894 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
895 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
896 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
897 CP_LOAD_STATE6_0_NUM_UNIT(variant->instrlen));
898 tu_cs_emit_qw(cs, 0);
899 tu_cs_emit_array(cs, binary, variant->info.sizedwords);
900 }
901 }
902
903 static void
904 tu6_emit_immediates(struct tu_cs *cs, const struct ir3_shader_variant *v,
905 uint32_t opcode, enum a6xx_state_block block)
906 {
907 /* dummy variant */
908 if (!v->shader)
909 return;
910
911 const struct ir3_const_state *const_state = &v->shader->const_state;
912 uint32_t base = const_state->offsets.immediate;
913 int size = const_state->immediates_count;
914
915 /* truncate size to avoid writing constants that shader
916 * does not use:
917 */
918 size = MIN2(size + base, v->constlen) - base;
919
920 if (size <= 0)
921 return;
922
923 tu_cs_emit_pkt7(cs, opcode, 3 + size * 4);
924 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
925 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
926 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
927 CP_LOAD_STATE6_0_STATE_BLOCK(block) |
928 CP_LOAD_STATE6_0_NUM_UNIT(size));
929 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
930 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
931
932 for (unsigned i = 0; i < size; i++) {
933 tu_cs_emit(cs, const_state->immediates[i].val[0]);
934 tu_cs_emit(cs, const_state->immediates[i].val[1]);
935 tu_cs_emit(cs, const_state->immediates[i].val[2]);
936 tu_cs_emit(cs, const_state->immediates[i].val[3]);
937 }
938 }
939
940 static void
941 tu6_emit_program(struct tu_cs *cs,
942 const struct tu_pipeline_builder *builder,
943 const struct tu_bo *binary_bo,
944 bool binning_pass)
945 {
946 static const struct ir3_shader_variant dummy_variant = {
947 .type = MESA_SHADER_NONE
948 };
949 assert(builder->shaders[MESA_SHADER_VERTEX]);
950 const struct ir3_shader_variant *vs =
951 &builder->shaders[MESA_SHADER_VERTEX]->variants[0];
952 const struct ir3_shader_variant *hs =
953 builder->shaders[MESA_SHADER_TESS_CTRL]
954 ? &builder->shaders[MESA_SHADER_TESS_CTRL]->variants[0]
955 : &dummy_variant;
956 const struct ir3_shader_variant *ds =
957 builder->shaders[MESA_SHADER_TESS_EVAL]
958 ? &builder->shaders[MESA_SHADER_TESS_EVAL]->variants[0]
959 : &dummy_variant;
960 const struct ir3_shader_variant *gs =
961 builder->shaders[MESA_SHADER_GEOMETRY]
962 ? &builder->shaders[MESA_SHADER_GEOMETRY]->variants[0]
963 : &dummy_variant;
964 const struct ir3_shader_variant *fs =
965 builder->shaders[MESA_SHADER_FRAGMENT]
966 ? &builder->shaders[MESA_SHADER_FRAGMENT]->variants[0]
967 : &dummy_variant;
968
969 if (binning_pass) {
970 vs = &builder->shaders[MESA_SHADER_VERTEX]->variants[1];
971 fs = &dummy_variant;
972 }
973
974 tu6_emit_vs_config(cs, vs);
975 tu6_emit_hs_config(cs, hs);
976 tu6_emit_ds_config(cs, ds);
977 tu6_emit_gs_config(cs, gs);
978 tu6_emit_fs_config(cs, fs);
979
980 tu6_emit_vs_system_values(cs, vs);
981 tu6_emit_vpc(cs, vs, fs, binning_pass);
982 tu6_emit_vpc_varying_modes(cs, fs, binning_pass);
983 tu6_emit_fs_inputs(cs, fs);
984 tu6_emit_fs_outputs(cs, fs, builder->color_attachment_count);
985
986 tu6_emit_shader_object(cs, MESA_SHADER_VERTEX, vs, binary_bo,
987 builder->shader_offsets[MESA_SHADER_VERTEX]);
988
989 tu6_emit_shader_object(cs, MESA_SHADER_FRAGMENT, fs, binary_bo,
990 builder->shader_offsets[MESA_SHADER_FRAGMENT]);
991
992 tu6_emit_immediates(cs, vs, CP_LOAD_STATE6_GEOM, SB6_VS_SHADER);
993 if (!binning_pass)
994 tu6_emit_immediates(cs, fs, CP_LOAD_STATE6_FRAG, SB6_FS_SHADER);
995 }
996
997 static void
998 tu6_emit_vertex_input(struct tu_cs *cs,
999 const struct ir3_shader_variant *vs,
1000 const VkPipelineVertexInputStateCreateInfo *vi_info,
1001 uint8_t bindings[MAX_VERTEX_ATTRIBS],
1002 uint16_t strides[MAX_VERTEX_ATTRIBS],
1003 uint16_t offsets[MAX_VERTEX_ATTRIBS],
1004 uint32_t *count)
1005 {
1006 uint32_t vfd_decode_idx = 0;
1007
1008 for (uint32_t i = 0; i < vs->inputs_count; i++) {
1009 if (vs->inputs[i].sysval || !vs->inputs[i].compmask)
1010 continue;
1011
1012 const VkVertexInputAttributeDescription *vi_attr =
1013 tu_find_vertex_input_attribute(vi_info, vs->inputs[i].slot);
1014 const VkVertexInputBindingDescription *vi_binding =
1015 tu_find_vertex_input_binding(vi_info, vi_attr);
1016 assert(vi_attr && vi_binding);
1017
1018 const struct tu_native_format *format =
1019 tu6_get_native_format(vi_attr->format);
1020 assert(format && format->vtx >= 0);
1021
1022 uint32_t vfd_decode = A6XX_VFD_DECODE_INSTR_IDX(vfd_decode_idx) |
1023 A6XX_VFD_DECODE_INSTR_FORMAT(format->vtx) |
1024 A6XX_VFD_DECODE_INSTR_SWAP(format->swap) |
1025 A6XX_VFD_DECODE_INSTR_UNK30;
1026 if (vi_binding->inputRate == VK_VERTEX_INPUT_RATE_INSTANCE)
1027 vfd_decode |= A6XX_VFD_DECODE_INSTR_INSTANCED;
1028 if (!vk_format_is_int(vi_attr->format))
1029 vfd_decode |= A6XX_VFD_DECODE_INSTR_FLOAT;
1030
1031 const uint32_t vfd_decode_step_rate = 1;
1032
1033 const uint32_t vfd_dest_cntl =
1034 A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vs->inputs[i].compmask) |
1035 A6XX_VFD_DEST_CNTL_INSTR_REGID(vs->inputs[i].regid);
1036
1037 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_DECODE(vfd_decode_idx), 2);
1038 tu_cs_emit(cs, vfd_decode);
1039 tu_cs_emit(cs, vfd_decode_step_rate);
1040
1041 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_DEST_CNTL(vfd_decode_idx), 1);
1042 tu_cs_emit(cs, vfd_dest_cntl);
1043
1044 bindings[vfd_decode_idx] = vi_binding->binding;
1045 strides[vfd_decode_idx] = vi_binding->stride;
1046 offsets[vfd_decode_idx] = vi_attr->offset;
1047
1048 vfd_decode_idx++;
1049 assert(vfd_decode_idx <= MAX_VERTEX_ATTRIBS);
1050 }
1051
1052 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_0, 1);
1053 tu_cs_emit(
1054 cs, A6XX_VFD_CONTROL_0_VTXCNT(vfd_decode_idx) | (vfd_decode_idx << 8));
1055
1056 *count = vfd_decode_idx;
1057 }
1058
1059 static uint32_t
1060 tu6_guardband_adj(uint32_t v)
1061 {
1062 if (v > 256)
1063 return (uint32_t)(511.0 - 65.0 * (log2(v) - 8.0));
1064 else
1065 return 511;
1066 }
1067
1068 void
1069 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport)
1070 {
1071 float offsets[3];
1072 float scales[3];
1073 scales[0] = viewport->width / 2.0f;
1074 scales[1] = viewport->height / 2.0f;
1075 scales[2] = viewport->maxDepth - viewport->minDepth;
1076 offsets[0] = viewport->x + scales[0];
1077 offsets[1] = viewport->y + scales[1];
1078 offsets[2] = viewport->minDepth;
1079
1080 VkOffset2D min;
1081 VkOffset2D max;
1082 min.x = (int32_t) viewport->x;
1083 max.x = (int32_t) ceilf(viewport->x + viewport->width);
1084 if (viewport->height >= 0.0f) {
1085 min.y = (int32_t) viewport->y;
1086 max.y = (int32_t) ceilf(viewport->y + viewport->height);
1087 } else {
1088 min.y = (int32_t)(viewport->y + viewport->height);
1089 max.y = (int32_t) ceilf(viewport->y);
1090 }
1091 /* the spec allows viewport->height to be 0.0f */
1092 if (min.y == max.y)
1093 max.y++;
1094 assert(min.x >= 0 && min.x < max.x);
1095 assert(min.y >= 0 && min.y < max.y);
1096
1097 VkExtent2D guardband_adj;
1098 guardband_adj.width = tu6_guardband_adj(max.x - min.x);
1099 guardband_adj.height = tu6_guardband_adj(max.y - min.y);
1100
1101 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0, 6);
1102 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XOFFSET_0(offsets[0]));
1103 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XSCALE_0(scales[0]));
1104 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YOFFSET_0(offsets[1]));
1105 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YSCALE_0(scales[1]));
1106 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZOFFSET_0(offsets[2]));
1107 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZSCALE_0(scales[2]));
1108
1109 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
1110 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(min.x) |
1111 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(min.y));
1112 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(max.x - 1) |
1113 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(max.y - 1));
1114
1115 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
1116 tu_cs_emit(cs,
1117 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj.width) |
1118 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj.height));
1119 }
1120
1121 void
1122 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor)
1123 {
1124 const VkOffset2D min = scissor->offset;
1125 const VkOffset2D max = {
1126 scissor->offset.x + scissor->extent.width,
1127 scissor->offset.y + scissor->extent.height,
1128 };
1129
1130 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
1131 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(min.x) |
1132 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(min.y));
1133 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(max.x - 1) |
1134 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(max.y - 1));
1135 }
1136
1137 static void
1138 tu6_emit_gras_unknowns(struct tu_cs *cs)
1139 {
1140 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8000, 1);
1141 tu_cs_emit(cs, 0x80);
1142 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8001, 1);
1143 tu_cs_emit(cs, 0x0);
1144 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LAYER_CNTL, 1);
1145 tu_cs_emit(cs, 0x0);
1146 }
1147
1148 static void
1149 tu6_emit_point_size(struct tu_cs *cs)
1150 {
1151 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POINT_MINMAX, 2);
1152 tu_cs_emit(cs, A6XX_GRAS_SU_POINT_MINMAX_MIN(1.0f / 16.0f) |
1153 A6XX_GRAS_SU_POINT_MINMAX_MAX(4092.0f));
1154 tu_cs_emit(cs, A6XX_GRAS_SU_POINT_SIZE(1.0f));
1155 }
1156
1157 static uint32_t
1158 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo *rast_info,
1159 VkSampleCountFlagBits samples)
1160 {
1161 uint32_t gras_su_cntl = 0;
1162
1163 if (rast_info->cullMode & VK_CULL_MODE_FRONT_BIT)
1164 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_FRONT;
1165 if (rast_info->cullMode & VK_CULL_MODE_BACK_BIT)
1166 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_BACK;
1167
1168 if (rast_info->frontFace == VK_FRONT_FACE_CLOCKWISE)
1169 gras_su_cntl |= A6XX_GRAS_SU_CNTL_FRONT_CW;
1170
1171 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1172
1173 if (rast_info->depthBiasEnable)
1174 gras_su_cntl |= A6XX_GRAS_SU_CNTL_POLY_OFFSET;
1175
1176 if (samples > VK_SAMPLE_COUNT_1_BIT)
1177 gras_su_cntl |= A6XX_GRAS_SU_CNTL_MSAA_ENABLE;
1178
1179 return gras_su_cntl;
1180 }
1181
1182 void
1183 tu6_emit_gras_su_cntl(struct tu_cs *cs,
1184 uint32_t gras_su_cntl,
1185 float line_width)
1186 {
1187 assert((gras_su_cntl & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK) == 0);
1188 gras_su_cntl |= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(line_width / 2.0f);
1189
1190 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_CNTL, 1);
1191 tu_cs_emit(cs, gras_su_cntl);
1192 }
1193
1194 void
1195 tu6_emit_depth_bias(struct tu_cs *cs,
1196 float constant_factor,
1197 float clamp,
1198 float slope_factor)
1199 {
1200 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
1201 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor));
1202 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor));
1203 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp));
1204 }
1205
1206 static void
1207 tu6_emit_alpha_control_disable(struct tu_cs *cs)
1208 {
1209 tu_cs_emit_pkt4(cs, REG_A6XX_RB_ALPHA_CONTROL, 1);
1210 tu_cs_emit(cs, 0);
1211 }
1212
1213 static void
1214 tu6_emit_depth_control(struct tu_cs *cs,
1215 const VkPipelineDepthStencilStateCreateInfo *ds_info)
1216 {
1217 assert(!ds_info->depthBoundsTestEnable);
1218
1219 uint32_t rb_depth_cntl = 0;
1220 if (ds_info->depthTestEnable) {
1221 rb_depth_cntl |=
1222 A6XX_RB_DEPTH_CNTL_Z_ENABLE |
1223 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) |
1224 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
1225
1226 if (ds_info->depthWriteEnable)
1227 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
1228 }
1229
1230 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_CNTL, 1);
1231 tu_cs_emit(cs, rb_depth_cntl);
1232 }
1233
1234 static void
1235 tu6_emit_stencil_control(struct tu_cs *cs,
1236 const VkPipelineDepthStencilStateCreateInfo *ds_info)
1237 {
1238 uint32_t rb_stencil_control = 0;
1239 if (ds_info->stencilTestEnable) {
1240 const VkStencilOpState *front = &ds_info->front;
1241 const VkStencilOpState *back = &ds_info->back;
1242 rb_stencil_control |=
1243 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
1244 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
1245 A6XX_RB_STENCIL_CONTROL_STENCIL_READ |
1246 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front->compareOp)) |
1247 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front->failOp)) |
1248 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front->passOp)) |
1249 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front->depthFailOp)) |
1250 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back->compareOp)) |
1251 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back->failOp)) |
1252 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back->passOp)) |
1253 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back->depthFailOp));
1254 }
1255
1256 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_CONTROL, 1);
1257 tu_cs_emit(cs, rb_stencil_control);
1258 }
1259
1260 void
1261 tu6_emit_stencil_compare_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1262 {
1263 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILMASK, 1);
1264 tu_cs_emit(
1265 cs, A6XX_RB_STENCILMASK_MASK(front) | A6XX_RB_STENCILMASK_BFMASK(back));
1266 }
1267
1268 void
1269 tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1270 {
1271 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILWRMASK, 1);
1272 tu_cs_emit(cs, A6XX_RB_STENCILWRMASK_WRMASK(front) |
1273 A6XX_RB_STENCILWRMASK_BFWRMASK(back));
1274 }
1275
1276 void
1277 tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back)
1278 {
1279 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILREF, 1);
1280 tu_cs_emit(cs,
1281 A6XX_RB_STENCILREF_REF(front) | A6XX_RB_STENCILREF_BFREF(back));
1282 }
1283
1284 static uint32_t
1285 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState *att,
1286 bool has_alpha)
1287 {
1288 const enum a3xx_rb_blend_opcode color_op = tu6_blend_op(att->colorBlendOp);
1289 const enum adreno_rb_blend_factor src_color_factor = tu6_blend_factor(
1290 has_alpha ? att->srcColorBlendFactor
1291 : tu_blend_factor_no_dst_alpha(att->srcColorBlendFactor));
1292 const enum adreno_rb_blend_factor dst_color_factor = tu6_blend_factor(
1293 has_alpha ? att->dstColorBlendFactor
1294 : tu_blend_factor_no_dst_alpha(att->dstColorBlendFactor));
1295 const enum a3xx_rb_blend_opcode alpha_op = tu6_blend_op(att->alphaBlendOp);
1296 const enum adreno_rb_blend_factor src_alpha_factor =
1297 tu6_blend_factor(att->srcAlphaBlendFactor);
1298 const enum adreno_rb_blend_factor dst_alpha_factor =
1299 tu6_blend_factor(att->dstAlphaBlendFactor);
1300
1301 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor) |
1302 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op) |
1303 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor) |
1304 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor) |
1305 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op) |
1306 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor);
1307 }
1308
1309 static uint32_t
1310 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState *att,
1311 uint32_t rb_mrt_control_rop,
1312 bool is_int,
1313 bool has_alpha)
1314 {
1315 uint32_t rb_mrt_control =
1316 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att->colorWriteMask);
1317
1318 /* ignore blending and logic op for integer attachments */
1319 if (is_int) {
1320 rb_mrt_control |= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
1321 return rb_mrt_control;
1322 }
1323
1324 rb_mrt_control |= rb_mrt_control_rop;
1325
1326 if (att->blendEnable) {
1327 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND;
1328
1329 if (has_alpha)
1330 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND2;
1331 }
1332
1333 return rb_mrt_control;
1334 }
1335
1336 static void
1337 tu6_emit_rb_mrt_controls(struct tu_cs *cs,
1338 const VkPipelineColorBlendStateCreateInfo *blend_info,
1339 const VkFormat attachment_formats[MAX_RTS],
1340 uint32_t *blend_enable_mask)
1341 {
1342 *blend_enable_mask = 0;
1343
1344 bool rop_reads_dst = false;
1345 uint32_t rb_mrt_control_rop = 0;
1346 if (blend_info->logicOpEnable) {
1347 rop_reads_dst = tu_logic_op_reads_dst(blend_info->logicOp);
1348 rb_mrt_control_rop =
1349 A6XX_RB_MRT_CONTROL_ROP_ENABLE |
1350 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info->logicOp));
1351 }
1352
1353 for (uint32_t i = 0; i < blend_info->attachmentCount; i++) {
1354 const VkPipelineColorBlendAttachmentState *att =
1355 &blend_info->pAttachments[i];
1356 const VkFormat format = attachment_formats[i];
1357
1358 uint32_t rb_mrt_control = 0;
1359 uint32_t rb_mrt_blend_control = 0;
1360 if (format != VK_FORMAT_UNDEFINED) {
1361 const bool is_int = vk_format_is_int(format);
1362 const bool has_alpha = vk_format_has_alpha(format);
1363
1364 rb_mrt_control =
1365 tu6_rb_mrt_control(att, rb_mrt_control_rop, is_int, has_alpha);
1366 rb_mrt_blend_control = tu6_rb_mrt_blend_control(att, has_alpha);
1367
1368 if (att->blendEnable || rop_reads_dst)
1369 *blend_enable_mask |= 1 << i;
1370 }
1371
1372 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
1373 tu_cs_emit(cs, rb_mrt_control);
1374 tu_cs_emit(cs, rb_mrt_blend_control);
1375 }
1376
1377 for (uint32_t i = blend_info->attachmentCount; i < MAX_RTS; i++) {
1378 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
1379 tu_cs_emit(cs, 0);
1380 tu_cs_emit(cs, 0);
1381 }
1382 }
1383
1384 static void
1385 tu6_emit_blend_control(struct tu_cs *cs,
1386 uint32_t blend_enable_mask,
1387 const VkPipelineMultisampleStateCreateInfo *msaa_info)
1388 {
1389 assert(!msaa_info->sampleShadingEnable);
1390 assert(!msaa_info->alphaToOneEnable);
1391
1392 uint32_t sp_blend_cntl = A6XX_SP_BLEND_CNTL_UNK8;
1393 if (blend_enable_mask)
1394 sp_blend_cntl |= A6XX_SP_BLEND_CNTL_ENABLED;
1395 if (msaa_info->alphaToCoverageEnable)
1396 sp_blend_cntl |= A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE;
1397
1398 const uint32_t sample_mask =
1399 msaa_info->pSampleMask ? *msaa_info->pSampleMask
1400 : ((1 << msaa_info->rasterizationSamples) - 1);
1401
1402 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
1403 uint32_t rb_blend_cntl =
1404 A6XX_RB_BLEND_CNTL_ENABLE_BLEND(blend_enable_mask) |
1405 A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND |
1406 A6XX_RB_BLEND_CNTL_SAMPLE_MASK(sample_mask);
1407 if (msaa_info->alphaToCoverageEnable)
1408 rb_blend_cntl |= A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE;
1409
1410 tu_cs_emit_pkt4(cs, REG_A6XX_SP_BLEND_CNTL, 1);
1411 tu_cs_emit(cs, sp_blend_cntl);
1412
1413 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_CNTL, 1);
1414 tu_cs_emit(cs, rb_blend_cntl);
1415 }
1416
1417 void
1418 tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4])
1419 {
1420 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_RED_F32, 4);
1421 tu_cs_emit_array(cs, (const uint32_t *) constants, 4);
1422 }
1423
1424 static VkResult
1425 tu_pipeline_builder_create_pipeline(struct tu_pipeline_builder *builder,
1426 struct tu_pipeline **out_pipeline)
1427 {
1428 struct tu_device *dev = builder->device;
1429
1430 struct tu_pipeline *pipeline =
1431 vk_zalloc2(&dev->alloc, builder->alloc, sizeof(*pipeline), 8,
1432 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1433 if (!pipeline)
1434 return VK_ERROR_OUT_OF_HOST_MEMORY;
1435
1436 tu_cs_init(&pipeline->cs, TU_CS_MODE_SUB_STREAM, 2048);
1437
1438 /* reserve the space now such that tu_cs_begin_sub_stream never fails */
1439 VkResult result = tu_cs_reserve_space(dev, &pipeline->cs, 2048);
1440 if (result != VK_SUCCESS) {
1441 vk_free2(&dev->alloc, builder->alloc, pipeline);
1442 return result;
1443 }
1444
1445 *out_pipeline = pipeline;
1446
1447 return VK_SUCCESS;
1448 }
1449
1450 static VkResult
1451 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder)
1452 {
1453 const VkPipelineShaderStageCreateInfo *stage_infos[MESA_SHADER_STAGES] = {
1454 NULL
1455 };
1456 for (uint32_t i = 0; i < builder->create_info->stageCount; i++) {
1457 gl_shader_stage stage =
1458 tu_shader_stage(builder->create_info->pStages[i].stage);
1459 stage_infos[stage] = &builder->create_info->pStages[i];
1460 }
1461
1462 struct tu_shader_compile_options options;
1463 tu_shader_compile_options_init(&options, builder->create_info);
1464
1465 /* compile shaders in reverse order */
1466 struct tu_shader *next_stage_shader = NULL;
1467 for (gl_shader_stage stage = MESA_SHADER_STAGES - 1;
1468 stage > MESA_SHADER_NONE; stage--) {
1469 const VkPipelineShaderStageCreateInfo *stage_info = stage_infos[stage];
1470 if (!stage_info)
1471 continue;
1472
1473 struct tu_shader *shader =
1474 tu_shader_create(builder->device, stage, stage_info, builder->alloc);
1475 if (!shader)
1476 return VK_ERROR_OUT_OF_HOST_MEMORY;
1477
1478 VkResult result =
1479 tu_shader_compile(builder->device, shader, next_stage_shader,
1480 &options, builder->alloc);
1481 if (result != VK_SUCCESS)
1482 return result;
1483
1484 builder->shaders[stage] = shader;
1485 builder->shader_offsets[stage] = builder->shader_total_size;
1486 builder->shader_total_size +=
1487 sizeof(uint32_t) * shader->variants[0].info.sizedwords;
1488
1489 next_stage_shader = shader;
1490 }
1491
1492 if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
1493 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1494 builder->binning_vs_offset = builder->shader_total_size;
1495 builder->shader_total_size +=
1496 sizeof(uint32_t) * vs->variants[1].info.sizedwords;
1497 }
1498
1499 return VK_SUCCESS;
1500 }
1501
1502 static VkResult
1503 tu_pipeline_builder_upload_shaders(struct tu_pipeline_builder *builder,
1504 struct tu_pipeline *pipeline)
1505 {
1506 struct tu_bo *bo = &pipeline->program.binary_bo;
1507
1508 VkResult result =
1509 tu_bo_init_new(builder->device, bo, builder->shader_total_size);
1510 if (result != VK_SUCCESS)
1511 return result;
1512
1513 result = tu_bo_map(builder->device, bo);
1514 if (result != VK_SUCCESS)
1515 return result;
1516
1517 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
1518 const struct tu_shader *shader = builder->shaders[i];
1519 if (!shader)
1520 continue;
1521
1522 memcpy(bo->map + builder->shader_offsets[i], shader->binary,
1523 sizeof(uint32_t) * shader->variants[0].info.sizedwords);
1524 }
1525
1526 if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
1527 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1528 memcpy(bo->map + builder->binning_vs_offset, vs->binning_binary,
1529 sizeof(uint32_t) * vs->variants[1].info.sizedwords);
1530 }
1531
1532 return VK_SUCCESS;
1533 }
1534
1535 static void
1536 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
1537 struct tu_pipeline *pipeline)
1538 {
1539 const VkPipelineDynamicStateCreateInfo *dynamic_info =
1540 builder->create_info->pDynamicState;
1541
1542 if (!dynamic_info)
1543 return;
1544
1545 for (uint32_t i = 0; i < dynamic_info->dynamicStateCount; i++) {
1546 pipeline->dynamic_state.mask |=
1547 tu_dynamic_state_bit(dynamic_info->pDynamicStates[i]);
1548 }
1549 }
1550
1551 static void
1552 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder *builder,
1553 struct tu_pipeline *pipeline)
1554 {
1555 struct tu_cs prog_cs;
1556 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 512, &prog_cs);
1557 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, false);
1558 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
1559
1560 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 512, &prog_cs);
1561 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, true);
1562 pipeline->program.binning_state_ib =
1563 tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
1564
1565 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
1566 if (!builder->shaders[i])
1567 continue;
1568
1569 struct tu_program_descriptor_linkage *link = &pipeline->program.link[i];
1570 struct ir3_shader *shader = builder->shaders[i]->variants[0].shader;
1571
1572 link->ubo_state = shader->ubo_state;
1573 link->const_state = shader->const_state;
1574 link->constlen = builder->shaders[i]->variants[0].constlen;
1575 link->texture_map = builder->shaders[i]->texture_map;
1576 link->sampler_map = builder->shaders[i]->sampler_map;
1577 link->ubo_map = builder->shaders[i]->ubo_map;
1578 link->ssbo_map = builder->shaders[i]->ssbo_map;
1579 link->image_mapping = builder->shaders[i]->variants[0].image_mapping;
1580 }
1581 }
1582
1583 static void
1584 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder *builder,
1585 struct tu_pipeline *pipeline)
1586 {
1587 const VkPipelineVertexInputStateCreateInfo *vi_info =
1588 builder->create_info->pVertexInputState;
1589 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1590
1591 struct tu_cs vi_cs;
1592 tu_cs_begin_sub_stream(builder->device, &pipeline->cs,
1593 MAX_VERTEX_ATTRIBS * 5 + 2, &vi_cs);
1594 tu6_emit_vertex_input(&vi_cs, &vs->variants[0], vi_info,
1595 pipeline->vi.bindings, pipeline->vi.strides,
1596 pipeline->vi.offsets, &pipeline->vi.count);
1597 pipeline->vi.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
1598
1599 if (vs->has_binning_pass) {
1600 tu_cs_begin_sub_stream(builder->device, &pipeline->cs,
1601 MAX_VERTEX_ATTRIBS * 5 + 2, &vi_cs);
1602 tu6_emit_vertex_input(
1603 &vi_cs, &vs->variants[1], vi_info, pipeline->vi.binning_bindings,
1604 pipeline->vi.binning_strides, pipeline->vi.binning_offsets,
1605 &pipeline->vi.binning_count);
1606 pipeline->vi.binning_state_ib =
1607 tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
1608 }
1609 }
1610
1611 static void
1612 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder *builder,
1613 struct tu_pipeline *pipeline)
1614 {
1615 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1616 builder->create_info->pInputAssemblyState;
1617
1618 pipeline->ia.primtype = tu6_primtype(ia_info->topology);
1619 pipeline->ia.primitive_restart = ia_info->primitiveRestartEnable;
1620 }
1621
1622 static void
1623 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder *builder,
1624 struct tu_pipeline *pipeline)
1625 {
1626 /* The spec says:
1627 *
1628 * pViewportState is a pointer to an instance of the
1629 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
1630 * pipeline has rasterization disabled."
1631 *
1632 * We leave the relevant registers stale in that case.
1633 */
1634 if (builder->rasterizer_discard)
1635 return;
1636
1637 const VkPipelineViewportStateCreateInfo *vp_info =
1638 builder->create_info->pViewportState;
1639
1640 struct tu_cs vp_cs;
1641 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 15, &vp_cs);
1642
1643 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_VIEWPORT)) {
1644 assert(vp_info->viewportCount == 1);
1645 tu6_emit_viewport(&vp_cs, vp_info->pViewports);
1646 }
1647
1648 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_SCISSOR)) {
1649 assert(vp_info->scissorCount == 1);
1650 tu6_emit_scissor(&vp_cs, vp_info->pScissors);
1651 }
1652
1653 pipeline->vp.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vp_cs);
1654 }
1655
1656 static void
1657 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder,
1658 struct tu_pipeline *pipeline)
1659 {
1660 const VkPipelineRasterizationStateCreateInfo *rast_info =
1661 builder->create_info->pRasterizationState;
1662
1663 assert(!rast_info->depthClampEnable);
1664 assert(rast_info->polygonMode == VK_POLYGON_MODE_FILL);
1665
1666 struct tu_cs rast_cs;
1667 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 20, &rast_cs);
1668
1669 /* move to hw ctx init? */
1670 tu6_emit_gras_unknowns(&rast_cs);
1671 tu6_emit_point_size(&rast_cs);
1672
1673 const uint32_t gras_su_cntl =
1674 tu6_gras_su_cntl(rast_info, builder->samples);
1675
1676 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH))
1677 tu6_emit_gras_su_cntl(&rast_cs, gras_su_cntl, rast_info->lineWidth);
1678
1679 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_DEPTH_BIAS)) {
1680 tu6_emit_depth_bias(&rast_cs, rast_info->depthBiasConstantFactor,
1681 rast_info->depthBiasClamp,
1682 rast_info->depthBiasSlopeFactor);
1683 }
1684
1685 pipeline->rast.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &rast_cs);
1686
1687 pipeline->rast.gras_su_cntl = gras_su_cntl;
1688 }
1689
1690 static void
1691 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
1692 struct tu_pipeline *pipeline)
1693 {
1694 /* The spec says:
1695 *
1696 * pDepthStencilState is a pointer to an instance of the
1697 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
1698 * the pipeline has rasterization disabled or if the subpass of the
1699 * render pass the pipeline is created against does not use a
1700 * depth/stencil attachment.
1701 *
1702 * We disable both depth and stenil tests in those cases.
1703 */
1704 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info;
1705 const VkPipelineDepthStencilStateCreateInfo *ds_info =
1706 builder->use_depth_stencil_attachment
1707 ? builder->create_info->pDepthStencilState
1708 : &dummy_ds_info;
1709
1710 struct tu_cs ds_cs;
1711 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 12, &ds_cs);
1712
1713 /* move to hw ctx init? */
1714 tu6_emit_alpha_control_disable(&ds_cs);
1715
1716 tu6_emit_depth_control(&ds_cs, ds_info);
1717 tu6_emit_stencil_control(&ds_cs, ds_info);
1718
1719 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
1720 tu6_emit_stencil_compare_mask(&ds_cs, ds_info->front.compareMask,
1721 ds_info->back.compareMask);
1722 }
1723 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
1724 tu6_emit_stencil_write_mask(&ds_cs, ds_info->front.writeMask,
1725 ds_info->back.writeMask);
1726 }
1727 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
1728 tu6_emit_stencil_reference(&ds_cs, ds_info->front.reference,
1729 ds_info->back.reference);
1730 }
1731
1732 pipeline->ds.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &ds_cs);
1733 }
1734
1735 static void
1736 tu_pipeline_builder_parse_multisample_and_color_blend(
1737 struct tu_pipeline_builder *builder, struct tu_pipeline *pipeline)
1738 {
1739 /* The spec says:
1740 *
1741 * pMultisampleState is a pointer to an instance of the
1742 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
1743 * has rasterization disabled.
1744 *
1745 * Also,
1746 *
1747 * pColorBlendState is a pointer to an instance of the
1748 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
1749 * pipeline has rasterization disabled or if the subpass of the render
1750 * pass the pipeline is created against does not use any color
1751 * attachments.
1752 *
1753 * We leave the relevant registers stale when rasterization is disabled.
1754 */
1755 if (builder->rasterizer_discard)
1756 return;
1757
1758 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info;
1759 const VkPipelineMultisampleStateCreateInfo *msaa_info =
1760 builder->create_info->pMultisampleState;
1761 const VkPipelineColorBlendStateCreateInfo *blend_info =
1762 builder->use_color_attachments ? builder->create_info->pColorBlendState
1763 : &dummy_blend_info;
1764
1765 struct tu_cs blend_cs;
1766 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, MAX_RTS * 3 + 9,
1767 &blend_cs);
1768
1769 uint32_t blend_enable_mask;
1770 tu6_emit_rb_mrt_controls(&blend_cs, blend_info,
1771 builder->color_attachment_formats,
1772 &blend_enable_mask);
1773
1774 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_BLEND_CONSTANTS))
1775 tu6_emit_blend_constants(&blend_cs, blend_info->blendConstants);
1776
1777 tu6_emit_blend_control(&blend_cs, blend_enable_mask, msaa_info);
1778
1779 pipeline->blend.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &blend_cs);
1780 }
1781
1782 static void
1783 tu_pipeline_finish(struct tu_pipeline *pipeline,
1784 struct tu_device *dev,
1785 const VkAllocationCallbacks *alloc)
1786 {
1787 tu_cs_finish(dev, &pipeline->cs);
1788
1789 if (pipeline->program.binary_bo.gem_handle)
1790 tu_bo_finish(dev, &pipeline->program.binary_bo);
1791 }
1792
1793 static VkResult
1794 tu_pipeline_builder_build(struct tu_pipeline_builder *builder,
1795 struct tu_pipeline **pipeline)
1796 {
1797 VkResult result = tu_pipeline_builder_create_pipeline(builder, pipeline);
1798 if (result != VK_SUCCESS)
1799 return result;
1800
1801 /* compile and upload shaders */
1802 result = tu_pipeline_builder_compile_shaders(builder);
1803 if (result == VK_SUCCESS)
1804 result = tu_pipeline_builder_upload_shaders(builder, *pipeline);
1805 if (result != VK_SUCCESS) {
1806 tu_pipeline_finish(*pipeline, builder->device, builder->alloc);
1807 vk_free2(&builder->device->alloc, builder->alloc, *pipeline);
1808 *pipeline = VK_NULL_HANDLE;
1809
1810 return result;
1811 }
1812
1813 tu_pipeline_builder_parse_dynamic(builder, *pipeline);
1814 tu_pipeline_builder_parse_shader_stages(builder, *pipeline);
1815 tu_pipeline_builder_parse_vertex_input(builder, *pipeline);
1816 tu_pipeline_builder_parse_input_assembly(builder, *pipeline);
1817 tu_pipeline_builder_parse_viewport(builder, *pipeline);
1818 tu_pipeline_builder_parse_rasterization(builder, *pipeline);
1819 tu_pipeline_builder_parse_depth_stencil(builder, *pipeline);
1820 tu_pipeline_builder_parse_multisample_and_color_blend(builder, *pipeline);
1821
1822 /* we should have reserved enough space upfront such that the CS never
1823 * grows
1824 */
1825 assert((*pipeline)->cs.bo_count == 1);
1826
1827 return VK_SUCCESS;
1828 }
1829
1830 static void
1831 tu_pipeline_builder_finish(struct tu_pipeline_builder *builder)
1832 {
1833 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
1834 if (!builder->shaders[i])
1835 continue;
1836 tu_shader_destroy(builder->device, builder->shaders[i], builder->alloc);
1837 }
1838 }
1839
1840 static void
1841 tu_pipeline_builder_init_graphics(
1842 struct tu_pipeline_builder *builder,
1843 struct tu_device *dev,
1844 struct tu_pipeline_cache *cache,
1845 const VkGraphicsPipelineCreateInfo *create_info,
1846 const VkAllocationCallbacks *alloc)
1847 {
1848 *builder = (struct tu_pipeline_builder) {
1849 .device = dev,
1850 .cache = cache,
1851 .create_info = create_info,
1852 .alloc = alloc,
1853 };
1854
1855 builder->rasterizer_discard =
1856 create_info->pRasterizationState->rasterizerDiscardEnable;
1857
1858 if (builder->rasterizer_discard) {
1859 builder->samples = VK_SAMPLE_COUNT_1_BIT;
1860 } else {
1861 builder->samples = create_info->pMultisampleState->rasterizationSamples;
1862
1863 const struct tu_render_pass *pass =
1864 tu_render_pass_from_handle(create_info->renderPass);
1865 const struct tu_subpass *subpass =
1866 &pass->subpasses[create_info->subpass];
1867
1868 builder->use_depth_stencil_attachment =
1869 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED;
1870
1871 assert(subpass->color_count == 0 ||
1872 subpass->color_count == create_info->pColorBlendState->attachmentCount);
1873 builder->color_attachment_count = subpass->color_count;
1874 for (uint32_t i = 0; i < subpass->color_count; i++) {
1875 const uint32_t a = subpass->color_attachments[i].attachment;
1876 if (a == VK_ATTACHMENT_UNUSED)
1877 continue;
1878
1879 builder->color_attachment_formats[i] = pass->attachments[a].format;
1880 builder->use_color_attachments = true;
1881 }
1882 }
1883 }
1884
1885 VkResult
1886 tu_CreateGraphicsPipelines(VkDevice device,
1887 VkPipelineCache pipelineCache,
1888 uint32_t count,
1889 const VkGraphicsPipelineCreateInfo *pCreateInfos,
1890 const VkAllocationCallbacks *pAllocator,
1891 VkPipeline *pPipelines)
1892 {
1893 TU_FROM_HANDLE(tu_device, dev, device);
1894 TU_FROM_HANDLE(tu_pipeline_cache, cache, pipelineCache);
1895 VkResult final_result = VK_SUCCESS;
1896
1897 for (uint32_t i = 0; i < count; i++) {
1898 struct tu_pipeline_builder builder;
1899 tu_pipeline_builder_init_graphics(&builder, dev, cache,
1900 &pCreateInfos[i], pAllocator);
1901
1902 struct tu_pipeline *pipeline = NULL;
1903 VkResult result = tu_pipeline_builder_build(&builder, &pipeline);
1904 tu_pipeline_builder_finish(&builder);
1905
1906 if (result == VK_SUCCESS) {
1907 pPipelines[i] = tu_pipeline_to_handle(pipeline);
1908 } else {
1909 pPipelines[i] = NULL;
1910 final_result = result;
1911 }
1912 }
1913
1914 return final_result;
1915 }
1916
1917 static VkResult
1918 tu_compute_pipeline_create(VkDevice _device,
1919 VkPipelineCache _cache,
1920 const VkComputePipelineCreateInfo *pCreateInfo,
1921 const VkAllocationCallbacks *pAllocator,
1922 VkPipeline *pPipeline)
1923 {
1924 return VK_SUCCESS;
1925 }
1926
1927 VkResult
1928 tu_CreateComputePipelines(VkDevice _device,
1929 VkPipelineCache pipelineCache,
1930 uint32_t count,
1931 const VkComputePipelineCreateInfo *pCreateInfos,
1932 const VkAllocationCallbacks *pAllocator,
1933 VkPipeline *pPipelines)
1934 {
1935 VkResult result = VK_SUCCESS;
1936
1937 unsigned i = 0;
1938 for (; i < count; i++) {
1939 VkResult r;
1940 r = tu_compute_pipeline_create(_device, pipelineCache, &pCreateInfos[i],
1941 pAllocator, &pPipelines[i]);
1942 if (r != VK_SUCCESS) {
1943 result = r;
1944 }
1945 pPipelines[i] = VK_NULL_HANDLE;
1946 }
1947
1948 return result;
1949 }
1950
1951 void
1952 tu_DestroyPipeline(VkDevice _device,
1953 VkPipeline _pipeline,
1954 const VkAllocationCallbacks *pAllocator)
1955 {
1956 TU_FROM_HANDLE(tu_device, dev, _device);
1957 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
1958
1959 if (!_pipeline)
1960 return;
1961
1962 tu_pipeline_finish(pipeline, dev, pAllocator);
1963 vk_free2(&dev->alloc, pAllocator, pipeline);
1964 }