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turnip: Emit geometry shader obj and related consts
[mesa.git] / src / freedreno / vulkan / tu_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "main/menums.h"
31 #include "nir/nir.h"
32 #include "nir/nir_builder.h"
33 #include "spirv/nir_spirv.h"
34 #include "util/debug.h"
35 #include "util/mesa-sha1.h"
36 #include "util/u_atomic.h"
37 #include "vk_format.h"
38 #include "vk_util.h"
39
40 #include "tu_cs.h"
41
42 struct tu_pipeline_builder
43 {
44 struct tu_device *device;
45 struct tu_pipeline_cache *cache;
46 struct tu_pipeline_layout *layout;
47 const VkAllocationCallbacks *alloc;
48 const VkGraphicsPipelineCreateInfo *create_info;
49
50 struct tu_shader *shaders[MESA_SHADER_STAGES];
51 uint32_t shader_offsets[MESA_SHADER_STAGES];
52 uint32_t binning_vs_offset;
53 uint32_t shader_total_size;
54
55 bool rasterizer_discard;
56 /* these states are affectd by rasterizer_discard */
57 VkSampleCountFlagBits samples;
58 bool use_depth_stencil_attachment;
59 bool use_color_attachments;
60 uint32_t color_attachment_count;
61 VkFormat color_attachment_formats[MAX_RTS];
62 };
63
64 static enum tu_dynamic_state_bits
65 tu_dynamic_state_bit(VkDynamicState state)
66 {
67 switch (state) {
68 case VK_DYNAMIC_STATE_VIEWPORT:
69 return TU_DYNAMIC_VIEWPORT;
70 case VK_DYNAMIC_STATE_SCISSOR:
71 return TU_DYNAMIC_SCISSOR;
72 case VK_DYNAMIC_STATE_LINE_WIDTH:
73 return TU_DYNAMIC_LINE_WIDTH;
74 case VK_DYNAMIC_STATE_DEPTH_BIAS:
75 return TU_DYNAMIC_DEPTH_BIAS;
76 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
77 return TU_DYNAMIC_BLEND_CONSTANTS;
78 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
79 return TU_DYNAMIC_DEPTH_BOUNDS;
80 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
81 return TU_DYNAMIC_STENCIL_COMPARE_MASK;
82 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
83 return TU_DYNAMIC_STENCIL_WRITE_MASK;
84 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
85 return TU_DYNAMIC_STENCIL_REFERENCE;
86 default:
87 unreachable("invalid dynamic state");
88 return 0;
89 }
90 }
91
92 static gl_shader_stage
93 tu_shader_stage(VkShaderStageFlagBits stage)
94 {
95 switch (stage) {
96 case VK_SHADER_STAGE_VERTEX_BIT:
97 return MESA_SHADER_VERTEX;
98 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
99 return MESA_SHADER_TESS_CTRL;
100 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
101 return MESA_SHADER_TESS_EVAL;
102 case VK_SHADER_STAGE_GEOMETRY_BIT:
103 return MESA_SHADER_GEOMETRY;
104 case VK_SHADER_STAGE_FRAGMENT_BIT:
105 return MESA_SHADER_FRAGMENT;
106 case VK_SHADER_STAGE_COMPUTE_BIT:
107 return MESA_SHADER_COMPUTE;
108 default:
109 unreachable("invalid VkShaderStageFlagBits");
110 return MESA_SHADER_NONE;
111 }
112 }
113
114 static const VkVertexInputAttributeDescription *
115 tu_find_vertex_input_attribute(
116 const VkPipelineVertexInputStateCreateInfo *vi_info, uint32_t slot)
117 {
118 assert(slot >= VERT_ATTRIB_GENERIC0);
119 slot -= VERT_ATTRIB_GENERIC0;
120 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
121 if (vi_info->pVertexAttributeDescriptions[i].location == slot)
122 return &vi_info->pVertexAttributeDescriptions[i];
123 }
124 return NULL;
125 }
126
127 static const VkVertexInputBindingDescription *
128 tu_find_vertex_input_binding(
129 const VkPipelineVertexInputStateCreateInfo *vi_info,
130 const VkVertexInputAttributeDescription *vi_attr)
131 {
132 assert(vi_attr);
133 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
134 if (vi_info->pVertexBindingDescriptions[i].binding == vi_attr->binding)
135 return &vi_info->pVertexBindingDescriptions[i];
136 }
137 return NULL;
138 }
139
140 static bool
141 tu_logic_op_reads_dst(VkLogicOp op)
142 {
143 switch (op) {
144 case VK_LOGIC_OP_CLEAR:
145 case VK_LOGIC_OP_COPY:
146 case VK_LOGIC_OP_COPY_INVERTED:
147 case VK_LOGIC_OP_SET:
148 return false;
149 default:
150 return true;
151 }
152 }
153
154 static VkBlendFactor
155 tu_blend_factor_no_dst_alpha(VkBlendFactor factor)
156 {
157 /* treat dst alpha as 1.0 and avoid reading it */
158 switch (factor) {
159 case VK_BLEND_FACTOR_DST_ALPHA:
160 return VK_BLEND_FACTOR_ONE;
161 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
162 return VK_BLEND_FACTOR_ZERO;
163 default:
164 return factor;
165 }
166 }
167
168 static enum pc_di_primtype
169 tu6_primtype(VkPrimitiveTopology topology)
170 {
171 switch (topology) {
172 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
173 return DI_PT_POINTLIST;
174 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
175 return DI_PT_LINELIST;
176 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
177 return DI_PT_LINESTRIP;
178 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
179 return DI_PT_TRILIST;
180 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
181 return DI_PT_TRISTRIP;
182 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
183 return DI_PT_TRIFAN;
184 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
185 return DI_PT_LINE_ADJ;
186 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
187 return DI_PT_LINESTRIP_ADJ;
188 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
189 return DI_PT_TRI_ADJ;
190 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
191 return DI_PT_TRISTRIP_ADJ;
192 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
193 default:
194 unreachable("invalid primitive topology");
195 return DI_PT_NONE;
196 }
197 }
198
199 static enum adreno_compare_func
200 tu6_compare_func(VkCompareOp op)
201 {
202 switch (op) {
203 case VK_COMPARE_OP_NEVER:
204 return FUNC_NEVER;
205 case VK_COMPARE_OP_LESS:
206 return FUNC_LESS;
207 case VK_COMPARE_OP_EQUAL:
208 return FUNC_EQUAL;
209 case VK_COMPARE_OP_LESS_OR_EQUAL:
210 return FUNC_LEQUAL;
211 case VK_COMPARE_OP_GREATER:
212 return FUNC_GREATER;
213 case VK_COMPARE_OP_NOT_EQUAL:
214 return FUNC_NOTEQUAL;
215 case VK_COMPARE_OP_GREATER_OR_EQUAL:
216 return FUNC_GEQUAL;
217 case VK_COMPARE_OP_ALWAYS:
218 return FUNC_ALWAYS;
219 default:
220 unreachable("invalid VkCompareOp");
221 return FUNC_NEVER;
222 }
223 }
224
225 static enum adreno_stencil_op
226 tu6_stencil_op(VkStencilOp op)
227 {
228 switch (op) {
229 case VK_STENCIL_OP_KEEP:
230 return STENCIL_KEEP;
231 case VK_STENCIL_OP_ZERO:
232 return STENCIL_ZERO;
233 case VK_STENCIL_OP_REPLACE:
234 return STENCIL_REPLACE;
235 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
236 return STENCIL_INCR_CLAMP;
237 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
238 return STENCIL_DECR_CLAMP;
239 case VK_STENCIL_OP_INVERT:
240 return STENCIL_INVERT;
241 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
242 return STENCIL_INCR_WRAP;
243 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
244 return STENCIL_DECR_WRAP;
245 default:
246 unreachable("invalid VkStencilOp");
247 return STENCIL_KEEP;
248 }
249 }
250
251 static enum a3xx_rop_code
252 tu6_rop(VkLogicOp op)
253 {
254 switch (op) {
255 case VK_LOGIC_OP_CLEAR:
256 return ROP_CLEAR;
257 case VK_LOGIC_OP_AND:
258 return ROP_AND;
259 case VK_LOGIC_OP_AND_REVERSE:
260 return ROP_AND_REVERSE;
261 case VK_LOGIC_OP_COPY:
262 return ROP_COPY;
263 case VK_LOGIC_OP_AND_INVERTED:
264 return ROP_AND_INVERTED;
265 case VK_LOGIC_OP_NO_OP:
266 return ROP_NOOP;
267 case VK_LOGIC_OP_XOR:
268 return ROP_XOR;
269 case VK_LOGIC_OP_OR:
270 return ROP_OR;
271 case VK_LOGIC_OP_NOR:
272 return ROP_NOR;
273 case VK_LOGIC_OP_EQUIVALENT:
274 return ROP_EQUIV;
275 case VK_LOGIC_OP_INVERT:
276 return ROP_INVERT;
277 case VK_LOGIC_OP_OR_REVERSE:
278 return ROP_OR_REVERSE;
279 case VK_LOGIC_OP_COPY_INVERTED:
280 return ROP_COPY_INVERTED;
281 case VK_LOGIC_OP_OR_INVERTED:
282 return ROP_OR_INVERTED;
283 case VK_LOGIC_OP_NAND:
284 return ROP_NAND;
285 case VK_LOGIC_OP_SET:
286 return ROP_SET;
287 default:
288 unreachable("invalid VkLogicOp");
289 return ROP_NOOP;
290 }
291 }
292
293 static enum adreno_rb_blend_factor
294 tu6_blend_factor(VkBlendFactor factor)
295 {
296 switch (factor) {
297 case VK_BLEND_FACTOR_ZERO:
298 return FACTOR_ZERO;
299 case VK_BLEND_FACTOR_ONE:
300 return FACTOR_ONE;
301 case VK_BLEND_FACTOR_SRC_COLOR:
302 return FACTOR_SRC_COLOR;
303 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
304 return FACTOR_ONE_MINUS_SRC_COLOR;
305 case VK_BLEND_FACTOR_DST_COLOR:
306 return FACTOR_DST_COLOR;
307 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
308 return FACTOR_ONE_MINUS_DST_COLOR;
309 case VK_BLEND_FACTOR_SRC_ALPHA:
310 return FACTOR_SRC_ALPHA;
311 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
312 return FACTOR_ONE_MINUS_SRC_ALPHA;
313 case VK_BLEND_FACTOR_DST_ALPHA:
314 return FACTOR_DST_ALPHA;
315 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
316 return FACTOR_ONE_MINUS_DST_ALPHA;
317 case VK_BLEND_FACTOR_CONSTANT_COLOR:
318 return FACTOR_CONSTANT_COLOR;
319 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
320 return FACTOR_ONE_MINUS_CONSTANT_COLOR;
321 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
322 return FACTOR_CONSTANT_ALPHA;
323 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
324 return FACTOR_ONE_MINUS_CONSTANT_ALPHA;
325 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
326 return FACTOR_SRC_ALPHA_SATURATE;
327 case VK_BLEND_FACTOR_SRC1_COLOR:
328 return FACTOR_SRC1_COLOR;
329 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
330 return FACTOR_ONE_MINUS_SRC1_COLOR;
331 case VK_BLEND_FACTOR_SRC1_ALPHA:
332 return FACTOR_SRC1_ALPHA;
333 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
334 return FACTOR_ONE_MINUS_SRC1_ALPHA;
335 default:
336 unreachable("invalid VkBlendFactor");
337 return FACTOR_ZERO;
338 }
339 }
340
341 static enum a3xx_rb_blend_opcode
342 tu6_blend_op(VkBlendOp op)
343 {
344 switch (op) {
345 case VK_BLEND_OP_ADD:
346 return BLEND_DST_PLUS_SRC;
347 case VK_BLEND_OP_SUBTRACT:
348 return BLEND_SRC_MINUS_DST;
349 case VK_BLEND_OP_REVERSE_SUBTRACT:
350 return BLEND_DST_MINUS_SRC;
351 case VK_BLEND_OP_MIN:
352 return BLEND_MIN_DST_SRC;
353 case VK_BLEND_OP_MAX:
354 return BLEND_MAX_DST_SRC;
355 default:
356 unreachable("invalid VkBlendOp");
357 return BLEND_DST_PLUS_SRC;
358 }
359 }
360
361 static unsigned
362 tu_shader_nibo(const struct tu_shader *shader)
363 {
364 /* Don't use ir3_shader_nibo(), because that would include declared but
365 * unused storage images and SSBOs.
366 */
367 return shader->ssbo_map.num_desc + shader->image_map.num_desc;
368 }
369
370 static void
371 tu6_emit_vs_config(struct tu_cs *cs, struct tu_shader *shader,
372 const struct ir3_shader_variant *vs)
373 {
374 uint32_t sp_vs_ctrl =
375 A6XX_SP_VS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
376 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs->info.max_reg + 1) |
377 A6XX_SP_VS_CTRL_REG0_MERGEDREGS |
378 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs->branchstack);
379 if (vs->need_pixlod)
380 sp_vs_ctrl |= A6XX_SP_VS_CTRL_REG0_PIXLODENABLE;
381 if (vs->need_fine_derivatives)
382 sp_vs_ctrl |= A6XX_SP_VS_CTRL_REG0_DIFF_FINE;
383
384 uint32_t sp_vs_config = A6XX_SP_VS_CONFIG_NTEX(shader->texture_map.num_desc) |
385 A6XX_SP_VS_CONFIG_NSAMP(shader->sampler_map.num_desc);
386 if (vs->instrlen)
387 sp_vs_config |= A6XX_SP_VS_CONFIG_ENABLED;
388
389 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_CTRL_REG0, 1);
390 tu_cs_emit(cs, sp_vs_ctrl);
391
392 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_CONFIG, 2);
393 tu_cs_emit(cs, sp_vs_config);
394 tu_cs_emit(cs, vs->instrlen);
395
396 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_VS_CNTL, 1);
397 tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(vs->constlen, 4)) |
398 A6XX_HLSQ_VS_CNTL_ENABLED);
399 }
400
401 static void
402 tu6_emit_hs_config(struct tu_cs *cs, struct tu_shader *shader,
403 const struct ir3_shader_variant *hs)
404 {
405 uint32_t sp_hs_config = 0;
406 if (hs->instrlen)
407 sp_hs_config |= A6XX_SP_HS_CONFIG_ENABLED;
408
409 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
410 tu_cs_emit(cs, 0);
411
412 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_CONFIG, 2);
413 tu_cs_emit(cs, sp_hs_config);
414 tu_cs_emit(cs, hs->instrlen);
415
416 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_HS_CNTL, 1);
417 tu_cs_emit(cs, A6XX_HLSQ_HS_CNTL_CONSTLEN(align(hs->constlen, 4)));
418 }
419
420 static void
421 tu6_emit_ds_config(struct tu_cs *cs, struct tu_shader *shader,
422 const struct ir3_shader_variant *ds)
423 {
424 uint32_t sp_ds_config = 0;
425 if (ds->instrlen)
426 sp_ds_config |= A6XX_SP_DS_CONFIG_ENABLED;
427
428 tu_cs_emit_pkt4(cs, REG_A6XX_SP_DS_CONFIG, 2);
429 tu_cs_emit(cs, sp_ds_config);
430 tu_cs_emit(cs, ds->instrlen);
431
432 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_DS_CNTL, 1);
433 tu_cs_emit(cs, A6XX_HLSQ_DS_CNTL_CONSTLEN(align(ds->constlen, 4)));
434 }
435
436 static void
437 tu6_emit_gs_config(struct tu_cs *cs, struct tu_shader *shader,
438 const struct ir3_shader_variant *gs)
439 {
440 uint32_t sp_gs_config = 0;
441 if (gs->instrlen)
442 sp_gs_config |= A6XX_SP_GS_CONFIG_ENABLED;
443
444 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
445 tu_cs_emit(cs, 0);
446
447 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CONFIG, 2);
448 tu_cs_emit(cs, sp_gs_config);
449 tu_cs_emit(cs, gs->instrlen);
450
451 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_GS_CNTL, 1);
452 tu_cs_emit(cs, A6XX_HLSQ_GS_CNTL_CONSTLEN(align(gs->constlen, 4)));
453 }
454
455 static void
456 tu6_emit_fs_config(struct tu_cs *cs, struct tu_shader *shader,
457 const struct ir3_shader_variant *fs)
458 {
459 uint32_t sp_fs_ctrl =
460 A6XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) | 0x1000000 |
461 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs->info.max_reg + 1) |
462 A6XX_SP_FS_CTRL_REG0_MERGEDREGS |
463 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs->branchstack);
464 if (fs->total_in > 0)
465 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_VARYING;
466 if (fs->need_pixlod)
467 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_PIXLODENABLE;
468 if (fs->need_fine_derivatives)
469 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_DIFF_FINE;
470
471 uint32_t sp_fs_config = 0;
472 unsigned shader_nibo = 0;
473 if (shader) {
474 shader_nibo = tu_shader_nibo(shader);
475 sp_fs_config = A6XX_SP_FS_CONFIG_NTEX(shader->texture_map.num_desc) |
476 A6XX_SP_FS_CONFIG_NSAMP(shader->sampler_map.num_desc) |
477 A6XX_SP_FS_CONFIG_NIBO(shader_nibo);
478 }
479
480 if (fs->instrlen)
481 sp_fs_config |= A6XX_SP_FS_CONFIG_ENABLED;
482
483 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_CTRL_REG0, 1);
484 tu_cs_emit(cs, sp_fs_ctrl);
485
486 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_CONFIG, 2);
487 tu_cs_emit(cs, sp_fs_config);
488 tu_cs_emit(cs, fs->instrlen);
489
490 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_FS_CNTL, 1);
491 tu_cs_emit(cs, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(fs->constlen, 4)) |
492 A6XX_HLSQ_FS_CNTL_ENABLED);
493
494 tu_cs_emit_pkt4(cs, REG_A6XX_SP_IBO_COUNT, 1);
495 tu_cs_emit(cs, shader_nibo);
496 }
497
498 static void
499 tu6_emit_cs_config(struct tu_cs *cs, const struct tu_shader *shader,
500 const struct ir3_shader_variant *v)
501 {
502 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
503 tu_cs_emit(cs, 0xff);
504
505 unsigned constlen = align(v->constlen, 4);
506 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL, 1);
507 tu_cs_emit(cs, A6XX_HLSQ_CS_CNTL_CONSTLEN(constlen) |
508 A6XX_HLSQ_CS_CNTL_ENABLED);
509
510 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_CONFIG, 2);
511 tu_cs_emit(cs, A6XX_SP_CS_CONFIG_ENABLED |
512 A6XX_SP_CS_CONFIG_NIBO(tu_shader_nibo(shader)) |
513 A6XX_SP_CS_CONFIG_NTEX(shader->texture_map.num_desc) |
514 A6XX_SP_CS_CONFIG_NSAMP(shader->sampler_map.num_desc));
515 tu_cs_emit(cs, v->instrlen);
516
517 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_CTRL_REG0, 1);
518 tu_cs_emit(cs, A6XX_SP_CS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
519 A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(v->info.max_reg + 1) |
520 A6XX_SP_CS_CTRL_REG0_MERGEDREGS |
521 A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(v->branchstack) |
522 COND(v->need_pixlod, A6XX_SP_CS_CTRL_REG0_PIXLODENABLE) |
523 COND(v->need_fine_derivatives, A6XX_SP_CS_CTRL_REG0_DIFF_FINE));
524
525 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_UNKNOWN_A9B1, 1);
526 tu_cs_emit(cs, 0x41);
527
528 uint32_t local_invocation_id =
529 ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
530 uint32_t work_group_id =
531 ir3_find_sysval_regid(v, SYSTEM_VALUE_WORK_GROUP_ID);
532
533 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL_0, 2);
534 tu_cs_emit(cs,
535 A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) |
536 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
537 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
538 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
539 tu_cs_emit(cs, 0x2fc); /* HLSQ_CS_UNKNOWN_B998 */
540
541 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_IBO_COUNT, 1);
542 tu_cs_emit(cs, tu_shader_nibo(shader));
543 }
544
545 static void
546 tu6_emit_vs_system_values(struct tu_cs *cs,
547 const struct ir3_shader_variant *vs)
548 {
549 const uint32_t vertexid_regid =
550 ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
551 const uint32_t instanceid_regid =
552 ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
553
554 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_1, 6);
555 tu_cs_emit(cs, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid) |
556 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid) |
557 0xfcfc0000);
558 tu_cs_emit(cs, 0x0000fcfc); /* VFD_CONTROL_2 */
559 tu_cs_emit(cs, 0xfcfcfcfc); /* VFD_CONTROL_3 */
560 tu_cs_emit(cs, 0x000000fc); /* VFD_CONTROL_4 */
561 tu_cs_emit(cs, 0x0000fcfc); /* VFD_CONTROL_5 */
562 tu_cs_emit(cs, 0x00000000); /* VFD_CONTROL_6 */
563 }
564
565 /* Add any missing varyings needed for stream-out. Otherwise varyings not
566 * used by fragment shader will be stripped out.
567 */
568 static void
569 tu6_link_streamout(struct ir3_shader_linkage *l,
570 const struct ir3_shader_variant *v)
571 {
572 const struct ir3_stream_output_info *info = &v->shader->stream_output;
573
574 /*
575 * First, any stream-out varyings not already in linkage map (ie. also
576 * consumed by frag shader) need to be added:
577 */
578 for (unsigned i = 0; i < info->num_outputs; i++) {
579 const struct ir3_stream_output *out = &info->output[i];
580 unsigned compmask =
581 (1 << (out->num_components + out->start_component)) - 1;
582 unsigned k = out->register_index;
583 unsigned idx, nextloc = 0;
584
585 /* psize/pos need to be the last entries in linkage map, and will
586 * get added link_stream_out, so skip over them:
587 */
588 if (v->outputs[k].slot == VARYING_SLOT_PSIZ ||
589 v->outputs[k].slot == VARYING_SLOT_POS)
590 continue;
591
592 for (idx = 0; idx < l->cnt; idx++) {
593 if (l->var[idx].regid == v->outputs[k].regid)
594 break;
595 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
596 }
597
598 /* add if not already in linkage map: */
599 if (idx == l->cnt)
600 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
601
602 /* expand component-mask if needed, ie streaming out all components
603 * but frag shader doesn't consume all components:
604 */
605 if (compmask & ~l->var[idx].compmask) {
606 l->var[idx].compmask |= compmask;
607 l->max_loc = MAX2(l->max_loc, l->var[idx].loc +
608 util_last_bit(l->var[idx].compmask));
609 }
610 }
611 }
612
613 static void
614 tu6_setup_streamout(const struct ir3_shader_variant *v,
615 struct ir3_shader_linkage *l, struct tu_streamout_state *tf)
616 {
617 const struct ir3_stream_output_info *info = &v->shader->stream_output;
618
619 memset(tf, 0, sizeof(*tf));
620
621 tf->prog_count = align(l->max_loc, 2) / 2;
622
623 debug_assert(tf->prog_count < ARRAY_SIZE(tf->prog));
624
625 /* set stride info to the streamout state */
626 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++)
627 tf->stride[i] = info->stride[i];
628
629 for (unsigned i = 0; i < info->num_outputs; i++) {
630 const struct ir3_stream_output *out = &info->output[i];
631 unsigned k = out->register_index;
632 unsigned idx;
633
634 tf->ncomp[out->output_buffer] += out->num_components;
635
636 /* linkage map sorted by order frag shader wants things, so
637 * a bit less ideal here..
638 */
639 for (idx = 0; idx < l->cnt; idx++)
640 if (l->var[idx].regid == v->outputs[k].regid)
641 break;
642
643 debug_assert(idx < l->cnt);
644
645 for (unsigned j = 0; j < out->num_components; j++) {
646 unsigned c = j + out->start_component;
647 unsigned loc = l->var[idx].loc + c;
648 unsigned off = j + out->dst_offset; /* in dwords */
649
650 if (loc & 1) {
651 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
652 A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
653 A6XX_VPC_SO_PROG_B_OFF(off * 4);
654 } else {
655 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
656 A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
657 A6XX_VPC_SO_PROG_A_OFF(off * 4);
658 }
659 }
660 }
661
662 tf->vpc_so_buf_cntl = A6XX_VPC_SO_BUF_CNTL_ENABLE |
663 COND(tf->ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
664 COND(tf->ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
665 COND(tf->ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
666 COND(tf->ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3);
667 }
668
669 static void
670 tu6_emit_const(struct tu_cs *cs, uint32_t opcode, uint32_t base,
671 enum a6xx_state_block block, uint32_t offset,
672 uint32_t size, uint32_t *dwords) {
673 assert(size % 4 == 0);
674
675 tu_cs_emit_pkt7(cs, opcode, 3 + size);
676 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
677 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
678 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
679 CP_LOAD_STATE6_0_STATE_BLOCK(block) |
680 CP_LOAD_STATE6_0_NUM_UNIT(size / 4));
681
682 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
683 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
684 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
685
686 tu_cs_emit_array(cs, dwords, size);
687 }
688
689 static void
690 tu6_emit_vpc(struct tu_cs *cs,
691 const struct ir3_shader_variant *vs,
692 const struct ir3_shader_variant *fs,
693 bool binning_pass,
694 struct tu_streamout_state *tf)
695 {
696 struct ir3_shader_linkage linkage = { 0 };
697 ir3_link_shaders(&linkage, vs, fs);
698
699 if (vs->shader->stream_output.num_outputs)
700 tu6_link_streamout(&linkage, vs);
701
702 BITSET_DECLARE(vpc_var_enables, 128) = { 0 };
703 for (uint32_t i = 0; i < linkage.cnt; i++) {
704 const uint32_t comp_count = util_last_bit(linkage.var[i].compmask);
705 for (uint32_t j = 0; j < comp_count; j++)
706 BITSET_SET(vpc_var_enables, linkage.var[i].loc + j);
707 }
708
709 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VAR_DISABLE(0), 4);
710 tu_cs_emit(cs, ~vpc_var_enables[0]);
711 tu_cs_emit(cs, ~vpc_var_enables[1]);
712 tu_cs_emit(cs, ~vpc_var_enables[2]);
713 tu_cs_emit(cs, ~vpc_var_enables[3]);
714
715 /* a6xx finds position/pointsize at the end */
716 const uint32_t position_regid =
717 ir3_find_output_regid(vs, VARYING_SLOT_POS);
718 const uint32_t pointsize_regid =
719 ir3_find_output_regid(vs, VARYING_SLOT_PSIZ);
720 uint32_t pointsize_loc = 0xff, position_loc = 0xff;
721 if (position_regid != regid(63, 0)) {
722 position_loc = linkage.max_loc;
723 ir3_link_add(&linkage, position_regid, 0xf, linkage.max_loc);
724 }
725 if (pointsize_regid != regid(63, 0)) {
726 pointsize_loc = linkage.max_loc;
727 ir3_link_add(&linkage, pointsize_regid, 0x1, linkage.max_loc);
728 }
729
730 if (vs->shader->stream_output.num_outputs)
731 tu6_setup_streamout(vs, &linkage, tf);
732
733 /* map vs outputs to VPC */
734 assert(linkage.cnt <= 32);
735 const uint32_t sp_vs_out_count = (linkage.cnt + 1) / 2;
736 const uint32_t sp_vs_vpc_dst_count = (linkage.cnt + 3) / 4;
737 uint32_t sp_vs_out[16];
738 uint32_t sp_vs_vpc_dst[8];
739 sp_vs_out[sp_vs_out_count - 1] = 0;
740 sp_vs_vpc_dst[sp_vs_vpc_dst_count - 1] = 0;
741 for (uint32_t i = 0; i < linkage.cnt; i++) {
742 ((uint16_t *) sp_vs_out)[i] =
743 A6XX_SP_VS_OUT_REG_A_REGID(linkage.var[i].regid) |
744 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage.var[i].compmask);
745 ((uint8_t *) sp_vs_vpc_dst)[i] =
746 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage.var[i].loc);
747 }
748
749 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_OUT_REG(0), sp_vs_out_count);
750 tu_cs_emit_array(cs, sp_vs_out, sp_vs_out_count);
751
752 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_VPC_DST_REG(0), sp_vs_vpc_dst_count);
753 tu_cs_emit_array(cs, sp_vs_vpc_dst, sp_vs_vpc_dst_count);
754
755 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_CNTL_0, 1);
756 tu_cs_emit(cs, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs->total_in) |
757 (fs->total_in > 0 ? A6XX_VPC_CNTL_0_VARYING : 0) |
758 0xff00ff00);
759
760 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK, 1);
761 tu_cs_emit(cs, A6XX_VPC_PACK_POSITIONLOC(position_loc) |
762 A6XX_VPC_PACK_PSIZELOC(pointsize_loc) |
763 A6XX_VPC_PACK_STRIDE_IN_VPC(linkage.max_loc));
764
765 tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
766 tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage.cnt));
767
768 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
769 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage.max_loc) |
770 (vs->writes_psize ? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE : 0));
771 }
772
773 static int
774 tu6_vpc_varying_mode(const struct ir3_shader_variant *fs,
775 uint32_t index,
776 uint8_t *interp_mode,
777 uint8_t *ps_repl_mode)
778 {
779 enum
780 {
781 INTERP_SMOOTH = 0,
782 INTERP_FLAT = 1,
783 INTERP_ZERO = 2,
784 INTERP_ONE = 3,
785 };
786 enum
787 {
788 PS_REPL_NONE = 0,
789 PS_REPL_S = 1,
790 PS_REPL_T = 2,
791 PS_REPL_ONE_MINUS_T = 3,
792 };
793
794 const uint32_t compmask = fs->inputs[index].compmask;
795
796 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
797 * fourth component occupy three consecutive varying slots
798 */
799 int shift = 0;
800 *interp_mode = 0;
801 *ps_repl_mode = 0;
802 if (fs->inputs[index].slot == VARYING_SLOT_PNTC) {
803 if (compmask & 0x1) {
804 *ps_repl_mode |= PS_REPL_S << shift;
805 shift += 2;
806 }
807 if (compmask & 0x2) {
808 *ps_repl_mode |= PS_REPL_T << shift;
809 shift += 2;
810 }
811 if (compmask & 0x4) {
812 *interp_mode |= INTERP_ZERO << shift;
813 shift += 2;
814 }
815 if (compmask & 0x8) {
816 *interp_mode |= INTERP_ONE << 6;
817 shift += 2;
818 }
819 } else if ((fs->inputs[index].interpolate == INTERP_MODE_FLAT) ||
820 fs->inputs[index].rasterflat) {
821 for (int i = 0; i < 4; i++) {
822 if (compmask & (1 << i)) {
823 *interp_mode |= INTERP_FLAT << shift;
824 shift += 2;
825 }
826 }
827 }
828
829 return shift;
830 }
831
832 static void
833 tu6_emit_vpc_varying_modes(struct tu_cs *cs,
834 const struct ir3_shader_variant *fs,
835 bool binning_pass)
836 {
837 uint32_t interp_modes[8] = { 0 };
838 uint32_t ps_repl_modes[8] = { 0 };
839
840 if (!binning_pass) {
841 for (int i = -1;
842 (i = ir3_next_varying(fs, i)) < (int) fs->inputs_count;) {
843
844 /* get the mode for input i */
845 uint8_t interp_mode;
846 uint8_t ps_repl_mode;
847 const int bits =
848 tu6_vpc_varying_mode(fs, i, &interp_mode, &ps_repl_mode);
849
850 /* OR the mode into the array */
851 const uint32_t inloc = fs->inputs[i].inloc * 2;
852 uint32_t n = inloc / 32;
853 uint32_t shift = inloc % 32;
854 interp_modes[n] |= interp_mode << shift;
855 ps_repl_modes[n] |= ps_repl_mode << shift;
856 if (shift + bits > 32) {
857 n++;
858 shift = 32 - shift;
859
860 interp_modes[n] |= interp_mode >> shift;
861 ps_repl_modes[n] |= ps_repl_mode >> shift;
862 }
863 }
864 }
865
866 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
867 tu_cs_emit_array(cs, interp_modes, 8);
868
869 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
870 tu_cs_emit_array(cs, ps_repl_modes, 8);
871 }
872
873 static void
874 tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
875 {
876 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
877 uint32_t ij_pix_regid, ij_samp_regid, ij_cent_regid, ij_size_regid;
878 uint32_t smask_in_regid;
879
880 bool sample_shading = fs->per_samp; /* TODO | key->sample_shading; */
881 bool enable_varyings = fs->total_in > 0;
882
883 samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
884 smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
885 face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
886 coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
887 zwcoord_regid = VALIDREG(coord_regid) ? coord_regid + 2 : regid(63, 0);
888 ij_pix_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
889 ij_samp_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE);
890 ij_cent_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID);
891 ij_size_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE);
892
893 if (fs->num_sampler_prefetch > 0) {
894 assert(VALIDREG(ij_pix_regid));
895 /* also, it seems like ij_pix is *required* to be r0.x */
896 assert(ij_pix_regid == regid(0, 0));
897 }
898
899 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
900 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
901 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
902 0x7000); // XXX);
903 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
904 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
905 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch->src) |
906 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch->samp_id) |
907 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch->tex_id) |
908 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch->dst) |
909 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch->wrmask) |
910 COND(prefetch->half_precision, A6XX_SP_FS_PREFETCH_CMD_HALF) |
911 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch->cmd));
912 }
913
914 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
915 tu_cs_emit(cs, 0x7);
916 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
917 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
918 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
919 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid));
920 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid) |
921 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid) |
922 0xfc00fc00);
923 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
924 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
925 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid) |
926 0x0000fc00);
927 tu_cs_emit(cs, 0xfc);
928
929 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
930 tu_cs_emit(cs, enable_varyings ? 3 : 1);
931
932 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
933 tu_cs_emit(cs, 0xff); /* XXX */
934
935 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CNTL, 1);
936 tu_cs_emit(cs,
937 CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_VARYING) |
938 CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_CENTROID) |
939 CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
940 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
941 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
942 COND(fs->frag_coord,
943 A6XX_GRAS_CNTL_SIZE |
944 A6XX_GRAS_CNTL_XCOORD |
945 A6XX_GRAS_CNTL_YCOORD |
946 A6XX_GRAS_CNTL_ZCOORD |
947 A6XX_GRAS_CNTL_WCOORD) |
948 COND(fs->frag_face, A6XX_GRAS_CNTL_SIZE));
949
950 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CONTROL0, 2);
951 tu_cs_emit(cs,
952 CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_VARYING) |
953 CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_CENTROID) |
954 CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING) |
955 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
956 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
957 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
958 COND(fs->frag_coord,
959 A6XX_RB_RENDER_CONTROL0_SIZE |
960 A6XX_RB_RENDER_CONTROL0_XCOORD |
961 A6XX_RB_RENDER_CONTROL0_YCOORD |
962 A6XX_RB_RENDER_CONTROL0_ZCOORD |
963 A6XX_RB_RENDER_CONTROL0_WCOORD) |
964 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE));
965 tu_cs_emit(cs,
966 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
967 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
968 CONDREG(ij_size_regid, A6XX_RB_RENDER_CONTROL1_SIZE) |
969 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
970
971 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CNTL, 1);
972 tu_cs_emit(cs, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
973
974 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8101, 1);
975 tu_cs_emit(cs, COND(sample_shading, 0x6)); // XXX
976
977 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
978 tu_cs_emit(cs, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
979 }
980
981 static void
982 tu6_emit_fs_outputs(struct tu_cs *cs,
983 const struct ir3_shader_variant *fs,
984 uint32_t mrt_count)
985 {
986 uint32_t smask_regid, posz_regid;
987
988 posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
989 smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
990
991 uint32_t fragdata_regid[8];
992 if (fs->color0_mrt) {
993 fragdata_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
994 for (uint32_t i = 1; i < ARRAY_SIZE(fragdata_regid); i++)
995 fragdata_regid[i] = fragdata_regid[0];
996 } else {
997 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++)
998 fragdata_regid[i] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0 + i);
999 }
1000
1001 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_CNTL0, 2);
1002 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
1003 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
1004 0xfc000000);
1005 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count));
1006
1007 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
1008 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++) {
1009 // TODO we could have a mix of half and full precision outputs,
1010 // we really need to figure out half-precision from IR3_REG_HALF
1011 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid[i]) |
1012 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION : 0));
1013 }
1014
1015 tu_cs_emit_pkt4(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
1016 tu_cs_emit(cs, COND(fs->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
1017 COND(fs->writes_smask, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK));
1018 tu_cs_emit(cs, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count));
1019
1020 uint32_t gras_su_depth_plane_cntl = 0;
1021 uint32_t rb_depth_plane_cntl = 0;
1022 if (fs->no_earlyz || fs->writes_pos) {
1023 gras_su_depth_plane_cntl |= A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
1024 rb_depth_plane_cntl |= A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
1025 }
1026
1027 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
1028 tu_cs_emit(cs, gras_su_depth_plane_cntl);
1029
1030 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
1031 tu_cs_emit(cs, rb_depth_plane_cntl);
1032 }
1033
1034 static void
1035 tu6_emit_shader_object(struct tu_cs *cs,
1036 gl_shader_stage stage,
1037 const struct ir3_shader_variant *variant,
1038 const struct tu_bo *binary_bo,
1039 uint32_t binary_offset)
1040 {
1041 uint16_t reg;
1042 uint8_t opcode;
1043 enum a6xx_state_block sb;
1044 switch (stage) {
1045 case MESA_SHADER_VERTEX:
1046 reg = REG_A6XX_SP_VS_OBJ_START_LO;
1047 opcode = CP_LOAD_STATE6_GEOM;
1048 sb = SB6_VS_SHADER;
1049 break;
1050 case MESA_SHADER_TESS_CTRL:
1051 reg = REG_A6XX_SP_HS_OBJ_START_LO;
1052 opcode = CP_LOAD_STATE6_GEOM;
1053 sb = SB6_HS_SHADER;
1054 break;
1055 case MESA_SHADER_TESS_EVAL:
1056 reg = REG_A6XX_SP_DS_OBJ_START_LO;
1057 opcode = CP_LOAD_STATE6_GEOM;
1058 sb = SB6_DS_SHADER;
1059 break;
1060 case MESA_SHADER_GEOMETRY:
1061 reg = REG_A6XX_SP_GS_OBJ_START_LO;
1062 opcode = CP_LOAD_STATE6_GEOM;
1063 sb = SB6_GS_SHADER;
1064 break;
1065 case MESA_SHADER_FRAGMENT:
1066 reg = REG_A6XX_SP_FS_OBJ_START_LO;
1067 opcode = CP_LOAD_STATE6_FRAG;
1068 sb = SB6_FS_SHADER;
1069 break;
1070 case MESA_SHADER_COMPUTE:
1071 reg = REG_A6XX_SP_CS_OBJ_START_LO;
1072 opcode = CP_LOAD_STATE6_FRAG;
1073 sb = SB6_CS_SHADER;
1074 break;
1075 default:
1076 unreachable("invalid gl_shader_stage");
1077 opcode = CP_LOAD_STATE6_GEOM;
1078 sb = SB6_VS_SHADER;
1079 break;
1080 }
1081
1082 if (!variant->instrlen) {
1083 tu_cs_emit_pkt4(cs, reg, 2);
1084 tu_cs_emit_qw(cs, 0);
1085 return;
1086 }
1087
1088 assert(variant->type == stage);
1089
1090 const uint64_t binary_iova = binary_bo->iova + binary_offset;
1091 assert((binary_iova & 0xf) == 0);
1092 /* note: it looks like HW might try to read a few instructions beyond the instrlen size
1093 * of the shader. this could be a potential source of problems at some point
1094 * possibly this doesn't happen if shader iova is aligned enough (to 4k for example)
1095 */
1096
1097 tu_cs_emit_pkt4(cs, reg, 2);
1098 tu_cs_emit_qw(cs, binary_iova);
1099
1100 /* always indirect */
1101 const bool indirect = true;
1102 if (indirect) {
1103 tu_cs_emit_pkt7(cs, opcode, 3);
1104 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
1105 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
1106 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
1107 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
1108 CP_LOAD_STATE6_0_NUM_UNIT(variant->instrlen));
1109 tu_cs_emit_qw(cs, binary_iova);
1110 } else {
1111 const void *binary = binary_bo->map + binary_offset;
1112
1113 tu_cs_emit_pkt7(cs, opcode, 3 + variant->info.sizedwords);
1114 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
1115 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
1116 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
1117 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
1118 CP_LOAD_STATE6_0_NUM_UNIT(variant->instrlen));
1119 tu_cs_emit_qw(cs, 0);
1120 tu_cs_emit_array(cs, binary, variant->info.sizedwords);
1121 }
1122 }
1123
1124 static void
1125 tu6_emit_immediates(struct tu_cs *cs, const struct ir3_shader_variant *v,
1126 uint32_t opcode, enum a6xx_state_block block)
1127 {
1128 /* dummy variant */
1129 if (!v->shader)
1130 return;
1131
1132 const struct ir3_const_state *const_state = &v->shader->const_state;
1133 uint32_t base = const_state->offsets.immediate;
1134 int size = const_state->immediates_count;
1135
1136 /* truncate size to avoid writing constants that shader
1137 * does not use:
1138 */
1139 size = MIN2(size + base, v->constlen) - base;
1140
1141 if (size <= 0)
1142 return;
1143
1144 tu_cs_emit_pkt7(cs, opcode, 3 + size * 4);
1145 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
1146 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
1147 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
1148 CP_LOAD_STATE6_0_STATE_BLOCK(block) |
1149 CP_LOAD_STATE6_0_NUM_UNIT(size));
1150 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
1151 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
1152
1153 for (unsigned i = 0; i < size; i++) {
1154 tu_cs_emit(cs, const_state->immediates[i].val[0]);
1155 tu_cs_emit(cs, const_state->immediates[i].val[1]);
1156 tu_cs_emit(cs, const_state->immediates[i].val[2]);
1157 tu_cs_emit(cs, const_state->immediates[i].val[3]);
1158 }
1159 }
1160
1161 static void
1162 tu6_emit_geometry_consts(struct tu_cs *cs,
1163 const struct ir3_shader_variant *vs,
1164 const struct ir3_shader_variant *gs) {
1165 unsigned num_vertices = gs->shader->nir->info.gs.vertices_in;
1166
1167 uint32_t params[4] = {
1168 vs->shader->output_size * num_vertices * 4, /* primitive stride */
1169 vs->shader->output_size * 4, /* vertex stride */
1170 0,
1171 0,
1172 };
1173 uint32_t vs_base = vs->shader->const_state.offsets.primitive_param;
1174 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, vs_base, SB6_VS_SHADER, 0,
1175 ARRAY_SIZE(params), params);
1176
1177 uint32_t gs_base = gs->shader->const_state.offsets.primitive_param;
1178 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, gs_base, SB6_GS_SHADER, 0,
1179 ARRAY_SIZE(params), params);
1180 }
1181
1182 static void
1183 tu6_emit_program(struct tu_cs *cs,
1184 const struct tu_pipeline_builder *builder,
1185 const struct tu_bo *binary_bo,
1186 bool binning_pass,
1187 struct tu_streamout_state *tf)
1188 {
1189 static const struct ir3_shader_variant dummy_variant = {
1190 .type = MESA_SHADER_NONE
1191 };
1192 assert(builder->shaders[MESA_SHADER_VERTEX]);
1193 const struct ir3_shader_variant *vs =
1194 &builder->shaders[MESA_SHADER_VERTEX]->variants[0];
1195 const struct ir3_shader_variant *hs =
1196 builder->shaders[MESA_SHADER_TESS_CTRL]
1197 ? &builder->shaders[MESA_SHADER_TESS_CTRL]->variants[0]
1198 : &dummy_variant;
1199 const struct ir3_shader_variant *ds =
1200 builder->shaders[MESA_SHADER_TESS_EVAL]
1201 ? &builder->shaders[MESA_SHADER_TESS_EVAL]->variants[0]
1202 : &dummy_variant;
1203 const struct ir3_shader_variant *gs =
1204 builder->shaders[MESA_SHADER_GEOMETRY]
1205 ? &builder->shaders[MESA_SHADER_GEOMETRY]->variants[0]
1206 : &dummy_variant;
1207 const struct ir3_shader_variant *fs =
1208 builder->shaders[MESA_SHADER_FRAGMENT]
1209 ? &builder->shaders[MESA_SHADER_FRAGMENT]->variants[0]
1210 : &dummy_variant;
1211 bool has_gs = gs->type != MESA_SHADER_NONE;
1212
1213 if (binning_pass) {
1214 /* if we have streamout, use full VS in binning pass, as the
1215 * binning pass VS will have outputs on other than position/psize
1216 * stripped out:
1217 */
1218 if (vs->shader->stream_output.num_outputs == 0)
1219 vs = &builder->shaders[MESA_SHADER_VERTEX]->variants[1];
1220 fs = &dummy_variant;
1221 }
1222
1223 tu6_emit_vs_config(cs, builder->shaders[MESA_SHADER_VERTEX], vs);
1224 tu6_emit_hs_config(cs, builder->shaders[MESA_SHADER_TESS_CTRL], hs);
1225 tu6_emit_ds_config(cs, builder->shaders[MESA_SHADER_TESS_EVAL], ds);
1226 tu6_emit_gs_config(cs, builder->shaders[MESA_SHADER_GEOMETRY], gs);
1227 tu6_emit_fs_config(cs, builder->shaders[MESA_SHADER_FRAGMENT], fs);
1228
1229 tu6_emit_vs_system_values(cs, vs);
1230 tu6_emit_vpc(cs, vs, fs, binning_pass, tf);
1231 tu6_emit_vpc_varying_modes(cs, fs, binning_pass);
1232 tu6_emit_fs_inputs(cs, fs);
1233 tu6_emit_fs_outputs(cs, fs, builder->color_attachment_count);
1234
1235 tu6_emit_shader_object(cs, MESA_SHADER_VERTEX, vs, binary_bo,
1236 binning_pass ? builder->binning_vs_offset : builder->shader_offsets[MESA_SHADER_VERTEX]);
1237 if (has_gs)
1238 tu6_emit_shader_object(cs, MESA_SHADER_GEOMETRY, gs, binary_bo,
1239 builder->shader_offsets[MESA_SHADER_GEOMETRY]);
1240 tu6_emit_shader_object(cs, MESA_SHADER_FRAGMENT, fs, binary_bo,
1241 builder->shader_offsets[MESA_SHADER_FRAGMENT]);
1242
1243 tu6_emit_immediates(cs, vs, CP_LOAD_STATE6_GEOM, SB6_VS_SHADER);
1244 if (has_gs) {
1245 tu6_emit_immediates(cs, gs, CP_LOAD_STATE6_GEOM, SB6_GS_SHADER);
1246 tu6_emit_geometry_consts(cs, vs, gs);
1247 }
1248 if (!binning_pass)
1249 tu6_emit_immediates(cs, fs, CP_LOAD_STATE6_FRAG, SB6_FS_SHADER);
1250 }
1251
1252 static void
1253 tu6_emit_vertex_input(struct tu_cs *cs,
1254 const struct ir3_shader_variant *vs,
1255 const VkPipelineVertexInputStateCreateInfo *vi_info,
1256 uint8_t bindings[MAX_VERTEX_ATTRIBS],
1257 uint16_t strides[MAX_VERTEX_ATTRIBS],
1258 uint16_t offsets[MAX_VERTEX_ATTRIBS],
1259 uint32_t *count)
1260 {
1261 uint32_t vfd_decode_idx = 0;
1262
1263 for (uint32_t i = 0; i < vs->inputs_count; i++) {
1264 if (vs->inputs[i].sysval || !vs->inputs[i].compmask)
1265 continue;
1266
1267 const VkVertexInputAttributeDescription *vi_attr =
1268 tu_find_vertex_input_attribute(vi_info, vs->inputs[i].slot);
1269 const VkVertexInputBindingDescription *vi_binding =
1270 tu_find_vertex_input_binding(vi_info, vi_attr);
1271 assert(vi_attr && vi_binding);
1272
1273 const struct tu_native_format format = tu6_format_vtx(vi_attr->format);
1274
1275 uint32_t vfd_decode = A6XX_VFD_DECODE_INSTR_IDX(vfd_decode_idx) |
1276 A6XX_VFD_DECODE_INSTR_FORMAT(format.fmt) |
1277 A6XX_VFD_DECODE_INSTR_SWAP(format.swap) |
1278 A6XX_VFD_DECODE_INSTR_UNK30;
1279 if (vi_binding->inputRate == VK_VERTEX_INPUT_RATE_INSTANCE)
1280 vfd_decode |= A6XX_VFD_DECODE_INSTR_INSTANCED;
1281 if (!vk_format_is_int(vi_attr->format))
1282 vfd_decode |= A6XX_VFD_DECODE_INSTR_FLOAT;
1283
1284 const uint32_t vfd_decode_step_rate = 1;
1285
1286 const uint32_t vfd_dest_cntl =
1287 A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vs->inputs[i].compmask) |
1288 A6XX_VFD_DEST_CNTL_INSTR_REGID(vs->inputs[i].regid);
1289
1290 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_DECODE(vfd_decode_idx), 2);
1291 tu_cs_emit(cs, vfd_decode);
1292 tu_cs_emit(cs, vfd_decode_step_rate);
1293
1294 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_DEST_CNTL(vfd_decode_idx), 1);
1295 tu_cs_emit(cs, vfd_dest_cntl);
1296
1297 bindings[vfd_decode_idx] = vi_binding->binding;
1298 strides[vfd_decode_idx] = vi_binding->stride;
1299 offsets[vfd_decode_idx] = vi_attr->offset;
1300
1301 vfd_decode_idx++;
1302 assert(vfd_decode_idx <= MAX_VERTEX_ATTRIBS);
1303 }
1304
1305 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_0, 1);
1306 tu_cs_emit(
1307 cs, A6XX_VFD_CONTROL_0_VTXCNT(vfd_decode_idx) | (vfd_decode_idx << 8));
1308
1309 *count = vfd_decode_idx;
1310 }
1311
1312 static uint32_t
1313 tu6_guardband_adj(uint32_t v)
1314 {
1315 if (v > 256)
1316 return (uint32_t)(511.0 - 65.0 * (log2(v) - 8.0));
1317 else
1318 return 511;
1319 }
1320
1321 void
1322 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport)
1323 {
1324 float offsets[3];
1325 float scales[3];
1326 scales[0] = viewport->width / 2.0f;
1327 scales[1] = viewport->height / 2.0f;
1328 scales[2] = viewport->maxDepth - viewport->minDepth;
1329 offsets[0] = viewport->x + scales[0];
1330 offsets[1] = viewport->y + scales[1];
1331 offsets[2] = viewport->minDepth;
1332
1333 VkOffset2D min;
1334 VkOffset2D max;
1335 min.x = (int32_t) viewport->x;
1336 max.x = (int32_t) ceilf(viewport->x + viewport->width);
1337 if (viewport->height >= 0.0f) {
1338 min.y = (int32_t) viewport->y;
1339 max.y = (int32_t) ceilf(viewport->y + viewport->height);
1340 } else {
1341 min.y = (int32_t)(viewport->y + viewport->height);
1342 max.y = (int32_t) ceilf(viewport->y);
1343 }
1344 /* the spec allows viewport->height to be 0.0f */
1345 if (min.y == max.y)
1346 max.y++;
1347 assert(min.x >= 0 && min.x < max.x);
1348 assert(min.y >= 0 && min.y < max.y);
1349
1350 VkExtent2D guardband_adj;
1351 guardband_adj.width = tu6_guardband_adj(max.x - min.x);
1352 guardband_adj.height = tu6_guardband_adj(max.y - min.y);
1353
1354 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0, 6);
1355 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XOFFSET_0(offsets[0]).value);
1356 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XSCALE_0(scales[0]).value);
1357 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YOFFSET_0(offsets[1]).value);
1358 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YSCALE_0(scales[1]).value);
1359 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZOFFSET_0(offsets[2]).value);
1360 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZSCALE_0(scales[2]).value);
1361
1362 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
1363 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(min.x) |
1364 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(min.y));
1365 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(max.x - 1) |
1366 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(max.y - 1));
1367
1368 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
1369 tu_cs_emit(cs,
1370 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj.width) |
1371 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj.height));
1372
1373 float z_clamp_min = MIN2(viewport->minDepth, viewport->maxDepth);
1374 float z_clamp_max = MAX2(viewport->minDepth, viewport->maxDepth);
1375
1376 tu_cs_emit_regs(cs,
1377 A6XX_GRAS_CL_Z_CLAMP_MIN(z_clamp_min),
1378 A6XX_GRAS_CL_Z_CLAMP_MAX(z_clamp_max));
1379
1380 tu_cs_emit_regs(cs,
1381 A6XX_RB_Z_CLAMP_MIN(z_clamp_min),
1382 A6XX_RB_Z_CLAMP_MAX(z_clamp_max));
1383 }
1384
1385 void
1386 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor)
1387 {
1388 const VkOffset2D min = scissor->offset;
1389 const VkOffset2D max = {
1390 scissor->offset.x + scissor->extent.width,
1391 scissor->offset.y + scissor->extent.height,
1392 };
1393
1394 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
1395 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(min.x) |
1396 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(min.y));
1397 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(max.x - 1) |
1398 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(max.y - 1));
1399 }
1400
1401 static void
1402 tu6_emit_gras_unknowns(struct tu_cs *cs)
1403 {
1404 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8001, 1);
1405 tu_cs_emit(cs, 0x0);
1406 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LAYER_CNTL, 1);
1407 tu_cs_emit(cs, 0x0);
1408 }
1409
1410 static void
1411 tu6_emit_point_size(struct tu_cs *cs)
1412 {
1413 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POINT_MINMAX, 2);
1414 tu_cs_emit(cs, A6XX_GRAS_SU_POINT_MINMAX_MIN(1.0f / 16.0f) |
1415 A6XX_GRAS_SU_POINT_MINMAX_MAX(4092.0f));
1416 tu_cs_emit(cs, A6XX_GRAS_SU_POINT_SIZE(1.0f).value);
1417 }
1418
1419 static uint32_t
1420 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo *rast_info,
1421 VkSampleCountFlagBits samples)
1422 {
1423 uint32_t gras_su_cntl = 0;
1424
1425 if (rast_info->cullMode & VK_CULL_MODE_FRONT_BIT)
1426 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_FRONT;
1427 if (rast_info->cullMode & VK_CULL_MODE_BACK_BIT)
1428 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_BACK;
1429
1430 if (rast_info->frontFace == VK_FRONT_FACE_CLOCKWISE)
1431 gras_su_cntl |= A6XX_GRAS_SU_CNTL_FRONT_CW;
1432
1433 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1434
1435 if (rast_info->depthBiasEnable)
1436 gras_su_cntl |= A6XX_GRAS_SU_CNTL_POLY_OFFSET;
1437
1438 if (samples > VK_SAMPLE_COUNT_1_BIT)
1439 gras_su_cntl |= A6XX_GRAS_SU_CNTL_MSAA_ENABLE;
1440
1441 return gras_su_cntl;
1442 }
1443
1444 void
1445 tu6_emit_gras_su_cntl(struct tu_cs *cs,
1446 uint32_t gras_su_cntl,
1447 float line_width)
1448 {
1449 assert((gras_su_cntl & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK) == 0);
1450 gras_su_cntl |= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(line_width / 2.0f);
1451
1452 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_CNTL, 1);
1453 tu_cs_emit(cs, gras_su_cntl);
1454 }
1455
1456 void
1457 tu6_emit_depth_bias(struct tu_cs *cs,
1458 float constant_factor,
1459 float clamp,
1460 float slope_factor)
1461 {
1462 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
1463 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor).value);
1464 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor).value);
1465 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp).value);
1466 }
1467
1468 static void
1469 tu6_emit_alpha_control_disable(struct tu_cs *cs)
1470 {
1471 tu_cs_emit_pkt4(cs, REG_A6XX_RB_ALPHA_CONTROL, 1);
1472 tu_cs_emit(cs, 0);
1473 }
1474
1475 static void
1476 tu6_emit_depth_control(struct tu_cs *cs,
1477 const VkPipelineDepthStencilStateCreateInfo *ds_info,
1478 const VkPipelineRasterizationStateCreateInfo *rast_info)
1479 {
1480 assert(!ds_info->depthBoundsTestEnable);
1481
1482 uint32_t rb_depth_cntl = 0;
1483 if (ds_info->depthTestEnable) {
1484 rb_depth_cntl |=
1485 A6XX_RB_DEPTH_CNTL_Z_ENABLE |
1486 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) |
1487 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
1488
1489 if (rast_info->depthClampEnable)
1490 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE;
1491
1492 if (ds_info->depthWriteEnable)
1493 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
1494 }
1495
1496 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_CNTL, 1);
1497 tu_cs_emit(cs, rb_depth_cntl);
1498 }
1499
1500 static void
1501 tu6_emit_stencil_control(struct tu_cs *cs,
1502 const VkPipelineDepthStencilStateCreateInfo *ds_info)
1503 {
1504 uint32_t rb_stencil_control = 0;
1505 if (ds_info->stencilTestEnable) {
1506 const VkStencilOpState *front = &ds_info->front;
1507 const VkStencilOpState *back = &ds_info->back;
1508 rb_stencil_control |=
1509 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
1510 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
1511 A6XX_RB_STENCIL_CONTROL_STENCIL_READ |
1512 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front->compareOp)) |
1513 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front->failOp)) |
1514 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front->passOp)) |
1515 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front->depthFailOp)) |
1516 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back->compareOp)) |
1517 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back->failOp)) |
1518 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back->passOp)) |
1519 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back->depthFailOp));
1520 }
1521
1522 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_CONTROL, 1);
1523 tu_cs_emit(cs, rb_stencil_control);
1524 }
1525
1526 void
1527 tu6_emit_stencil_compare_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1528 {
1529 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILMASK, 1);
1530 tu_cs_emit(
1531 cs, A6XX_RB_STENCILMASK_MASK(front) | A6XX_RB_STENCILMASK_BFMASK(back));
1532 }
1533
1534 void
1535 tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1536 {
1537 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILWRMASK, 1);
1538 tu_cs_emit(cs, A6XX_RB_STENCILWRMASK_WRMASK(front) |
1539 A6XX_RB_STENCILWRMASK_BFWRMASK(back));
1540 }
1541
1542 void
1543 tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back)
1544 {
1545 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILREF, 1);
1546 tu_cs_emit(cs,
1547 A6XX_RB_STENCILREF_REF(front) | A6XX_RB_STENCILREF_BFREF(back));
1548 }
1549
1550 static uint32_t
1551 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState *att,
1552 bool has_alpha)
1553 {
1554 const enum a3xx_rb_blend_opcode color_op = tu6_blend_op(att->colorBlendOp);
1555 const enum adreno_rb_blend_factor src_color_factor = tu6_blend_factor(
1556 has_alpha ? att->srcColorBlendFactor
1557 : tu_blend_factor_no_dst_alpha(att->srcColorBlendFactor));
1558 const enum adreno_rb_blend_factor dst_color_factor = tu6_blend_factor(
1559 has_alpha ? att->dstColorBlendFactor
1560 : tu_blend_factor_no_dst_alpha(att->dstColorBlendFactor));
1561 const enum a3xx_rb_blend_opcode alpha_op = tu6_blend_op(att->alphaBlendOp);
1562 const enum adreno_rb_blend_factor src_alpha_factor =
1563 tu6_blend_factor(att->srcAlphaBlendFactor);
1564 const enum adreno_rb_blend_factor dst_alpha_factor =
1565 tu6_blend_factor(att->dstAlphaBlendFactor);
1566
1567 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor) |
1568 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op) |
1569 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor) |
1570 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor) |
1571 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op) |
1572 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor);
1573 }
1574
1575 static uint32_t
1576 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState *att,
1577 uint32_t rb_mrt_control_rop,
1578 bool is_int,
1579 bool has_alpha)
1580 {
1581 uint32_t rb_mrt_control =
1582 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att->colorWriteMask);
1583
1584 /* ignore blending and logic op for integer attachments */
1585 if (is_int) {
1586 rb_mrt_control |= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
1587 return rb_mrt_control;
1588 }
1589
1590 rb_mrt_control |= rb_mrt_control_rop;
1591
1592 if (att->blendEnable) {
1593 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND;
1594
1595 if (has_alpha)
1596 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND2;
1597 }
1598
1599 return rb_mrt_control;
1600 }
1601
1602 static void
1603 tu6_emit_rb_mrt_controls(struct tu_cs *cs,
1604 const VkPipelineColorBlendStateCreateInfo *blend_info,
1605 const VkFormat attachment_formats[MAX_RTS],
1606 uint32_t *blend_enable_mask)
1607 {
1608 *blend_enable_mask = 0;
1609
1610 bool rop_reads_dst = false;
1611 uint32_t rb_mrt_control_rop = 0;
1612 if (blend_info->logicOpEnable) {
1613 rop_reads_dst = tu_logic_op_reads_dst(blend_info->logicOp);
1614 rb_mrt_control_rop =
1615 A6XX_RB_MRT_CONTROL_ROP_ENABLE |
1616 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info->logicOp));
1617 }
1618
1619 for (uint32_t i = 0; i < blend_info->attachmentCount; i++) {
1620 const VkPipelineColorBlendAttachmentState *att =
1621 &blend_info->pAttachments[i];
1622 const VkFormat format = attachment_formats[i];
1623
1624 uint32_t rb_mrt_control = 0;
1625 uint32_t rb_mrt_blend_control = 0;
1626 if (format != VK_FORMAT_UNDEFINED) {
1627 const bool is_int = vk_format_is_int(format);
1628 const bool has_alpha = vk_format_has_alpha(format);
1629
1630 rb_mrt_control =
1631 tu6_rb_mrt_control(att, rb_mrt_control_rop, is_int, has_alpha);
1632 rb_mrt_blend_control = tu6_rb_mrt_blend_control(att, has_alpha);
1633
1634 if (att->blendEnable || rop_reads_dst)
1635 *blend_enable_mask |= 1 << i;
1636 }
1637
1638 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
1639 tu_cs_emit(cs, rb_mrt_control);
1640 tu_cs_emit(cs, rb_mrt_blend_control);
1641 }
1642 }
1643
1644 static void
1645 tu6_emit_blend_control(struct tu_cs *cs,
1646 uint32_t blend_enable_mask,
1647 const VkPipelineMultisampleStateCreateInfo *msaa_info)
1648 {
1649 assert(!msaa_info->alphaToOneEnable);
1650
1651 uint32_t sp_blend_cntl = A6XX_SP_BLEND_CNTL_UNK8;
1652 if (blend_enable_mask)
1653 sp_blend_cntl |= A6XX_SP_BLEND_CNTL_ENABLED;
1654 if (msaa_info->alphaToCoverageEnable)
1655 sp_blend_cntl |= A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE;
1656
1657 const uint32_t sample_mask =
1658 msaa_info->pSampleMask ? *msaa_info->pSampleMask
1659 : ((1 << msaa_info->rasterizationSamples) - 1);
1660
1661 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
1662 uint32_t rb_blend_cntl =
1663 A6XX_RB_BLEND_CNTL_ENABLE_BLEND(blend_enable_mask) |
1664 A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND |
1665 A6XX_RB_BLEND_CNTL_SAMPLE_MASK(sample_mask);
1666 if (msaa_info->alphaToCoverageEnable)
1667 rb_blend_cntl |= A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE;
1668
1669 tu_cs_emit_pkt4(cs, REG_A6XX_SP_BLEND_CNTL, 1);
1670 tu_cs_emit(cs, sp_blend_cntl);
1671
1672 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_CNTL, 1);
1673 tu_cs_emit(cs, rb_blend_cntl);
1674 }
1675
1676 void
1677 tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4])
1678 {
1679 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_RED_F32, 4);
1680 tu_cs_emit_array(cs, (const uint32_t *) constants, 4);
1681 }
1682
1683 static VkResult
1684 tu_pipeline_create(struct tu_device *dev,
1685 const VkAllocationCallbacks *pAllocator,
1686 struct tu_pipeline **out_pipeline)
1687 {
1688 struct tu_pipeline *pipeline =
1689 vk_zalloc2(&dev->alloc, pAllocator, sizeof(*pipeline), 8,
1690 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1691 if (!pipeline)
1692 return VK_ERROR_OUT_OF_HOST_MEMORY;
1693
1694 tu_cs_init(&pipeline->cs, dev, TU_CS_MODE_SUB_STREAM, 2048);
1695
1696 /* reserve the space now such that tu_cs_begin_sub_stream never fails */
1697 VkResult result = tu_cs_reserve_space(&pipeline->cs, 2048);
1698 if (result != VK_SUCCESS) {
1699 vk_free2(&dev->alloc, pAllocator, pipeline);
1700 return result;
1701 }
1702
1703 *out_pipeline = pipeline;
1704
1705 return VK_SUCCESS;
1706 }
1707
1708 static VkResult
1709 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder)
1710 {
1711 const VkPipelineShaderStageCreateInfo *stage_infos[MESA_SHADER_STAGES] = {
1712 NULL
1713 };
1714 for (uint32_t i = 0; i < builder->create_info->stageCount; i++) {
1715 gl_shader_stage stage =
1716 tu_shader_stage(builder->create_info->pStages[i].stage);
1717 stage_infos[stage] = &builder->create_info->pStages[i];
1718 }
1719
1720 struct tu_shader_compile_options options;
1721 tu_shader_compile_options_init(&options, builder->create_info);
1722
1723 /* compile shaders in reverse order */
1724 struct tu_shader *next_stage_shader = NULL;
1725 for (gl_shader_stage stage = MESA_SHADER_STAGES - 1;
1726 stage > MESA_SHADER_NONE; stage--) {
1727 const VkPipelineShaderStageCreateInfo *stage_info = stage_infos[stage];
1728 if (!stage_info)
1729 continue;
1730
1731 struct tu_shader *shader =
1732 tu_shader_create(builder->device, stage, stage_info, builder->layout,
1733 builder->alloc);
1734 if (!shader)
1735 return VK_ERROR_OUT_OF_HOST_MEMORY;
1736
1737 VkResult result =
1738 tu_shader_compile(builder->device, shader, next_stage_shader,
1739 &options, builder->alloc);
1740 if (result != VK_SUCCESS)
1741 return result;
1742
1743 builder->shaders[stage] = shader;
1744 builder->shader_offsets[stage] = builder->shader_total_size;
1745 builder->shader_total_size +=
1746 sizeof(uint32_t) * shader->variants[0].info.sizedwords;
1747
1748 next_stage_shader = shader;
1749 }
1750
1751 if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
1752 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1753 const struct ir3_shader_variant *variant;
1754
1755 if (vs->ir3_shader.stream_output.num_outputs)
1756 variant = &vs->variants[0];
1757 else
1758 variant = &vs->variants[1];
1759
1760 builder->binning_vs_offset = builder->shader_total_size;
1761 builder->shader_total_size +=
1762 sizeof(uint32_t) * variant->info.sizedwords;
1763 }
1764
1765 return VK_SUCCESS;
1766 }
1767
1768 static VkResult
1769 tu_pipeline_builder_upload_shaders(struct tu_pipeline_builder *builder,
1770 struct tu_pipeline *pipeline)
1771 {
1772 struct tu_bo *bo = &pipeline->program.binary_bo;
1773
1774 VkResult result =
1775 tu_bo_init_new(builder->device, bo, builder->shader_total_size);
1776 if (result != VK_SUCCESS)
1777 return result;
1778
1779 result = tu_bo_map(builder->device, bo);
1780 if (result != VK_SUCCESS)
1781 return result;
1782
1783 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
1784 const struct tu_shader *shader = builder->shaders[i];
1785 if (!shader)
1786 continue;
1787
1788 memcpy(bo->map + builder->shader_offsets[i], shader->binary,
1789 sizeof(uint32_t) * shader->variants[0].info.sizedwords);
1790 }
1791
1792 if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
1793 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1794 const struct ir3_shader_variant *variant;
1795 void *bin;
1796
1797 if (vs->ir3_shader.stream_output.num_outputs) {
1798 variant = &vs->variants[0];
1799 bin = vs->binary;
1800 } else {
1801 variant = &vs->variants[1];
1802 bin = vs->binning_binary;
1803 }
1804
1805 memcpy(bo->map + builder->binning_vs_offset, bin,
1806 sizeof(uint32_t) * variant->info.sizedwords);
1807 }
1808
1809 return VK_SUCCESS;
1810 }
1811
1812 static void
1813 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
1814 struct tu_pipeline *pipeline)
1815 {
1816 const VkPipelineDynamicStateCreateInfo *dynamic_info =
1817 builder->create_info->pDynamicState;
1818
1819 if (!dynamic_info)
1820 return;
1821
1822 for (uint32_t i = 0; i < dynamic_info->dynamicStateCount; i++) {
1823 pipeline->dynamic_state.mask |=
1824 tu_dynamic_state_bit(dynamic_info->pDynamicStates[i]);
1825 }
1826 }
1827
1828 static void
1829 tu_pipeline_set_linkage(struct tu_program_descriptor_linkage *link,
1830 struct tu_shader *shader,
1831 struct ir3_shader_variant *v)
1832 {
1833 link->ubo_state = v->shader->ubo_state;
1834 link->const_state = v->shader->const_state;
1835 link->constlen = v->constlen;
1836 link->texture_map = shader->texture_map;
1837 link->sampler_map = shader->sampler_map;
1838 link->ubo_map = shader->ubo_map;
1839 link->ssbo_map = shader->ssbo_map;
1840 link->image_map = shader->image_map;
1841 }
1842
1843 static void
1844 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder *builder,
1845 struct tu_pipeline *pipeline)
1846 {
1847 struct tu_cs prog_cs;
1848 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
1849 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, false, &pipeline->streamout);
1850 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
1851
1852 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
1853 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, true, &pipeline->streamout);
1854 pipeline->program.binning_state_ib =
1855 tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
1856
1857 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
1858 if (!builder->shaders[i])
1859 continue;
1860
1861 tu_pipeline_set_linkage(&pipeline->program.link[i],
1862 builder->shaders[i],
1863 &builder->shaders[i]->variants[0]);
1864 }
1865 }
1866
1867 static void
1868 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder *builder,
1869 struct tu_pipeline *pipeline)
1870 {
1871 const VkPipelineVertexInputStateCreateInfo *vi_info =
1872 builder->create_info->pVertexInputState;
1873 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1874
1875 struct tu_cs vi_cs;
1876 tu_cs_begin_sub_stream(&pipeline->cs,
1877 MAX_VERTEX_ATTRIBS * 5 + 2, &vi_cs);
1878 tu6_emit_vertex_input(&vi_cs, &vs->variants[0], vi_info,
1879 pipeline->vi.bindings, pipeline->vi.strides,
1880 pipeline->vi.offsets, &pipeline->vi.count);
1881 pipeline->vi.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
1882
1883 if (vs->has_binning_pass) {
1884 tu_cs_begin_sub_stream(&pipeline->cs,
1885 MAX_VERTEX_ATTRIBS * 5 + 2, &vi_cs);
1886 tu6_emit_vertex_input(
1887 &vi_cs, &vs->variants[1], vi_info, pipeline->vi.binning_bindings,
1888 pipeline->vi.binning_strides, pipeline->vi.binning_offsets,
1889 &pipeline->vi.binning_count);
1890 pipeline->vi.binning_state_ib =
1891 tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
1892 }
1893 }
1894
1895 static void
1896 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder *builder,
1897 struct tu_pipeline *pipeline)
1898 {
1899 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1900 builder->create_info->pInputAssemblyState;
1901
1902 pipeline->ia.primtype = tu6_primtype(ia_info->topology);
1903 pipeline->ia.primitive_restart = ia_info->primitiveRestartEnable;
1904 }
1905
1906 static void
1907 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder *builder,
1908 struct tu_pipeline *pipeline)
1909 {
1910 /* The spec says:
1911 *
1912 * pViewportState is a pointer to an instance of the
1913 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
1914 * pipeline has rasterization disabled."
1915 *
1916 * We leave the relevant registers stale in that case.
1917 */
1918 if (builder->rasterizer_discard)
1919 return;
1920
1921 const VkPipelineViewportStateCreateInfo *vp_info =
1922 builder->create_info->pViewportState;
1923
1924 struct tu_cs vp_cs;
1925 tu_cs_begin_sub_stream(&pipeline->cs, 21, &vp_cs);
1926
1927 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_VIEWPORT)) {
1928 assert(vp_info->viewportCount == 1);
1929 tu6_emit_viewport(&vp_cs, vp_info->pViewports);
1930 }
1931
1932 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_SCISSOR)) {
1933 assert(vp_info->scissorCount == 1);
1934 tu6_emit_scissor(&vp_cs, vp_info->pScissors);
1935 }
1936
1937 pipeline->vp.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vp_cs);
1938 }
1939
1940 static void
1941 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder,
1942 struct tu_pipeline *pipeline)
1943 {
1944 const VkPipelineRasterizationStateCreateInfo *rast_info =
1945 builder->create_info->pRasterizationState;
1946
1947 assert(rast_info->polygonMode == VK_POLYGON_MODE_FILL);
1948
1949 struct tu_cs rast_cs;
1950 tu_cs_begin_sub_stream(&pipeline->cs, 20, &rast_cs);
1951
1952
1953 tu_cs_emit_regs(&rast_cs,
1954 A6XX_GRAS_CL_CNTL(
1955 .znear_clip_disable = rast_info->depthClampEnable,
1956 .zfar_clip_disable = rast_info->depthClampEnable,
1957 .unk5 = rast_info->depthClampEnable,
1958 .zero_gb_scale_z = 1,
1959 .vp_clip_code_ignore = 1));
1960 /* move to hw ctx init? */
1961 tu6_emit_gras_unknowns(&rast_cs);
1962 tu6_emit_point_size(&rast_cs);
1963
1964 const uint32_t gras_su_cntl =
1965 tu6_gras_su_cntl(rast_info, builder->samples);
1966
1967 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH))
1968 tu6_emit_gras_su_cntl(&rast_cs, gras_su_cntl, rast_info->lineWidth);
1969
1970 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_DEPTH_BIAS)) {
1971 tu6_emit_depth_bias(&rast_cs, rast_info->depthBiasConstantFactor,
1972 rast_info->depthBiasClamp,
1973 rast_info->depthBiasSlopeFactor);
1974 }
1975
1976 pipeline->rast.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &rast_cs);
1977
1978 pipeline->rast.gras_su_cntl = gras_su_cntl;
1979 }
1980
1981 static void
1982 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
1983 struct tu_pipeline *pipeline)
1984 {
1985 /* The spec says:
1986 *
1987 * pDepthStencilState is a pointer to an instance of the
1988 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
1989 * the pipeline has rasterization disabled or if the subpass of the
1990 * render pass the pipeline is created against does not use a
1991 * depth/stencil attachment.
1992 *
1993 * We disable both depth and stenil tests in those cases.
1994 */
1995 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info;
1996 const VkPipelineDepthStencilStateCreateInfo *ds_info =
1997 builder->use_depth_stencil_attachment
1998 ? builder->create_info->pDepthStencilState
1999 : &dummy_ds_info;
2000
2001 struct tu_cs ds_cs;
2002 tu_cs_begin_sub_stream(&pipeline->cs, 12, &ds_cs);
2003
2004 /* move to hw ctx init? */
2005 tu6_emit_alpha_control_disable(&ds_cs);
2006
2007 tu6_emit_depth_control(&ds_cs, ds_info, builder->create_info->pRasterizationState);
2008 tu6_emit_stencil_control(&ds_cs, ds_info);
2009
2010 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
2011 tu6_emit_stencil_compare_mask(&ds_cs, ds_info->front.compareMask,
2012 ds_info->back.compareMask);
2013 }
2014 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
2015 tu6_emit_stencil_write_mask(&ds_cs, ds_info->front.writeMask,
2016 ds_info->back.writeMask);
2017 }
2018 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
2019 tu6_emit_stencil_reference(&ds_cs, ds_info->front.reference,
2020 ds_info->back.reference);
2021 }
2022
2023 pipeline->ds.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &ds_cs);
2024 }
2025
2026 static void
2027 tu_pipeline_builder_parse_multisample_and_color_blend(
2028 struct tu_pipeline_builder *builder, struct tu_pipeline *pipeline)
2029 {
2030 /* The spec says:
2031 *
2032 * pMultisampleState is a pointer to an instance of the
2033 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
2034 * has rasterization disabled.
2035 *
2036 * Also,
2037 *
2038 * pColorBlendState is a pointer to an instance of the
2039 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
2040 * pipeline has rasterization disabled or if the subpass of the render
2041 * pass the pipeline is created against does not use any color
2042 * attachments.
2043 *
2044 * We leave the relevant registers stale when rasterization is disabled.
2045 */
2046 if (builder->rasterizer_discard)
2047 return;
2048
2049 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info;
2050 const VkPipelineMultisampleStateCreateInfo *msaa_info =
2051 builder->create_info->pMultisampleState;
2052 const VkPipelineColorBlendStateCreateInfo *blend_info =
2053 builder->use_color_attachments ? builder->create_info->pColorBlendState
2054 : &dummy_blend_info;
2055
2056 struct tu_cs blend_cs;
2057 tu_cs_begin_sub_stream(&pipeline->cs, MAX_RTS * 3 + 9, &blend_cs);
2058
2059 uint32_t blend_enable_mask;
2060 tu6_emit_rb_mrt_controls(&blend_cs, blend_info,
2061 builder->color_attachment_formats,
2062 &blend_enable_mask);
2063
2064 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_BLEND_CONSTANTS))
2065 tu6_emit_blend_constants(&blend_cs, blend_info->blendConstants);
2066
2067 tu6_emit_blend_control(&blend_cs, blend_enable_mask, msaa_info);
2068
2069 pipeline->blend.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &blend_cs);
2070 }
2071
2072 static void
2073 tu_pipeline_finish(struct tu_pipeline *pipeline,
2074 struct tu_device *dev,
2075 const VkAllocationCallbacks *alloc)
2076 {
2077 tu_cs_finish(&pipeline->cs);
2078
2079 if (pipeline->program.binary_bo.gem_handle)
2080 tu_bo_finish(dev, &pipeline->program.binary_bo);
2081 }
2082
2083 static VkResult
2084 tu_pipeline_builder_build(struct tu_pipeline_builder *builder,
2085 struct tu_pipeline **pipeline)
2086 {
2087 VkResult result = tu_pipeline_create(builder->device, builder->alloc,
2088 pipeline);
2089 if (result != VK_SUCCESS)
2090 return result;
2091
2092 /* compile and upload shaders */
2093 result = tu_pipeline_builder_compile_shaders(builder);
2094 if (result == VK_SUCCESS)
2095 result = tu_pipeline_builder_upload_shaders(builder, *pipeline);
2096 if (result != VK_SUCCESS) {
2097 tu_pipeline_finish(*pipeline, builder->device, builder->alloc);
2098 vk_free2(&builder->device->alloc, builder->alloc, *pipeline);
2099 *pipeline = VK_NULL_HANDLE;
2100
2101 return result;
2102 }
2103
2104 tu_pipeline_builder_parse_dynamic(builder, *pipeline);
2105 tu_pipeline_builder_parse_shader_stages(builder, *pipeline);
2106 tu_pipeline_builder_parse_vertex_input(builder, *pipeline);
2107 tu_pipeline_builder_parse_input_assembly(builder, *pipeline);
2108 tu_pipeline_builder_parse_viewport(builder, *pipeline);
2109 tu_pipeline_builder_parse_rasterization(builder, *pipeline);
2110 tu_pipeline_builder_parse_depth_stencil(builder, *pipeline);
2111 tu_pipeline_builder_parse_multisample_and_color_blend(builder, *pipeline);
2112
2113 /* we should have reserved enough space upfront such that the CS never
2114 * grows
2115 */
2116 assert((*pipeline)->cs.bo_count == 1);
2117
2118 return VK_SUCCESS;
2119 }
2120
2121 static void
2122 tu_pipeline_builder_finish(struct tu_pipeline_builder *builder)
2123 {
2124 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
2125 if (!builder->shaders[i])
2126 continue;
2127 tu_shader_destroy(builder->device, builder->shaders[i], builder->alloc);
2128 }
2129 }
2130
2131 static void
2132 tu_pipeline_builder_init_graphics(
2133 struct tu_pipeline_builder *builder,
2134 struct tu_device *dev,
2135 struct tu_pipeline_cache *cache,
2136 const VkGraphicsPipelineCreateInfo *create_info,
2137 const VkAllocationCallbacks *alloc)
2138 {
2139 TU_FROM_HANDLE(tu_pipeline_layout, layout, create_info->layout);
2140
2141 *builder = (struct tu_pipeline_builder) {
2142 .device = dev,
2143 .cache = cache,
2144 .create_info = create_info,
2145 .alloc = alloc,
2146 .layout = layout,
2147 };
2148
2149 builder->rasterizer_discard =
2150 create_info->pRasterizationState->rasterizerDiscardEnable;
2151
2152 if (builder->rasterizer_discard) {
2153 builder->samples = VK_SAMPLE_COUNT_1_BIT;
2154 } else {
2155 builder->samples = create_info->pMultisampleState->rasterizationSamples;
2156
2157 const struct tu_render_pass *pass =
2158 tu_render_pass_from_handle(create_info->renderPass);
2159 const struct tu_subpass *subpass =
2160 &pass->subpasses[create_info->subpass];
2161
2162 builder->use_depth_stencil_attachment =
2163 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED;
2164
2165 assert(subpass->color_count == 0 ||
2166 !create_info->pColorBlendState ||
2167 subpass->color_count == create_info->pColorBlendState->attachmentCount);
2168 builder->color_attachment_count = subpass->color_count;
2169 for (uint32_t i = 0; i < subpass->color_count; i++) {
2170 const uint32_t a = subpass->color_attachments[i].attachment;
2171 if (a == VK_ATTACHMENT_UNUSED)
2172 continue;
2173
2174 builder->color_attachment_formats[i] = pass->attachments[a].format;
2175 builder->use_color_attachments = true;
2176 }
2177 }
2178 }
2179
2180 static VkResult
2181 tu_graphics_pipeline_create(VkDevice device,
2182 VkPipelineCache pipelineCache,
2183 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2184 const VkAllocationCallbacks *pAllocator,
2185 VkPipeline *pPipeline)
2186 {
2187 TU_FROM_HANDLE(tu_device, dev, device);
2188 TU_FROM_HANDLE(tu_pipeline_cache, cache, pipelineCache);
2189
2190 struct tu_pipeline_builder builder;
2191 tu_pipeline_builder_init_graphics(&builder, dev, cache,
2192 pCreateInfo, pAllocator);
2193
2194 struct tu_pipeline *pipeline = NULL;
2195 VkResult result = tu_pipeline_builder_build(&builder, &pipeline);
2196 tu_pipeline_builder_finish(&builder);
2197
2198 if (result == VK_SUCCESS)
2199 *pPipeline = tu_pipeline_to_handle(pipeline);
2200 else
2201 *pPipeline = VK_NULL_HANDLE;
2202
2203 return result;
2204 }
2205
2206 VkResult
2207 tu_CreateGraphicsPipelines(VkDevice device,
2208 VkPipelineCache pipelineCache,
2209 uint32_t count,
2210 const VkGraphicsPipelineCreateInfo *pCreateInfos,
2211 const VkAllocationCallbacks *pAllocator,
2212 VkPipeline *pPipelines)
2213 {
2214 VkResult final_result = VK_SUCCESS;
2215
2216 for (uint32_t i = 0; i < count; i++) {
2217 VkResult result = tu_graphics_pipeline_create(device, pipelineCache,
2218 &pCreateInfos[i], pAllocator,
2219 &pPipelines[i]);
2220
2221 if (result != VK_SUCCESS)
2222 final_result = result;
2223 }
2224
2225 return final_result;
2226 }
2227
2228 static void
2229 tu6_emit_compute_program(struct tu_cs *cs,
2230 struct tu_shader *shader,
2231 const struct tu_bo *binary_bo)
2232 {
2233 const struct ir3_shader_variant *v = &shader->variants[0];
2234
2235 tu6_emit_cs_config(cs, shader, v);
2236
2237 /* The compute program is the only one in the pipeline, so 0 offset. */
2238 tu6_emit_shader_object(cs, MESA_SHADER_COMPUTE, v, binary_bo, 0);
2239
2240 tu6_emit_immediates(cs, v, CP_LOAD_STATE6_FRAG, SB6_CS_SHADER);
2241 }
2242
2243 static VkResult
2244 tu_compute_upload_shader(VkDevice device,
2245 struct tu_pipeline *pipeline,
2246 struct tu_shader *shader)
2247 {
2248 TU_FROM_HANDLE(tu_device, dev, device);
2249 struct tu_bo *bo = &pipeline->program.binary_bo;
2250 struct ir3_shader_variant *v = &shader->variants[0];
2251
2252 uint32_t shader_size = sizeof(uint32_t) * v->info.sizedwords;
2253 VkResult result =
2254 tu_bo_init_new(dev, bo, shader_size);
2255 if (result != VK_SUCCESS)
2256 return result;
2257
2258 result = tu_bo_map(dev, bo);
2259 if (result != VK_SUCCESS)
2260 return result;
2261
2262 memcpy(bo->map, shader->binary, shader_size);
2263
2264 return VK_SUCCESS;
2265 }
2266
2267
2268 static VkResult
2269 tu_compute_pipeline_create(VkDevice device,
2270 VkPipelineCache _cache,
2271 const VkComputePipelineCreateInfo *pCreateInfo,
2272 const VkAllocationCallbacks *pAllocator,
2273 VkPipeline *pPipeline)
2274 {
2275 TU_FROM_HANDLE(tu_device, dev, device);
2276 TU_FROM_HANDLE(tu_pipeline_layout, layout, pCreateInfo->layout);
2277 const VkPipelineShaderStageCreateInfo *stage_info = &pCreateInfo->stage;
2278 VkResult result;
2279
2280 struct tu_pipeline *pipeline;
2281
2282 *pPipeline = VK_NULL_HANDLE;
2283
2284 result = tu_pipeline_create(dev, pAllocator, &pipeline);
2285 if (result != VK_SUCCESS)
2286 return result;
2287
2288 pipeline->layout = layout;
2289
2290 struct tu_shader_compile_options options;
2291 tu_shader_compile_options_init(&options, NULL);
2292
2293 struct tu_shader *shader =
2294 tu_shader_create(dev, MESA_SHADER_COMPUTE, stage_info, layout, pAllocator);
2295 if (!shader) {
2296 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2297 goto fail;
2298 }
2299
2300 result = tu_shader_compile(dev, shader, NULL, &options, pAllocator);
2301 if (result != VK_SUCCESS)
2302 goto fail;
2303
2304 struct ir3_shader_variant *v = &shader->variants[0];
2305
2306 tu_pipeline_set_linkage(&pipeline->program.link[MESA_SHADER_COMPUTE],
2307 shader, v);
2308
2309 result = tu_compute_upload_shader(device, pipeline, shader);
2310 if (result != VK_SUCCESS)
2311 goto fail;
2312
2313 for (int i = 0; i < 3; i++)
2314 pipeline->compute.local_size[i] = v->shader->nir->info.cs.local_size[i];
2315
2316 struct tu_cs prog_cs;
2317 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2318 tu6_emit_compute_program(&prog_cs, shader, &pipeline->program.binary_bo);
2319 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2320
2321 *pPipeline = tu_pipeline_to_handle(pipeline);
2322 return VK_SUCCESS;
2323
2324 fail:
2325 if (shader)
2326 tu_shader_destroy(dev, shader, pAllocator);
2327
2328 tu_pipeline_finish(pipeline, dev, pAllocator);
2329 vk_free2(&dev->alloc, pAllocator, pipeline);
2330
2331 return result;
2332 }
2333
2334 VkResult
2335 tu_CreateComputePipelines(VkDevice device,
2336 VkPipelineCache pipelineCache,
2337 uint32_t count,
2338 const VkComputePipelineCreateInfo *pCreateInfos,
2339 const VkAllocationCallbacks *pAllocator,
2340 VkPipeline *pPipelines)
2341 {
2342 VkResult final_result = VK_SUCCESS;
2343
2344 for (uint32_t i = 0; i < count; i++) {
2345 VkResult result = tu_compute_pipeline_create(device, pipelineCache,
2346 &pCreateInfos[i],
2347 pAllocator, &pPipelines[i]);
2348 if (result != VK_SUCCESS)
2349 final_result = result;
2350 }
2351
2352 return final_result;
2353 }
2354
2355 void
2356 tu_DestroyPipeline(VkDevice _device,
2357 VkPipeline _pipeline,
2358 const VkAllocationCallbacks *pAllocator)
2359 {
2360 TU_FROM_HANDLE(tu_device, dev, _device);
2361 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
2362
2363 if (!_pipeline)
2364 return;
2365
2366 tu_pipeline_finish(pipeline, dev, pAllocator);
2367 vk_free2(&dev->alloc, pAllocator, pipeline);
2368 }