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turnip: Refactor the graphics pipeline create implementation.
[mesa.git] / src / freedreno / vulkan / tu_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "main/menums.h"
31 #include "nir/nir.h"
32 #include "nir/nir_builder.h"
33 #include "spirv/nir_spirv.h"
34 #include "util/debug.h"
35 #include "util/mesa-sha1.h"
36 #include "util/u_atomic.h"
37 #include "vk_format.h"
38 #include "vk_util.h"
39
40 #include "tu_cs.h"
41
42 struct tu_pipeline_builder
43 {
44 struct tu_device *device;
45 struct tu_pipeline_cache *cache;
46 const VkAllocationCallbacks *alloc;
47 const VkGraphicsPipelineCreateInfo *create_info;
48
49 struct tu_shader *shaders[MESA_SHADER_STAGES];
50 uint32_t shader_offsets[MESA_SHADER_STAGES];
51 uint32_t binning_vs_offset;
52 uint32_t shader_total_size;
53
54 bool rasterizer_discard;
55 /* these states are affectd by rasterizer_discard */
56 VkSampleCountFlagBits samples;
57 bool use_depth_stencil_attachment;
58 bool use_color_attachments;
59 uint32_t color_attachment_count;
60 VkFormat color_attachment_formats[MAX_RTS];
61 };
62
63 static enum tu_dynamic_state_bits
64 tu_dynamic_state_bit(VkDynamicState state)
65 {
66 switch (state) {
67 case VK_DYNAMIC_STATE_VIEWPORT:
68 return TU_DYNAMIC_VIEWPORT;
69 case VK_DYNAMIC_STATE_SCISSOR:
70 return TU_DYNAMIC_SCISSOR;
71 case VK_DYNAMIC_STATE_LINE_WIDTH:
72 return TU_DYNAMIC_LINE_WIDTH;
73 case VK_DYNAMIC_STATE_DEPTH_BIAS:
74 return TU_DYNAMIC_DEPTH_BIAS;
75 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
76 return TU_DYNAMIC_BLEND_CONSTANTS;
77 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
78 return TU_DYNAMIC_DEPTH_BOUNDS;
79 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
80 return TU_DYNAMIC_STENCIL_COMPARE_MASK;
81 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
82 return TU_DYNAMIC_STENCIL_WRITE_MASK;
83 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
84 return TU_DYNAMIC_STENCIL_REFERENCE;
85 default:
86 unreachable("invalid dynamic state");
87 return 0;
88 }
89 }
90
91 static gl_shader_stage
92 tu_shader_stage(VkShaderStageFlagBits stage)
93 {
94 switch (stage) {
95 case VK_SHADER_STAGE_VERTEX_BIT:
96 return MESA_SHADER_VERTEX;
97 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
98 return MESA_SHADER_TESS_CTRL;
99 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
100 return MESA_SHADER_TESS_EVAL;
101 case VK_SHADER_STAGE_GEOMETRY_BIT:
102 return MESA_SHADER_GEOMETRY;
103 case VK_SHADER_STAGE_FRAGMENT_BIT:
104 return MESA_SHADER_FRAGMENT;
105 case VK_SHADER_STAGE_COMPUTE_BIT:
106 return MESA_SHADER_COMPUTE;
107 default:
108 unreachable("invalid VkShaderStageFlagBits");
109 return MESA_SHADER_NONE;
110 }
111 }
112
113 static const VkVertexInputAttributeDescription *
114 tu_find_vertex_input_attribute(
115 const VkPipelineVertexInputStateCreateInfo *vi_info, uint32_t slot)
116 {
117 assert(slot >= VERT_ATTRIB_GENERIC0);
118 slot -= VERT_ATTRIB_GENERIC0;
119 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
120 if (vi_info->pVertexAttributeDescriptions[i].location == slot)
121 return &vi_info->pVertexAttributeDescriptions[i];
122 }
123 return NULL;
124 }
125
126 static const VkVertexInputBindingDescription *
127 tu_find_vertex_input_binding(
128 const VkPipelineVertexInputStateCreateInfo *vi_info,
129 const VkVertexInputAttributeDescription *vi_attr)
130 {
131 assert(vi_attr);
132 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
133 if (vi_info->pVertexBindingDescriptions[i].binding == vi_attr->binding)
134 return &vi_info->pVertexBindingDescriptions[i];
135 }
136 return NULL;
137 }
138
139 static bool
140 tu_logic_op_reads_dst(VkLogicOp op)
141 {
142 switch (op) {
143 case VK_LOGIC_OP_CLEAR:
144 case VK_LOGIC_OP_COPY:
145 case VK_LOGIC_OP_COPY_INVERTED:
146 case VK_LOGIC_OP_SET:
147 return false;
148 default:
149 return true;
150 }
151 }
152
153 static VkBlendFactor
154 tu_blend_factor_no_dst_alpha(VkBlendFactor factor)
155 {
156 /* treat dst alpha as 1.0 and avoid reading it */
157 switch (factor) {
158 case VK_BLEND_FACTOR_DST_ALPHA:
159 return VK_BLEND_FACTOR_ONE;
160 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
161 return VK_BLEND_FACTOR_ZERO;
162 default:
163 return factor;
164 }
165 }
166
167 static enum pc_di_primtype
168 tu6_primtype(VkPrimitiveTopology topology)
169 {
170 switch (topology) {
171 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
172 return DI_PT_POINTLIST;
173 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
174 return DI_PT_LINELIST;
175 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
176 return DI_PT_LINESTRIP;
177 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
178 return DI_PT_TRILIST;
179 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
180 return DI_PT_TRISTRIP;
181 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
182 return DI_PT_TRIFAN;
183 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
184 return DI_PT_LINE_ADJ;
185 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
186 return DI_PT_LINESTRIP_ADJ;
187 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
188 return DI_PT_TRI_ADJ;
189 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
190 return DI_PT_TRISTRIP_ADJ;
191 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
192 default:
193 unreachable("invalid primitive topology");
194 return DI_PT_NONE;
195 }
196 }
197
198 static enum adreno_compare_func
199 tu6_compare_func(VkCompareOp op)
200 {
201 switch (op) {
202 case VK_COMPARE_OP_NEVER:
203 return FUNC_NEVER;
204 case VK_COMPARE_OP_LESS:
205 return FUNC_LESS;
206 case VK_COMPARE_OP_EQUAL:
207 return FUNC_EQUAL;
208 case VK_COMPARE_OP_LESS_OR_EQUAL:
209 return FUNC_LEQUAL;
210 case VK_COMPARE_OP_GREATER:
211 return FUNC_GREATER;
212 case VK_COMPARE_OP_NOT_EQUAL:
213 return FUNC_NOTEQUAL;
214 case VK_COMPARE_OP_GREATER_OR_EQUAL:
215 return FUNC_GEQUAL;
216 case VK_COMPARE_OP_ALWAYS:
217 return FUNC_ALWAYS;
218 default:
219 unreachable("invalid VkCompareOp");
220 return FUNC_NEVER;
221 }
222 }
223
224 static enum adreno_stencil_op
225 tu6_stencil_op(VkStencilOp op)
226 {
227 switch (op) {
228 case VK_STENCIL_OP_KEEP:
229 return STENCIL_KEEP;
230 case VK_STENCIL_OP_ZERO:
231 return STENCIL_ZERO;
232 case VK_STENCIL_OP_REPLACE:
233 return STENCIL_REPLACE;
234 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
235 return STENCIL_INCR_CLAMP;
236 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
237 return STENCIL_DECR_CLAMP;
238 case VK_STENCIL_OP_INVERT:
239 return STENCIL_INVERT;
240 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
241 return STENCIL_INCR_WRAP;
242 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
243 return STENCIL_DECR_WRAP;
244 default:
245 unreachable("invalid VkStencilOp");
246 return STENCIL_KEEP;
247 }
248 }
249
250 static enum a3xx_rop_code
251 tu6_rop(VkLogicOp op)
252 {
253 switch (op) {
254 case VK_LOGIC_OP_CLEAR:
255 return ROP_CLEAR;
256 case VK_LOGIC_OP_AND:
257 return ROP_AND;
258 case VK_LOGIC_OP_AND_REVERSE:
259 return ROP_AND_REVERSE;
260 case VK_LOGIC_OP_COPY:
261 return ROP_COPY;
262 case VK_LOGIC_OP_AND_INVERTED:
263 return ROP_AND_INVERTED;
264 case VK_LOGIC_OP_NO_OP:
265 return ROP_NOOP;
266 case VK_LOGIC_OP_XOR:
267 return ROP_XOR;
268 case VK_LOGIC_OP_OR:
269 return ROP_OR;
270 case VK_LOGIC_OP_NOR:
271 return ROP_NOR;
272 case VK_LOGIC_OP_EQUIVALENT:
273 return ROP_EQUIV;
274 case VK_LOGIC_OP_INVERT:
275 return ROP_INVERT;
276 case VK_LOGIC_OP_OR_REVERSE:
277 return ROP_OR_REVERSE;
278 case VK_LOGIC_OP_COPY_INVERTED:
279 return ROP_COPY_INVERTED;
280 case VK_LOGIC_OP_OR_INVERTED:
281 return ROP_OR_INVERTED;
282 case VK_LOGIC_OP_NAND:
283 return ROP_NAND;
284 case VK_LOGIC_OP_SET:
285 return ROP_SET;
286 default:
287 unreachable("invalid VkLogicOp");
288 return ROP_NOOP;
289 }
290 }
291
292 static enum adreno_rb_blend_factor
293 tu6_blend_factor(VkBlendFactor factor)
294 {
295 switch (factor) {
296 case VK_BLEND_FACTOR_ZERO:
297 return FACTOR_ZERO;
298 case VK_BLEND_FACTOR_ONE:
299 return FACTOR_ONE;
300 case VK_BLEND_FACTOR_SRC_COLOR:
301 return FACTOR_SRC_COLOR;
302 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
303 return FACTOR_ONE_MINUS_SRC_COLOR;
304 case VK_BLEND_FACTOR_DST_COLOR:
305 return FACTOR_DST_COLOR;
306 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
307 return FACTOR_ONE_MINUS_DST_COLOR;
308 case VK_BLEND_FACTOR_SRC_ALPHA:
309 return FACTOR_SRC_ALPHA;
310 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
311 return FACTOR_ONE_MINUS_SRC_ALPHA;
312 case VK_BLEND_FACTOR_DST_ALPHA:
313 return FACTOR_DST_ALPHA;
314 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
315 return FACTOR_ONE_MINUS_DST_ALPHA;
316 case VK_BLEND_FACTOR_CONSTANT_COLOR:
317 return FACTOR_CONSTANT_COLOR;
318 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
319 return FACTOR_ONE_MINUS_CONSTANT_COLOR;
320 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
321 return FACTOR_CONSTANT_ALPHA;
322 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
323 return FACTOR_ONE_MINUS_CONSTANT_ALPHA;
324 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
325 return FACTOR_SRC_ALPHA_SATURATE;
326 case VK_BLEND_FACTOR_SRC1_COLOR:
327 return FACTOR_SRC1_COLOR;
328 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
329 return FACTOR_ONE_MINUS_SRC1_COLOR;
330 case VK_BLEND_FACTOR_SRC1_ALPHA:
331 return FACTOR_SRC1_ALPHA;
332 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
333 return FACTOR_ONE_MINUS_SRC1_ALPHA;
334 default:
335 unreachable("invalid VkBlendFactor");
336 return FACTOR_ZERO;
337 }
338 }
339
340 static enum a3xx_rb_blend_opcode
341 tu6_blend_op(VkBlendOp op)
342 {
343 switch (op) {
344 case VK_BLEND_OP_ADD:
345 return BLEND_DST_PLUS_SRC;
346 case VK_BLEND_OP_SUBTRACT:
347 return BLEND_SRC_MINUS_DST;
348 case VK_BLEND_OP_REVERSE_SUBTRACT:
349 return BLEND_DST_MINUS_SRC;
350 case VK_BLEND_OP_MIN:
351 return BLEND_MIN_DST_SRC;
352 case VK_BLEND_OP_MAX:
353 return BLEND_MAX_DST_SRC;
354 default:
355 unreachable("invalid VkBlendOp");
356 return BLEND_DST_PLUS_SRC;
357 }
358 }
359
360 static void
361 tu6_emit_vs_config(struct tu_cs *cs, const struct ir3_shader_variant *vs)
362 {
363 uint32_t sp_vs_ctrl =
364 A6XX_SP_VS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
365 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs->info.max_reg + 1) |
366 A6XX_SP_VS_CTRL_REG0_MERGEDREGS |
367 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs->branchstack);
368 if (vs->need_pixlod)
369 sp_vs_ctrl |= A6XX_SP_VS_CTRL_REG0_PIXLODENABLE;
370
371 uint32_t sp_vs_config = A6XX_SP_VS_CONFIG_NTEX(vs->num_samp) |
372 A6XX_SP_VS_CONFIG_NSAMP(vs->num_samp);
373 if (vs->instrlen)
374 sp_vs_config |= A6XX_SP_VS_CONFIG_ENABLED;
375
376 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_CTRL_REG0, 1);
377 tu_cs_emit(cs, sp_vs_ctrl);
378
379 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_CONFIG, 2);
380 tu_cs_emit(cs, sp_vs_config);
381 tu_cs_emit(cs, vs->instrlen);
382
383 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_VS_CNTL, 1);
384 tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(vs->constlen, 4)) |
385 A6XX_HLSQ_VS_CNTL_ENABLED);
386 }
387
388 static void
389 tu6_emit_hs_config(struct tu_cs *cs, const struct ir3_shader_variant *hs)
390 {
391 uint32_t sp_hs_config = 0;
392 if (hs->instrlen)
393 sp_hs_config |= A6XX_SP_HS_CONFIG_ENABLED;
394
395 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
396 tu_cs_emit(cs, 0);
397
398 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_CONFIG, 2);
399 tu_cs_emit(cs, sp_hs_config);
400 tu_cs_emit(cs, hs->instrlen);
401
402 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_HS_CNTL, 1);
403 tu_cs_emit(cs, A6XX_HLSQ_HS_CNTL_CONSTLEN(align(hs->constlen, 4)));
404 }
405
406 static void
407 tu6_emit_ds_config(struct tu_cs *cs, const struct ir3_shader_variant *ds)
408 {
409 uint32_t sp_ds_config = 0;
410 if (ds->instrlen)
411 sp_ds_config |= A6XX_SP_DS_CONFIG_ENABLED;
412
413 tu_cs_emit_pkt4(cs, REG_A6XX_SP_DS_CONFIG, 2);
414 tu_cs_emit(cs, sp_ds_config);
415 tu_cs_emit(cs, ds->instrlen);
416
417 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_DS_CNTL, 1);
418 tu_cs_emit(cs, A6XX_HLSQ_DS_CNTL_CONSTLEN(align(ds->constlen, 4)));
419 }
420
421 static void
422 tu6_emit_gs_config(struct tu_cs *cs, const struct ir3_shader_variant *gs)
423 {
424 uint32_t sp_gs_config = 0;
425 if (gs->instrlen)
426 sp_gs_config |= A6XX_SP_GS_CONFIG_ENABLED;
427
428 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
429 tu_cs_emit(cs, 0);
430
431 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CONFIG, 2);
432 tu_cs_emit(cs, sp_gs_config);
433 tu_cs_emit(cs, gs->instrlen);
434
435 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_GS_CNTL, 1);
436 tu_cs_emit(cs, A6XX_HLSQ_GS_CNTL_CONSTLEN(align(gs->constlen, 4)));
437 }
438
439 static void
440 tu6_emit_fs_config(struct tu_cs *cs, const struct ir3_shader_variant *fs)
441 {
442 uint32_t sp_fs_ctrl =
443 A6XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) | 0x1000000 |
444 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs->info.max_reg + 1) |
445 A6XX_SP_FS_CTRL_REG0_MERGEDREGS |
446 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs->branchstack);
447 if (fs->total_in > 0 || fs->frag_coord)
448 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_VARYING;
449 if (fs->need_pixlod)
450 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_PIXLODENABLE;
451
452 uint32_t sp_fs_config = A6XX_SP_FS_CONFIG_NTEX(fs->num_samp) |
453 A6XX_SP_FS_CONFIG_NSAMP(fs->num_samp) |
454 A6XX_SP_FS_CONFIG_NIBO(fs->image_mapping.num_ibo);
455 if (fs->instrlen)
456 sp_fs_config |= A6XX_SP_FS_CONFIG_ENABLED;
457
458 tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_A9A8, 1);
459 tu_cs_emit(cs, 0);
460
461 tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_AB00, 1);
462 tu_cs_emit(cs, 0x5);
463
464 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_CTRL_REG0, 1);
465 tu_cs_emit(cs, sp_fs_ctrl);
466
467 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_CONFIG, 2);
468 tu_cs_emit(cs, sp_fs_config);
469 tu_cs_emit(cs, fs->instrlen);
470
471 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_FS_CNTL, 1);
472 tu_cs_emit(cs, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(fs->constlen, 4)) |
473 A6XX_HLSQ_FS_CNTL_ENABLED);
474
475 tu_cs_emit_pkt4(cs, REG_A6XX_SP_IBO_COUNT, 1);
476 tu_cs_emit(cs, fs->image_mapping.num_ibo);
477 }
478
479 static void
480 tu6_emit_vs_system_values(struct tu_cs *cs,
481 const struct ir3_shader_variant *vs)
482 {
483 const uint32_t vertexid_regid =
484 ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
485 const uint32_t instanceid_regid =
486 ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
487
488 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_1, 6);
489 tu_cs_emit(cs, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid) |
490 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid) |
491 0xfcfc0000);
492 tu_cs_emit(cs, 0x0000fcfc); /* VFD_CONTROL_2 */
493 tu_cs_emit(cs, 0xfcfcfcfc); /* VFD_CONTROL_3 */
494 tu_cs_emit(cs, 0x000000fc); /* VFD_CONTROL_4 */
495 tu_cs_emit(cs, 0x0000fcfc); /* VFD_CONTROL_5 */
496 tu_cs_emit(cs, 0x00000000); /* VFD_CONTROL_6 */
497 }
498
499 static void
500 tu6_emit_vpc(struct tu_cs *cs,
501 const struct ir3_shader_variant *vs,
502 const struct ir3_shader_variant *fs,
503 bool binning_pass)
504 {
505 struct ir3_shader_linkage linkage = { 0 };
506 ir3_link_shaders(&linkage, vs, fs);
507
508 if (vs->shader->stream_output.num_outputs && !binning_pass)
509 tu_finishme("stream output");
510
511 BITSET_DECLARE(vpc_var_enables, 128) = { 0 };
512 for (uint32_t i = 0; i < linkage.cnt; i++) {
513 const uint32_t comp_count = util_last_bit(linkage.var[i].compmask);
514 for (uint32_t j = 0; j < comp_count; j++)
515 BITSET_SET(vpc_var_enables, linkage.var[i].loc + j);
516 }
517
518 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VAR_DISABLE(0), 4);
519 tu_cs_emit(cs, ~vpc_var_enables[0]);
520 tu_cs_emit(cs, ~vpc_var_enables[1]);
521 tu_cs_emit(cs, ~vpc_var_enables[2]);
522 tu_cs_emit(cs, ~vpc_var_enables[3]);
523
524 /* a6xx finds position/pointsize at the end */
525 const uint32_t position_regid =
526 ir3_find_output_regid(vs, VARYING_SLOT_POS);
527 const uint32_t pointsize_regid =
528 ir3_find_output_regid(vs, VARYING_SLOT_PSIZ);
529 uint32_t pointsize_loc = 0xff, position_loc = 0xff;
530 if (position_regid != regid(63, 0)) {
531 position_loc = linkage.max_loc;
532 ir3_link_add(&linkage, position_regid, 0xf, linkage.max_loc);
533 }
534 if (pointsize_regid != regid(63, 0)) {
535 pointsize_loc = linkage.max_loc;
536 ir3_link_add(&linkage, pointsize_regid, 0x1, linkage.max_loc);
537 }
538
539 /* map vs outputs to VPC */
540 assert(linkage.cnt <= 32);
541 const uint32_t sp_vs_out_count = (linkage.cnt + 1) / 2;
542 const uint32_t sp_vs_vpc_dst_count = (linkage.cnt + 3) / 4;
543 uint32_t sp_vs_out[16];
544 uint32_t sp_vs_vpc_dst[8];
545 sp_vs_out[sp_vs_out_count - 1] = 0;
546 sp_vs_vpc_dst[sp_vs_vpc_dst_count - 1] = 0;
547 for (uint32_t i = 0; i < linkage.cnt; i++) {
548 ((uint16_t *) sp_vs_out)[i] =
549 A6XX_SP_VS_OUT_REG_A_REGID(linkage.var[i].regid) |
550 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage.var[i].compmask);
551 ((uint8_t *) sp_vs_vpc_dst)[i] =
552 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage.var[i].loc);
553 }
554
555 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_OUT_REG(0), sp_vs_out_count);
556 tu_cs_emit_array(cs, sp_vs_out, sp_vs_out_count);
557
558 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_VPC_DST_REG(0), sp_vs_vpc_dst_count);
559 tu_cs_emit_array(cs, sp_vs_vpc_dst, sp_vs_vpc_dst_count);
560
561 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_CNTL_0, 1);
562 tu_cs_emit(cs, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs->total_in) |
563 (fs->total_in > 0 ? A6XX_VPC_CNTL_0_VARYING : 0) |
564 0xff00ff00);
565
566 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK, 1);
567 tu_cs_emit(cs, A6XX_VPC_PACK_POSITIONLOC(position_loc) |
568 A6XX_VPC_PACK_PSIZELOC(pointsize_loc) |
569 A6XX_VPC_PACK_STRIDE_IN_VPC(linkage.max_loc));
570
571 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_GS_SIV_CNTL, 1);
572 tu_cs_emit(cs, 0x0000ffff); /* XXX */
573
574 tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
575 tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage.cnt));
576
577 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
578 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage.max_loc) |
579 (vs->writes_psize ? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE : 0));
580 }
581
582 static int
583 tu6_vpc_varying_mode(const struct ir3_shader_variant *fs,
584 uint32_t index,
585 uint8_t *interp_mode,
586 uint8_t *ps_repl_mode)
587 {
588 enum
589 {
590 INTERP_SMOOTH = 0,
591 INTERP_FLAT = 1,
592 INTERP_ZERO = 2,
593 INTERP_ONE = 3,
594 };
595 enum
596 {
597 PS_REPL_NONE = 0,
598 PS_REPL_S = 1,
599 PS_REPL_T = 2,
600 PS_REPL_ONE_MINUS_T = 3,
601 };
602
603 const uint32_t compmask = fs->inputs[index].compmask;
604
605 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
606 * fourth component occupy three consecutive varying slots
607 */
608 int shift = 0;
609 *interp_mode = 0;
610 *ps_repl_mode = 0;
611 if (fs->inputs[index].slot == VARYING_SLOT_PNTC) {
612 if (compmask & 0x1) {
613 *ps_repl_mode |= PS_REPL_S << shift;
614 shift += 2;
615 }
616 if (compmask & 0x2) {
617 *ps_repl_mode |= PS_REPL_T << shift;
618 shift += 2;
619 }
620 if (compmask & 0x4) {
621 *interp_mode |= INTERP_ZERO << shift;
622 shift += 2;
623 }
624 if (compmask & 0x8) {
625 *interp_mode |= INTERP_ONE << 6;
626 shift += 2;
627 }
628 } else if ((fs->inputs[index].interpolate == INTERP_MODE_FLAT) ||
629 fs->inputs[index].rasterflat) {
630 for (int i = 0; i < 4; i++) {
631 if (compmask & (1 << i)) {
632 *interp_mode |= INTERP_FLAT << shift;
633 shift += 2;
634 }
635 }
636 }
637
638 return shift;
639 }
640
641 static void
642 tu6_emit_vpc_varying_modes(struct tu_cs *cs,
643 const struct ir3_shader_variant *fs,
644 bool binning_pass)
645 {
646 uint32_t interp_modes[8] = { 0 };
647 uint32_t ps_repl_modes[8] = { 0 };
648
649 if (!binning_pass) {
650 for (int i = -1;
651 (i = ir3_next_varying(fs, i)) < (int) fs->inputs_count;) {
652
653 /* get the mode for input i */
654 uint8_t interp_mode;
655 uint8_t ps_repl_mode;
656 const int bits =
657 tu6_vpc_varying_mode(fs, i, &interp_mode, &ps_repl_mode);
658
659 /* OR the mode into the array */
660 const uint32_t inloc = fs->inputs[i].inloc * 2;
661 uint32_t n = inloc / 32;
662 uint32_t shift = inloc % 32;
663 interp_modes[n] |= interp_mode << shift;
664 ps_repl_modes[n] |= ps_repl_mode << shift;
665 if (shift + bits > 32) {
666 n++;
667 shift = 32 - shift;
668
669 interp_modes[n] |= interp_mode >> shift;
670 ps_repl_modes[n] |= ps_repl_mode >> shift;
671 }
672 }
673 }
674
675 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
676 tu_cs_emit_array(cs, interp_modes, 8);
677
678 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
679 tu_cs_emit_array(cs, ps_repl_modes, 8);
680 }
681
682 static void
683 tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
684 {
685 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
686 uint32_t ij_pix_regid, ij_samp_regid, ij_cent_regid, ij_size_regid;
687 uint32_t smask_in_regid;
688
689 bool sample_shading = fs->per_samp; /* TODO | key->sample_shading; */
690 bool enable_varyings = fs->total_in > 0;
691
692 samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
693 smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
694 face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
695 coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
696 zwcoord_regid = VALIDREG(coord_regid) ? coord_regid + 2 : regid(63, 0);
697 ij_pix_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PIXEL);
698 ij_samp_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_SAMPLE);
699 ij_cent_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_CENTROID);
700 ij_size_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_SIZE);
701
702 if (fs->num_sampler_prefetch > 0) {
703 assert(VALIDREG(ij_pix_regid));
704 /* also, it seems like ij_pix is *required* to be r0.x */
705 assert(ij_pix_regid == regid(0, 0));
706 }
707
708 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
709 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
710 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
711 0x7000); // XXX);
712 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
713 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
714 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch->src) |
715 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch->samp_id) |
716 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch->tex_id) |
717 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch->dst) |
718 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch->wrmask) |
719 COND(prefetch->half_precision, A6XX_SP_FS_PREFETCH_CMD_HALF) |
720 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch->cmd));
721 }
722
723 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
724 tu_cs_emit(cs, 0x7);
725 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
726 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
727 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
728 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid));
729 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid) |
730 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid) |
731 0xfc00fc00);
732 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
733 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
734 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid) |
735 0x0000fc00);
736 tu_cs_emit(cs, 0xfc);
737
738 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
739 tu_cs_emit(cs, enable_varyings ? 3 : 1);
740
741 tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_A982, 1);
742 tu_cs_emit(cs, 0); /* XXX */
743
744 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
745 tu_cs_emit(cs, 0xff); /* XXX */
746
747 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CNTL, 1);
748 tu_cs_emit(cs,
749 CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_VARYING) |
750 CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_CENTROID) |
751 CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
752 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
753 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
754 COND(fs->frag_coord,
755 A6XX_GRAS_CNTL_SIZE |
756 A6XX_GRAS_CNTL_XCOORD |
757 A6XX_GRAS_CNTL_YCOORD |
758 A6XX_GRAS_CNTL_ZCOORD |
759 A6XX_GRAS_CNTL_WCOORD) |
760 COND(fs->frag_face, A6XX_GRAS_CNTL_SIZE));
761
762 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CONTROL0, 2);
763 tu_cs_emit(cs,
764 CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_VARYING) |
765 CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_CENTROID) |
766 CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING) |
767 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
768 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
769 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
770 COND(fs->frag_coord,
771 A6XX_RB_RENDER_CONTROL0_SIZE |
772 A6XX_RB_RENDER_CONTROL0_XCOORD |
773 A6XX_RB_RENDER_CONTROL0_YCOORD |
774 A6XX_RB_RENDER_CONTROL0_ZCOORD |
775 A6XX_RB_RENDER_CONTROL0_WCOORD) |
776 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE));
777 tu_cs_emit(cs,
778 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
779 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
780 CONDREG(ij_size_regid, A6XX_RB_RENDER_CONTROL1_SIZE) |
781 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
782 }
783
784 static void
785 tu6_emit_fs_outputs(struct tu_cs *cs,
786 const struct ir3_shader_variant *fs,
787 uint32_t mrt_count)
788 {
789 uint32_t smask_regid, posz_regid;
790
791 posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
792 smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
793
794 uint32_t fragdata_regid[8];
795 if (fs->color0_mrt) {
796 fragdata_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
797 for (uint32_t i = 1; i < ARRAY_SIZE(fragdata_regid); i++)
798 fragdata_regid[i] = fragdata_regid[0];
799 } else {
800 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++)
801 fragdata_regid[i] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0 + i);
802 }
803
804 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_CNTL0, 2);
805 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
806 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
807 0xfc000000);
808 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count));
809
810 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
811 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++) {
812 // TODO we could have a mix of half and full precision outputs,
813 // we really need to figure out half-precision from IR3_REG_HALF
814 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid[i]) |
815 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION : 0));
816 }
817
818 tu_cs_emit_pkt4(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
819 tu_cs_emit(cs, fs->writes_pos ? A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z : 0);
820 tu_cs_emit(cs, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count));
821
822 uint32_t gras_su_depth_plane_cntl = 0;
823 uint32_t rb_depth_plane_cntl = 0;
824 if (fs->no_earlyz | fs->writes_pos) {
825 gras_su_depth_plane_cntl |= A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
826 rb_depth_plane_cntl |= A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
827 }
828
829 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
830 tu_cs_emit(cs, gras_su_depth_plane_cntl);
831
832 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
833 tu_cs_emit(cs, rb_depth_plane_cntl);
834 }
835
836 static void
837 tu6_emit_shader_object(struct tu_cs *cs,
838 gl_shader_stage stage,
839 const struct ir3_shader_variant *variant,
840 const struct tu_bo *binary_bo,
841 uint32_t binary_offset)
842 {
843 uint16_t reg;
844 uint8_t opcode;
845 enum a6xx_state_block sb;
846 switch (stage) {
847 case MESA_SHADER_VERTEX:
848 reg = REG_A6XX_SP_VS_OBJ_START_LO;
849 opcode = CP_LOAD_STATE6_GEOM;
850 sb = SB6_VS_SHADER;
851 break;
852 case MESA_SHADER_TESS_CTRL:
853 reg = REG_A6XX_SP_HS_OBJ_START_LO;
854 opcode = CP_LOAD_STATE6_GEOM;
855 sb = SB6_HS_SHADER;
856 break;
857 case MESA_SHADER_TESS_EVAL:
858 reg = REG_A6XX_SP_DS_OBJ_START_LO;
859 opcode = CP_LOAD_STATE6_GEOM;
860 sb = SB6_DS_SHADER;
861 break;
862 case MESA_SHADER_GEOMETRY:
863 reg = REG_A6XX_SP_GS_OBJ_START_LO;
864 opcode = CP_LOAD_STATE6_GEOM;
865 sb = SB6_GS_SHADER;
866 break;
867 case MESA_SHADER_FRAGMENT:
868 reg = REG_A6XX_SP_FS_OBJ_START_LO;
869 opcode = CP_LOAD_STATE6_FRAG;
870 sb = SB6_FS_SHADER;
871 break;
872 case MESA_SHADER_COMPUTE:
873 reg = REG_A6XX_SP_CS_OBJ_START_LO;
874 opcode = CP_LOAD_STATE6_FRAG;
875 sb = SB6_CS_SHADER;
876 break;
877 default:
878 unreachable("invalid gl_shader_stage");
879 opcode = CP_LOAD_STATE6_GEOM;
880 sb = SB6_VS_SHADER;
881 break;
882 }
883
884 if (!variant->instrlen) {
885 tu_cs_emit_pkt4(cs, reg, 2);
886 tu_cs_emit_qw(cs, 0);
887 return;
888 }
889
890 assert(variant->type == stage);
891
892 const uint64_t binary_iova = binary_bo->iova + binary_offset;
893 assert((binary_iova & 0x3) == 0);
894
895 tu_cs_emit_pkt4(cs, reg, 2);
896 tu_cs_emit_qw(cs, binary_iova);
897
898 /* always indirect */
899 const bool indirect = true;
900 if (indirect) {
901 tu_cs_emit_pkt7(cs, opcode, 3);
902 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
903 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
904 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
905 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
906 CP_LOAD_STATE6_0_NUM_UNIT(variant->instrlen));
907 tu_cs_emit_qw(cs, binary_iova);
908 } else {
909 const void *binary = binary_bo->map + binary_offset;
910
911 tu_cs_emit_pkt7(cs, opcode, 3 + variant->info.sizedwords);
912 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
913 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
914 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
915 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
916 CP_LOAD_STATE6_0_NUM_UNIT(variant->instrlen));
917 tu_cs_emit_qw(cs, 0);
918 tu_cs_emit_array(cs, binary, variant->info.sizedwords);
919 }
920 }
921
922 static void
923 tu6_emit_immediates(struct tu_cs *cs, const struct ir3_shader_variant *v,
924 uint32_t opcode, enum a6xx_state_block block)
925 {
926 /* dummy variant */
927 if (!v->shader)
928 return;
929
930 const struct ir3_const_state *const_state = &v->shader->const_state;
931 uint32_t base = const_state->offsets.immediate;
932 int size = const_state->immediates_count;
933
934 /* truncate size to avoid writing constants that shader
935 * does not use:
936 */
937 size = MIN2(size + base, v->constlen) - base;
938
939 if (size <= 0)
940 return;
941
942 tu_cs_emit_pkt7(cs, opcode, 3 + size * 4);
943 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
944 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
945 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
946 CP_LOAD_STATE6_0_STATE_BLOCK(block) |
947 CP_LOAD_STATE6_0_NUM_UNIT(size));
948 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
949 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
950
951 for (unsigned i = 0; i < size; i++) {
952 tu_cs_emit(cs, const_state->immediates[i].val[0]);
953 tu_cs_emit(cs, const_state->immediates[i].val[1]);
954 tu_cs_emit(cs, const_state->immediates[i].val[2]);
955 tu_cs_emit(cs, const_state->immediates[i].val[3]);
956 }
957 }
958
959 static void
960 tu6_emit_program(struct tu_cs *cs,
961 const struct tu_pipeline_builder *builder,
962 const struct tu_bo *binary_bo,
963 bool binning_pass)
964 {
965 static const struct ir3_shader_variant dummy_variant = {
966 .type = MESA_SHADER_NONE
967 };
968 assert(builder->shaders[MESA_SHADER_VERTEX]);
969 const struct ir3_shader_variant *vs =
970 &builder->shaders[MESA_SHADER_VERTEX]->variants[0];
971 const struct ir3_shader_variant *hs =
972 builder->shaders[MESA_SHADER_TESS_CTRL]
973 ? &builder->shaders[MESA_SHADER_TESS_CTRL]->variants[0]
974 : &dummy_variant;
975 const struct ir3_shader_variant *ds =
976 builder->shaders[MESA_SHADER_TESS_EVAL]
977 ? &builder->shaders[MESA_SHADER_TESS_EVAL]->variants[0]
978 : &dummy_variant;
979 const struct ir3_shader_variant *gs =
980 builder->shaders[MESA_SHADER_GEOMETRY]
981 ? &builder->shaders[MESA_SHADER_GEOMETRY]->variants[0]
982 : &dummy_variant;
983 const struct ir3_shader_variant *fs =
984 builder->shaders[MESA_SHADER_FRAGMENT]
985 ? &builder->shaders[MESA_SHADER_FRAGMENT]->variants[0]
986 : &dummy_variant;
987
988 if (binning_pass) {
989 vs = &builder->shaders[MESA_SHADER_VERTEX]->variants[1];
990 fs = &dummy_variant;
991 }
992
993 tu6_emit_vs_config(cs, vs);
994 tu6_emit_hs_config(cs, hs);
995 tu6_emit_ds_config(cs, ds);
996 tu6_emit_gs_config(cs, gs);
997 tu6_emit_fs_config(cs, fs);
998
999 tu6_emit_vs_system_values(cs, vs);
1000 tu6_emit_vpc(cs, vs, fs, binning_pass);
1001 tu6_emit_vpc_varying_modes(cs, fs, binning_pass);
1002 tu6_emit_fs_inputs(cs, fs);
1003 tu6_emit_fs_outputs(cs, fs, builder->color_attachment_count);
1004
1005 tu6_emit_shader_object(cs, MESA_SHADER_VERTEX, vs, binary_bo,
1006 builder->shader_offsets[MESA_SHADER_VERTEX]);
1007
1008 tu6_emit_shader_object(cs, MESA_SHADER_FRAGMENT, fs, binary_bo,
1009 builder->shader_offsets[MESA_SHADER_FRAGMENT]);
1010
1011 tu6_emit_immediates(cs, vs, CP_LOAD_STATE6_GEOM, SB6_VS_SHADER);
1012 if (!binning_pass)
1013 tu6_emit_immediates(cs, fs, CP_LOAD_STATE6_FRAG, SB6_FS_SHADER);
1014 }
1015
1016 static void
1017 tu6_emit_vertex_input(struct tu_cs *cs,
1018 const struct ir3_shader_variant *vs,
1019 const VkPipelineVertexInputStateCreateInfo *vi_info,
1020 uint8_t bindings[MAX_VERTEX_ATTRIBS],
1021 uint16_t strides[MAX_VERTEX_ATTRIBS],
1022 uint16_t offsets[MAX_VERTEX_ATTRIBS],
1023 uint32_t *count)
1024 {
1025 uint32_t vfd_decode_idx = 0;
1026
1027 for (uint32_t i = 0; i < vs->inputs_count; i++) {
1028 if (vs->inputs[i].sysval || !vs->inputs[i].compmask)
1029 continue;
1030
1031 const VkVertexInputAttributeDescription *vi_attr =
1032 tu_find_vertex_input_attribute(vi_info, vs->inputs[i].slot);
1033 const VkVertexInputBindingDescription *vi_binding =
1034 tu_find_vertex_input_binding(vi_info, vi_attr);
1035 assert(vi_attr && vi_binding);
1036
1037 const struct tu_native_format *format =
1038 tu6_get_native_format(vi_attr->format);
1039 assert(format && format->vtx >= 0);
1040
1041 uint32_t vfd_decode = A6XX_VFD_DECODE_INSTR_IDX(vfd_decode_idx) |
1042 A6XX_VFD_DECODE_INSTR_FORMAT(format->vtx) |
1043 A6XX_VFD_DECODE_INSTR_SWAP(format->swap) |
1044 A6XX_VFD_DECODE_INSTR_UNK30;
1045 if (vi_binding->inputRate == VK_VERTEX_INPUT_RATE_INSTANCE)
1046 vfd_decode |= A6XX_VFD_DECODE_INSTR_INSTANCED;
1047 if (!vk_format_is_int(vi_attr->format))
1048 vfd_decode |= A6XX_VFD_DECODE_INSTR_FLOAT;
1049
1050 const uint32_t vfd_decode_step_rate = 1;
1051
1052 const uint32_t vfd_dest_cntl =
1053 A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vs->inputs[i].compmask) |
1054 A6XX_VFD_DEST_CNTL_INSTR_REGID(vs->inputs[i].regid);
1055
1056 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_DECODE(vfd_decode_idx), 2);
1057 tu_cs_emit(cs, vfd_decode);
1058 tu_cs_emit(cs, vfd_decode_step_rate);
1059
1060 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_DEST_CNTL(vfd_decode_idx), 1);
1061 tu_cs_emit(cs, vfd_dest_cntl);
1062
1063 bindings[vfd_decode_idx] = vi_binding->binding;
1064 strides[vfd_decode_idx] = vi_binding->stride;
1065 offsets[vfd_decode_idx] = vi_attr->offset;
1066
1067 vfd_decode_idx++;
1068 assert(vfd_decode_idx <= MAX_VERTEX_ATTRIBS);
1069 }
1070
1071 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_0, 1);
1072 tu_cs_emit(
1073 cs, A6XX_VFD_CONTROL_0_VTXCNT(vfd_decode_idx) | (vfd_decode_idx << 8));
1074
1075 *count = vfd_decode_idx;
1076 }
1077
1078 static uint32_t
1079 tu6_guardband_adj(uint32_t v)
1080 {
1081 if (v > 256)
1082 return (uint32_t)(511.0 - 65.0 * (log2(v) - 8.0));
1083 else
1084 return 511;
1085 }
1086
1087 void
1088 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport)
1089 {
1090 float offsets[3];
1091 float scales[3];
1092 scales[0] = viewport->width / 2.0f;
1093 scales[1] = viewport->height / 2.0f;
1094 scales[2] = viewport->maxDepth - viewport->minDepth;
1095 offsets[0] = viewport->x + scales[0];
1096 offsets[1] = viewport->y + scales[1];
1097 offsets[2] = viewport->minDepth;
1098
1099 VkOffset2D min;
1100 VkOffset2D max;
1101 min.x = (int32_t) viewport->x;
1102 max.x = (int32_t) ceilf(viewport->x + viewport->width);
1103 if (viewport->height >= 0.0f) {
1104 min.y = (int32_t) viewport->y;
1105 max.y = (int32_t) ceilf(viewport->y + viewport->height);
1106 } else {
1107 min.y = (int32_t)(viewport->y + viewport->height);
1108 max.y = (int32_t) ceilf(viewport->y);
1109 }
1110 /* the spec allows viewport->height to be 0.0f */
1111 if (min.y == max.y)
1112 max.y++;
1113 assert(min.x >= 0 && min.x < max.x);
1114 assert(min.y >= 0 && min.y < max.y);
1115
1116 VkExtent2D guardband_adj;
1117 guardband_adj.width = tu6_guardband_adj(max.x - min.x);
1118 guardband_adj.height = tu6_guardband_adj(max.y - min.y);
1119
1120 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0, 6);
1121 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XOFFSET_0(offsets[0]));
1122 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XSCALE_0(scales[0]));
1123 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YOFFSET_0(offsets[1]));
1124 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YSCALE_0(scales[1]));
1125 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZOFFSET_0(offsets[2]));
1126 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZSCALE_0(scales[2]));
1127
1128 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
1129 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(min.x) |
1130 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(min.y));
1131 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(max.x - 1) |
1132 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(max.y - 1));
1133
1134 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
1135 tu_cs_emit(cs,
1136 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj.width) |
1137 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj.height));
1138 }
1139
1140 void
1141 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor)
1142 {
1143 const VkOffset2D min = scissor->offset;
1144 const VkOffset2D max = {
1145 scissor->offset.x + scissor->extent.width,
1146 scissor->offset.y + scissor->extent.height,
1147 };
1148
1149 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
1150 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(min.x) |
1151 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(min.y));
1152 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(max.x - 1) |
1153 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(max.y - 1));
1154 }
1155
1156 static void
1157 tu6_emit_gras_unknowns(struct tu_cs *cs)
1158 {
1159 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8000, 1);
1160 tu_cs_emit(cs, 0x80);
1161 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8001, 1);
1162 tu_cs_emit(cs, 0x0);
1163 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LAYER_CNTL, 1);
1164 tu_cs_emit(cs, 0x0);
1165 }
1166
1167 static void
1168 tu6_emit_point_size(struct tu_cs *cs)
1169 {
1170 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POINT_MINMAX, 2);
1171 tu_cs_emit(cs, A6XX_GRAS_SU_POINT_MINMAX_MIN(1.0f / 16.0f) |
1172 A6XX_GRAS_SU_POINT_MINMAX_MAX(4092.0f));
1173 tu_cs_emit(cs, A6XX_GRAS_SU_POINT_SIZE(1.0f));
1174 }
1175
1176 static uint32_t
1177 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo *rast_info,
1178 VkSampleCountFlagBits samples)
1179 {
1180 uint32_t gras_su_cntl = 0;
1181
1182 if (rast_info->cullMode & VK_CULL_MODE_FRONT_BIT)
1183 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_FRONT;
1184 if (rast_info->cullMode & VK_CULL_MODE_BACK_BIT)
1185 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_BACK;
1186
1187 if (rast_info->frontFace == VK_FRONT_FACE_CLOCKWISE)
1188 gras_su_cntl |= A6XX_GRAS_SU_CNTL_FRONT_CW;
1189
1190 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1191
1192 if (rast_info->depthBiasEnable)
1193 gras_su_cntl |= A6XX_GRAS_SU_CNTL_POLY_OFFSET;
1194
1195 if (samples > VK_SAMPLE_COUNT_1_BIT)
1196 gras_su_cntl |= A6XX_GRAS_SU_CNTL_MSAA_ENABLE;
1197
1198 return gras_su_cntl;
1199 }
1200
1201 void
1202 tu6_emit_gras_su_cntl(struct tu_cs *cs,
1203 uint32_t gras_su_cntl,
1204 float line_width)
1205 {
1206 assert((gras_su_cntl & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK) == 0);
1207 gras_su_cntl |= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(line_width / 2.0f);
1208
1209 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_CNTL, 1);
1210 tu_cs_emit(cs, gras_su_cntl);
1211 }
1212
1213 void
1214 tu6_emit_depth_bias(struct tu_cs *cs,
1215 float constant_factor,
1216 float clamp,
1217 float slope_factor)
1218 {
1219 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
1220 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor));
1221 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor));
1222 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp));
1223 }
1224
1225 static void
1226 tu6_emit_alpha_control_disable(struct tu_cs *cs)
1227 {
1228 tu_cs_emit_pkt4(cs, REG_A6XX_RB_ALPHA_CONTROL, 1);
1229 tu_cs_emit(cs, 0);
1230 }
1231
1232 static void
1233 tu6_emit_depth_control(struct tu_cs *cs,
1234 const VkPipelineDepthStencilStateCreateInfo *ds_info)
1235 {
1236 assert(!ds_info->depthBoundsTestEnable);
1237
1238 uint32_t rb_depth_cntl = 0;
1239 if (ds_info->depthTestEnable) {
1240 rb_depth_cntl |=
1241 A6XX_RB_DEPTH_CNTL_Z_ENABLE |
1242 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) |
1243 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
1244
1245 if (ds_info->depthWriteEnable)
1246 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
1247 }
1248
1249 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_CNTL, 1);
1250 tu_cs_emit(cs, rb_depth_cntl);
1251 }
1252
1253 static void
1254 tu6_emit_stencil_control(struct tu_cs *cs,
1255 const VkPipelineDepthStencilStateCreateInfo *ds_info)
1256 {
1257 uint32_t rb_stencil_control = 0;
1258 if (ds_info->stencilTestEnable) {
1259 const VkStencilOpState *front = &ds_info->front;
1260 const VkStencilOpState *back = &ds_info->back;
1261 rb_stencil_control |=
1262 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
1263 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
1264 A6XX_RB_STENCIL_CONTROL_STENCIL_READ |
1265 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front->compareOp)) |
1266 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front->failOp)) |
1267 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front->passOp)) |
1268 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front->depthFailOp)) |
1269 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back->compareOp)) |
1270 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back->failOp)) |
1271 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back->passOp)) |
1272 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back->depthFailOp));
1273 }
1274
1275 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_CONTROL, 1);
1276 tu_cs_emit(cs, rb_stencil_control);
1277 }
1278
1279 void
1280 tu6_emit_stencil_compare_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1281 {
1282 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILMASK, 1);
1283 tu_cs_emit(
1284 cs, A6XX_RB_STENCILMASK_MASK(front) | A6XX_RB_STENCILMASK_BFMASK(back));
1285 }
1286
1287 void
1288 tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1289 {
1290 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILWRMASK, 1);
1291 tu_cs_emit(cs, A6XX_RB_STENCILWRMASK_WRMASK(front) |
1292 A6XX_RB_STENCILWRMASK_BFWRMASK(back));
1293 }
1294
1295 void
1296 tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back)
1297 {
1298 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILREF, 1);
1299 tu_cs_emit(cs,
1300 A6XX_RB_STENCILREF_REF(front) | A6XX_RB_STENCILREF_BFREF(back));
1301 }
1302
1303 static uint32_t
1304 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState *att,
1305 bool has_alpha)
1306 {
1307 const enum a3xx_rb_blend_opcode color_op = tu6_blend_op(att->colorBlendOp);
1308 const enum adreno_rb_blend_factor src_color_factor = tu6_blend_factor(
1309 has_alpha ? att->srcColorBlendFactor
1310 : tu_blend_factor_no_dst_alpha(att->srcColorBlendFactor));
1311 const enum adreno_rb_blend_factor dst_color_factor = tu6_blend_factor(
1312 has_alpha ? att->dstColorBlendFactor
1313 : tu_blend_factor_no_dst_alpha(att->dstColorBlendFactor));
1314 const enum a3xx_rb_blend_opcode alpha_op = tu6_blend_op(att->alphaBlendOp);
1315 const enum adreno_rb_blend_factor src_alpha_factor =
1316 tu6_blend_factor(att->srcAlphaBlendFactor);
1317 const enum adreno_rb_blend_factor dst_alpha_factor =
1318 tu6_blend_factor(att->dstAlphaBlendFactor);
1319
1320 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor) |
1321 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op) |
1322 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor) |
1323 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor) |
1324 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op) |
1325 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor);
1326 }
1327
1328 static uint32_t
1329 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState *att,
1330 uint32_t rb_mrt_control_rop,
1331 bool is_int,
1332 bool has_alpha)
1333 {
1334 uint32_t rb_mrt_control =
1335 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att->colorWriteMask);
1336
1337 /* ignore blending and logic op for integer attachments */
1338 if (is_int) {
1339 rb_mrt_control |= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
1340 return rb_mrt_control;
1341 }
1342
1343 rb_mrt_control |= rb_mrt_control_rop;
1344
1345 if (att->blendEnable) {
1346 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND;
1347
1348 if (has_alpha)
1349 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND2;
1350 }
1351
1352 return rb_mrt_control;
1353 }
1354
1355 static void
1356 tu6_emit_rb_mrt_controls(struct tu_cs *cs,
1357 const VkPipelineColorBlendStateCreateInfo *blend_info,
1358 const VkFormat attachment_formats[MAX_RTS],
1359 uint32_t *blend_enable_mask)
1360 {
1361 *blend_enable_mask = 0;
1362
1363 bool rop_reads_dst = false;
1364 uint32_t rb_mrt_control_rop = 0;
1365 if (blend_info->logicOpEnable) {
1366 rop_reads_dst = tu_logic_op_reads_dst(blend_info->logicOp);
1367 rb_mrt_control_rop =
1368 A6XX_RB_MRT_CONTROL_ROP_ENABLE |
1369 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info->logicOp));
1370 }
1371
1372 for (uint32_t i = 0; i < blend_info->attachmentCount; i++) {
1373 const VkPipelineColorBlendAttachmentState *att =
1374 &blend_info->pAttachments[i];
1375 const VkFormat format = attachment_formats[i];
1376
1377 uint32_t rb_mrt_control = 0;
1378 uint32_t rb_mrt_blend_control = 0;
1379 if (format != VK_FORMAT_UNDEFINED) {
1380 const bool is_int = vk_format_is_int(format);
1381 const bool has_alpha = vk_format_has_alpha(format);
1382
1383 rb_mrt_control =
1384 tu6_rb_mrt_control(att, rb_mrt_control_rop, is_int, has_alpha);
1385 rb_mrt_blend_control = tu6_rb_mrt_blend_control(att, has_alpha);
1386
1387 if (att->blendEnable || rop_reads_dst)
1388 *blend_enable_mask |= 1 << i;
1389 }
1390
1391 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
1392 tu_cs_emit(cs, rb_mrt_control);
1393 tu_cs_emit(cs, rb_mrt_blend_control);
1394 }
1395
1396 for (uint32_t i = blend_info->attachmentCount; i < MAX_RTS; i++) {
1397 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
1398 tu_cs_emit(cs, 0);
1399 tu_cs_emit(cs, 0);
1400 }
1401 }
1402
1403 static void
1404 tu6_emit_blend_control(struct tu_cs *cs,
1405 uint32_t blend_enable_mask,
1406 const VkPipelineMultisampleStateCreateInfo *msaa_info)
1407 {
1408 assert(!msaa_info->sampleShadingEnable);
1409 assert(!msaa_info->alphaToOneEnable);
1410
1411 uint32_t sp_blend_cntl = A6XX_SP_BLEND_CNTL_UNK8;
1412 if (blend_enable_mask)
1413 sp_blend_cntl |= A6XX_SP_BLEND_CNTL_ENABLED;
1414 if (msaa_info->alphaToCoverageEnable)
1415 sp_blend_cntl |= A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE;
1416
1417 const uint32_t sample_mask =
1418 msaa_info->pSampleMask ? *msaa_info->pSampleMask
1419 : ((1 << msaa_info->rasterizationSamples) - 1);
1420
1421 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
1422 uint32_t rb_blend_cntl =
1423 A6XX_RB_BLEND_CNTL_ENABLE_BLEND(blend_enable_mask) |
1424 A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND |
1425 A6XX_RB_BLEND_CNTL_SAMPLE_MASK(sample_mask);
1426 if (msaa_info->alphaToCoverageEnable)
1427 rb_blend_cntl |= A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE;
1428
1429 tu_cs_emit_pkt4(cs, REG_A6XX_SP_BLEND_CNTL, 1);
1430 tu_cs_emit(cs, sp_blend_cntl);
1431
1432 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_CNTL, 1);
1433 tu_cs_emit(cs, rb_blend_cntl);
1434 }
1435
1436 void
1437 tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4])
1438 {
1439 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_RED_F32, 4);
1440 tu_cs_emit_array(cs, (const uint32_t *) constants, 4);
1441 }
1442
1443 static VkResult
1444 tu_pipeline_builder_create_pipeline(struct tu_pipeline_builder *builder,
1445 struct tu_pipeline **out_pipeline)
1446 {
1447 struct tu_device *dev = builder->device;
1448
1449 struct tu_pipeline *pipeline =
1450 vk_zalloc2(&dev->alloc, builder->alloc, sizeof(*pipeline), 8,
1451 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1452 if (!pipeline)
1453 return VK_ERROR_OUT_OF_HOST_MEMORY;
1454
1455 tu_cs_init(&pipeline->cs, TU_CS_MODE_SUB_STREAM, 2048);
1456
1457 /* reserve the space now such that tu_cs_begin_sub_stream never fails */
1458 VkResult result = tu_cs_reserve_space(dev, &pipeline->cs, 2048);
1459 if (result != VK_SUCCESS) {
1460 vk_free2(&dev->alloc, builder->alloc, pipeline);
1461 return result;
1462 }
1463
1464 *out_pipeline = pipeline;
1465
1466 return VK_SUCCESS;
1467 }
1468
1469 static VkResult
1470 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder)
1471 {
1472 const VkPipelineShaderStageCreateInfo *stage_infos[MESA_SHADER_STAGES] = {
1473 NULL
1474 };
1475 for (uint32_t i = 0; i < builder->create_info->stageCount; i++) {
1476 gl_shader_stage stage =
1477 tu_shader_stage(builder->create_info->pStages[i].stage);
1478 stage_infos[stage] = &builder->create_info->pStages[i];
1479 }
1480
1481 struct tu_shader_compile_options options;
1482 tu_shader_compile_options_init(&options, builder->create_info);
1483
1484 /* compile shaders in reverse order */
1485 struct tu_shader *next_stage_shader = NULL;
1486 for (gl_shader_stage stage = MESA_SHADER_STAGES - 1;
1487 stage > MESA_SHADER_NONE; stage--) {
1488 const VkPipelineShaderStageCreateInfo *stage_info = stage_infos[stage];
1489 if (!stage_info)
1490 continue;
1491
1492 struct tu_shader *shader =
1493 tu_shader_create(builder->device, stage, stage_info, builder->alloc);
1494 if (!shader)
1495 return VK_ERROR_OUT_OF_HOST_MEMORY;
1496
1497 VkResult result =
1498 tu_shader_compile(builder->device, shader, next_stage_shader,
1499 &options, builder->alloc);
1500 if (result != VK_SUCCESS)
1501 return result;
1502
1503 builder->shaders[stage] = shader;
1504 builder->shader_offsets[stage] = builder->shader_total_size;
1505 builder->shader_total_size +=
1506 sizeof(uint32_t) * shader->variants[0].info.sizedwords;
1507
1508 next_stage_shader = shader;
1509 }
1510
1511 if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
1512 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1513 builder->binning_vs_offset = builder->shader_total_size;
1514 builder->shader_total_size +=
1515 sizeof(uint32_t) * vs->variants[1].info.sizedwords;
1516 }
1517
1518 return VK_SUCCESS;
1519 }
1520
1521 static VkResult
1522 tu_pipeline_builder_upload_shaders(struct tu_pipeline_builder *builder,
1523 struct tu_pipeline *pipeline)
1524 {
1525 struct tu_bo *bo = &pipeline->program.binary_bo;
1526
1527 VkResult result =
1528 tu_bo_init_new(builder->device, bo, builder->shader_total_size);
1529 if (result != VK_SUCCESS)
1530 return result;
1531
1532 result = tu_bo_map(builder->device, bo);
1533 if (result != VK_SUCCESS)
1534 return result;
1535
1536 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
1537 const struct tu_shader *shader = builder->shaders[i];
1538 if (!shader)
1539 continue;
1540
1541 memcpy(bo->map + builder->shader_offsets[i], shader->binary,
1542 sizeof(uint32_t) * shader->variants[0].info.sizedwords);
1543 }
1544
1545 if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
1546 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1547 memcpy(bo->map + builder->binning_vs_offset, vs->binning_binary,
1548 sizeof(uint32_t) * vs->variants[1].info.sizedwords);
1549 }
1550
1551 return VK_SUCCESS;
1552 }
1553
1554 static void
1555 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
1556 struct tu_pipeline *pipeline)
1557 {
1558 const VkPipelineDynamicStateCreateInfo *dynamic_info =
1559 builder->create_info->pDynamicState;
1560
1561 if (!dynamic_info)
1562 return;
1563
1564 for (uint32_t i = 0; i < dynamic_info->dynamicStateCount; i++) {
1565 pipeline->dynamic_state.mask |=
1566 tu_dynamic_state_bit(dynamic_info->pDynamicStates[i]);
1567 }
1568 }
1569
1570 static void
1571 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder *builder,
1572 struct tu_pipeline *pipeline)
1573 {
1574 struct tu_cs prog_cs;
1575 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 512, &prog_cs);
1576 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, false);
1577 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
1578
1579 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 512, &prog_cs);
1580 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, true);
1581 pipeline->program.binning_state_ib =
1582 tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
1583
1584 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
1585 if (!builder->shaders[i])
1586 continue;
1587
1588 struct tu_program_descriptor_linkage *link = &pipeline->program.link[i];
1589 struct ir3_shader *shader = builder->shaders[i]->variants[0].shader;
1590
1591 link->ubo_state = shader->ubo_state;
1592 link->const_state = shader->const_state;
1593 link->constlen = builder->shaders[i]->variants[0].constlen;
1594 link->texture_map = builder->shaders[i]->texture_map;
1595 link->sampler_map = builder->shaders[i]->sampler_map;
1596 link->ubo_map = builder->shaders[i]->ubo_map;
1597 link->ssbo_map = builder->shaders[i]->ssbo_map;
1598 link->image_mapping = builder->shaders[i]->variants[0].image_mapping;
1599 }
1600 }
1601
1602 static void
1603 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder *builder,
1604 struct tu_pipeline *pipeline)
1605 {
1606 const VkPipelineVertexInputStateCreateInfo *vi_info =
1607 builder->create_info->pVertexInputState;
1608 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1609
1610 struct tu_cs vi_cs;
1611 tu_cs_begin_sub_stream(builder->device, &pipeline->cs,
1612 MAX_VERTEX_ATTRIBS * 5 + 2, &vi_cs);
1613 tu6_emit_vertex_input(&vi_cs, &vs->variants[0], vi_info,
1614 pipeline->vi.bindings, pipeline->vi.strides,
1615 pipeline->vi.offsets, &pipeline->vi.count);
1616 pipeline->vi.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
1617
1618 if (vs->has_binning_pass) {
1619 tu_cs_begin_sub_stream(builder->device, &pipeline->cs,
1620 MAX_VERTEX_ATTRIBS * 5 + 2, &vi_cs);
1621 tu6_emit_vertex_input(
1622 &vi_cs, &vs->variants[1], vi_info, pipeline->vi.binning_bindings,
1623 pipeline->vi.binning_strides, pipeline->vi.binning_offsets,
1624 &pipeline->vi.binning_count);
1625 pipeline->vi.binning_state_ib =
1626 tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
1627 }
1628 }
1629
1630 static void
1631 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder *builder,
1632 struct tu_pipeline *pipeline)
1633 {
1634 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1635 builder->create_info->pInputAssemblyState;
1636
1637 pipeline->ia.primtype = tu6_primtype(ia_info->topology);
1638 pipeline->ia.primitive_restart = ia_info->primitiveRestartEnable;
1639 }
1640
1641 static void
1642 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder *builder,
1643 struct tu_pipeline *pipeline)
1644 {
1645 /* The spec says:
1646 *
1647 * pViewportState is a pointer to an instance of the
1648 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
1649 * pipeline has rasterization disabled."
1650 *
1651 * We leave the relevant registers stale in that case.
1652 */
1653 if (builder->rasterizer_discard)
1654 return;
1655
1656 const VkPipelineViewportStateCreateInfo *vp_info =
1657 builder->create_info->pViewportState;
1658
1659 struct tu_cs vp_cs;
1660 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 15, &vp_cs);
1661
1662 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_VIEWPORT)) {
1663 assert(vp_info->viewportCount == 1);
1664 tu6_emit_viewport(&vp_cs, vp_info->pViewports);
1665 }
1666
1667 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_SCISSOR)) {
1668 assert(vp_info->scissorCount == 1);
1669 tu6_emit_scissor(&vp_cs, vp_info->pScissors);
1670 }
1671
1672 pipeline->vp.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vp_cs);
1673 }
1674
1675 static void
1676 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder,
1677 struct tu_pipeline *pipeline)
1678 {
1679 const VkPipelineRasterizationStateCreateInfo *rast_info =
1680 builder->create_info->pRasterizationState;
1681
1682 assert(!rast_info->depthClampEnable);
1683 assert(rast_info->polygonMode == VK_POLYGON_MODE_FILL);
1684
1685 struct tu_cs rast_cs;
1686 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 20, &rast_cs);
1687
1688 /* move to hw ctx init? */
1689 tu6_emit_gras_unknowns(&rast_cs);
1690 tu6_emit_point_size(&rast_cs);
1691
1692 const uint32_t gras_su_cntl =
1693 tu6_gras_su_cntl(rast_info, builder->samples);
1694
1695 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH))
1696 tu6_emit_gras_su_cntl(&rast_cs, gras_su_cntl, rast_info->lineWidth);
1697
1698 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_DEPTH_BIAS)) {
1699 tu6_emit_depth_bias(&rast_cs, rast_info->depthBiasConstantFactor,
1700 rast_info->depthBiasClamp,
1701 rast_info->depthBiasSlopeFactor);
1702 }
1703
1704 pipeline->rast.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &rast_cs);
1705
1706 pipeline->rast.gras_su_cntl = gras_su_cntl;
1707 }
1708
1709 static void
1710 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
1711 struct tu_pipeline *pipeline)
1712 {
1713 /* The spec says:
1714 *
1715 * pDepthStencilState is a pointer to an instance of the
1716 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
1717 * the pipeline has rasterization disabled or if the subpass of the
1718 * render pass the pipeline is created against does not use a
1719 * depth/stencil attachment.
1720 *
1721 * We disable both depth and stenil tests in those cases.
1722 */
1723 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info;
1724 const VkPipelineDepthStencilStateCreateInfo *ds_info =
1725 builder->use_depth_stencil_attachment
1726 ? builder->create_info->pDepthStencilState
1727 : &dummy_ds_info;
1728
1729 struct tu_cs ds_cs;
1730 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 12, &ds_cs);
1731
1732 /* move to hw ctx init? */
1733 tu6_emit_alpha_control_disable(&ds_cs);
1734
1735 tu6_emit_depth_control(&ds_cs, ds_info);
1736 tu6_emit_stencil_control(&ds_cs, ds_info);
1737
1738 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
1739 tu6_emit_stencil_compare_mask(&ds_cs, ds_info->front.compareMask,
1740 ds_info->back.compareMask);
1741 }
1742 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
1743 tu6_emit_stencil_write_mask(&ds_cs, ds_info->front.writeMask,
1744 ds_info->back.writeMask);
1745 }
1746 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
1747 tu6_emit_stencil_reference(&ds_cs, ds_info->front.reference,
1748 ds_info->back.reference);
1749 }
1750
1751 pipeline->ds.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &ds_cs);
1752 }
1753
1754 static void
1755 tu_pipeline_builder_parse_multisample_and_color_blend(
1756 struct tu_pipeline_builder *builder, struct tu_pipeline *pipeline)
1757 {
1758 /* The spec says:
1759 *
1760 * pMultisampleState is a pointer to an instance of the
1761 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
1762 * has rasterization disabled.
1763 *
1764 * Also,
1765 *
1766 * pColorBlendState is a pointer to an instance of the
1767 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
1768 * pipeline has rasterization disabled or if the subpass of the render
1769 * pass the pipeline is created against does not use any color
1770 * attachments.
1771 *
1772 * We leave the relevant registers stale when rasterization is disabled.
1773 */
1774 if (builder->rasterizer_discard)
1775 return;
1776
1777 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info;
1778 const VkPipelineMultisampleStateCreateInfo *msaa_info =
1779 builder->create_info->pMultisampleState;
1780 const VkPipelineColorBlendStateCreateInfo *blend_info =
1781 builder->use_color_attachments ? builder->create_info->pColorBlendState
1782 : &dummy_blend_info;
1783
1784 struct tu_cs blend_cs;
1785 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, MAX_RTS * 3 + 9,
1786 &blend_cs);
1787
1788 uint32_t blend_enable_mask;
1789 tu6_emit_rb_mrt_controls(&blend_cs, blend_info,
1790 builder->color_attachment_formats,
1791 &blend_enable_mask);
1792
1793 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_BLEND_CONSTANTS))
1794 tu6_emit_blend_constants(&blend_cs, blend_info->blendConstants);
1795
1796 tu6_emit_blend_control(&blend_cs, blend_enable_mask, msaa_info);
1797
1798 pipeline->blend.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &blend_cs);
1799 }
1800
1801 static void
1802 tu_pipeline_finish(struct tu_pipeline *pipeline,
1803 struct tu_device *dev,
1804 const VkAllocationCallbacks *alloc)
1805 {
1806 tu_cs_finish(dev, &pipeline->cs);
1807
1808 if (pipeline->program.binary_bo.gem_handle)
1809 tu_bo_finish(dev, &pipeline->program.binary_bo);
1810 }
1811
1812 static VkResult
1813 tu_pipeline_builder_build(struct tu_pipeline_builder *builder,
1814 struct tu_pipeline **pipeline)
1815 {
1816 VkResult result = tu_pipeline_builder_create_pipeline(builder, pipeline);
1817 if (result != VK_SUCCESS)
1818 return result;
1819
1820 /* compile and upload shaders */
1821 result = tu_pipeline_builder_compile_shaders(builder);
1822 if (result == VK_SUCCESS)
1823 result = tu_pipeline_builder_upload_shaders(builder, *pipeline);
1824 if (result != VK_SUCCESS) {
1825 tu_pipeline_finish(*pipeline, builder->device, builder->alloc);
1826 vk_free2(&builder->device->alloc, builder->alloc, *pipeline);
1827 *pipeline = VK_NULL_HANDLE;
1828
1829 return result;
1830 }
1831
1832 tu_pipeline_builder_parse_dynamic(builder, *pipeline);
1833 tu_pipeline_builder_parse_shader_stages(builder, *pipeline);
1834 tu_pipeline_builder_parse_vertex_input(builder, *pipeline);
1835 tu_pipeline_builder_parse_input_assembly(builder, *pipeline);
1836 tu_pipeline_builder_parse_viewport(builder, *pipeline);
1837 tu_pipeline_builder_parse_rasterization(builder, *pipeline);
1838 tu_pipeline_builder_parse_depth_stencil(builder, *pipeline);
1839 tu_pipeline_builder_parse_multisample_and_color_blend(builder, *pipeline);
1840
1841 /* we should have reserved enough space upfront such that the CS never
1842 * grows
1843 */
1844 assert((*pipeline)->cs.bo_count == 1);
1845
1846 return VK_SUCCESS;
1847 }
1848
1849 static void
1850 tu_pipeline_builder_finish(struct tu_pipeline_builder *builder)
1851 {
1852 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
1853 if (!builder->shaders[i])
1854 continue;
1855 tu_shader_destroy(builder->device, builder->shaders[i], builder->alloc);
1856 }
1857 }
1858
1859 static void
1860 tu_pipeline_builder_init_graphics(
1861 struct tu_pipeline_builder *builder,
1862 struct tu_device *dev,
1863 struct tu_pipeline_cache *cache,
1864 const VkGraphicsPipelineCreateInfo *create_info,
1865 const VkAllocationCallbacks *alloc)
1866 {
1867 *builder = (struct tu_pipeline_builder) {
1868 .device = dev,
1869 .cache = cache,
1870 .create_info = create_info,
1871 .alloc = alloc,
1872 };
1873
1874 builder->rasterizer_discard =
1875 create_info->pRasterizationState->rasterizerDiscardEnable;
1876
1877 if (builder->rasterizer_discard) {
1878 builder->samples = VK_SAMPLE_COUNT_1_BIT;
1879 } else {
1880 builder->samples = create_info->pMultisampleState->rasterizationSamples;
1881
1882 const struct tu_render_pass *pass =
1883 tu_render_pass_from_handle(create_info->renderPass);
1884 const struct tu_subpass *subpass =
1885 &pass->subpasses[create_info->subpass];
1886
1887 builder->use_depth_stencil_attachment =
1888 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED;
1889
1890 assert(subpass->color_count == 0 ||
1891 subpass->color_count == create_info->pColorBlendState->attachmentCount);
1892 builder->color_attachment_count = subpass->color_count;
1893 for (uint32_t i = 0; i < subpass->color_count; i++) {
1894 const uint32_t a = subpass->color_attachments[i].attachment;
1895 if (a == VK_ATTACHMENT_UNUSED)
1896 continue;
1897
1898 builder->color_attachment_formats[i] = pass->attachments[a].format;
1899 builder->use_color_attachments = true;
1900 }
1901 }
1902 }
1903
1904 static VkResult
1905 tu_graphics_pipeline_create(VkDevice device,
1906 VkPipelineCache pipelineCache,
1907 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1908 const VkAllocationCallbacks *pAllocator,
1909 VkPipeline *pPipeline)
1910 {
1911 TU_FROM_HANDLE(tu_device, dev, device);
1912 TU_FROM_HANDLE(tu_pipeline_cache, cache, pipelineCache);
1913
1914 struct tu_pipeline_builder builder;
1915 tu_pipeline_builder_init_graphics(&builder, dev, cache,
1916 pCreateInfo, pAllocator);
1917
1918 struct tu_pipeline *pipeline = NULL;
1919 VkResult result = tu_pipeline_builder_build(&builder, &pipeline);
1920 tu_pipeline_builder_finish(&builder);
1921
1922 if (result == VK_SUCCESS)
1923 *pPipeline = tu_pipeline_to_handle(pipeline);
1924 else
1925 *pPipeline = NULL;
1926
1927 return result;
1928 }
1929
1930 VkResult
1931 tu_CreateGraphicsPipelines(VkDevice device,
1932 VkPipelineCache pipelineCache,
1933 uint32_t count,
1934 const VkGraphicsPipelineCreateInfo *pCreateInfos,
1935 const VkAllocationCallbacks *pAllocator,
1936 VkPipeline *pPipelines)
1937 {
1938 VkResult final_result = VK_SUCCESS;
1939
1940 for (uint32_t i = 0; i < count; i++) {
1941 VkResult result = tu_graphics_pipeline_create(device, pipelineCache,
1942 &pCreateInfos[i], pAllocator,
1943 &pPipelines[i]);
1944
1945 if (result != VK_SUCCESS)
1946 final_result = result;
1947 }
1948
1949 return final_result;
1950 }
1951
1952 static VkResult
1953 tu_compute_pipeline_create(VkDevice _device,
1954 VkPipelineCache _cache,
1955 const VkComputePipelineCreateInfo *pCreateInfo,
1956 const VkAllocationCallbacks *pAllocator,
1957 VkPipeline *pPipeline)
1958 {
1959 return VK_SUCCESS;
1960 }
1961
1962 VkResult
1963 tu_CreateComputePipelines(VkDevice _device,
1964 VkPipelineCache pipelineCache,
1965 uint32_t count,
1966 const VkComputePipelineCreateInfo *pCreateInfos,
1967 const VkAllocationCallbacks *pAllocator,
1968 VkPipeline *pPipelines)
1969 {
1970 VkResult result = VK_SUCCESS;
1971
1972 unsigned i = 0;
1973 for (; i < count; i++) {
1974 VkResult r;
1975 r = tu_compute_pipeline_create(_device, pipelineCache, &pCreateInfos[i],
1976 pAllocator, &pPipelines[i]);
1977 if (r != VK_SUCCESS) {
1978 result = r;
1979 }
1980 pPipelines[i] = VK_NULL_HANDLE;
1981 }
1982
1983 return result;
1984 }
1985
1986 void
1987 tu_DestroyPipeline(VkDevice _device,
1988 VkPipeline _pipeline,
1989 const VkAllocationCallbacks *pAllocator)
1990 {
1991 TU_FROM_HANDLE(tu_device, dev, _device);
1992 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
1993
1994 if (!_pipeline)
1995 return;
1996
1997 tu_pipeline_finish(pipeline, dev, pAllocator);
1998 vk_free2(&dev->alloc, pAllocator, pipeline);
1999 }