src/freedreno/vulkan/tu_pipeline.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  */
  27
  28 #include "tu_private.h"
  29
  30 #include "main/menums.h"
  31 #include "nir/nir.h"
  32 #include "nir/nir_builder.h"
  33 #include "spirv/nir_spirv.h"
  34 #include "util/debug.h"
  35 #include "util/mesa-sha1.h"
  36 #include "util/u_atomic.h"
  37 #include "vk_format.h"
  38 #include "vk_util.h"
  39
  40 #include "tu_cs.h"
  41
  42 struct tu_pipeline_builder
  43 {
  44    struct tu_device *device;
  45    struct tu_pipeline_cache *cache;
  46    struct tu_pipeline_layout *layout;
  47    const VkAllocationCallbacks *alloc;
  48    const VkGraphicsPipelineCreateInfo *create_info;
  49
  50    struct tu_shader *shaders[MESA_SHADER_STAGES];
  51    uint32_t shader_offsets[MESA_SHADER_STAGES];
  52    uint32_t binning_vs_offset;
  53    uint32_t shader_total_size;
  54
  55    bool rasterizer_discard;
  56    /* these states are affectd by rasterizer_discard */
  57    VkSampleCountFlagBits samples;
  58    bool use_depth_stencil_attachment;
  59    bool use_color_attachments;
  60    uint32_t color_attachment_count;
  61    VkFormat color_attachment_formats[MAX_RTS];
  62 };
  63
  64 static enum tu_dynamic_state_bits
  65 tu_dynamic_state_bit(VkDynamicState state)
  66 {
  67    switch (state) {
  68    case VK_DYNAMIC_STATE_VIEWPORT:
  69       return TU_DYNAMIC_VIEWPORT;
  70    case VK_DYNAMIC_STATE_SCISSOR:
  71       return TU_DYNAMIC_SCISSOR;
  72    case VK_DYNAMIC_STATE_LINE_WIDTH:
  73       return TU_DYNAMIC_LINE_WIDTH;
  74    case VK_DYNAMIC_STATE_DEPTH_BIAS:
  75       return TU_DYNAMIC_DEPTH_BIAS;
  76    case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
  77       return TU_DYNAMIC_BLEND_CONSTANTS;
  78    case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
  79       return TU_DYNAMIC_DEPTH_BOUNDS;
  80    case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
  81       return TU_DYNAMIC_STENCIL_COMPARE_MASK;
  82    case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
  83       return TU_DYNAMIC_STENCIL_WRITE_MASK;
  84    case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
  85       return TU_DYNAMIC_STENCIL_REFERENCE;
  86    default:
  87       unreachable("invalid dynamic state");
  88       return 0;
  89    }
  90 }
  91
  92 static gl_shader_stage
  93 tu_shader_stage(VkShaderStageFlagBits stage)
  94 {
  95    switch (stage) {
  96    case VK_SHADER_STAGE_VERTEX_BIT:
  97       return MESA_SHADER_VERTEX;
  98    case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
  99       return MESA_SHADER_TESS_CTRL;
 100    case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
 101       return MESA_SHADER_TESS_EVAL;
 102    case VK_SHADER_STAGE_GEOMETRY_BIT:
 103       return MESA_SHADER_GEOMETRY;
 104    case VK_SHADER_STAGE_FRAGMENT_BIT:
 105       return MESA_SHADER_FRAGMENT;
 106    case VK_SHADER_STAGE_COMPUTE_BIT:
 107       return MESA_SHADER_COMPUTE;
 108    default:
 109       unreachable("invalid VkShaderStageFlagBits");
 110       return MESA_SHADER_NONE;
 111    }
 112 }
 113
 114 static const VkVertexInputAttributeDescription *
 115 tu_find_vertex_input_attribute(
 116    const VkPipelineVertexInputStateCreateInfo *vi_info, uint32_t slot)
 117 {
 118    assert(slot >= VERT_ATTRIB_GENERIC0);
 119    slot -= VERT_ATTRIB_GENERIC0;
 120    for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
 121       if (vi_info->pVertexAttributeDescriptions[i].location == slot)
 122          return &vi_info->pVertexAttributeDescriptions[i];
 123    }
 124    return NULL;
 125 }
 126
 127 static const VkVertexInputBindingDescription *
 128 tu_find_vertex_input_binding(
 129    const VkPipelineVertexInputStateCreateInfo *vi_info,
 130    const VkVertexInputAttributeDescription *vi_attr)
 131 {
 132    assert(vi_attr);
 133    for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
 134       if (vi_info->pVertexBindingDescriptions[i].binding == vi_attr->binding)
 135          return &vi_info->pVertexBindingDescriptions[i];
 136    }
 137    return NULL;
 138 }
 139
 140 static bool
 141 tu_logic_op_reads_dst(VkLogicOp op)
 142 {
 143    switch (op) {
 144    case VK_LOGIC_OP_CLEAR:
 145    case VK_LOGIC_OP_COPY:
 146    case VK_LOGIC_OP_COPY_INVERTED:
 147    case VK_LOGIC_OP_SET:
 148       return false;
 149    default:
 150       return true;
 151    }
 152 }
 153
 154 static VkBlendFactor
 155 tu_blend_factor_no_dst_alpha(VkBlendFactor factor)
 156 {
 157    /* treat dst alpha as 1.0 and avoid reading it */
 158    switch (factor) {
 159    case VK_BLEND_FACTOR_DST_ALPHA:
 160       return VK_BLEND_FACTOR_ONE;
 161    case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
 162       return VK_BLEND_FACTOR_ZERO;
 163    default:
 164       return factor;
 165    }
 166 }
 167
 168 static enum pc_di_primtype
 169 tu6_primtype(VkPrimitiveTopology topology)
 170 {
 171    switch (topology) {
 172    case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
 173       return DI_PT_POINTLIST;
 174    case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
 175       return DI_PT_LINELIST;
 176    case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
 177       return DI_PT_LINESTRIP;
 178    case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
 179       return DI_PT_TRILIST;
 180    case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
 181       return DI_PT_TRISTRIP;
 182    case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
 183       return DI_PT_TRIFAN;
 184    case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
 185       return DI_PT_LINE_ADJ;
 186    case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
 187       return DI_PT_LINESTRIP_ADJ;
 188    case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
 189       return DI_PT_TRI_ADJ;
 190    case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
 191       return DI_PT_TRISTRIP_ADJ;
 192    case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
 193    default:
 194       unreachable("invalid primitive topology");
 195       return DI_PT_NONE;
 196    }
 197 }
 198
 199 static enum adreno_compare_func
 200 tu6_compare_func(VkCompareOp op)
 201 {
 202    switch (op) {
 203    case VK_COMPARE_OP_NEVER:
 204       return FUNC_NEVER;
 205    case VK_COMPARE_OP_LESS:
 206       return FUNC_LESS;
 207    case VK_COMPARE_OP_EQUAL:
 208       return FUNC_EQUAL;
 209    case VK_COMPARE_OP_LESS_OR_EQUAL:
 210       return FUNC_LEQUAL;
 211    case VK_COMPARE_OP_GREATER:
 212       return FUNC_GREATER;
 213    case VK_COMPARE_OP_NOT_EQUAL:
 214       return FUNC_NOTEQUAL;
 215    case VK_COMPARE_OP_GREATER_OR_EQUAL:
 216       return FUNC_GEQUAL;
 217    case VK_COMPARE_OP_ALWAYS:
 218       return FUNC_ALWAYS;
 219    default:
 220       unreachable("invalid VkCompareOp");
 221       return FUNC_NEVER;
 222    }
 223 }
 224
 225 static enum adreno_stencil_op
 226 tu6_stencil_op(VkStencilOp op)
 227 {
 228    switch (op) {
 229    case VK_STENCIL_OP_KEEP:
 230       return STENCIL_KEEP;
 231    case VK_STENCIL_OP_ZERO:
 232       return STENCIL_ZERO;
 233    case VK_STENCIL_OP_REPLACE:
 234       return STENCIL_REPLACE;
 235    case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
 236       return STENCIL_INCR_CLAMP;
 237    case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
 238       return STENCIL_DECR_CLAMP;
 239    case VK_STENCIL_OP_INVERT:
 240       return STENCIL_INVERT;
 241    case VK_STENCIL_OP_INCREMENT_AND_WRAP:
 242       return STENCIL_INCR_WRAP;
 243    case VK_STENCIL_OP_DECREMENT_AND_WRAP:
 244       return STENCIL_DECR_WRAP;
 245    default:
 246       unreachable("invalid VkStencilOp");
 247       return STENCIL_KEEP;
 248    }
 249 }
 250
 251 static enum a3xx_rop_code
 252 tu6_rop(VkLogicOp op)
 253 {
 254    switch (op) {
 255    case VK_LOGIC_OP_CLEAR:
 256       return ROP_CLEAR;
 257    case VK_LOGIC_OP_AND:
 258       return ROP_AND;
 259    case VK_LOGIC_OP_AND_REVERSE:
 260       return ROP_AND_REVERSE;
 261    case VK_LOGIC_OP_COPY:
 262       return ROP_COPY;
 263    case VK_LOGIC_OP_AND_INVERTED:
 264       return ROP_AND_INVERTED;
 265    case VK_LOGIC_OP_NO_OP:
 266       return ROP_NOOP;
 267    case VK_LOGIC_OP_XOR:
 268       return ROP_XOR;
 269    case VK_LOGIC_OP_OR:
 270       return ROP_OR;
 271    case VK_LOGIC_OP_NOR:
 272       return ROP_NOR;
 273    case VK_LOGIC_OP_EQUIVALENT:
 274       return ROP_EQUIV;
 275    case VK_LOGIC_OP_INVERT:
 276       return ROP_INVERT;
 277    case VK_LOGIC_OP_OR_REVERSE:
 278       return ROP_OR_REVERSE;
 279    case VK_LOGIC_OP_COPY_INVERTED:
 280       return ROP_COPY_INVERTED;
 281    case VK_LOGIC_OP_OR_INVERTED:
 282       return ROP_OR_INVERTED;
 283    case VK_LOGIC_OP_NAND:
 284       return ROP_NAND;
 285    case VK_LOGIC_OP_SET:
 286       return ROP_SET;
 287    default:
 288       unreachable("invalid VkLogicOp");
 289       return ROP_NOOP;
 290    }
 291 }
 292
 293 static enum adreno_rb_blend_factor
 294 tu6_blend_factor(VkBlendFactor factor)
 295 {
 296    switch (factor) {
 297    case VK_BLEND_FACTOR_ZERO:
 298       return FACTOR_ZERO;
 299    case VK_BLEND_FACTOR_ONE:
 300       return FACTOR_ONE;
 301    case VK_BLEND_FACTOR_SRC_COLOR:
 302       return FACTOR_SRC_COLOR;
 303    case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
 304       return FACTOR_ONE_MINUS_SRC_COLOR;
 305    case VK_BLEND_FACTOR_DST_COLOR:
 306       return FACTOR_DST_COLOR;
 307    case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
 308       return FACTOR_ONE_MINUS_DST_COLOR;
 309    case VK_BLEND_FACTOR_SRC_ALPHA:
 310       return FACTOR_SRC_ALPHA;
 311    case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
 312       return FACTOR_ONE_MINUS_SRC_ALPHA;
 313    case VK_BLEND_FACTOR_DST_ALPHA:
 314       return FACTOR_DST_ALPHA;
 315    case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
 316       return FACTOR_ONE_MINUS_DST_ALPHA;
 317    case VK_BLEND_FACTOR_CONSTANT_COLOR:
 318       return FACTOR_CONSTANT_COLOR;
 319    case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
 320       return FACTOR_ONE_MINUS_CONSTANT_COLOR;
 321    case VK_BLEND_FACTOR_CONSTANT_ALPHA:
 322       return FACTOR_CONSTANT_ALPHA;
 323    case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
 324       return FACTOR_ONE_MINUS_CONSTANT_ALPHA;
 325    case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
 326       return FACTOR_SRC_ALPHA_SATURATE;
 327    case VK_BLEND_FACTOR_SRC1_COLOR:
 328       return FACTOR_SRC1_COLOR;
 329    case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
 330       return FACTOR_ONE_MINUS_SRC1_COLOR;
 331    case VK_BLEND_FACTOR_SRC1_ALPHA:
 332       return FACTOR_SRC1_ALPHA;
 333    case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
 334       return FACTOR_ONE_MINUS_SRC1_ALPHA;
 335    default:
 336       unreachable("invalid VkBlendFactor");
 337       return FACTOR_ZERO;
 338    }
 339 }
 340
 341 static enum a3xx_rb_blend_opcode
 342 tu6_blend_op(VkBlendOp op)
 343 {
 344    switch (op) {
 345    case VK_BLEND_OP_ADD:
 346       return BLEND_DST_PLUS_SRC;
 347    case VK_BLEND_OP_SUBTRACT:
 348       return BLEND_SRC_MINUS_DST;
 349    case VK_BLEND_OP_REVERSE_SUBTRACT:
 350       return BLEND_DST_MINUS_SRC;
 351    case VK_BLEND_OP_MIN:
 352       return BLEND_MIN_DST_SRC;
 353    case VK_BLEND_OP_MAX:
 354       return BLEND_MAX_DST_SRC;
 355    default:
 356       unreachable("invalid VkBlendOp");
 357       return BLEND_DST_PLUS_SRC;
 358    }
 359 }
 360
 361 static unsigned
 362 tu_shader_nibo(const struct tu_shader *shader)
 363 {
 364    /* Don't use ir3_shader_nibo(), because that would include declared but
 365     * unused storage images and SSBOs.
 366     */
 367    return shader->ssbo_map.num_desc + shader->image_map.num_desc;
 368 }
 369
 370 static void
 371 tu6_emit_vs_config(struct tu_cs *cs, struct tu_shader *shader,
 372                    const struct ir3_shader_variant *vs)
 373 {
 374    uint32_t sp_vs_ctrl =
 375       A6XX_SP_VS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
 376       A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs->info.max_reg + 1) |
 377       A6XX_SP_VS_CTRL_REG0_MERGEDREGS |
 378       A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs->branchstack);
 379    if (vs->need_pixlod)
 380       sp_vs_ctrl |= A6XX_SP_VS_CTRL_REG0_PIXLODENABLE;
 381    if (vs->need_fine_derivatives)
 382       sp_vs_ctrl |= A6XX_SP_VS_CTRL_REG0_DIFF_FINE;
 383
 384    uint32_t sp_vs_config = A6XX_SP_VS_CONFIG_NTEX(shader->texture_map.num_desc) |
 385                            A6XX_SP_VS_CONFIG_NSAMP(shader->sampler_map.num_desc);
 386    if (vs->instrlen)
 387       sp_vs_config |= A6XX_SP_VS_CONFIG_ENABLED;
 388
 389    tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_CTRL_REG0, 1);
 390    tu_cs_emit(cs, sp_vs_ctrl);
 391
 392    tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_CONFIG, 2);
 393    tu_cs_emit(cs, sp_vs_config);
 394    tu_cs_emit(cs, vs->instrlen);
 395
 396    tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_VS_CNTL, 1);
 397    tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(vs->constlen, 4)) |
 398                   A6XX_HLSQ_VS_CNTL_ENABLED);
 399 }
 400
 401 static void
 402 tu6_emit_hs_config(struct tu_cs *cs, struct tu_shader *shader,
 403                    const struct ir3_shader_variant *hs)
 404 {
 405    uint32_t sp_hs_config = 0;
 406    if (hs->instrlen)
 407       sp_hs_config |= A6XX_SP_HS_CONFIG_ENABLED;
 408
 409    tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
 410    tu_cs_emit(cs, 0);
 411
 412    tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_CONFIG, 2);
 413    tu_cs_emit(cs, sp_hs_config);
 414    tu_cs_emit(cs, hs->instrlen);
 415
 416    tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_HS_CNTL, 1);
 417    tu_cs_emit(cs, A6XX_HLSQ_HS_CNTL_CONSTLEN(align(hs->constlen, 4)));
 418 }
 419
 420 static void
 421 tu6_emit_ds_config(struct tu_cs *cs, struct tu_shader *shader,
 422                    const struct ir3_shader_variant *ds)
 423 {
 424    uint32_t sp_ds_config = 0;
 425    if (ds->instrlen)
 426       sp_ds_config |= A6XX_SP_DS_CONFIG_ENABLED;
 427
 428    tu_cs_emit_pkt4(cs, REG_A6XX_SP_DS_CONFIG, 2);
 429    tu_cs_emit(cs, sp_ds_config);
 430    tu_cs_emit(cs, ds->instrlen);
 431
 432    tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_DS_CNTL, 1);
 433    tu_cs_emit(cs, A6XX_HLSQ_DS_CNTL_CONSTLEN(align(ds->constlen, 4)));
 434 }
 435
 436 static void
 437 tu6_emit_gs_config(struct tu_cs *cs, struct tu_shader *shader,
 438                    const struct ir3_shader_variant *gs)
 439 {
 440    uint32_t sp_gs_config = 0;
 441    if (gs->instrlen)
 442       sp_gs_config |= A6XX_SP_GS_CONFIG_ENABLED;
 443
 444    tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
 445    tu_cs_emit(cs, 0);
 446
 447    tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CONFIG, 2);
 448    tu_cs_emit(cs, sp_gs_config);
 449    tu_cs_emit(cs, gs->instrlen);
 450
 451    tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_GS_CNTL, 1);
 452    tu_cs_emit(cs, A6XX_HLSQ_GS_CNTL_CONSTLEN(align(gs->constlen, 4)));
 453 }
 454
 455 static void
 456 tu6_emit_fs_config(struct tu_cs *cs, struct tu_shader *shader,
 457                    const struct ir3_shader_variant *fs)
 458 {
 459    uint32_t sp_fs_ctrl =
 460       A6XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) | 0x1000000 |
 461       A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs->info.max_reg + 1) |
 462       A6XX_SP_FS_CTRL_REG0_MERGEDREGS |
 463       A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs->branchstack);
 464    if (fs->total_in > 0)
 465       sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_VARYING;
 466    if (fs->need_pixlod)
 467       sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_PIXLODENABLE;
 468    if (fs->need_fine_derivatives)
 469       sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_DIFF_FINE;
 470
 471    uint32_t sp_fs_config = 0;
 472    unsigned shader_nibo = 0;
 473    if (shader) {
 474       shader_nibo = tu_shader_nibo(shader);
 475       sp_fs_config = A6XX_SP_FS_CONFIG_NTEX(shader->texture_map.num_desc) |
 476                      A6XX_SP_FS_CONFIG_NSAMP(shader->sampler_map.num_desc) |
 477                      A6XX_SP_FS_CONFIG_NIBO(shader_nibo);
 478    }
 479
 480    if (fs->instrlen)
 481       sp_fs_config |= A6XX_SP_FS_CONFIG_ENABLED;
 482
 483    tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_A9A8, 1);
 484    tu_cs_emit(cs, 0);
 485
 486    tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_AB00, 1);
 487    tu_cs_emit(cs, 0x5);
 488
 489    tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_CTRL_REG0, 1);
 490    tu_cs_emit(cs, sp_fs_ctrl);
 491
 492    tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_CONFIG, 2);
 493    tu_cs_emit(cs, sp_fs_config);
 494    tu_cs_emit(cs, fs->instrlen);
 495
 496    tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_FS_CNTL, 1);
 497    tu_cs_emit(cs, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(fs->constlen, 4)) |
 498                   A6XX_HLSQ_FS_CNTL_ENABLED);
 499
 500    tu_cs_emit_pkt4(cs, REG_A6XX_SP_IBO_COUNT, 1);
 501    tu_cs_emit(cs, shader_nibo);
 502 }
 503
 504 static void
 505 tu6_emit_cs_config(struct tu_cs *cs, const struct tu_shader *shader,
 506                    const struct ir3_shader_variant *v)
 507 {
 508    tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
 509    tu_cs_emit(cs, 0xff);
 510
 511    unsigned constlen = align(v->constlen, 4);
 512    tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL, 1);
 513    tu_cs_emit(cs, A6XX_HLSQ_CS_CNTL_CONSTLEN(constlen) |
 514               A6XX_HLSQ_CS_CNTL_ENABLED);
 515
 516    tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_CONFIG, 2);
 517    tu_cs_emit(cs, A6XX_SP_CS_CONFIG_ENABLED |
 518               A6XX_SP_CS_CONFIG_NIBO(tu_shader_nibo(shader)) |
 519               A6XX_SP_CS_CONFIG_NTEX(shader->texture_map.num_desc) |
 520               A6XX_SP_CS_CONFIG_NSAMP(shader->sampler_map.num_desc));
 521    tu_cs_emit(cs, v->instrlen);
 522
 523    tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_CTRL_REG0, 1);
 524    tu_cs_emit(cs, A6XX_SP_CS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
 525               A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(v->info.max_reg + 1) |
 526               A6XX_SP_CS_CTRL_REG0_MERGEDREGS |
 527               A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(v->branchstack) |
 528               COND(v->need_pixlod, A6XX_SP_CS_CTRL_REG0_PIXLODENABLE) |
 529               COND(v->need_fine_derivatives, A6XX_SP_CS_CTRL_REG0_DIFF_FINE));
 530
 531    tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_UNKNOWN_A9B1, 1);
 532    tu_cs_emit(cs, 0x41);
 533
 534    uint32_t local_invocation_id =
 535       ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
 536    uint32_t work_group_id =
 537       ir3_find_sysval_regid(v, SYSTEM_VALUE_WORK_GROUP_ID);
 538
 539    tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL_0, 2);
 540    tu_cs_emit(cs,
 541               A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) |
 542               A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
 543               A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
 544               A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
 545    tu_cs_emit(cs, 0x2fc);             /* HLSQ_CS_UNKNOWN_B998 */
 546
 547    tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_IBO_COUNT, 1);
 548    tu_cs_emit(cs, tu_shader_nibo(shader));
 549 }
 550
 551 static void
 552 tu6_emit_vs_system_values(struct tu_cs *cs,
 553                           const struct ir3_shader_variant *vs)
 554 {
 555    const uint32_t vertexid_regid =
 556       ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
 557    const uint32_t instanceid_regid =
 558       ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
 559
 560    tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_1, 6);
 561    tu_cs_emit(cs, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid) |
 562                      A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid) |
 563                      0xfcfc0000);
 564    tu_cs_emit(cs, 0x0000fcfc); /* VFD_CONTROL_2 */
 565    tu_cs_emit(cs, 0xfcfcfcfc); /* VFD_CONTROL_3 */
 566    tu_cs_emit(cs, 0x000000fc); /* VFD_CONTROL_4 */
 567    tu_cs_emit(cs, 0x0000fcfc); /* VFD_CONTROL_5 */
 568    tu_cs_emit(cs, 0x00000000); /* VFD_CONTROL_6 */
 569 }
 570
 571 static void
 572 tu6_emit_vpc(struct tu_cs *cs,
 573              const struct ir3_shader_variant *vs,
 574              const struct ir3_shader_variant *fs,
 575              bool binning_pass)
 576 {
 577    struct ir3_shader_linkage linkage = { 0 };
 578    ir3_link_shaders(&linkage, vs, fs);
 579
 580    if (vs->shader->stream_output.num_outputs && !binning_pass)
 581       tu_finishme("stream output");
 582
 583    BITSET_DECLARE(vpc_var_enables, 128) = { 0 };
 584    for (uint32_t i = 0; i < linkage.cnt; i++) {
 585       const uint32_t comp_count = util_last_bit(linkage.var[i].compmask);
 586       for (uint32_t j = 0; j < comp_count; j++)
 587          BITSET_SET(vpc_var_enables, linkage.var[i].loc + j);
 588    }
 589
 590    tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VAR_DISABLE(0), 4);
 591    tu_cs_emit(cs, ~vpc_var_enables[0]);
 592    tu_cs_emit(cs, ~vpc_var_enables[1]);
 593    tu_cs_emit(cs, ~vpc_var_enables[2]);
 594    tu_cs_emit(cs, ~vpc_var_enables[3]);
 595
 596    /* a6xx finds position/pointsize at the end */
 597    const uint32_t position_regid =
 598       ir3_find_output_regid(vs, VARYING_SLOT_POS);
 599    const uint32_t pointsize_regid =
 600       ir3_find_output_regid(vs, VARYING_SLOT_PSIZ);
 601    uint32_t pointsize_loc = 0xff, position_loc = 0xff;
 602    if (position_regid != regid(63, 0)) {
 603       position_loc = linkage.max_loc;
 604       ir3_link_add(&linkage, position_regid, 0xf, linkage.max_loc);
 605    }
 606    if (pointsize_regid != regid(63, 0)) {
 607       pointsize_loc = linkage.max_loc;
 608       ir3_link_add(&linkage, pointsize_regid, 0x1, linkage.max_loc);
 609    }
 610
 611    /* map vs outputs to VPC */
 612    assert(linkage.cnt <= 32);
 613    const uint32_t sp_vs_out_count = (linkage.cnt + 1) / 2;
 614    const uint32_t sp_vs_vpc_dst_count = (linkage.cnt + 3) / 4;
 615    uint32_t sp_vs_out[16];
 616    uint32_t sp_vs_vpc_dst[8];
 617    sp_vs_out[sp_vs_out_count - 1] = 0;
 618    sp_vs_vpc_dst[sp_vs_vpc_dst_count - 1] = 0;
 619    for (uint32_t i = 0; i < linkage.cnt; i++) {
 620       ((uint16_t *) sp_vs_out)[i] =
 621          A6XX_SP_VS_OUT_REG_A_REGID(linkage.var[i].regid) |
 622          A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage.var[i].compmask);
 623       ((uint8_t *) sp_vs_vpc_dst)[i] =
 624          A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage.var[i].loc);
 625    }
 626
 627    tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_OUT_REG(0), sp_vs_out_count);
 628    tu_cs_emit_array(cs, sp_vs_out, sp_vs_out_count);
 629
 630    tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_VPC_DST_REG(0), sp_vs_vpc_dst_count);
 631    tu_cs_emit_array(cs, sp_vs_vpc_dst, sp_vs_vpc_dst_count);
 632
 633    tu_cs_emit_pkt4(cs, REG_A6XX_VPC_CNTL_0, 1);
 634    tu_cs_emit(cs, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs->total_in) |
 635                      (fs->total_in > 0 ? A6XX_VPC_CNTL_0_VARYING : 0) |
 636                      0xff00ff00);
 637
 638    tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK, 1);
 639    tu_cs_emit(cs, A6XX_VPC_PACK_POSITIONLOC(position_loc) |
 640                      A6XX_VPC_PACK_PSIZELOC(pointsize_loc) |
 641                      A6XX_VPC_PACK_STRIDE_IN_VPC(linkage.max_loc));
 642
 643    tu_cs_emit_pkt4(cs, REG_A6XX_VPC_GS_SIV_CNTL, 1);
 644    tu_cs_emit(cs, 0x0000ffff); /* XXX */
 645
 646    tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
 647    tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage.cnt));
 648
 649    tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
 650    tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage.max_loc) |
 651                      (vs->writes_psize ? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE : 0));
 652 }
 653
 654 static int
 655 tu6_vpc_varying_mode(const struct ir3_shader_variant *fs,
 656                      uint32_t index,
 657                      uint8_t *interp_mode,
 658                      uint8_t *ps_repl_mode)
 659 {
 660    enum
 661    {
 662       INTERP_SMOOTH = 0,
 663       INTERP_FLAT = 1,
 664       INTERP_ZERO = 2,
 665       INTERP_ONE = 3,
 666    };
 667    enum
 668    {
 669       PS_REPL_NONE = 0,
 670       PS_REPL_S = 1,
 671       PS_REPL_T = 2,
 672       PS_REPL_ONE_MINUS_T = 3,
 673    };
 674
 675    const uint32_t compmask = fs->inputs[index].compmask;
 676
 677    /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
 678     * fourth component occupy three consecutive varying slots
 679     */
 680    int shift = 0;
 681    *interp_mode = 0;
 682    *ps_repl_mode = 0;
 683    if (fs->inputs[index].slot == VARYING_SLOT_PNTC) {
 684       if (compmask & 0x1) {
 685          *ps_repl_mode |= PS_REPL_S << shift;
 686          shift += 2;
 687       }
 688       if (compmask & 0x2) {
 689          *ps_repl_mode |= PS_REPL_T << shift;
 690          shift += 2;
 691       }
 692       if (compmask & 0x4) {
 693          *interp_mode |= INTERP_ZERO << shift;
 694          shift += 2;
 695       }
 696       if (compmask & 0x8) {
 697          *interp_mode |= INTERP_ONE << 6;
 698          shift += 2;
 699       }
 700    } else if ((fs->inputs[index].interpolate == INTERP_MODE_FLAT) ||
 701               fs->inputs[index].rasterflat) {
 702       for (int i = 0; i < 4; i++) {
 703          if (compmask & (1 << i)) {
 704             *interp_mode |= INTERP_FLAT << shift;
 705             shift += 2;
 706          }
 707       }
 708    }
 709
 710    return shift;
 711 }
 712
 713 static void
 714 tu6_emit_vpc_varying_modes(struct tu_cs *cs,
 715                            const struct ir3_shader_variant *fs,
 716                            bool binning_pass)
 717 {
 718    uint32_t interp_modes[8] = { 0 };
 719    uint32_t ps_repl_modes[8] = { 0 };
 720
 721    if (!binning_pass) {
 722       for (int i = -1;
 723            (i = ir3_next_varying(fs, i)) < (int) fs->inputs_count;) {
 724
 725          /* get the mode for input i */
 726          uint8_t interp_mode;
 727          uint8_t ps_repl_mode;
 728          const int bits =
 729             tu6_vpc_varying_mode(fs, i, &interp_mode, &ps_repl_mode);
 730
 731          /* OR the mode into the array */
 732          const uint32_t inloc = fs->inputs[i].inloc * 2;
 733          uint32_t n = inloc / 32;
 734          uint32_t shift = inloc % 32;
 735          interp_modes[n] |= interp_mode << shift;
 736          ps_repl_modes[n] |= ps_repl_mode << shift;
 737          if (shift + bits > 32) {
 738             n++;
 739             shift = 32 - shift;
 740
 741             interp_modes[n] |= interp_mode >> shift;
 742             ps_repl_modes[n] |= ps_repl_mode >> shift;
 743          }
 744       }
 745    }
 746
 747    tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
 748    tu_cs_emit_array(cs, interp_modes, 8);
 749
 750    tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
 751    tu_cs_emit_array(cs, ps_repl_modes, 8);
 752 }
 753
 754 static void
 755 tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
 756 {
 757    uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
 758    uint32_t ij_pix_regid, ij_samp_regid, ij_cent_regid, ij_size_regid;
 759    uint32_t smask_in_regid;
 760
 761    bool sample_shading = fs->per_samp; /* TODO | key->sample_shading; */
 762    bool enable_varyings = fs->total_in > 0;
 763
 764    samp_id_regid   = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
 765    smask_in_regid  = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
 766    face_regid      = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
 767    coord_regid     = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
 768    zwcoord_regid   = VALIDREG(coord_regid) ? coord_regid + 2 : regid(63, 0);
 769    ij_pix_regid    = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
 770    ij_samp_regid   = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE);
 771    ij_cent_regid   = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID);
 772    ij_size_regid   = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE);
 773
 774    if (fs->num_sampler_prefetch > 0) {
 775       assert(VALIDREG(ij_pix_regid));
 776       /* also, it seems like ij_pix is *required* to be r0.x */
 777       assert(ij_pix_regid == regid(0, 0));
 778    }
 779
 780    tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
 781    tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
 782          A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
 783          0x7000);    // XXX);
 784    for (int i = 0; i < fs->num_sampler_prefetch; i++) {
 785       const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
 786       tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch->src) |
 787                      A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch->samp_id) |
 788                      A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch->tex_id) |
 789                      A6XX_SP_FS_PREFETCH_CMD_DST(prefetch->dst) |
 790                      A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch->wrmask) |
 791                      COND(prefetch->half_precision, A6XX_SP_FS_PREFETCH_CMD_HALF) |
 792                      A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch->cmd));
 793    }
 794
 795    tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
 796    tu_cs_emit(cs, 0x7);
 797    tu_cs_emit(cs, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
 798                   A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
 799                   A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
 800                   A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid));
 801    tu_cs_emit(cs, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid) |
 802                   A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid) |
 803                   0xfc00fc00);
 804    tu_cs_emit(cs, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
 805                   A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
 806                   A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid) |
 807                   0x0000fc00);
 808    tu_cs_emit(cs, 0xfc);
 809
 810    tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
 811    tu_cs_emit(cs, enable_varyings ? 3 : 1);
 812
 813    tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_A982, 1);
 814    tu_cs_emit(cs, 0); /* XXX */
 815
 816    tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
 817    tu_cs_emit(cs, 0xff); /* XXX */
 818
 819    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CNTL, 1);
 820    tu_cs_emit(cs,
 821          CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_VARYING) |
 822          CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_CENTROID) |
 823          CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
 824          COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
 825          COND(VALIDREG(ij_size_regid) &&  sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
 826          COND(fs->frag_coord,
 827                A6XX_GRAS_CNTL_SIZE |
 828                A6XX_GRAS_CNTL_XCOORD |
 829                A6XX_GRAS_CNTL_YCOORD |
 830                A6XX_GRAS_CNTL_ZCOORD |
 831                A6XX_GRAS_CNTL_WCOORD) |
 832          COND(fs->frag_face, A6XX_GRAS_CNTL_SIZE));
 833
 834    tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CONTROL0, 2);
 835    tu_cs_emit(cs,
 836          CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_VARYING) |
 837          CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_CENTROID) |
 838          CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING) |
 839          COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
 840          COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
 841          COND(VALIDREG(ij_size_regid) &&  sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
 842          COND(fs->frag_coord,
 843                A6XX_RB_RENDER_CONTROL0_SIZE |
 844                A6XX_RB_RENDER_CONTROL0_XCOORD |
 845                A6XX_RB_RENDER_CONTROL0_YCOORD |
 846                A6XX_RB_RENDER_CONTROL0_ZCOORD |
 847                A6XX_RB_RENDER_CONTROL0_WCOORD) |
 848          COND(fs->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE));
 849    tu_cs_emit(cs,
 850          CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
 851          CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
 852          CONDREG(ij_size_regid, A6XX_RB_RENDER_CONTROL1_SIZE) |
 853          COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
 854
 855    tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CNTL, 1);
 856    tu_cs_emit(cs, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
 857
 858    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8101, 1);
 859    tu_cs_emit(cs, COND(sample_shading, 0x6));  // XXX
 860
 861    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
 862    tu_cs_emit(cs, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
 863 }
 864
 865 static void
 866 tu6_emit_fs_outputs(struct tu_cs *cs,
 867                     const struct ir3_shader_variant *fs,
 868                     uint32_t mrt_count)
 869 {
 870    uint32_t smask_regid, posz_regid;
 871
 872    posz_regid      = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
 873    smask_regid     = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
 874
 875    uint32_t fragdata_regid[8];
 876    if (fs->color0_mrt) {
 877       fragdata_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
 878       for (uint32_t i = 1; i < ARRAY_SIZE(fragdata_regid); i++)
 879          fragdata_regid[i] = fragdata_regid[0];
 880    } else {
 881       for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++)
 882          fragdata_regid[i] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0 + i);
 883    }
 884
 885    tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_CNTL0, 2);
 886    tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
 887                   A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
 888                   0xfc000000);
 889    tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count));
 890
 891    tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
 892    for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++) {
 893       // TODO we could have a mix of half and full precision outputs,
 894       // we really need to figure out half-precision from IR3_REG_HALF
 895       tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid[i]) |
 896                         (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION : 0));
 897    }
 898
 899    tu_cs_emit_pkt4(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
 900    tu_cs_emit(cs, COND(fs->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
 901                   COND(fs->writes_smask, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK));
 902    tu_cs_emit(cs, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count));
 903
 904    uint32_t gras_su_depth_plane_cntl = 0;
 905    uint32_t rb_depth_plane_cntl = 0;
 906    if (fs->no_earlyz || fs->writes_pos) {
 907       gras_su_depth_plane_cntl |= A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
 908       rb_depth_plane_cntl |= A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
 909    }
 910
 911    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
 912    tu_cs_emit(cs, gras_su_depth_plane_cntl);
 913
 914    tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
 915    tu_cs_emit(cs, rb_depth_plane_cntl);
 916 }
 917
 918 static void
 919 tu6_emit_shader_object(struct tu_cs *cs,
 920                        gl_shader_stage stage,
 921                        const struct ir3_shader_variant *variant,
 922                        const struct tu_bo *binary_bo,
 923                        uint32_t binary_offset)
 924 {
 925    uint16_t reg;
 926    uint8_t opcode;
 927    enum a6xx_state_block sb;
 928    switch (stage) {
 929    case MESA_SHADER_VERTEX:
 930       reg = REG_A6XX_SP_VS_OBJ_START_LO;
 931       opcode = CP_LOAD_STATE6_GEOM;
 932       sb = SB6_VS_SHADER;
 933       break;
 934    case MESA_SHADER_TESS_CTRL:
 935       reg = REG_A6XX_SP_HS_OBJ_START_LO;
 936       opcode = CP_LOAD_STATE6_GEOM;
 937       sb = SB6_HS_SHADER;
 938       break;
 939    case MESA_SHADER_TESS_EVAL:
 940       reg = REG_A6XX_SP_DS_OBJ_START_LO;
 941       opcode = CP_LOAD_STATE6_GEOM;
 942       sb = SB6_DS_SHADER;
 943       break;
 944    case MESA_SHADER_GEOMETRY:
 945       reg = REG_A6XX_SP_GS_OBJ_START_LO;
 946       opcode = CP_LOAD_STATE6_GEOM;
 947       sb = SB6_GS_SHADER;
 948       break;
 949    case MESA_SHADER_FRAGMENT:
 950       reg = REG_A6XX_SP_FS_OBJ_START_LO;
 951       opcode = CP_LOAD_STATE6_FRAG;
 952       sb = SB6_FS_SHADER;
 953       break;
 954    case MESA_SHADER_COMPUTE:
 955       reg = REG_A6XX_SP_CS_OBJ_START_LO;
 956       opcode = CP_LOAD_STATE6_FRAG;
 957       sb = SB6_CS_SHADER;
 958       break;
 959    default:
 960       unreachable("invalid gl_shader_stage");
 961       opcode = CP_LOAD_STATE6_GEOM;
 962       sb = SB6_VS_SHADER;
 963       break;
 964    }
 965
 966    if (!variant->instrlen) {
 967       tu_cs_emit_pkt4(cs, reg, 2);
 968       tu_cs_emit_qw(cs, 0);
 969       return;
 970    }
 971
 972    assert(variant->type == stage);
 973
 974    const uint64_t binary_iova = binary_bo->iova + binary_offset;
 975    assert((binary_iova & 0x3) == 0);
 976
 977    tu_cs_emit_pkt4(cs, reg, 2);
 978    tu_cs_emit_qw(cs, binary_iova);
 979
 980    /* always indirect */
 981    const bool indirect = true;
 982    if (indirect) {
 983       tu_cs_emit_pkt7(cs, opcode, 3);
 984       tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
 985                         CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
 986                         CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
 987                         CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
 988                         CP_LOAD_STATE6_0_NUM_UNIT(variant->instrlen));
 989       tu_cs_emit_qw(cs, binary_iova);
 990    } else {
 991       const void *binary = binary_bo->map + binary_offset;
 992
 993       tu_cs_emit_pkt7(cs, opcode, 3 + variant->info.sizedwords);
 994       tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
 995                         CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
 996                         CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
 997                         CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
 998                         CP_LOAD_STATE6_0_NUM_UNIT(variant->instrlen));
 999       tu_cs_emit_qw(cs, 0);
1000       tu_cs_emit_array(cs, binary, variant->info.sizedwords);
1001    }
1002 }
1003
1004 static void
1005 tu6_emit_immediates(struct tu_cs *cs, const struct ir3_shader_variant *v,
1006                     uint32_t opcode, enum a6xx_state_block block)
1007 {
1008    /* dummy variant */
1009    if (!v->shader)
1010       return;
1011
1012    const struct ir3_const_state *const_state = &v->shader->const_state;
1013    uint32_t base = const_state->offsets.immediate;
1014    int size = const_state->immediates_count;
1015
1016    /* truncate size to avoid writing constants that shader
1017     * does not use:
1018     */
1019    size = MIN2(size + base, v->constlen) - base;
1020
1021    if (size <= 0)
1022       return;
1023
1024    tu_cs_emit_pkt7(cs, opcode, 3 + size * 4);
1025    tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
1026                   CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
1027                   CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
1028                   CP_LOAD_STATE6_0_STATE_BLOCK(block) |
1029                   CP_LOAD_STATE6_0_NUM_UNIT(size));
1030    tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
1031    tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
1032
1033    for (unsigned i = 0; i < size; i++) {
1034       tu_cs_emit(cs, const_state->immediates[i].val[0]);
1035       tu_cs_emit(cs, const_state->immediates[i].val[1]);
1036       tu_cs_emit(cs, const_state->immediates[i].val[2]);
1037       tu_cs_emit(cs, const_state->immediates[i].val[3]);
1038    }
1039 }
1040
1041 static void
1042 tu6_emit_program(struct tu_cs *cs,
1043                  const struct tu_pipeline_builder *builder,
1044                  const struct tu_bo *binary_bo,
1045                  bool binning_pass)
1046 {
1047    static const struct ir3_shader_variant dummy_variant = {
1048       .type = MESA_SHADER_NONE
1049    };
1050    assert(builder->shaders[MESA_SHADER_VERTEX]);
1051    const struct ir3_shader_variant *vs =
1052       &builder->shaders[MESA_SHADER_VERTEX]->variants[0];
1053    const struct ir3_shader_variant *hs =
1054       builder->shaders[MESA_SHADER_TESS_CTRL]
1055          ? &builder->shaders[MESA_SHADER_TESS_CTRL]->variants[0]
1056          : &dummy_variant;
1057    const struct ir3_shader_variant *ds =
1058       builder->shaders[MESA_SHADER_TESS_EVAL]
1059          ? &builder->shaders[MESA_SHADER_TESS_EVAL]->variants[0]
1060          : &dummy_variant;
1061    const struct ir3_shader_variant *gs =
1062       builder->shaders[MESA_SHADER_GEOMETRY]
1063          ? &builder->shaders[MESA_SHADER_GEOMETRY]->variants[0]
1064          : &dummy_variant;
1065    const struct ir3_shader_variant *fs =
1066       builder->shaders[MESA_SHADER_FRAGMENT]
1067          ? &builder->shaders[MESA_SHADER_FRAGMENT]->variants[0]
1068          : &dummy_variant;
1069
1070    if (binning_pass) {
1071       vs = &builder->shaders[MESA_SHADER_VERTEX]->variants[1];
1072       fs = &dummy_variant;
1073    }
1074
1075    tu6_emit_vs_config(cs, builder->shaders[MESA_SHADER_VERTEX], vs);
1076    tu6_emit_hs_config(cs, builder->shaders[MESA_SHADER_TESS_CTRL], hs);
1077    tu6_emit_ds_config(cs, builder->shaders[MESA_SHADER_TESS_EVAL], ds);
1078    tu6_emit_gs_config(cs, builder->shaders[MESA_SHADER_GEOMETRY], gs);
1079    tu6_emit_fs_config(cs, builder->shaders[MESA_SHADER_FRAGMENT], fs);
1080
1081    tu6_emit_vs_system_values(cs, vs);
1082    tu6_emit_vpc(cs, vs, fs, binning_pass);
1083    tu6_emit_vpc_varying_modes(cs, fs, binning_pass);
1084    tu6_emit_fs_inputs(cs, fs);
1085    tu6_emit_fs_outputs(cs, fs, builder->color_attachment_count);
1086
1087    tu6_emit_shader_object(cs, MESA_SHADER_VERTEX, vs, binary_bo,
1088       binning_pass ? builder->binning_vs_offset : builder->shader_offsets[MESA_SHADER_VERTEX]);
1089
1090    tu6_emit_shader_object(cs, MESA_SHADER_FRAGMENT, fs, binary_bo,
1091                           builder->shader_offsets[MESA_SHADER_FRAGMENT]);
1092
1093    tu6_emit_immediates(cs, vs, CP_LOAD_STATE6_GEOM, SB6_VS_SHADER);
1094    if (!binning_pass)
1095       tu6_emit_immediates(cs, fs, CP_LOAD_STATE6_FRAG, SB6_FS_SHADER);
1096 }
1097
1098 static void
1099 tu6_emit_vertex_input(struct tu_cs *cs,
1100                       const struct ir3_shader_variant *vs,
1101                       const VkPipelineVertexInputStateCreateInfo *vi_info,
1102                       uint8_t bindings[MAX_VERTEX_ATTRIBS],
1103                       uint16_t strides[MAX_VERTEX_ATTRIBS],
1104                       uint16_t offsets[MAX_VERTEX_ATTRIBS],
1105                       uint32_t *count)
1106 {
1107    uint32_t vfd_decode_idx = 0;
1108
1109    for (uint32_t i = 0; i < vs->inputs_count; i++) {
1110       if (vs->inputs[i].sysval || !vs->inputs[i].compmask)
1111          continue;
1112
1113       const VkVertexInputAttributeDescription *vi_attr =
1114          tu_find_vertex_input_attribute(vi_info, vs->inputs[i].slot);
1115       const VkVertexInputBindingDescription *vi_binding =
1116          tu_find_vertex_input_binding(vi_info, vi_attr);
1117       assert(vi_attr && vi_binding);
1118
1119       const struct tu_native_format format = tu6_format_vtx(vi_attr->format);
1120
1121       uint32_t vfd_decode = A6XX_VFD_DECODE_INSTR_IDX(vfd_decode_idx) |
1122                             A6XX_VFD_DECODE_INSTR_FORMAT(format.fmt) |
1123                             A6XX_VFD_DECODE_INSTR_SWAP(format.swap) |
1124                             A6XX_VFD_DECODE_INSTR_UNK30;
1125       if (vi_binding->inputRate == VK_VERTEX_INPUT_RATE_INSTANCE)
1126          vfd_decode |= A6XX_VFD_DECODE_INSTR_INSTANCED;
1127       if (!vk_format_is_int(vi_attr->format))
1128          vfd_decode |= A6XX_VFD_DECODE_INSTR_FLOAT;
1129
1130       const uint32_t vfd_decode_step_rate = 1;
1131
1132       const uint32_t vfd_dest_cntl =
1133          A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vs->inputs[i].compmask) |
1134          A6XX_VFD_DEST_CNTL_INSTR_REGID(vs->inputs[i].regid);
1135
1136       tu_cs_emit_pkt4(cs, REG_A6XX_VFD_DECODE(vfd_decode_idx), 2);
1137       tu_cs_emit(cs, vfd_decode);
1138       tu_cs_emit(cs, vfd_decode_step_rate);
1139
1140       tu_cs_emit_pkt4(cs, REG_A6XX_VFD_DEST_CNTL(vfd_decode_idx), 1);
1141       tu_cs_emit(cs, vfd_dest_cntl);
1142
1143       bindings[vfd_decode_idx] = vi_binding->binding;
1144       strides[vfd_decode_idx] = vi_binding->stride;
1145       offsets[vfd_decode_idx] = vi_attr->offset;
1146
1147       vfd_decode_idx++;
1148       assert(vfd_decode_idx <= MAX_VERTEX_ATTRIBS);
1149    }
1150
1151    tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_0, 1);
1152    tu_cs_emit(
1153       cs, A6XX_VFD_CONTROL_0_VTXCNT(vfd_decode_idx) | (vfd_decode_idx << 8));
1154
1155    *count = vfd_decode_idx;
1156 }
1157
1158 static uint32_t
1159 tu6_guardband_adj(uint32_t v)
1160 {
1161    if (v > 256)
1162       return (uint32_t)(511.0 - 65.0 * (log2(v) - 8.0));
1163    else
1164       return 511;
1165 }
1166
1167 void
1168 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport)
1169 {
1170    float offsets[3];
1171    float scales[3];
1172    scales[0] = viewport->width / 2.0f;
1173    scales[1] = viewport->height / 2.0f;
1174    scales[2] = viewport->maxDepth - viewport->minDepth;
1175    offsets[0] = viewport->x + scales[0];
1176    offsets[1] = viewport->y + scales[1];
1177    offsets[2] = viewport->minDepth;
1178
1179    VkOffset2D min;
1180    VkOffset2D max;
1181    min.x = (int32_t) viewport->x;
1182    max.x = (int32_t) ceilf(viewport->x + viewport->width);
1183    if (viewport->height >= 0.0f) {
1184       min.y = (int32_t) viewport->y;
1185       max.y = (int32_t) ceilf(viewport->y + viewport->height);
1186    } else {
1187       min.y = (int32_t)(viewport->y + viewport->height);
1188       max.y = (int32_t) ceilf(viewport->y);
1189    }
1190    /* the spec allows viewport->height to be 0.0f */
1191    if (min.y == max.y)
1192       max.y++;
1193    assert(min.x >= 0 && min.x < max.x);
1194    assert(min.y >= 0 && min.y < max.y);
1195
1196    VkExtent2D guardband_adj;
1197    guardband_adj.width = tu6_guardband_adj(max.x - min.x);
1198    guardband_adj.height = tu6_guardband_adj(max.y - min.y);
1199
1200    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0, 6);
1201    tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XOFFSET_0(offsets[0]).value);
1202    tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XSCALE_0(scales[0]).value);
1203    tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YOFFSET_0(offsets[1]).value);
1204    tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YSCALE_0(scales[1]).value);
1205    tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZOFFSET_0(offsets[2]).value);
1206    tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZSCALE_0(scales[2]).value);
1207
1208    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
1209    tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(min.x) |
1210                      A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(min.y));
1211    tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(max.x - 1) |
1212                      A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(max.y - 1));
1213
1214    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
1215    tu_cs_emit(cs,
1216               A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj.width) |
1217                  A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj.height));
1218 }
1219
1220 void
1221 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor)
1222 {
1223    const VkOffset2D min = scissor->offset;
1224    const VkOffset2D max = {
1225       scissor->offset.x + scissor->extent.width,
1226       scissor->offset.y + scissor->extent.height,
1227    };
1228
1229    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
1230    tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(min.x) |
1231                      A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(min.y));
1232    tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(max.x - 1) |
1233                      A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(max.y - 1));
1234 }
1235
1236 static void
1237 tu6_emit_gras_unknowns(struct tu_cs *cs)
1238 {
1239    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_DISABLE_CNTL, 1);
1240    tu_cs_emit(cs, A6XX_GRAS_DISABLE_CNTL_VP_CLIP_CODE_IGNORE);
1241    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8001, 1);
1242    tu_cs_emit(cs, 0x0);
1243    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LAYER_CNTL, 1);
1244    tu_cs_emit(cs, 0x0);
1245 }
1246
1247 static void
1248 tu6_emit_point_size(struct tu_cs *cs)
1249 {
1250    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POINT_MINMAX, 2);
1251    tu_cs_emit(cs, A6XX_GRAS_SU_POINT_MINMAX_MIN(1.0f / 16.0f) |
1252                      A6XX_GRAS_SU_POINT_MINMAX_MAX(4092.0f));
1253    tu_cs_emit(cs, A6XX_GRAS_SU_POINT_SIZE(1.0f).value);
1254 }
1255
1256 static uint32_t
1257 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo *rast_info,
1258                  VkSampleCountFlagBits samples)
1259 {
1260    uint32_t gras_su_cntl = 0;
1261
1262    if (rast_info->cullMode & VK_CULL_MODE_FRONT_BIT)
1263       gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_FRONT;
1264    if (rast_info->cullMode & VK_CULL_MODE_BACK_BIT)
1265       gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_BACK;
1266
1267    if (rast_info->frontFace == VK_FRONT_FACE_CLOCKWISE)
1268       gras_su_cntl |= A6XX_GRAS_SU_CNTL_FRONT_CW;
1269
1270    /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1271
1272    if (rast_info->depthBiasEnable)
1273       gras_su_cntl |= A6XX_GRAS_SU_CNTL_POLY_OFFSET;
1274
1275    if (samples > VK_SAMPLE_COUNT_1_BIT)
1276       gras_su_cntl |= A6XX_GRAS_SU_CNTL_MSAA_ENABLE;
1277
1278    return gras_su_cntl;
1279 }
1280
1281 void
1282 tu6_emit_gras_su_cntl(struct tu_cs *cs,
1283                       uint32_t gras_su_cntl,
1284                       float line_width)
1285 {
1286    assert((gras_su_cntl & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK) == 0);
1287    gras_su_cntl |= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(line_width / 2.0f);
1288
1289    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_CNTL, 1);
1290    tu_cs_emit(cs, gras_su_cntl);
1291 }
1292
1293 void
1294 tu6_emit_depth_bias(struct tu_cs *cs,
1295                     float constant_factor,
1296                     float clamp,
1297                     float slope_factor)
1298 {
1299    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
1300    tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor).value);
1301    tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor).value);
1302    tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp).value);
1303 }
1304
1305 static void
1306 tu6_emit_alpha_control_disable(struct tu_cs *cs)
1307 {
1308    tu_cs_emit_pkt4(cs, REG_A6XX_RB_ALPHA_CONTROL, 1);
1309    tu_cs_emit(cs, 0);
1310 }
1311
1312 static void
1313 tu6_emit_depth_control(struct tu_cs *cs,
1314                        const VkPipelineDepthStencilStateCreateInfo *ds_info)
1315 {
1316    assert(!ds_info->depthBoundsTestEnable);
1317
1318    uint32_t rb_depth_cntl = 0;
1319    if (ds_info->depthTestEnable) {
1320       rb_depth_cntl |=
1321          A6XX_RB_DEPTH_CNTL_Z_ENABLE |
1322          A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) |
1323          A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
1324
1325       if (ds_info->depthWriteEnable)
1326          rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
1327    }
1328
1329    tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_CNTL, 1);
1330    tu_cs_emit(cs, rb_depth_cntl);
1331 }
1332
1333 static void
1334 tu6_emit_stencil_control(struct tu_cs *cs,
1335                          const VkPipelineDepthStencilStateCreateInfo *ds_info)
1336 {
1337    uint32_t rb_stencil_control = 0;
1338    if (ds_info->stencilTestEnable) {
1339       const VkStencilOpState *front = &ds_info->front;
1340       const VkStencilOpState *back = &ds_info->back;
1341       rb_stencil_control |=
1342          A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
1343          A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
1344          A6XX_RB_STENCIL_CONTROL_STENCIL_READ |
1345          A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front->compareOp)) |
1346          A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front->failOp)) |
1347          A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front->passOp)) |
1348          A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front->depthFailOp)) |
1349          A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back->compareOp)) |
1350          A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back->failOp)) |
1351          A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back->passOp)) |
1352          A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back->depthFailOp));
1353    }
1354
1355    tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_CONTROL, 1);
1356    tu_cs_emit(cs, rb_stencil_control);
1357 }
1358
1359 void
1360 tu6_emit_stencil_compare_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1361 {
1362    tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILMASK, 1);
1363    tu_cs_emit(
1364       cs, A6XX_RB_STENCILMASK_MASK(front) | A6XX_RB_STENCILMASK_BFMASK(back));
1365 }
1366
1367 void
1368 tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1369 {
1370    tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILWRMASK, 1);
1371    tu_cs_emit(cs, A6XX_RB_STENCILWRMASK_WRMASK(front) |
1372                      A6XX_RB_STENCILWRMASK_BFWRMASK(back));
1373 }
1374
1375 void
1376 tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back)
1377 {
1378    tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILREF, 1);
1379    tu_cs_emit(cs,
1380               A6XX_RB_STENCILREF_REF(front) | A6XX_RB_STENCILREF_BFREF(back));
1381 }
1382
1383 static uint32_t
1384 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState *att,
1385                          bool has_alpha)
1386 {
1387    const enum a3xx_rb_blend_opcode color_op = tu6_blend_op(att->colorBlendOp);
1388    const enum adreno_rb_blend_factor src_color_factor = tu6_blend_factor(
1389       has_alpha ? att->srcColorBlendFactor
1390                 : tu_blend_factor_no_dst_alpha(att->srcColorBlendFactor));
1391    const enum adreno_rb_blend_factor dst_color_factor = tu6_blend_factor(
1392       has_alpha ? att->dstColorBlendFactor
1393                 : tu_blend_factor_no_dst_alpha(att->dstColorBlendFactor));
1394    const enum a3xx_rb_blend_opcode alpha_op = tu6_blend_op(att->alphaBlendOp);
1395    const enum adreno_rb_blend_factor src_alpha_factor =
1396       tu6_blend_factor(att->srcAlphaBlendFactor);
1397    const enum adreno_rb_blend_factor dst_alpha_factor =
1398       tu6_blend_factor(att->dstAlphaBlendFactor);
1399
1400    return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor) |
1401           A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op) |
1402           A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor) |
1403           A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor) |
1404           A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op) |
1405           A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor);
1406 }
1407
1408 static uint32_t
1409 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState *att,
1410                    uint32_t rb_mrt_control_rop,
1411                    bool is_int,
1412                    bool has_alpha)
1413 {
1414    uint32_t rb_mrt_control =
1415       A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att->colorWriteMask);
1416
1417    /* ignore blending and logic op for integer attachments */
1418    if (is_int) {
1419       rb_mrt_control |= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
1420       return rb_mrt_control;
1421    }
1422
1423    rb_mrt_control |= rb_mrt_control_rop;
1424
1425    if (att->blendEnable) {
1426       rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND;
1427
1428       if (has_alpha)
1429          rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND2;
1430    }
1431
1432    return rb_mrt_control;
1433 }
1434
1435 static void
1436 tu6_emit_rb_mrt_controls(struct tu_cs *cs,
1437                          const VkPipelineColorBlendStateCreateInfo *blend_info,
1438                          const VkFormat attachment_formats[MAX_RTS],
1439                          uint32_t *blend_enable_mask)
1440 {
1441    *blend_enable_mask = 0;
1442
1443    bool rop_reads_dst = false;
1444    uint32_t rb_mrt_control_rop = 0;
1445    if (blend_info->logicOpEnable) {
1446       rop_reads_dst = tu_logic_op_reads_dst(blend_info->logicOp);
1447       rb_mrt_control_rop =
1448          A6XX_RB_MRT_CONTROL_ROP_ENABLE |
1449          A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info->logicOp));
1450    }
1451
1452    for (uint32_t i = 0; i < blend_info->attachmentCount; i++) {
1453       const VkPipelineColorBlendAttachmentState *att =
1454          &blend_info->pAttachments[i];
1455       const VkFormat format = attachment_formats[i];
1456
1457       uint32_t rb_mrt_control = 0;
1458       uint32_t rb_mrt_blend_control = 0;
1459       if (format != VK_FORMAT_UNDEFINED) {
1460          const bool is_int = vk_format_is_int(format);
1461          const bool has_alpha = vk_format_has_alpha(format);
1462
1463          rb_mrt_control =
1464             tu6_rb_mrt_control(att, rb_mrt_control_rop, is_int, has_alpha);
1465          rb_mrt_blend_control = tu6_rb_mrt_blend_control(att, has_alpha);
1466
1467          if (att->blendEnable || rop_reads_dst)
1468             *blend_enable_mask |= 1 << i;
1469       }
1470
1471       tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
1472       tu_cs_emit(cs, rb_mrt_control);
1473       tu_cs_emit(cs, rb_mrt_blend_control);
1474    }
1475
1476    for (uint32_t i = blend_info->attachmentCount; i < MAX_RTS; i++) {
1477       tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
1478       tu_cs_emit(cs, 0);
1479       tu_cs_emit(cs, 0);
1480    }
1481 }
1482
1483 static void
1484 tu6_emit_blend_control(struct tu_cs *cs,
1485                        uint32_t blend_enable_mask,
1486                        const VkPipelineMultisampleStateCreateInfo *msaa_info)
1487 {
1488    assert(!msaa_info->alphaToOneEnable);
1489
1490    uint32_t sp_blend_cntl = A6XX_SP_BLEND_CNTL_UNK8;
1491    if (blend_enable_mask)
1492       sp_blend_cntl |= A6XX_SP_BLEND_CNTL_ENABLED;
1493    if (msaa_info->alphaToCoverageEnable)
1494       sp_blend_cntl |= A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE;
1495
1496    const uint32_t sample_mask =
1497       msaa_info->pSampleMask ? *msaa_info->pSampleMask
1498                              : ((1 << msaa_info->rasterizationSamples) - 1);
1499
1500    /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
1501    uint32_t rb_blend_cntl =
1502       A6XX_RB_BLEND_CNTL_ENABLE_BLEND(blend_enable_mask) |
1503       A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND |
1504       A6XX_RB_BLEND_CNTL_SAMPLE_MASK(sample_mask);
1505    if (msaa_info->alphaToCoverageEnable)
1506       rb_blend_cntl |= A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE;
1507
1508    tu_cs_emit_pkt4(cs, REG_A6XX_SP_BLEND_CNTL, 1);
1509    tu_cs_emit(cs, sp_blend_cntl);
1510
1511    tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_CNTL, 1);
1512    tu_cs_emit(cs, rb_blend_cntl);
1513 }
1514
1515 void
1516 tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4])
1517 {
1518    tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_RED_F32, 4);
1519    tu_cs_emit_array(cs, (const uint32_t *) constants, 4);
1520 }
1521
1522 static VkResult
1523 tu_pipeline_create(struct tu_device *dev,
1524                    const VkAllocationCallbacks *pAllocator,
1525                    struct tu_pipeline **out_pipeline)
1526 {
1527    struct tu_pipeline *pipeline =
1528       vk_zalloc2(&dev->alloc, pAllocator, sizeof(*pipeline), 8,
1529                  VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1530    if (!pipeline)
1531       return VK_ERROR_OUT_OF_HOST_MEMORY;
1532
1533    tu_cs_init(&pipeline->cs, dev, TU_CS_MODE_SUB_STREAM, 2048);
1534
1535    /* reserve the space now such that tu_cs_begin_sub_stream never fails */
1536    VkResult result = tu_cs_reserve_space(&pipeline->cs, 2048);
1537    if (result != VK_SUCCESS) {
1538       vk_free2(&dev->alloc, pAllocator, pipeline);
1539       return result;
1540    }
1541
1542    *out_pipeline = pipeline;
1543
1544    return VK_SUCCESS;
1545 }
1546
1547 static VkResult
1548 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder)
1549 {
1550    const VkPipelineShaderStageCreateInfo *stage_infos[MESA_SHADER_STAGES] = {
1551       NULL
1552    };
1553    for (uint32_t i = 0; i < builder->create_info->stageCount; i++) {
1554       gl_shader_stage stage =
1555          tu_shader_stage(builder->create_info->pStages[i].stage);
1556       stage_infos[stage] = &builder->create_info->pStages[i];
1557    }
1558
1559    struct tu_shader_compile_options options;
1560    tu_shader_compile_options_init(&options, builder->create_info);
1561
1562    /* compile shaders in reverse order */
1563    struct tu_shader *next_stage_shader = NULL;
1564    for (gl_shader_stage stage = MESA_SHADER_STAGES - 1;
1565         stage > MESA_SHADER_NONE; stage--) {
1566       const VkPipelineShaderStageCreateInfo *stage_info = stage_infos[stage];
1567       if (!stage_info)
1568          continue;
1569
1570       struct tu_shader *shader =
1571          tu_shader_create(builder->device, stage, stage_info, builder->layout,
1572                           builder->alloc);
1573       if (!shader)
1574          return VK_ERROR_OUT_OF_HOST_MEMORY;
1575
1576       VkResult result =
1577          tu_shader_compile(builder->device, shader, next_stage_shader,
1578                            &options, builder->alloc);
1579       if (result != VK_SUCCESS)
1580          return result;
1581
1582       builder->shaders[stage] = shader;
1583       builder->shader_offsets[stage] = builder->shader_total_size;
1584       builder->shader_total_size +=
1585          sizeof(uint32_t) * shader->variants[0].info.sizedwords;
1586
1587       next_stage_shader = shader;
1588    }
1589
1590    if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
1591       const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1592       builder->binning_vs_offset = builder->shader_total_size;
1593       builder->shader_total_size +=
1594          sizeof(uint32_t) * vs->variants[1].info.sizedwords;
1595    }
1596
1597    return VK_SUCCESS;
1598 }
1599
1600 static VkResult
1601 tu_pipeline_builder_upload_shaders(struct tu_pipeline_builder *builder,
1602                                    struct tu_pipeline *pipeline)
1603 {
1604    struct tu_bo *bo = &pipeline->program.binary_bo;
1605
1606    VkResult result =
1607       tu_bo_init_new(builder->device, bo, builder->shader_total_size);
1608    if (result != VK_SUCCESS)
1609       return result;
1610
1611    result = tu_bo_map(builder->device, bo);
1612    if (result != VK_SUCCESS)
1613       return result;
1614
1615    for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
1616       const struct tu_shader *shader = builder->shaders[i];
1617       if (!shader)
1618          continue;
1619
1620       memcpy(bo->map + builder->shader_offsets[i], shader->binary,
1621              sizeof(uint32_t) * shader->variants[0].info.sizedwords);
1622    }
1623
1624    if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
1625       const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1626       memcpy(bo->map + builder->binning_vs_offset, vs->binning_binary,
1627              sizeof(uint32_t) * vs->variants[1].info.sizedwords);
1628    }
1629
1630    return VK_SUCCESS;
1631 }
1632
1633 static void
1634 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
1635                                   struct tu_pipeline *pipeline)
1636 {
1637    const VkPipelineDynamicStateCreateInfo *dynamic_info =
1638       builder->create_info->pDynamicState;
1639
1640    if (!dynamic_info)
1641       return;
1642
1643    for (uint32_t i = 0; i < dynamic_info->dynamicStateCount; i++) {
1644       pipeline->dynamic_state.mask |=
1645          tu_dynamic_state_bit(dynamic_info->pDynamicStates[i]);
1646    }
1647 }
1648
1649 static void
1650 tu_pipeline_set_linkage(struct tu_program_descriptor_linkage *link,
1651                         struct tu_shader *shader,
1652                         struct ir3_shader_variant *v)
1653 {
1654    link->ubo_state = v->shader->ubo_state;
1655    link->const_state = v->shader->const_state;
1656    link->constlen = v->constlen;
1657    link->texture_map = shader->texture_map;
1658    link->sampler_map = shader->sampler_map;
1659    link->ubo_map = shader->ubo_map;
1660    link->ssbo_map = shader->ssbo_map;
1661    link->image_map = shader->image_map;
1662 }
1663
1664 static void
1665 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder *builder,
1666                                         struct tu_pipeline *pipeline)
1667 {
1668    struct tu_cs prog_cs;
1669    tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
1670    tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, false);
1671    pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
1672
1673    tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
1674    tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, true);
1675    pipeline->program.binning_state_ib =
1676       tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
1677
1678    for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
1679       if (!builder->shaders[i])
1680          continue;
1681
1682       tu_pipeline_set_linkage(&pipeline->program.link[i],
1683                               builder->shaders[i],
1684                               &builder->shaders[i]->variants[0]);
1685    }
1686 }
1687
1688 static void
1689 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder *builder,
1690                                        struct tu_pipeline *pipeline)
1691 {
1692    const VkPipelineVertexInputStateCreateInfo *vi_info =
1693       builder->create_info->pVertexInputState;
1694    const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1695
1696    struct tu_cs vi_cs;
1697    tu_cs_begin_sub_stream(&pipeline->cs,
1698                           MAX_VERTEX_ATTRIBS * 5 + 2, &vi_cs);
1699    tu6_emit_vertex_input(&vi_cs, &vs->variants[0], vi_info,
1700                          pipeline->vi.bindings, pipeline->vi.strides,
1701                          pipeline->vi.offsets, &pipeline->vi.count);
1702    pipeline->vi.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
1703
1704    if (vs->has_binning_pass) {
1705       tu_cs_begin_sub_stream(&pipeline->cs,
1706                              MAX_VERTEX_ATTRIBS * 5 + 2, &vi_cs);
1707       tu6_emit_vertex_input(
1708          &vi_cs, &vs->variants[1], vi_info, pipeline->vi.binning_bindings,
1709          pipeline->vi.binning_strides, pipeline->vi.binning_offsets,
1710          &pipeline->vi.binning_count);
1711       pipeline->vi.binning_state_ib =
1712          tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
1713    }
1714 }
1715
1716 static void
1717 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder *builder,
1718                                          struct tu_pipeline *pipeline)
1719 {
1720    const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1721       builder->create_info->pInputAssemblyState;
1722
1723    pipeline->ia.primtype = tu6_primtype(ia_info->topology);
1724    pipeline->ia.primitive_restart = ia_info->primitiveRestartEnable;
1725 }
1726
1727 static void
1728 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder *builder,
1729                                    struct tu_pipeline *pipeline)
1730 {
1731    /* The spec says:
1732     *
1733     *    pViewportState is a pointer to an instance of the
1734     *    VkPipelineViewportStateCreateInfo structure, and is ignored if the
1735     *    pipeline has rasterization disabled."
1736     *
1737     * We leave the relevant registers stale in that case.
1738     */
1739    if (builder->rasterizer_discard)
1740       return;
1741
1742    const VkPipelineViewportStateCreateInfo *vp_info =
1743       builder->create_info->pViewportState;
1744
1745    struct tu_cs vp_cs;
1746    tu_cs_begin_sub_stream(&pipeline->cs, 15, &vp_cs);
1747
1748    if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_VIEWPORT)) {
1749       assert(vp_info->viewportCount == 1);
1750       tu6_emit_viewport(&vp_cs, vp_info->pViewports);
1751    }
1752
1753    if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_SCISSOR)) {
1754       assert(vp_info->scissorCount == 1);
1755       tu6_emit_scissor(&vp_cs, vp_info->pScissors);
1756    }
1757
1758    pipeline->vp.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vp_cs);
1759 }
1760
1761 static void
1762 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder,
1763                                         struct tu_pipeline *pipeline)
1764 {
1765    const VkPipelineRasterizationStateCreateInfo *rast_info =
1766       builder->create_info->pRasterizationState;
1767
1768    assert(!rast_info->depthClampEnable);
1769    assert(rast_info->polygonMode == VK_POLYGON_MODE_FILL);
1770
1771    struct tu_cs rast_cs;
1772    tu_cs_begin_sub_stream(&pipeline->cs, 20, &rast_cs);
1773
1774    /* move to hw ctx init? */
1775    tu6_emit_gras_unknowns(&rast_cs);
1776    tu6_emit_point_size(&rast_cs);
1777
1778    const uint32_t gras_su_cntl =
1779       tu6_gras_su_cntl(rast_info, builder->samples);
1780
1781    if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH))
1782       tu6_emit_gras_su_cntl(&rast_cs, gras_su_cntl, rast_info->lineWidth);
1783
1784    if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_DEPTH_BIAS)) {
1785       tu6_emit_depth_bias(&rast_cs, rast_info->depthBiasConstantFactor,
1786                           rast_info->depthBiasClamp,
1787                           rast_info->depthBiasSlopeFactor);
1788    }
1789
1790    pipeline->rast.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &rast_cs);
1791
1792    pipeline->rast.gras_su_cntl = gras_su_cntl;
1793 }
1794
1795 static void
1796 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
1797                                         struct tu_pipeline *pipeline)
1798 {
1799    /* The spec says:
1800     *
1801     *    pDepthStencilState is a pointer to an instance of the
1802     *    VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
1803     *    the pipeline has rasterization disabled or if the subpass of the
1804     *    render pass the pipeline is created against does not use a
1805     *    depth/stencil attachment.
1806     *
1807     * We disable both depth and stenil tests in those cases.
1808     */
1809    static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info;
1810    const VkPipelineDepthStencilStateCreateInfo *ds_info =
1811       builder->use_depth_stencil_attachment
1812          ? builder->create_info->pDepthStencilState
1813          : &dummy_ds_info;
1814
1815    struct tu_cs ds_cs;
1816    tu_cs_begin_sub_stream(&pipeline->cs, 12, &ds_cs);
1817
1818    /* move to hw ctx init? */
1819    tu6_emit_alpha_control_disable(&ds_cs);
1820
1821    tu6_emit_depth_control(&ds_cs, ds_info);
1822    tu6_emit_stencil_control(&ds_cs, ds_info);
1823
1824    if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
1825       tu6_emit_stencil_compare_mask(&ds_cs, ds_info->front.compareMask,
1826                                     ds_info->back.compareMask);
1827    }
1828    if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
1829       tu6_emit_stencil_write_mask(&ds_cs, ds_info->front.writeMask,
1830                                   ds_info->back.writeMask);
1831    }
1832    if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
1833       tu6_emit_stencil_reference(&ds_cs, ds_info->front.reference,
1834                                  ds_info->back.reference);
1835    }
1836
1837    pipeline->ds.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &ds_cs);
1838 }
1839
1840 static void
1841 tu_pipeline_builder_parse_multisample_and_color_blend(
1842    struct tu_pipeline_builder *builder, struct tu_pipeline *pipeline)
1843 {
1844    /* The spec says:
1845     *
1846     *    pMultisampleState is a pointer to an instance of the
1847     *    VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
1848     *    has rasterization disabled.
1849     *
1850     * Also,
1851     *
1852     *    pColorBlendState is a pointer to an instance of the
1853     *    VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
1854     *    pipeline has rasterization disabled or if the subpass of the render
1855     *    pass the pipeline is created against does not use any color
1856     *    attachments.
1857     *
1858     * We leave the relevant registers stale when rasterization is disabled.
1859     */
1860    if (builder->rasterizer_discard)
1861       return;
1862
1863    static const VkPipelineColorBlendStateCreateInfo dummy_blend_info;
1864    const VkPipelineMultisampleStateCreateInfo *msaa_info =
1865       builder->create_info->pMultisampleState;
1866    const VkPipelineColorBlendStateCreateInfo *blend_info =
1867       builder->use_color_attachments ? builder->create_info->pColorBlendState
1868                                      : &dummy_blend_info;
1869
1870    struct tu_cs blend_cs;
1871    tu_cs_begin_sub_stream(&pipeline->cs, MAX_RTS * 3 + 9, &blend_cs);
1872
1873    uint32_t blend_enable_mask;
1874    tu6_emit_rb_mrt_controls(&blend_cs, blend_info,
1875                             builder->color_attachment_formats,
1876                             &blend_enable_mask);
1877
1878    if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_BLEND_CONSTANTS))
1879       tu6_emit_blend_constants(&blend_cs, blend_info->blendConstants);
1880
1881    tu6_emit_blend_control(&blend_cs, blend_enable_mask, msaa_info);
1882
1883    pipeline->blend.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &blend_cs);
1884 }
1885
1886 static void
1887 tu_pipeline_finish(struct tu_pipeline *pipeline,
1888                    struct tu_device *dev,
1889                    const VkAllocationCallbacks *alloc)
1890 {
1891    tu_cs_finish(&pipeline->cs);
1892
1893    if (pipeline->program.binary_bo.gem_handle)
1894       tu_bo_finish(dev, &pipeline->program.binary_bo);
1895 }
1896
1897 static VkResult
1898 tu_pipeline_builder_build(struct tu_pipeline_builder *builder,
1899                           struct tu_pipeline **pipeline)
1900 {
1901    VkResult result = tu_pipeline_create(builder->device, builder->alloc,
1902                                         pipeline);
1903    if (result != VK_SUCCESS)
1904       return result;
1905
1906    /* compile and upload shaders */
1907    result = tu_pipeline_builder_compile_shaders(builder);
1908    if (result == VK_SUCCESS)
1909       result = tu_pipeline_builder_upload_shaders(builder, *pipeline);
1910    if (result != VK_SUCCESS) {
1911       tu_pipeline_finish(*pipeline, builder->device, builder->alloc);
1912       vk_free2(&builder->device->alloc, builder->alloc, *pipeline);
1913       *pipeline = VK_NULL_HANDLE;
1914
1915       return result;
1916    }
1917
1918    tu_pipeline_builder_parse_dynamic(builder, *pipeline);
1919    tu_pipeline_builder_parse_shader_stages(builder, *pipeline);
1920    tu_pipeline_builder_parse_vertex_input(builder, *pipeline);
1921    tu_pipeline_builder_parse_input_assembly(builder, *pipeline);
1922    tu_pipeline_builder_parse_viewport(builder, *pipeline);
1923    tu_pipeline_builder_parse_rasterization(builder, *pipeline);
1924    tu_pipeline_builder_parse_depth_stencil(builder, *pipeline);
1925    tu_pipeline_builder_parse_multisample_and_color_blend(builder, *pipeline);
1926
1927    /* we should have reserved enough space upfront such that the CS never
1928     * grows
1929     */
1930    assert((*pipeline)->cs.bo_count == 1);
1931
1932    return VK_SUCCESS;
1933 }
1934
1935 static void
1936 tu_pipeline_builder_finish(struct tu_pipeline_builder *builder)
1937 {
1938    for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
1939       if (!builder->shaders[i])
1940          continue;
1941       tu_shader_destroy(builder->device, builder->shaders[i], builder->alloc);
1942    }
1943 }
1944
1945 static void
1946 tu_pipeline_builder_init_graphics(
1947    struct tu_pipeline_builder *builder,
1948    struct tu_device *dev,
1949    struct tu_pipeline_cache *cache,
1950    const VkGraphicsPipelineCreateInfo *create_info,
1951    const VkAllocationCallbacks *alloc)
1952 {
1953    TU_FROM_HANDLE(tu_pipeline_layout, layout, create_info->layout);
1954
1955    *builder = (struct tu_pipeline_builder) {
1956       .device = dev,
1957       .cache = cache,
1958       .create_info = create_info,
1959       .alloc = alloc,
1960       .layout = layout,
1961    };
1962
1963    builder->rasterizer_discard =
1964       create_info->pRasterizationState->rasterizerDiscardEnable;
1965
1966    if (builder->rasterizer_discard) {
1967       builder->samples = VK_SAMPLE_COUNT_1_BIT;
1968    } else {
1969       builder->samples = create_info->pMultisampleState->rasterizationSamples;
1970
1971       const struct tu_render_pass *pass =
1972          tu_render_pass_from_handle(create_info->renderPass);
1973       const struct tu_subpass *subpass =
1974          &pass->subpasses[create_info->subpass];
1975
1976       builder->use_depth_stencil_attachment =
1977          subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED;
1978
1979       assert(subpass->color_count == 0 ||
1980              !create_info->pColorBlendState ||
1981              subpass->color_count == create_info->pColorBlendState->attachmentCount);
1982       builder->color_attachment_count = subpass->color_count;
1983       for (uint32_t i = 0; i < subpass->color_count; i++) {
1984          const uint32_t a = subpass->color_attachments[i].attachment;
1985          if (a == VK_ATTACHMENT_UNUSED)
1986             continue;
1987
1988          builder->color_attachment_formats[i] = pass->attachments[a].format;
1989          builder->use_color_attachments = true;
1990       }
1991    }
1992 }
1993
1994 static VkResult
1995 tu_graphics_pipeline_create(VkDevice device,
1996                             VkPipelineCache pipelineCache,
1997                             const VkGraphicsPipelineCreateInfo *pCreateInfo,
1998                             const VkAllocationCallbacks *pAllocator,
1999                             VkPipeline *pPipeline)
2000 {
2001    TU_FROM_HANDLE(tu_device, dev, device);
2002    TU_FROM_HANDLE(tu_pipeline_cache, cache, pipelineCache);
2003
2004    struct tu_pipeline_builder builder;
2005    tu_pipeline_builder_init_graphics(&builder, dev, cache,
2006                                      pCreateInfo, pAllocator);
2007
2008    struct tu_pipeline *pipeline = NULL;
2009    VkResult result = tu_pipeline_builder_build(&builder, &pipeline);
2010    tu_pipeline_builder_finish(&builder);
2011
2012    if (result == VK_SUCCESS)
2013       *pPipeline = tu_pipeline_to_handle(pipeline);
2014    else
2015       *pPipeline = VK_NULL_HANDLE;
2016
2017    return result;
2018 }
2019
2020 VkResult
2021 tu_CreateGraphicsPipelines(VkDevice device,
2022                            VkPipelineCache pipelineCache,
2023                            uint32_t count,
2024                            const VkGraphicsPipelineCreateInfo *pCreateInfos,
2025                            const VkAllocationCallbacks *pAllocator,
2026                            VkPipeline *pPipelines)
2027 {
2028    VkResult final_result = VK_SUCCESS;
2029
2030    for (uint32_t i = 0; i < count; i++) {
2031       VkResult result = tu_graphics_pipeline_create(device, pipelineCache,
2032                                                     &pCreateInfos[i], pAllocator,
2033                                                     &pPipelines[i]);
2034
2035       if (result != VK_SUCCESS)
2036          final_result = result;
2037    }
2038
2039    return final_result;
2040 }
2041
2042 static void
2043 tu6_emit_compute_program(struct tu_cs *cs,
2044                          struct tu_shader *shader,
2045                          const struct tu_bo *binary_bo)
2046 {
2047    const struct ir3_shader_variant *v = &shader->variants[0];
2048
2049    tu6_emit_cs_config(cs, shader, v);
2050
2051    /* The compute program is the only one in the pipeline, so 0 offset. */
2052    tu6_emit_shader_object(cs, MESA_SHADER_COMPUTE, v, binary_bo, 0);
2053
2054    tu6_emit_immediates(cs, v, CP_LOAD_STATE6_FRAG, SB6_CS_SHADER);
2055 }
2056
2057 static VkResult
2058 tu_compute_upload_shader(VkDevice device,
2059                          struct tu_pipeline *pipeline,
2060                          struct tu_shader *shader)
2061 {
2062    TU_FROM_HANDLE(tu_device, dev, device);
2063    struct tu_bo *bo = &pipeline->program.binary_bo;
2064    struct ir3_shader_variant *v = &shader->variants[0];
2065
2066    uint32_t shader_size = sizeof(uint32_t) * v->info.sizedwords;
2067    VkResult result =
2068       tu_bo_init_new(dev, bo, shader_size);
2069    if (result != VK_SUCCESS)
2070       return result;
2071
2072    result = tu_bo_map(dev, bo);
2073    if (result != VK_SUCCESS)
2074       return result;
2075
2076    memcpy(bo->map, shader->binary, shader_size);
2077
2078    return VK_SUCCESS;
2079 }
2080
2081
2082 static VkResult
2083 tu_compute_pipeline_create(VkDevice device,
2084                            VkPipelineCache _cache,
2085                            const VkComputePipelineCreateInfo *pCreateInfo,
2086                            const VkAllocationCallbacks *pAllocator,
2087                            VkPipeline *pPipeline)
2088 {
2089    TU_FROM_HANDLE(tu_device, dev, device);
2090    TU_FROM_HANDLE(tu_pipeline_layout, layout, pCreateInfo->layout);
2091    const VkPipelineShaderStageCreateInfo *stage_info = &pCreateInfo->stage;
2092    VkResult result;
2093
2094    struct tu_pipeline *pipeline;
2095
2096    *pPipeline = VK_NULL_HANDLE;
2097
2098    result = tu_pipeline_create(dev, pAllocator, &pipeline);
2099    if (result != VK_SUCCESS)
2100       return result;
2101
2102    pipeline->layout = layout;
2103
2104    struct tu_shader_compile_options options;
2105    tu_shader_compile_options_init(&options, NULL);
2106
2107    struct tu_shader *shader =
2108       tu_shader_create(dev, MESA_SHADER_COMPUTE, stage_info, layout, pAllocator);
2109    if (!shader) {
2110       result = VK_ERROR_OUT_OF_HOST_MEMORY;
2111       goto fail;
2112    }
2113
2114    result = tu_shader_compile(dev, shader, NULL, &options, pAllocator);
2115    if (result != VK_SUCCESS)
2116       goto fail;
2117
2118    struct ir3_shader_variant *v = &shader->variants[0];
2119
2120    tu_pipeline_set_linkage(&pipeline->program.link[MESA_SHADER_COMPUTE],
2121                            shader, v);
2122
2123    result = tu_compute_upload_shader(device, pipeline, shader);
2124    if (result != VK_SUCCESS)
2125       goto fail;
2126
2127    for (int i = 0; i < 3; i++)
2128       pipeline->compute.local_size[i] = v->shader->nir->info.cs.local_size[i];
2129
2130    struct tu_cs prog_cs;
2131    tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2132    tu6_emit_compute_program(&prog_cs, shader, &pipeline->program.binary_bo);
2133    pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2134
2135    *pPipeline = tu_pipeline_to_handle(pipeline);
2136    return VK_SUCCESS;
2137
2138 fail:
2139    if (shader)
2140       tu_shader_destroy(dev, shader, pAllocator);
2141
2142    tu_pipeline_finish(pipeline, dev, pAllocator);
2143    vk_free2(&dev->alloc, pAllocator, pipeline);
2144
2145    return result;
2146 }
2147
2148 VkResult
2149 tu_CreateComputePipelines(VkDevice device,
2150                           VkPipelineCache pipelineCache,
2151                           uint32_t count,
2152                           const VkComputePipelineCreateInfo *pCreateInfos,
2153                           const VkAllocationCallbacks *pAllocator,
2154                           VkPipeline *pPipelines)
2155 {
2156    VkResult final_result = VK_SUCCESS;
2157
2158    for (uint32_t i = 0; i < count; i++) {
2159       VkResult result = tu_compute_pipeline_create(device, pipelineCache,
2160                                                    &pCreateInfos[i],
2161                                                    pAllocator, &pPipelines[i]);
2162       if (result != VK_SUCCESS)
2163          final_result = result;
2164    }
2165
2166    return final_result;
2167 }
2168
2169 void
2170 tu_DestroyPipeline(VkDevice _device,
2171                    VkPipeline _pipeline,
2172                    const VkAllocationCallbacks *pAllocator)
2173 {
2174    TU_FROM_HANDLE(tu_device, dev, _device);
2175    TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
2176
2177    if (!_pipeline)
2178       return;
2179
2180    tu_pipeline_finish(pipeline, dev, pAllocator);
2181    vk_free2(&dev->alloc, pAllocator, pipeline);
2182 }