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turnip: fix triangle strip
[mesa.git] / src / freedreno / vulkan / tu_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "main/menums.h"
31 #include "nir/nir.h"
32 #include "nir/nir_builder.h"
33 #include "spirv/nir_spirv.h"
34 #include "util/debug.h"
35 #include "util/mesa-sha1.h"
36 #include "util/u_atomic.h"
37 #include "vk_format.h"
38 #include "vk_util.h"
39
40 #include "tu_cs.h"
41
42 struct tu_pipeline_builder
43 {
44 struct tu_device *device;
45 struct tu_pipeline_cache *cache;
46 const VkAllocationCallbacks *alloc;
47 const VkGraphicsPipelineCreateInfo *create_info;
48
49 struct tu_shader *shaders[MESA_SHADER_STAGES];
50 uint32_t shader_offsets[MESA_SHADER_STAGES];
51 uint32_t binning_vs_offset;
52 uint32_t shader_total_size;
53
54 bool rasterizer_discard;
55 /* these states are affectd by rasterizer_discard */
56 VkSampleCountFlagBits samples;
57 bool use_depth_stencil_attachment;
58 bool use_color_attachments;
59 uint32_t color_attachment_count;
60 VkFormat color_attachment_formats[MAX_RTS];
61 };
62
63 static enum tu_dynamic_state_bits
64 tu_dynamic_state_bit(VkDynamicState state)
65 {
66 switch (state) {
67 case VK_DYNAMIC_STATE_VIEWPORT:
68 return TU_DYNAMIC_VIEWPORT;
69 case VK_DYNAMIC_STATE_SCISSOR:
70 return TU_DYNAMIC_SCISSOR;
71 case VK_DYNAMIC_STATE_LINE_WIDTH:
72 return TU_DYNAMIC_LINE_WIDTH;
73 case VK_DYNAMIC_STATE_DEPTH_BIAS:
74 return TU_DYNAMIC_DEPTH_BIAS;
75 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
76 return TU_DYNAMIC_BLEND_CONSTANTS;
77 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
78 return TU_DYNAMIC_DEPTH_BOUNDS;
79 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
80 return TU_DYNAMIC_STENCIL_COMPARE_MASK;
81 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
82 return TU_DYNAMIC_STENCIL_WRITE_MASK;
83 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
84 return TU_DYNAMIC_STENCIL_REFERENCE;
85 default:
86 unreachable("invalid dynamic state");
87 return 0;
88 }
89 }
90
91 static gl_shader_stage
92 tu_shader_stage(VkShaderStageFlagBits stage)
93 {
94 switch (stage) {
95 case VK_SHADER_STAGE_VERTEX_BIT:
96 return MESA_SHADER_VERTEX;
97 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
98 return MESA_SHADER_TESS_CTRL;
99 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
100 return MESA_SHADER_TESS_EVAL;
101 case VK_SHADER_STAGE_GEOMETRY_BIT:
102 return MESA_SHADER_GEOMETRY;
103 case VK_SHADER_STAGE_FRAGMENT_BIT:
104 return MESA_SHADER_FRAGMENT;
105 case VK_SHADER_STAGE_COMPUTE_BIT:
106 return MESA_SHADER_COMPUTE;
107 default:
108 unreachable("invalid VkShaderStageFlagBits");
109 return MESA_SHADER_NONE;
110 }
111 }
112
113 static const VkVertexInputAttributeDescription *
114 tu_find_vertex_input_attribute(
115 const VkPipelineVertexInputStateCreateInfo *vi_info, uint32_t slot)
116 {
117 assert(slot >= VERT_ATTRIB_GENERIC0);
118 slot -= VERT_ATTRIB_GENERIC0;
119 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
120 if (vi_info->pVertexAttributeDescriptions[i].location == slot)
121 return &vi_info->pVertexAttributeDescriptions[i];
122 }
123 return NULL;
124 }
125
126 static const VkVertexInputBindingDescription *
127 tu_find_vertex_input_binding(
128 const VkPipelineVertexInputStateCreateInfo *vi_info,
129 const VkVertexInputAttributeDescription *vi_attr)
130 {
131 assert(vi_attr);
132 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
133 if (vi_info->pVertexBindingDescriptions[i].binding == vi_attr->binding)
134 return &vi_info->pVertexBindingDescriptions[i];
135 }
136 return NULL;
137 }
138
139 static bool
140 tu_logic_op_reads_dst(VkLogicOp op)
141 {
142 switch (op) {
143 case VK_LOGIC_OP_CLEAR:
144 case VK_LOGIC_OP_COPY:
145 case VK_LOGIC_OP_COPY_INVERTED:
146 case VK_LOGIC_OP_SET:
147 return false;
148 default:
149 return true;
150 }
151 }
152
153 static VkBlendFactor
154 tu_blend_factor_no_dst_alpha(VkBlendFactor factor)
155 {
156 /* treat dst alpha as 1.0 and avoid reading it */
157 switch (factor) {
158 case VK_BLEND_FACTOR_DST_ALPHA:
159 return VK_BLEND_FACTOR_ONE;
160 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
161 return VK_BLEND_FACTOR_ZERO;
162 default:
163 return factor;
164 }
165 }
166
167 static enum pc_di_primtype
168 tu6_primtype(VkPrimitiveTopology topology)
169 {
170 switch (topology) {
171 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
172 return DI_PT_POINTLIST;
173 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
174 return DI_PT_LINELIST;
175 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
176 return DI_PT_LINESTRIP;
177 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
178 return DI_PT_TRILIST;
179 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
180 return DI_PT_TRISTRIP;
181 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
182 return DI_PT_TRIFAN;
183 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
184 return DI_PT_LINE_ADJ;
185 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
186 return DI_PT_LINESTRIP_ADJ;
187 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
188 return DI_PT_TRI_ADJ;
189 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
190 return DI_PT_TRISTRIP_ADJ;
191 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
192 default:
193 unreachable("invalid primitive topology");
194 return DI_PT_NONE;
195 }
196 }
197
198 static enum adreno_compare_func
199 tu6_compare_func(VkCompareOp op)
200 {
201 switch (op) {
202 case VK_COMPARE_OP_NEVER:
203 return FUNC_NEVER;
204 case VK_COMPARE_OP_LESS:
205 return FUNC_LESS;
206 case VK_COMPARE_OP_EQUAL:
207 return FUNC_EQUAL;
208 case VK_COMPARE_OP_LESS_OR_EQUAL:
209 return FUNC_LEQUAL;
210 case VK_COMPARE_OP_GREATER:
211 return FUNC_GREATER;
212 case VK_COMPARE_OP_NOT_EQUAL:
213 return FUNC_NOTEQUAL;
214 case VK_COMPARE_OP_GREATER_OR_EQUAL:
215 return FUNC_GEQUAL;
216 case VK_COMPARE_OP_ALWAYS:
217 return FUNC_ALWAYS;
218 default:
219 unreachable("invalid VkCompareOp");
220 return FUNC_NEVER;
221 }
222 }
223
224 static enum adreno_stencil_op
225 tu6_stencil_op(VkStencilOp op)
226 {
227 switch (op) {
228 case VK_STENCIL_OP_KEEP:
229 return STENCIL_KEEP;
230 case VK_STENCIL_OP_ZERO:
231 return STENCIL_ZERO;
232 case VK_STENCIL_OP_REPLACE:
233 return STENCIL_REPLACE;
234 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
235 return STENCIL_INCR_CLAMP;
236 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
237 return STENCIL_DECR_CLAMP;
238 case VK_STENCIL_OP_INVERT:
239 return STENCIL_INVERT;
240 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
241 return STENCIL_INCR_WRAP;
242 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
243 return STENCIL_DECR_WRAP;
244 default:
245 unreachable("invalid VkStencilOp");
246 return STENCIL_KEEP;
247 }
248 }
249
250 static enum a3xx_rop_code
251 tu6_rop(VkLogicOp op)
252 {
253 switch (op) {
254 case VK_LOGIC_OP_CLEAR:
255 return ROP_CLEAR;
256 case VK_LOGIC_OP_AND:
257 return ROP_AND;
258 case VK_LOGIC_OP_AND_REVERSE:
259 return ROP_AND_REVERSE;
260 case VK_LOGIC_OP_COPY:
261 return ROP_COPY;
262 case VK_LOGIC_OP_AND_INVERTED:
263 return ROP_AND_INVERTED;
264 case VK_LOGIC_OP_NO_OP:
265 return ROP_NOOP;
266 case VK_LOGIC_OP_XOR:
267 return ROP_XOR;
268 case VK_LOGIC_OP_OR:
269 return ROP_OR;
270 case VK_LOGIC_OP_NOR:
271 return ROP_NOR;
272 case VK_LOGIC_OP_EQUIVALENT:
273 return ROP_EQUIV;
274 case VK_LOGIC_OP_INVERT:
275 return ROP_INVERT;
276 case VK_LOGIC_OP_OR_REVERSE:
277 return ROP_OR_REVERSE;
278 case VK_LOGIC_OP_COPY_INVERTED:
279 return ROP_COPY_INVERTED;
280 case VK_LOGIC_OP_OR_INVERTED:
281 return ROP_OR_INVERTED;
282 case VK_LOGIC_OP_NAND:
283 return ROP_NAND;
284 case VK_LOGIC_OP_SET:
285 return ROP_SET;
286 default:
287 unreachable("invalid VkLogicOp");
288 return ROP_NOOP;
289 }
290 }
291
292 static enum adreno_rb_blend_factor
293 tu6_blend_factor(VkBlendFactor factor)
294 {
295 switch (factor) {
296 case VK_BLEND_FACTOR_ZERO:
297 return FACTOR_ZERO;
298 case VK_BLEND_FACTOR_ONE:
299 return FACTOR_ONE;
300 case VK_BLEND_FACTOR_SRC_COLOR:
301 return FACTOR_SRC_COLOR;
302 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
303 return FACTOR_ONE_MINUS_SRC_COLOR;
304 case VK_BLEND_FACTOR_DST_COLOR:
305 return FACTOR_DST_COLOR;
306 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
307 return FACTOR_ONE_MINUS_DST_COLOR;
308 case VK_BLEND_FACTOR_SRC_ALPHA:
309 return FACTOR_SRC_ALPHA;
310 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
311 return FACTOR_ONE_MINUS_SRC_ALPHA;
312 case VK_BLEND_FACTOR_DST_ALPHA:
313 return FACTOR_DST_ALPHA;
314 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
315 return FACTOR_ONE_MINUS_DST_ALPHA;
316 case VK_BLEND_FACTOR_CONSTANT_COLOR:
317 return FACTOR_CONSTANT_COLOR;
318 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
319 return FACTOR_ONE_MINUS_CONSTANT_COLOR;
320 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
321 return FACTOR_CONSTANT_ALPHA;
322 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
323 return FACTOR_ONE_MINUS_CONSTANT_ALPHA;
324 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
325 return FACTOR_SRC_ALPHA_SATURATE;
326 case VK_BLEND_FACTOR_SRC1_COLOR:
327 return FACTOR_SRC1_COLOR;
328 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
329 return FACTOR_ONE_MINUS_SRC1_COLOR;
330 case VK_BLEND_FACTOR_SRC1_ALPHA:
331 return FACTOR_SRC1_ALPHA;
332 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
333 return FACTOR_ONE_MINUS_SRC1_ALPHA;
334 default:
335 unreachable("invalid VkBlendFactor");
336 return FACTOR_ZERO;
337 }
338 }
339
340 static enum a3xx_rb_blend_opcode
341 tu6_blend_op(VkBlendOp op)
342 {
343 switch (op) {
344 case VK_BLEND_OP_ADD:
345 return BLEND_DST_PLUS_SRC;
346 case VK_BLEND_OP_SUBTRACT:
347 return BLEND_SRC_MINUS_DST;
348 case VK_BLEND_OP_REVERSE_SUBTRACT:
349 return BLEND_DST_MINUS_SRC;
350 case VK_BLEND_OP_MIN:
351 return BLEND_MIN_DST_SRC;
352 case VK_BLEND_OP_MAX:
353 return BLEND_MAX_DST_SRC;
354 default:
355 unreachable("invalid VkBlendOp");
356 return BLEND_DST_PLUS_SRC;
357 }
358 }
359
360 static void
361 tu6_emit_vs_config(struct tu_cs *cs, const struct ir3_shader_variant *vs)
362 {
363 uint32_t sp_vs_ctrl =
364 A6XX_SP_VS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
365 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs->info.max_reg + 1) |
366 A6XX_SP_VS_CTRL_REG0_MERGEDREGS |
367 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs->branchstack);
368 if (vs->num_samp)
369 sp_vs_ctrl |= A6XX_SP_VS_CTRL_REG0_PIXLODENABLE;
370
371 uint32_t sp_vs_config = A6XX_SP_VS_CONFIG_NTEX(vs->num_samp) |
372 A6XX_SP_VS_CONFIG_NSAMP(vs->num_samp);
373 if (vs->instrlen)
374 sp_vs_config |= A6XX_SP_VS_CONFIG_ENABLED;
375
376 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_CTRL_REG0, 1);
377 tu_cs_emit(cs, sp_vs_ctrl);
378
379 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_CONFIG, 2);
380 tu_cs_emit(cs, sp_vs_config);
381 tu_cs_emit(cs, vs->instrlen);
382
383 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_VS_CNTL, 1);
384 tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(vs->constlen, 4)) | 0x100);
385 }
386
387 static void
388 tu6_emit_hs_config(struct tu_cs *cs, const struct ir3_shader_variant *hs)
389 {
390 uint32_t sp_hs_config = 0;
391 if (hs->instrlen)
392 sp_hs_config |= A6XX_SP_HS_CONFIG_ENABLED;
393
394 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
395 tu_cs_emit(cs, 0);
396
397 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_CONFIG, 2);
398 tu_cs_emit(cs, sp_hs_config);
399 tu_cs_emit(cs, hs->instrlen);
400
401 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_HS_CNTL, 1);
402 tu_cs_emit(cs, A6XX_HLSQ_HS_CNTL_CONSTLEN(align(hs->constlen, 4)));
403 }
404
405 static void
406 tu6_emit_ds_config(struct tu_cs *cs, const struct ir3_shader_variant *ds)
407 {
408 uint32_t sp_ds_config = 0;
409 if (ds->instrlen)
410 sp_ds_config |= A6XX_SP_DS_CONFIG_ENABLED;
411
412 tu_cs_emit_pkt4(cs, REG_A6XX_SP_DS_CONFIG, 2);
413 tu_cs_emit(cs, sp_ds_config);
414 tu_cs_emit(cs, ds->instrlen);
415
416 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_DS_CNTL, 1);
417 tu_cs_emit(cs, A6XX_HLSQ_DS_CNTL_CONSTLEN(align(ds->constlen, 4)));
418 }
419
420 static void
421 tu6_emit_gs_config(struct tu_cs *cs, const struct ir3_shader_variant *gs)
422 {
423 uint32_t sp_gs_config = 0;
424 if (gs->instrlen)
425 sp_gs_config |= A6XX_SP_GS_CONFIG_ENABLED;
426
427 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
428 tu_cs_emit(cs, 0);
429
430 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CONFIG, 2);
431 tu_cs_emit(cs, sp_gs_config);
432 tu_cs_emit(cs, gs->instrlen);
433
434 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_GS_CNTL, 1);
435 tu_cs_emit(cs, A6XX_HLSQ_GS_CNTL_CONSTLEN(align(gs->constlen, 4)));
436 }
437
438 static void
439 tu6_emit_fs_config(struct tu_cs *cs, const struct ir3_shader_variant *fs)
440 {
441 uint32_t sp_fs_ctrl =
442 A6XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) | 0x1000000 |
443 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs->info.max_reg + 1) |
444 A6XX_SP_FS_CTRL_REG0_MERGEDREGS |
445 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs->branchstack);
446 if (fs->total_in > 0 || fs->frag_coord)
447 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_VARYING;
448 if (fs->num_samp > 0)
449 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_PIXLODENABLE;
450
451 uint32_t sp_fs_config = A6XX_SP_FS_CONFIG_NTEX(fs->num_samp) |
452 A6XX_SP_FS_CONFIG_NSAMP(fs->num_samp);
453 if (fs->instrlen)
454 sp_fs_config |= A6XX_SP_FS_CONFIG_ENABLED;
455
456 tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_A99E, 1);
457 tu_cs_emit(cs, 0x7fc0);
458
459 tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_A9A8, 1);
460 tu_cs_emit(cs, 0);
461
462 tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_AB00, 1);
463 tu_cs_emit(cs, 0x5);
464
465 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_CTRL_REG0, 1);
466 tu_cs_emit(cs, sp_fs_ctrl);
467
468 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_CONFIG, 2);
469 tu_cs_emit(cs, sp_fs_config);
470 tu_cs_emit(cs, fs->instrlen);
471
472 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_FS_CNTL, 1);
473 tu_cs_emit(cs, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(fs->constlen, 4)) | 0x100);
474 }
475
476 static void
477 tu6_emit_vs_system_values(struct tu_cs *cs,
478 const struct ir3_shader_variant *vs)
479 {
480 const uint32_t vertexid_regid =
481 ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
482 const uint32_t instanceid_regid =
483 ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
484
485 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_1, 6);
486 tu_cs_emit(cs, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid) |
487 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid) |
488 0xfcfc0000);
489 tu_cs_emit(cs, 0x0000fcfc); /* VFD_CONTROL_2 */
490 tu_cs_emit(cs, 0xfcfcfcfc); /* VFD_CONTROL_3 */
491 tu_cs_emit(cs, 0x000000fc); /* VFD_CONTROL_4 */
492 tu_cs_emit(cs, 0x0000fcfc); /* VFD_CONTROL_5 */
493 tu_cs_emit(cs, 0x00000000); /* VFD_CONTROL_6 */
494 }
495
496 static void
497 tu6_emit_vpc(struct tu_cs *cs,
498 const struct ir3_shader_variant *vs,
499 const struct ir3_shader_variant *fs,
500 bool binning_pass)
501 {
502 struct ir3_shader_linkage linkage = { 0 };
503 ir3_link_shaders(&linkage, vs, fs);
504
505 if (vs->shader->stream_output.num_outputs && !binning_pass)
506 tu_finishme("stream output");
507
508 BITSET_DECLARE(vpc_var_enables, 128) = { 0 };
509 for (uint32_t i = 0; i < linkage.cnt; i++) {
510 const uint32_t comp_count = util_last_bit(linkage.var[i].compmask);
511 for (uint32_t j = 0; j < comp_count; j++)
512 BITSET_SET(vpc_var_enables, linkage.var[i].loc + j);
513 }
514
515 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VAR_DISABLE(0), 4);
516 tu_cs_emit(cs, ~vpc_var_enables[0]);
517 tu_cs_emit(cs, ~vpc_var_enables[1]);
518 tu_cs_emit(cs, ~vpc_var_enables[2]);
519 tu_cs_emit(cs, ~vpc_var_enables[3]);
520
521 /* a6xx finds position/pointsize at the end */
522 const uint32_t position_regid =
523 ir3_find_output_regid(vs, VARYING_SLOT_POS);
524 const uint32_t pointsize_regid =
525 ir3_find_output_regid(vs, VARYING_SLOT_PSIZ);
526 uint32_t pointsize_loc = 0xff, position_loc = 0xff;
527 if (position_regid != regid(63, 0)) {
528 position_loc = linkage.max_loc;
529 ir3_link_add(&linkage, position_regid, 0xf, linkage.max_loc);
530 }
531 if (pointsize_regid != regid(63, 0)) {
532 pointsize_loc = linkage.max_loc;
533 ir3_link_add(&linkage, pointsize_regid, 0x1, linkage.max_loc);
534 }
535
536 /* map vs outputs to VPC */
537 assert(linkage.cnt <= 32);
538 const uint32_t sp_vs_out_count = (linkage.cnt + 1) / 2;
539 const uint32_t sp_vs_vpc_dst_count = (linkage.cnt + 3) / 4;
540 uint32_t sp_vs_out[16];
541 uint32_t sp_vs_vpc_dst[8];
542 sp_vs_out[sp_vs_out_count - 1] = 0;
543 sp_vs_vpc_dst[sp_vs_vpc_dst_count - 1] = 0;
544 for (uint32_t i = 0; i < linkage.cnt; i++) {
545 ((uint16_t *) sp_vs_out)[i] =
546 A6XX_SP_VS_OUT_REG_A_REGID(linkage.var[i].regid) |
547 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage.var[i].compmask);
548 ((uint8_t *) sp_vs_vpc_dst)[i] =
549 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage.var[i].loc);
550 }
551
552 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_OUT_REG(0), sp_vs_out_count);
553 tu_cs_emit_array(cs, sp_vs_out, sp_vs_out_count);
554
555 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_VPC_DST_REG(0), sp_vs_vpc_dst_count);
556 tu_cs_emit_array(cs, sp_vs_vpc_dst, sp_vs_vpc_dst_count);
557
558 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_CNTL_0, 1);
559 tu_cs_emit(cs, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs->total_in) |
560 (fs->total_in > 0 ? A6XX_VPC_CNTL_0_VARYING : 0) |
561 0xff00ff00);
562
563 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK, 1);
564 tu_cs_emit(cs, A6XX_VPC_PACK_POSITIONLOC(position_loc) |
565 A6XX_VPC_PACK_PSIZELOC(pointsize_loc) |
566 A6XX_VPC_PACK_STRIDE_IN_VPC(linkage.max_loc));
567
568 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_GS_SIV_CNTL, 1);
569 tu_cs_emit(cs, 0x0000ffff); /* XXX */
570
571 tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
572 tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage.cnt));
573
574 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
575 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage.max_loc) |
576 (vs->writes_psize ? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE : 0));
577 }
578
579 static int
580 tu6_vpc_varying_mode(const struct ir3_shader_variant *fs,
581 uint32_t index,
582 uint8_t *interp_mode,
583 uint8_t *ps_repl_mode)
584 {
585 enum
586 {
587 INTERP_SMOOTH = 0,
588 INTERP_FLAT = 1,
589 INTERP_ZERO = 2,
590 INTERP_ONE = 3,
591 };
592 enum
593 {
594 PS_REPL_NONE = 0,
595 PS_REPL_S = 1,
596 PS_REPL_T = 2,
597 PS_REPL_ONE_MINUS_T = 3,
598 };
599
600 const uint32_t compmask = fs->inputs[index].compmask;
601
602 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
603 * fourth component occupy three consecutive varying slots
604 */
605 int shift = 0;
606 *interp_mode = 0;
607 *ps_repl_mode = 0;
608 if (fs->inputs[index].slot == VARYING_SLOT_PNTC) {
609 if (compmask & 0x1) {
610 *ps_repl_mode |= PS_REPL_S << shift;
611 shift += 2;
612 }
613 if (compmask & 0x2) {
614 *ps_repl_mode |= PS_REPL_T << shift;
615 shift += 2;
616 }
617 if (compmask & 0x4) {
618 *interp_mode |= INTERP_ZERO << shift;
619 shift += 2;
620 }
621 if (compmask & 0x8) {
622 *interp_mode |= INTERP_ONE << 6;
623 shift += 2;
624 }
625 } else if ((fs->inputs[index].interpolate == INTERP_MODE_FLAT) ||
626 fs->inputs[index].rasterflat) {
627 for (int i = 0; i < 4; i++) {
628 if (compmask & (1 << i)) {
629 *interp_mode |= INTERP_FLAT << shift;
630 shift += 2;
631 }
632 }
633 }
634
635 return shift;
636 }
637
638 static void
639 tu6_emit_vpc_varying_modes(struct tu_cs *cs,
640 const struct ir3_shader_variant *fs,
641 bool binning_pass)
642 {
643 uint32_t interp_modes[8] = { 0 };
644 uint32_t ps_repl_modes[8] = { 0 };
645
646 if (!binning_pass) {
647 for (int i = -1;
648 (i = ir3_next_varying(fs, i)) < (int) fs->inputs_count;) {
649
650 /* get the mode for input i */
651 uint8_t interp_mode;
652 uint8_t ps_repl_mode;
653 const int bits =
654 tu6_vpc_varying_mode(fs, i, &interp_mode, &ps_repl_mode);
655
656 /* OR the mode into the array */
657 const uint32_t inloc = fs->inputs[i].inloc * 2;
658 uint32_t n = inloc / 32;
659 uint32_t shift = inloc % 32;
660 interp_modes[n] |= interp_mode << shift;
661 ps_repl_modes[n] |= ps_repl_mode << shift;
662 if (shift + bits > 32) {
663 n++;
664 shift = 32 - shift;
665
666 interp_modes[n] |= interp_mode >> shift;
667 ps_repl_modes[n] |= ps_repl_mode >> shift;
668 }
669 }
670 }
671
672 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
673 tu_cs_emit_array(cs, interp_modes, 8);
674
675 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
676 tu_cs_emit_array(cs, ps_repl_modes, 8);
677 }
678
679 static void
680 tu6_emit_fs_system_values(struct tu_cs *cs,
681 const struct ir3_shader_variant *fs)
682 {
683 const uint32_t frontfacing_regid =
684 ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
685 const uint32_t sampleid_regid =
686 ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
687 const uint32_t samplemaskin_regid =
688 ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
689 const uint32_t fragcoord_xy_regid =
690 ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
691 const uint32_t fragcoord_zw_regid = (fragcoord_xy_regid != regid(63, 0))
692 ? (fragcoord_xy_regid + 2)
693 : fragcoord_xy_regid;
694 const uint32_t varyingcoord_regid =
695 ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PIXEL);
696
697 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
698 tu_cs_emit(cs, 0x7);
699 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(frontfacing_regid) |
700 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(sampleid_regid) |
701 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(samplemaskin_regid) |
702 A6XX_HLSQ_CONTROL_2_REG_SIZE(regid(63, 0)));
703 tu_cs_emit(cs,
704 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(varyingcoord_regid) |
705 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(regid(63, 0)) |
706 0xfc00fc00);
707 tu_cs_emit(cs,
708 A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(fragcoord_xy_regid) |
709 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(fragcoord_zw_regid) |
710 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(regid(63, 0)) |
711 0x0000fc00);
712 tu_cs_emit(cs, 0xfc);
713 }
714
715 static void
716 tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
717 {
718 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
719 tu_cs_emit(cs, fs->total_in > 0 ? 3 : 1);
720
721 tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_A982, 1);
722 tu_cs_emit(cs, 0); /* XXX */
723
724 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
725 tu_cs_emit(cs, 0xff); /* XXX */
726
727 uint32_t gras_cntl = 0;
728 if (fs->total_in > 0)
729 gras_cntl |= A6XX_GRAS_CNTL_VARYING;
730 if (fs->frag_coord) {
731 gras_cntl |= A6XX_GRAS_CNTL_SIZE | A6XX_GRAS_CNTL_XCOORD |
732 A6XX_GRAS_CNTL_YCOORD | A6XX_GRAS_CNTL_ZCOORD |
733 A6XX_GRAS_CNTL_WCOORD;
734 }
735
736 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CNTL, 1);
737 tu_cs_emit(cs, gras_cntl);
738
739 uint32_t rb_render_control = 0;
740 if (fs->total_in > 0) {
741 rb_render_control =
742 A6XX_RB_RENDER_CONTROL0_VARYING | A6XX_RB_RENDER_CONTROL0_UNK10;
743 }
744 if (fs->frag_coord) {
745 rb_render_control |=
746 A6XX_RB_RENDER_CONTROL0_SIZE | A6XX_RB_RENDER_CONTROL0_XCOORD |
747 A6XX_RB_RENDER_CONTROL0_YCOORD | A6XX_RB_RENDER_CONTROL0_ZCOORD |
748 A6XX_RB_RENDER_CONTROL0_WCOORD;
749 }
750
751 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CONTROL0, 2);
752 tu_cs_emit(cs, rb_render_control);
753 tu_cs_emit(cs, (fs->frag_face ? A6XX_RB_RENDER_CONTROL1_FACENESS : 0));
754 }
755
756 static void
757 tu6_emit_fs_outputs(struct tu_cs *cs,
758 const struct ir3_shader_variant *fs,
759 uint32_t mrt_count)
760 {
761 const uint32_t fragdepth_regid =
762 ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
763 uint32_t fragdata_regid[8];
764 if (fs->color0_mrt) {
765 fragdata_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
766 for (uint32_t i = 1; i < ARRAY_SIZE(fragdata_regid); i++)
767 fragdata_regid[i] = fragdata_regid[0];
768 } else {
769 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++)
770 fragdata_regid[i] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0 + i);
771 }
772
773 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_CNTL0, 2);
774 tu_cs_emit(
775 cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(fragdepth_regid) | 0xfcfc0000);
776 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count));
777
778 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
779 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++) {
780 // TODO we could have a mix of half and full precision outputs,
781 // we really need to figure out half-precision from IR3_REG_HALF
782 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid[i]) |
783 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION : 0));
784 }
785
786 tu_cs_emit_pkt4(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
787 tu_cs_emit(cs, fs->writes_pos ? A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z : 0);
788 tu_cs_emit(cs, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count));
789
790 uint32_t gras_su_depth_plane_cntl = 0;
791 uint32_t rb_depth_plane_cntl = 0;
792 if (fs->no_earlyz | fs->writes_pos) {
793 gras_su_depth_plane_cntl |= A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
794 rb_depth_plane_cntl |= A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
795 }
796
797 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
798 tu_cs_emit(cs, gras_su_depth_plane_cntl);
799
800 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
801 tu_cs_emit(cs, rb_depth_plane_cntl);
802 }
803
804 static void
805 tu6_emit_shader_object(struct tu_cs *cs,
806 gl_shader_stage stage,
807 const struct ir3_shader_variant *variant,
808 const struct tu_bo *binary_bo,
809 uint32_t binary_offset)
810 {
811 uint16_t reg;
812 uint8_t opcode;
813 enum a6xx_state_block sb;
814 switch (stage) {
815 case MESA_SHADER_VERTEX:
816 reg = REG_A6XX_SP_VS_OBJ_START_LO;
817 opcode = CP_LOAD_STATE6_GEOM;
818 sb = SB6_VS_SHADER;
819 break;
820 case MESA_SHADER_TESS_CTRL:
821 reg = REG_A6XX_SP_HS_OBJ_START_LO;
822 opcode = CP_LOAD_STATE6_GEOM;
823 sb = SB6_HS_SHADER;
824 break;
825 case MESA_SHADER_TESS_EVAL:
826 reg = REG_A6XX_SP_DS_OBJ_START_LO;
827 opcode = CP_LOAD_STATE6_GEOM;
828 sb = SB6_DS_SHADER;
829 break;
830 case MESA_SHADER_GEOMETRY:
831 reg = REG_A6XX_SP_GS_OBJ_START_LO;
832 opcode = CP_LOAD_STATE6_GEOM;
833 sb = SB6_GS_SHADER;
834 break;
835 case MESA_SHADER_FRAGMENT:
836 reg = REG_A6XX_SP_FS_OBJ_START_LO;
837 opcode = CP_LOAD_STATE6_FRAG;
838 sb = SB6_FS_SHADER;
839 break;
840 case MESA_SHADER_COMPUTE:
841 reg = REG_A6XX_SP_CS_OBJ_START_LO;
842 opcode = CP_LOAD_STATE6_FRAG;
843 sb = SB6_CS_SHADER;
844 break;
845 default:
846 unreachable("invalid gl_shader_stage");
847 opcode = CP_LOAD_STATE6_GEOM;
848 sb = SB6_VS_SHADER;
849 break;
850 }
851
852 if (!variant->instrlen) {
853 tu_cs_emit_pkt4(cs, reg, 2);
854 tu_cs_emit_qw(cs, 0);
855 return;
856 }
857
858 assert(variant->type == stage);
859
860 const uint64_t binary_iova = binary_bo->iova + binary_offset;
861 assert((binary_iova & 0x3) == 0);
862
863 tu_cs_emit_pkt4(cs, reg, 2);
864 tu_cs_emit_qw(cs, binary_iova);
865
866 /* always indirect */
867 const bool indirect = true;
868 if (indirect) {
869 tu_cs_emit_pkt7(cs, opcode, 3);
870 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
871 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
872 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
873 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
874 CP_LOAD_STATE6_0_NUM_UNIT(variant->instrlen));
875 tu_cs_emit_qw(cs, binary_iova);
876 } else {
877 const void *binary = binary_bo->map + binary_offset;
878
879 tu_cs_emit_pkt7(cs, opcode, 3 + variant->info.sizedwords);
880 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
881 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
882 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
883 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
884 CP_LOAD_STATE6_0_NUM_UNIT(variant->instrlen));
885 tu_cs_emit_qw(cs, 0);
886 tu_cs_emit_array(cs, binary, variant->info.sizedwords);
887 }
888 }
889
890 static void
891 tu6_emit_immediates(struct tu_cs *cs, const struct ir3_shader_variant *v,
892 uint32_t opcode, enum a6xx_state_block block)
893 {
894 const struct ir3_const_state *const_state = &v->shader->const_state;
895 uint32_t base = const_state->offsets.immediate;
896 int size = const_state->immediates_count;
897
898 /* truncate size to avoid writing constants that shader
899 * does not use:
900 */
901 size = MIN2(size + base, v->constlen) - base;
902
903 if (size <= 0)
904 return;
905
906 tu_cs_emit_pkt7(cs, opcode, 3 + size * 4);
907 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
908 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
909 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
910 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_FS_SHADER) |
911 CP_LOAD_STATE6_0_NUM_UNIT(size));
912 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
913 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
914
915 for (unsigned i = 0; i < size; i++) {
916 tu_cs_emit(cs, const_state->immediates[i].val[0]);
917 tu_cs_emit(cs, const_state->immediates[i].val[1]);
918 tu_cs_emit(cs, const_state->immediates[i].val[2]);
919 tu_cs_emit(cs, const_state->immediates[i].val[3]);
920 }
921 }
922
923 static void
924 tu6_emit_program(struct tu_cs *cs,
925 const struct tu_pipeline_builder *builder,
926 const struct tu_bo *binary_bo,
927 bool binning_pass)
928 {
929 static const struct ir3_shader_variant dummy_variant = {
930 .type = MESA_SHADER_NONE
931 };
932 assert(builder->shaders[MESA_SHADER_VERTEX]);
933 const struct ir3_shader_variant *vs =
934 &builder->shaders[MESA_SHADER_VERTEX]->variants[0];
935 const struct ir3_shader_variant *hs =
936 builder->shaders[MESA_SHADER_TESS_CTRL]
937 ? &builder->shaders[MESA_SHADER_TESS_CTRL]->variants[0]
938 : &dummy_variant;
939 const struct ir3_shader_variant *ds =
940 builder->shaders[MESA_SHADER_TESS_EVAL]
941 ? &builder->shaders[MESA_SHADER_TESS_EVAL]->variants[0]
942 : &dummy_variant;
943 const struct ir3_shader_variant *gs =
944 builder->shaders[MESA_SHADER_GEOMETRY]
945 ? &builder->shaders[MESA_SHADER_GEOMETRY]->variants[0]
946 : &dummy_variant;
947 const struct ir3_shader_variant *fs =
948 builder->shaders[MESA_SHADER_FRAGMENT]
949 ? &builder->shaders[MESA_SHADER_FRAGMENT]->variants[0]
950 : &dummy_variant;
951
952 if (binning_pass) {
953 vs = &builder->shaders[MESA_SHADER_VERTEX]->variants[1];
954 fs = &dummy_variant;
955 }
956
957 tu6_emit_vs_config(cs, vs);
958 tu6_emit_hs_config(cs, hs);
959 tu6_emit_ds_config(cs, ds);
960 tu6_emit_gs_config(cs, gs);
961 tu6_emit_fs_config(cs, fs);
962
963 tu6_emit_vs_system_values(cs, vs);
964 tu6_emit_vpc(cs, vs, fs, binning_pass);
965 tu6_emit_vpc_varying_modes(cs, fs, binning_pass);
966 tu6_emit_fs_system_values(cs, fs);
967 tu6_emit_fs_inputs(cs, fs);
968 tu6_emit_fs_outputs(cs, fs, builder->color_attachment_count);
969
970 tu6_emit_shader_object(cs, MESA_SHADER_VERTEX, vs, binary_bo,
971 builder->shader_offsets[MESA_SHADER_VERTEX]);
972
973 tu6_emit_shader_object(cs, MESA_SHADER_FRAGMENT, fs, binary_bo,
974 builder->shader_offsets[MESA_SHADER_FRAGMENT]);
975
976 tu6_emit_immediates(cs, vs, CP_LOAD_STATE6_GEOM, SB6_VS_SHADER);
977 if (!binning_pass)
978 tu6_emit_immediates(cs, fs, CP_LOAD_STATE6_FRAG, SB6_FS_SHADER);
979 }
980
981 static void
982 tu6_emit_vertex_input(struct tu_cs *cs,
983 const struct ir3_shader_variant *vs,
984 const VkPipelineVertexInputStateCreateInfo *vi_info,
985 uint8_t bindings[MAX_VERTEX_ATTRIBS],
986 uint16_t strides[MAX_VERTEX_ATTRIBS],
987 uint16_t offsets[MAX_VERTEX_ATTRIBS],
988 uint32_t *count)
989 {
990 uint32_t vfd_decode_idx = 0;
991
992 /* why do we go beyond inputs_count? */
993 assert(vs->inputs_count + 1 <= MAX_VERTEX_ATTRIBS);
994 for (uint32_t i = 0; i <= vs->inputs_count; i++) {
995 if (vs->inputs[i].sysval || !vs->inputs[i].compmask)
996 continue;
997
998 const VkVertexInputAttributeDescription *vi_attr =
999 tu_find_vertex_input_attribute(vi_info, vs->inputs[i].slot);
1000 const VkVertexInputBindingDescription *vi_binding =
1001 tu_find_vertex_input_binding(vi_info, vi_attr);
1002 assert(vi_attr && vi_binding);
1003
1004 const struct tu_native_format *format =
1005 tu6_get_native_format(vi_attr->format);
1006 assert(format && format->vtx >= 0);
1007
1008 uint32_t vfd_decode = A6XX_VFD_DECODE_INSTR_IDX(vfd_decode_idx) |
1009 A6XX_VFD_DECODE_INSTR_FORMAT(format->vtx) |
1010 A6XX_VFD_DECODE_INSTR_SWAP(format->swap) |
1011 A6XX_VFD_DECODE_INSTR_UNK30;
1012 if (vi_binding->inputRate == VK_VERTEX_INPUT_RATE_INSTANCE)
1013 vfd_decode |= A6XX_VFD_DECODE_INSTR_INSTANCED;
1014 if (!vk_format_is_int(vi_attr->format))
1015 vfd_decode |= A6XX_VFD_DECODE_INSTR_FLOAT;
1016
1017 const uint32_t vfd_decode_step_rate = 1;
1018
1019 const uint32_t vfd_dest_cntl =
1020 A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vs->inputs[i].compmask) |
1021 A6XX_VFD_DEST_CNTL_INSTR_REGID(vs->inputs[i].regid);
1022
1023 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_DECODE(vfd_decode_idx), 2);
1024 tu_cs_emit(cs, vfd_decode);
1025 tu_cs_emit(cs, vfd_decode_step_rate);
1026
1027 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_DEST_CNTL(vfd_decode_idx), 1);
1028 tu_cs_emit(cs, vfd_dest_cntl);
1029
1030 bindings[vfd_decode_idx] = vi_binding->binding;
1031 strides[vfd_decode_idx] = vi_binding->stride;
1032 offsets[vfd_decode_idx] = vi_attr->offset;
1033
1034 vfd_decode_idx++;
1035 }
1036
1037 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_0, 1);
1038 tu_cs_emit(
1039 cs, A6XX_VFD_CONTROL_0_VTXCNT(vfd_decode_idx) | (vfd_decode_idx << 8));
1040
1041 *count = vfd_decode_idx;
1042 }
1043
1044 static uint32_t
1045 tu6_guardband_adj(uint32_t v)
1046 {
1047 if (v > 256)
1048 return (uint32_t)(511.0 - 65.0 * (log2(v) - 8.0));
1049 else
1050 return 511;
1051 }
1052
1053 void
1054 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport)
1055 {
1056 float offsets[3];
1057 float scales[3];
1058 scales[0] = viewport->width / 2.0f;
1059 scales[1] = viewport->height / 2.0f;
1060 scales[2] = viewport->maxDepth - viewport->minDepth;
1061 offsets[0] = viewport->x + scales[0];
1062 offsets[1] = viewport->y + scales[1];
1063 offsets[2] = viewport->minDepth;
1064
1065 VkOffset2D min;
1066 VkOffset2D max;
1067 min.x = (int32_t) viewport->x;
1068 max.x = (int32_t) ceilf(viewport->x + viewport->width);
1069 if (viewport->height >= 0.0f) {
1070 min.y = (int32_t) viewport->y;
1071 max.y = (int32_t) ceilf(viewport->y + viewport->height);
1072 } else {
1073 min.y = (int32_t)(viewport->y + viewport->height);
1074 max.y = (int32_t) ceilf(viewport->y);
1075 }
1076 /* the spec allows viewport->height to be 0.0f */
1077 if (min.y == max.y)
1078 max.y++;
1079 assert(min.x >= 0 && min.x < max.x);
1080 assert(min.y >= 0 && min.y < max.y);
1081
1082 VkExtent2D guardband_adj;
1083 guardband_adj.width = tu6_guardband_adj(max.x - min.x);
1084 guardband_adj.height = tu6_guardband_adj(max.y - min.y);
1085
1086 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0, 6);
1087 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XOFFSET_0(offsets[0]));
1088 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XSCALE_0(scales[0]));
1089 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YOFFSET_0(offsets[1]));
1090 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YSCALE_0(scales[1]));
1091 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZOFFSET_0(offsets[2]));
1092 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZSCALE_0(scales[2]));
1093
1094 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
1095 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(min.x) |
1096 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(min.y));
1097 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(max.x - 1) |
1098 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(max.y - 1));
1099
1100 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
1101 tu_cs_emit(cs,
1102 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj.width) |
1103 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj.height));
1104 }
1105
1106 void
1107 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor)
1108 {
1109 const VkOffset2D min = scissor->offset;
1110 const VkOffset2D max = {
1111 scissor->offset.x + scissor->extent.width,
1112 scissor->offset.y + scissor->extent.height,
1113 };
1114
1115 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
1116 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(min.x) |
1117 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(min.y));
1118 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(max.x - 1) |
1119 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(max.y - 1));
1120 }
1121
1122 static void
1123 tu6_emit_gras_unknowns(struct tu_cs *cs)
1124 {
1125 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8000, 1);
1126 tu_cs_emit(cs, 0x80);
1127 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8001, 1);
1128 tu_cs_emit(cs, 0x0);
1129 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8004, 1);
1130 tu_cs_emit(cs, 0x0);
1131 }
1132
1133 static void
1134 tu6_emit_point_size(struct tu_cs *cs)
1135 {
1136 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POINT_MINMAX, 2);
1137 tu_cs_emit(cs, A6XX_GRAS_SU_POINT_MINMAX_MIN(1.0f / 16.0f) |
1138 A6XX_GRAS_SU_POINT_MINMAX_MAX(4092.0f));
1139 tu_cs_emit(cs, A6XX_GRAS_SU_POINT_SIZE(1.0f));
1140 }
1141
1142 static uint32_t
1143 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo *rast_info,
1144 VkSampleCountFlagBits samples)
1145 {
1146 uint32_t gras_su_cntl = 0;
1147
1148 if (rast_info->cullMode & VK_CULL_MODE_FRONT_BIT)
1149 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_FRONT;
1150 if (rast_info->cullMode & VK_CULL_MODE_BACK_BIT)
1151 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_BACK;
1152
1153 if (rast_info->frontFace == VK_FRONT_FACE_CLOCKWISE)
1154 gras_su_cntl |= A6XX_GRAS_SU_CNTL_FRONT_CW;
1155
1156 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1157
1158 if (rast_info->depthBiasEnable)
1159 gras_su_cntl |= A6XX_GRAS_SU_CNTL_POLY_OFFSET;
1160
1161 if (samples > VK_SAMPLE_COUNT_1_BIT)
1162 gras_su_cntl |= A6XX_GRAS_SU_CNTL_MSAA_ENABLE;
1163
1164 return gras_su_cntl;
1165 }
1166
1167 void
1168 tu6_emit_gras_su_cntl(struct tu_cs *cs,
1169 uint32_t gras_su_cntl,
1170 float line_width)
1171 {
1172 assert((gras_su_cntl & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK) == 0);
1173 gras_su_cntl |= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(line_width / 2.0f);
1174
1175 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_CNTL, 1);
1176 tu_cs_emit(cs, gras_su_cntl);
1177 }
1178
1179 void
1180 tu6_emit_depth_bias(struct tu_cs *cs,
1181 float constant_factor,
1182 float clamp,
1183 float slope_factor)
1184 {
1185 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
1186 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor));
1187 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor));
1188 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp));
1189 }
1190
1191 static void
1192 tu6_emit_alpha_control_disable(struct tu_cs *cs)
1193 {
1194 tu_cs_emit_pkt4(cs, REG_A6XX_RB_ALPHA_CONTROL, 1);
1195 tu_cs_emit(cs, 0);
1196 }
1197
1198 static void
1199 tu6_emit_depth_control(struct tu_cs *cs,
1200 const VkPipelineDepthStencilStateCreateInfo *ds_info)
1201 {
1202 assert(!ds_info->depthBoundsTestEnable);
1203
1204 uint32_t rb_depth_cntl = 0;
1205 if (ds_info->depthTestEnable) {
1206 rb_depth_cntl |=
1207 A6XX_RB_DEPTH_CNTL_Z_ENABLE |
1208 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) |
1209 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
1210
1211 if (ds_info->depthWriteEnable)
1212 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
1213 }
1214
1215 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_CNTL, 1);
1216 tu_cs_emit(cs, rb_depth_cntl);
1217 }
1218
1219 static void
1220 tu6_emit_stencil_control(struct tu_cs *cs,
1221 const VkPipelineDepthStencilStateCreateInfo *ds_info)
1222 {
1223 uint32_t rb_stencil_control = 0;
1224 if (ds_info->stencilTestEnable) {
1225 const VkStencilOpState *front = &ds_info->front;
1226 const VkStencilOpState *back = &ds_info->back;
1227 rb_stencil_control |=
1228 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
1229 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
1230 A6XX_RB_STENCIL_CONTROL_STENCIL_READ |
1231 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front->compareOp)) |
1232 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front->failOp)) |
1233 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front->passOp)) |
1234 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front->depthFailOp)) |
1235 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back->compareOp)) |
1236 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back->failOp)) |
1237 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back->passOp)) |
1238 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back->depthFailOp));
1239 }
1240
1241 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_CONTROL, 1);
1242 tu_cs_emit(cs, rb_stencil_control);
1243 }
1244
1245 void
1246 tu6_emit_stencil_compare_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1247 {
1248 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILMASK, 1);
1249 tu_cs_emit(
1250 cs, A6XX_RB_STENCILMASK_MASK(front) | A6XX_RB_STENCILMASK_BFMASK(back));
1251 }
1252
1253 void
1254 tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1255 {
1256 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILWRMASK, 1);
1257 tu_cs_emit(cs, A6XX_RB_STENCILWRMASK_WRMASK(front) |
1258 A6XX_RB_STENCILWRMASK_BFWRMASK(back));
1259 }
1260
1261 void
1262 tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back)
1263 {
1264 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILREF, 1);
1265 tu_cs_emit(cs,
1266 A6XX_RB_STENCILREF_REF(front) | A6XX_RB_STENCILREF_BFREF(back));
1267 }
1268
1269 static uint32_t
1270 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState *att,
1271 bool has_alpha)
1272 {
1273 const enum a3xx_rb_blend_opcode color_op = tu6_blend_op(att->colorBlendOp);
1274 const enum adreno_rb_blend_factor src_color_factor = tu6_blend_factor(
1275 has_alpha ? att->srcColorBlendFactor
1276 : tu_blend_factor_no_dst_alpha(att->srcColorBlendFactor));
1277 const enum adreno_rb_blend_factor dst_color_factor = tu6_blend_factor(
1278 has_alpha ? att->dstColorBlendFactor
1279 : tu_blend_factor_no_dst_alpha(att->dstColorBlendFactor));
1280 const enum a3xx_rb_blend_opcode alpha_op = tu6_blend_op(att->alphaBlendOp);
1281 const enum adreno_rb_blend_factor src_alpha_factor =
1282 tu6_blend_factor(att->srcAlphaBlendFactor);
1283 const enum adreno_rb_blend_factor dst_alpha_factor =
1284 tu6_blend_factor(att->dstAlphaBlendFactor);
1285
1286 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor) |
1287 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op) |
1288 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor) |
1289 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor) |
1290 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op) |
1291 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor);
1292 }
1293
1294 static uint32_t
1295 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState *att,
1296 uint32_t rb_mrt_control_rop,
1297 bool is_int,
1298 bool has_alpha)
1299 {
1300 uint32_t rb_mrt_control =
1301 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att->colorWriteMask);
1302
1303 /* ignore blending and logic op for integer attachments */
1304 if (is_int) {
1305 rb_mrt_control |= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
1306 return rb_mrt_control;
1307 }
1308
1309 rb_mrt_control |= rb_mrt_control_rop;
1310
1311 if (att->blendEnable) {
1312 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND;
1313
1314 if (has_alpha)
1315 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND2;
1316 }
1317
1318 return rb_mrt_control;
1319 }
1320
1321 static void
1322 tu6_emit_rb_mrt_controls(struct tu_cs *cs,
1323 const VkPipelineColorBlendStateCreateInfo *blend_info,
1324 const VkFormat attachment_formats[MAX_RTS],
1325 uint32_t *blend_enable_mask)
1326 {
1327 *blend_enable_mask = 0;
1328
1329 bool rop_reads_dst = false;
1330 uint32_t rb_mrt_control_rop = 0;
1331 if (blend_info->logicOpEnable) {
1332 rop_reads_dst = tu_logic_op_reads_dst(blend_info->logicOp);
1333 rb_mrt_control_rop =
1334 A6XX_RB_MRT_CONTROL_ROP_ENABLE |
1335 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info->logicOp));
1336 }
1337
1338 for (uint32_t i = 0; i < blend_info->attachmentCount; i++) {
1339 const VkPipelineColorBlendAttachmentState *att =
1340 &blend_info->pAttachments[i];
1341 const VkFormat format = attachment_formats[i];
1342
1343 uint32_t rb_mrt_control = 0;
1344 uint32_t rb_mrt_blend_control = 0;
1345 if (format != VK_FORMAT_UNDEFINED) {
1346 const bool is_int = vk_format_is_int(format);
1347 const bool has_alpha = vk_format_has_alpha(format);
1348
1349 rb_mrt_control =
1350 tu6_rb_mrt_control(att, rb_mrt_control_rop, is_int, has_alpha);
1351 rb_mrt_blend_control = tu6_rb_mrt_blend_control(att, has_alpha);
1352
1353 if (att->blendEnable || rop_reads_dst)
1354 *blend_enable_mask |= 1 << i;
1355 }
1356
1357 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
1358 tu_cs_emit(cs, rb_mrt_control);
1359 tu_cs_emit(cs, rb_mrt_blend_control);
1360 }
1361
1362 for (uint32_t i = blend_info->attachmentCount; i < MAX_RTS; i++) {
1363 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
1364 tu_cs_emit(cs, 0);
1365 tu_cs_emit(cs, 0);
1366 }
1367 }
1368
1369 static void
1370 tu6_emit_blend_control(struct tu_cs *cs,
1371 uint32_t blend_enable_mask,
1372 const VkPipelineMultisampleStateCreateInfo *msaa_info)
1373 {
1374 assert(!msaa_info->sampleShadingEnable);
1375 assert(!msaa_info->alphaToOneEnable);
1376
1377 uint32_t sp_blend_cntl = A6XX_SP_BLEND_CNTL_UNK8;
1378 if (blend_enable_mask)
1379 sp_blend_cntl |= A6XX_SP_BLEND_CNTL_ENABLED;
1380 if (msaa_info->alphaToCoverageEnable)
1381 sp_blend_cntl |= A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE;
1382
1383 const uint32_t sample_mask =
1384 msaa_info->pSampleMask ? *msaa_info->pSampleMask
1385 : ((1 << msaa_info->rasterizationSamples) - 1);
1386
1387 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
1388 uint32_t rb_blend_cntl =
1389 A6XX_RB_BLEND_CNTL_ENABLE_BLEND(blend_enable_mask) |
1390 A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND |
1391 A6XX_RB_BLEND_CNTL_SAMPLE_MASK(sample_mask);
1392 if (msaa_info->alphaToCoverageEnable)
1393 rb_blend_cntl |= A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE;
1394
1395 tu_cs_emit_pkt4(cs, REG_A6XX_SP_BLEND_CNTL, 1);
1396 tu_cs_emit(cs, sp_blend_cntl);
1397
1398 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_CNTL, 1);
1399 tu_cs_emit(cs, rb_blend_cntl);
1400 }
1401
1402 void
1403 tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4])
1404 {
1405 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_RED_F32, 4);
1406 tu_cs_emit_array(cs, (const uint32_t *) constants, 4);
1407 }
1408
1409 static VkResult
1410 tu_pipeline_builder_create_pipeline(struct tu_pipeline_builder *builder,
1411 struct tu_pipeline **out_pipeline)
1412 {
1413 struct tu_device *dev = builder->device;
1414
1415 struct tu_pipeline *pipeline =
1416 vk_zalloc2(&dev->alloc, builder->alloc, sizeof(*pipeline), 8,
1417 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1418 if (!pipeline)
1419 return VK_ERROR_OUT_OF_HOST_MEMORY;
1420
1421 tu_cs_init(&pipeline->cs, TU_CS_MODE_SUB_STREAM, 2048);
1422
1423 /* reserve the space now such that tu_cs_begin_sub_stream never fails */
1424 VkResult result = tu_cs_reserve_space(dev, &pipeline->cs, 2048);
1425 if (result != VK_SUCCESS) {
1426 vk_free2(&dev->alloc, builder->alloc, pipeline);
1427 return result;
1428 }
1429
1430 *out_pipeline = pipeline;
1431
1432 return VK_SUCCESS;
1433 }
1434
1435 static VkResult
1436 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder)
1437 {
1438 const VkPipelineShaderStageCreateInfo *stage_infos[MESA_SHADER_STAGES] = {
1439 NULL
1440 };
1441 for (uint32_t i = 0; i < builder->create_info->stageCount; i++) {
1442 gl_shader_stage stage =
1443 tu_shader_stage(builder->create_info->pStages[i].stage);
1444 stage_infos[stage] = &builder->create_info->pStages[i];
1445 }
1446
1447 struct tu_shader_compile_options options;
1448 tu_shader_compile_options_init(&options, builder->create_info);
1449
1450 /* compile shaders in reverse order */
1451 struct tu_shader *next_stage_shader = NULL;
1452 for (gl_shader_stage stage = MESA_SHADER_STAGES - 1;
1453 stage > MESA_SHADER_NONE; stage--) {
1454 const VkPipelineShaderStageCreateInfo *stage_info = stage_infos[stage];
1455 if (!stage_info)
1456 continue;
1457
1458 struct tu_shader *shader =
1459 tu_shader_create(builder->device, stage, stage_info, builder->alloc);
1460 if (!shader)
1461 return VK_ERROR_OUT_OF_HOST_MEMORY;
1462
1463 VkResult result =
1464 tu_shader_compile(builder->device, shader, next_stage_shader,
1465 &options, builder->alloc);
1466 if (result != VK_SUCCESS)
1467 return result;
1468
1469 builder->shaders[stage] = shader;
1470 builder->shader_offsets[stage] = builder->shader_total_size;
1471 builder->shader_total_size +=
1472 sizeof(uint32_t) * shader->variants[0].info.sizedwords;
1473
1474 next_stage_shader = shader;
1475 }
1476
1477 if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
1478 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1479 builder->binning_vs_offset = builder->shader_total_size;
1480 builder->shader_total_size +=
1481 sizeof(uint32_t) * vs->variants[1].info.sizedwords;
1482 }
1483
1484 return VK_SUCCESS;
1485 }
1486
1487 static VkResult
1488 tu_pipeline_builder_upload_shaders(struct tu_pipeline_builder *builder,
1489 struct tu_pipeline *pipeline)
1490 {
1491 struct tu_bo *bo = &pipeline->program.binary_bo;
1492
1493 VkResult result =
1494 tu_bo_init_new(builder->device, bo, builder->shader_total_size);
1495 if (result != VK_SUCCESS)
1496 return result;
1497
1498 result = tu_bo_map(builder->device, bo);
1499 if (result != VK_SUCCESS)
1500 return result;
1501
1502 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
1503 const struct tu_shader *shader = builder->shaders[i];
1504 if (!shader)
1505 continue;
1506
1507 memcpy(bo->map + builder->shader_offsets[i], shader->binary,
1508 sizeof(uint32_t) * shader->variants[0].info.sizedwords);
1509 }
1510
1511 if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
1512 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1513 memcpy(bo->map + builder->binning_vs_offset, vs->binning_binary,
1514 sizeof(uint32_t) * vs->variants[1].info.sizedwords);
1515 }
1516
1517 return VK_SUCCESS;
1518 }
1519
1520 static void
1521 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
1522 struct tu_pipeline *pipeline)
1523 {
1524 const VkPipelineDynamicStateCreateInfo *dynamic_info =
1525 builder->create_info->pDynamicState;
1526
1527 if (!dynamic_info)
1528 return;
1529
1530 for (uint32_t i = 0; i < dynamic_info->dynamicStateCount; i++) {
1531 pipeline->dynamic_state.mask |=
1532 tu_dynamic_state_bit(dynamic_info->pDynamicStates[i]);
1533 }
1534 }
1535
1536 static void
1537 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder *builder,
1538 struct tu_pipeline *pipeline)
1539 {
1540 struct tu_cs prog_cs;
1541 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 512, &prog_cs);
1542 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, false);
1543 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
1544
1545 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 512, &prog_cs);
1546 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, true);
1547 pipeline->program.binning_state_ib =
1548 tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
1549
1550 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
1551 if (!builder->shaders[i])
1552 continue;
1553
1554 struct tu_program_descriptor_linkage *link = &pipeline->program.link[i];
1555 struct ir3_shader *shader = builder->shaders[i]->variants[0].shader;
1556
1557 link->ubo_state = shader->ubo_state;
1558 link->constlen = builder->shaders[i]->variants[0].constlen;
1559 link->offset_ubo = shader->const_state.offsets.ubo;
1560 link->num_ubo = shader->const_state.num_ubos;
1561 link->texture_map = builder->shaders[i]->texture_map;
1562 link->sampler_map = builder->shaders[i]->sampler_map;
1563 link->ubo_map = builder->shaders[i]->ubo_map;
1564 }
1565 }
1566
1567 static void
1568 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder *builder,
1569 struct tu_pipeline *pipeline)
1570 {
1571 const VkPipelineVertexInputStateCreateInfo *vi_info =
1572 builder->create_info->pVertexInputState;
1573 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1574
1575 struct tu_cs vi_cs;
1576 tu_cs_begin_sub_stream(builder->device, &pipeline->cs,
1577 MAX_VERTEX_ATTRIBS * 5 + 2, &vi_cs);
1578 tu6_emit_vertex_input(&vi_cs, &vs->variants[0], vi_info,
1579 pipeline->vi.bindings, pipeline->vi.strides,
1580 pipeline->vi.offsets, &pipeline->vi.count);
1581 pipeline->vi.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
1582
1583 if (vs->has_binning_pass) {
1584 tu_cs_begin_sub_stream(builder->device, &pipeline->cs,
1585 MAX_VERTEX_ATTRIBS * 5 + 2, &vi_cs);
1586 tu6_emit_vertex_input(
1587 &vi_cs, &vs->variants[1], vi_info, pipeline->vi.binning_bindings,
1588 pipeline->vi.binning_strides, pipeline->vi.binning_offsets,
1589 &pipeline->vi.binning_count);
1590 pipeline->vi.binning_state_ib =
1591 tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
1592 }
1593 }
1594
1595 static void
1596 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder *builder,
1597 struct tu_pipeline *pipeline)
1598 {
1599 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1600 builder->create_info->pInputAssemblyState;
1601
1602 pipeline->ia.primtype = tu6_primtype(ia_info->topology);
1603 pipeline->ia.primitive_restart = ia_info->primitiveRestartEnable;
1604 }
1605
1606 static void
1607 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder *builder,
1608 struct tu_pipeline *pipeline)
1609 {
1610 /* The spec says:
1611 *
1612 * pViewportState is a pointer to an instance of the
1613 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
1614 * pipeline has rasterization disabled."
1615 *
1616 * We leave the relevant registers stale in that case.
1617 */
1618 if (builder->rasterizer_discard)
1619 return;
1620
1621 const VkPipelineViewportStateCreateInfo *vp_info =
1622 builder->create_info->pViewportState;
1623
1624 struct tu_cs vp_cs;
1625 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 15, &vp_cs);
1626
1627 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_VIEWPORT)) {
1628 assert(vp_info->viewportCount == 1);
1629 tu6_emit_viewport(&vp_cs, vp_info->pViewports);
1630 }
1631
1632 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_SCISSOR)) {
1633 assert(vp_info->scissorCount == 1);
1634 tu6_emit_scissor(&vp_cs, vp_info->pScissors);
1635 }
1636
1637 pipeline->vp.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vp_cs);
1638 }
1639
1640 static void
1641 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder,
1642 struct tu_pipeline *pipeline)
1643 {
1644 const VkPipelineRasterizationStateCreateInfo *rast_info =
1645 builder->create_info->pRasterizationState;
1646
1647 assert(!rast_info->depthClampEnable);
1648 assert(rast_info->polygonMode == VK_POLYGON_MODE_FILL);
1649
1650 struct tu_cs rast_cs;
1651 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 20, &rast_cs);
1652
1653 /* move to hw ctx init? */
1654 tu6_emit_gras_unknowns(&rast_cs);
1655 tu6_emit_point_size(&rast_cs);
1656
1657 const uint32_t gras_su_cntl =
1658 tu6_gras_su_cntl(rast_info, builder->samples);
1659
1660 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH))
1661 tu6_emit_gras_su_cntl(&rast_cs, gras_su_cntl, rast_info->lineWidth);
1662
1663 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_DEPTH_BIAS)) {
1664 tu6_emit_depth_bias(&rast_cs, rast_info->depthBiasConstantFactor,
1665 rast_info->depthBiasClamp,
1666 rast_info->depthBiasSlopeFactor);
1667 }
1668
1669 pipeline->rast.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &rast_cs);
1670
1671 pipeline->rast.gras_su_cntl = gras_su_cntl;
1672 }
1673
1674 static void
1675 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
1676 struct tu_pipeline *pipeline)
1677 {
1678 /* The spec says:
1679 *
1680 * pDepthStencilState is a pointer to an instance of the
1681 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
1682 * the pipeline has rasterization disabled or if the subpass of the
1683 * render pass the pipeline is created against does not use a
1684 * depth/stencil attachment.
1685 *
1686 * We disable both depth and stenil tests in those cases.
1687 */
1688 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info;
1689 const VkPipelineDepthStencilStateCreateInfo *ds_info =
1690 builder->use_depth_stencil_attachment
1691 ? builder->create_info->pDepthStencilState
1692 : &dummy_ds_info;
1693
1694 struct tu_cs ds_cs;
1695 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 12, &ds_cs);
1696
1697 /* move to hw ctx init? */
1698 tu6_emit_alpha_control_disable(&ds_cs);
1699
1700 tu6_emit_depth_control(&ds_cs, ds_info);
1701 tu6_emit_stencil_control(&ds_cs, ds_info);
1702
1703 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
1704 tu6_emit_stencil_compare_mask(&ds_cs, ds_info->front.compareMask,
1705 ds_info->back.compareMask);
1706 }
1707 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
1708 tu6_emit_stencil_write_mask(&ds_cs, ds_info->front.writeMask,
1709 ds_info->back.writeMask);
1710 }
1711 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
1712 tu6_emit_stencil_reference(&ds_cs, ds_info->front.reference,
1713 ds_info->back.reference);
1714 }
1715
1716 pipeline->ds.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &ds_cs);
1717 }
1718
1719 static void
1720 tu_pipeline_builder_parse_multisample_and_color_blend(
1721 struct tu_pipeline_builder *builder, struct tu_pipeline *pipeline)
1722 {
1723 /* The spec says:
1724 *
1725 * pMultisampleState is a pointer to an instance of the
1726 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
1727 * has rasterization disabled.
1728 *
1729 * Also,
1730 *
1731 * pColorBlendState is a pointer to an instance of the
1732 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
1733 * pipeline has rasterization disabled or if the subpass of the render
1734 * pass the pipeline is created against does not use any color
1735 * attachments.
1736 *
1737 * We leave the relevant registers stale when rasterization is disabled.
1738 */
1739 if (builder->rasterizer_discard)
1740 return;
1741
1742 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info;
1743 const VkPipelineMultisampleStateCreateInfo *msaa_info =
1744 builder->create_info->pMultisampleState;
1745 const VkPipelineColorBlendStateCreateInfo *blend_info =
1746 builder->use_color_attachments ? builder->create_info->pColorBlendState
1747 : &dummy_blend_info;
1748
1749 struct tu_cs blend_cs;
1750 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, MAX_RTS * 3 + 9,
1751 &blend_cs);
1752
1753 uint32_t blend_enable_mask;
1754 tu6_emit_rb_mrt_controls(&blend_cs, blend_info,
1755 builder->color_attachment_formats,
1756 &blend_enable_mask);
1757
1758 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_BLEND_CONSTANTS))
1759 tu6_emit_blend_constants(&blend_cs, blend_info->blendConstants);
1760
1761 tu6_emit_blend_control(&blend_cs, blend_enable_mask, msaa_info);
1762
1763 pipeline->blend.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &blend_cs);
1764 }
1765
1766 static void
1767 tu_pipeline_finish(struct tu_pipeline *pipeline,
1768 struct tu_device *dev,
1769 const VkAllocationCallbacks *alloc)
1770 {
1771 tu_cs_finish(dev, &pipeline->cs);
1772
1773 if (pipeline->program.binary_bo.gem_handle)
1774 tu_bo_finish(dev, &pipeline->program.binary_bo);
1775 }
1776
1777 static VkResult
1778 tu_pipeline_builder_build(struct tu_pipeline_builder *builder,
1779 struct tu_pipeline **pipeline)
1780 {
1781 VkResult result = tu_pipeline_builder_create_pipeline(builder, pipeline);
1782 if (result != VK_SUCCESS)
1783 return result;
1784
1785 /* compile and upload shaders */
1786 result = tu_pipeline_builder_compile_shaders(builder);
1787 if (result == VK_SUCCESS)
1788 result = tu_pipeline_builder_upload_shaders(builder, *pipeline);
1789 if (result != VK_SUCCESS) {
1790 tu_pipeline_finish(*pipeline, builder->device, builder->alloc);
1791 vk_free2(&builder->device->alloc, builder->alloc, *pipeline);
1792 *pipeline = VK_NULL_HANDLE;
1793
1794 return result;
1795 }
1796
1797 tu_pipeline_builder_parse_dynamic(builder, *pipeline);
1798 tu_pipeline_builder_parse_shader_stages(builder, *pipeline);
1799 tu_pipeline_builder_parse_vertex_input(builder, *pipeline);
1800 tu_pipeline_builder_parse_input_assembly(builder, *pipeline);
1801 tu_pipeline_builder_parse_viewport(builder, *pipeline);
1802 tu_pipeline_builder_parse_rasterization(builder, *pipeline);
1803 tu_pipeline_builder_parse_depth_stencil(builder, *pipeline);
1804 tu_pipeline_builder_parse_multisample_and_color_blend(builder, *pipeline);
1805
1806 /* we should have reserved enough space upfront such that the CS never
1807 * grows
1808 */
1809 assert((*pipeline)->cs.bo_count == 1);
1810
1811 return VK_SUCCESS;
1812 }
1813
1814 static void
1815 tu_pipeline_builder_finish(struct tu_pipeline_builder *builder)
1816 {
1817 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
1818 if (!builder->shaders[i])
1819 continue;
1820 tu_shader_destroy(builder->device, builder->shaders[i], builder->alloc);
1821 }
1822 }
1823
1824 static void
1825 tu_pipeline_builder_init_graphics(
1826 struct tu_pipeline_builder *builder,
1827 struct tu_device *dev,
1828 struct tu_pipeline_cache *cache,
1829 const VkGraphicsPipelineCreateInfo *create_info,
1830 const VkAllocationCallbacks *alloc)
1831 {
1832 *builder = (struct tu_pipeline_builder) {
1833 .device = dev,
1834 .cache = cache,
1835 .create_info = create_info,
1836 .alloc = alloc,
1837 };
1838
1839 builder->rasterizer_discard =
1840 create_info->pRasterizationState->rasterizerDiscardEnable;
1841
1842 if (builder->rasterizer_discard) {
1843 builder->samples = VK_SAMPLE_COUNT_1_BIT;
1844 } else {
1845 builder->samples = create_info->pMultisampleState->rasterizationSamples;
1846
1847 const struct tu_render_pass *pass =
1848 tu_render_pass_from_handle(create_info->renderPass);
1849 const struct tu_subpass *subpass =
1850 &pass->subpasses[create_info->subpass];
1851
1852 builder->use_depth_stencil_attachment =
1853 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED;
1854
1855 assert(subpass->color_count ==
1856 create_info->pColorBlendState->attachmentCount);
1857 builder->color_attachment_count = subpass->color_count;
1858 for (uint32_t i = 0; i < subpass->color_count; i++) {
1859 const uint32_t a = subpass->color_attachments[i].attachment;
1860 if (a == VK_ATTACHMENT_UNUSED)
1861 continue;
1862
1863 builder->color_attachment_formats[i] = pass->attachments[a].format;
1864 builder->use_color_attachments = true;
1865 }
1866 }
1867 }
1868
1869 VkResult
1870 tu_CreateGraphicsPipelines(VkDevice device,
1871 VkPipelineCache pipelineCache,
1872 uint32_t count,
1873 const VkGraphicsPipelineCreateInfo *pCreateInfos,
1874 const VkAllocationCallbacks *pAllocator,
1875 VkPipeline *pPipelines)
1876 {
1877 TU_FROM_HANDLE(tu_device, dev, device);
1878 TU_FROM_HANDLE(tu_pipeline_cache, cache, pipelineCache);
1879 VkResult final_result = VK_SUCCESS;
1880
1881 for (uint32_t i = 0; i < count; i++) {
1882 struct tu_pipeline_builder builder;
1883 tu_pipeline_builder_init_graphics(&builder, dev, cache,
1884 &pCreateInfos[i], pAllocator);
1885
1886 struct tu_pipeline *pipeline = NULL;
1887 VkResult result = tu_pipeline_builder_build(&builder, &pipeline);
1888 tu_pipeline_builder_finish(&builder);
1889
1890 if (result == VK_SUCCESS) {
1891 pPipelines[i] = tu_pipeline_to_handle(pipeline);
1892 } else {
1893 pPipelines[i] = NULL;
1894 final_result = result;
1895 }
1896 }
1897
1898 return final_result;
1899 }
1900
1901 static VkResult
1902 tu_compute_pipeline_create(VkDevice _device,
1903 VkPipelineCache _cache,
1904 const VkComputePipelineCreateInfo *pCreateInfo,
1905 const VkAllocationCallbacks *pAllocator,
1906 VkPipeline *pPipeline)
1907 {
1908 return VK_SUCCESS;
1909 }
1910
1911 VkResult
1912 tu_CreateComputePipelines(VkDevice _device,
1913 VkPipelineCache pipelineCache,
1914 uint32_t count,
1915 const VkComputePipelineCreateInfo *pCreateInfos,
1916 const VkAllocationCallbacks *pAllocator,
1917 VkPipeline *pPipelines)
1918 {
1919 VkResult result = VK_SUCCESS;
1920
1921 unsigned i = 0;
1922 for (; i < count; i++) {
1923 VkResult r;
1924 r = tu_compute_pipeline_create(_device, pipelineCache, &pCreateInfos[i],
1925 pAllocator, &pPipelines[i]);
1926 if (r != VK_SUCCESS) {
1927 result = r;
1928 pPipelines[i] = VK_NULL_HANDLE;
1929 }
1930 }
1931
1932 return result;
1933 }
1934
1935 void
1936 tu_DestroyPipeline(VkDevice _device,
1937 VkPipeline _pipeline,
1938 const VkAllocationCallbacks *pAllocator)
1939 {
1940 TU_FROM_HANDLE(tu_device, dev, _device);
1941 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
1942
1943 if (!_pipeline)
1944 return;
1945
1946 tu_pipeline_finish(pipeline, dev, pAllocator);
1947 vk_free2(&dev->alloc, pAllocator, pipeline);
1948 }