2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 #include "tu_private.h"
30 #include "ir3/ir3_nir.h"
31 #include "main/menums.h"
33 #include "nir/nir_builder.h"
34 #include "spirv/nir_spirv.h"
35 #include "util/debug.h"
36 #include "util/mesa-sha1.h"
37 #include "util/u_atomic.h"
38 #include "vk_format.h"
43 struct tu_pipeline_builder
45 struct tu_device
*device
;
46 struct tu_pipeline_cache
*cache
;
47 struct tu_pipeline_layout
*layout
;
48 const VkAllocationCallbacks
*alloc
;
49 const VkGraphicsPipelineCreateInfo
*create_info
;
51 struct tu_shader
*shaders
[MESA_SHADER_STAGES
];
52 uint32_t shader_offsets
[MESA_SHADER_STAGES
];
53 uint32_t binning_vs_offset
;
54 uint32_t shader_total_size
;
56 bool rasterizer_discard
;
57 /* these states are affectd by rasterizer_discard */
58 VkSampleCountFlagBits samples
;
59 bool use_depth_stencil_attachment
;
60 bool use_color_attachments
;
61 uint32_t color_attachment_count
;
62 VkFormat color_attachment_formats
[MAX_RTS
];
65 static enum tu_dynamic_state_bits
66 tu_dynamic_state_bit(VkDynamicState state
)
69 case VK_DYNAMIC_STATE_VIEWPORT
:
70 return TU_DYNAMIC_VIEWPORT
;
71 case VK_DYNAMIC_STATE_SCISSOR
:
72 return TU_DYNAMIC_SCISSOR
;
73 case VK_DYNAMIC_STATE_LINE_WIDTH
:
74 return TU_DYNAMIC_LINE_WIDTH
;
75 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
76 return TU_DYNAMIC_DEPTH_BIAS
;
77 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
78 return TU_DYNAMIC_BLEND_CONSTANTS
;
79 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
80 return TU_DYNAMIC_DEPTH_BOUNDS
;
81 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
82 return TU_DYNAMIC_STENCIL_COMPARE_MASK
;
83 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
84 return TU_DYNAMIC_STENCIL_WRITE_MASK
;
85 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
86 return TU_DYNAMIC_STENCIL_REFERENCE
;
88 unreachable("invalid dynamic state");
93 static gl_shader_stage
94 tu_shader_stage(VkShaderStageFlagBits stage
)
97 case VK_SHADER_STAGE_VERTEX_BIT
:
98 return MESA_SHADER_VERTEX
;
99 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
100 return MESA_SHADER_TESS_CTRL
;
101 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
102 return MESA_SHADER_TESS_EVAL
;
103 case VK_SHADER_STAGE_GEOMETRY_BIT
:
104 return MESA_SHADER_GEOMETRY
;
105 case VK_SHADER_STAGE_FRAGMENT_BIT
:
106 return MESA_SHADER_FRAGMENT
;
107 case VK_SHADER_STAGE_COMPUTE_BIT
:
108 return MESA_SHADER_COMPUTE
;
110 unreachable("invalid VkShaderStageFlagBits");
111 return MESA_SHADER_NONE
;
115 static const VkVertexInputAttributeDescription
*
116 tu_find_vertex_input_attribute(
117 const VkPipelineVertexInputStateCreateInfo
*vi_info
, uint32_t slot
)
119 assert(slot
>= VERT_ATTRIB_GENERIC0
);
120 slot
-= VERT_ATTRIB_GENERIC0
;
121 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
122 if (vi_info
->pVertexAttributeDescriptions
[i
].location
== slot
)
123 return &vi_info
->pVertexAttributeDescriptions
[i
];
128 static const VkVertexInputBindingDescription
*
129 tu_find_vertex_input_binding(
130 const VkPipelineVertexInputStateCreateInfo
*vi_info
,
131 const VkVertexInputAttributeDescription
*vi_attr
)
134 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
135 if (vi_info
->pVertexBindingDescriptions
[i
].binding
== vi_attr
->binding
)
136 return &vi_info
->pVertexBindingDescriptions
[i
];
142 tu_logic_op_reads_dst(VkLogicOp op
)
145 case VK_LOGIC_OP_CLEAR
:
146 case VK_LOGIC_OP_COPY
:
147 case VK_LOGIC_OP_COPY_INVERTED
:
148 case VK_LOGIC_OP_SET
:
156 tu_blend_factor_no_dst_alpha(VkBlendFactor factor
)
158 /* treat dst alpha as 1.0 and avoid reading it */
160 case VK_BLEND_FACTOR_DST_ALPHA
:
161 return VK_BLEND_FACTOR_ONE
;
162 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
163 return VK_BLEND_FACTOR_ZERO
;
169 static enum pc_di_primtype
170 tu6_primtype(VkPrimitiveTopology topology
)
173 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
174 return DI_PT_POINTLIST
;
175 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
176 return DI_PT_LINELIST
;
177 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
178 return DI_PT_LINESTRIP
;
179 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
180 return DI_PT_TRILIST
;
181 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
182 return DI_PT_TRISTRIP
;
183 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
185 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
186 return DI_PT_LINE_ADJ
;
187 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
188 return DI_PT_LINESTRIP_ADJ
;
189 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
190 return DI_PT_TRI_ADJ
;
191 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
192 return DI_PT_TRISTRIP_ADJ
;
193 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
195 unreachable("invalid primitive topology");
200 static enum adreno_compare_func
201 tu6_compare_func(VkCompareOp op
)
204 case VK_COMPARE_OP_NEVER
:
206 case VK_COMPARE_OP_LESS
:
208 case VK_COMPARE_OP_EQUAL
:
210 case VK_COMPARE_OP_LESS_OR_EQUAL
:
212 case VK_COMPARE_OP_GREATER
:
214 case VK_COMPARE_OP_NOT_EQUAL
:
215 return FUNC_NOTEQUAL
;
216 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
218 case VK_COMPARE_OP_ALWAYS
:
221 unreachable("invalid VkCompareOp");
226 static enum adreno_stencil_op
227 tu6_stencil_op(VkStencilOp op
)
230 case VK_STENCIL_OP_KEEP
:
232 case VK_STENCIL_OP_ZERO
:
234 case VK_STENCIL_OP_REPLACE
:
235 return STENCIL_REPLACE
;
236 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
237 return STENCIL_INCR_CLAMP
;
238 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
239 return STENCIL_DECR_CLAMP
;
240 case VK_STENCIL_OP_INVERT
:
241 return STENCIL_INVERT
;
242 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
243 return STENCIL_INCR_WRAP
;
244 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
245 return STENCIL_DECR_WRAP
;
247 unreachable("invalid VkStencilOp");
252 static enum a3xx_rop_code
253 tu6_rop(VkLogicOp op
)
256 case VK_LOGIC_OP_CLEAR
:
258 case VK_LOGIC_OP_AND
:
260 case VK_LOGIC_OP_AND_REVERSE
:
261 return ROP_AND_REVERSE
;
262 case VK_LOGIC_OP_COPY
:
264 case VK_LOGIC_OP_AND_INVERTED
:
265 return ROP_AND_INVERTED
;
266 case VK_LOGIC_OP_NO_OP
:
268 case VK_LOGIC_OP_XOR
:
272 case VK_LOGIC_OP_NOR
:
274 case VK_LOGIC_OP_EQUIVALENT
:
276 case VK_LOGIC_OP_INVERT
:
278 case VK_LOGIC_OP_OR_REVERSE
:
279 return ROP_OR_REVERSE
;
280 case VK_LOGIC_OP_COPY_INVERTED
:
281 return ROP_COPY_INVERTED
;
282 case VK_LOGIC_OP_OR_INVERTED
:
283 return ROP_OR_INVERTED
;
284 case VK_LOGIC_OP_NAND
:
286 case VK_LOGIC_OP_SET
:
289 unreachable("invalid VkLogicOp");
294 static enum adreno_rb_blend_factor
295 tu6_blend_factor(VkBlendFactor factor
)
298 case VK_BLEND_FACTOR_ZERO
:
300 case VK_BLEND_FACTOR_ONE
:
302 case VK_BLEND_FACTOR_SRC_COLOR
:
303 return FACTOR_SRC_COLOR
;
304 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
305 return FACTOR_ONE_MINUS_SRC_COLOR
;
306 case VK_BLEND_FACTOR_DST_COLOR
:
307 return FACTOR_DST_COLOR
;
308 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
309 return FACTOR_ONE_MINUS_DST_COLOR
;
310 case VK_BLEND_FACTOR_SRC_ALPHA
:
311 return FACTOR_SRC_ALPHA
;
312 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
313 return FACTOR_ONE_MINUS_SRC_ALPHA
;
314 case VK_BLEND_FACTOR_DST_ALPHA
:
315 return FACTOR_DST_ALPHA
;
316 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
317 return FACTOR_ONE_MINUS_DST_ALPHA
;
318 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
319 return FACTOR_CONSTANT_COLOR
;
320 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
321 return FACTOR_ONE_MINUS_CONSTANT_COLOR
;
322 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
323 return FACTOR_CONSTANT_ALPHA
;
324 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
325 return FACTOR_ONE_MINUS_CONSTANT_ALPHA
;
326 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
327 return FACTOR_SRC_ALPHA_SATURATE
;
328 case VK_BLEND_FACTOR_SRC1_COLOR
:
329 return FACTOR_SRC1_COLOR
;
330 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
331 return FACTOR_ONE_MINUS_SRC1_COLOR
;
332 case VK_BLEND_FACTOR_SRC1_ALPHA
:
333 return FACTOR_SRC1_ALPHA
;
334 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
335 return FACTOR_ONE_MINUS_SRC1_ALPHA
;
337 unreachable("invalid VkBlendFactor");
342 static enum a3xx_rb_blend_opcode
343 tu6_blend_op(VkBlendOp op
)
346 case VK_BLEND_OP_ADD
:
347 return BLEND_DST_PLUS_SRC
;
348 case VK_BLEND_OP_SUBTRACT
:
349 return BLEND_SRC_MINUS_DST
;
350 case VK_BLEND_OP_REVERSE_SUBTRACT
:
351 return BLEND_DST_MINUS_SRC
;
352 case VK_BLEND_OP_MIN
:
353 return BLEND_MIN_DST_SRC
;
354 case VK_BLEND_OP_MAX
:
355 return BLEND_MAX_DST_SRC
;
357 unreachable("invalid VkBlendOp");
358 return BLEND_DST_PLUS_SRC
;
363 tu_shader_nibo(const struct tu_shader
*shader
)
365 /* Don't use ir3_shader_nibo(), because that would include declared but
366 * unused storage images and SSBOs.
368 return shader
->ssbo_map
.num_desc
+ shader
->image_map
.num_desc
;
372 tu6_emit_vs_config(struct tu_cs
*cs
, struct tu_shader
*shader
,
373 const struct ir3_shader_variant
*vs
)
375 uint32_t sp_vs_ctrl
=
376 A6XX_SP_VS_CTRL_REG0_THREADSIZE(FOUR_QUADS
) |
377 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs
->info
.max_reg
+ 1) |
378 A6XX_SP_VS_CTRL_REG0_MERGEDREGS
|
379 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs
->branchstack
);
381 sp_vs_ctrl
|= A6XX_SP_VS_CTRL_REG0_PIXLODENABLE
;
382 if (vs
->need_fine_derivatives
)
383 sp_vs_ctrl
|= A6XX_SP_VS_CTRL_REG0_DIFF_FINE
;
385 uint32_t sp_vs_config
= A6XX_SP_VS_CONFIG_NTEX(shader
->texture_map
.num_desc
) |
386 A6XX_SP_VS_CONFIG_NSAMP(shader
->sampler_map
.num_desc
);
388 sp_vs_config
|= A6XX_SP_VS_CONFIG_ENABLED
;
390 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_VS_CTRL_REG0
, 1);
391 tu_cs_emit(cs
, sp_vs_ctrl
);
393 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_VS_CONFIG
, 2);
394 tu_cs_emit(cs
, sp_vs_config
);
395 tu_cs_emit(cs
, vs
->instrlen
);
397 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_VS_CNTL
, 1);
398 tu_cs_emit(cs
, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(vs
->constlen
, 4)) |
399 A6XX_HLSQ_VS_CNTL_ENABLED
);
403 tu6_emit_hs_config(struct tu_cs
*cs
, struct tu_shader
*shader
,
404 const struct ir3_shader_variant
*hs
)
406 uint32_t sp_hs_config
= 0;
408 sp_hs_config
|= A6XX_SP_HS_CONFIG_ENABLED
;
410 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_HS_UNKNOWN_A831
, 1);
413 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_HS_CONFIG
, 2);
414 tu_cs_emit(cs
, sp_hs_config
);
415 tu_cs_emit(cs
, hs
->instrlen
);
417 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_HS_CNTL
, 1);
418 tu_cs_emit(cs
, A6XX_HLSQ_HS_CNTL_CONSTLEN(align(hs
->constlen
, 4)));
422 tu6_emit_ds_config(struct tu_cs
*cs
, struct tu_shader
*shader
,
423 const struct ir3_shader_variant
*ds
)
425 uint32_t sp_ds_config
= 0;
427 sp_ds_config
|= A6XX_SP_DS_CONFIG_ENABLED
;
429 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_DS_CONFIG
, 2);
430 tu_cs_emit(cs
, sp_ds_config
);
431 tu_cs_emit(cs
, ds
->instrlen
);
433 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_DS_CNTL
, 1);
434 tu_cs_emit(cs
, A6XX_HLSQ_DS_CNTL_CONSTLEN(align(ds
->constlen
, 4)));
438 tu6_emit_gs_config(struct tu_cs
*cs
, struct tu_shader
*shader
,
439 const struct ir3_shader_variant
*gs
)
441 bool has_gs
= gs
->type
!= MESA_SHADER_NONE
;
442 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_UNKNOWN_A871
, 1);
445 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_CONFIG
, 2);
446 tu_cs_emit(cs
, COND(has_gs
,
447 A6XX_SP_GS_CONFIG_ENABLED
|
448 A6XX_SP_GS_CONFIG_NIBO(ir3_shader_nibo(gs
)) |
449 A6XX_SP_GS_CONFIG_NTEX(gs
->num_samp
) |
450 A6XX_SP_GS_CONFIG_NSAMP(gs
->num_samp
)));
451 tu_cs_emit(cs
, gs
->instrlen
);
453 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_GS_CNTL
, 1);
454 tu_cs_emit(cs
, COND(has_gs
, A6XX_HLSQ_GS_CNTL_ENABLED
) |
455 A6XX_HLSQ_GS_CNTL_CONSTLEN(align(gs
->constlen
, 4)));
459 tu6_emit_fs_config(struct tu_cs
*cs
, struct tu_shader
*shader
,
460 const struct ir3_shader_variant
*fs
)
462 uint32_t sp_fs_ctrl
=
463 A6XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS
) | 0x1000000 |
464 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs
->info
.max_reg
+ 1) |
465 A6XX_SP_FS_CTRL_REG0_MERGEDREGS
|
466 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs
->branchstack
);
467 if (fs
->total_in
> 0)
468 sp_fs_ctrl
|= A6XX_SP_FS_CTRL_REG0_VARYING
;
470 sp_fs_ctrl
|= A6XX_SP_FS_CTRL_REG0_PIXLODENABLE
;
471 if (fs
->need_fine_derivatives
)
472 sp_fs_ctrl
|= A6XX_SP_FS_CTRL_REG0_DIFF_FINE
;
474 uint32_t sp_fs_config
= 0;
475 unsigned shader_nibo
= 0;
477 shader_nibo
= tu_shader_nibo(shader
);
478 sp_fs_config
= A6XX_SP_FS_CONFIG_NTEX(shader
->texture_map
.num_desc
) |
479 A6XX_SP_FS_CONFIG_NSAMP(shader
->sampler_map
.num_desc
) |
480 A6XX_SP_FS_CONFIG_NIBO(shader_nibo
);
484 sp_fs_config
|= A6XX_SP_FS_CONFIG_ENABLED
;
486 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_CTRL_REG0
, 1);
487 tu_cs_emit(cs
, sp_fs_ctrl
);
489 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_CONFIG
, 2);
490 tu_cs_emit(cs
, sp_fs_config
);
491 tu_cs_emit(cs
, fs
->instrlen
);
493 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_FS_CNTL
, 1);
494 tu_cs_emit(cs
, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(fs
->constlen
, 4)) |
495 A6XX_HLSQ_FS_CNTL_ENABLED
);
497 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_IBO_COUNT
, 1);
498 tu_cs_emit(cs
, shader_nibo
);
502 tu6_emit_cs_config(struct tu_cs
*cs
, const struct tu_shader
*shader
,
503 const struct ir3_shader_variant
*v
)
505 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_UPDATE_CNTL
, 1);
506 tu_cs_emit(cs
, 0xff);
508 unsigned constlen
= align(v
->constlen
, 4);
509 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_CS_CNTL
, 1);
510 tu_cs_emit(cs
, A6XX_HLSQ_CS_CNTL_CONSTLEN(constlen
) |
511 A6XX_HLSQ_CS_CNTL_ENABLED
);
513 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_CS_CONFIG
, 2);
514 tu_cs_emit(cs
, A6XX_SP_CS_CONFIG_ENABLED
|
515 A6XX_SP_CS_CONFIG_NIBO(tu_shader_nibo(shader
)) |
516 A6XX_SP_CS_CONFIG_NTEX(shader
->texture_map
.num_desc
) |
517 A6XX_SP_CS_CONFIG_NSAMP(shader
->sampler_map
.num_desc
));
518 tu_cs_emit(cs
, v
->instrlen
);
520 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_CS_CTRL_REG0
, 1);
521 tu_cs_emit(cs
, A6XX_SP_CS_CTRL_REG0_THREADSIZE(FOUR_QUADS
) |
522 A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(v
->info
.max_reg
+ 1) |
523 A6XX_SP_CS_CTRL_REG0_MERGEDREGS
|
524 A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(v
->branchstack
) |
525 COND(v
->need_pixlod
, A6XX_SP_CS_CTRL_REG0_PIXLODENABLE
) |
526 COND(v
->need_fine_derivatives
, A6XX_SP_CS_CTRL_REG0_DIFF_FINE
));
528 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_CS_UNKNOWN_A9B1
, 1);
529 tu_cs_emit(cs
, 0x41);
531 uint32_t local_invocation_id
=
532 ir3_find_sysval_regid(v
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
);
533 uint32_t work_group_id
=
534 ir3_find_sysval_regid(v
, SYSTEM_VALUE_WORK_GROUP_ID
);
536 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_CS_CNTL_0
, 2);
538 A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id
) |
539 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
540 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
541 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id
));
542 tu_cs_emit(cs
, 0x2fc); /* HLSQ_CS_UNKNOWN_B998 */
544 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_CS_IBO_COUNT
, 1);
545 tu_cs_emit(cs
, tu_shader_nibo(shader
));
549 tu6_emit_vs_system_values(struct tu_cs
*cs
,
550 const struct ir3_shader_variant
*vs
,
551 const struct ir3_shader_variant
*gs
)
553 const uint32_t vertexid_regid
=
554 ir3_find_sysval_regid(vs
, SYSTEM_VALUE_VERTEX_ID
);
555 const uint32_t instanceid_regid
=
556 ir3_find_sysval_regid(vs
, SYSTEM_VALUE_INSTANCE_ID
);
557 const uint32_t primitiveid_regid
= gs
->type
!= MESA_SHADER_NONE
?
558 ir3_find_sysval_regid(gs
, SYSTEM_VALUE_PRIMITIVE_ID
) :
560 const uint32_t gsheader_regid
= gs
->type
!= MESA_SHADER_NONE
?
561 ir3_find_sysval_regid(gs
, SYSTEM_VALUE_GS_HEADER_IR3
) :
564 tu_cs_emit_pkt4(cs
, REG_A6XX_VFD_CONTROL_1
, 6);
565 tu_cs_emit(cs
, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid
) |
566 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid
) |
567 A6XX_VFD_CONTROL_1_REGID4PRIMID(primitiveid_regid
) |
569 tu_cs_emit(cs
, 0x0000fcfc); /* VFD_CONTROL_2 */
570 tu_cs_emit(cs
, 0xfcfcfcfc); /* VFD_CONTROL_3 */
571 tu_cs_emit(cs
, 0x000000fc); /* VFD_CONTROL_4 */
572 tu_cs_emit(cs
, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gsheader_regid
) |
573 0xfc00); /* VFD_CONTROL_5 */
574 tu_cs_emit(cs
, 0x00000000); /* VFD_CONTROL_6 */
577 /* Add any missing varyings needed for stream-out. Otherwise varyings not
578 * used by fragment shader will be stripped out.
581 tu6_link_streamout(struct ir3_shader_linkage
*l
,
582 const struct ir3_shader_variant
*v
)
584 const struct ir3_stream_output_info
*info
= &v
->shader
->stream_output
;
587 * First, any stream-out varyings not already in linkage map (ie. also
588 * consumed by frag shader) need to be added:
590 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
591 const struct ir3_stream_output
*out
= &info
->output
[i
];
593 (1 << (out
->num_components
+ out
->start_component
)) - 1;
594 unsigned k
= out
->register_index
;
595 unsigned idx
, nextloc
= 0;
597 /* psize/pos need to be the last entries in linkage map, and will
598 * get added link_stream_out, so skip over them:
600 if (v
->outputs
[k
].slot
== VARYING_SLOT_PSIZ
||
601 v
->outputs
[k
].slot
== VARYING_SLOT_POS
)
604 for (idx
= 0; idx
< l
->cnt
; idx
++) {
605 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
607 nextloc
= MAX2(nextloc
, l
->var
[idx
].loc
+ 4);
610 /* add if not already in linkage map: */
612 ir3_link_add(l
, v
->outputs
[k
].regid
, compmask
, nextloc
);
614 /* expand component-mask if needed, ie streaming out all components
615 * but frag shader doesn't consume all components:
617 if (compmask
& ~l
->var
[idx
].compmask
) {
618 l
->var
[idx
].compmask
|= compmask
;
619 l
->max_loc
= MAX2(l
->max_loc
, l
->var
[idx
].loc
+
620 util_last_bit(l
->var
[idx
].compmask
));
626 tu6_setup_streamout(const struct ir3_shader_variant
*v
,
627 struct ir3_shader_linkage
*l
, struct tu_streamout_state
*tf
)
629 const struct ir3_stream_output_info
*info
= &v
->shader
->stream_output
;
631 memset(tf
, 0, sizeof(*tf
));
633 tf
->prog_count
= align(l
->max_loc
, 2) / 2;
635 debug_assert(tf
->prog_count
< ARRAY_SIZE(tf
->prog
));
637 /* set stride info to the streamout state */
638 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++)
639 tf
->stride
[i
] = info
->stride
[i
];
641 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
642 const struct ir3_stream_output
*out
= &info
->output
[i
];
643 unsigned k
= out
->register_index
;
646 tf
->ncomp
[out
->output_buffer
] += out
->num_components
;
648 /* linkage map sorted by order frag shader wants things, so
649 * a bit less ideal here..
651 for (idx
= 0; idx
< l
->cnt
; idx
++)
652 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
655 debug_assert(idx
< l
->cnt
);
657 for (unsigned j
= 0; j
< out
->num_components
; j
++) {
658 unsigned c
= j
+ out
->start_component
;
659 unsigned loc
= l
->var
[idx
].loc
+ c
;
660 unsigned off
= j
+ out
->dst_offset
; /* in dwords */
663 tf
->prog
[loc
/2] |= A6XX_VPC_SO_PROG_B_EN
|
664 A6XX_VPC_SO_PROG_B_BUF(out
->output_buffer
) |
665 A6XX_VPC_SO_PROG_B_OFF(off
* 4);
667 tf
->prog
[loc
/2] |= A6XX_VPC_SO_PROG_A_EN
|
668 A6XX_VPC_SO_PROG_A_BUF(out
->output_buffer
) |
669 A6XX_VPC_SO_PROG_A_OFF(off
* 4);
674 tf
->vpc_so_buf_cntl
= A6XX_VPC_SO_BUF_CNTL_ENABLE
|
675 COND(tf
->ncomp
[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0
) |
676 COND(tf
->ncomp
[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1
) |
677 COND(tf
->ncomp
[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2
) |
678 COND(tf
->ncomp
[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3
);
682 tu6_emit_const(struct tu_cs
*cs
, uint32_t opcode
, uint32_t base
,
683 enum a6xx_state_block block
, uint32_t offset
,
684 uint32_t size
, uint32_t *dwords
) {
685 assert(size
% 4 == 0);
687 tu_cs_emit_pkt7(cs
, opcode
, 3 + size
);
688 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(base
) |
689 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
690 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
691 CP_LOAD_STATE6_0_STATE_BLOCK(block
) |
692 CP_LOAD_STATE6_0_NUM_UNIT(size
/ 4));
694 tu_cs_emit(cs
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
695 tu_cs_emit(cs
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
696 dwords
= (uint32_t *)&((uint8_t *)dwords
)[offset
];
698 tu_cs_emit_array(cs
, dwords
, size
);
702 tu6_emit_link_map(struct tu_cs
*cs
,
703 const struct ir3_shader_variant
*producer
,
704 const struct ir3_shader_variant
*consumer
) {
705 const struct ir3_const_state
*const_state
= &consumer
->shader
->const_state
;
706 uint32_t base
= const_state
->offsets
.primitive_map
;
707 uint32_t patch_locs
[MAX_VARYING
] = { }, num_loc
;
708 num_loc
= ir3_link_geometry_stages(producer
, consumer
, patch_locs
);
709 int size
= DIV_ROUND_UP(num_loc
, 4);
711 size
= (MIN2(size
+ base
, consumer
->constlen
) - base
) * 4;
713 tu6_emit_const(cs
, CP_LOAD_STATE6_GEOM
, base
, SB6_GS_SHADER
, 0, size
,
718 gl_primitive_to_tess(uint16_t primitive
) {
724 case GL_TRIANGLE_STRIP
:
732 tu6_emit_vpc(struct tu_cs
*cs
,
733 const struct ir3_shader_variant
*vs
,
734 const struct ir3_shader_variant
*gs
,
735 const struct ir3_shader_variant
*fs
,
737 struct tu_streamout_state
*tf
)
739 bool has_gs
= gs
->type
!= MESA_SHADER_NONE
;
740 const struct ir3_shader_variant
*last_shader
= has_gs
? gs
: vs
;
741 struct ir3_shader_linkage linkage
= { 0 };
742 ir3_link_shaders(&linkage
, last_shader
, fs
);
744 if (last_shader
->shader
->stream_output
.num_outputs
)
745 tu6_link_streamout(&linkage
, last_shader
);
747 BITSET_DECLARE(vpc_var_enables
, 128) = { 0 };
748 for (uint32_t i
= 0; i
< linkage
.cnt
; i
++) {
749 const uint32_t comp_count
= util_last_bit(linkage
.var
[i
].compmask
);
750 for (uint32_t j
= 0; j
< comp_count
; j
++)
751 BITSET_SET(vpc_var_enables
, linkage
.var
[i
].loc
+ j
);
754 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_VAR_DISABLE(0), 4);
755 tu_cs_emit(cs
, ~vpc_var_enables
[0]);
756 tu_cs_emit(cs
, ~vpc_var_enables
[1]);
757 tu_cs_emit(cs
, ~vpc_var_enables
[2]);
758 tu_cs_emit(cs
, ~vpc_var_enables
[3]);
760 /* a6xx finds position/pointsize at the end */
761 const uint32_t position_regid
=
762 ir3_find_output_regid(last_shader
, VARYING_SLOT_POS
);
763 const uint32_t pointsize_regid
=
764 ir3_find_output_regid(last_shader
, VARYING_SLOT_PSIZ
);
765 const uint32_t layer_regid
= has_gs
?
766 ir3_find_output_regid(gs
, VARYING_SLOT_LAYER
) : regid(63, 0);
768 uint32_t pointsize_loc
= 0xff, position_loc
= 0xff, layer_loc
= 0xff;
769 if (layer_regid
!= regid(63, 0)) {
770 layer_loc
= linkage
.max_loc
;
771 ir3_link_add(&linkage
, layer_regid
, 0x1, linkage
.max_loc
);
773 if (position_regid
!= regid(63, 0)) {
774 position_loc
= linkage
.max_loc
;
775 ir3_link_add(&linkage
, position_regid
, 0xf, linkage
.max_loc
);
777 if (pointsize_regid
!= regid(63, 0)) {
778 pointsize_loc
= linkage
.max_loc
;
779 ir3_link_add(&linkage
, pointsize_regid
, 0x1, linkage
.max_loc
);
782 if (last_shader
->shader
->stream_output
.num_outputs
)
783 tu6_setup_streamout(last_shader
, &linkage
, tf
);
785 /* map outputs of the last shader to VPC */
786 assert(linkage
.cnt
<= 32);
787 const uint32_t sp_out_count
= DIV_ROUND_UP(linkage
.cnt
, 2);
788 const uint32_t sp_vpc_dst_count
= DIV_ROUND_UP(linkage
.cnt
, 4);
790 uint32_t sp_vpc_dst
[8];
791 for (uint32_t i
= 0; i
< linkage
.cnt
; i
++) {
792 ((uint16_t *) sp_out
)[i
] =
793 A6XX_SP_VS_OUT_REG_A_REGID(linkage
.var
[i
].regid
) |
794 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage
.var
[i
].compmask
);
795 ((uint8_t *) sp_vpc_dst
)[i
] =
796 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage
.var
[i
].loc
);
800 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_OUT_REG(0), sp_out_count
);
802 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_VS_OUT_REG(0), sp_out_count
);
803 tu_cs_emit_array(cs
, sp_out
, sp_out_count
);
806 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_VPC_DST_REG(0), sp_vpc_dst_count
);
808 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_VS_VPC_DST_REG(0), sp_vpc_dst_count
);
809 tu_cs_emit_array(cs
, sp_vpc_dst
, sp_vpc_dst_count
);
811 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_CNTL_0
, 1);
812 tu_cs_emit(cs
, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs
->total_in
) |
813 (fs
->total_in
> 0 ? A6XX_VPC_CNTL_0_VARYING
: 0) |
816 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_PACK
, 1);
817 tu_cs_emit(cs
, A6XX_VPC_PACK_POSITIONLOC(position_loc
) |
818 A6XX_VPC_PACK_PSIZELOC(pointsize_loc
) |
819 A6XX_VPC_PACK_STRIDE_IN_VPC(linkage
.max_loc
));
822 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_CTRL_REG0
, 1);
823 tu_cs_emit(cs
, A6XX_SP_GS_CTRL_REG0_THREADSIZE(TWO_QUADS
) |
824 A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(gs
->info
.max_reg
+ 1) |
825 A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(gs
->branchstack
) |
826 COND(gs
->need_pixlod
, A6XX_SP_GS_CTRL_REG0_PIXLODENABLE
));
828 tu6_emit_link_map(cs
, vs
, gs
);
830 uint32_t primitive_regid
=
831 ir3_find_sysval_regid(gs
, SYSTEM_VALUE_PRIMITIVE_ID
);
832 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_PACK_GS
, 1);
833 tu_cs_emit(cs
, A6XX_VPC_PACK_GS_POSITIONLOC(position_loc
) |
834 A6XX_VPC_PACK_GS_PSIZELOC(pointsize_loc
) |
835 A6XX_VPC_PACK_GS_STRIDE_IN_VPC(linkage
.max_loc
));
837 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_UNKNOWN_9105
, 1);
838 tu_cs_emit(cs
, A6XX_VPC_UNKNOWN_9105_LAYERLOC(layer_loc
) | 0xff00);
840 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_UNKNOWN_809C
, 1);
841 tu_cs_emit(cs
, CONDREG(layer_regid
,
842 A6XX_GRAS_UNKNOWN_809C_GS_WRITES_LAYER
));
844 uint32_t flags_regid
= ir3_find_output_regid(gs
,
845 VARYING_SLOT_GS_VERTEX_FLAGS_IR3
);
847 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_PRIMITIVE_CNTL_GS
, 1);
848 tu_cs_emit(cs
, A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT(linkage
.cnt
) |
849 A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID(flags_regid
));
851 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_2
, 1);
852 tu_cs_emit(cs
, A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC(linkage
.max_loc
) |
853 CONDREG(pointsize_regid
, A6XX_PC_PRIMITIVE_CNTL_2_PSIZE
) |
854 CONDREG(layer_regid
, A6XX_PC_PRIMITIVE_CNTL_2_LAYER
) |
855 CONDREG(primitive_regid
, A6XX_PC_PRIMITIVE_CNTL_2_PRIMITIVE_ID
));
857 uint32_t vertices_out
= gs
->shader
->nir
->info
.gs
.vertices_out
- 1;
859 gl_primitive_to_tess(gs
->shader
->nir
->info
.gs
.output_primitive
);
860 uint32_t invocations
= gs
->shader
->nir
->info
.gs
.invocations
- 1;
861 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_5
, 1);
863 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(vertices_out
) |
864 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output
) |
865 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(invocations
));
867 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_3
, 1);
870 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_UNKNOWN_8003
, 1);
873 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_UNKNOWN_9100
, 1);
874 tu_cs_emit(cs
, 0xff);
876 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_UNKNOWN_9102
, 1);
877 tu_cs_emit(cs
, 0xffff00);
879 /* Size of per-primitive alloction in ldlw memory in vec4s. */
881 gs
->shader
->nir
->info
.gs
.vertices_in
*
882 DIV_ROUND_UP(vs
->shader
->output_size
, 4);
883 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_6
, 1);
884 tu_cs_emit(cs
, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size
));
886 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_UNKNOWN_9B07
, 1);
889 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_UNKNOWN_A871
, 1);
890 tu_cs_emit(cs
, vs
->shader
->output_size
);
893 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_PRIMITIVE_CNTL
, 1);
894 tu_cs_emit(cs
, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage
.cnt
));
896 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_1
, 1);
897 tu_cs_emit(cs
, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage
.max_loc
) |
898 (last_shader
->writes_psize
? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE
: 0));
902 tu6_vpc_varying_mode(const struct ir3_shader_variant
*fs
,
904 uint8_t *interp_mode
,
905 uint8_t *ps_repl_mode
)
919 PS_REPL_ONE_MINUS_T
= 3,
922 const uint32_t compmask
= fs
->inputs
[index
].compmask
;
924 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
925 * fourth component occupy three consecutive varying slots
930 if (fs
->inputs
[index
].slot
== VARYING_SLOT_PNTC
) {
931 if (compmask
& 0x1) {
932 *ps_repl_mode
|= PS_REPL_S
<< shift
;
935 if (compmask
& 0x2) {
936 *ps_repl_mode
|= PS_REPL_T
<< shift
;
939 if (compmask
& 0x4) {
940 *interp_mode
|= INTERP_ZERO
<< shift
;
943 if (compmask
& 0x8) {
944 *interp_mode
|= INTERP_ONE
<< 6;
947 } else if ((fs
->inputs
[index
].interpolate
== INTERP_MODE_FLAT
) ||
948 fs
->inputs
[index
].rasterflat
) {
949 for (int i
= 0; i
< 4; i
++) {
950 if (compmask
& (1 << i
)) {
951 *interp_mode
|= INTERP_FLAT
<< shift
;
961 tu6_emit_vpc_varying_modes(struct tu_cs
*cs
,
962 const struct ir3_shader_variant
*fs
,
965 uint32_t interp_modes
[8] = { 0 };
966 uint32_t ps_repl_modes
[8] = { 0 };
970 (i
= ir3_next_varying(fs
, i
)) < (int) fs
->inputs_count
;) {
972 /* get the mode for input i */
974 uint8_t ps_repl_mode
;
976 tu6_vpc_varying_mode(fs
, i
, &interp_mode
, &ps_repl_mode
);
978 /* OR the mode into the array */
979 const uint32_t inloc
= fs
->inputs
[i
].inloc
* 2;
980 uint32_t n
= inloc
/ 32;
981 uint32_t shift
= inloc
% 32;
982 interp_modes
[n
] |= interp_mode
<< shift
;
983 ps_repl_modes
[n
] |= ps_repl_mode
<< shift
;
984 if (shift
+ bits
> 32) {
988 interp_modes
[n
] |= interp_mode
>> shift
;
989 ps_repl_modes
[n
] |= ps_repl_mode
>> shift
;
994 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
995 tu_cs_emit_array(cs
, interp_modes
, 8);
997 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
998 tu_cs_emit_array(cs
, ps_repl_modes
, 8);
1002 tu6_emit_fs_inputs(struct tu_cs
*cs
, const struct ir3_shader_variant
*fs
)
1004 uint32_t face_regid
, coord_regid
, zwcoord_regid
, samp_id_regid
;
1005 uint32_t ij_pix_regid
, ij_samp_regid
, ij_cent_regid
, ij_size_regid
;
1006 uint32_t smask_in_regid
;
1008 bool sample_shading
= fs
->per_samp
; /* TODO | key->sample_shading; */
1009 bool enable_varyings
= fs
->total_in
> 0;
1011 samp_id_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_SAMPLE_ID
);
1012 smask_in_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_SAMPLE_MASK_IN
);
1013 face_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_FRONT_FACE
);
1014 coord_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_FRAG_COORD
);
1015 zwcoord_regid
= VALIDREG(coord_regid
) ? coord_regid
+ 2 : regid(63, 0);
1016 ij_pix_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
);
1017 ij_samp_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE
);
1018 ij_cent_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID
);
1019 ij_size_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE
);
1021 if (fs
->num_sampler_prefetch
> 0) {
1022 assert(VALIDREG(ij_pix_regid
));
1023 /* also, it seems like ij_pix is *required* to be r0.x */
1024 assert(ij_pix_regid
== regid(0, 0));
1027 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_PREFETCH_CNTL
, 1 + fs
->num_sampler_prefetch
);
1028 tu_cs_emit(cs
, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs
->num_sampler_prefetch
) |
1029 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
1031 for (int i
= 0; i
< fs
->num_sampler_prefetch
; i
++) {
1032 const struct ir3_sampler_prefetch
*prefetch
= &fs
->sampler_prefetch
[i
];
1033 tu_cs_emit(cs
, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch
->src
) |
1034 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch
->samp_id
) |
1035 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch
->tex_id
) |
1036 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch
->dst
) |
1037 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch
->wrmask
) |
1038 COND(prefetch
->half_precision
, A6XX_SP_FS_PREFETCH_CMD_HALF
) |
1039 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch
->cmd
));
1042 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_CONTROL_1_REG
, 5);
1043 tu_cs_emit(cs
, 0x7);
1044 tu_cs_emit(cs
, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid
) |
1045 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid
) |
1046 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid
) |
1047 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid
));
1048 tu_cs_emit(cs
, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid
) |
1049 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid
) |
1051 tu_cs_emit(cs
, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid
) |
1052 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid
) |
1053 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid
) |
1055 tu_cs_emit(cs
, 0xfc);
1057 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_UNKNOWN_B980
, 1);
1058 tu_cs_emit(cs
, enable_varyings
? 3 : 1);
1060 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_UPDATE_CNTL
, 1);
1061 tu_cs_emit(cs
, 0xff); /* XXX */
1063 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_CNTL
, 1);
1065 CONDREG(ij_pix_regid
, A6XX_GRAS_CNTL_VARYING
) |
1066 CONDREG(ij_cent_regid
, A6XX_GRAS_CNTL_CENTROID
) |
1067 CONDREG(ij_samp_regid
, A6XX_GRAS_CNTL_PERSAMP_VARYING
) |
1068 COND(VALIDREG(ij_size_regid
) && !sample_shading
, A6XX_GRAS_CNTL_SIZE
) |
1069 COND(VALIDREG(ij_size_regid
) && sample_shading
, A6XX_GRAS_CNTL_SIZE_PERSAMP
) |
1070 COND(fs
->frag_coord
,
1071 A6XX_GRAS_CNTL_SIZE
|
1072 A6XX_GRAS_CNTL_XCOORD
|
1073 A6XX_GRAS_CNTL_YCOORD
|
1074 A6XX_GRAS_CNTL_ZCOORD
|
1075 A6XX_GRAS_CNTL_WCOORD
) |
1076 COND(fs
->frag_face
, A6XX_GRAS_CNTL_SIZE
));
1078 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_RENDER_CONTROL0
, 2);
1080 CONDREG(ij_pix_regid
, A6XX_RB_RENDER_CONTROL0_VARYING
) |
1081 CONDREG(ij_cent_regid
, A6XX_RB_RENDER_CONTROL0_CENTROID
) |
1082 CONDREG(ij_samp_regid
, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING
) |
1083 COND(enable_varyings
, A6XX_RB_RENDER_CONTROL0_UNK10
) |
1084 COND(VALIDREG(ij_size_regid
) && !sample_shading
, A6XX_RB_RENDER_CONTROL0_SIZE
) |
1085 COND(VALIDREG(ij_size_regid
) && sample_shading
, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP
) |
1086 COND(fs
->frag_coord
,
1087 A6XX_RB_RENDER_CONTROL0_SIZE
|
1088 A6XX_RB_RENDER_CONTROL0_XCOORD
|
1089 A6XX_RB_RENDER_CONTROL0_YCOORD
|
1090 A6XX_RB_RENDER_CONTROL0_ZCOORD
|
1091 A6XX_RB_RENDER_CONTROL0_WCOORD
) |
1092 COND(fs
->frag_face
, A6XX_RB_RENDER_CONTROL0_SIZE
));
1094 CONDREG(smask_in_regid
, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK
) |
1095 CONDREG(samp_id_regid
, A6XX_RB_RENDER_CONTROL1_SAMPLEID
) |
1096 CONDREG(ij_size_regid
, A6XX_RB_RENDER_CONTROL1_SIZE
) |
1097 COND(fs
->frag_face
, A6XX_RB_RENDER_CONTROL1_FACENESS
));
1099 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_SAMPLE_CNTL
, 1);
1100 tu_cs_emit(cs
, COND(sample_shading
, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE
));
1102 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_UNKNOWN_8101
, 1);
1103 tu_cs_emit(cs
, COND(sample_shading
, 0x6)); // XXX
1105 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SAMPLE_CNTL
, 1);
1106 tu_cs_emit(cs
, COND(sample_shading
, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE
));
1110 tu6_emit_fs_outputs(struct tu_cs
*cs
,
1111 const struct ir3_shader_variant
*fs
,
1114 uint32_t smask_regid
, posz_regid
;
1116 posz_regid
= ir3_find_output_regid(fs
, FRAG_RESULT_DEPTH
);
1117 smask_regid
= ir3_find_output_regid(fs
, FRAG_RESULT_SAMPLE_MASK
);
1119 uint32_t fragdata_regid
[8];
1120 if (fs
->color0_mrt
) {
1121 fragdata_regid
[0] = ir3_find_output_regid(fs
, FRAG_RESULT_COLOR
);
1122 for (uint32_t i
= 1; i
< ARRAY_SIZE(fragdata_regid
); i
++)
1123 fragdata_regid
[i
] = fragdata_regid
[0];
1125 for (uint32_t i
= 0; i
< ARRAY_SIZE(fragdata_regid
); i
++)
1126 fragdata_regid
[i
] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA0
+ i
);
1129 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_OUTPUT_CNTL0
, 2);
1130 tu_cs_emit(cs
, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid
) |
1131 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid
) |
1133 tu_cs_emit(cs
, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count
));
1135 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
1136 for (uint32_t i
= 0; i
< ARRAY_SIZE(fragdata_regid
); i
++) {
1137 // TODO we could have a mix of half and full precision outputs,
1138 // we really need to figure out half-precision from IR3_REG_HALF
1139 tu_cs_emit(cs
, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid
[i
]) |
1140 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION
: 0));
1143 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_FS_OUTPUT_CNTL0
, 2);
1144 tu_cs_emit(cs
, COND(fs
->writes_pos
, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z
) |
1145 COND(fs
->writes_smask
, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK
));
1146 tu_cs_emit(cs
, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count
));
1148 uint32_t gras_su_depth_plane_cntl
= 0;
1149 uint32_t rb_depth_plane_cntl
= 0;
1150 if (fs
->no_earlyz
|| fs
->writes_pos
) {
1151 gras_su_depth_plane_cntl
|= A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
;
1152 rb_depth_plane_cntl
|= A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
;
1155 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL
, 1);
1156 tu_cs_emit(cs
, gras_su_depth_plane_cntl
);
1158 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_PLANE_CNTL
, 1);
1159 tu_cs_emit(cs
, rb_depth_plane_cntl
);
1163 tu6_emit_shader_object(struct tu_cs
*cs
,
1164 gl_shader_stage stage
,
1165 const struct ir3_shader_variant
*variant
,
1166 const struct tu_bo
*binary_bo
,
1167 uint32_t binary_offset
)
1171 enum a6xx_state_block sb
;
1173 case MESA_SHADER_VERTEX
:
1174 reg
= REG_A6XX_SP_VS_OBJ_START_LO
;
1175 opcode
= CP_LOAD_STATE6_GEOM
;
1178 case MESA_SHADER_TESS_CTRL
:
1179 reg
= REG_A6XX_SP_HS_OBJ_START_LO
;
1180 opcode
= CP_LOAD_STATE6_GEOM
;
1183 case MESA_SHADER_TESS_EVAL
:
1184 reg
= REG_A6XX_SP_DS_OBJ_START_LO
;
1185 opcode
= CP_LOAD_STATE6_GEOM
;
1188 case MESA_SHADER_GEOMETRY
:
1189 reg
= REG_A6XX_SP_GS_OBJ_START_LO
;
1190 opcode
= CP_LOAD_STATE6_GEOM
;
1193 case MESA_SHADER_FRAGMENT
:
1194 reg
= REG_A6XX_SP_FS_OBJ_START_LO
;
1195 opcode
= CP_LOAD_STATE6_FRAG
;
1198 case MESA_SHADER_COMPUTE
:
1199 reg
= REG_A6XX_SP_CS_OBJ_START_LO
;
1200 opcode
= CP_LOAD_STATE6_FRAG
;
1204 unreachable("invalid gl_shader_stage");
1205 opcode
= CP_LOAD_STATE6_GEOM
;
1210 if (!variant
->instrlen
) {
1211 tu_cs_emit_pkt4(cs
, reg
, 2);
1212 tu_cs_emit_qw(cs
, 0);
1216 assert(variant
->type
== stage
);
1218 const uint64_t binary_iova
= binary_bo
->iova
+ binary_offset
;
1219 assert((binary_iova
& 0xf) == 0);
1220 /* note: it looks like HW might try to read a few instructions beyond the instrlen size
1221 * of the shader. this could be a potential source of problems at some point
1222 * possibly this doesn't happen if shader iova is aligned enough (to 4k for example)
1225 tu_cs_emit_pkt4(cs
, reg
, 2);
1226 tu_cs_emit_qw(cs
, binary_iova
);
1228 /* always indirect */
1229 const bool indirect
= true;
1231 tu_cs_emit_pkt7(cs
, opcode
, 3);
1232 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(0) |
1233 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER
) |
1234 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
1235 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
1236 CP_LOAD_STATE6_0_NUM_UNIT(variant
->instrlen
));
1237 tu_cs_emit_qw(cs
, binary_iova
);
1239 const void *binary
= binary_bo
->map
+ binary_offset
;
1241 tu_cs_emit_pkt7(cs
, opcode
, 3 + variant
->info
.sizedwords
);
1242 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(0) |
1243 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER
) |
1244 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
1245 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
1246 CP_LOAD_STATE6_0_NUM_UNIT(variant
->instrlen
));
1247 tu_cs_emit_qw(cs
, 0);
1248 tu_cs_emit_array(cs
, binary
, variant
->info
.sizedwords
);
1253 tu6_emit_immediates(struct tu_cs
*cs
, const struct ir3_shader_variant
*v
,
1254 uint32_t opcode
, enum a6xx_state_block block
)
1260 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
1261 uint32_t base
= const_state
->offsets
.immediate
;
1262 int size
= const_state
->immediates_count
;
1264 /* truncate size to avoid writing constants that shader
1267 size
= MIN2(size
+ base
, v
->constlen
) - base
;
1272 tu_cs_emit_pkt7(cs
, opcode
, 3 + size
* 4);
1273 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(base
) |
1274 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
1275 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
1276 CP_LOAD_STATE6_0_STATE_BLOCK(block
) |
1277 CP_LOAD_STATE6_0_NUM_UNIT(size
));
1278 tu_cs_emit(cs
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
1279 tu_cs_emit(cs
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
1281 for (unsigned i
= 0; i
< size
; i
++) {
1282 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[0]);
1283 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[1]);
1284 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[2]);
1285 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[3]);
1290 tu6_emit_geometry_consts(struct tu_cs
*cs
,
1291 const struct ir3_shader_variant
*vs
,
1292 const struct ir3_shader_variant
*gs
) {
1293 unsigned num_vertices
= gs
->shader
->nir
->info
.gs
.vertices_in
;
1295 uint32_t params
[4] = {
1296 vs
->shader
->output_size
* num_vertices
* 4, /* primitive stride */
1297 vs
->shader
->output_size
* 4, /* vertex stride */
1301 uint32_t vs_base
= vs
->shader
->const_state
.offsets
.primitive_param
;
1302 tu6_emit_const(cs
, CP_LOAD_STATE6_GEOM
, vs_base
, SB6_VS_SHADER
, 0,
1303 ARRAY_SIZE(params
), params
);
1305 uint32_t gs_base
= gs
->shader
->const_state
.offsets
.primitive_param
;
1306 tu6_emit_const(cs
, CP_LOAD_STATE6_GEOM
, gs_base
, SB6_GS_SHADER
, 0,
1307 ARRAY_SIZE(params
), params
);
1311 tu6_emit_program(struct tu_cs
*cs
,
1312 const struct tu_pipeline_builder
*builder
,
1313 const struct tu_bo
*binary_bo
,
1315 struct tu_streamout_state
*tf
)
1317 static const struct ir3_shader_variant dummy_variant
= {
1318 .type
= MESA_SHADER_NONE
1320 assert(builder
->shaders
[MESA_SHADER_VERTEX
]);
1321 const struct ir3_shader_variant
*vs
=
1322 &builder
->shaders
[MESA_SHADER_VERTEX
]->variants
[0];
1323 const struct ir3_shader_variant
*hs
=
1324 builder
->shaders
[MESA_SHADER_TESS_CTRL
]
1325 ? &builder
->shaders
[MESA_SHADER_TESS_CTRL
]->variants
[0]
1327 const struct ir3_shader_variant
*ds
=
1328 builder
->shaders
[MESA_SHADER_TESS_EVAL
]
1329 ? &builder
->shaders
[MESA_SHADER_TESS_EVAL
]->variants
[0]
1331 const struct ir3_shader_variant
*gs
=
1332 builder
->shaders
[MESA_SHADER_GEOMETRY
]
1333 ? &builder
->shaders
[MESA_SHADER_GEOMETRY
]->variants
[0]
1335 const struct ir3_shader_variant
*fs
=
1336 builder
->shaders
[MESA_SHADER_FRAGMENT
]
1337 ? &builder
->shaders
[MESA_SHADER_FRAGMENT
]->variants
[0]
1339 bool has_gs
= gs
->type
!= MESA_SHADER_NONE
;
1342 /* if we have streamout, use full VS in binning pass, as the
1343 * binning pass VS will have outputs on other than position/psize
1346 if (vs
->shader
->stream_output
.num_outputs
== 0)
1347 vs
= &builder
->shaders
[MESA_SHADER_VERTEX
]->variants
[1];
1348 fs
= &dummy_variant
;
1351 tu6_emit_vs_config(cs
, builder
->shaders
[MESA_SHADER_VERTEX
], vs
);
1352 tu6_emit_hs_config(cs
, builder
->shaders
[MESA_SHADER_TESS_CTRL
], hs
);
1353 tu6_emit_ds_config(cs
, builder
->shaders
[MESA_SHADER_TESS_EVAL
], ds
);
1354 tu6_emit_gs_config(cs
, builder
->shaders
[MESA_SHADER_GEOMETRY
], gs
);
1355 tu6_emit_fs_config(cs
, builder
->shaders
[MESA_SHADER_FRAGMENT
], fs
);
1357 tu6_emit_vs_system_values(cs
, vs
, gs
);
1358 tu6_emit_vpc(cs
, vs
, gs
, fs
, binning_pass
, tf
);
1359 tu6_emit_vpc_varying_modes(cs
, fs
, binning_pass
);
1360 tu6_emit_fs_inputs(cs
, fs
);
1361 tu6_emit_fs_outputs(cs
, fs
, builder
->color_attachment_count
);
1363 tu6_emit_shader_object(cs
, MESA_SHADER_VERTEX
, vs
, binary_bo
,
1364 binning_pass
? builder
->binning_vs_offset
: builder
->shader_offsets
[MESA_SHADER_VERTEX
]);
1366 tu6_emit_shader_object(cs
, MESA_SHADER_GEOMETRY
, gs
, binary_bo
,
1367 builder
->shader_offsets
[MESA_SHADER_GEOMETRY
]);
1368 tu6_emit_shader_object(cs
, MESA_SHADER_FRAGMENT
, fs
, binary_bo
,
1369 builder
->shader_offsets
[MESA_SHADER_FRAGMENT
]);
1371 tu6_emit_immediates(cs
, vs
, CP_LOAD_STATE6_GEOM
, SB6_VS_SHADER
);
1373 tu6_emit_immediates(cs
, gs
, CP_LOAD_STATE6_GEOM
, SB6_GS_SHADER
);
1374 tu6_emit_geometry_consts(cs
, vs
, gs
);
1377 tu6_emit_immediates(cs
, fs
, CP_LOAD_STATE6_FRAG
, SB6_FS_SHADER
);
1381 tu6_emit_vertex_input(struct tu_cs
*cs
,
1382 const struct ir3_shader_variant
*vs
,
1383 const VkPipelineVertexInputStateCreateInfo
*vi_info
,
1384 uint8_t bindings
[MAX_VERTEX_ATTRIBS
],
1385 uint16_t strides
[MAX_VERTEX_ATTRIBS
],
1386 uint16_t offsets
[MAX_VERTEX_ATTRIBS
],
1389 uint32_t vfd_decode_idx
= 0;
1391 for (uint32_t i
= 0; i
< vs
->inputs_count
; i
++) {
1392 if (vs
->inputs
[i
].sysval
|| !vs
->inputs
[i
].compmask
)
1395 const VkVertexInputAttributeDescription
*vi_attr
=
1396 tu_find_vertex_input_attribute(vi_info
, vs
->inputs
[i
].slot
);
1397 const VkVertexInputBindingDescription
*vi_binding
=
1398 tu_find_vertex_input_binding(vi_info
, vi_attr
);
1399 assert(vi_attr
&& vi_binding
);
1401 const struct tu_native_format format
= tu6_format_vtx(vi_attr
->format
);
1403 uint32_t vfd_decode
= A6XX_VFD_DECODE_INSTR_IDX(vfd_decode_idx
) |
1404 A6XX_VFD_DECODE_INSTR_FORMAT(format
.fmt
) |
1405 A6XX_VFD_DECODE_INSTR_SWAP(format
.swap
) |
1406 A6XX_VFD_DECODE_INSTR_UNK30
;
1407 if (vi_binding
->inputRate
== VK_VERTEX_INPUT_RATE_INSTANCE
)
1408 vfd_decode
|= A6XX_VFD_DECODE_INSTR_INSTANCED
;
1409 if (!vk_format_is_int(vi_attr
->format
))
1410 vfd_decode
|= A6XX_VFD_DECODE_INSTR_FLOAT
;
1412 const uint32_t vfd_decode_step_rate
= 1;
1414 const uint32_t vfd_dest_cntl
=
1415 A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vs
->inputs
[i
].compmask
) |
1416 A6XX_VFD_DEST_CNTL_INSTR_REGID(vs
->inputs
[i
].regid
);
1418 tu_cs_emit_pkt4(cs
, REG_A6XX_VFD_DECODE(vfd_decode_idx
), 2);
1419 tu_cs_emit(cs
, vfd_decode
);
1420 tu_cs_emit(cs
, vfd_decode_step_rate
);
1422 tu_cs_emit_pkt4(cs
, REG_A6XX_VFD_DEST_CNTL(vfd_decode_idx
), 1);
1423 tu_cs_emit(cs
, vfd_dest_cntl
);
1425 bindings
[vfd_decode_idx
] = vi_binding
->binding
;
1426 strides
[vfd_decode_idx
] = vi_binding
->stride
;
1427 offsets
[vfd_decode_idx
] = vi_attr
->offset
;
1430 assert(vfd_decode_idx
<= MAX_VERTEX_ATTRIBS
);
1433 tu_cs_emit_pkt4(cs
, REG_A6XX_VFD_CONTROL_0
, 1);
1435 cs
, A6XX_VFD_CONTROL_0_VTXCNT(vfd_decode_idx
) | (vfd_decode_idx
<< 8));
1437 *count
= vfd_decode_idx
;
1441 tu6_guardband_adj(uint32_t v
)
1444 return (uint32_t)(511.0 - 65.0 * (log2(v
) - 8.0));
1450 tu6_emit_viewport(struct tu_cs
*cs
, const VkViewport
*viewport
)
1454 scales
[0] = viewport
->width
/ 2.0f
;
1455 scales
[1] = viewport
->height
/ 2.0f
;
1456 scales
[2] = viewport
->maxDepth
- viewport
->minDepth
;
1457 offsets
[0] = viewport
->x
+ scales
[0];
1458 offsets
[1] = viewport
->y
+ scales
[1];
1459 offsets
[2] = viewport
->minDepth
;
1463 min
.x
= (int32_t) viewport
->x
;
1464 max
.x
= (int32_t) ceilf(viewport
->x
+ viewport
->width
);
1465 if (viewport
->height
>= 0.0f
) {
1466 min
.y
= (int32_t) viewport
->y
;
1467 max
.y
= (int32_t) ceilf(viewport
->y
+ viewport
->height
);
1469 min
.y
= (int32_t)(viewport
->y
+ viewport
->height
);
1470 max
.y
= (int32_t) ceilf(viewport
->y
);
1472 /* the spec allows viewport->height to be 0.0f */
1475 assert(min
.x
>= 0 && min
.x
< max
.x
);
1476 assert(min
.y
>= 0 && min
.y
< max
.y
);
1478 VkExtent2D guardband_adj
;
1479 guardband_adj
.width
= tu6_guardband_adj(max
.x
- min
.x
);
1480 guardband_adj
.height
= tu6_guardband_adj(max
.y
- min
.y
);
1482 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0
, 6);
1483 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_XOFFSET_0(offsets
[0]).value
);
1484 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_XSCALE_0(scales
[0]).value
);
1485 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_YOFFSET_0(offsets
[1]).value
);
1486 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_YSCALE_0(scales
[1]).value
);
1487 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_ZOFFSET_0(offsets
[2]).value
);
1488 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_ZSCALE_0(scales
[2]).value
);
1490 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0
, 2);
1491 tu_cs_emit(cs
, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(min
.x
) |
1492 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(min
.y
));
1493 tu_cs_emit(cs
, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(max
.x
- 1) |
1494 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(max
.y
- 1));
1496 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ
, 1);
1498 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj
.width
) |
1499 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj
.height
));
1501 float z_clamp_min
= MIN2(viewport
->minDepth
, viewport
->maxDepth
);
1502 float z_clamp_max
= MAX2(viewport
->minDepth
, viewport
->maxDepth
);
1505 A6XX_GRAS_CL_Z_CLAMP_MIN(z_clamp_min
),
1506 A6XX_GRAS_CL_Z_CLAMP_MAX(z_clamp_max
));
1509 A6XX_RB_Z_CLAMP_MIN(z_clamp_min
),
1510 A6XX_RB_Z_CLAMP_MAX(z_clamp_max
));
1514 tu6_emit_scissor(struct tu_cs
*cs
, const VkRect2D
*scissor
)
1516 const VkOffset2D min
= scissor
->offset
;
1517 const VkOffset2D max
= {
1518 scissor
->offset
.x
+ scissor
->extent
.width
,
1519 scissor
->offset
.y
+ scissor
->extent
.height
,
1522 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0
, 2);
1523 tu_cs_emit(cs
, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(min
.x
) |
1524 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(min
.y
));
1525 tu_cs_emit(cs
, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(max
.x
- 1) |
1526 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(max
.y
- 1));
1530 tu6_emit_gras_unknowns(struct tu_cs
*cs
)
1532 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_UNKNOWN_8001
, 1);
1533 tu_cs_emit(cs
, 0x0);
1537 tu6_emit_point_size(struct tu_cs
*cs
)
1539 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_POINT_MINMAX
, 2);
1540 tu_cs_emit(cs
, A6XX_GRAS_SU_POINT_MINMAX_MIN(1.0f
/ 16.0f
) |
1541 A6XX_GRAS_SU_POINT_MINMAX_MAX(4092.0f
));
1542 tu_cs_emit(cs
, A6XX_GRAS_SU_POINT_SIZE(1.0f
).value
);
1546 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo
*rast_info
,
1547 VkSampleCountFlagBits samples
)
1549 uint32_t gras_su_cntl
= 0;
1551 if (rast_info
->cullMode
& VK_CULL_MODE_FRONT_BIT
)
1552 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_CULL_FRONT
;
1553 if (rast_info
->cullMode
& VK_CULL_MODE_BACK_BIT
)
1554 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_CULL_BACK
;
1556 if (rast_info
->frontFace
== VK_FRONT_FACE_CLOCKWISE
)
1557 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_FRONT_CW
;
1559 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1561 if (rast_info
->depthBiasEnable
)
1562 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_POLY_OFFSET
;
1564 if (samples
> VK_SAMPLE_COUNT_1_BIT
)
1565 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_MSAA_ENABLE
;
1567 return gras_su_cntl
;
1571 tu6_emit_gras_su_cntl(struct tu_cs
*cs
,
1572 uint32_t gras_su_cntl
,
1575 assert((gras_su_cntl
& A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK
) == 0);
1576 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(line_width
/ 2.0f
);
1578 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_CNTL
, 1);
1579 tu_cs_emit(cs
, gras_su_cntl
);
1583 tu6_emit_depth_bias(struct tu_cs
*cs
,
1584 float constant_factor
,
1588 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE
, 3);
1589 tu_cs_emit(cs
, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor
).value
);
1590 tu_cs_emit(cs
, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor
).value
);
1591 tu_cs_emit(cs
, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp
).value
);
1595 tu6_emit_alpha_control_disable(struct tu_cs
*cs
)
1597 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_ALPHA_CONTROL
, 1);
1602 tu6_emit_depth_control(struct tu_cs
*cs
,
1603 const VkPipelineDepthStencilStateCreateInfo
*ds_info
,
1604 const VkPipelineRasterizationStateCreateInfo
*rast_info
)
1606 assert(!ds_info
->depthBoundsTestEnable
);
1608 uint32_t rb_depth_cntl
= 0;
1609 if (ds_info
->depthTestEnable
) {
1611 A6XX_RB_DEPTH_CNTL_Z_ENABLE
|
1612 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info
->depthCompareOp
)) |
1613 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE
;
1615 if (rast_info
->depthClampEnable
)
1616 rb_depth_cntl
|= A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE
;
1618 if (ds_info
->depthWriteEnable
)
1619 rb_depth_cntl
|= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE
;
1622 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_CNTL
, 1);
1623 tu_cs_emit(cs
, rb_depth_cntl
);
1627 tu6_emit_stencil_control(struct tu_cs
*cs
,
1628 const VkPipelineDepthStencilStateCreateInfo
*ds_info
)
1630 uint32_t rb_stencil_control
= 0;
1631 if (ds_info
->stencilTestEnable
) {
1632 const VkStencilOpState
*front
= &ds_info
->front
;
1633 const VkStencilOpState
*back
= &ds_info
->back
;
1634 rb_stencil_control
|=
1635 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE
|
1636 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF
|
1637 A6XX_RB_STENCIL_CONTROL_STENCIL_READ
|
1638 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front
->compareOp
)) |
1639 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front
->failOp
)) |
1640 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front
->passOp
)) |
1641 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front
->depthFailOp
)) |
1642 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back
->compareOp
)) |
1643 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back
->failOp
)) |
1644 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back
->passOp
)) |
1645 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back
->depthFailOp
));
1648 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCIL_CONTROL
, 1);
1649 tu_cs_emit(cs
, rb_stencil_control
);
1653 tu6_emit_stencil_compare_mask(struct tu_cs
*cs
, uint32_t front
, uint32_t back
)
1655 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCILMASK
, 1);
1657 cs
, A6XX_RB_STENCILMASK_MASK(front
) | A6XX_RB_STENCILMASK_BFMASK(back
));
1661 tu6_emit_stencil_write_mask(struct tu_cs
*cs
, uint32_t front
, uint32_t back
)
1663 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCILWRMASK
, 1);
1664 tu_cs_emit(cs
, A6XX_RB_STENCILWRMASK_WRMASK(front
) |
1665 A6XX_RB_STENCILWRMASK_BFWRMASK(back
));
1669 tu6_emit_stencil_reference(struct tu_cs
*cs
, uint32_t front
, uint32_t back
)
1671 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCILREF
, 1);
1673 A6XX_RB_STENCILREF_REF(front
) | A6XX_RB_STENCILREF_BFREF(back
));
1677 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState
*att
,
1680 const enum a3xx_rb_blend_opcode color_op
= tu6_blend_op(att
->colorBlendOp
);
1681 const enum adreno_rb_blend_factor src_color_factor
= tu6_blend_factor(
1682 has_alpha
? att
->srcColorBlendFactor
1683 : tu_blend_factor_no_dst_alpha(att
->srcColorBlendFactor
));
1684 const enum adreno_rb_blend_factor dst_color_factor
= tu6_blend_factor(
1685 has_alpha
? att
->dstColorBlendFactor
1686 : tu_blend_factor_no_dst_alpha(att
->dstColorBlendFactor
));
1687 const enum a3xx_rb_blend_opcode alpha_op
= tu6_blend_op(att
->alphaBlendOp
);
1688 const enum adreno_rb_blend_factor src_alpha_factor
=
1689 tu6_blend_factor(att
->srcAlphaBlendFactor
);
1690 const enum adreno_rb_blend_factor dst_alpha_factor
=
1691 tu6_blend_factor(att
->dstAlphaBlendFactor
);
1693 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor
) |
1694 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op
) |
1695 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor
) |
1696 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor
) |
1697 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op
) |
1698 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor
);
1702 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState
*att
,
1703 uint32_t rb_mrt_control_rop
,
1707 uint32_t rb_mrt_control
=
1708 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att
->colorWriteMask
);
1710 /* ignore blending and logic op for integer attachments */
1712 rb_mrt_control
|= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY
);
1713 return rb_mrt_control
;
1716 rb_mrt_control
|= rb_mrt_control_rop
;
1718 if (att
->blendEnable
) {
1719 rb_mrt_control
|= A6XX_RB_MRT_CONTROL_BLEND
;
1722 rb_mrt_control
|= A6XX_RB_MRT_CONTROL_BLEND2
;
1725 return rb_mrt_control
;
1729 tu6_emit_rb_mrt_controls(struct tu_cs
*cs
,
1730 const VkPipelineColorBlendStateCreateInfo
*blend_info
,
1731 const VkFormat attachment_formats
[MAX_RTS
],
1732 uint32_t *blend_enable_mask
)
1734 *blend_enable_mask
= 0;
1736 bool rop_reads_dst
= false;
1737 uint32_t rb_mrt_control_rop
= 0;
1738 if (blend_info
->logicOpEnable
) {
1739 rop_reads_dst
= tu_logic_op_reads_dst(blend_info
->logicOp
);
1740 rb_mrt_control_rop
=
1741 A6XX_RB_MRT_CONTROL_ROP_ENABLE
|
1742 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info
->logicOp
));
1745 for (uint32_t i
= 0; i
< blend_info
->attachmentCount
; i
++) {
1746 const VkPipelineColorBlendAttachmentState
*att
=
1747 &blend_info
->pAttachments
[i
];
1748 const VkFormat format
= attachment_formats
[i
];
1750 uint32_t rb_mrt_control
= 0;
1751 uint32_t rb_mrt_blend_control
= 0;
1752 if (format
!= VK_FORMAT_UNDEFINED
) {
1753 const bool is_int
= vk_format_is_int(format
);
1754 const bool has_alpha
= vk_format_has_alpha(format
);
1757 tu6_rb_mrt_control(att
, rb_mrt_control_rop
, is_int
, has_alpha
);
1758 rb_mrt_blend_control
= tu6_rb_mrt_blend_control(att
, has_alpha
);
1760 if (att
->blendEnable
|| rop_reads_dst
)
1761 *blend_enable_mask
|= 1 << i
;
1764 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_CONTROL(i
), 2);
1765 tu_cs_emit(cs
, rb_mrt_control
);
1766 tu_cs_emit(cs
, rb_mrt_blend_control
);
1771 tu6_emit_blend_control(struct tu_cs
*cs
,
1772 uint32_t blend_enable_mask
,
1773 const VkPipelineMultisampleStateCreateInfo
*msaa_info
)
1775 assert(!msaa_info
->alphaToOneEnable
);
1777 uint32_t sp_blend_cntl
= A6XX_SP_BLEND_CNTL_UNK8
;
1778 if (blend_enable_mask
)
1779 sp_blend_cntl
|= A6XX_SP_BLEND_CNTL_ENABLED
;
1780 if (msaa_info
->alphaToCoverageEnable
)
1781 sp_blend_cntl
|= A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE
;
1783 const uint32_t sample_mask
=
1784 msaa_info
->pSampleMask
? *msaa_info
->pSampleMask
1785 : ((1 << msaa_info
->rasterizationSamples
) - 1);
1787 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
1788 uint32_t rb_blend_cntl
=
1789 A6XX_RB_BLEND_CNTL_ENABLE_BLEND(blend_enable_mask
) |
1790 A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND
|
1791 A6XX_RB_BLEND_CNTL_SAMPLE_MASK(sample_mask
);
1792 if (msaa_info
->alphaToCoverageEnable
)
1793 rb_blend_cntl
|= A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE
;
1795 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_BLEND_CNTL
, 1);
1796 tu_cs_emit(cs
, sp_blend_cntl
);
1798 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_BLEND_CNTL
, 1);
1799 tu_cs_emit(cs
, rb_blend_cntl
);
1803 tu6_emit_blend_constants(struct tu_cs
*cs
, const float constants
[4])
1805 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_BLEND_RED_F32
, 4);
1806 tu_cs_emit_array(cs
, (const uint32_t *) constants
, 4);
1810 tu_pipeline_create(struct tu_device
*dev
,
1811 const VkAllocationCallbacks
*pAllocator
,
1812 struct tu_pipeline
**out_pipeline
)
1814 struct tu_pipeline
*pipeline
=
1815 vk_zalloc2(&dev
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
1816 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1818 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1820 tu_cs_init(&pipeline
->cs
, dev
, TU_CS_MODE_SUB_STREAM
, 2048);
1822 /* reserve the space now such that tu_cs_begin_sub_stream never fails */
1823 VkResult result
= tu_cs_reserve_space(&pipeline
->cs
, 2048);
1824 if (result
!= VK_SUCCESS
) {
1825 vk_free2(&dev
->alloc
, pAllocator
, pipeline
);
1829 *out_pipeline
= pipeline
;
1835 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder
*builder
)
1837 const VkPipelineShaderStageCreateInfo
*stage_infos
[MESA_SHADER_STAGES
] = {
1840 for (uint32_t i
= 0; i
< builder
->create_info
->stageCount
; i
++) {
1841 gl_shader_stage stage
=
1842 tu_shader_stage(builder
->create_info
->pStages
[i
].stage
);
1843 stage_infos
[stage
] = &builder
->create_info
->pStages
[i
];
1846 struct tu_shader_compile_options options
;
1847 tu_shader_compile_options_init(&options
, builder
->create_info
);
1849 /* compile shaders in reverse order */
1850 struct tu_shader
*next_stage_shader
= NULL
;
1851 for (gl_shader_stage stage
= MESA_SHADER_STAGES
- 1;
1852 stage
> MESA_SHADER_NONE
; stage
--) {
1853 const VkPipelineShaderStageCreateInfo
*stage_info
= stage_infos
[stage
];
1857 struct tu_shader
*shader
=
1858 tu_shader_create(builder
->device
, stage
, stage_info
, builder
->layout
,
1861 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1864 tu_shader_compile(builder
->device
, shader
, next_stage_shader
,
1865 &options
, builder
->alloc
);
1866 if (result
!= VK_SUCCESS
)
1869 builder
->shaders
[stage
] = shader
;
1870 builder
->shader_offsets
[stage
] = builder
->shader_total_size
;
1871 builder
->shader_total_size
+=
1872 sizeof(uint32_t) * shader
->variants
[0].info
.sizedwords
;
1874 next_stage_shader
= shader
;
1877 if (builder
->shaders
[MESA_SHADER_VERTEX
]->has_binning_pass
) {
1878 const struct tu_shader
*vs
= builder
->shaders
[MESA_SHADER_VERTEX
];
1879 const struct ir3_shader_variant
*variant
;
1881 if (vs
->ir3_shader
.stream_output
.num_outputs
)
1882 variant
= &vs
->variants
[0];
1884 variant
= &vs
->variants
[1];
1886 builder
->binning_vs_offset
= builder
->shader_total_size
;
1887 builder
->shader_total_size
+=
1888 sizeof(uint32_t) * variant
->info
.sizedwords
;
1895 tu_pipeline_builder_upload_shaders(struct tu_pipeline_builder
*builder
,
1896 struct tu_pipeline
*pipeline
)
1898 struct tu_bo
*bo
= &pipeline
->program
.binary_bo
;
1901 tu_bo_init_new(builder
->device
, bo
, builder
->shader_total_size
);
1902 if (result
!= VK_SUCCESS
)
1905 result
= tu_bo_map(builder
->device
, bo
);
1906 if (result
!= VK_SUCCESS
)
1909 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
1910 const struct tu_shader
*shader
= builder
->shaders
[i
];
1914 memcpy(bo
->map
+ builder
->shader_offsets
[i
], shader
->binary
,
1915 sizeof(uint32_t) * shader
->variants
[0].info
.sizedwords
);
1918 if (builder
->shaders
[MESA_SHADER_VERTEX
]->has_binning_pass
) {
1919 const struct tu_shader
*vs
= builder
->shaders
[MESA_SHADER_VERTEX
];
1920 const struct ir3_shader_variant
*variant
;
1923 if (vs
->ir3_shader
.stream_output
.num_outputs
) {
1924 variant
= &vs
->variants
[0];
1927 variant
= &vs
->variants
[1];
1928 bin
= vs
->binning_binary
;
1931 memcpy(bo
->map
+ builder
->binning_vs_offset
, bin
,
1932 sizeof(uint32_t) * variant
->info
.sizedwords
);
1939 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder
*builder
,
1940 struct tu_pipeline
*pipeline
)
1942 const VkPipelineDynamicStateCreateInfo
*dynamic_info
=
1943 builder
->create_info
->pDynamicState
;
1948 for (uint32_t i
= 0; i
< dynamic_info
->dynamicStateCount
; i
++) {
1949 pipeline
->dynamic_state
.mask
|=
1950 tu_dynamic_state_bit(dynamic_info
->pDynamicStates
[i
]);
1955 tu_pipeline_set_linkage(struct tu_program_descriptor_linkage
*link
,
1956 struct tu_shader
*shader
,
1957 struct ir3_shader_variant
*v
)
1959 link
->ubo_state
= v
->shader
->ubo_state
;
1960 link
->const_state
= v
->shader
->const_state
;
1961 link
->constlen
= v
->constlen
;
1962 link
->texture_map
= shader
->texture_map
;
1963 link
->sampler_map
= shader
->sampler_map
;
1964 link
->ubo_map
= shader
->ubo_map
;
1965 link
->ssbo_map
= shader
->ssbo_map
;
1966 link
->image_map
= shader
->image_map
;
1970 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder
*builder
,
1971 struct tu_pipeline
*pipeline
)
1973 struct tu_cs prog_cs
;
1974 tu_cs_begin_sub_stream(&pipeline
->cs
, 512, &prog_cs
);
1975 tu6_emit_program(&prog_cs
, builder
, &pipeline
->program
.binary_bo
, false, &pipeline
->streamout
);
1976 pipeline
->program
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &prog_cs
);
1978 tu_cs_begin_sub_stream(&pipeline
->cs
, 512, &prog_cs
);
1979 tu6_emit_program(&prog_cs
, builder
, &pipeline
->program
.binary_bo
, true, &pipeline
->streamout
);
1980 pipeline
->program
.binning_state_ib
=
1981 tu_cs_end_sub_stream(&pipeline
->cs
, &prog_cs
);
1983 VkShaderStageFlags stages
= 0;
1984 for (unsigned i
= 0; i
< builder
->create_info
->stageCount
; i
++) {
1985 stages
|= builder
->create_info
->pStages
[i
].stage
;
1987 pipeline
->active_stages
= stages
;
1989 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
1990 if (!builder
->shaders
[i
])
1993 tu_pipeline_set_linkage(&pipeline
->program
.link
[i
],
1994 builder
->shaders
[i
],
1995 &builder
->shaders
[i
]->variants
[0]);
2000 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder
*builder
,
2001 struct tu_pipeline
*pipeline
)
2003 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
2004 builder
->create_info
->pVertexInputState
;
2005 const struct tu_shader
*vs
= builder
->shaders
[MESA_SHADER_VERTEX
];
2008 tu_cs_begin_sub_stream(&pipeline
->cs
,
2009 MAX_VERTEX_ATTRIBS
* 5 + 2, &vi_cs
);
2010 tu6_emit_vertex_input(&vi_cs
, &vs
->variants
[0], vi_info
,
2011 pipeline
->vi
.bindings
, pipeline
->vi
.strides
,
2012 pipeline
->vi
.offsets
, &pipeline
->vi
.count
);
2013 pipeline
->vi
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &vi_cs
);
2015 if (vs
->has_binning_pass
) {
2016 tu_cs_begin_sub_stream(&pipeline
->cs
,
2017 MAX_VERTEX_ATTRIBS
* 5 + 2, &vi_cs
);
2018 tu6_emit_vertex_input(
2019 &vi_cs
, &vs
->variants
[1], vi_info
, pipeline
->vi
.binning_bindings
,
2020 pipeline
->vi
.binning_strides
, pipeline
->vi
.binning_offsets
,
2021 &pipeline
->vi
.binning_count
);
2022 pipeline
->vi
.binning_state_ib
=
2023 tu_cs_end_sub_stream(&pipeline
->cs
, &vi_cs
);
2028 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder
*builder
,
2029 struct tu_pipeline
*pipeline
)
2031 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
2032 builder
->create_info
->pInputAssemblyState
;
2034 pipeline
->ia
.primtype
= tu6_primtype(ia_info
->topology
);
2035 pipeline
->ia
.primitive_restart
= ia_info
->primitiveRestartEnable
;
2039 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder
*builder
,
2040 struct tu_pipeline
*pipeline
)
2044 * pViewportState is a pointer to an instance of the
2045 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
2046 * pipeline has rasterization disabled."
2048 * We leave the relevant registers stale in that case.
2050 if (builder
->rasterizer_discard
)
2053 const VkPipelineViewportStateCreateInfo
*vp_info
=
2054 builder
->create_info
->pViewportState
;
2057 tu_cs_begin_sub_stream(&pipeline
->cs
, 21, &vp_cs
);
2059 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_VIEWPORT
)) {
2060 assert(vp_info
->viewportCount
== 1);
2061 tu6_emit_viewport(&vp_cs
, vp_info
->pViewports
);
2064 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_SCISSOR
)) {
2065 assert(vp_info
->scissorCount
== 1);
2066 tu6_emit_scissor(&vp_cs
, vp_info
->pScissors
);
2069 pipeline
->vp
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &vp_cs
);
2073 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder
*builder
,
2074 struct tu_pipeline
*pipeline
)
2076 const VkPipelineRasterizationStateCreateInfo
*rast_info
=
2077 builder
->create_info
->pRasterizationState
;
2079 assert(rast_info
->polygonMode
== VK_POLYGON_MODE_FILL
);
2081 struct tu_cs rast_cs
;
2082 tu_cs_begin_sub_stream(&pipeline
->cs
, 20, &rast_cs
);
2085 tu_cs_emit_regs(&rast_cs
,
2087 .znear_clip_disable
= rast_info
->depthClampEnable
,
2088 .zfar_clip_disable
= rast_info
->depthClampEnable
,
2089 .unk5
= rast_info
->depthClampEnable
,
2090 .zero_gb_scale_z
= 1,
2091 .vp_clip_code_ignore
= 1));
2092 /* move to hw ctx init? */
2093 tu6_emit_gras_unknowns(&rast_cs
);
2094 tu6_emit_point_size(&rast_cs
);
2096 const uint32_t gras_su_cntl
=
2097 tu6_gras_su_cntl(rast_info
, builder
->samples
);
2099 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_LINE_WIDTH
))
2100 tu6_emit_gras_su_cntl(&rast_cs
, gras_su_cntl
, rast_info
->lineWidth
);
2102 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_DEPTH_BIAS
)) {
2103 tu6_emit_depth_bias(&rast_cs
, rast_info
->depthBiasConstantFactor
,
2104 rast_info
->depthBiasClamp
,
2105 rast_info
->depthBiasSlopeFactor
);
2108 pipeline
->rast
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &rast_cs
);
2110 pipeline
->rast
.gras_su_cntl
= gras_su_cntl
;
2114 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder
*builder
,
2115 struct tu_pipeline
*pipeline
)
2119 * pDepthStencilState is a pointer to an instance of the
2120 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
2121 * the pipeline has rasterization disabled or if the subpass of the
2122 * render pass the pipeline is created against does not use a
2123 * depth/stencil attachment.
2125 * We disable both depth and stenil tests in those cases.
2127 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info
;
2128 const VkPipelineDepthStencilStateCreateInfo
*ds_info
=
2129 builder
->use_depth_stencil_attachment
2130 ? builder
->create_info
->pDepthStencilState
2134 tu_cs_begin_sub_stream(&pipeline
->cs
, 12, &ds_cs
);
2136 /* move to hw ctx init? */
2137 tu6_emit_alpha_control_disable(&ds_cs
);
2139 tu6_emit_depth_control(&ds_cs
, ds_info
, builder
->create_info
->pRasterizationState
);
2140 tu6_emit_stencil_control(&ds_cs
, ds_info
);
2142 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_COMPARE_MASK
)) {
2143 tu6_emit_stencil_compare_mask(&ds_cs
, ds_info
->front
.compareMask
,
2144 ds_info
->back
.compareMask
);
2146 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_WRITE_MASK
)) {
2147 tu6_emit_stencil_write_mask(&ds_cs
, ds_info
->front
.writeMask
,
2148 ds_info
->back
.writeMask
);
2150 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_REFERENCE
)) {
2151 tu6_emit_stencil_reference(&ds_cs
, ds_info
->front
.reference
,
2152 ds_info
->back
.reference
);
2155 pipeline
->ds
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &ds_cs
);
2159 tu_pipeline_builder_parse_multisample_and_color_blend(
2160 struct tu_pipeline_builder
*builder
, struct tu_pipeline
*pipeline
)
2164 * pMultisampleState is a pointer to an instance of the
2165 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
2166 * has rasterization disabled.
2170 * pColorBlendState is a pointer to an instance of the
2171 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
2172 * pipeline has rasterization disabled or if the subpass of the render
2173 * pass the pipeline is created against does not use any color
2176 * We leave the relevant registers stale when rasterization is disabled.
2178 if (builder
->rasterizer_discard
)
2181 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info
;
2182 const VkPipelineMultisampleStateCreateInfo
*msaa_info
=
2183 builder
->create_info
->pMultisampleState
;
2184 const VkPipelineColorBlendStateCreateInfo
*blend_info
=
2185 builder
->use_color_attachments
? builder
->create_info
->pColorBlendState
2186 : &dummy_blend_info
;
2188 struct tu_cs blend_cs
;
2189 tu_cs_begin_sub_stream(&pipeline
->cs
, MAX_RTS
* 3 + 9, &blend_cs
);
2191 uint32_t blend_enable_mask
;
2192 tu6_emit_rb_mrt_controls(&blend_cs
, blend_info
,
2193 builder
->color_attachment_formats
,
2194 &blend_enable_mask
);
2196 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_BLEND_CONSTANTS
))
2197 tu6_emit_blend_constants(&blend_cs
, blend_info
->blendConstants
);
2199 tu6_emit_blend_control(&blend_cs
, blend_enable_mask
, msaa_info
);
2201 pipeline
->blend
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &blend_cs
);
2205 tu_pipeline_finish(struct tu_pipeline
*pipeline
,
2206 struct tu_device
*dev
,
2207 const VkAllocationCallbacks
*alloc
)
2209 tu_cs_finish(&pipeline
->cs
);
2211 if (pipeline
->program
.binary_bo
.gem_handle
)
2212 tu_bo_finish(dev
, &pipeline
->program
.binary_bo
);
2216 tu_pipeline_builder_build(struct tu_pipeline_builder
*builder
,
2217 struct tu_pipeline
**pipeline
)
2219 VkResult result
= tu_pipeline_create(builder
->device
, builder
->alloc
,
2221 if (result
!= VK_SUCCESS
)
2224 /* compile and upload shaders */
2225 result
= tu_pipeline_builder_compile_shaders(builder
);
2226 if (result
== VK_SUCCESS
)
2227 result
= tu_pipeline_builder_upload_shaders(builder
, *pipeline
);
2228 if (result
!= VK_SUCCESS
) {
2229 tu_pipeline_finish(*pipeline
, builder
->device
, builder
->alloc
);
2230 vk_free2(&builder
->device
->alloc
, builder
->alloc
, *pipeline
);
2231 *pipeline
= VK_NULL_HANDLE
;
2236 tu_pipeline_builder_parse_dynamic(builder
, *pipeline
);
2237 tu_pipeline_builder_parse_shader_stages(builder
, *pipeline
);
2238 tu_pipeline_builder_parse_vertex_input(builder
, *pipeline
);
2239 tu_pipeline_builder_parse_input_assembly(builder
, *pipeline
);
2240 tu_pipeline_builder_parse_viewport(builder
, *pipeline
);
2241 tu_pipeline_builder_parse_rasterization(builder
, *pipeline
);
2242 tu_pipeline_builder_parse_depth_stencil(builder
, *pipeline
);
2243 tu_pipeline_builder_parse_multisample_and_color_blend(builder
, *pipeline
);
2245 /* we should have reserved enough space upfront such that the CS never
2248 assert((*pipeline
)->cs
.bo_count
== 1);
2254 tu_pipeline_builder_finish(struct tu_pipeline_builder
*builder
)
2256 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2257 if (!builder
->shaders
[i
])
2259 tu_shader_destroy(builder
->device
, builder
->shaders
[i
], builder
->alloc
);
2264 tu_pipeline_builder_init_graphics(
2265 struct tu_pipeline_builder
*builder
,
2266 struct tu_device
*dev
,
2267 struct tu_pipeline_cache
*cache
,
2268 const VkGraphicsPipelineCreateInfo
*create_info
,
2269 const VkAllocationCallbacks
*alloc
)
2271 TU_FROM_HANDLE(tu_pipeline_layout
, layout
, create_info
->layout
);
2273 *builder
= (struct tu_pipeline_builder
) {
2276 .create_info
= create_info
,
2281 builder
->rasterizer_discard
=
2282 create_info
->pRasterizationState
->rasterizerDiscardEnable
;
2284 if (builder
->rasterizer_discard
) {
2285 builder
->samples
= VK_SAMPLE_COUNT_1_BIT
;
2287 builder
->samples
= create_info
->pMultisampleState
->rasterizationSamples
;
2289 const struct tu_render_pass
*pass
=
2290 tu_render_pass_from_handle(create_info
->renderPass
);
2291 const struct tu_subpass
*subpass
=
2292 &pass
->subpasses
[create_info
->subpass
];
2294 builder
->use_depth_stencil_attachment
=
2295 subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
;
2297 assert(subpass
->color_count
== 0 ||
2298 !create_info
->pColorBlendState
||
2299 subpass
->color_count
== create_info
->pColorBlendState
->attachmentCount
);
2300 builder
->color_attachment_count
= subpass
->color_count
;
2301 for (uint32_t i
= 0; i
< subpass
->color_count
; i
++) {
2302 const uint32_t a
= subpass
->color_attachments
[i
].attachment
;
2303 if (a
== VK_ATTACHMENT_UNUSED
)
2306 builder
->color_attachment_formats
[i
] = pass
->attachments
[a
].format
;
2307 builder
->use_color_attachments
= true;
2313 tu_graphics_pipeline_create(VkDevice device
,
2314 VkPipelineCache pipelineCache
,
2315 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2316 const VkAllocationCallbacks
*pAllocator
,
2317 VkPipeline
*pPipeline
)
2319 TU_FROM_HANDLE(tu_device
, dev
, device
);
2320 TU_FROM_HANDLE(tu_pipeline_cache
, cache
, pipelineCache
);
2322 struct tu_pipeline_builder builder
;
2323 tu_pipeline_builder_init_graphics(&builder
, dev
, cache
,
2324 pCreateInfo
, pAllocator
);
2326 struct tu_pipeline
*pipeline
= NULL
;
2327 VkResult result
= tu_pipeline_builder_build(&builder
, &pipeline
);
2328 tu_pipeline_builder_finish(&builder
);
2330 if (result
== VK_SUCCESS
)
2331 *pPipeline
= tu_pipeline_to_handle(pipeline
);
2333 *pPipeline
= VK_NULL_HANDLE
;
2339 tu_CreateGraphicsPipelines(VkDevice device
,
2340 VkPipelineCache pipelineCache
,
2342 const VkGraphicsPipelineCreateInfo
*pCreateInfos
,
2343 const VkAllocationCallbacks
*pAllocator
,
2344 VkPipeline
*pPipelines
)
2346 VkResult final_result
= VK_SUCCESS
;
2348 for (uint32_t i
= 0; i
< count
; i
++) {
2349 VkResult result
= tu_graphics_pipeline_create(device
, pipelineCache
,
2350 &pCreateInfos
[i
], pAllocator
,
2353 if (result
!= VK_SUCCESS
)
2354 final_result
= result
;
2357 return final_result
;
2361 tu6_emit_compute_program(struct tu_cs
*cs
,
2362 struct tu_shader
*shader
,
2363 const struct tu_bo
*binary_bo
)
2365 const struct ir3_shader_variant
*v
= &shader
->variants
[0];
2367 tu6_emit_cs_config(cs
, shader
, v
);
2369 /* The compute program is the only one in the pipeline, so 0 offset. */
2370 tu6_emit_shader_object(cs
, MESA_SHADER_COMPUTE
, v
, binary_bo
, 0);
2372 tu6_emit_immediates(cs
, v
, CP_LOAD_STATE6_FRAG
, SB6_CS_SHADER
);
2376 tu_compute_upload_shader(VkDevice device
,
2377 struct tu_pipeline
*pipeline
,
2378 struct tu_shader
*shader
)
2380 TU_FROM_HANDLE(tu_device
, dev
, device
);
2381 struct tu_bo
*bo
= &pipeline
->program
.binary_bo
;
2382 struct ir3_shader_variant
*v
= &shader
->variants
[0];
2384 uint32_t shader_size
= sizeof(uint32_t) * v
->info
.sizedwords
;
2386 tu_bo_init_new(dev
, bo
, shader_size
);
2387 if (result
!= VK_SUCCESS
)
2390 result
= tu_bo_map(dev
, bo
);
2391 if (result
!= VK_SUCCESS
)
2394 memcpy(bo
->map
, shader
->binary
, shader_size
);
2401 tu_compute_pipeline_create(VkDevice device
,
2402 VkPipelineCache _cache
,
2403 const VkComputePipelineCreateInfo
*pCreateInfo
,
2404 const VkAllocationCallbacks
*pAllocator
,
2405 VkPipeline
*pPipeline
)
2407 TU_FROM_HANDLE(tu_device
, dev
, device
);
2408 TU_FROM_HANDLE(tu_pipeline_layout
, layout
, pCreateInfo
->layout
);
2409 const VkPipelineShaderStageCreateInfo
*stage_info
= &pCreateInfo
->stage
;
2412 struct tu_pipeline
*pipeline
;
2414 *pPipeline
= VK_NULL_HANDLE
;
2416 result
= tu_pipeline_create(dev
, pAllocator
, &pipeline
);
2417 if (result
!= VK_SUCCESS
)
2420 pipeline
->layout
= layout
;
2422 struct tu_shader_compile_options options
;
2423 tu_shader_compile_options_init(&options
, NULL
);
2425 struct tu_shader
*shader
=
2426 tu_shader_create(dev
, MESA_SHADER_COMPUTE
, stage_info
, layout
, pAllocator
);
2428 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2432 result
= tu_shader_compile(dev
, shader
, NULL
, &options
, pAllocator
);
2433 if (result
!= VK_SUCCESS
)
2436 struct ir3_shader_variant
*v
= &shader
->variants
[0];
2438 tu_pipeline_set_linkage(&pipeline
->program
.link
[MESA_SHADER_COMPUTE
],
2441 result
= tu_compute_upload_shader(device
, pipeline
, shader
);
2442 if (result
!= VK_SUCCESS
)
2445 for (int i
= 0; i
< 3; i
++)
2446 pipeline
->compute
.local_size
[i
] = v
->shader
->nir
->info
.cs
.local_size
[i
];
2448 struct tu_cs prog_cs
;
2449 tu_cs_begin_sub_stream(&pipeline
->cs
, 512, &prog_cs
);
2450 tu6_emit_compute_program(&prog_cs
, shader
, &pipeline
->program
.binary_bo
);
2451 pipeline
->program
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &prog_cs
);
2453 *pPipeline
= tu_pipeline_to_handle(pipeline
);
2458 tu_shader_destroy(dev
, shader
, pAllocator
);
2460 tu_pipeline_finish(pipeline
, dev
, pAllocator
);
2461 vk_free2(&dev
->alloc
, pAllocator
, pipeline
);
2467 tu_CreateComputePipelines(VkDevice device
,
2468 VkPipelineCache pipelineCache
,
2470 const VkComputePipelineCreateInfo
*pCreateInfos
,
2471 const VkAllocationCallbacks
*pAllocator
,
2472 VkPipeline
*pPipelines
)
2474 VkResult final_result
= VK_SUCCESS
;
2476 for (uint32_t i
= 0; i
< count
; i
++) {
2477 VkResult result
= tu_compute_pipeline_create(device
, pipelineCache
,
2479 pAllocator
, &pPipelines
[i
]);
2480 if (result
!= VK_SUCCESS
)
2481 final_result
= result
;
2484 return final_result
;
2488 tu_DestroyPipeline(VkDevice _device
,
2489 VkPipeline _pipeline
,
2490 const VkAllocationCallbacks
*pAllocator
)
2492 TU_FROM_HANDLE(tu_device
, dev
, _device
);
2493 TU_FROM_HANDLE(tu_pipeline
, pipeline
, _pipeline
);
2498 tu_pipeline_finish(pipeline
, dev
, pAllocator
);
2499 vk_free2(&dev
->alloc
, pAllocator
, pipeline
);