src/freedreno/vulkan/tu_pipeline.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  */
  27
  28 #include "tu_private.h"
  29
  30 #include "main/menums.h"
  31 #include "nir/nir.h"
  32 #include "nir/nir_builder.h"
  33 #include "spirv/nir_spirv.h"
  34 #include "util/debug.h"
  35 #include "util/mesa-sha1.h"
  36 #include "util/u_atomic.h"
  37 #include "vk_format.h"
  38 #include "vk_util.h"
  39
  40 #include "tu_cs.h"
  41
  42 struct tu_pipeline_builder
  43 {
  44    struct tu_device *device;
  45    struct tu_pipeline_cache *cache;
  46    struct tu_pipeline_layout *layout;
  47    const VkAllocationCallbacks *alloc;
  48    const VkGraphicsPipelineCreateInfo *create_info;
  49
  50    struct tu_shader *shaders[MESA_SHADER_STAGES];
  51    uint32_t shader_offsets[MESA_SHADER_STAGES];
  52    uint32_t binning_vs_offset;
  53    uint32_t shader_total_size;
  54
  55    bool rasterizer_discard;
  56    /* these states are affectd by rasterizer_discard */
  57    VkSampleCountFlagBits samples;
  58    bool use_depth_stencil_attachment;
  59    bool use_color_attachments;
  60    uint32_t color_attachment_count;
  61    VkFormat color_attachment_formats[MAX_RTS];
  62 };
  63
  64 static enum tu_dynamic_state_bits
  65 tu_dynamic_state_bit(VkDynamicState state)
  66 {
  67    switch (state) {
  68    case VK_DYNAMIC_STATE_VIEWPORT:
  69       return TU_DYNAMIC_VIEWPORT;
  70    case VK_DYNAMIC_STATE_SCISSOR:
  71       return TU_DYNAMIC_SCISSOR;
  72    case VK_DYNAMIC_STATE_LINE_WIDTH:
  73       return TU_DYNAMIC_LINE_WIDTH;
  74    case VK_DYNAMIC_STATE_DEPTH_BIAS:
  75       return TU_DYNAMIC_DEPTH_BIAS;
  76    case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
  77       return TU_DYNAMIC_BLEND_CONSTANTS;
  78    case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
  79       return TU_DYNAMIC_DEPTH_BOUNDS;
  80    case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
  81       return TU_DYNAMIC_STENCIL_COMPARE_MASK;
  82    case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
  83       return TU_DYNAMIC_STENCIL_WRITE_MASK;
  84    case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
  85       return TU_DYNAMIC_STENCIL_REFERENCE;
  86    default:
  87       unreachable("invalid dynamic state");
  88       return 0;
  89    }
  90 }
  91
  92 static gl_shader_stage
  93 tu_shader_stage(VkShaderStageFlagBits stage)
  94 {
  95    switch (stage) {
  96    case VK_SHADER_STAGE_VERTEX_BIT:
  97       return MESA_SHADER_VERTEX;
  98    case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
  99       return MESA_SHADER_TESS_CTRL;
 100    case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
 101       return MESA_SHADER_TESS_EVAL;
 102    case VK_SHADER_STAGE_GEOMETRY_BIT:
 103       return MESA_SHADER_GEOMETRY;
 104    case VK_SHADER_STAGE_FRAGMENT_BIT:
 105       return MESA_SHADER_FRAGMENT;
 106    case VK_SHADER_STAGE_COMPUTE_BIT:
 107       return MESA_SHADER_COMPUTE;
 108    default:
 109       unreachable("invalid VkShaderStageFlagBits");
 110       return MESA_SHADER_NONE;
 111    }
 112 }
 113
 114 static const VkVertexInputAttributeDescription *
 115 tu_find_vertex_input_attribute(
 116    const VkPipelineVertexInputStateCreateInfo *vi_info, uint32_t slot)
 117 {
 118    assert(slot >= VERT_ATTRIB_GENERIC0);
 119    slot -= VERT_ATTRIB_GENERIC0;
 120    for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
 121       if (vi_info->pVertexAttributeDescriptions[i].location == slot)
 122          return &vi_info->pVertexAttributeDescriptions[i];
 123    }
 124    return NULL;
 125 }
 126
 127 static const VkVertexInputBindingDescription *
 128 tu_find_vertex_input_binding(
 129    const VkPipelineVertexInputStateCreateInfo *vi_info,
 130    const VkVertexInputAttributeDescription *vi_attr)
 131 {
 132    assert(vi_attr);
 133    for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
 134       if (vi_info->pVertexBindingDescriptions[i].binding == vi_attr->binding)
 135          return &vi_info->pVertexBindingDescriptions[i];
 136    }
 137    return NULL;
 138 }
 139
 140 static bool
 141 tu_logic_op_reads_dst(VkLogicOp op)
 142 {
 143    switch (op) {
 144    case VK_LOGIC_OP_CLEAR:
 145    case VK_LOGIC_OP_COPY:
 146    case VK_LOGIC_OP_COPY_INVERTED:
 147    case VK_LOGIC_OP_SET:
 148       return false;
 149    default:
 150       return true;
 151    }
 152 }
 153
 154 static VkBlendFactor
 155 tu_blend_factor_no_dst_alpha(VkBlendFactor factor)
 156 {
 157    /* treat dst alpha as 1.0 and avoid reading it */
 158    switch (factor) {
 159    case VK_BLEND_FACTOR_DST_ALPHA:
 160       return VK_BLEND_FACTOR_ONE;
 161    case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
 162       return VK_BLEND_FACTOR_ZERO;
 163    default:
 164       return factor;
 165    }
 166 }
 167
 168 static enum pc_di_primtype
 169 tu6_primtype(VkPrimitiveTopology topology)
 170 {
 171    switch (topology) {
 172    case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
 173       return DI_PT_POINTLIST;
 174    case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
 175       return DI_PT_LINELIST;
 176    case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
 177       return DI_PT_LINESTRIP;
 178    case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
 179       return DI_PT_TRILIST;
 180    case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
 181       return DI_PT_TRISTRIP;
 182    case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
 183       return DI_PT_TRIFAN;
 184    case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
 185       return DI_PT_LINE_ADJ;
 186    case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
 187       return DI_PT_LINESTRIP_ADJ;
 188    case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
 189       return DI_PT_TRI_ADJ;
 190    case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
 191       return DI_PT_TRISTRIP_ADJ;
 192    case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
 193    default:
 194       unreachable("invalid primitive topology");
 195       return DI_PT_NONE;
 196    }
 197 }
 198
 199 static enum adreno_compare_func
 200 tu6_compare_func(VkCompareOp op)
 201 {
 202    switch (op) {
 203    case VK_COMPARE_OP_NEVER:
 204       return FUNC_NEVER;
 205    case VK_COMPARE_OP_LESS:
 206       return FUNC_LESS;
 207    case VK_COMPARE_OP_EQUAL:
 208       return FUNC_EQUAL;
 209    case VK_COMPARE_OP_LESS_OR_EQUAL:
 210       return FUNC_LEQUAL;
 211    case VK_COMPARE_OP_GREATER:
 212       return FUNC_GREATER;
 213    case VK_COMPARE_OP_NOT_EQUAL:
 214       return FUNC_NOTEQUAL;
 215    case VK_COMPARE_OP_GREATER_OR_EQUAL:
 216       return FUNC_GEQUAL;
 217    case VK_COMPARE_OP_ALWAYS:
 218       return FUNC_ALWAYS;
 219    default:
 220       unreachable("invalid VkCompareOp");
 221       return FUNC_NEVER;
 222    }
 223 }
 224
 225 static enum adreno_stencil_op
 226 tu6_stencil_op(VkStencilOp op)
 227 {
 228    switch (op) {
 229    case VK_STENCIL_OP_KEEP:
 230       return STENCIL_KEEP;
 231    case VK_STENCIL_OP_ZERO:
 232       return STENCIL_ZERO;
 233    case VK_STENCIL_OP_REPLACE:
 234       return STENCIL_REPLACE;
 235    case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
 236       return STENCIL_INCR_CLAMP;
 237    case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
 238       return STENCIL_DECR_CLAMP;
 239    case VK_STENCIL_OP_INVERT:
 240       return STENCIL_INVERT;
 241    case VK_STENCIL_OP_INCREMENT_AND_WRAP:
 242       return STENCIL_INCR_WRAP;
 243    case VK_STENCIL_OP_DECREMENT_AND_WRAP:
 244       return STENCIL_DECR_WRAP;
 245    default:
 246       unreachable("invalid VkStencilOp");
 247       return STENCIL_KEEP;
 248    }
 249 }
 250
 251 static enum a3xx_rop_code
 252 tu6_rop(VkLogicOp op)
 253 {
 254    switch (op) {
 255    case VK_LOGIC_OP_CLEAR:
 256       return ROP_CLEAR;
 257    case VK_LOGIC_OP_AND:
 258       return ROP_AND;
 259    case VK_LOGIC_OP_AND_REVERSE:
 260       return ROP_AND_REVERSE;
 261    case VK_LOGIC_OP_COPY:
 262       return ROP_COPY;
 263    case VK_LOGIC_OP_AND_INVERTED:
 264       return ROP_AND_INVERTED;
 265    case VK_LOGIC_OP_NO_OP:
 266       return ROP_NOOP;
 267    case VK_LOGIC_OP_XOR:
 268       return ROP_XOR;
 269    case VK_LOGIC_OP_OR:
 270       return ROP_OR;
 271    case VK_LOGIC_OP_NOR:
 272       return ROP_NOR;
 273    case VK_LOGIC_OP_EQUIVALENT:
 274       return ROP_EQUIV;
 275    case VK_LOGIC_OP_INVERT:
 276       return ROP_INVERT;
 277    case VK_LOGIC_OP_OR_REVERSE:
 278       return ROP_OR_REVERSE;
 279    case VK_LOGIC_OP_COPY_INVERTED:
 280       return ROP_COPY_INVERTED;
 281    case VK_LOGIC_OP_OR_INVERTED:
 282       return ROP_OR_INVERTED;
 283    case VK_LOGIC_OP_NAND:
 284       return ROP_NAND;
 285    case VK_LOGIC_OP_SET:
 286       return ROP_SET;
 287    default:
 288       unreachable("invalid VkLogicOp");
 289       return ROP_NOOP;
 290    }
 291 }
 292
 293 static enum adreno_rb_blend_factor
 294 tu6_blend_factor(VkBlendFactor factor)
 295 {
 296    switch (factor) {
 297    case VK_BLEND_FACTOR_ZERO:
 298       return FACTOR_ZERO;
 299    case VK_BLEND_FACTOR_ONE:
 300       return FACTOR_ONE;
 301    case VK_BLEND_FACTOR_SRC_COLOR:
 302       return FACTOR_SRC_COLOR;
 303    case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
 304       return FACTOR_ONE_MINUS_SRC_COLOR;
 305    case VK_BLEND_FACTOR_DST_COLOR:
 306       return FACTOR_DST_COLOR;
 307    case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
 308       return FACTOR_ONE_MINUS_DST_COLOR;
 309    case VK_BLEND_FACTOR_SRC_ALPHA:
 310       return FACTOR_SRC_ALPHA;
 311    case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
 312       return FACTOR_ONE_MINUS_SRC_ALPHA;
 313    case VK_BLEND_FACTOR_DST_ALPHA:
 314       return FACTOR_DST_ALPHA;
 315    case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
 316       return FACTOR_ONE_MINUS_DST_ALPHA;
 317    case VK_BLEND_FACTOR_CONSTANT_COLOR:
 318       return FACTOR_CONSTANT_COLOR;
 319    case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
 320       return FACTOR_ONE_MINUS_CONSTANT_COLOR;
 321    case VK_BLEND_FACTOR_CONSTANT_ALPHA:
 322       return FACTOR_CONSTANT_ALPHA;
 323    case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
 324       return FACTOR_ONE_MINUS_CONSTANT_ALPHA;
 325    case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
 326       return FACTOR_SRC_ALPHA_SATURATE;
 327    case VK_BLEND_FACTOR_SRC1_COLOR:
 328       return FACTOR_SRC1_COLOR;
 329    case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
 330       return FACTOR_ONE_MINUS_SRC1_COLOR;
 331    case VK_BLEND_FACTOR_SRC1_ALPHA:
 332       return FACTOR_SRC1_ALPHA;
 333    case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
 334       return FACTOR_ONE_MINUS_SRC1_ALPHA;
 335    default:
 336       unreachable("invalid VkBlendFactor");
 337       return FACTOR_ZERO;
 338    }
 339 }
 340
 341 static enum a3xx_rb_blend_opcode
 342 tu6_blend_op(VkBlendOp op)
 343 {
 344    switch (op) {
 345    case VK_BLEND_OP_ADD:
 346       return BLEND_DST_PLUS_SRC;
 347    case VK_BLEND_OP_SUBTRACT:
 348       return BLEND_SRC_MINUS_DST;
 349    case VK_BLEND_OP_REVERSE_SUBTRACT:
 350       return BLEND_DST_MINUS_SRC;
 351    case VK_BLEND_OP_MIN:
 352       return BLEND_MIN_DST_SRC;
 353    case VK_BLEND_OP_MAX:
 354       return BLEND_MAX_DST_SRC;
 355    default:
 356       unreachable("invalid VkBlendOp");
 357       return BLEND_DST_PLUS_SRC;
 358    }
 359 }
 360
 361 static unsigned
 362 tu_shader_nibo(const struct tu_shader *shader)
 363 {
 364    /* Don't use ir3_shader_nibo(), because that would include declared but
 365     * unused storage images and SSBOs.
 366     */
 367    return shader->ssbo_map.num_desc + shader->image_map.num_desc;
 368 }
 369
 370 static void
 371 tu6_emit_vs_config(struct tu_cs *cs, struct tu_shader *shader,
 372                    const struct ir3_shader_variant *vs)
 373 {
 374    uint32_t sp_vs_ctrl =
 375       A6XX_SP_VS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
 376       A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs->info.max_reg + 1) |
 377       A6XX_SP_VS_CTRL_REG0_MERGEDREGS |
 378       A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs->branchstack);
 379    if (vs->need_pixlod)
 380       sp_vs_ctrl |= A6XX_SP_VS_CTRL_REG0_PIXLODENABLE;
 381
 382    uint32_t sp_vs_config = A6XX_SP_VS_CONFIG_NTEX(shader->texture_map.num_desc) |
 383                            A6XX_SP_VS_CONFIG_NSAMP(shader->sampler_map.num_desc);
 384    if (vs->instrlen)
 385       sp_vs_config |= A6XX_SP_VS_CONFIG_ENABLED;
 386
 387    tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_CTRL_REG0, 1);
 388    tu_cs_emit(cs, sp_vs_ctrl);
 389
 390    tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_CONFIG, 2);
 391    tu_cs_emit(cs, sp_vs_config);
 392    tu_cs_emit(cs, vs->instrlen);
 393
 394    tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_VS_CNTL, 1);
 395    tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(vs->constlen, 4)) |
 396                   A6XX_HLSQ_VS_CNTL_ENABLED);
 397 }
 398
 399 static void
 400 tu6_emit_hs_config(struct tu_cs *cs, struct tu_shader *shader,
 401                    const struct ir3_shader_variant *hs)
 402 {
 403    uint32_t sp_hs_config = 0;
 404    if (hs->instrlen)
 405       sp_hs_config |= A6XX_SP_HS_CONFIG_ENABLED;
 406
 407    tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
 408    tu_cs_emit(cs, 0);
 409
 410    tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_CONFIG, 2);
 411    tu_cs_emit(cs, sp_hs_config);
 412    tu_cs_emit(cs, hs->instrlen);
 413
 414    tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_HS_CNTL, 1);
 415    tu_cs_emit(cs, A6XX_HLSQ_HS_CNTL_CONSTLEN(align(hs->constlen, 4)));
 416 }
 417
 418 static void
 419 tu6_emit_ds_config(struct tu_cs *cs, struct tu_shader *shader,
 420                    const struct ir3_shader_variant *ds)
 421 {
 422    uint32_t sp_ds_config = 0;
 423    if (ds->instrlen)
 424       sp_ds_config |= A6XX_SP_DS_CONFIG_ENABLED;
 425
 426    tu_cs_emit_pkt4(cs, REG_A6XX_SP_DS_CONFIG, 2);
 427    tu_cs_emit(cs, sp_ds_config);
 428    tu_cs_emit(cs, ds->instrlen);
 429
 430    tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_DS_CNTL, 1);
 431    tu_cs_emit(cs, A6XX_HLSQ_DS_CNTL_CONSTLEN(align(ds->constlen, 4)));
 432 }
 433
 434 static void
 435 tu6_emit_gs_config(struct tu_cs *cs, struct tu_shader *shader,
 436                    const struct ir3_shader_variant *gs)
 437 {
 438    uint32_t sp_gs_config = 0;
 439    if (gs->instrlen)
 440       sp_gs_config |= A6XX_SP_GS_CONFIG_ENABLED;
 441
 442    tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
 443    tu_cs_emit(cs, 0);
 444
 445    tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CONFIG, 2);
 446    tu_cs_emit(cs, sp_gs_config);
 447    tu_cs_emit(cs, gs->instrlen);
 448
 449    tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_GS_CNTL, 1);
 450    tu_cs_emit(cs, A6XX_HLSQ_GS_CNTL_CONSTLEN(align(gs->constlen, 4)));
 451 }
 452
 453 static void
 454 tu6_emit_fs_config(struct tu_cs *cs, struct tu_shader *shader,
 455                    const struct ir3_shader_variant *fs)
 456 {
 457    uint32_t sp_fs_ctrl =
 458       A6XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) | 0x1000000 |
 459       A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs->info.max_reg + 1) |
 460       A6XX_SP_FS_CTRL_REG0_MERGEDREGS |
 461       A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs->branchstack);
 462    if (fs->total_in > 0)
 463       sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_VARYING;
 464    if (fs->need_pixlod)
 465       sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_PIXLODENABLE;
 466
 467    uint32_t sp_fs_config = A6XX_SP_FS_CONFIG_NTEX(shader->texture_map.num_desc) |
 468                            A6XX_SP_FS_CONFIG_NSAMP(shader->sampler_map.num_desc) |
 469                            A6XX_SP_FS_CONFIG_NIBO(tu_shader_nibo(shader));
 470    if (fs->instrlen)
 471       sp_fs_config |= A6XX_SP_FS_CONFIG_ENABLED;
 472
 473    tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_A9A8, 1);
 474    tu_cs_emit(cs, 0);
 475
 476    tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_AB00, 1);
 477    tu_cs_emit(cs, 0x5);
 478
 479    tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_CTRL_REG0, 1);
 480    tu_cs_emit(cs, sp_fs_ctrl);
 481
 482    tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_CONFIG, 2);
 483    tu_cs_emit(cs, sp_fs_config);
 484    tu_cs_emit(cs, fs->instrlen);
 485
 486    tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_FS_CNTL, 1);
 487    tu_cs_emit(cs, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(fs->constlen, 4)) |
 488                   A6XX_HLSQ_FS_CNTL_ENABLED);
 489
 490    tu_cs_emit_pkt4(cs, REG_A6XX_SP_IBO_COUNT, 1);
 491    tu_cs_emit(cs, tu_shader_nibo(shader));
 492 }
 493
 494 static void
 495 tu6_emit_cs_config(struct tu_cs *cs, const struct tu_shader *shader,
 496                    const struct ir3_shader_variant *v)
 497 {
 498    tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
 499    tu_cs_emit(cs, 0xff);
 500
 501    unsigned constlen = align(v->constlen, 4);
 502    tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL, 1);
 503    tu_cs_emit(cs, A6XX_HLSQ_CS_CNTL_CONSTLEN(constlen) |
 504               A6XX_HLSQ_CS_CNTL_ENABLED);
 505
 506    tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_CONFIG, 2);
 507    tu_cs_emit(cs, A6XX_SP_CS_CONFIG_ENABLED |
 508               A6XX_SP_CS_CONFIG_NIBO(tu_shader_nibo(shader)) |
 509               A6XX_SP_CS_CONFIG_NTEX(shader->texture_map.num_desc) |
 510               A6XX_SP_CS_CONFIG_NSAMP(shader->sampler_map.num_desc));
 511    tu_cs_emit(cs, v->instrlen);
 512
 513    tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_CTRL_REG0, 1);
 514    tu_cs_emit(cs, A6XX_SP_CS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
 515               A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(v->info.max_reg + 1) |
 516               A6XX_SP_CS_CTRL_REG0_MERGEDREGS |
 517               A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(v->branchstack) |
 518               COND(v->need_pixlod, A6XX_SP_CS_CTRL_REG0_PIXLODENABLE));
 519
 520    tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_UNKNOWN_A9B1, 1);
 521    tu_cs_emit(cs, 0x41);
 522
 523    uint32_t local_invocation_id =
 524       ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
 525    uint32_t work_group_id =
 526       ir3_find_sysval_regid(v, SYSTEM_VALUE_WORK_GROUP_ID);
 527
 528    tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL_0, 2);
 529    tu_cs_emit(cs,
 530               A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) |
 531               A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
 532               A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
 533               A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
 534    tu_cs_emit(cs, 0x2fc);             /* HLSQ_CS_UNKNOWN_B998 */
 535
 536    tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_IBO_COUNT, 1);
 537    tu_cs_emit(cs, tu_shader_nibo(shader));
 538 }
 539
 540 static void
 541 tu6_emit_vs_system_values(struct tu_cs *cs,
 542                           const struct ir3_shader_variant *vs)
 543 {
 544    const uint32_t vertexid_regid =
 545       ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
 546    const uint32_t instanceid_regid =
 547       ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
 548
 549    tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_1, 6);
 550    tu_cs_emit(cs, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid) |
 551                      A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid) |
 552                      0xfcfc0000);
 553    tu_cs_emit(cs, 0x0000fcfc); /* VFD_CONTROL_2 */
 554    tu_cs_emit(cs, 0xfcfcfcfc); /* VFD_CONTROL_3 */
 555    tu_cs_emit(cs, 0x000000fc); /* VFD_CONTROL_4 */
 556    tu_cs_emit(cs, 0x0000fcfc); /* VFD_CONTROL_5 */
 557    tu_cs_emit(cs, 0x00000000); /* VFD_CONTROL_6 */
 558 }
 559
 560 static void
 561 tu6_emit_vpc(struct tu_cs *cs,
 562              const struct ir3_shader_variant *vs,
 563              const struct ir3_shader_variant *fs,
 564              bool binning_pass)
 565 {
 566    struct ir3_shader_linkage linkage = { 0 };
 567    ir3_link_shaders(&linkage, vs, fs);
 568
 569    if (vs->shader->stream_output.num_outputs && !binning_pass)
 570       tu_finishme("stream output");
 571
 572    BITSET_DECLARE(vpc_var_enables, 128) = { 0 };
 573    for (uint32_t i = 0; i < linkage.cnt; i++) {
 574       const uint32_t comp_count = util_last_bit(linkage.var[i].compmask);
 575       for (uint32_t j = 0; j < comp_count; j++)
 576          BITSET_SET(vpc_var_enables, linkage.var[i].loc + j);
 577    }
 578
 579    tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VAR_DISABLE(0), 4);
 580    tu_cs_emit(cs, ~vpc_var_enables[0]);
 581    tu_cs_emit(cs, ~vpc_var_enables[1]);
 582    tu_cs_emit(cs, ~vpc_var_enables[2]);
 583    tu_cs_emit(cs, ~vpc_var_enables[3]);
 584
 585    /* a6xx finds position/pointsize at the end */
 586    const uint32_t position_regid =
 587       ir3_find_output_regid(vs, VARYING_SLOT_POS);
 588    const uint32_t pointsize_regid =
 589       ir3_find_output_regid(vs, VARYING_SLOT_PSIZ);
 590    uint32_t pointsize_loc = 0xff, position_loc = 0xff;
 591    if (position_regid != regid(63, 0)) {
 592       position_loc = linkage.max_loc;
 593       ir3_link_add(&linkage, position_regid, 0xf, linkage.max_loc);
 594    }
 595    if (pointsize_regid != regid(63, 0)) {
 596       pointsize_loc = linkage.max_loc;
 597       ir3_link_add(&linkage, pointsize_regid, 0x1, linkage.max_loc);
 598    }
 599
 600    /* map vs outputs to VPC */
 601    assert(linkage.cnt <= 32);
 602    const uint32_t sp_vs_out_count = (linkage.cnt + 1) / 2;
 603    const uint32_t sp_vs_vpc_dst_count = (linkage.cnt + 3) / 4;
 604    uint32_t sp_vs_out[16];
 605    uint32_t sp_vs_vpc_dst[8];
 606    sp_vs_out[sp_vs_out_count - 1] = 0;
 607    sp_vs_vpc_dst[sp_vs_vpc_dst_count - 1] = 0;
 608    for (uint32_t i = 0; i < linkage.cnt; i++) {
 609       ((uint16_t *) sp_vs_out)[i] =
 610          A6XX_SP_VS_OUT_REG_A_REGID(linkage.var[i].regid) |
 611          A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage.var[i].compmask);
 612       ((uint8_t *) sp_vs_vpc_dst)[i] =
 613          A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage.var[i].loc);
 614    }
 615
 616    tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_OUT_REG(0), sp_vs_out_count);
 617    tu_cs_emit_array(cs, sp_vs_out, sp_vs_out_count);
 618
 619    tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_VPC_DST_REG(0), sp_vs_vpc_dst_count);
 620    tu_cs_emit_array(cs, sp_vs_vpc_dst, sp_vs_vpc_dst_count);
 621
 622    tu_cs_emit_pkt4(cs, REG_A6XX_VPC_CNTL_0, 1);
 623    tu_cs_emit(cs, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs->total_in) |
 624                      (fs->total_in > 0 ? A6XX_VPC_CNTL_0_VARYING : 0) |
 625                      0xff00ff00);
 626
 627    tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK, 1);
 628    tu_cs_emit(cs, A6XX_VPC_PACK_POSITIONLOC(position_loc) |
 629                      A6XX_VPC_PACK_PSIZELOC(pointsize_loc) |
 630                      A6XX_VPC_PACK_STRIDE_IN_VPC(linkage.max_loc));
 631
 632    tu_cs_emit_pkt4(cs, REG_A6XX_VPC_GS_SIV_CNTL, 1);
 633    tu_cs_emit(cs, 0x0000ffff); /* XXX */
 634
 635    tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
 636    tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage.cnt));
 637
 638    tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
 639    tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage.max_loc) |
 640                      (vs->writes_psize ? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE : 0));
 641 }
 642
 643 static int
 644 tu6_vpc_varying_mode(const struct ir3_shader_variant *fs,
 645                      uint32_t index,
 646                      uint8_t *interp_mode,
 647                      uint8_t *ps_repl_mode)
 648 {
 649    enum
 650    {
 651       INTERP_SMOOTH = 0,
 652       INTERP_FLAT = 1,
 653       INTERP_ZERO = 2,
 654       INTERP_ONE = 3,
 655    };
 656    enum
 657    {
 658       PS_REPL_NONE = 0,
 659       PS_REPL_S = 1,
 660       PS_REPL_T = 2,
 661       PS_REPL_ONE_MINUS_T = 3,
 662    };
 663
 664    const uint32_t compmask = fs->inputs[index].compmask;
 665
 666    /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
 667     * fourth component occupy three consecutive varying slots
 668     */
 669    int shift = 0;
 670    *interp_mode = 0;
 671    *ps_repl_mode = 0;
 672    if (fs->inputs[index].slot == VARYING_SLOT_PNTC) {
 673       if (compmask & 0x1) {
 674          *ps_repl_mode |= PS_REPL_S << shift;
 675          shift += 2;
 676       }
 677       if (compmask & 0x2) {
 678          *ps_repl_mode |= PS_REPL_T << shift;
 679          shift += 2;
 680       }
 681       if (compmask & 0x4) {
 682          *interp_mode |= INTERP_ZERO << shift;
 683          shift += 2;
 684       }
 685       if (compmask & 0x8) {
 686          *interp_mode |= INTERP_ONE << 6;
 687          shift += 2;
 688       }
 689    } else if ((fs->inputs[index].interpolate == INTERP_MODE_FLAT) ||
 690               fs->inputs[index].rasterflat) {
 691       for (int i = 0; i < 4; i++) {
 692          if (compmask & (1 << i)) {
 693             *interp_mode |= INTERP_FLAT << shift;
 694             shift += 2;
 695          }
 696       }
 697    }
 698
 699    return shift;
 700 }
 701
 702 static void
 703 tu6_emit_vpc_varying_modes(struct tu_cs *cs,
 704                            const struct ir3_shader_variant *fs,
 705                            bool binning_pass)
 706 {
 707    uint32_t interp_modes[8] = { 0 };
 708    uint32_t ps_repl_modes[8] = { 0 };
 709
 710    if (!binning_pass) {
 711       for (int i = -1;
 712            (i = ir3_next_varying(fs, i)) < (int) fs->inputs_count;) {
 713
 714          /* get the mode for input i */
 715          uint8_t interp_mode;
 716          uint8_t ps_repl_mode;
 717          const int bits =
 718             tu6_vpc_varying_mode(fs, i, &interp_mode, &ps_repl_mode);
 719
 720          /* OR the mode into the array */
 721          const uint32_t inloc = fs->inputs[i].inloc * 2;
 722          uint32_t n = inloc / 32;
 723          uint32_t shift = inloc % 32;
 724          interp_modes[n] |= interp_mode << shift;
 725          ps_repl_modes[n] |= ps_repl_mode << shift;
 726          if (shift + bits > 32) {
 727             n++;
 728             shift = 32 - shift;
 729
 730             interp_modes[n] |= interp_mode >> shift;
 731             ps_repl_modes[n] |= ps_repl_mode >> shift;
 732          }
 733       }
 734    }
 735
 736    tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
 737    tu_cs_emit_array(cs, interp_modes, 8);
 738
 739    tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
 740    tu_cs_emit_array(cs, ps_repl_modes, 8);
 741 }
 742
 743 static void
 744 tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
 745 {
 746    uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
 747    uint32_t ij_pix_regid, ij_samp_regid, ij_cent_regid, ij_size_regid;
 748    uint32_t smask_in_regid;
 749
 750    bool sample_shading = fs->per_samp; /* TODO | key->sample_shading; */
 751    bool enable_varyings = fs->total_in > 0;
 752
 753    samp_id_regid   = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
 754    smask_in_regid  = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
 755    face_regid      = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
 756    coord_regid     = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
 757    zwcoord_regid   = VALIDREG(coord_regid) ? coord_regid + 2 : regid(63, 0);
 758    ij_pix_regid    = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PIXEL);
 759    ij_samp_regid   = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_SAMPLE);
 760    ij_cent_regid   = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_CENTROID);
 761    ij_size_regid   = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_SIZE);
 762
 763    if (fs->num_sampler_prefetch > 0) {
 764       assert(VALIDREG(ij_pix_regid));
 765       /* also, it seems like ij_pix is *required* to be r0.x */
 766       assert(ij_pix_regid == regid(0, 0));
 767    }
 768
 769    tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
 770    tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
 771          A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
 772          0x7000);    // XXX);
 773    for (int i = 0; i < fs->num_sampler_prefetch; i++) {
 774       const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
 775       tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch->src) |
 776                      A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch->samp_id) |
 777                      A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch->tex_id) |
 778                      A6XX_SP_FS_PREFETCH_CMD_DST(prefetch->dst) |
 779                      A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch->wrmask) |
 780                      COND(prefetch->half_precision, A6XX_SP_FS_PREFETCH_CMD_HALF) |
 781                      A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch->cmd));
 782    }
 783
 784    tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
 785    tu_cs_emit(cs, 0x7);
 786    tu_cs_emit(cs, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
 787                   A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
 788                   A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
 789                   A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid));
 790    tu_cs_emit(cs, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid) |
 791                   A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid) |
 792                   0xfc00fc00);
 793    tu_cs_emit(cs, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
 794                   A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
 795                   A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid) |
 796                   0x0000fc00);
 797    tu_cs_emit(cs, 0xfc);
 798
 799    tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
 800    tu_cs_emit(cs, enable_varyings ? 3 : 1);
 801
 802    tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_A982, 1);
 803    tu_cs_emit(cs, 0); /* XXX */
 804
 805    tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
 806    tu_cs_emit(cs, 0xff); /* XXX */
 807
 808    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CNTL, 1);
 809    tu_cs_emit(cs,
 810          CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_VARYING) |
 811          CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_CENTROID) |
 812          CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
 813          COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
 814          COND(VALIDREG(ij_size_regid) &&  sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
 815          COND(fs->frag_coord,
 816                A6XX_GRAS_CNTL_SIZE |
 817                A6XX_GRAS_CNTL_XCOORD |
 818                A6XX_GRAS_CNTL_YCOORD |
 819                A6XX_GRAS_CNTL_ZCOORD |
 820                A6XX_GRAS_CNTL_WCOORD) |
 821          COND(fs->frag_face, A6XX_GRAS_CNTL_SIZE));
 822
 823    tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CONTROL0, 2);
 824    tu_cs_emit(cs,
 825          CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_VARYING) |
 826          CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_CENTROID) |
 827          CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING) |
 828          COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
 829          COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
 830          COND(VALIDREG(ij_size_regid) &&  sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
 831          COND(fs->frag_coord,
 832                A6XX_RB_RENDER_CONTROL0_SIZE |
 833                A6XX_RB_RENDER_CONTROL0_XCOORD |
 834                A6XX_RB_RENDER_CONTROL0_YCOORD |
 835                A6XX_RB_RENDER_CONTROL0_ZCOORD |
 836                A6XX_RB_RENDER_CONTROL0_WCOORD) |
 837          COND(fs->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE));
 838    tu_cs_emit(cs,
 839          CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
 840          CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
 841          CONDREG(ij_size_regid, A6XX_RB_RENDER_CONTROL1_SIZE) |
 842          COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
 843 }
 844
 845 static void
 846 tu6_emit_fs_outputs(struct tu_cs *cs,
 847                     const struct ir3_shader_variant *fs,
 848                     uint32_t mrt_count)
 849 {
 850    uint32_t smask_regid, posz_regid;
 851
 852    posz_regid      = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
 853    smask_regid     = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
 854
 855    uint32_t fragdata_regid[8];
 856    if (fs->color0_mrt) {
 857       fragdata_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
 858       for (uint32_t i = 1; i < ARRAY_SIZE(fragdata_regid); i++)
 859          fragdata_regid[i] = fragdata_regid[0];
 860    } else {
 861       for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++)
 862          fragdata_regid[i] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0 + i);
 863    }
 864
 865    tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_CNTL0, 2);
 866    tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
 867                   A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
 868                   0xfc000000);
 869    tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count));
 870
 871    tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
 872    for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++) {
 873       // TODO we could have a mix of half and full precision outputs,
 874       // we really need to figure out half-precision from IR3_REG_HALF
 875       tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid[i]) |
 876                         (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION : 0));
 877    }
 878
 879    tu_cs_emit_pkt4(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
 880    tu_cs_emit(cs, COND(fs->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
 881                   COND(fs->writes_smask, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK));
 882    tu_cs_emit(cs, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count));
 883
 884    uint32_t gras_su_depth_plane_cntl = 0;
 885    uint32_t rb_depth_plane_cntl = 0;
 886    if (fs->no_earlyz || fs->writes_pos) {
 887       gras_su_depth_plane_cntl |= A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
 888       rb_depth_plane_cntl |= A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
 889    }
 890
 891    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
 892    tu_cs_emit(cs, gras_su_depth_plane_cntl);
 893
 894    tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
 895    tu_cs_emit(cs, rb_depth_plane_cntl);
 896 }
 897
 898 static void
 899 tu6_emit_shader_object(struct tu_cs *cs,
 900                        gl_shader_stage stage,
 901                        const struct ir3_shader_variant *variant,
 902                        const struct tu_bo *binary_bo,
 903                        uint32_t binary_offset)
 904 {
 905    uint16_t reg;
 906    uint8_t opcode;
 907    enum a6xx_state_block sb;
 908    switch (stage) {
 909    case MESA_SHADER_VERTEX:
 910       reg = REG_A6XX_SP_VS_OBJ_START_LO;
 911       opcode = CP_LOAD_STATE6_GEOM;
 912       sb = SB6_VS_SHADER;
 913       break;
 914    case MESA_SHADER_TESS_CTRL:
 915       reg = REG_A6XX_SP_HS_OBJ_START_LO;
 916       opcode = CP_LOAD_STATE6_GEOM;
 917       sb = SB6_HS_SHADER;
 918       break;
 919    case MESA_SHADER_TESS_EVAL:
 920       reg = REG_A6XX_SP_DS_OBJ_START_LO;
 921       opcode = CP_LOAD_STATE6_GEOM;
 922       sb = SB6_DS_SHADER;
 923       break;
 924    case MESA_SHADER_GEOMETRY:
 925       reg = REG_A6XX_SP_GS_OBJ_START_LO;
 926       opcode = CP_LOAD_STATE6_GEOM;
 927       sb = SB6_GS_SHADER;
 928       break;
 929    case MESA_SHADER_FRAGMENT:
 930       reg = REG_A6XX_SP_FS_OBJ_START_LO;
 931       opcode = CP_LOAD_STATE6_FRAG;
 932       sb = SB6_FS_SHADER;
 933       break;
 934    case MESA_SHADER_COMPUTE:
 935       reg = REG_A6XX_SP_CS_OBJ_START_LO;
 936       opcode = CP_LOAD_STATE6_FRAG;
 937       sb = SB6_CS_SHADER;
 938       break;
 939    default:
 940       unreachable("invalid gl_shader_stage");
 941       opcode = CP_LOAD_STATE6_GEOM;
 942       sb = SB6_VS_SHADER;
 943       break;
 944    }
 945
 946    if (!variant->instrlen) {
 947       tu_cs_emit_pkt4(cs, reg, 2);
 948       tu_cs_emit_qw(cs, 0);
 949       return;
 950    }
 951
 952    assert(variant->type == stage);
 953
 954    const uint64_t binary_iova = binary_bo->iova + binary_offset;
 955    assert((binary_iova & 0x3) == 0);
 956
 957    tu_cs_emit_pkt4(cs, reg, 2);
 958    tu_cs_emit_qw(cs, binary_iova);
 959
 960    /* always indirect */
 961    const bool indirect = true;
 962    if (indirect) {
 963       tu_cs_emit_pkt7(cs, opcode, 3);
 964       tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
 965                         CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
 966                         CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
 967                         CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
 968                         CP_LOAD_STATE6_0_NUM_UNIT(variant->instrlen));
 969       tu_cs_emit_qw(cs, binary_iova);
 970    } else {
 971       const void *binary = binary_bo->map + binary_offset;
 972
 973       tu_cs_emit_pkt7(cs, opcode, 3 + variant->info.sizedwords);
 974       tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
 975                         CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
 976                         CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
 977                         CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
 978                         CP_LOAD_STATE6_0_NUM_UNIT(variant->instrlen));
 979       tu_cs_emit_qw(cs, 0);
 980       tu_cs_emit_array(cs, binary, variant->info.sizedwords);
 981    }
 982 }
 983
 984 static void
 985 tu6_emit_immediates(struct tu_cs *cs, const struct ir3_shader_variant *v,
 986                     uint32_t opcode, enum a6xx_state_block block)
 987 {
 988    /* dummy variant */
 989    if (!v->shader)
 990       return;
 991
 992    const struct ir3_const_state *const_state = &v->shader->const_state;
 993    uint32_t base = const_state->offsets.immediate;
 994    int size = const_state->immediates_count;
 995
 996    /* truncate size to avoid writing constants that shader
 997     * does not use:
 998     */
 999    size = MIN2(size + base, v->constlen) - base;
1000
1001    if (size <= 0)
1002       return;
1003
1004    tu_cs_emit_pkt7(cs, opcode, 3 + size * 4);
1005    tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
1006                   CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
1007                   CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
1008                   CP_LOAD_STATE6_0_STATE_BLOCK(block) |
1009                   CP_LOAD_STATE6_0_NUM_UNIT(size));
1010    tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
1011    tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
1012
1013    for (unsigned i = 0; i < size; i++) {
1014       tu_cs_emit(cs, const_state->immediates[i].val[0]);
1015       tu_cs_emit(cs, const_state->immediates[i].val[1]);
1016       tu_cs_emit(cs, const_state->immediates[i].val[2]);
1017       tu_cs_emit(cs, const_state->immediates[i].val[3]);
1018    }
1019 }
1020
1021 static void
1022 tu6_emit_program(struct tu_cs *cs,
1023                  const struct tu_pipeline_builder *builder,
1024                  const struct tu_bo *binary_bo,
1025                  bool binning_pass)
1026 {
1027    static const struct ir3_shader_variant dummy_variant = {
1028       .type = MESA_SHADER_NONE
1029    };
1030    assert(builder->shaders[MESA_SHADER_VERTEX]);
1031    const struct ir3_shader_variant *vs =
1032       &builder->shaders[MESA_SHADER_VERTEX]->variants[0];
1033    const struct ir3_shader_variant *hs =
1034       builder->shaders[MESA_SHADER_TESS_CTRL]
1035          ? &builder->shaders[MESA_SHADER_TESS_CTRL]->variants[0]
1036          : &dummy_variant;
1037    const struct ir3_shader_variant *ds =
1038       builder->shaders[MESA_SHADER_TESS_EVAL]
1039          ? &builder->shaders[MESA_SHADER_TESS_EVAL]->variants[0]
1040          : &dummy_variant;
1041    const struct ir3_shader_variant *gs =
1042       builder->shaders[MESA_SHADER_GEOMETRY]
1043          ? &builder->shaders[MESA_SHADER_GEOMETRY]->variants[0]
1044          : &dummy_variant;
1045    const struct ir3_shader_variant *fs =
1046       builder->shaders[MESA_SHADER_FRAGMENT]
1047          ? &builder->shaders[MESA_SHADER_FRAGMENT]->variants[0]
1048          : &dummy_variant;
1049
1050    if (binning_pass) {
1051       vs = &builder->shaders[MESA_SHADER_VERTEX]->variants[1];
1052       fs = &dummy_variant;
1053    }
1054
1055    tu6_emit_vs_config(cs, builder->shaders[MESA_SHADER_VERTEX], vs);
1056    tu6_emit_hs_config(cs, builder->shaders[MESA_SHADER_TESS_CTRL], hs);
1057    tu6_emit_ds_config(cs, builder->shaders[MESA_SHADER_TESS_EVAL], ds);
1058    tu6_emit_gs_config(cs, builder->shaders[MESA_SHADER_GEOMETRY], gs);
1059    tu6_emit_fs_config(cs, builder->shaders[MESA_SHADER_FRAGMENT], fs);
1060
1061    tu6_emit_vs_system_values(cs, vs);
1062    tu6_emit_vpc(cs, vs, fs, binning_pass);
1063    tu6_emit_vpc_varying_modes(cs, fs, binning_pass);
1064    tu6_emit_fs_inputs(cs, fs);
1065    tu6_emit_fs_outputs(cs, fs, builder->color_attachment_count);
1066
1067    tu6_emit_shader_object(cs, MESA_SHADER_VERTEX, vs, binary_bo,
1068       binning_pass ? builder->binning_vs_offset : builder->shader_offsets[MESA_SHADER_VERTEX]);
1069
1070    tu6_emit_shader_object(cs, MESA_SHADER_FRAGMENT, fs, binary_bo,
1071                           builder->shader_offsets[MESA_SHADER_FRAGMENT]);
1072
1073    tu6_emit_immediates(cs, vs, CP_LOAD_STATE6_GEOM, SB6_VS_SHADER);
1074    if (!binning_pass)
1075       tu6_emit_immediates(cs, fs, CP_LOAD_STATE6_FRAG, SB6_FS_SHADER);
1076 }
1077
1078 static void
1079 tu6_emit_vertex_input(struct tu_cs *cs,
1080                       const struct ir3_shader_variant *vs,
1081                       const VkPipelineVertexInputStateCreateInfo *vi_info,
1082                       uint8_t bindings[MAX_VERTEX_ATTRIBS],
1083                       uint16_t strides[MAX_VERTEX_ATTRIBS],
1084                       uint16_t offsets[MAX_VERTEX_ATTRIBS],
1085                       uint32_t *count)
1086 {
1087    uint32_t vfd_decode_idx = 0;
1088
1089    for (uint32_t i = 0; i < vs->inputs_count; i++) {
1090       if (vs->inputs[i].sysval || !vs->inputs[i].compmask)
1091          continue;
1092
1093       const VkVertexInputAttributeDescription *vi_attr =
1094          tu_find_vertex_input_attribute(vi_info, vs->inputs[i].slot);
1095       const VkVertexInputBindingDescription *vi_binding =
1096          tu_find_vertex_input_binding(vi_info, vi_attr);
1097       assert(vi_attr && vi_binding);
1098
1099       const struct tu_native_format *format =
1100          tu6_get_native_format(vi_attr->format);
1101       assert(format && format->vtx >= 0);
1102
1103       uint32_t vfd_decode = A6XX_VFD_DECODE_INSTR_IDX(vfd_decode_idx) |
1104                             A6XX_VFD_DECODE_INSTR_FORMAT(format->vtx) |
1105                             A6XX_VFD_DECODE_INSTR_SWAP(format->swap) |
1106                             A6XX_VFD_DECODE_INSTR_UNK30;
1107       if (vi_binding->inputRate == VK_VERTEX_INPUT_RATE_INSTANCE)
1108          vfd_decode |= A6XX_VFD_DECODE_INSTR_INSTANCED;
1109       if (!vk_format_is_int(vi_attr->format))
1110          vfd_decode |= A6XX_VFD_DECODE_INSTR_FLOAT;
1111
1112       const uint32_t vfd_decode_step_rate = 1;
1113
1114       const uint32_t vfd_dest_cntl =
1115          A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vs->inputs[i].compmask) |
1116          A6XX_VFD_DEST_CNTL_INSTR_REGID(vs->inputs[i].regid);
1117
1118       tu_cs_emit_pkt4(cs, REG_A6XX_VFD_DECODE(vfd_decode_idx), 2);
1119       tu_cs_emit(cs, vfd_decode);
1120       tu_cs_emit(cs, vfd_decode_step_rate);
1121
1122       tu_cs_emit_pkt4(cs, REG_A6XX_VFD_DEST_CNTL(vfd_decode_idx), 1);
1123       tu_cs_emit(cs, vfd_dest_cntl);
1124
1125       bindings[vfd_decode_idx] = vi_binding->binding;
1126       strides[vfd_decode_idx] = vi_binding->stride;
1127       offsets[vfd_decode_idx] = vi_attr->offset;
1128
1129       vfd_decode_idx++;
1130       assert(vfd_decode_idx <= MAX_VERTEX_ATTRIBS);
1131    }
1132
1133    tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_0, 1);
1134    tu_cs_emit(
1135       cs, A6XX_VFD_CONTROL_0_VTXCNT(vfd_decode_idx) | (vfd_decode_idx << 8));
1136
1137    *count = vfd_decode_idx;
1138 }
1139
1140 static uint32_t
1141 tu6_guardband_adj(uint32_t v)
1142 {
1143    if (v > 256)
1144       return (uint32_t)(511.0 - 65.0 * (log2(v) - 8.0));
1145    else
1146       return 511;
1147 }
1148
1149 void
1150 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport)
1151 {
1152    float offsets[3];
1153    float scales[3];
1154    scales[0] = viewport->width / 2.0f;
1155    scales[1] = viewport->height / 2.0f;
1156    scales[2] = viewport->maxDepth - viewport->minDepth;
1157    offsets[0] = viewport->x + scales[0];
1158    offsets[1] = viewport->y + scales[1];
1159    offsets[2] = viewport->minDepth;
1160
1161    VkOffset2D min;
1162    VkOffset2D max;
1163    min.x = (int32_t) viewport->x;
1164    max.x = (int32_t) ceilf(viewport->x + viewport->width);
1165    if (viewport->height >= 0.0f) {
1166       min.y = (int32_t) viewport->y;
1167       max.y = (int32_t) ceilf(viewport->y + viewport->height);
1168    } else {
1169       min.y = (int32_t)(viewport->y + viewport->height);
1170       max.y = (int32_t) ceilf(viewport->y);
1171    }
1172    /* the spec allows viewport->height to be 0.0f */
1173    if (min.y == max.y)
1174       max.y++;
1175    assert(min.x >= 0 && min.x < max.x);
1176    assert(min.y >= 0 && min.y < max.y);
1177
1178    VkExtent2D guardband_adj;
1179    guardband_adj.width = tu6_guardband_adj(max.x - min.x);
1180    guardband_adj.height = tu6_guardband_adj(max.y - min.y);
1181
1182    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0, 6);
1183    tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XOFFSET_0(offsets[0]));
1184    tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XSCALE_0(scales[0]));
1185    tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YOFFSET_0(offsets[1]));
1186    tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YSCALE_0(scales[1]));
1187    tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZOFFSET_0(offsets[2]));
1188    tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZSCALE_0(scales[2]));
1189
1190    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
1191    tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(min.x) |
1192                      A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(min.y));
1193    tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(max.x - 1) |
1194                      A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(max.y - 1));
1195
1196    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
1197    tu_cs_emit(cs,
1198               A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj.width) |
1199                  A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj.height));
1200 }
1201
1202 void
1203 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor)
1204 {
1205    const VkOffset2D min = scissor->offset;
1206    const VkOffset2D max = {
1207       scissor->offset.x + scissor->extent.width,
1208       scissor->offset.y + scissor->extent.height,
1209    };
1210
1211    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
1212    tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(min.x) |
1213                      A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(min.y));
1214    tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(max.x - 1) |
1215                      A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(max.y - 1));
1216 }
1217
1218 static void
1219 tu6_emit_gras_unknowns(struct tu_cs *cs)
1220 {
1221    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8000, 1);
1222    tu_cs_emit(cs, 0x80);
1223    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8001, 1);
1224    tu_cs_emit(cs, 0x0);
1225    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LAYER_CNTL, 1);
1226    tu_cs_emit(cs, 0x0);
1227 }
1228
1229 static void
1230 tu6_emit_point_size(struct tu_cs *cs)
1231 {
1232    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POINT_MINMAX, 2);
1233    tu_cs_emit(cs, A6XX_GRAS_SU_POINT_MINMAX_MIN(1.0f / 16.0f) |
1234                      A6XX_GRAS_SU_POINT_MINMAX_MAX(4092.0f));
1235    tu_cs_emit(cs, A6XX_GRAS_SU_POINT_SIZE(1.0f));
1236 }
1237
1238 static uint32_t
1239 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo *rast_info,
1240                  VkSampleCountFlagBits samples)
1241 {
1242    uint32_t gras_su_cntl = 0;
1243
1244    if (rast_info->cullMode & VK_CULL_MODE_FRONT_BIT)
1245       gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_FRONT;
1246    if (rast_info->cullMode & VK_CULL_MODE_BACK_BIT)
1247       gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_BACK;
1248
1249    if (rast_info->frontFace == VK_FRONT_FACE_CLOCKWISE)
1250       gras_su_cntl |= A6XX_GRAS_SU_CNTL_FRONT_CW;
1251
1252    /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1253
1254    if (rast_info->depthBiasEnable)
1255       gras_su_cntl |= A6XX_GRAS_SU_CNTL_POLY_OFFSET;
1256
1257    if (samples > VK_SAMPLE_COUNT_1_BIT)
1258       gras_su_cntl |= A6XX_GRAS_SU_CNTL_MSAA_ENABLE;
1259
1260    return gras_su_cntl;
1261 }
1262
1263 void
1264 tu6_emit_gras_su_cntl(struct tu_cs *cs,
1265                       uint32_t gras_su_cntl,
1266                       float line_width)
1267 {
1268    assert((gras_su_cntl & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK) == 0);
1269    gras_su_cntl |= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(line_width / 2.0f);
1270
1271    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_CNTL, 1);
1272    tu_cs_emit(cs, gras_su_cntl);
1273 }
1274
1275 void
1276 tu6_emit_depth_bias(struct tu_cs *cs,
1277                     float constant_factor,
1278                     float clamp,
1279                     float slope_factor)
1280 {
1281    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
1282    tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor));
1283    tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor));
1284    tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp));
1285 }
1286
1287 static void
1288 tu6_emit_alpha_control_disable(struct tu_cs *cs)
1289 {
1290    tu_cs_emit_pkt4(cs, REG_A6XX_RB_ALPHA_CONTROL, 1);
1291    tu_cs_emit(cs, 0);
1292 }
1293
1294 static void
1295 tu6_emit_depth_control(struct tu_cs *cs,
1296                        const VkPipelineDepthStencilStateCreateInfo *ds_info)
1297 {
1298    assert(!ds_info->depthBoundsTestEnable);
1299
1300    uint32_t rb_depth_cntl = 0;
1301    if (ds_info->depthTestEnable) {
1302       rb_depth_cntl |=
1303          A6XX_RB_DEPTH_CNTL_Z_ENABLE |
1304          A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) |
1305          A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
1306
1307       if (ds_info->depthWriteEnable)
1308          rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
1309    }
1310
1311    tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_CNTL, 1);
1312    tu_cs_emit(cs, rb_depth_cntl);
1313 }
1314
1315 static void
1316 tu6_emit_stencil_control(struct tu_cs *cs,
1317                          const VkPipelineDepthStencilStateCreateInfo *ds_info)
1318 {
1319    uint32_t rb_stencil_control = 0;
1320    if (ds_info->stencilTestEnable) {
1321       const VkStencilOpState *front = &ds_info->front;
1322       const VkStencilOpState *back = &ds_info->back;
1323       rb_stencil_control |=
1324          A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
1325          A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
1326          A6XX_RB_STENCIL_CONTROL_STENCIL_READ |
1327          A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front->compareOp)) |
1328          A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front->failOp)) |
1329          A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front->passOp)) |
1330          A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front->depthFailOp)) |
1331          A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back->compareOp)) |
1332          A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back->failOp)) |
1333          A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back->passOp)) |
1334          A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back->depthFailOp));
1335    }
1336
1337    tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_CONTROL, 1);
1338    tu_cs_emit(cs, rb_stencil_control);
1339 }
1340
1341 void
1342 tu6_emit_stencil_compare_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1343 {
1344    tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILMASK, 1);
1345    tu_cs_emit(
1346       cs, A6XX_RB_STENCILMASK_MASK(front) | A6XX_RB_STENCILMASK_BFMASK(back));
1347 }
1348
1349 void
1350 tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1351 {
1352    tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILWRMASK, 1);
1353    tu_cs_emit(cs, A6XX_RB_STENCILWRMASK_WRMASK(front) |
1354                      A6XX_RB_STENCILWRMASK_BFWRMASK(back));
1355 }
1356
1357 void
1358 tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back)
1359 {
1360    tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILREF, 1);
1361    tu_cs_emit(cs,
1362               A6XX_RB_STENCILREF_REF(front) | A6XX_RB_STENCILREF_BFREF(back));
1363 }
1364
1365 static uint32_t
1366 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState *att,
1367                          bool has_alpha)
1368 {
1369    const enum a3xx_rb_blend_opcode color_op = tu6_blend_op(att->colorBlendOp);
1370    const enum adreno_rb_blend_factor src_color_factor = tu6_blend_factor(
1371       has_alpha ? att->srcColorBlendFactor
1372                 : tu_blend_factor_no_dst_alpha(att->srcColorBlendFactor));
1373    const enum adreno_rb_blend_factor dst_color_factor = tu6_blend_factor(
1374       has_alpha ? att->dstColorBlendFactor
1375                 : tu_blend_factor_no_dst_alpha(att->dstColorBlendFactor));
1376    const enum a3xx_rb_blend_opcode alpha_op = tu6_blend_op(att->alphaBlendOp);
1377    const enum adreno_rb_blend_factor src_alpha_factor =
1378       tu6_blend_factor(att->srcAlphaBlendFactor);
1379    const enum adreno_rb_blend_factor dst_alpha_factor =
1380       tu6_blend_factor(att->dstAlphaBlendFactor);
1381
1382    return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor) |
1383           A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op) |
1384           A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor) |
1385           A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor) |
1386           A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op) |
1387           A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor);
1388 }
1389
1390 static uint32_t
1391 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState *att,
1392                    uint32_t rb_mrt_control_rop,
1393                    bool is_int,
1394                    bool has_alpha)
1395 {
1396    uint32_t rb_mrt_control =
1397       A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att->colorWriteMask);
1398
1399    /* ignore blending and logic op for integer attachments */
1400    if (is_int) {
1401       rb_mrt_control |= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
1402       return rb_mrt_control;
1403    }
1404
1405    rb_mrt_control |= rb_mrt_control_rop;
1406
1407    if (att->blendEnable) {
1408       rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND;
1409
1410       if (has_alpha)
1411          rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND2;
1412    }
1413
1414    return rb_mrt_control;
1415 }
1416
1417 static void
1418 tu6_emit_rb_mrt_controls(struct tu_cs *cs,
1419                          const VkPipelineColorBlendStateCreateInfo *blend_info,
1420                          const VkFormat attachment_formats[MAX_RTS],
1421                          uint32_t *blend_enable_mask)
1422 {
1423    *blend_enable_mask = 0;
1424
1425    bool rop_reads_dst = false;
1426    uint32_t rb_mrt_control_rop = 0;
1427    if (blend_info->logicOpEnable) {
1428       rop_reads_dst = tu_logic_op_reads_dst(blend_info->logicOp);
1429       rb_mrt_control_rop =
1430          A6XX_RB_MRT_CONTROL_ROP_ENABLE |
1431          A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info->logicOp));
1432    }
1433
1434    for (uint32_t i = 0; i < blend_info->attachmentCount; i++) {
1435       const VkPipelineColorBlendAttachmentState *att =
1436          &blend_info->pAttachments[i];
1437       const VkFormat format = attachment_formats[i];
1438
1439       uint32_t rb_mrt_control = 0;
1440       uint32_t rb_mrt_blend_control = 0;
1441       if (format != VK_FORMAT_UNDEFINED) {
1442          const bool is_int = vk_format_is_int(format);
1443          const bool has_alpha = vk_format_has_alpha(format);
1444
1445          rb_mrt_control =
1446             tu6_rb_mrt_control(att, rb_mrt_control_rop, is_int, has_alpha);
1447          rb_mrt_blend_control = tu6_rb_mrt_blend_control(att, has_alpha);
1448
1449          if (att->blendEnable || rop_reads_dst)
1450             *blend_enable_mask |= 1 << i;
1451       }
1452
1453       tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
1454       tu_cs_emit(cs, rb_mrt_control);
1455       tu_cs_emit(cs, rb_mrt_blend_control);
1456    }
1457
1458    for (uint32_t i = blend_info->attachmentCount; i < MAX_RTS; i++) {
1459       tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
1460       tu_cs_emit(cs, 0);
1461       tu_cs_emit(cs, 0);
1462    }
1463 }
1464
1465 static void
1466 tu6_emit_blend_control(struct tu_cs *cs,
1467                        uint32_t blend_enable_mask,
1468                        const VkPipelineMultisampleStateCreateInfo *msaa_info)
1469 {
1470    assert(!msaa_info->sampleShadingEnable);
1471    assert(!msaa_info->alphaToOneEnable);
1472
1473    uint32_t sp_blend_cntl = A6XX_SP_BLEND_CNTL_UNK8;
1474    if (blend_enable_mask)
1475       sp_blend_cntl |= A6XX_SP_BLEND_CNTL_ENABLED;
1476    if (msaa_info->alphaToCoverageEnable)
1477       sp_blend_cntl |= A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE;
1478
1479    const uint32_t sample_mask =
1480       msaa_info->pSampleMask ? *msaa_info->pSampleMask
1481                              : ((1 << msaa_info->rasterizationSamples) - 1);
1482
1483    /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
1484    uint32_t rb_blend_cntl =
1485       A6XX_RB_BLEND_CNTL_ENABLE_BLEND(blend_enable_mask) |
1486       A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND |
1487       A6XX_RB_BLEND_CNTL_SAMPLE_MASK(sample_mask);
1488    if (msaa_info->alphaToCoverageEnable)
1489       rb_blend_cntl |= A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE;
1490
1491    tu_cs_emit_pkt4(cs, REG_A6XX_SP_BLEND_CNTL, 1);
1492    tu_cs_emit(cs, sp_blend_cntl);
1493
1494    tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_CNTL, 1);
1495    tu_cs_emit(cs, rb_blend_cntl);
1496 }
1497
1498 void
1499 tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4])
1500 {
1501    tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_RED_F32, 4);
1502    tu_cs_emit_array(cs, (const uint32_t *) constants, 4);
1503 }
1504
1505 static VkResult
1506 tu_pipeline_create(struct tu_device *dev,
1507                    const VkAllocationCallbacks *pAllocator,
1508                    struct tu_pipeline **out_pipeline)
1509 {
1510    struct tu_pipeline *pipeline =
1511       vk_zalloc2(&dev->alloc, pAllocator, sizeof(*pipeline), 8,
1512                  VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1513    if (!pipeline)
1514       return VK_ERROR_OUT_OF_HOST_MEMORY;
1515
1516    tu_cs_init(&pipeline->cs, TU_CS_MODE_SUB_STREAM, 2048);
1517
1518    /* reserve the space now such that tu_cs_begin_sub_stream never fails */
1519    VkResult result = tu_cs_reserve_space(dev, &pipeline->cs, 2048);
1520    if (result != VK_SUCCESS) {
1521       vk_free2(&dev->alloc, pAllocator, pipeline);
1522       return result;
1523    }
1524
1525    *out_pipeline = pipeline;
1526
1527    return VK_SUCCESS;
1528 }
1529
1530 static VkResult
1531 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder)
1532 {
1533    const VkPipelineShaderStageCreateInfo *stage_infos[MESA_SHADER_STAGES] = {
1534       NULL
1535    };
1536    for (uint32_t i = 0; i < builder->create_info->stageCount; i++) {
1537       gl_shader_stage stage =
1538          tu_shader_stage(builder->create_info->pStages[i].stage);
1539       stage_infos[stage] = &builder->create_info->pStages[i];
1540    }
1541
1542    struct tu_shader_compile_options options;
1543    tu_shader_compile_options_init(&options, builder->create_info);
1544
1545    /* compile shaders in reverse order */
1546    struct tu_shader *next_stage_shader = NULL;
1547    for (gl_shader_stage stage = MESA_SHADER_STAGES - 1;
1548         stage > MESA_SHADER_NONE; stage--) {
1549       const VkPipelineShaderStageCreateInfo *stage_info = stage_infos[stage];
1550       if (!stage_info)
1551          continue;
1552
1553       struct tu_shader *shader =
1554          tu_shader_create(builder->device, stage, stage_info, builder->layout,
1555                           builder->alloc);
1556       if (!shader)
1557          return VK_ERROR_OUT_OF_HOST_MEMORY;
1558
1559       VkResult result =
1560          tu_shader_compile(builder->device, shader, next_stage_shader,
1561                            &options, builder->alloc);
1562       if (result != VK_SUCCESS)
1563          return result;
1564
1565       builder->shaders[stage] = shader;
1566       builder->shader_offsets[stage] = builder->shader_total_size;
1567       builder->shader_total_size +=
1568          sizeof(uint32_t) * shader->variants[0].info.sizedwords;
1569
1570       next_stage_shader = shader;
1571    }
1572
1573    if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
1574       const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1575       builder->binning_vs_offset = builder->shader_total_size;
1576       builder->shader_total_size +=
1577          sizeof(uint32_t) * vs->variants[1].info.sizedwords;
1578    }
1579
1580    return VK_SUCCESS;
1581 }
1582
1583 static VkResult
1584 tu_pipeline_builder_upload_shaders(struct tu_pipeline_builder *builder,
1585                                    struct tu_pipeline *pipeline)
1586 {
1587    struct tu_bo *bo = &pipeline->program.binary_bo;
1588
1589    VkResult result =
1590       tu_bo_init_new(builder->device, bo, builder->shader_total_size);
1591    if (result != VK_SUCCESS)
1592       return result;
1593
1594    result = tu_bo_map(builder->device, bo);
1595    if (result != VK_SUCCESS)
1596       return result;
1597
1598    for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
1599       const struct tu_shader *shader = builder->shaders[i];
1600       if (!shader)
1601          continue;
1602
1603       memcpy(bo->map + builder->shader_offsets[i], shader->binary,
1604              sizeof(uint32_t) * shader->variants[0].info.sizedwords);
1605    }
1606
1607    if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
1608       const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1609       memcpy(bo->map + builder->binning_vs_offset, vs->binning_binary,
1610              sizeof(uint32_t) * vs->variants[1].info.sizedwords);
1611    }
1612
1613    return VK_SUCCESS;
1614 }
1615
1616 static void
1617 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
1618                                   struct tu_pipeline *pipeline)
1619 {
1620    const VkPipelineDynamicStateCreateInfo *dynamic_info =
1621       builder->create_info->pDynamicState;
1622
1623    if (!dynamic_info)
1624       return;
1625
1626    for (uint32_t i = 0; i < dynamic_info->dynamicStateCount; i++) {
1627       pipeline->dynamic_state.mask |=
1628          tu_dynamic_state_bit(dynamic_info->pDynamicStates[i]);
1629    }
1630 }
1631
1632 static void
1633 tu_pipeline_set_linkage(struct tu_program_descriptor_linkage *link,
1634                         struct tu_shader *shader,
1635                         struct ir3_shader_variant *v)
1636 {
1637    link->ubo_state = v->shader->ubo_state;
1638    link->const_state = v->shader->const_state;
1639    link->constlen = v->constlen;
1640    link->texture_map = shader->texture_map;
1641    link->sampler_map = shader->sampler_map;
1642    link->ubo_map = shader->ubo_map;
1643    link->ssbo_map = shader->ssbo_map;
1644    link->image_map = shader->image_map;
1645 }
1646
1647 static void
1648 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder *builder,
1649                                         struct tu_pipeline *pipeline)
1650 {
1651    struct tu_cs prog_cs;
1652    tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 512, &prog_cs);
1653    tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, false);
1654    pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
1655
1656    tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 512, &prog_cs);
1657    tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, true);
1658    pipeline->program.binning_state_ib =
1659       tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
1660
1661    for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
1662       if (!builder->shaders[i])
1663          continue;
1664
1665       tu_pipeline_set_linkage(&pipeline->program.link[i],
1666                               builder->shaders[i],
1667                               &builder->shaders[i]->variants[0]);
1668    }
1669 }
1670
1671 static void
1672 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder *builder,
1673                                        struct tu_pipeline *pipeline)
1674 {
1675    const VkPipelineVertexInputStateCreateInfo *vi_info =
1676       builder->create_info->pVertexInputState;
1677    const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1678
1679    struct tu_cs vi_cs;
1680    tu_cs_begin_sub_stream(builder->device, &pipeline->cs,
1681                           MAX_VERTEX_ATTRIBS * 5 + 2, &vi_cs);
1682    tu6_emit_vertex_input(&vi_cs, &vs->variants[0], vi_info,
1683                          pipeline->vi.bindings, pipeline->vi.strides,
1684                          pipeline->vi.offsets, &pipeline->vi.count);
1685    pipeline->vi.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
1686
1687    if (vs->has_binning_pass) {
1688       tu_cs_begin_sub_stream(builder->device, &pipeline->cs,
1689                              MAX_VERTEX_ATTRIBS * 5 + 2, &vi_cs);
1690       tu6_emit_vertex_input(
1691          &vi_cs, &vs->variants[1], vi_info, pipeline->vi.binning_bindings,
1692          pipeline->vi.binning_strides, pipeline->vi.binning_offsets,
1693          &pipeline->vi.binning_count);
1694       pipeline->vi.binning_state_ib =
1695          tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
1696    }
1697 }
1698
1699 static void
1700 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder *builder,
1701                                          struct tu_pipeline *pipeline)
1702 {
1703    const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1704       builder->create_info->pInputAssemblyState;
1705
1706    pipeline->ia.primtype = tu6_primtype(ia_info->topology);
1707    pipeline->ia.primitive_restart = ia_info->primitiveRestartEnable;
1708 }
1709
1710 static void
1711 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder *builder,
1712                                    struct tu_pipeline *pipeline)
1713 {
1714    /* The spec says:
1715     *
1716     *    pViewportState is a pointer to an instance of the
1717     *    VkPipelineViewportStateCreateInfo structure, and is ignored if the
1718     *    pipeline has rasterization disabled."
1719     *
1720     * We leave the relevant registers stale in that case.
1721     */
1722    if (builder->rasterizer_discard)
1723       return;
1724
1725    const VkPipelineViewportStateCreateInfo *vp_info =
1726       builder->create_info->pViewportState;
1727
1728    struct tu_cs vp_cs;
1729    tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 15, &vp_cs);
1730
1731    if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_VIEWPORT)) {
1732       assert(vp_info->viewportCount == 1);
1733       tu6_emit_viewport(&vp_cs, vp_info->pViewports);
1734    }
1735
1736    if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_SCISSOR)) {
1737       assert(vp_info->scissorCount == 1);
1738       tu6_emit_scissor(&vp_cs, vp_info->pScissors);
1739    }
1740
1741    pipeline->vp.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vp_cs);
1742 }
1743
1744 static void
1745 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder,
1746                                         struct tu_pipeline *pipeline)
1747 {
1748    const VkPipelineRasterizationStateCreateInfo *rast_info =
1749       builder->create_info->pRasterizationState;
1750
1751    assert(!rast_info->depthClampEnable);
1752    assert(rast_info->polygonMode == VK_POLYGON_MODE_FILL);
1753
1754    struct tu_cs rast_cs;
1755    tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 20, &rast_cs);
1756
1757    /* move to hw ctx init? */
1758    tu6_emit_gras_unknowns(&rast_cs);
1759    tu6_emit_point_size(&rast_cs);
1760
1761    const uint32_t gras_su_cntl =
1762       tu6_gras_su_cntl(rast_info, builder->samples);
1763
1764    if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH))
1765       tu6_emit_gras_su_cntl(&rast_cs, gras_su_cntl, rast_info->lineWidth);
1766
1767    if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_DEPTH_BIAS)) {
1768       tu6_emit_depth_bias(&rast_cs, rast_info->depthBiasConstantFactor,
1769                           rast_info->depthBiasClamp,
1770                           rast_info->depthBiasSlopeFactor);
1771    }
1772
1773    pipeline->rast.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &rast_cs);
1774
1775    pipeline->rast.gras_su_cntl = gras_su_cntl;
1776 }
1777
1778 static void
1779 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
1780                                         struct tu_pipeline *pipeline)
1781 {
1782    /* The spec says:
1783     *
1784     *    pDepthStencilState is a pointer to an instance of the
1785     *    VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
1786     *    the pipeline has rasterization disabled or if the subpass of the
1787     *    render pass the pipeline is created against does not use a
1788     *    depth/stencil attachment.
1789     *
1790     * We disable both depth and stenil tests in those cases.
1791     */
1792    static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info;
1793    const VkPipelineDepthStencilStateCreateInfo *ds_info =
1794       builder->use_depth_stencil_attachment
1795          ? builder->create_info->pDepthStencilState
1796          : &dummy_ds_info;
1797
1798    struct tu_cs ds_cs;
1799    tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 12, &ds_cs);
1800
1801    /* move to hw ctx init? */
1802    tu6_emit_alpha_control_disable(&ds_cs);
1803
1804    tu6_emit_depth_control(&ds_cs, ds_info);
1805    tu6_emit_stencil_control(&ds_cs, ds_info);
1806
1807    if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
1808       tu6_emit_stencil_compare_mask(&ds_cs, ds_info->front.compareMask,
1809                                     ds_info->back.compareMask);
1810    }
1811    if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
1812       tu6_emit_stencil_write_mask(&ds_cs, ds_info->front.writeMask,
1813                                   ds_info->back.writeMask);
1814    }
1815    if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
1816       tu6_emit_stencil_reference(&ds_cs, ds_info->front.reference,
1817                                  ds_info->back.reference);
1818    }
1819
1820    pipeline->ds.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &ds_cs);
1821 }
1822
1823 static void
1824 tu_pipeline_builder_parse_multisample_and_color_blend(
1825    struct tu_pipeline_builder *builder, struct tu_pipeline *pipeline)
1826 {
1827    /* The spec says:
1828     *
1829     *    pMultisampleState is a pointer to an instance of the
1830     *    VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
1831     *    has rasterization disabled.
1832     *
1833     * Also,
1834     *
1835     *    pColorBlendState is a pointer to an instance of the
1836     *    VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
1837     *    pipeline has rasterization disabled or if the subpass of the render
1838     *    pass the pipeline is created against does not use any color
1839     *    attachments.
1840     *
1841     * We leave the relevant registers stale when rasterization is disabled.
1842     */
1843    if (builder->rasterizer_discard)
1844       return;
1845
1846    static const VkPipelineColorBlendStateCreateInfo dummy_blend_info;
1847    const VkPipelineMultisampleStateCreateInfo *msaa_info =
1848       builder->create_info->pMultisampleState;
1849    const VkPipelineColorBlendStateCreateInfo *blend_info =
1850       builder->use_color_attachments ? builder->create_info->pColorBlendState
1851                                      : &dummy_blend_info;
1852
1853    struct tu_cs blend_cs;
1854    tu_cs_begin_sub_stream(builder->device, &pipeline->cs, MAX_RTS * 3 + 9,
1855                           &blend_cs);
1856
1857    uint32_t blend_enable_mask;
1858    tu6_emit_rb_mrt_controls(&blend_cs, blend_info,
1859                             builder->color_attachment_formats,
1860                             &blend_enable_mask);
1861
1862    if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_BLEND_CONSTANTS))
1863       tu6_emit_blend_constants(&blend_cs, blend_info->blendConstants);
1864
1865    tu6_emit_blend_control(&blend_cs, blend_enable_mask, msaa_info);
1866
1867    pipeline->blend.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &blend_cs);
1868 }
1869
1870 static void
1871 tu_pipeline_finish(struct tu_pipeline *pipeline,
1872                    struct tu_device *dev,
1873                    const VkAllocationCallbacks *alloc)
1874 {
1875    tu_cs_finish(dev, &pipeline->cs);
1876
1877    if (pipeline->program.binary_bo.gem_handle)
1878       tu_bo_finish(dev, &pipeline->program.binary_bo);
1879 }
1880
1881 static VkResult
1882 tu_pipeline_builder_build(struct tu_pipeline_builder *builder,
1883                           struct tu_pipeline **pipeline)
1884 {
1885    VkResult result = tu_pipeline_create(builder->device, builder->alloc,
1886                                         pipeline);
1887    if (result != VK_SUCCESS)
1888       return result;
1889
1890    /* compile and upload shaders */
1891    result = tu_pipeline_builder_compile_shaders(builder);
1892    if (result == VK_SUCCESS)
1893       result = tu_pipeline_builder_upload_shaders(builder, *pipeline);
1894    if (result != VK_SUCCESS) {
1895       tu_pipeline_finish(*pipeline, builder->device, builder->alloc);
1896       vk_free2(&builder->device->alloc, builder->alloc, *pipeline);
1897       *pipeline = VK_NULL_HANDLE;
1898
1899       return result;
1900    }
1901
1902    tu_pipeline_builder_parse_dynamic(builder, *pipeline);
1903    tu_pipeline_builder_parse_shader_stages(builder, *pipeline);
1904    tu_pipeline_builder_parse_vertex_input(builder, *pipeline);
1905    tu_pipeline_builder_parse_input_assembly(builder, *pipeline);
1906    tu_pipeline_builder_parse_viewport(builder, *pipeline);
1907    tu_pipeline_builder_parse_rasterization(builder, *pipeline);
1908    tu_pipeline_builder_parse_depth_stencil(builder, *pipeline);
1909    tu_pipeline_builder_parse_multisample_and_color_blend(builder, *pipeline);
1910
1911    /* we should have reserved enough space upfront such that the CS never
1912     * grows
1913     */
1914    assert((*pipeline)->cs.bo_count == 1);
1915
1916    return VK_SUCCESS;
1917 }
1918
1919 static void
1920 tu_pipeline_builder_finish(struct tu_pipeline_builder *builder)
1921 {
1922    for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
1923       if (!builder->shaders[i])
1924          continue;
1925       tu_shader_destroy(builder->device, builder->shaders[i], builder->alloc);
1926    }
1927 }
1928
1929 static void
1930 tu_pipeline_builder_init_graphics(
1931    struct tu_pipeline_builder *builder,
1932    struct tu_device *dev,
1933    struct tu_pipeline_cache *cache,
1934    const VkGraphicsPipelineCreateInfo *create_info,
1935    const VkAllocationCallbacks *alloc)
1936 {
1937    TU_FROM_HANDLE(tu_pipeline_layout, layout, create_info->layout);
1938
1939    *builder = (struct tu_pipeline_builder) {
1940       .device = dev,
1941       .cache = cache,
1942       .create_info = create_info,
1943       .alloc = alloc,
1944       .layout = layout,
1945    };
1946
1947    builder->rasterizer_discard =
1948       create_info->pRasterizationState->rasterizerDiscardEnable;
1949
1950    if (builder->rasterizer_discard) {
1951       builder->samples = VK_SAMPLE_COUNT_1_BIT;
1952    } else {
1953       builder->samples = create_info->pMultisampleState->rasterizationSamples;
1954
1955       const struct tu_render_pass *pass =
1956          tu_render_pass_from_handle(create_info->renderPass);
1957       const struct tu_subpass *subpass =
1958          &pass->subpasses[create_info->subpass];
1959
1960       builder->use_depth_stencil_attachment =
1961          subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED;
1962
1963       assert(subpass->color_count == 0 ||
1964              !create_info->pColorBlendState ||
1965              subpass->color_count == create_info->pColorBlendState->attachmentCount);
1966       builder->color_attachment_count = subpass->color_count;
1967       for (uint32_t i = 0; i < subpass->color_count; i++) {
1968          const uint32_t a = subpass->color_attachments[i].attachment;
1969          if (a == VK_ATTACHMENT_UNUSED)
1970             continue;
1971
1972          builder->color_attachment_formats[i] = pass->attachments[a].format;
1973          builder->use_color_attachments = true;
1974       }
1975    }
1976 }
1977
1978 static VkResult
1979 tu_graphics_pipeline_create(VkDevice device,
1980                             VkPipelineCache pipelineCache,
1981                             const VkGraphicsPipelineCreateInfo *pCreateInfo,
1982                             const VkAllocationCallbacks *pAllocator,
1983                             VkPipeline *pPipeline)
1984 {
1985    TU_FROM_HANDLE(tu_device, dev, device);
1986    TU_FROM_HANDLE(tu_pipeline_cache, cache, pipelineCache);
1987
1988    struct tu_pipeline_builder builder;
1989    tu_pipeline_builder_init_graphics(&builder, dev, cache,
1990                                      pCreateInfo, pAllocator);
1991
1992    struct tu_pipeline *pipeline = NULL;
1993    VkResult result = tu_pipeline_builder_build(&builder, &pipeline);
1994    tu_pipeline_builder_finish(&builder);
1995
1996    if (result == VK_SUCCESS)
1997       *pPipeline = tu_pipeline_to_handle(pipeline);
1998    else
1999       *pPipeline = VK_NULL_HANDLE;
2000
2001    return result;
2002 }
2003
2004 VkResult
2005 tu_CreateGraphicsPipelines(VkDevice device,
2006                            VkPipelineCache pipelineCache,
2007                            uint32_t count,
2008                            const VkGraphicsPipelineCreateInfo *pCreateInfos,
2009                            const VkAllocationCallbacks *pAllocator,
2010                            VkPipeline *pPipelines)
2011 {
2012    VkResult final_result = VK_SUCCESS;
2013
2014    for (uint32_t i = 0; i < count; i++) {
2015       VkResult result = tu_graphics_pipeline_create(device, pipelineCache,
2016                                                     &pCreateInfos[i], pAllocator,
2017                                                     &pPipelines[i]);
2018
2019       if (result != VK_SUCCESS)
2020          final_result = result;
2021    }
2022
2023    return final_result;
2024 }
2025
2026 static void
2027 tu6_emit_compute_program(struct tu_cs *cs,
2028                          struct tu_shader *shader,
2029                          const struct tu_bo *binary_bo)
2030 {
2031    const struct ir3_shader_variant *v = &shader->variants[0];
2032
2033    tu6_emit_cs_config(cs, shader, v);
2034
2035    /* The compute program is the only one in the pipeline, so 0 offset. */
2036    tu6_emit_shader_object(cs, MESA_SHADER_COMPUTE, v, binary_bo, 0);
2037
2038    tu6_emit_immediates(cs, v, CP_LOAD_STATE6_FRAG, SB6_CS_SHADER);
2039 }
2040
2041 static VkResult
2042 tu_compute_upload_shader(VkDevice device,
2043                          struct tu_pipeline *pipeline,
2044                          struct tu_shader *shader)
2045 {
2046    TU_FROM_HANDLE(tu_device, dev, device);
2047    struct tu_bo *bo = &pipeline->program.binary_bo;
2048    struct ir3_shader_variant *v = &shader->variants[0];
2049
2050    uint32_t shader_size = sizeof(uint32_t) * v->info.sizedwords;
2051    VkResult result =
2052       tu_bo_init_new(dev, bo, shader_size);
2053    if (result != VK_SUCCESS)
2054       return result;
2055
2056    result = tu_bo_map(dev, bo);
2057    if (result != VK_SUCCESS)
2058       return result;
2059
2060    memcpy(bo->map, shader->binary, shader_size);
2061
2062    return VK_SUCCESS;
2063 }
2064
2065
2066 static VkResult
2067 tu_compute_pipeline_create(VkDevice device,
2068                            VkPipelineCache _cache,
2069                            const VkComputePipelineCreateInfo *pCreateInfo,
2070                            const VkAllocationCallbacks *pAllocator,
2071                            VkPipeline *pPipeline)
2072 {
2073    TU_FROM_HANDLE(tu_device, dev, device);
2074    TU_FROM_HANDLE(tu_pipeline_layout, layout, pCreateInfo->layout);
2075    const VkPipelineShaderStageCreateInfo *stage_info = &pCreateInfo->stage;
2076    VkResult result;
2077
2078    struct tu_pipeline *pipeline;
2079
2080    result = tu_pipeline_create(dev, pAllocator, &pipeline);
2081    if (result != VK_SUCCESS)
2082       return result;
2083
2084    pipeline->layout = layout;
2085
2086    struct tu_shader_compile_options options;
2087    tu_shader_compile_options_init(&options, NULL);
2088
2089    struct tu_shader *shader =
2090       tu_shader_create(dev, MESA_SHADER_COMPUTE, stage_info, layout, pAllocator);
2091    if (!shader) {
2092       result = VK_ERROR_OUT_OF_HOST_MEMORY;
2093       goto fail;
2094    }
2095
2096    result = tu_shader_compile(dev, shader, NULL, &options, pAllocator);
2097    if (result != VK_SUCCESS)
2098       return result;
2099
2100    struct ir3_shader_variant *v = &shader->variants[0];
2101
2102    tu_pipeline_set_linkage(&pipeline->program.link[MESA_SHADER_COMPUTE],
2103                            shader, v);
2104
2105    result = tu_compute_upload_shader(device, pipeline, shader);
2106    if (result != VK_SUCCESS)
2107       return result;
2108
2109    for (int i = 0; i < 3; i++)
2110       pipeline->compute.local_size[i] = v->shader->nir->info.cs.local_size[i];
2111
2112    struct tu_cs prog_cs;
2113    tu_cs_begin_sub_stream(dev, &pipeline->cs, 512, &prog_cs);
2114    tu6_emit_compute_program(&prog_cs, shader, &pipeline->program.binary_bo);
2115    pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2116
2117    *pPipeline = tu_pipeline_to_handle(pipeline);
2118    return VK_SUCCESS;
2119
2120 fail:
2121    tu_shader_destroy(dev, shader, pAllocator);
2122    if (result != VK_SUCCESS) {
2123       tu_pipeline_finish(pipeline, dev, pAllocator);
2124       vk_free2(&dev->alloc, pAllocator, pipeline);
2125    }
2126
2127    return result;
2128 }
2129
2130 VkResult
2131 tu_CreateComputePipelines(VkDevice device,
2132                           VkPipelineCache pipelineCache,
2133                           uint32_t count,
2134                           const VkComputePipelineCreateInfo *pCreateInfos,
2135                           const VkAllocationCallbacks *pAllocator,
2136                           VkPipeline *pPipelines)
2137 {
2138    VkResult final_result = VK_SUCCESS;
2139
2140    for (uint32_t i = 0; i < count; i++) {
2141       VkResult result = tu_compute_pipeline_create(device, pipelineCache,
2142                                                    &pCreateInfos[i],
2143                                                    pAllocator, &pPipelines[i]);
2144       if (result != VK_SUCCESS)
2145          final_result = result;
2146    }
2147
2148    return final_result;
2149 }
2150
2151 void
2152 tu_DestroyPipeline(VkDevice _device,
2153                    VkPipeline _pipeline,
2154                    const VkAllocationCallbacks *pAllocator)
2155 {
2156    TU_FROM_HANDLE(tu_device, dev, _device);
2157    TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
2158
2159    if (!_pipeline)
2160       return;
2161
2162    tu_pipeline_finish(pipeline, dev, pAllocator);
2163    vk_free2(&dev->alloc, pAllocator, pipeline);
2164 }