projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
turnip: improve vertex input handling
[mesa.git] / src / freedreno / vulkan / tu_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "ir3/ir3_nir.h"
31 #include "main/menums.h"
32 #include "nir/nir.h"
33 #include "nir/nir_builder.h"
34 #include "spirv/nir_spirv.h"
35 #include "util/debug.h"
36 #include "util/mesa-sha1.h"
37 #include "util/u_atomic.h"
38 #include "vk_format.h"
39 #include "vk_util.h"
40
41 #include "tu_cs.h"
42
43 struct tu_pipeline_builder
44 {
45 struct tu_device *device;
46 struct tu_pipeline_cache *cache;
47 struct tu_pipeline_layout *layout;
48 const VkAllocationCallbacks *alloc;
49 const VkGraphicsPipelineCreateInfo *create_info;
50
51 struct tu_shader *shaders[MESA_SHADER_STAGES];
52 uint32_t shader_offsets[MESA_SHADER_STAGES];
53 uint32_t binning_vs_offset;
54 uint32_t shader_total_size;
55
56 bool rasterizer_discard;
57 /* these states are affectd by rasterizer_discard */
58 VkSampleCountFlagBits samples;
59 bool use_depth_stencil_attachment;
60 bool use_color_attachments;
61 uint32_t color_attachment_count;
62 VkFormat color_attachment_formats[MAX_RTS];
63 };
64
65 static enum tu_dynamic_state_bits
66 tu_dynamic_state_bit(VkDynamicState state)
67 {
68 switch (state) {
69 case VK_DYNAMIC_STATE_VIEWPORT:
70 return TU_DYNAMIC_VIEWPORT;
71 case VK_DYNAMIC_STATE_SCISSOR:
72 return TU_DYNAMIC_SCISSOR;
73 case VK_DYNAMIC_STATE_LINE_WIDTH:
74 return TU_DYNAMIC_LINE_WIDTH;
75 case VK_DYNAMIC_STATE_DEPTH_BIAS:
76 return TU_DYNAMIC_DEPTH_BIAS;
77 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
78 return TU_DYNAMIC_BLEND_CONSTANTS;
79 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
80 return TU_DYNAMIC_DEPTH_BOUNDS;
81 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
82 return TU_DYNAMIC_STENCIL_COMPARE_MASK;
83 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
84 return TU_DYNAMIC_STENCIL_WRITE_MASK;
85 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
86 return TU_DYNAMIC_STENCIL_REFERENCE;
87 default:
88 unreachable("invalid dynamic state");
89 return 0;
90 }
91 }
92
93 static gl_shader_stage
94 tu_shader_stage(VkShaderStageFlagBits stage)
95 {
96 switch (stage) {
97 case VK_SHADER_STAGE_VERTEX_BIT:
98 return MESA_SHADER_VERTEX;
99 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
100 return MESA_SHADER_TESS_CTRL;
101 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
102 return MESA_SHADER_TESS_EVAL;
103 case VK_SHADER_STAGE_GEOMETRY_BIT:
104 return MESA_SHADER_GEOMETRY;
105 case VK_SHADER_STAGE_FRAGMENT_BIT:
106 return MESA_SHADER_FRAGMENT;
107 case VK_SHADER_STAGE_COMPUTE_BIT:
108 return MESA_SHADER_COMPUTE;
109 default:
110 unreachable("invalid VkShaderStageFlagBits");
111 return MESA_SHADER_NONE;
112 }
113 }
114
115 static bool
116 tu_logic_op_reads_dst(VkLogicOp op)
117 {
118 switch (op) {
119 case VK_LOGIC_OP_CLEAR:
120 case VK_LOGIC_OP_COPY:
121 case VK_LOGIC_OP_COPY_INVERTED:
122 case VK_LOGIC_OP_SET:
123 return false;
124 default:
125 return true;
126 }
127 }
128
129 static VkBlendFactor
130 tu_blend_factor_no_dst_alpha(VkBlendFactor factor)
131 {
132 /* treat dst alpha as 1.0 and avoid reading it */
133 switch (factor) {
134 case VK_BLEND_FACTOR_DST_ALPHA:
135 return VK_BLEND_FACTOR_ONE;
136 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
137 return VK_BLEND_FACTOR_ZERO;
138 default:
139 return factor;
140 }
141 }
142
143 static enum pc_di_primtype
144 tu6_primtype(VkPrimitiveTopology topology)
145 {
146 switch (topology) {
147 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
148 return DI_PT_POINTLIST;
149 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
150 return DI_PT_LINELIST;
151 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
152 return DI_PT_LINESTRIP;
153 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
154 return DI_PT_TRILIST;
155 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
156 return DI_PT_TRISTRIP;
157 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
158 return DI_PT_TRIFAN;
159 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
160 return DI_PT_LINE_ADJ;
161 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
162 return DI_PT_LINESTRIP_ADJ;
163 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
164 return DI_PT_TRI_ADJ;
165 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
166 return DI_PT_TRISTRIP_ADJ;
167 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
168 default:
169 unreachable("invalid primitive topology");
170 return DI_PT_NONE;
171 }
172 }
173
174 static enum adreno_compare_func
175 tu6_compare_func(VkCompareOp op)
176 {
177 switch (op) {
178 case VK_COMPARE_OP_NEVER:
179 return FUNC_NEVER;
180 case VK_COMPARE_OP_LESS:
181 return FUNC_LESS;
182 case VK_COMPARE_OP_EQUAL:
183 return FUNC_EQUAL;
184 case VK_COMPARE_OP_LESS_OR_EQUAL:
185 return FUNC_LEQUAL;
186 case VK_COMPARE_OP_GREATER:
187 return FUNC_GREATER;
188 case VK_COMPARE_OP_NOT_EQUAL:
189 return FUNC_NOTEQUAL;
190 case VK_COMPARE_OP_GREATER_OR_EQUAL:
191 return FUNC_GEQUAL;
192 case VK_COMPARE_OP_ALWAYS:
193 return FUNC_ALWAYS;
194 default:
195 unreachable("invalid VkCompareOp");
196 return FUNC_NEVER;
197 }
198 }
199
200 static enum adreno_stencil_op
201 tu6_stencil_op(VkStencilOp op)
202 {
203 switch (op) {
204 case VK_STENCIL_OP_KEEP:
205 return STENCIL_KEEP;
206 case VK_STENCIL_OP_ZERO:
207 return STENCIL_ZERO;
208 case VK_STENCIL_OP_REPLACE:
209 return STENCIL_REPLACE;
210 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
211 return STENCIL_INCR_CLAMP;
212 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
213 return STENCIL_DECR_CLAMP;
214 case VK_STENCIL_OP_INVERT:
215 return STENCIL_INVERT;
216 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
217 return STENCIL_INCR_WRAP;
218 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
219 return STENCIL_DECR_WRAP;
220 default:
221 unreachable("invalid VkStencilOp");
222 return STENCIL_KEEP;
223 }
224 }
225
226 static enum a3xx_rop_code
227 tu6_rop(VkLogicOp op)
228 {
229 switch (op) {
230 case VK_LOGIC_OP_CLEAR:
231 return ROP_CLEAR;
232 case VK_LOGIC_OP_AND:
233 return ROP_AND;
234 case VK_LOGIC_OP_AND_REVERSE:
235 return ROP_AND_REVERSE;
236 case VK_LOGIC_OP_COPY:
237 return ROP_COPY;
238 case VK_LOGIC_OP_AND_INVERTED:
239 return ROP_AND_INVERTED;
240 case VK_LOGIC_OP_NO_OP:
241 return ROP_NOOP;
242 case VK_LOGIC_OP_XOR:
243 return ROP_XOR;
244 case VK_LOGIC_OP_OR:
245 return ROP_OR;
246 case VK_LOGIC_OP_NOR:
247 return ROP_NOR;
248 case VK_LOGIC_OP_EQUIVALENT:
249 return ROP_EQUIV;
250 case VK_LOGIC_OP_INVERT:
251 return ROP_INVERT;
252 case VK_LOGIC_OP_OR_REVERSE:
253 return ROP_OR_REVERSE;
254 case VK_LOGIC_OP_COPY_INVERTED:
255 return ROP_COPY_INVERTED;
256 case VK_LOGIC_OP_OR_INVERTED:
257 return ROP_OR_INVERTED;
258 case VK_LOGIC_OP_NAND:
259 return ROP_NAND;
260 case VK_LOGIC_OP_SET:
261 return ROP_SET;
262 default:
263 unreachable("invalid VkLogicOp");
264 return ROP_NOOP;
265 }
266 }
267
268 static enum adreno_rb_blend_factor
269 tu6_blend_factor(VkBlendFactor factor)
270 {
271 switch (factor) {
272 case VK_BLEND_FACTOR_ZERO:
273 return FACTOR_ZERO;
274 case VK_BLEND_FACTOR_ONE:
275 return FACTOR_ONE;
276 case VK_BLEND_FACTOR_SRC_COLOR:
277 return FACTOR_SRC_COLOR;
278 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
279 return FACTOR_ONE_MINUS_SRC_COLOR;
280 case VK_BLEND_FACTOR_DST_COLOR:
281 return FACTOR_DST_COLOR;
282 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
283 return FACTOR_ONE_MINUS_DST_COLOR;
284 case VK_BLEND_FACTOR_SRC_ALPHA:
285 return FACTOR_SRC_ALPHA;
286 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
287 return FACTOR_ONE_MINUS_SRC_ALPHA;
288 case VK_BLEND_FACTOR_DST_ALPHA:
289 return FACTOR_DST_ALPHA;
290 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
291 return FACTOR_ONE_MINUS_DST_ALPHA;
292 case VK_BLEND_FACTOR_CONSTANT_COLOR:
293 return FACTOR_CONSTANT_COLOR;
294 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
295 return FACTOR_ONE_MINUS_CONSTANT_COLOR;
296 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
297 return FACTOR_CONSTANT_ALPHA;
298 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
299 return FACTOR_ONE_MINUS_CONSTANT_ALPHA;
300 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
301 return FACTOR_SRC_ALPHA_SATURATE;
302 case VK_BLEND_FACTOR_SRC1_COLOR:
303 return FACTOR_SRC1_COLOR;
304 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
305 return FACTOR_ONE_MINUS_SRC1_COLOR;
306 case VK_BLEND_FACTOR_SRC1_ALPHA:
307 return FACTOR_SRC1_ALPHA;
308 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
309 return FACTOR_ONE_MINUS_SRC1_ALPHA;
310 default:
311 unreachable("invalid VkBlendFactor");
312 return FACTOR_ZERO;
313 }
314 }
315
316 static enum a3xx_rb_blend_opcode
317 tu6_blend_op(VkBlendOp op)
318 {
319 switch (op) {
320 case VK_BLEND_OP_ADD:
321 return BLEND_DST_PLUS_SRC;
322 case VK_BLEND_OP_SUBTRACT:
323 return BLEND_SRC_MINUS_DST;
324 case VK_BLEND_OP_REVERSE_SUBTRACT:
325 return BLEND_DST_MINUS_SRC;
326 case VK_BLEND_OP_MIN:
327 return BLEND_MIN_DST_SRC;
328 case VK_BLEND_OP_MAX:
329 return BLEND_MAX_DST_SRC;
330 default:
331 unreachable("invalid VkBlendOp");
332 return BLEND_DST_PLUS_SRC;
333 }
334 }
335
336 static unsigned
337 tu_shader_nibo(const struct tu_shader *shader)
338 {
339 /* Don't use ir3_shader_nibo(), because that would include declared but
340 * unused storage images and SSBOs.
341 */
342 return shader->ssbo_map.num_desc + shader->image_map.num_desc;
343 }
344
345 static void
346 tu6_emit_vs_config(struct tu_cs *cs, struct tu_shader *shader,
347 const struct ir3_shader_variant *vs)
348 {
349 uint32_t sp_vs_ctrl =
350 A6XX_SP_VS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
351 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs->info.max_reg + 1) |
352 A6XX_SP_VS_CTRL_REG0_MERGEDREGS |
353 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs->branchstack);
354 if (vs->need_pixlod)
355 sp_vs_ctrl |= A6XX_SP_VS_CTRL_REG0_PIXLODENABLE;
356 if (vs->need_fine_derivatives)
357 sp_vs_ctrl |= A6XX_SP_VS_CTRL_REG0_DIFF_FINE;
358
359 uint32_t sp_vs_config = A6XX_SP_VS_CONFIG_NTEX(shader->texture_map.num_desc) |
360 A6XX_SP_VS_CONFIG_NSAMP(shader->sampler_map.num_desc);
361 if (vs->instrlen)
362 sp_vs_config |= A6XX_SP_VS_CONFIG_ENABLED;
363
364 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_CTRL_REG0, 1);
365 tu_cs_emit(cs, sp_vs_ctrl);
366
367 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_CONFIG, 2);
368 tu_cs_emit(cs, sp_vs_config);
369 tu_cs_emit(cs, vs->instrlen);
370
371 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_VS_CNTL, 1);
372 tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(vs->constlen, 4)) |
373 A6XX_HLSQ_VS_CNTL_ENABLED);
374 }
375
376 static void
377 tu6_emit_hs_config(struct tu_cs *cs, struct tu_shader *shader,
378 const struct ir3_shader_variant *hs)
379 {
380 uint32_t sp_hs_config = 0;
381 if (hs->instrlen)
382 sp_hs_config |= A6XX_SP_HS_CONFIG_ENABLED;
383
384 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
385 tu_cs_emit(cs, 0);
386
387 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_CONFIG, 2);
388 tu_cs_emit(cs, sp_hs_config);
389 tu_cs_emit(cs, hs->instrlen);
390
391 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_HS_CNTL, 1);
392 tu_cs_emit(cs, A6XX_HLSQ_HS_CNTL_CONSTLEN(align(hs->constlen, 4)));
393 }
394
395 static void
396 tu6_emit_ds_config(struct tu_cs *cs, struct tu_shader *shader,
397 const struct ir3_shader_variant *ds)
398 {
399 uint32_t sp_ds_config = 0;
400 if (ds->instrlen)
401 sp_ds_config |= A6XX_SP_DS_CONFIG_ENABLED;
402
403 tu_cs_emit_pkt4(cs, REG_A6XX_SP_DS_CONFIG, 2);
404 tu_cs_emit(cs, sp_ds_config);
405 tu_cs_emit(cs, ds->instrlen);
406
407 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_DS_CNTL, 1);
408 tu_cs_emit(cs, A6XX_HLSQ_DS_CNTL_CONSTLEN(align(ds->constlen, 4)));
409 }
410
411 static void
412 tu6_emit_gs_config(struct tu_cs *cs, struct tu_shader *shader,
413 const struct ir3_shader_variant *gs)
414 {
415 bool has_gs = gs->type != MESA_SHADER_NONE;
416 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
417 tu_cs_emit(cs, 0);
418
419 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CONFIG, 2);
420 tu_cs_emit(cs, COND(has_gs,
421 A6XX_SP_GS_CONFIG_ENABLED |
422 A6XX_SP_GS_CONFIG_NIBO(ir3_shader_nibo(gs)) |
423 A6XX_SP_GS_CONFIG_NTEX(gs->num_samp) |
424 A6XX_SP_GS_CONFIG_NSAMP(gs->num_samp)));
425 tu_cs_emit(cs, gs->instrlen);
426
427 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_GS_CNTL, 1);
428 tu_cs_emit(cs, COND(has_gs, A6XX_HLSQ_GS_CNTL_ENABLED) |
429 A6XX_HLSQ_GS_CNTL_CONSTLEN(align(gs->constlen, 4)));
430 }
431
432 static void
433 tu6_emit_fs_config(struct tu_cs *cs, struct tu_shader *shader,
434 const struct ir3_shader_variant *fs)
435 {
436 uint32_t sp_fs_ctrl =
437 A6XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) | 0x1000000 |
438 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs->info.max_reg + 1) |
439 A6XX_SP_FS_CTRL_REG0_MERGEDREGS |
440 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs->branchstack);
441 if (fs->total_in > 0)
442 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_VARYING;
443 if (fs->need_pixlod)
444 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_PIXLODENABLE;
445 if (fs->need_fine_derivatives)
446 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_DIFF_FINE;
447
448 uint32_t sp_fs_config = 0;
449 unsigned shader_nibo = 0;
450 if (shader) {
451 shader_nibo = tu_shader_nibo(shader);
452 sp_fs_config = A6XX_SP_FS_CONFIG_NTEX(shader->texture_map.num_desc) |
453 A6XX_SP_FS_CONFIG_NSAMP(shader->sampler_map.num_desc) |
454 A6XX_SP_FS_CONFIG_NIBO(shader_nibo);
455 }
456
457 if (fs->instrlen)
458 sp_fs_config |= A6XX_SP_FS_CONFIG_ENABLED;
459
460 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_CTRL_REG0, 1);
461 tu_cs_emit(cs, sp_fs_ctrl);
462
463 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_CONFIG, 2);
464 tu_cs_emit(cs, sp_fs_config);
465 tu_cs_emit(cs, fs->instrlen);
466
467 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_FS_CNTL, 1);
468 tu_cs_emit(cs, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(fs->constlen, 4)) |
469 A6XX_HLSQ_FS_CNTL_ENABLED);
470
471 tu_cs_emit_pkt4(cs, REG_A6XX_SP_IBO_COUNT, 1);
472 tu_cs_emit(cs, shader_nibo);
473 }
474
475 static void
476 tu6_emit_cs_config(struct tu_cs *cs, const struct tu_shader *shader,
477 const struct ir3_shader_variant *v)
478 {
479 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
480 tu_cs_emit(cs, 0xff);
481
482 unsigned constlen = align(v->constlen, 4);
483 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL, 1);
484 tu_cs_emit(cs, A6XX_HLSQ_CS_CNTL_CONSTLEN(constlen) |
485 A6XX_HLSQ_CS_CNTL_ENABLED);
486
487 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_CONFIG, 2);
488 tu_cs_emit(cs, A6XX_SP_CS_CONFIG_ENABLED |
489 A6XX_SP_CS_CONFIG_NIBO(tu_shader_nibo(shader)) |
490 A6XX_SP_CS_CONFIG_NTEX(shader->texture_map.num_desc) |
491 A6XX_SP_CS_CONFIG_NSAMP(shader->sampler_map.num_desc));
492 tu_cs_emit(cs, v->instrlen);
493
494 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_CTRL_REG0, 1);
495 tu_cs_emit(cs, A6XX_SP_CS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
496 A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(v->info.max_reg + 1) |
497 A6XX_SP_CS_CTRL_REG0_MERGEDREGS |
498 A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(v->branchstack) |
499 COND(v->need_pixlod, A6XX_SP_CS_CTRL_REG0_PIXLODENABLE) |
500 COND(v->need_fine_derivatives, A6XX_SP_CS_CTRL_REG0_DIFF_FINE));
501
502 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_UNKNOWN_A9B1, 1);
503 tu_cs_emit(cs, 0x41);
504
505 uint32_t local_invocation_id =
506 ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
507 uint32_t work_group_id =
508 ir3_find_sysval_regid(v, SYSTEM_VALUE_WORK_GROUP_ID);
509
510 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL_0, 2);
511 tu_cs_emit(cs,
512 A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) |
513 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
514 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
515 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
516 tu_cs_emit(cs, 0x2fc); /* HLSQ_CS_UNKNOWN_B998 */
517
518 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_IBO_COUNT, 1);
519 tu_cs_emit(cs, tu_shader_nibo(shader));
520 }
521
522 static void
523 tu6_emit_vs_system_values(struct tu_cs *cs,
524 const struct ir3_shader_variant *vs,
525 const struct ir3_shader_variant *gs)
526 {
527 const uint32_t vertexid_regid =
528 ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
529 const uint32_t instanceid_regid =
530 ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
531 const uint32_t primitiveid_regid = gs->type != MESA_SHADER_NONE ?
532 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID) :
533 regid(63, 0);
534 const uint32_t gsheader_regid = gs->type != MESA_SHADER_NONE ?
535 ir3_find_sysval_regid(gs, SYSTEM_VALUE_GS_HEADER_IR3) :
536 regid(63, 0);
537
538 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_1, 6);
539 tu_cs_emit(cs, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid) |
540 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid) |
541 A6XX_VFD_CONTROL_1_REGID4PRIMID(primitiveid_regid) |
542 0xfc000000);
543 tu_cs_emit(cs, 0x0000fcfc); /* VFD_CONTROL_2 */
544 tu_cs_emit(cs, 0xfcfcfcfc); /* VFD_CONTROL_3 */
545 tu_cs_emit(cs, 0x000000fc); /* VFD_CONTROL_4 */
546 tu_cs_emit(cs, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gsheader_regid) |
547 0xfc00); /* VFD_CONTROL_5 */
548 tu_cs_emit(cs, 0x00000000); /* VFD_CONTROL_6 */
549 }
550
551 /* Add any missing varyings needed for stream-out. Otherwise varyings not
552 * used by fragment shader will be stripped out.
553 */
554 static void
555 tu6_link_streamout(struct ir3_shader_linkage *l,
556 const struct ir3_shader_variant *v)
557 {
558 const struct ir3_stream_output_info *info = &v->shader->stream_output;
559
560 /*
561 * First, any stream-out varyings not already in linkage map (ie. also
562 * consumed by frag shader) need to be added:
563 */
564 for (unsigned i = 0; i < info->num_outputs; i++) {
565 const struct ir3_stream_output *out = &info->output[i];
566 unsigned compmask =
567 (1 << (out->num_components + out->start_component)) - 1;
568 unsigned k = out->register_index;
569 unsigned idx, nextloc = 0;
570
571 /* psize/pos need to be the last entries in linkage map, and will
572 * get added link_stream_out, so skip over them:
573 */
574 if (v->outputs[k].slot == VARYING_SLOT_PSIZ ||
575 v->outputs[k].slot == VARYING_SLOT_POS)
576 continue;
577
578 for (idx = 0; idx < l->cnt; idx++) {
579 if (l->var[idx].regid == v->outputs[k].regid)
580 break;
581 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
582 }
583
584 /* add if not already in linkage map: */
585 if (idx == l->cnt)
586 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
587
588 /* expand component-mask if needed, ie streaming out all components
589 * but frag shader doesn't consume all components:
590 */
591 if (compmask & ~l->var[idx].compmask) {
592 l->var[idx].compmask |= compmask;
593 l->max_loc = MAX2(l->max_loc, l->var[idx].loc +
594 util_last_bit(l->var[idx].compmask));
595 }
596 }
597 }
598
599 static void
600 tu6_setup_streamout(const struct ir3_shader_variant *v,
601 struct ir3_shader_linkage *l, struct tu_streamout_state *tf)
602 {
603 const struct ir3_stream_output_info *info = &v->shader->stream_output;
604
605 memset(tf, 0, sizeof(*tf));
606
607 tf->prog_count = align(l->max_loc, 2) / 2;
608
609 debug_assert(tf->prog_count < ARRAY_SIZE(tf->prog));
610
611 /* set stride info to the streamout state */
612 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++)
613 tf->stride[i] = info->stride[i];
614
615 for (unsigned i = 0; i < info->num_outputs; i++) {
616 const struct ir3_stream_output *out = &info->output[i];
617 unsigned k = out->register_index;
618 unsigned idx;
619
620 tf->ncomp[out->output_buffer] += out->num_components;
621
622 /* linkage map sorted by order frag shader wants things, so
623 * a bit less ideal here..
624 */
625 for (idx = 0; idx < l->cnt; idx++)
626 if (l->var[idx].regid == v->outputs[k].regid)
627 break;
628
629 debug_assert(idx < l->cnt);
630
631 for (unsigned j = 0; j < out->num_components; j++) {
632 unsigned c = j + out->start_component;
633 unsigned loc = l->var[idx].loc + c;
634 unsigned off = j + out->dst_offset; /* in dwords */
635
636 if (loc & 1) {
637 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
638 A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
639 A6XX_VPC_SO_PROG_B_OFF(off * 4);
640 } else {
641 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
642 A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
643 A6XX_VPC_SO_PROG_A_OFF(off * 4);
644 }
645 }
646 }
647
648 tf->vpc_so_buf_cntl = A6XX_VPC_SO_BUF_CNTL_ENABLE |
649 COND(tf->ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
650 COND(tf->ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
651 COND(tf->ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
652 COND(tf->ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3);
653 }
654
655 static void
656 tu6_emit_const(struct tu_cs *cs, uint32_t opcode, uint32_t base,
657 enum a6xx_state_block block, uint32_t offset,
658 uint32_t size, uint32_t *dwords) {
659 assert(size % 4 == 0);
660
661 tu_cs_emit_pkt7(cs, opcode, 3 + size);
662 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
663 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
664 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
665 CP_LOAD_STATE6_0_STATE_BLOCK(block) |
666 CP_LOAD_STATE6_0_NUM_UNIT(size / 4));
667
668 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
669 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
670 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
671
672 tu_cs_emit_array(cs, dwords, size);
673 }
674
675 static void
676 tu6_emit_link_map(struct tu_cs *cs,
677 const struct ir3_shader_variant *producer,
678 const struct ir3_shader_variant *consumer) {
679 const struct ir3_const_state *const_state = &consumer->shader->const_state;
680 uint32_t base = const_state->offsets.primitive_map;
681 uint32_t patch_locs[MAX_VARYING] = { }, num_loc;
682 num_loc = ir3_link_geometry_stages(producer, consumer, patch_locs);
683 int size = DIV_ROUND_UP(num_loc, 4);
684
685 size = (MIN2(size + base, consumer->constlen) - base) * 4;
686
687 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, base, SB6_GS_SHADER, 0, size,
688 patch_locs);
689 }
690
691 static uint16_t
692 gl_primitive_to_tess(uint16_t primitive) {
693 switch (primitive) {
694 case GL_POINTS:
695 return TESS_POINTS;
696 case GL_LINE_STRIP:
697 return TESS_LINES;
698 case GL_TRIANGLE_STRIP:
699 return TESS_CW_TRIS;
700 default:
701 unreachable("");
702 }
703 }
704
705 static void
706 tu6_emit_vpc(struct tu_cs *cs,
707 const struct ir3_shader_variant *vs,
708 const struct ir3_shader_variant *gs,
709 const struct ir3_shader_variant *fs,
710 bool binning_pass,
711 struct tu_streamout_state *tf)
712 {
713 bool has_gs = gs->type != MESA_SHADER_NONE;
714 const struct ir3_shader_variant *last_shader = has_gs ? gs : vs;
715 struct ir3_shader_linkage linkage = { 0 };
716 ir3_link_shaders(&linkage, last_shader, fs);
717
718 if (last_shader->shader->stream_output.num_outputs)
719 tu6_link_streamout(&linkage, last_shader);
720
721 BITSET_DECLARE(vpc_var_enables, 128) = { 0 };
722 for (uint32_t i = 0; i < linkage.cnt; i++) {
723 const uint32_t comp_count = util_last_bit(linkage.var[i].compmask);
724 for (uint32_t j = 0; j < comp_count; j++)
725 BITSET_SET(vpc_var_enables, linkage.var[i].loc + j);
726 }
727
728 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VAR_DISABLE(0), 4);
729 tu_cs_emit(cs, ~vpc_var_enables[0]);
730 tu_cs_emit(cs, ~vpc_var_enables[1]);
731 tu_cs_emit(cs, ~vpc_var_enables[2]);
732 tu_cs_emit(cs, ~vpc_var_enables[3]);
733
734 /* a6xx finds position/pointsize at the end */
735 const uint32_t position_regid =
736 ir3_find_output_regid(last_shader, VARYING_SLOT_POS);
737 const uint32_t pointsize_regid =
738 ir3_find_output_regid(last_shader, VARYING_SLOT_PSIZ);
739 const uint32_t layer_regid = has_gs ?
740 ir3_find_output_regid(gs, VARYING_SLOT_LAYER) : regid(63, 0);
741
742 uint32_t pointsize_loc = 0xff, position_loc = 0xff, layer_loc = 0xff;
743 if (layer_regid != regid(63, 0)) {
744 layer_loc = linkage.max_loc;
745 ir3_link_add(&linkage, layer_regid, 0x1, linkage.max_loc);
746 }
747 if (position_regid != regid(63, 0)) {
748 position_loc = linkage.max_loc;
749 ir3_link_add(&linkage, position_regid, 0xf, linkage.max_loc);
750 }
751 if (pointsize_regid != regid(63, 0)) {
752 pointsize_loc = linkage.max_loc;
753 ir3_link_add(&linkage, pointsize_regid, 0x1, linkage.max_loc);
754 }
755
756 if (last_shader->shader->stream_output.num_outputs)
757 tu6_setup_streamout(last_shader, &linkage, tf);
758
759 /* map outputs of the last shader to VPC */
760 assert(linkage.cnt <= 32);
761 const uint32_t sp_out_count = DIV_ROUND_UP(linkage.cnt, 2);
762 const uint32_t sp_vpc_dst_count = DIV_ROUND_UP(linkage.cnt, 4);
763 uint32_t sp_out[16];
764 uint32_t sp_vpc_dst[8];
765 for (uint32_t i = 0; i < linkage.cnt; i++) {
766 ((uint16_t *) sp_out)[i] =
767 A6XX_SP_VS_OUT_REG_A_REGID(linkage.var[i].regid) |
768 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage.var[i].compmask);
769 ((uint8_t *) sp_vpc_dst)[i] =
770 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage.var[i].loc);
771 }
772
773 if (has_gs)
774 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_OUT_REG(0), sp_out_count);
775 else
776 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_OUT_REG(0), sp_out_count);
777 tu_cs_emit_array(cs, sp_out, sp_out_count);
778
779 if (has_gs)
780 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_VPC_DST_REG(0), sp_vpc_dst_count);
781 else
782 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_VPC_DST_REG(0), sp_vpc_dst_count);
783 tu_cs_emit_array(cs, sp_vpc_dst, sp_vpc_dst_count);
784
785 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_CNTL_0, 1);
786 tu_cs_emit(cs, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs->total_in) |
787 (fs->total_in > 0 ? A6XX_VPC_CNTL_0_VARYING : 0) |
788 0xff00ff00);
789
790 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK, 1);
791 tu_cs_emit(cs, A6XX_VPC_PACK_POSITIONLOC(position_loc) |
792 A6XX_VPC_PACK_PSIZELOC(pointsize_loc) |
793 A6XX_VPC_PACK_STRIDE_IN_VPC(linkage.max_loc));
794
795 if (has_gs) {
796 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CTRL_REG0, 1);
797 tu_cs_emit(cs, A6XX_SP_GS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
798 A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(gs->info.max_reg + 1) |
799 A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(gs->branchstack) |
800 COND(gs->need_pixlod, A6XX_SP_GS_CTRL_REG0_PIXLODENABLE));
801
802 tu6_emit_link_map(cs, vs, gs);
803
804 uint32_t primitive_regid =
805 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID);
806 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK_GS, 1);
807 tu_cs_emit(cs, A6XX_VPC_PACK_GS_POSITIONLOC(position_loc) |
808 A6XX_VPC_PACK_GS_PSIZELOC(pointsize_loc) |
809 A6XX_VPC_PACK_GS_STRIDE_IN_VPC(linkage.max_loc));
810
811 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9105, 1);
812 tu_cs_emit(cs, A6XX_VPC_UNKNOWN_9105_LAYERLOC(layer_loc) | 0xff00);
813
814 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_809C, 1);
815 tu_cs_emit(cs, CONDREG(layer_regid,
816 A6XX_GRAS_UNKNOWN_809C_GS_WRITES_LAYER));
817
818 uint32_t flags_regid = ir3_find_output_regid(gs,
819 VARYING_SLOT_GS_VERTEX_FLAGS_IR3);
820
821 tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL_GS, 1);
822 tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT(linkage.cnt) |
823 A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID(flags_regid));
824
825 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_2, 1);
826 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC(linkage.max_loc) |
827 CONDREG(pointsize_regid, A6XX_PC_PRIMITIVE_CNTL_2_PSIZE) |
828 CONDREG(layer_regid, A6XX_PC_PRIMITIVE_CNTL_2_LAYER) |
829 CONDREG(primitive_regid, A6XX_PC_PRIMITIVE_CNTL_2_PRIMITIVE_ID));
830
831 uint32_t vertices_out = gs->shader->nir->info.gs.vertices_out - 1;
832 uint16_t output =
833 gl_primitive_to_tess(gs->shader->nir->info.gs.output_primitive);
834 uint32_t invocations = gs->shader->nir->info.gs.invocations - 1;
835 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_5, 1);
836 tu_cs_emit(cs,
837 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(vertices_out) |
838 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output) |
839 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(invocations));
840
841 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_3, 1);
842 tu_cs_emit(cs, 0);
843
844 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8003, 1);
845 tu_cs_emit(cs, 0);
846
847 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9100, 1);
848 tu_cs_emit(cs, 0xff);
849
850 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9102, 1);
851 tu_cs_emit(cs, 0xffff00);
852
853 /* Size of per-primitive alloction in ldlw memory in vec4s. */
854 uint32_t vec4_size =
855 gs->shader->nir->info.gs.vertices_in *
856 DIV_ROUND_UP(vs->shader->output_size, 4);
857 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
858 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size));
859
860 tu_cs_emit_pkt4(cs, REG_A6XX_PC_UNKNOWN_9B07, 1);
861 tu_cs_emit(cs, 0);
862
863 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
864 tu_cs_emit(cs, vs->shader->output_size);
865 }
866
867 tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
868 tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage.cnt));
869
870 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
871 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage.max_loc) |
872 (last_shader->writes_psize ? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE : 0));
873 }
874
875 static int
876 tu6_vpc_varying_mode(const struct ir3_shader_variant *fs,
877 uint32_t index,
878 uint8_t *interp_mode,
879 uint8_t *ps_repl_mode)
880 {
881 enum
882 {
883 INTERP_SMOOTH = 0,
884 INTERP_FLAT = 1,
885 INTERP_ZERO = 2,
886 INTERP_ONE = 3,
887 };
888 enum
889 {
890 PS_REPL_NONE = 0,
891 PS_REPL_S = 1,
892 PS_REPL_T = 2,
893 PS_REPL_ONE_MINUS_T = 3,
894 };
895
896 const uint32_t compmask = fs->inputs[index].compmask;
897
898 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
899 * fourth component occupy three consecutive varying slots
900 */
901 int shift = 0;
902 *interp_mode = 0;
903 *ps_repl_mode = 0;
904 if (fs->inputs[index].slot == VARYING_SLOT_PNTC) {
905 if (compmask & 0x1) {
906 *ps_repl_mode |= PS_REPL_S << shift;
907 shift += 2;
908 }
909 if (compmask & 0x2) {
910 *ps_repl_mode |= PS_REPL_T << shift;
911 shift += 2;
912 }
913 if (compmask & 0x4) {
914 *interp_mode |= INTERP_ZERO << shift;
915 shift += 2;
916 }
917 if (compmask & 0x8) {
918 *interp_mode |= INTERP_ONE << 6;
919 shift += 2;
920 }
921 } else if ((fs->inputs[index].interpolate == INTERP_MODE_FLAT) ||
922 fs->inputs[index].rasterflat) {
923 for (int i = 0; i < 4; i++) {
924 if (compmask & (1 << i)) {
925 *interp_mode |= INTERP_FLAT << shift;
926 shift += 2;
927 }
928 }
929 }
930
931 return shift;
932 }
933
934 static void
935 tu6_emit_vpc_varying_modes(struct tu_cs *cs,
936 const struct ir3_shader_variant *fs,
937 bool binning_pass)
938 {
939 uint32_t interp_modes[8] = { 0 };
940 uint32_t ps_repl_modes[8] = { 0 };
941
942 if (!binning_pass) {
943 for (int i = -1;
944 (i = ir3_next_varying(fs, i)) < (int) fs->inputs_count;) {
945
946 /* get the mode for input i */
947 uint8_t interp_mode;
948 uint8_t ps_repl_mode;
949 const int bits =
950 tu6_vpc_varying_mode(fs, i, &interp_mode, &ps_repl_mode);
951
952 /* OR the mode into the array */
953 const uint32_t inloc = fs->inputs[i].inloc * 2;
954 uint32_t n = inloc / 32;
955 uint32_t shift = inloc % 32;
956 interp_modes[n] |= interp_mode << shift;
957 ps_repl_modes[n] |= ps_repl_mode << shift;
958 if (shift + bits > 32) {
959 n++;
960 shift = 32 - shift;
961
962 interp_modes[n] |= interp_mode >> shift;
963 ps_repl_modes[n] |= ps_repl_mode >> shift;
964 }
965 }
966 }
967
968 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
969 tu_cs_emit_array(cs, interp_modes, 8);
970
971 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
972 tu_cs_emit_array(cs, ps_repl_modes, 8);
973 }
974
975 static void
976 tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
977 {
978 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
979 uint32_t ij_pix_regid, ij_samp_regid, ij_cent_regid, ij_size_regid;
980 uint32_t smask_in_regid;
981
982 bool sample_shading = fs->per_samp; /* TODO | key->sample_shading; */
983 bool enable_varyings = fs->total_in > 0;
984
985 samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
986 smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
987 face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
988 coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
989 zwcoord_regid = VALIDREG(coord_regid) ? coord_regid + 2 : regid(63, 0);
990 ij_pix_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
991 ij_samp_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE);
992 ij_cent_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID);
993 ij_size_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE);
994
995 if (fs->num_sampler_prefetch > 0) {
996 assert(VALIDREG(ij_pix_regid));
997 /* also, it seems like ij_pix is *required* to be r0.x */
998 assert(ij_pix_regid == regid(0, 0));
999 }
1000
1001 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
1002 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
1003 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
1004 0x7000); // XXX);
1005 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
1006 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
1007 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch->src) |
1008 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch->samp_id) |
1009 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch->tex_id) |
1010 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch->dst) |
1011 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch->wrmask) |
1012 COND(prefetch->half_precision, A6XX_SP_FS_PREFETCH_CMD_HALF) |
1013 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch->cmd));
1014 }
1015
1016 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
1017 tu_cs_emit(cs, 0x7);
1018 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
1019 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
1020 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
1021 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid));
1022 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid) |
1023 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid) |
1024 0xfc00fc00);
1025 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
1026 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
1027 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid) |
1028 0x0000fc00);
1029 tu_cs_emit(cs, 0xfc);
1030
1031 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
1032 tu_cs_emit(cs, enable_varyings ? 3 : 1);
1033
1034 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
1035 tu_cs_emit(cs, 0xff); /* XXX */
1036
1037 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CNTL, 1);
1038 tu_cs_emit(cs,
1039 CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_VARYING) |
1040 CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_CENTROID) |
1041 CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
1042 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
1043 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
1044 COND(fs->frag_coord,
1045 A6XX_GRAS_CNTL_SIZE |
1046 A6XX_GRAS_CNTL_XCOORD |
1047 A6XX_GRAS_CNTL_YCOORD |
1048 A6XX_GRAS_CNTL_ZCOORD |
1049 A6XX_GRAS_CNTL_WCOORD) |
1050 COND(fs->frag_face, A6XX_GRAS_CNTL_SIZE));
1051
1052 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CONTROL0, 2);
1053 tu_cs_emit(cs,
1054 CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_VARYING) |
1055 CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_CENTROID) |
1056 CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING) |
1057 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
1058 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
1059 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
1060 COND(fs->frag_coord,
1061 A6XX_RB_RENDER_CONTROL0_SIZE |
1062 A6XX_RB_RENDER_CONTROL0_XCOORD |
1063 A6XX_RB_RENDER_CONTROL0_YCOORD |
1064 A6XX_RB_RENDER_CONTROL0_ZCOORD |
1065 A6XX_RB_RENDER_CONTROL0_WCOORD) |
1066 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE));
1067 tu_cs_emit(cs,
1068 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
1069 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
1070 CONDREG(ij_size_regid, A6XX_RB_RENDER_CONTROL1_SIZE) |
1071 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
1072
1073 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CNTL, 1);
1074 tu_cs_emit(cs, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
1075
1076 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8101, 1);
1077 tu_cs_emit(cs, COND(sample_shading, 0x6)); // XXX
1078
1079 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
1080 tu_cs_emit(cs, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
1081 }
1082
1083 static void
1084 tu6_emit_fs_outputs(struct tu_cs *cs,
1085 const struct ir3_shader_variant *fs,
1086 uint32_t mrt_count)
1087 {
1088 uint32_t smask_regid, posz_regid;
1089
1090 posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
1091 smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
1092
1093 uint32_t fragdata_regid[8];
1094 if (fs->color0_mrt) {
1095 fragdata_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
1096 for (uint32_t i = 1; i < ARRAY_SIZE(fragdata_regid); i++)
1097 fragdata_regid[i] = fragdata_regid[0];
1098 } else {
1099 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++)
1100 fragdata_regid[i] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0 + i);
1101 }
1102
1103 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_CNTL0, 2);
1104 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
1105 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
1106 0xfc000000);
1107 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count));
1108
1109 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
1110 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++) {
1111 // TODO we could have a mix of half and full precision outputs,
1112 // we really need to figure out half-precision from IR3_REG_HALF
1113 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid[i]) |
1114 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION : 0));
1115 }
1116
1117 tu_cs_emit_pkt4(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
1118 tu_cs_emit(cs, COND(fs->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
1119 COND(fs->writes_smask, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK));
1120 tu_cs_emit(cs, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count));
1121
1122 uint32_t gras_su_depth_plane_cntl = 0;
1123 uint32_t rb_depth_plane_cntl = 0;
1124 if (fs->no_earlyz || fs->writes_pos) {
1125 gras_su_depth_plane_cntl |= A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
1126 rb_depth_plane_cntl |= A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
1127 }
1128
1129 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
1130 tu_cs_emit(cs, gras_su_depth_plane_cntl);
1131
1132 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
1133 tu_cs_emit(cs, rb_depth_plane_cntl);
1134 }
1135
1136 static void
1137 tu6_emit_shader_object(struct tu_cs *cs,
1138 gl_shader_stage stage,
1139 const struct ir3_shader_variant *variant,
1140 const struct tu_bo *binary_bo,
1141 uint32_t binary_offset)
1142 {
1143 uint16_t reg;
1144 uint8_t opcode;
1145 enum a6xx_state_block sb;
1146 switch (stage) {
1147 case MESA_SHADER_VERTEX:
1148 reg = REG_A6XX_SP_VS_OBJ_START_LO;
1149 opcode = CP_LOAD_STATE6_GEOM;
1150 sb = SB6_VS_SHADER;
1151 break;
1152 case MESA_SHADER_TESS_CTRL:
1153 reg = REG_A6XX_SP_HS_OBJ_START_LO;
1154 opcode = CP_LOAD_STATE6_GEOM;
1155 sb = SB6_HS_SHADER;
1156 break;
1157 case MESA_SHADER_TESS_EVAL:
1158 reg = REG_A6XX_SP_DS_OBJ_START_LO;
1159 opcode = CP_LOAD_STATE6_GEOM;
1160 sb = SB6_DS_SHADER;
1161 break;
1162 case MESA_SHADER_GEOMETRY:
1163 reg = REG_A6XX_SP_GS_OBJ_START_LO;
1164 opcode = CP_LOAD_STATE6_GEOM;
1165 sb = SB6_GS_SHADER;
1166 break;
1167 case MESA_SHADER_FRAGMENT:
1168 reg = REG_A6XX_SP_FS_OBJ_START_LO;
1169 opcode = CP_LOAD_STATE6_FRAG;
1170 sb = SB6_FS_SHADER;
1171 break;
1172 case MESA_SHADER_COMPUTE:
1173 reg = REG_A6XX_SP_CS_OBJ_START_LO;
1174 opcode = CP_LOAD_STATE6_FRAG;
1175 sb = SB6_CS_SHADER;
1176 break;
1177 default:
1178 unreachable("invalid gl_shader_stage");
1179 opcode = CP_LOAD_STATE6_GEOM;
1180 sb = SB6_VS_SHADER;
1181 break;
1182 }
1183
1184 if (!variant->instrlen) {
1185 tu_cs_emit_pkt4(cs, reg, 2);
1186 tu_cs_emit_qw(cs, 0);
1187 return;
1188 }
1189
1190 assert(variant->type == stage);
1191
1192 const uint64_t binary_iova = binary_bo->iova + binary_offset;
1193 assert((binary_iova & 0xf) == 0);
1194 /* note: it looks like HW might try to read a few instructions beyond the instrlen size
1195 * of the shader. this could be a potential source of problems at some point
1196 * possibly this doesn't happen if shader iova is aligned enough (to 4k for example)
1197 */
1198
1199 tu_cs_emit_pkt4(cs, reg, 2);
1200 tu_cs_emit_qw(cs, binary_iova);
1201
1202 /* always indirect */
1203 const bool indirect = true;
1204 if (indirect) {
1205 tu_cs_emit_pkt7(cs, opcode, 3);
1206 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
1207 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
1208 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
1209 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
1210 CP_LOAD_STATE6_0_NUM_UNIT(variant->instrlen));
1211 tu_cs_emit_qw(cs, binary_iova);
1212 } else {
1213 const void *binary = binary_bo->map + binary_offset;
1214
1215 tu_cs_emit_pkt7(cs, opcode, 3 + variant->info.sizedwords);
1216 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
1217 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
1218 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
1219 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
1220 CP_LOAD_STATE6_0_NUM_UNIT(variant->instrlen));
1221 tu_cs_emit_qw(cs, 0);
1222 tu_cs_emit_array(cs, binary, variant->info.sizedwords);
1223 }
1224 }
1225
1226 static void
1227 tu6_emit_immediates(struct tu_cs *cs, const struct ir3_shader_variant *v,
1228 uint32_t opcode, enum a6xx_state_block block)
1229 {
1230 /* dummy variant */
1231 if (!v->shader)
1232 return;
1233
1234 const struct ir3_const_state *const_state = &v->shader->const_state;
1235 uint32_t base = const_state->offsets.immediate;
1236 int size = const_state->immediates_count;
1237
1238 /* truncate size to avoid writing constants that shader
1239 * does not use:
1240 */
1241 size = MIN2(size + base, v->constlen) - base;
1242
1243 if (size <= 0)
1244 return;
1245
1246 tu_cs_emit_pkt7(cs, opcode, 3 + size * 4);
1247 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
1248 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
1249 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
1250 CP_LOAD_STATE6_0_STATE_BLOCK(block) |
1251 CP_LOAD_STATE6_0_NUM_UNIT(size));
1252 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
1253 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
1254
1255 for (unsigned i = 0; i < size; i++) {
1256 tu_cs_emit(cs, const_state->immediates[i].val[0]);
1257 tu_cs_emit(cs, const_state->immediates[i].val[1]);
1258 tu_cs_emit(cs, const_state->immediates[i].val[2]);
1259 tu_cs_emit(cs, const_state->immediates[i].val[3]);
1260 }
1261 }
1262
1263 static void
1264 tu6_emit_geometry_consts(struct tu_cs *cs,
1265 const struct ir3_shader_variant *vs,
1266 const struct ir3_shader_variant *gs) {
1267 unsigned num_vertices = gs->shader->nir->info.gs.vertices_in;
1268
1269 uint32_t params[4] = {
1270 vs->shader->output_size * num_vertices * 4, /* primitive stride */
1271 vs->shader->output_size * 4, /* vertex stride */
1272 0,
1273 0,
1274 };
1275 uint32_t vs_base = vs->shader->const_state.offsets.primitive_param;
1276 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, vs_base, SB6_VS_SHADER, 0,
1277 ARRAY_SIZE(params), params);
1278
1279 uint32_t gs_base = gs->shader->const_state.offsets.primitive_param;
1280 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, gs_base, SB6_GS_SHADER, 0,
1281 ARRAY_SIZE(params), params);
1282 }
1283
1284 static void
1285 tu6_emit_program(struct tu_cs *cs,
1286 const struct tu_pipeline_builder *builder,
1287 const struct tu_bo *binary_bo,
1288 bool binning_pass,
1289 struct tu_streamout_state *tf)
1290 {
1291 static const struct ir3_shader_variant dummy_variant = {
1292 .type = MESA_SHADER_NONE
1293 };
1294 assert(builder->shaders[MESA_SHADER_VERTEX]);
1295 const struct ir3_shader_variant *vs =
1296 &builder->shaders[MESA_SHADER_VERTEX]->variants[0];
1297 const struct ir3_shader_variant *hs =
1298 builder->shaders[MESA_SHADER_TESS_CTRL]
1299 ? &builder->shaders[MESA_SHADER_TESS_CTRL]->variants[0]
1300 : &dummy_variant;
1301 const struct ir3_shader_variant *ds =
1302 builder->shaders[MESA_SHADER_TESS_EVAL]
1303 ? &builder->shaders[MESA_SHADER_TESS_EVAL]->variants[0]
1304 : &dummy_variant;
1305 const struct ir3_shader_variant *gs =
1306 builder->shaders[MESA_SHADER_GEOMETRY]
1307 ? &builder->shaders[MESA_SHADER_GEOMETRY]->variants[0]
1308 : &dummy_variant;
1309 const struct ir3_shader_variant *fs =
1310 builder->shaders[MESA_SHADER_FRAGMENT]
1311 ? &builder->shaders[MESA_SHADER_FRAGMENT]->variants[0]
1312 : &dummy_variant;
1313 bool has_gs = gs->type != MESA_SHADER_NONE;
1314
1315 if (binning_pass) {
1316 /* if we have streamout, use full VS in binning pass, as the
1317 * binning pass VS will have outputs on other than position/psize
1318 * stripped out:
1319 */
1320 if (vs->shader->stream_output.num_outputs == 0)
1321 vs = &builder->shaders[MESA_SHADER_VERTEX]->variants[1];
1322 fs = &dummy_variant;
1323 }
1324
1325 tu6_emit_vs_config(cs, builder->shaders[MESA_SHADER_VERTEX], vs);
1326 tu6_emit_hs_config(cs, builder->shaders[MESA_SHADER_TESS_CTRL], hs);
1327 tu6_emit_ds_config(cs, builder->shaders[MESA_SHADER_TESS_EVAL], ds);
1328 tu6_emit_gs_config(cs, builder->shaders[MESA_SHADER_GEOMETRY], gs);
1329 tu6_emit_fs_config(cs, builder->shaders[MESA_SHADER_FRAGMENT], fs);
1330
1331 tu6_emit_vs_system_values(cs, vs, gs);
1332 tu6_emit_vpc(cs, vs, gs, fs, binning_pass, tf);
1333 tu6_emit_vpc_varying_modes(cs, fs, binning_pass);
1334 tu6_emit_fs_inputs(cs, fs);
1335 tu6_emit_fs_outputs(cs, fs, builder->color_attachment_count);
1336
1337 tu6_emit_shader_object(cs, MESA_SHADER_VERTEX, vs, binary_bo,
1338 binning_pass ? builder->binning_vs_offset : builder->shader_offsets[MESA_SHADER_VERTEX]);
1339 if (has_gs)
1340 tu6_emit_shader_object(cs, MESA_SHADER_GEOMETRY, gs, binary_bo,
1341 builder->shader_offsets[MESA_SHADER_GEOMETRY]);
1342 tu6_emit_shader_object(cs, MESA_SHADER_FRAGMENT, fs, binary_bo,
1343 builder->shader_offsets[MESA_SHADER_FRAGMENT]);
1344
1345 tu6_emit_immediates(cs, vs, CP_LOAD_STATE6_GEOM, SB6_VS_SHADER);
1346 if (has_gs) {
1347 tu6_emit_immediates(cs, gs, CP_LOAD_STATE6_GEOM, SB6_GS_SHADER);
1348 tu6_emit_geometry_consts(cs, vs, gs);
1349 }
1350 if (!binning_pass)
1351 tu6_emit_immediates(cs, fs, CP_LOAD_STATE6_FRAG, SB6_FS_SHADER);
1352 }
1353
1354 static void
1355 tu6_emit_vertex_input(struct tu_cs *cs,
1356 const struct ir3_shader_variant *vs,
1357 const VkPipelineVertexInputStateCreateInfo *info,
1358 uint8_t bindings[MAX_VERTEX_ATTRIBS],
1359 uint32_t *count)
1360 {
1361 uint32_t vfd_fetch_idx = 0;
1362 uint32_t vfd_decode_idx = 0;
1363 uint32_t binding_instanced = 0; /* bitmask of instanced bindings */
1364
1365 for (uint32_t i = 0; i < info->vertexBindingDescriptionCount; i++) {
1366 const VkVertexInputBindingDescription *binding =
1367 &info->pVertexBindingDescriptions[i];
1368
1369 tu_cs_emit_regs(cs,
1370 A6XX_VFD_FETCH_STRIDE(vfd_fetch_idx, binding->stride));
1371
1372 if (binding->inputRate == VK_VERTEX_INPUT_RATE_INSTANCE)
1373 binding_instanced |= 1 << binding->binding;
1374
1375 bindings[vfd_fetch_idx] = binding->binding;
1376 vfd_fetch_idx++;
1377 }
1378
1379 /* TODO: emit all VFD_DECODE/VFD_DEST_CNTL in same (two) pkt4 */
1380
1381 for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
1382 const VkVertexInputAttributeDescription *attr =
1383 &info->pVertexAttributeDescriptions[i];
1384 uint32_t binding_idx, input_idx;
1385
1386 for (binding_idx = 0; binding_idx < vfd_fetch_idx; binding_idx++) {
1387 if (bindings[binding_idx] == attr->binding)
1388 break;
1389 }
1390 assert(binding_idx < vfd_fetch_idx);
1391
1392 for (input_idx = 0; input_idx < vs->inputs_count; input_idx++) {
1393 if ((vs->inputs[input_idx].slot - VERT_ATTRIB_GENERIC0) == attr->location)
1394 break;
1395 }
1396
1397 /* attribute not used, skip it */
1398 if (input_idx == vs->inputs_count)
1399 continue;
1400
1401 const struct tu_native_format format = tu6_format_vtx(attr->format);
1402 tu_cs_emit_regs(cs,
1403 A6XX_VFD_DECODE_INSTR(vfd_decode_idx,
1404 .idx = binding_idx,
1405 .offset = attr->offset,
1406 .instanced = binding_instanced & (1 << attr->binding),
1407 .format = format.fmt,
1408 .swap = format.swap,
1409 .unk30 = 1,
1410 ._float = !vk_format_is_int(attr->format)),
1411 A6XX_VFD_DECODE_STEP_RATE(vfd_decode_idx, 1));
1412
1413 tu_cs_emit_regs(cs,
1414 A6XX_VFD_DEST_CNTL_INSTR(vfd_decode_idx,
1415 .writemask = vs->inputs[input_idx].compmask,
1416 .regid = vs->inputs[input_idx].regid));
1417
1418 vfd_decode_idx++;
1419 }
1420
1421 tu_cs_emit_regs(cs,
1422 A6XX_VFD_CONTROL_0(
1423 .fetch_cnt = vfd_fetch_idx,
1424 .decode_cnt = vfd_decode_idx));
1425
1426 *count = vfd_fetch_idx;
1427 }
1428
1429 static uint32_t
1430 tu6_guardband_adj(uint32_t v)
1431 {
1432 if (v > 256)
1433 return (uint32_t)(511.0 - 65.0 * (log2(v) - 8.0));
1434 else
1435 return 511;
1436 }
1437
1438 void
1439 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport)
1440 {
1441 float offsets[3];
1442 float scales[3];
1443 scales[0] = viewport->width / 2.0f;
1444 scales[1] = viewport->height / 2.0f;
1445 scales[2] = viewport->maxDepth - viewport->minDepth;
1446 offsets[0] = viewport->x + scales[0];
1447 offsets[1] = viewport->y + scales[1];
1448 offsets[2] = viewport->minDepth;
1449
1450 VkOffset2D min;
1451 VkOffset2D max;
1452 min.x = (int32_t) viewport->x;
1453 max.x = (int32_t) ceilf(viewport->x + viewport->width);
1454 if (viewport->height >= 0.0f) {
1455 min.y = (int32_t) viewport->y;
1456 max.y = (int32_t) ceilf(viewport->y + viewport->height);
1457 } else {
1458 min.y = (int32_t)(viewport->y + viewport->height);
1459 max.y = (int32_t) ceilf(viewport->y);
1460 }
1461 /* the spec allows viewport->height to be 0.0f */
1462 if (min.y == max.y)
1463 max.y++;
1464 assert(min.x >= 0 && min.x < max.x);
1465 assert(min.y >= 0 && min.y < max.y);
1466
1467 VkExtent2D guardband_adj;
1468 guardband_adj.width = tu6_guardband_adj(max.x - min.x);
1469 guardband_adj.height = tu6_guardband_adj(max.y - min.y);
1470
1471 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0, 6);
1472 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XOFFSET_0(offsets[0]).value);
1473 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XSCALE_0(scales[0]).value);
1474 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YOFFSET_0(offsets[1]).value);
1475 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YSCALE_0(scales[1]).value);
1476 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZOFFSET_0(offsets[2]).value);
1477 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZSCALE_0(scales[2]).value);
1478
1479 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
1480 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(min.x) |
1481 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(min.y));
1482 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(max.x - 1) |
1483 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(max.y - 1));
1484
1485 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
1486 tu_cs_emit(cs,
1487 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj.width) |
1488 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj.height));
1489
1490 float z_clamp_min = MIN2(viewport->minDepth, viewport->maxDepth);
1491 float z_clamp_max = MAX2(viewport->minDepth, viewport->maxDepth);
1492
1493 tu_cs_emit_regs(cs,
1494 A6XX_GRAS_CL_Z_CLAMP_MIN(z_clamp_min),
1495 A6XX_GRAS_CL_Z_CLAMP_MAX(z_clamp_max));
1496
1497 tu_cs_emit_regs(cs,
1498 A6XX_RB_Z_CLAMP_MIN(z_clamp_min),
1499 A6XX_RB_Z_CLAMP_MAX(z_clamp_max));
1500 }
1501
1502 void
1503 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor)
1504 {
1505 const VkOffset2D min = scissor->offset;
1506 const VkOffset2D max = {
1507 scissor->offset.x + scissor->extent.width,
1508 scissor->offset.y + scissor->extent.height,
1509 };
1510
1511 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
1512 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(min.x) |
1513 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(min.y));
1514 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(max.x - 1) |
1515 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(max.y - 1));
1516 }
1517
1518 static void
1519 tu6_emit_gras_unknowns(struct tu_cs *cs)
1520 {
1521 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8001, 1);
1522 tu_cs_emit(cs, 0x0);
1523 }
1524
1525 static void
1526 tu6_emit_point_size(struct tu_cs *cs)
1527 {
1528 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POINT_MINMAX, 2);
1529 tu_cs_emit(cs, A6XX_GRAS_SU_POINT_MINMAX_MIN(1.0f / 16.0f) |
1530 A6XX_GRAS_SU_POINT_MINMAX_MAX(4092.0f));
1531 tu_cs_emit(cs, A6XX_GRAS_SU_POINT_SIZE(1.0f).value);
1532 }
1533
1534 static uint32_t
1535 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo *rast_info,
1536 VkSampleCountFlagBits samples)
1537 {
1538 uint32_t gras_su_cntl = 0;
1539
1540 if (rast_info->cullMode & VK_CULL_MODE_FRONT_BIT)
1541 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_FRONT;
1542 if (rast_info->cullMode & VK_CULL_MODE_BACK_BIT)
1543 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_BACK;
1544
1545 if (rast_info->frontFace == VK_FRONT_FACE_CLOCKWISE)
1546 gras_su_cntl |= A6XX_GRAS_SU_CNTL_FRONT_CW;
1547
1548 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1549
1550 if (rast_info->depthBiasEnable)
1551 gras_su_cntl |= A6XX_GRAS_SU_CNTL_POLY_OFFSET;
1552
1553 if (samples > VK_SAMPLE_COUNT_1_BIT)
1554 gras_su_cntl |= A6XX_GRAS_SU_CNTL_MSAA_ENABLE;
1555
1556 return gras_su_cntl;
1557 }
1558
1559 void
1560 tu6_emit_gras_su_cntl(struct tu_cs *cs,
1561 uint32_t gras_su_cntl,
1562 float line_width)
1563 {
1564 assert((gras_su_cntl & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK) == 0);
1565 gras_su_cntl |= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(line_width / 2.0f);
1566
1567 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_CNTL, 1);
1568 tu_cs_emit(cs, gras_su_cntl);
1569 }
1570
1571 void
1572 tu6_emit_depth_bias(struct tu_cs *cs,
1573 float constant_factor,
1574 float clamp,
1575 float slope_factor)
1576 {
1577 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
1578 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor).value);
1579 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor).value);
1580 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp).value);
1581 }
1582
1583 static void
1584 tu6_emit_alpha_control_disable(struct tu_cs *cs)
1585 {
1586 tu_cs_emit_pkt4(cs, REG_A6XX_RB_ALPHA_CONTROL, 1);
1587 tu_cs_emit(cs, 0);
1588 }
1589
1590 static void
1591 tu6_emit_depth_control(struct tu_cs *cs,
1592 const VkPipelineDepthStencilStateCreateInfo *ds_info,
1593 const VkPipelineRasterizationStateCreateInfo *rast_info)
1594 {
1595 assert(!ds_info->depthBoundsTestEnable);
1596
1597 uint32_t rb_depth_cntl = 0;
1598 if (ds_info->depthTestEnable) {
1599 rb_depth_cntl |=
1600 A6XX_RB_DEPTH_CNTL_Z_ENABLE |
1601 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) |
1602 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
1603
1604 if (rast_info->depthClampEnable)
1605 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE;
1606
1607 if (ds_info->depthWriteEnable)
1608 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
1609 }
1610
1611 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_CNTL, 1);
1612 tu_cs_emit(cs, rb_depth_cntl);
1613 }
1614
1615 static void
1616 tu6_emit_stencil_control(struct tu_cs *cs,
1617 const VkPipelineDepthStencilStateCreateInfo *ds_info)
1618 {
1619 uint32_t rb_stencil_control = 0;
1620 if (ds_info->stencilTestEnable) {
1621 const VkStencilOpState *front = &ds_info->front;
1622 const VkStencilOpState *back = &ds_info->back;
1623 rb_stencil_control |=
1624 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
1625 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
1626 A6XX_RB_STENCIL_CONTROL_STENCIL_READ |
1627 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front->compareOp)) |
1628 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front->failOp)) |
1629 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front->passOp)) |
1630 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front->depthFailOp)) |
1631 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back->compareOp)) |
1632 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back->failOp)) |
1633 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back->passOp)) |
1634 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back->depthFailOp));
1635 }
1636
1637 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_CONTROL, 1);
1638 tu_cs_emit(cs, rb_stencil_control);
1639 }
1640
1641 void
1642 tu6_emit_stencil_compare_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1643 {
1644 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILMASK, 1);
1645 tu_cs_emit(
1646 cs, A6XX_RB_STENCILMASK_MASK(front) | A6XX_RB_STENCILMASK_BFMASK(back));
1647 }
1648
1649 void
1650 tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1651 {
1652 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILWRMASK, 1);
1653 tu_cs_emit(cs, A6XX_RB_STENCILWRMASK_WRMASK(front) |
1654 A6XX_RB_STENCILWRMASK_BFWRMASK(back));
1655 }
1656
1657 void
1658 tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back)
1659 {
1660 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILREF, 1);
1661 tu_cs_emit(cs,
1662 A6XX_RB_STENCILREF_REF(front) | A6XX_RB_STENCILREF_BFREF(back));
1663 }
1664
1665 static uint32_t
1666 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState *att,
1667 bool has_alpha)
1668 {
1669 const enum a3xx_rb_blend_opcode color_op = tu6_blend_op(att->colorBlendOp);
1670 const enum adreno_rb_blend_factor src_color_factor = tu6_blend_factor(
1671 has_alpha ? att->srcColorBlendFactor
1672 : tu_blend_factor_no_dst_alpha(att->srcColorBlendFactor));
1673 const enum adreno_rb_blend_factor dst_color_factor = tu6_blend_factor(
1674 has_alpha ? att->dstColorBlendFactor
1675 : tu_blend_factor_no_dst_alpha(att->dstColorBlendFactor));
1676 const enum a3xx_rb_blend_opcode alpha_op = tu6_blend_op(att->alphaBlendOp);
1677 const enum adreno_rb_blend_factor src_alpha_factor =
1678 tu6_blend_factor(att->srcAlphaBlendFactor);
1679 const enum adreno_rb_blend_factor dst_alpha_factor =
1680 tu6_blend_factor(att->dstAlphaBlendFactor);
1681
1682 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor) |
1683 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op) |
1684 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor) |
1685 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor) |
1686 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op) |
1687 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor);
1688 }
1689
1690 static uint32_t
1691 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState *att,
1692 uint32_t rb_mrt_control_rop,
1693 bool is_int,
1694 bool has_alpha)
1695 {
1696 uint32_t rb_mrt_control =
1697 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att->colorWriteMask);
1698
1699 /* ignore blending and logic op for integer attachments */
1700 if (is_int) {
1701 rb_mrt_control |= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
1702 return rb_mrt_control;
1703 }
1704
1705 rb_mrt_control |= rb_mrt_control_rop;
1706
1707 if (att->blendEnable) {
1708 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND;
1709
1710 if (has_alpha)
1711 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND2;
1712 }
1713
1714 return rb_mrt_control;
1715 }
1716
1717 static void
1718 tu6_emit_rb_mrt_controls(struct tu_cs *cs,
1719 const VkPipelineColorBlendStateCreateInfo *blend_info,
1720 const VkFormat attachment_formats[MAX_RTS],
1721 uint32_t *blend_enable_mask)
1722 {
1723 *blend_enable_mask = 0;
1724
1725 bool rop_reads_dst = false;
1726 uint32_t rb_mrt_control_rop = 0;
1727 if (blend_info->logicOpEnable) {
1728 rop_reads_dst = tu_logic_op_reads_dst(blend_info->logicOp);
1729 rb_mrt_control_rop =
1730 A6XX_RB_MRT_CONTROL_ROP_ENABLE |
1731 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info->logicOp));
1732 }
1733
1734 for (uint32_t i = 0; i < blend_info->attachmentCount; i++) {
1735 const VkPipelineColorBlendAttachmentState *att =
1736 &blend_info->pAttachments[i];
1737 const VkFormat format = attachment_formats[i];
1738
1739 uint32_t rb_mrt_control = 0;
1740 uint32_t rb_mrt_blend_control = 0;
1741 if (format != VK_FORMAT_UNDEFINED) {
1742 const bool is_int = vk_format_is_int(format);
1743 const bool has_alpha = vk_format_has_alpha(format);
1744
1745 rb_mrt_control =
1746 tu6_rb_mrt_control(att, rb_mrt_control_rop, is_int, has_alpha);
1747 rb_mrt_blend_control = tu6_rb_mrt_blend_control(att, has_alpha);
1748
1749 if (att->blendEnable || rop_reads_dst)
1750 *blend_enable_mask |= 1 << i;
1751 }
1752
1753 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
1754 tu_cs_emit(cs, rb_mrt_control);
1755 tu_cs_emit(cs, rb_mrt_blend_control);
1756 }
1757 }
1758
1759 static void
1760 tu6_emit_blend_control(struct tu_cs *cs,
1761 uint32_t blend_enable_mask,
1762 const VkPipelineMultisampleStateCreateInfo *msaa_info)
1763 {
1764 assert(!msaa_info->alphaToOneEnable);
1765
1766 uint32_t sp_blend_cntl = A6XX_SP_BLEND_CNTL_UNK8;
1767 if (blend_enable_mask)
1768 sp_blend_cntl |= A6XX_SP_BLEND_CNTL_ENABLED;
1769 if (msaa_info->alphaToCoverageEnable)
1770 sp_blend_cntl |= A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE;
1771
1772 const uint32_t sample_mask =
1773 msaa_info->pSampleMask ? *msaa_info->pSampleMask
1774 : ((1 << msaa_info->rasterizationSamples) - 1);
1775
1776 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
1777 uint32_t rb_blend_cntl =
1778 A6XX_RB_BLEND_CNTL_ENABLE_BLEND(blend_enable_mask) |
1779 A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND |
1780 A6XX_RB_BLEND_CNTL_SAMPLE_MASK(sample_mask);
1781 if (msaa_info->alphaToCoverageEnable)
1782 rb_blend_cntl |= A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE;
1783
1784 tu_cs_emit_pkt4(cs, REG_A6XX_SP_BLEND_CNTL, 1);
1785 tu_cs_emit(cs, sp_blend_cntl);
1786
1787 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_CNTL, 1);
1788 tu_cs_emit(cs, rb_blend_cntl);
1789 }
1790
1791 void
1792 tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4])
1793 {
1794 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_RED_F32, 4);
1795 tu_cs_emit_array(cs, (const uint32_t *) constants, 4);
1796 }
1797
1798 static VkResult
1799 tu_pipeline_create(struct tu_device *dev,
1800 const VkAllocationCallbacks *pAllocator,
1801 struct tu_pipeline **out_pipeline)
1802 {
1803 struct tu_pipeline *pipeline =
1804 vk_zalloc2(&dev->alloc, pAllocator, sizeof(*pipeline), 8,
1805 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1806 if (!pipeline)
1807 return VK_ERROR_OUT_OF_HOST_MEMORY;
1808
1809 tu_cs_init(&pipeline->cs, dev, TU_CS_MODE_SUB_STREAM, 2048);
1810
1811 /* reserve the space now such that tu_cs_begin_sub_stream never fails */
1812 VkResult result = tu_cs_reserve_space(&pipeline->cs, 2048);
1813 if (result != VK_SUCCESS) {
1814 vk_free2(&dev->alloc, pAllocator, pipeline);
1815 return result;
1816 }
1817
1818 *out_pipeline = pipeline;
1819
1820 return VK_SUCCESS;
1821 }
1822
1823 static VkResult
1824 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder)
1825 {
1826 const VkPipelineShaderStageCreateInfo *stage_infos[MESA_SHADER_STAGES] = {
1827 NULL
1828 };
1829 for (uint32_t i = 0; i < builder->create_info->stageCount; i++) {
1830 gl_shader_stage stage =
1831 tu_shader_stage(builder->create_info->pStages[i].stage);
1832 stage_infos[stage] = &builder->create_info->pStages[i];
1833 }
1834
1835 struct tu_shader_compile_options options;
1836 tu_shader_compile_options_init(&options, builder->create_info);
1837
1838 /* compile shaders in reverse order */
1839 struct tu_shader *next_stage_shader = NULL;
1840 for (gl_shader_stage stage = MESA_SHADER_STAGES - 1;
1841 stage > MESA_SHADER_NONE; stage--) {
1842 const VkPipelineShaderStageCreateInfo *stage_info = stage_infos[stage];
1843 if (!stage_info)
1844 continue;
1845
1846 struct tu_shader *shader =
1847 tu_shader_create(builder->device, stage, stage_info, builder->layout,
1848 builder->alloc);
1849 if (!shader)
1850 return VK_ERROR_OUT_OF_HOST_MEMORY;
1851
1852 VkResult result =
1853 tu_shader_compile(builder->device, shader, next_stage_shader,
1854 &options, builder->alloc);
1855 if (result != VK_SUCCESS)
1856 return result;
1857
1858 builder->shaders[stage] = shader;
1859 builder->shader_offsets[stage] = builder->shader_total_size;
1860 builder->shader_total_size +=
1861 sizeof(uint32_t) * shader->variants[0].info.sizedwords;
1862
1863 next_stage_shader = shader;
1864 }
1865
1866 if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
1867 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1868 const struct ir3_shader_variant *variant;
1869
1870 if (vs->ir3_shader.stream_output.num_outputs)
1871 variant = &vs->variants[0];
1872 else
1873 variant = &vs->variants[1];
1874
1875 builder->binning_vs_offset = builder->shader_total_size;
1876 builder->shader_total_size +=
1877 sizeof(uint32_t) * variant->info.sizedwords;
1878 }
1879
1880 return VK_SUCCESS;
1881 }
1882
1883 static VkResult
1884 tu_pipeline_builder_upload_shaders(struct tu_pipeline_builder *builder,
1885 struct tu_pipeline *pipeline)
1886 {
1887 struct tu_bo *bo = &pipeline->program.binary_bo;
1888
1889 VkResult result =
1890 tu_bo_init_new(builder->device, bo, builder->shader_total_size);
1891 if (result != VK_SUCCESS)
1892 return result;
1893
1894 result = tu_bo_map(builder->device, bo);
1895 if (result != VK_SUCCESS)
1896 return result;
1897
1898 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
1899 const struct tu_shader *shader = builder->shaders[i];
1900 if (!shader)
1901 continue;
1902
1903 memcpy(bo->map + builder->shader_offsets[i], shader->binary,
1904 sizeof(uint32_t) * shader->variants[0].info.sizedwords);
1905 }
1906
1907 if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
1908 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1909 const struct ir3_shader_variant *variant;
1910 void *bin;
1911
1912 if (vs->ir3_shader.stream_output.num_outputs) {
1913 variant = &vs->variants[0];
1914 bin = vs->binary;
1915 } else {
1916 variant = &vs->variants[1];
1917 bin = vs->binning_binary;
1918 }
1919
1920 memcpy(bo->map + builder->binning_vs_offset, bin,
1921 sizeof(uint32_t) * variant->info.sizedwords);
1922 }
1923
1924 return VK_SUCCESS;
1925 }
1926
1927 static void
1928 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
1929 struct tu_pipeline *pipeline)
1930 {
1931 const VkPipelineDynamicStateCreateInfo *dynamic_info =
1932 builder->create_info->pDynamicState;
1933
1934 if (!dynamic_info)
1935 return;
1936
1937 for (uint32_t i = 0; i < dynamic_info->dynamicStateCount; i++) {
1938 pipeline->dynamic_state.mask |=
1939 tu_dynamic_state_bit(dynamic_info->pDynamicStates[i]);
1940 }
1941 }
1942
1943 static void
1944 tu_pipeline_set_linkage(struct tu_program_descriptor_linkage *link,
1945 struct tu_shader *shader,
1946 struct ir3_shader_variant *v)
1947 {
1948 link->ubo_state = v->shader->ubo_state;
1949 link->const_state = v->shader->const_state;
1950 link->constlen = v->constlen;
1951 link->texture_map = shader->texture_map;
1952 link->sampler_map = shader->sampler_map;
1953 link->ubo_map = shader->ubo_map;
1954 link->ssbo_map = shader->ssbo_map;
1955 link->image_map = shader->image_map;
1956 }
1957
1958 static void
1959 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder *builder,
1960 struct tu_pipeline *pipeline)
1961 {
1962 struct tu_cs prog_cs;
1963 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
1964 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, false, &pipeline->streamout);
1965 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
1966
1967 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
1968 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, true, &pipeline->streamout);
1969 pipeline->program.binning_state_ib =
1970 tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
1971
1972 VkShaderStageFlags stages = 0;
1973 for (unsigned i = 0; i < builder->create_info->stageCount; i++) {
1974 stages |= builder->create_info->pStages[i].stage;
1975 }
1976 pipeline->active_stages = stages;
1977
1978 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
1979 if (!builder->shaders[i])
1980 continue;
1981
1982 tu_pipeline_set_linkage(&pipeline->program.link[i],
1983 builder->shaders[i],
1984 &builder->shaders[i]->variants[0]);
1985 }
1986 }
1987
1988 static void
1989 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder *builder,
1990 struct tu_pipeline *pipeline)
1991 {
1992 const VkPipelineVertexInputStateCreateInfo *vi_info =
1993 builder->create_info->pVertexInputState;
1994 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1995
1996 struct tu_cs vi_cs;
1997 tu_cs_begin_sub_stream(&pipeline->cs,
1998 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
1999 tu6_emit_vertex_input(&vi_cs, &vs->variants[0], vi_info,
2000 pipeline->vi.bindings, &pipeline->vi.count);
2001 pipeline->vi.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
2002
2003 if (vs->has_binning_pass) {
2004 tu_cs_begin_sub_stream(&pipeline->cs,
2005 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
2006 tu6_emit_vertex_input(
2007 &vi_cs, &vs->variants[1], vi_info, pipeline->vi.binning_bindings,
2008 &pipeline->vi.binning_count);
2009 pipeline->vi.binning_state_ib =
2010 tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
2011 }
2012 }
2013
2014 static void
2015 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder *builder,
2016 struct tu_pipeline *pipeline)
2017 {
2018 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
2019 builder->create_info->pInputAssemblyState;
2020
2021 pipeline->ia.primtype = tu6_primtype(ia_info->topology);
2022 pipeline->ia.primitive_restart = ia_info->primitiveRestartEnable;
2023 }
2024
2025 static void
2026 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder *builder,
2027 struct tu_pipeline *pipeline)
2028 {
2029 /* The spec says:
2030 *
2031 * pViewportState is a pointer to an instance of the
2032 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
2033 * pipeline has rasterization disabled."
2034 *
2035 * We leave the relevant registers stale in that case.
2036 */
2037 if (builder->rasterizer_discard)
2038 return;
2039
2040 const VkPipelineViewportStateCreateInfo *vp_info =
2041 builder->create_info->pViewportState;
2042
2043 struct tu_cs vp_cs;
2044 tu_cs_begin_sub_stream(&pipeline->cs, 21, &vp_cs);
2045
2046 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_VIEWPORT)) {
2047 assert(vp_info->viewportCount == 1);
2048 tu6_emit_viewport(&vp_cs, vp_info->pViewports);
2049 }
2050
2051 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_SCISSOR)) {
2052 assert(vp_info->scissorCount == 1);
2053 tu6_emit_scissor(&vp_cs, vp_info->pScissors);
2054 }
2055
2056 pipeline->vp.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vp_cs);
2057 }
2058
2059 static void
2060 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder,
2061 struct tu_pipeline *pipeline)
2062 {
2063 const VkPipelineRasterizationStateCreateInfo *rast_info =
2064 builder->create_info->pRasterizationState;
2065
2066 assert(rast_info->polygonMode == VK_POLYGON_MODE_FILL);
2067
2068 struct tu_cs rast_cs;
2069 tu_cs_begin_sub_stream(&pipeline->cs, 20, &rast_cs);
2070
2071
2072 tu_cs_emit_regs(&rast_cs,
2073 A6XX_GRAS_CL_CNTL(
2074 .znear_clip_disable = rast_info->depthClampEnable,
2075 .zfar_clip_disable = rast_info->depthClampEnable,
2076 .unk5 = rast_info->depthClampEnable,
2077 .zero_gb_scale_z = 1,
2078 .vp_clip_code_ignore = 1));
2079 /* move to hw ctx init? */
2080 tu6_emit_gras_unknowns(&rast_cs);
2081 tu6_emit_point_size(&rast_cs);
2082
2083 const uint32_t gras_su_cntl =
2084 tu6_gras_su_cntl(rast_info, builder->samples);
2085
2086 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH))
2087 tu6_emit_gras_su_cntl(&rast_cs, gras_su_cntl, rast_info->lineWidth);
2088
2089 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_DEPTH_BIAS)) {
2090 tu6_emit_depth_bias(&rast_cs, rast_info->depthBiasConstantFactor,
2091 rast_info->depthBiasClamp,
2092 rast_info->depthBiasSlopeFactor);
2093 }
2094
2095 pipeline->rast.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &rast_cs);
2096
2097 pipeline->rast.gras_su_cntl = gras_su_cntl;
2098 }
2099
2100 static void
2101 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
2102 struct tu_pipeline *pipeline)
2103 {
2104 /* The spec says:
2105 *
2106 * pDepthStencilState is a pointer to an instance of the
2107 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
2108 * the pipeline has rasterization disabled or if the subpass of the
2109 * render pass the pipeline is created against does not use a
2110 * depth/stencil attachment.
2111 *
2112 * We disable both depth and stenil tests in those cases.
2113 */
2114 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info;
2115 const VkPipelineDepthStencilStateCreateInfo *ds_info =
2116 builder->use_depth_stencil_attachment
2117 ? builder->create_info->pDepthStencilState
2118 : &dummy_ds_info;
2119
2120 struct tu_cs ds_cs;
2121 tu_cs_begin_sub_stream(&pipeline->cs, 12, &ds_cs);
2122
2123 /* move to hw ctx init? */
2124 tu6_emit_alpha_control_disable(&ds_cs);
2125
2126 tu6_emit_depth_control(&ds_cs, ds_info, builder->create_info->pRasterizationState);
2127 tu6_emit_stencil_control(&ds_cs, ds_info);
2128
2129 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
2130 tu6_emit_stencil_compare_mask(&ds_cs, ds_info->front.compareMask,
2131 ds_info->back.compareMask);
2132 }
2133 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
2134 tu6_emit_stencil_write_mask(&ds_cs, ds_info->front.writeMask,
2135 ds_info->back.writeMask);
2136 }
2137 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
2138 tu6_emit_stencil_reference(&ds_cs, ds_info->front.reference,
2139 ds_info->back.reference);
2140 }
2141
2142 pipeline->ds.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &ds_cs);
2143 }
2144
2145 static void
2146 tu_pipeline_builder_parse_multisample_and_color_blend(
2147 struct tu_pipeline_builder *builder, struct tu_pipeline *pipeline)
2148 {
2149 /* The spec says:
2150 *
2151 * pMultisampleState is a pointer to an instance of the
2152 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
2153 * has rasterization disabled.
2154 *
2155 * Also,
2156 *
2157 * pColorBlendState is a pointer to an instance of the
2158 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
2159 * pipeline has rasterization disabled or if the subpass of the render
2160 * pass the pipeline is created against does not use any color
2161 * attachments.
2162 *
2163 * We leave the relevant registers stale when rasterization is disabled.
2164 */
2165 if (builder->rasterizer_discard)
2166 return;
2167
2168 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info;
2169 const VkPipelineMultisampleStateCreateInfo *msaa_info =
2170 builder->create_info->pMultisampleState;
2171 const VkPipelineColorBlendStateCreateInfo *blend_info =
2172 builder->use_color_attachments ? builder->create_info->pColorBlendState
2173 : &dummy_blend_info;
2174
2175 struct tu_cs blend_cs;
2176 tu_cs_begin_sub_stream(&pipeline->cs, MAX_RTS * 3 + 9, &blend_cs);
2177
2178 uint32_t blend_enable_mask;
2179 tu6_emit_rb_mrt_controls(&blend_cs, blend_info,
2180 builder->color_attachment_formats,
2181 &blend_enable_mask);
2182
2183 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_BLEND_CONSTANTS))
2184 tu6_emit_blend_constants(&blend_cs, blend_info->blendConstants);
2185
2186 tu6_emit_blend_control(&blend_cs, blend_enable_mask, msaa_info);
2187
2188 pipeline->blend.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &blend_cs);
2189 }
2190
2191 static void
2192 tu_pipeline_finish(struct tu_pipeline *pipeline,
2193 struct tu_device *dev,
2194 const VkAllocationCallbacks *alloc)
2195 {
2196 tu_cs_finish(&pipeline->cs);
2197
2198 if (pipeline->program.binary_bo.gem_handle)
2199 tu_bo_finish(dev, &pipeline->program.binary_bo);
2200 }
2201
2202 static VkResult
2203 tu_pipeline_builder_build(struct tu_pipeline_builder *builder,
2204 struct tu_pipeline **pipeline)
2205 {
2206 VkResult result = tu_pipeline_create(builder->device, builder->alloc,
2207 pipeline);
2208 if (result != VK_SUCCESS)
2209 return result;
2210
2211 /* compile and upload shaders */
2212 result = tu_pipeline_builder_compile_shaders(builder);
2213 if (result == VK_SUCCESS)
2214 result = tu_pipeline_builder_upload_shaders(builder, *pipeline);
2215 if (result != VK_SUCCESS) {
2216 tu_pipeline_finish(*pipeline, builder->device, builder->alloc);
2217 vk_free2(&builder->device->alloc, builder->alloc, *pipeline);
2218 *pipeline = VK_NULL_HANDLE;
2219
2220 return result;
2221 }
2222
2223 tu_pipeline_builder_parse_dynamic(builder, *pipeline);
2224 tu_pipeline_builder_parse_shader_stages(builder, *pipeline);
2225 tu_pipeline_builder_parse_vertex_input(builder, *pipeline);
2226 tu_pipeline_builder_parse_input_assembly(builder, *pipeline);
2227 tu_pipeline_builder_parse_viewport(builder, *pipeline);
2228 tu_pipeline_builder_parse_rasterization(builder, *pipeline);
2229 tu_pipeline_builder_parse_depth_stencil(builder, *pipeline);
2230 tu_pipeline_builder_parse_multisample_and_color_blend(builder, *pipeline);
2231
2232 /* we should have reserved enough space upfront such that the CS never
2233 * grows
2234 */
2235 assert((*pipeline)->cs.bo_count == 1);
2236
2237 return VK_SUCCESS;
2238 }
2239
2240 static void
2241 tu_pipeline_builder_finish(struct tu_pipeline_builder *builder)
2242 {
2243 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
2244 if (!builder->shaders[i])
2245 continue;
2246 tu_shader_destroy(builder->device, builder->shaders[i], builder->alloc);
2247 }
2248 }
2249
2250 static void
2251 tu_pipeline_builder_init_graphics(
2252 struct tu_pipeline_builder *builder,
2253 struct tu_device *dev,
2254 struct tu_pipeline_cache *cache,
2255 const VkGraphicsPipelineCreateInfo *create_info,
2256 const VkAllocationCallbacks *alloc)
2257 {
2258 TU_FROM_HANDLE(tu_pipeline_layout, layout, create_info->layout);
2259
2260 *builder = (struct tu_pipeline_builder) {
2261 .device = dev,
2262 .cache = cache,
2263 .create_info = create_info,
2264 .alloc = alloc,
2265 .layout = layout,
2266 };
2267
2268 builder->rasterizer_discard =
2269 create_info->pRasterizationState->rasterizerDiscardEnable;
2270
2271 if (builder->rasterizer_discard) {
2272 builder->samples = VK_SAMPLE_COUNT_1_BIT;
2273 } else {
2274 builder->samples = create_info->pMultisampleState->rasterizationSamples;
2275
2276 const struct tu_render_pass *pass =
2277 tu_render_pass_from_handle(create_info->renderPass);
2278 const struct tu_subpass *subpass =
2279 &pass->subpasses[create_info->subpass];
2280
2281 builder->use_depth_stencil_attachment =
2282 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED;
2283
2284 assert(subpass->color_count == 0 ||
2285 !create_info->pColorBlendState ||
2286 subpass->color_count == create_info->pColorBlendState->attachmentCount);
2287 builder->color_attachment_count = subpass->color_count;
2288 for (uint32_t i = 0; i < subpass->color_count; i++) {
2289 const uint32_t a = subpass->color_attachments[i].attachment;
2290 if (a == VK_ATTACHMENT_UNUSED)
2291 continue;
2292
2293 builder->color_attachment_formats[i] = pass->attachments[a].format;
2294 builder->use_color_attachments = true;
2295 }
2296 }
2297 }
2298
2299 static VkResult
2300 tu_graphics_pipeline_create(VkDevice device,
2301 VkPipelineCache pipelineCache,
2302 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2303 const VkAllocationCallbacks *pAllocator,
2304 VkPipeline *pPipeline)
2305 {
2306 TU_FROM_HANDLE(tu_device, dev, device);
2307 TU_FROM_HANDLE(tu_pipeline_cache, cache, pipelineCache);
2308
2309 struct tu_pipeline_builder builder;
2310 tu_pipeline_builder_init_graphics(&builder, dev, cache,
2311 pCreateInfo, pAllocator);
2312
2313 struct tu_pipeline *pipeline = NULL;
2314 VkResult result = tu_pipeline_builder_build(&builder, &pipeline);
2315 tu_pipeline_builder_finish(&builder);
2316
2317 if (result == VK_SUCCESS)
2318 *pPipeline = tu_pipeline_to_handle(pipeline);
2319 else
2320 *pPipeline = VK_NULL_HANDLE;
2321
2322 return result;
2323 }
2324
2325 VkResult
2326 tu_CreateGraphicsPipelines(VkDevice device,
2327 VkPipelineCache pipelineCache,
2328 uint32_t count,
2329 const VkGraphicsPipelineCreateInfo *pCreateInfos,
2330 const VkAllocationCallbacks *pAllocator,
2331 VkPipeline *pPipelines)
2332 {
2333 VkResult final_result = VK_SUCCESS;
2334
2335 for (uint32_t i = 0; i < count; i++) {
2336 VkResult result = tu_graphics_pipeline_create(device, pipelineCache,
2337 &pCreateInfos[i], pAllocator,
2338 &pPipelines[i]);
2339
2340 if (result != VK_SUCCESS)
2341 final_result = result;
2342 }
2343
2344 return final_result;
2345 }
2346
2347 static void
2348 tu6_emit_compute_program(struct tu_cs *cs,
2349 struct tu_shader *shader,
2350 const struct tu_bo *binary_bo)
2351 {
2352 const struct ir3_shader_variant *v = &shader->variants[0];
2353
2354 tu6_emit_cs_config(cs, shader, v);
2355
2356 /* The compute program is the only one in the pipeline, so 0 offset. */
2357 tu6_emit_shader_object(cs, MESA_SHADER_COMPUTE, v, binary_bo, 0);
2358
2359 tu6_emit_immediates(cs, v, CP_LOAD_STATE6_FRAG, SB6_CS_SHADER);
2360 }
2361
2362 static VkResult
2363 tu_compute_upload_shader(VkDevice device,
2364 struct tu_pipeline *pipeline,
2365 struct tu_shader *shader)
2366 {
2367 TU_FROM_HANDLE(tu_device, dev, device);
2368 struct tu_bo *bo = &pipeline->program.binary_bo;
2369 struct ir3_shader_variant *v = &shader->variants[0];
2370
2371 uint32_t shader_size = sizeof(uint32_t) * v->info.sizedwords;
2372 VkResult result =
2373 tu_bo_init_new(dev, bo, shader_size);
2374 if (result != VK_SUCCESS)
2375 return result;
2376
2377 result = tu_bo_map(dev, bo);
2378 if (result != VK_SUCCESS)
2379 return result;
2380
2381 memcpy(bo->map, shader->binary, shader_size);
2382
2383 return VK_SUCCESS;
2384 }
2385
2386
2387 static VkResult
2388 tu_compute_pipeline_create(VkDevice device,
2389 VkPipelineCache _cache,
2390 const VkComputePipelineCreateInfo *pCreateInfo,
2391 const VkAllocationCallbacks *pAllocator,
2392 VkPipeline *pPipeline)
2393 {
2394 TU_FROM_HANDLE(tu_device, dev, device);
2395 TU_FROM_HANDLE(tu_pipeline_layout, layout, pCreateInfo->layout);
2396 const VkPipelineShaderStageCreateInfo *stage_info = &pCreateInfo->stage;
2397 VkResult result;
2398
2399 struct tu_pipeline *pipeline;
2400
2401 *pPipeline = VK_NULL_HANDLE;
2402
2403 result = tu_pipeline_create(dev, pAllocator, &pipeline);
2404 if (result != VK_SUCCESS)
2405 return result;
2406
2407 pipeline->layout = layout;
2408
2409 struct tu_shader_compile_options options;
2410 tu_shader_compile_options_init(&options, NULL);
2411
2412 struct tu_shader *shader =
2413 tu_shader_create(dev, MESA_SHADER_COMPUTE, stage_info, layout, pAllocator);
2414 if (!shader) {
2415 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2416 goto fail;
2417 }
2418
2419 result = tu_shader_compile(dev, shader, NULL, &options, pAllocator);
2420 if (result != VK_SUCCESS)
2421 goto fail;
2422
2423 struct ir3_shader_variant *v = &shader->variants[0];
2424
2425 tu_pipeline_set_linkage(&pipeline->program.link[MESA_SHADER_COMPUTE],
2426 shader, v);
2427
2428 result = tu_compute_upload_shader(device, pipeline, shader);
2429 if (result != VK_SUCCESS)
2430 goto fail;
2431
2432 for (int i = 0; i < 3; i++)
2433 pipeline->compute.local_size[i] = v->shader->nir->info.cs.local_size[i];
2434
2435 struct tu_cs prog_cs;
2436 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2437 tu6_emit_compute_program(&prog_cs, shader, &pipeline->program.binary_bo);
2438 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2439
2440 *pPipeline = tu_pipeline_to_handle(pipeline);
2441 return VK_SUCCESS;
2442
2443 fail:
2444 if (shader)
2445 tu_shader_destroy(dev, shader, pAllocator);
2446
2447 tu_pipeline_finish(pipeline, dev, pAllocator);
2448 vk_free2(&dev->alloc, pAllocator, pipeline);
2449
2450 return result;
2451 }
2452
2453 VkResult
2454 tu_CreateComputePipelines(VkDevice device,
2455 VkPipelineCache pipelineCache,
2456 uint32_t count,
2457 const VkComputePipelineCreateInfo *pCreateInfos,
2458 const VkAllocationCallbacks *pAllocator,
2459 VkPipeline *pPipelines)
2460 {
2461 VkResult final_result = VK_SUCCESS;
2462
2463 for (uint32_t i = 0; i < count; i++) {
2464 VkResult result = tu_compute_pipeline_create(device, pipelineCache,
2465 &pCreateInfos[i],
2466 pAllocator, &pPipelines[i]);
2467 if (result != VK_SUCCESS)
2468 final_result = result;
2469 }
2470
2471 return final_result;
2472 }
2473
2474 void
2475 tu_DestroyPipeline(VkDevice _device,
2476 VkPipeline _pipeline,
2477 const VkAllocationCallbacks *pAllocator)
2478 {
2479 TU_FROM_HANDLE(tu_device, dev, _device);
2480 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
2481
2482 if (!_pipeline)
2483 return;
2484
2485 tu_pipeline_finish(pipeline, dev, pAllocator);
2486 vk_free2(&dev->alloc, pAllocator, pipeline);
2487 }