2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
43 #define VG(x) ((void)0)
46 #include "c11/threads.h"
47 #include "main/macros.h"
48 #include "util/list.h"
49 #include "util/macros.h"
50 #include "util/u_atomic.h"
52 #include "vk_object.h"
53 #include "vk_debug_report.h"
54 #include "wsi_common.h"
56 #include "ir3/ir3_compiler.h"
57 #include "ir3/ir3_shader.h"
59 #include "adreno_common.xml.h"
60 #include "adreno_pm4.xml.h"
62 #include "fdl/freedreno_layout.h"
64 #include "tu_descriptor_set.h"
65 #include "tu_extensions.h"
68 /* Pre-declarations needed for WSI entrypoints */
71 typedef struct xcb_connection_t xcb_connection_t
;
72 typedef uint32_t xcb_visualid_t
;
73 typedef uint32_t xcb_window_t
;
75 #include <vulkan/vk_android_native_buffer.h>
76 #include <vulkan/vk_icd.h>
77 #include <vulkan/vulkan.h>
78 #include <vulkan/vulkan_intel.h>
80 #include "tu_entrypoints.h"
82 #include "vk_format.h"
85 #define MAX_VERTEX_ATTRIBS 32
87 #define MAX_VSC_PIPES 32
88 #define MAX_VIEWPORTS 1
89 #define MAX_SCISSORS 16
90 #define MAX_DISCARD_RECTANGLES 4
91 #define MAX_PUSH_CONSTANTS_SIZE 128
92 #define MAX_PUSH_DESCRIPTORS 32
93 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
94 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
95 #define MAX_DYNAMIC_BUFFERS \
96 (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
97 #define TU_MAX_DRM_DEVICES 8
99 #define MAX_BIND_POINTS 2 /* compute + graphics */
100 /* The Qualcomm driver exposes 0x20000058 */
101 #define MAX_STORAGE_BUFFER_RANGE 0x20000000
102 /* We use ldc for uniform buffer loads, just like the Qualcomm driver, so
103 * expose the same maximum range.
104 * TODO: The SIZE bitfield is 15 bits, and in 4-dword units, so the actual
105 * range might be higher.
107 #define MAX_UNIFORM_BUFFER_RANGE 0x10000
109 #define A6XX_TEX_CONST_DWORDS 16
110 #define A6XX_TEX_SAMP_DWORDS 4
112 #define tu_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
114 #define for_each_bit(b, dword) \
115 for (uint32_t __dword = (dword); \
116 (b) = __builtin_ffs(__dword) - 1, __dword; __dword &= ~(1 << (b)))
118 #define COND(bool, val) ((bool) ? (val) : 0)
119 #define BIT(bit) (1u << (bit))
121 /* Whenever we generate an error, pass it through this function. Useful for
122 * debugging, where we can break on it. Only call at error site, not when
123 * propagating errors. Might be useful to plug in a stack trace here.
129 __vk_errorf(struct tu_instance
*instance
,
136 #define vk_error(instance, error) \
137 __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
138 #define vk_errorf(instance, error, format, ...) \
139 __vk_errorf(instance, error, __FILE__, __LINE__, format, ##__VA_ARGS__);
142 __tu_finishme(const char *file
, int line
, const char *format
, ...)
145 tu_loge(const char *format
, ...) tu_printflike(1, 2);
147 tu_logi(const char *format
, ...) tu_printflike(1, 2);
150 * Print a FINISHME message, including its source location.
152 #define tu_finishme(format, ...) \
154 static bool reported = false; \
156 __tu_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
163 tu_finishme("stub %s", __func__); \
167 tu_lookup_entrypoint_unchecked(const char *name
);
169 tu_lookup_entrypoint_checked(
171 uint32_t core_version
,
172 const struct tu_instance_extension_table
*instance
,
173 const struct tu_device_extension_table
*device
);
175 struct tu_physical_device
177 struct vk_object_base base
;
179 struct tu_instance
*instance
;
182 char name
[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE
];
183 uint8_t driver_uuid
[VK_UUID_SIZE
];
184 uint8_t device_uuid
[VK_UUID_SIZE
];
185 uint8_t cache_uuid
[VK_UUID_SIZE
];
187 struct wsi_device wsi_device
;
195 uint32_t ccu_offset_gmem
;
196 uint32_t ccu_offset_bypass
;
197 /* alignment for size of tiles */
198 uint32_t tile_align_w
;
199 #define TILE_ALIGN_H 16
200 /* gmem store/load granularity */
201 #define GMEM_ALIGN_W 16
202 #define GMEM_ALIGN_H 4
205 uint32_t PC_UNKNOWN_9805
;
206 uint32_t SP_UNKNOWN_A0F8
;
209 int msm_major_version
;
210 int msm_minor_version
;
214 /* This is the drivers on-disk cache used as a fallback as opposed to
215 * the pipeline cache defined by apps.
217 struct disk_cache
*disk_cache
;
219 struct tu_device_extension_table supported_extensions
;
224 TU_DEBUG_STARTUP
= 1 << 0,
225 TU_DEBUG_NIR
= 1 << 1,
226 TU_DEBUG_IR3
= 1 << 2,
227 TU_DEBUG_NOBIN
= 1 << 3,
228 TU_DEBUG_SYSMEM
= 1 << 4,
229 TU_DEBUG_FORCEBIN
= 1 << 5,
230 TU_DEBUG_NOUBWC
= 1 << 6,
235 struct vk_object_base base
;
237 VkAllocationCallbacks alloc
;
239 uint32_t api_version
;
240 int physical_device_count
;
241 struct tu_physical_device physical_devices
[TU_MAX_DRM_DEVICES
];
243 enum tu_debug_flags debug_flags
;
245 struct vk_debug_report_instance debug_report_callbacks
;
247 struct tu_instance_extension_table enabled_extensions
;
251 tu_wsi_init(struct tu_physical_device
*physical_device
);
253 tu_wsi_finish(struct tu_physical_device
*physical_device
);
256 tu_instance_extension_supported(const char *name
);
258 tu_physical_device_api_version(struct tu_physical_device
*dev
);
260 tu_physical_device_extension_supported(struct tu_physical_device
*dev
,
265 struct tu_pipeline_cache
267 struct vk_object_base base
;
269 struct tu_device
*device
;
270 pthread_mutex_t mutex
;
274 uint32_t kernel_count
;
275 struct cache_entry
**hash_table
;
278 VkAllocationCallbacks alloc
;
281 struct tu_pipeline_key
287 #define TU_QUEUE_GENERAL 0
289 #define TU_MAX_QUEUE_FAMILIES 1
293 struct vk_object_base base
;
294 struct wsi_fence
*fence_wsi
;
300 tu_fence_init(struct tu_fence
*fence
, bool signaled
);
302 tu_fence_finish(struct tu_fence
*fence
);
304 tu_fence_update_fd(struct tu_fence
*fence
, int fd
);
306 tu_fence_copy(struct tu_fence
*fence
, const struct tu_fence
*src
);
308 tu_fence_signal(struct tu_fence
*fence
);
310 tu_fence_wait_idle(struct tu_fence
*fence
);
314 struct vk_object_base base
;
316 struct tu_device
*device
;
317 uint32_t queue_family_index
;
319 VkDeviceQueueCreateFlags flags
;
321 uint32_t msm_queue_id
;
322 struct tu_fence submit_fence
;
337 GLOBAL_SH_FS_CLEAR_MAX
= GLOBAL_SH_FS_CLEAR0
+ MAX_RTS
,
341 #define TU_BORDER_COLOR_COUNT 4096
342 #define TU_BORDER_COLOR_BUILTIN 6
344 /* This struct defines the layout of the global_bo */
347 /* clear/blit shaders, all <= 16 instrs (16 instr = 1 instrlen unit) */
348 instr_t shaders
[GLOBAL_SH_COUNT
][16];
350 uint32_t seqno_dummy
; /* dummy seqno for CP_EVENT_WRITE */
352 volatile uint32_t vsc_draw_overflow
;
354 volatile uint32_t vsc_prim_overflow
;
358 /* scratch space for VPC_SO[i].FLUSH_BASE_LO/HI, start on 32 byte boundary. */
364 /* note: larger global bo will be used for customBorderColors */
365 struct bcolor_entry bcolor_builtin
[TU_BORDER_COLOR_BUILTIN
], bcolor
[];
367 #define gb_offset(member) offsetof(struct tu6_global, member)
368 #define global_iova(cmd, member) ((cmd)->device->global_bo.iova + gb_offset(member))
370 void tu_init_clear_blit_shaders(struct tu6_global
*global
);
372 /* extra space in vsc draw/prim streams */
378 struct tu_instance
*instance
;
380 struct tu_queue
*queues
[TU_MAX_QUEUE_FAMILIES
];
381 int queue_count
[TU_MAX_QUEUE_FAMILIES
];
383 struct tu_physical_device
*physical_device
;
386 struct ir3_compiler
*compiler
;
388 /* Backup in-memory cache to be used if the app doesn't provide one */
389 struct tu_pipeline_cache
*mem_cache
;
391 #define MIN_SCRATCH_BO_SIZE_LOG2 12 /* A page */
393 /* Currently the kernel driver uses a 32-bit GPU address space, but it
394 * should be impossible to go beyond 48 bits.
400 } scratch_bos
[48 - MIN_SCRATCH_BO_SIZE_LOG2
];
402 struct tu_bo global_bo
;
404 struct tu_device_extension_table enabled_extensions
;
406 uint32_t vsc_draw_strm_pitch
;
407 uint32_t vsc_prim_strm_pitch
;
408 BITSET_DECLARE(custom_border_color
, TU_BORDER_COLOR_COUNT
);
412 VkResult
_tu_device_set_lost(struct tu_device
*device
,
413 const char *file
, int line
,
414 const char *msg
, ...) PRINTFLIKE(4, 5);
415 #define tu_device_set_lost(dev, ...) \
416 _tu_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
419 tu_device_is_lost(struct tu_device
*device
)
421 return unlikely(p_atomic_read(&device
->_lost
));
425 tu_bo_init_new(struct tu_device
*dev
, struct tu_bo
*bo
, uint64_t size
);
427 tu_bo_init_dmabuf(struct tu_device
*dev
,
432 tu_bo_export_dmabuf(struct tu_device
*dev
, struct tu_bo
*bo
);
434 tu_bo_finish(struct tu_device
*dev
, struct tu_bo
*bo
);
436 tu_bo_map(struct tu_device
*dev
, struct tu_bo
*bo
);
438 /* Get a scratch bo for use inside a command buffer. This will always return
439 * the same bo given the same size or similar sizes, so only one scratch bo
440 * can be used at the same time. It's meant for short-lived things where we
441 * need to write to some piece of memory, read from it, and then immediately
445 tu_get_scratch_bo(struct tu_device
*dev
, uint64_t size
, struct tu_bo
**bo
);
450 const struct tu_bo
*bo
;
456 struct tu_cs_memory
{
461 struct tu_draw_state
{
466 enum tu_dynamic_state
468 /* re-use VK_DYNAMIC_STATE_ enums for non-extended dynamic states */
469 TU_DYNAMIC_STATE_SAMPLE_LOCATIONS
= VK_DYNAMIC_STATE_STENCIL_REFERENCE
+ 1,
470 TU_DYNAMIC_STATE_COUNT
,
473 enum tu_draw_state_group_id
475 TU_DRAW_STATE_PROGRAM
,
476 TU_DRAW_STATE_PROGRAM_BINNING
,
480 TU_DRAW_STATE_VI_BINNING
,
484 TU_DRAW_STATE_VS_CONST
,
485 TU_DRAW_STATE_HS_CONST
,
486 TU_DRAW_STATE_DS_CONST
,
487 TU_DRAW_STATE_GS_CONST
,
488 TU_DRAW_STATE_FS_CONST
,
489 TU_DRAW_STATE_DESC_SETS
,
490 TU_DRAW_STATE_DESC_SETS_LOAD
,
491 TU_DRAW_STATE_VS_PARAMS
,
492 TU_DRAW_STATE_INPUT_ATTACHMENTS_GMEM
,
493 TU_DRAW_STATE_INPUT_ATTACHMENTS_SYSMEM
,
495 /* dynamic state related draw states */
496 TU_DRAW_STATE_DYNAMIC
,
497 TU_DRAW_STATE_COUNT
= TU_DRAW_STATE_DYNAMIC
+ TU_DYNAMIC_STATE_COUNT
,
504 * A command stream in TU_CS_MODE_GROW mode grows automatically whenever it
505 * is full. tu_cs_begin must be called before command packet emission and
506 * tu_cs_end must be called after.
508 * This mode may create multiple entries internally. The entries must be
509 * submitted together.
514 * A command stream in TU_CS_MODE_EXTERNAL mode wraps an external,
515 * fixed-size buffer. tu_cs_begin and tu_cs_end are optional and have no
518 * This mode does not create any entry or any BO.
523 * A command stream in TU_CS_MODE_SUB_STREAM mode does not support direct
524 * command packet emission. tu_cs_begin_sub_stream must be called to get a
525 * sub-stream to emit comamnd packets to. When done with the sub-stream,
526 * tu_cs_end_sub_stream must be called.
528 * This mode does not create any entry internally.
530 TU_CS_MODE_SUB_STREAM
,
537 uint32_t *reserved_end
;
540 struct tu_device
*device
;
541 enum tu_cs_mode mode
;
542 uint32_t next_bo_size
;
544 struct tu_cs_entry
*entries
;
545 uint32_t entry_count
;
546 uint32_t entry_capacity
;
550 uint32_t bo_capacity
;
552 /* state for cond_exec_start/cond_exec_end */
554 uint32_t *cond_dwords
;
557 struct tu_device_memory
559 struct vk_object_base base
;
564 /* for dedicated allocations */
565 struct tu_image
*image
;
566 struct tu_buffer
*buffer
;
573 struct tu_descriptor_range
579 struct tu_descriptor_set
581 struct vk_object_base base
;
583 const struct tu_descriptor_set_layout
*layout
;
584 struct tu_descriptor_pool
*pool
;
588 uint32_t *mapped_ptr
;
590 uint32_t *dynamic_descriptors
;
592 struct tu_bo
*buffers
[0];
595 struct tu_push_descriptor_set
597 struct tu_descriptor_set set
;
601 struct tu_descriptor_pool_entry
605 struct tu_descriptor_set
*set
;
608 struct tu_descriptor_pool
610 struct vk_object_base base
;
613 uint64_t current_offset
;
616 uint8_t *host_memory_base
;
617 uint8_t *host_memory_ptr
;
618 uint8_t *host_memory_end
;
620 uint32_t entry_count
;
621 uint32_t max_entry_count
;
622 struct tu_descriptor_pool_entry entries
[0];
625 struct tu_descriptor_update_template_entry
627 VkDescriptorType descriptor_type
;
629 /* The number of descriptors to update */
630 uint32_t descriptor_count
;
632 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array
636 /* In dwords. Not valid/used for dynamic descriptors */
639 uint32_t buffer_offset
;
641 /* Only valid for combined image samplers and samplers */
642 uint16_t has_sampler
;
648 /* For push descriptors */
649 const uint32_t *immutable_samplers
;
652 struct tu_descriptor_update_template
654 struct vk_object_base base
;
656 uint32_t entry_count
;
657 struct tu_descriptor_update_template_entry entry
[0];
662 struct vk_object_base base
;
666 VkBufferUsageFlags usage
;
667 VkBufferCreateFlags flags
;
670 VkDeviceSize bo_offset
;
673 static inline uint64_t
674 tu_buffer_iova(struct tu_buffer
*buffer
)
676 return buffer
->bo
->iova
+ buffer
->bo_offset
;
679 struct tu_vertex_binding
681 struct tu_buffer
*buffer
;
686 tu_get_debug_option_name(int id
);
689 tu_get_perftest_option_name(int id
);
691 struct tu_descriptor_state
693 struct tu_descriptor_set
*sets
[MAX_SETS
];
694 uint32_t dynamic_descriptors
[MAX_DYNAMIC_BUFFERS
* A6XX_TEX_CONST_DWORDS
];
697 enum tu_cmd_dirty_bits
699 TU_CMD_DIRTY_VERTEX_BUFFERS
= 1 << 2,
700 TU_CMD_DIRTY_DESC_SETS_LOAD
= 1 << 3,
701 TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD
= 1 << 4,
702 TU_CMD_DIRTY_SHADER_CONSTS
= 1 << 5,
703 /* all draw states were disabled and need to be re-enabled: */
704 TU_CMD_DIRTY_DRAW_STATE
= 1 << 7,
707 /* There are only three cache domains we have to care about: the CCU, or
708 * color cache unit, which is used for color and depth/stencil attachments
709 * and copy/blit destinations, and is split conceptually into color and depth,
710 * and the universal cache or UCHE which is used for pretty much everything
711 * else, except for the CP (uncached) and host. We need to flush whenever data
712 * crosses these boundaries.
715 enum tu_cmd_access_mask
{
716 TU_ACCESS_UCHE_READ
= 1 << 0,
717 TU_ACCESS_UCHE_WRITE
= 1 << 1,
718 TU_ACCESS_CCU_COLOR_READ
= 1 << 2,
719 TU_ACCESS_CCU_COLOR_WRITE
= 1 << 3,
720 TU_ACCESS_CCU_DEPTH_READ
= 1 << 4,
721 TU_ACCESS_CCU_DEPTH_WRITE
= 1 << 5,
723 /* Experiments have shown that while it's safe to avoid flushing the CCU
724 * after each blit/renderpass, it's not safe to assume that subsequent
725 * lookups with a different attachment state will hit unflushed cache
726 * entries. That is, the CCU needs to be flushed and possibly invalidated
727 * when accessing memory with a different attachment state. Writing to an
728 * attachment under the following conditions after clearing using the
729 * normal 2d engine path is known to have issues:
731 * - It isn't the 0'th layer.
732 * - There are more than one attachment, and this isn't the 0'th attachment
733 * (this seems to also depend on the cpp of the attachments).
735 * Our best guess is that the layer/MRT state is used when computing
736 * the location of a cache entry in CCU, to avoid conflicts. We assume that
737 * any access in a renderpass after or before an access by a transfer needs
738 * a flush/invalidate, and use the _INCOHERENT variants to represent access
741 TU_ACCESS_CCU_COLOR_INCOHERENT_READ
= 1 << 6,
742 TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
= 1 << 7,
743 TU_ACCESS_CCU_DEPTH_INCOHERENT_READ
= 1 << 8,
744 TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE
= 1 << 9,
746 /* Accesses by the host */
747 TU_ACCESS_HOST_READ
= 1 << 10,
748 TU_ACCESS_HOST_WRITE
= 1 << 11,
750 /* Accesses by a GPU engine which bypasses any cache. e.g. writes via
751 * CP_EVENT_WRITE::BLIT and the CP are SYSMEM_WRITE.
753 TU_ACCESS_SYSMEM_READ
= 1 << 12,
754 TU_ACCESS_SYSMEM_WRITE
= 1 << 13,
756 /* Set if a WFI is required. This can be required for:
757 * - 2D engine which (on some models) doesn't wait for flushes to complete
759 * - CP draw indirect opcodes, where we need to wait for any flushes to
760 * complete but the CP implicitly waits for WFI's to complete and
761 * therefore we only need a WFI after the flushes.
763 TU_ACCESS_WFI_READ
= 1 << 14,
765 /* Set if a CP_WAIT_FOR_ME is required due to the data being read by the CP
766 * without it waiting for any WFI.
768 TU_ACCESS_WFM_READ
= 1 << 15,
770 /* Memory writes from the CP start in-order with draws and event writes,
771 * but execute asynchronously and hence need a CP_WAIT_MEM_WRITES if read.
773 TU_ACCESS_CP_WRITE
= 1 << 16,
776 TU_ACCESS_UCHE_READ
|
777 TU_ACCESS_CCU_COLOR_READ
|
778 TU_ACCESS_CCU_DEPTH_READ
|
779 TU_ACCESS_CCU_COLOR_INCOHERENT_READ
|
780 TU_ACCESS_CCU_DEPTH_INCOHERENT_READ
|
781 TU_ACCESS_HOST_READ
|
782 TU_ACCESS_SYSMEM_READ
|
787 TU_ACCESS_UCHE_WRITE
|
788 TU_ACCESS_CCU_COLOR_WRITE
|
789 TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
|
790 TU_ACCESS_CCU_DEPTH_WRITE
|
791 TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE
|
792 TU_ACCESS_HOST_WRITE
|
793 TU_ACCESS_SYSMEM_WRITE
|
801 enum tu_cmd_flush_bits
{
802 TU_CMD_FLAG_CCU_FLUSH_DEPTH
= 1 << 0,
803 TU_CMD_FLAG_CCU_FLUSH_COLOR
= 1 << 1,
804 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
= 1 << 2,
805 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
= 1 << 3,
806 TU_CMD_FLAG_CACHE_FLUSH
= 1 << 4,
807 TU_CMD_FLAG_CACHE_INVALIDATE
= 1 << 5,
808 TU_CMD_FLAG_WAIT_MEM_WRITES
= 1 << 6,
809 TU_CMD_FLAG_WAIT_FOR_IDLE
= 1 << 7,
810 TU_CMD_FLAG_WAIT_FOR_ME
= 1 << 8,
812 TU_CMD_FLAG_ALL_FLUSH
=
813 TU_CMD_FLAG_CCU_FLUSH_DEPTH
|
814 TU_CMD_FLAG_CCU_FLUSH_COLOR
|
815 TU_CMD_FLAG_CACHE_FLUSH
|
816 /* Treat the CP as a sort of "cache" which may need to be "flushed" via
817 * waiting for writes to land with WAIT_FOR_MEM_WRITES.
819 TU_CMD_FLAG_WAIT_MEM_WRITES
,
821 TU_CMD_FLAG_GPU_INVALIDATE
=
822 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
|
823 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
|
824 TU_CMD_FLAG_CACHE_INVALIDATE
,
826 TU_CMD_FLAG_ALL_INVALIDATE
=
827 TU_CMD_FLAG_GPU_INVALIDATE
|
828 /* Treat the CP as a sort of "cache" which may need to be "invalidated"
829 * via waiting for UCHE/CCU flushes to land with WFI/WFM.
831 TU_CMD_FLAG_WAIT_FOR_IDLE
|
832 TU_CMD_FLAG_WAIT_FOR_ME
,
835 /* Changing the CCU from sysmem mode to gmem mode or vice-versa is pretty
836 * heavy, involving a CCU cache flush/invalidate and a WFI in order to change
837 * which part of the gmem is used by the CCU. Here we keep track of what the
840 enum tu_cmd_ccu_state
{
846 struct tu_cache_state
{
847 /* Caches which must be made available (flushed) eventually if there are
848 * any users outside that cache domain, and caches which must be
849 * invalidated eventually if there are any reads.
851 enum tu_cmd_flush_bits pending_flush_bits
;
852 /* Pending flushes */
853 enum tu_cmd_flush_bits flush_bits
;
860 struct tu_pipeline
*pipeline
;
861 struct tu_pipeline
*compute_pipeline
;
866 struct tu_buffer
*buffers
[MAX_VBS
];
867 VkDeviceSize offsets
[MAX_VBS
];
870 /* for dynamic states that can't be emitted directly */
871 uint32_t dynamic_stencil_mask
;
872 uint32_t dynamic_stencil_wrmask
;
873 uint32_t dynamic_stencil_ref
;
874 uint32_t dynamic_gras_su_cntl
;
876 /* saved states to re-emit in TU_CMD_DIRTY_DRAW_STATE case */
877 struct tu_draw_state dynamic_state
[TU_DYNAMIC_STATE_COUNT
];
878 struct tu_draw_state vertex_buffers
;
879 struct tu_draw_state shader_const
[MESA_SHADER_STAGES
];
880 struct tu_draw_state desc_sets
;
882 struct tu_draw_state vs_params
;
886 uint32_t max_index_count
;
889 /* because streamout base has to be 32-byte aligned
890 * there is an extra offset to deal with when it is
893 uint8_t streamout_offset
[IR3_MAX_SO_BUFFERS
];
895 /* Renderpasses are tricky, because we may need to flush differently if
896 * using sysmem vs. gmem and therefore we have to delay any flushing that
897 * happens before a renderpass. So we have to have two copies of the flush
898 * state, one for intra-renderpass flushes (i.e. renderpass dependencies)
899 * and one for outside a renderpass.
901 struct tu_cache_state cache
;
902 struct tu_cache_state renderpass_cache
;
904 enum tu_cmd_ccu_state ccu_state
;
906 const struct tu_render_pass
*pass
;
907 const struct tu_subpass
*subpass
;
908 const struct tu_framebuffer
*framebuffer
;
909 VkRect2D render_area
;
911 struct tu_cs_entry tile_store_ib
;
915 bool has_subpass_predication
;
916 bool predication_active
;
921 struct vk_object_base base
;
923 VkAllocationCallbacks alloc
;
924 struct list_head cmd_buffers
;
925 struct list_head free_cmd_buffers
;
926 uint32_t queue_family_index
;
929 struct tu_cmd_buffer_upload
934 struct list_head list
;
937 enum tu_cmd_buffer_status
939 TU_CMD_BUFFER_STATUS_INVALID
,
940 TU_CMD_BUFFER_STATUS_INITIAL
,
941 TU_CMD_BUFFER_STATUS_RECORDING
,
942 TU_CMD_BUFFER_STATUS_EXECUTABLE
,
943 TU_CMD_BUFFER_STATUS_PENDING
,
946 #ifndef MSM_SUBMIT_BO_READ
947 #define MSM_SUBMIT_BO_READ 0x0001
948 #define MSM_SUBMIT_BO_WRITE 0x0002
949 #define MSM_SUBMIT_BO_DUMP 0x0004
951 struct drm_msm_gem_submit_bo
{
952 uint32_t flags
; /* in, mask of MSM_SUBMIT_BO_x */
953 uint32_t handle
; /* in, GEM handle */
954 uint64_t presumed
; /* in/out, presumed buffer address */
962 struct drm_msm_gem_submit_bo
*bo_infos
;
965 #define TU_BO_LIST_FAILED (~0)
968 tu_bo_list_init(struct tu_bo_list
*list
);
970 tu_bo_list_destroy(struct tu_bo_list
*list
);
972 tu_bo_list_reset(struct tu_bo_list
*list
);
974 tu_bo_list_add(struct tu_bo_list
*list
,
975 const struct tu_bo
*bo
,
978 tu_bo_list_merge(struct tu_bo_list
*list
, const struct tu_bo_list
*other
);
982 struct vk_object_base base
;
984 struct tu_device
*device
;
986 struct tu_cmd_pool
*pool
;
987 struct list_head pool_link
;
989 VkCommandBufferUsageFlags usage_flags
;
990 VkCommandBufferLevel level
;
991 enum tu_cmd_buffer_status status
;
993 struct tu_cmd_state state
;
994 struct tu_vertex_binding vertex_bindings
[MAX_VBS
];
995 uint32_t vertex_bindings_set
;
996 uint32_t queue_family_index
;
998 uint32_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
/ 4];
999 VkShaderStageFlags push_constant_stages
;
1000 struct tu_descriptor_set meta_push_descriptors
;
1002 struct tu_descriptor_state descriptors
[MAX_BIND_POINTS
];
1004 struct tu_cmd_buffer_upload upload
;
1006 VkResult record_result
;
1008 struct tu_bo_list bo_list
;
1010 struct tu_cs draw_cs
;
1011 struct tu_cs draw_epilogue_cs
;
1012 struct tu_cs sub_cs
;
1014 uint32_t vsc_draw_strm_pitch
;
1015 uint32_t vsc_prim_strm_pitch
;
1018 /* Temporary struct for tracking a register state to be written, used by
1019 * a6xx-pack.h and tu_cs_emit_regs()
1021 struct tu_reg_value
{
1032 void tu_emit_cache_flush_renderpass(struct tu_cmd_buffer
*cmd_buffer
,
1035 void tu_emit_cache_flush_ccu(struct tu_cmd_buffer
*cmd_buffer
,
1037 enum tu_cmd_ccu_state ccu_state
);
1040 tu6_emit_event_write(struct tu_cmd_buffer
*cmd
,
1042 enum vgt_event_type event
);
1044 static inline struct tu_descriptor_state
*
1045 tu_get_descriptors_state(struct tu_cmd_buffer
*cmd_buffer
,
1046 VkPipelineBindPoint bind_point
)
1048 return &cmd_buffer
->descriptors
[bind_point
];
1053 struct vk_object_base base
;
1057 struct tu_shader_module
1059 struct vk_object_base base
;
1061 unsigned char sha1
[20];
1064 const uint32_t *code
[0];
1067 struct tu_push_constant_range
1075 struct ir3_shader
*ir3_shader
;
1077 struct tu_push_constant_range push_consts
;
1078 uint8_t active_desc_sets
;
1082 tu_shader_create(struct tu_device
*dev
,
1083 gl_shader_stage stage
,
1084 const VkPipelineShaderStageCreateInfo
*stage_info
,
1085 struct tu_pipeline_layout
*layout
,
1086 const VkAllocationCallbacks
*alloc
);
1089 tu_shader_destroy(struct tu_device
*dev
,
1090 struct tu_shader
*shader
,
1091 const VkAllocationCallbacks
*alloc
);
1093 struct tu_program_descriptor_linkage
1095 struct ir3_const_state const_state
;
1099 struct tu_push_constant_range push_consts
;
1104 struct vk_object_base base
;
1108 struct tu_pipeline_layout
*layout
;
1110 bool need_indirect_descriptor_sets
;
1111 VkShaderStageFlags active_stages
;
1112 uint32_t active_desc_sets
;
1114 /* mask of enabled dynamic states
1115 * if BIT(i) is set, pipeline->dynamic_state[i] is *NOT* used
1117 uint32_t dynamic_state_mask
;
1118 struct tu_draw_state dynamic_state
[TU_DYNAMIC_STATE_COUNT
];
1120 /* gras_su_cntl without line width, used for dynamic line width state */
1121 uint32_t gras_su_cntl
;
1123 /* draw states for the pipeline */
1124 struct tu_draw_state load_state
, rast_state
, ds_state
, blend_state
;
1128 struct tu_draw_state state
;
1129 struct tu_draw_state binning_state
;
1131 struct tu_program_descriptor_linkage link
[MESA_SHADER_STAGES
];
1136 struct tu_draw_state state
;
1137 struct tu_draw_state binning_state
;
1138 uint32_t bindings_used
;
1143 enum pc_di_primtype primtype
;
1144 bool primitive_restart
;
1149 uint32_t patch_type
;
1150 uint32_t param_stride
;
1151 uint32_t hs_bo_regid
;
1152 uint32_t ds_bo_regid
;
1153 bool upper_left_domain_origin
;
1158 uint32_t local_size
[3];
1163 tu6_emit_viewport(struct tu_cs
*cs
, const VkViewport
*viewport
);
1166 tu6_emit_scissor(struct tu_cs
*cs
, const VkRect2D
*scissor
);
1169 tu6_emit_sample_locations(struct tu_cs
*cs
, const VkSampleLocationsInfoEXT
*samp_loc
);
1172 tu6_emit_depth_bias(struct tu_cs
*cs
,
1173 float constant_factor
,
1175 float slope_factor
);
1177 void tu6_emit_msaa(struct tu_cs
*cs
, VkSampleCountFlagBits samples
);
1179 void tu6_emit_window_scissor(struct tu_cs
*cs
, uint32_t x1
, uint32_t y1
, uint32_t x2
, uint32_t y2
);
1181 void tu6_emit_window_offset(struct tu_cs
*cs
, uint32_t x1
, uint32_t y1
);
1184 tu6_emit_xs_config(struct tu_cs
*cs
,
1185 gl_shader_stage stage
,
1186 const struct ir3_shader_variant
*xs
,
1187 uint64_t binary_iova
);
1190 tu6_emit_vpc(struct tu_cs
*cs
,
1191 const struct ir3_shader_variant
*vs
,
1192 const struct ir3_shader_variant
*hs
,
1193 const struct ir3_shader_variant
*ds
,
1194 const struct ir3_shader_variant
*gs
,
1195 const struct ir3_shader_variant
*fs
,
1196 uint32_t patch_control_points
,
1197 bool vshs_workgroup
);
1200 tu6_emit_fs_inputs(struct tu_cs
*cs
, const struct ir3_shader_variant
*fs
);
1202 struct tu_image_view
;
1205 tu_resolve_sysmem(struct tu_cmd_buffer
*cmd
,
1207 struct tu_image_view
*src
,
1208 struct tu_image_view
*dst
,
1210 const VkRect2D
*rect
);
1213 tu_clear_sysmem_attachment(struct tu_cmd_buffer
*cmd
,
1216 const VkRenderPassBeginInfo
*info
);
1219 tu_clear_gmem_attachment(struct tu_cmd_buffer
*cmd
,
1222 const VkRenderPassBeginInfo
*info
);
1225 tu_load_gmem_attachment(struct tu_cmd_buffer
*cmd
,
1230 /* expose this function to be able to emit load without checking LOAD_OP */
1232 tu_emit_load_gmem_attachment(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
, uint32_t a
);
1234 /* note: gmem store can also resolve */
1236 tu_store_gmem_attachment(struct tu_cmd_buffer
*cmd
,
1241 enum tu_supported_formats
{
1247 struct tu_native_format
1249 enum a6xx_format fmt
: 8;
1250 enum a3xx_color_swap swap
: 8;
1251 enum a6xx_tile_mode tile_mode
: 8;
1252 enum tu_supported_formats supported
: 8;
1255 struct tu_native_format
tu6_format_vtx(VkFormat format
);
1256 struct tu_native_format
tu6_format_color(VkFormat format
, enum a6xx_tile_mode tile_mode
);
1257 struct tu_native_format
tu6_format_texture(VkFormat format
, enum a6xx_tile_mode tile_mode
);
1259 static inline enum a6xx_format
1260 tu6_base_format(VkFormat format
)
1262 /* note: tu6_format_color doesn't care about tiling for .fmt field */
1263 return tu6_format_color(format
, TILE6_LINEAR
).fmt
;
1268 struct vk_object_base base
;
1271 /* The original VkFormat provided by the client. This may not match any
1272 * of the actual surface formats.
1275 VkImageAspectFlags aspects
;
1276 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1277 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1278 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1280 uint32_t level_count
;
1281 uint32_t layer_count
;
1282 VkSampleCountFlagBits samples
;
1284 struct fdl_layout layout
[3];
1285 uint32_t total_size
;
1287 unsigned queue_family_mask
;
1291 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1292 VkDeviceMemory owned_memory
;
1294 /* Set when bound */
1296 VkDeviceSize bo_offset
;
1299 static inline uint32_t
1300 tu_get_layerCount(const struct tu_image
*image
,
1301 const VkImageSubresourceRange
*range
)
1303 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
1304 ? image
->layer_count
- range
->baseArrayLayer
1305 : range
->layerCount
;
1308 static inline uint32_t
1309 tu_get_levelCount(const struct tu_image
*image
,
1310 const VkImageSubresourceRange
*range
)
1312 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
1313 ? image
->level_count
- range
->baseMipLevel
1314 : range
->levelCount
;
1317 struct tu_image_view
1319 struct vk_object_base base
;
1321 struct tu_image
*image
; /**< VkImageViewCreateInfo::image */
1325 uint32_t layer_size
;
1326 uint32_t ubwc_layer_size
;
1328 /* used to determine if fast gmem store path can be used */
1334 uint32_t descriptor
[A6XX_TEX_CONST_DWORDS
];
1336 /* Descriptor for use as a storage image as opposed to a sampled image.
1337 * This has a few differences for cube maps (e.g. type).
1339 uint32_t storage_descriptor
[A6XX_TEX_CONST_DWORDS
];
1341 /* pre-filled register values */
1343 uint32_t FLAG_BUFFER_PITCH
;
1345 uint32_t RB_MRT_BUF_INFO
;
1346 uint32_t SP_FS_MRT_REG
;
1348 uint32_t SP_PS_2D_SRC_INFO
;
1349 uint32_t SP_PS_2D_SRC_SIZE
;
1351 uint32_t RB_2D_DST_INFO
;
1353 uint32_t RB_BLIT_DST_INFO
;
1355 /* for d32s8 separate stencil */
1356 uint64_t stencil_base_addr
;
1357 uint32_t stencil_layer_size
;
1358 uint32_t stencil_PITCH
;
1361 struct tu_sampler_ycbcr_conversion
{
1362 struct vk_object_base base
;
1365 VkSamplerYcbcrModelConversion ycbcr_model
;
1366 VkSamplerYcbcrRange ycbcr_range
;
1367 VkComponentMapping components
;
1368 VkChromaLocation chroma_offsets
[2];
1369 VkFilter chroma_filter
;
1373 struct vk_object_base base
;
1375 uint32_t descriptor
[A6XX_TEX_SAMP_DWORDS
];
1376 struct tu_sampler_ycbcr_conversion
*ycbcr_sampler
;
1380 tu_cs_image_ref(struct tu_cs
*cs
, const struct tu_image_view
*iview
, uint32_t layer
);
1383 tu_cs_image_ref_2d(struct tu_cs
*cs
, const struct tu_image_view
*iview
, uint32_t layer
, bool src
);
1386 tu_cs_image_flag_ref(struct tu_cs
*cs
, const struct tu_image_view
*iview
, uint32_t layer
);
1389 tu_cs_image_stencil_ref(struct tu_cs
*cs
, const struct tu_image_view
*iview
, uint32_t layer
);
1391 #define tu_image_view_stencil(iview, x) \
1392 ((iview->x & ~A6XX_##x##_COLOR_FORMAT__MASK) | A6XX_##x##_COLOR_FORMAT(FMT6_8_UINT))
1395 tu_image_create(VkDevice _device
,
1396 const VkImageCreateInfo
*pCreateInfo
,
1397 const VkAllocationCallbacks
*alloc
,
1400 const VkSubresourceLayout
*plane_layouts
);
1403 tu_image_from_gralloc(VkDevice device_h
,
1404 const VkImageCreateInfo
*base_info
,
1405 const VkNativeBufferANDROID
*gralloc_info
,
1406 const VkAllocationCallbacks
*alloc
,
1407 VkImage
*out_image_h
);
1410 tu_image_view_init(struct tu_image_view
*iview
,
1411 const VkImageViewCreateInfo
*pCreateInfo
,
1412 bool limited_z24s8
);
1414 struct tu_buffer_view
1416 struct vk_object_base base
;
1418 uint32_t descriptor
[A6XX_TEX_CONST_DWORDS
];
1420 struct tu_buffer
*buffer
;
1423 tu_buffer_view_init(struct tu_buffer_view
*view
,
1424 struct tu_device
*device
,
1425 const VkBufferViewCreateInfo
*pCreateInfo
);
1427 struct tu_attachment_info
1429 struct tu_image_view
*attachment
;
1432 struct tu_framebuffer
1434 struct vk_object_base base
;
1440 /* size of the first tile */
1442 /* number of tiles */
1443 VkExtent2D tile_count
;
1445 /* size of the first VSC pipe */
1447 /* number of VSC pipes */
1448 VkExtent2D pipe_count
;
1450 /* pipe register values */
1451 uint32_t pipe_config
[MAX_VSC_PIPES
];
1452 uint32_t pipe_sizes
[MAX_VSC_PIPES
];
1454 uint32_t attachment_count
;
1455 struct tu_attachment_info attachments
[0];
1459 tu_framebuffer_tiling_config(struct tu_framebuffer
*fb
,
1460 const struct tu_device
*device
,
1461 const struct tu_render_pass
*pass
);
1463 struct tu_subpass_barrier
{
1464 VkPipelineStageFlags src_stage_mask
;
1465 VkAccessFlags src_access_mask
;
1466 VkAccessFlags dst_access_mask
;
1467 bool incoherent_ccu_color
, incoherent_ccu_depth
;
1470 struct tu_subpass_attachment
1472 uint32_t attachment
;
1477 uint32_t input_count
;
1478 uint32_t color_count
;
1479 struct tu_subpass_attachment
*input_attachments
;
1480 struct tu_subpass_attachment
*color_attachments
;
1481 struct tu_subpass_attachment
*resolve_attachments
;
1482 struct tu_subpass_attachment depth_stencil_attachment
;
1484 VkSampleCountFlagBits samples
;
1487 uint32_t multiview_mask
;
1489 struct tu_subpass_barrier start_barrier
;
1492 struct tu_render_pass_attachment
1497 VkImageAspectFlags clear_mask
;
1498 uint32_t clear_views
;
1501 int32_t gmem_offset
;
1502 /* for D32S8 separate stencil: */
1505 int32_t gmem_offset_stencil
;
1508 struct tu_render_pass
1510 struct vk_object_base base
;
1512 uint32_t attachment_count
;
1513 uint32_t subpass_count
;
1514 uint32_t gmem_pixels
;
1515 uint32_t tile_align_w
;
1516 struct tu_subpass_attachment
*subpass_attachments
;
1517 struct tu_render_pass_attachment
*attachments
;
1518 struct tu_subpass_barrier end_barrier
;
1519 struct tu_subpass subpasses
[0];
1522 struct tu_query_pool
1524 struct vk_object_base base
;
1529 uint32_t pipeline_statistics
;
1533 enum tu_semaphore_kind
1536 TU_SEMAPHORE_SYNCOBJ
,
1539 struct tu_semaphore_part
1541 enum tu_semaphore_kind kind
;
1549 struct vk_object_base base
;
1551 struct tu_semaphore_part permanent
;
1552 struct tu_semaphore_part temporary
;
1556 tu_set_descriptor_set(struct tu_cmd_buffer
*cmd_buffer
,
1557 VkPipelineBindPoint bind_point
,
1558 struct tu_descriptor_set
*set
,
1562 tu_update_descriptor_sets(struct tu_device
*device
,
1563 struct tu_cmd_buffer
*cmd_buffer
,
1564 VkDescriptorSet overrideSet
,
1565 uint32_t descriptorWriteCount
,
1566 const VkWriteDescriptorSet
*pDescriptorWrites
,
1567 uint32_t descriptorCopyCount
,
1568 const VkCopyDescriptorSet
*pDescriptorCopies
);
1571 tu_update_descriptor_set_with_template(
1572 struct tu_device
*device
,
1573 struct tu_cmd_buffer
*cmd_buffer
,
1574 struct tu_descriptor_set
*set
,
1575 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
1579 tu_physical_device_init(struct tu_physical_device
*device
,
1580 struct tu_instance
*instance
);
1582 tu_enumerate_devices(struct tu_instance
*instance
);
1585 tu_drm_submitqueue_new(const struct tu_device
*dev
,
1587 uint32_t *queue_id
);
1590 tu_drm_submitqueue_close(const struct tu_device
*dev
, uint32_t queue_id
);
1592 #define TU_DEFINE_HANDLE_CASTS(__tu_type, __VkType) \
1594 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1596 return (struct __tu_type *) _handle; \
1599 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1601 return (__VkType) _obj; \
1604 #define TU_DEFINE_NONDISP_HANDLE_CASTS(__tu_type, __VkType) \
1606 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1608 return (struct __tu_type *) (uintptr_t) _handle; \
1611 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1613 return (__VkType)(uintptr_t) _obj; \
1616 #define TU_FROM_HANDLE(__tu_type, __name, __handle) \
1617 struct __tu_type *__name = __tu_type##_from_handle(__handle)
1619 TU_DEFINE_HANDLE_CASTS(tu_cmd_buffer
, VkCommandBuffer
)
1620 TU_DEFINE_HANDLE_CASTS(tu_device
, VkDevice
)
1621 TU_DEFINE_HANDLE_CASTS(tu_instance
, VkInstance
)
1622 TU_DEFINE_HANDLE_CASTS(tu_physical_device
, VkPhysicalDevice
)
1623 TU_DEFINE_HANDLE_CASTS(tu_queue
, VkQueue
)
1625 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_cmd_pool
, VkCommandPool
)
1626 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer
, VkBuffer
)
1627 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer_view
, VkBufferView
)
1628 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_pool
, VkDescriptorPool
)
1629 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set
, VkDescriptorSet
)
1630 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set_layout
,
1631 VkDescriptorSetLayout
)
1632 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_update_template
,
1633 VkDescriptorUpdateTemplate
)
1634 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_device_memory
, VkDeviceMemory
)
1635 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_fence
, VkFence
)
1636 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_event
, VkEvent
)
1637 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_framebuffer
, VkFramebuffer
)
1638 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image
, VkImage
)
1639 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image_view
, VkImageView
);
1640 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_cache
, VkPipelineCache
)
1641 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline
, VkPipeline
)
1642 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_layout
, VkPipelineLayout
)
1643 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_query_pool
, VkQueryPool
)
1644 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_render_pass
, VkRenderPass
)
1645 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_sampler
, VkSampler
)
1646 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_sampler_ycbcr_conversion
, VkSamplerYcbcrConversion
)
1647 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_shader_module
, VkShaderModule
)
1648 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_semaphore
, VkSemaphore
)
1650 #endif /* TU_PRIVATE_H */