2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
43 #define VG(x) ((void)0)
46 #include "c11/threads.h"
47 #include "main/macros.h"
48 #include "util/list.h"
49 #include "util/macros.h"
51 #include "vk_debug_report.h"
52 #include "wsi_common.h"
54 #include "drm-uapi/msm_drm.h"
55 #include "ir3/ir3_compiler.h"
56 #include "ir3/ir3_shader.h"
58 #include "adreno_common.xml.h"
59 #include "adreno_pm4.xml.h"
61 #include "fdl/freedreno_layout.h"
63 #include "tu_descriptor_set.h"
64 #include "tu_extensions.h"
67 /* Pre-declarations needed for WSI entrypoints */
70 typedef struct xcb_connection_t xcb_connection_t
;
71 typedef uint32_t xcb_visualid_t
;
72 typedef uint32_t xcb_window_t
;
74 #include <vulkan/vk_android_native_buffer.h>
75 #include <vulkan/vk_icd.h>
76 #include <vulkan/vulkan.h>
77 #include <vulkan/vulkan_intel.h>
79 #include "tu_entrypoints.h"
81 #include "vk_format.h"
84 #define MAX_VERTEX_ATTRIBS 32
86 #define MAX_VSC_PIPES 32
87 #define MAX_VIEWPORTS 1
88 #define MAX_SCISSORS 16
89 #define MAX_DISCARD_RECTANGLES 4
90 #define MAX_PUSH_CONSTANTS_SIZE 128
91 #define MAX_PUSH_DESCRIPTORS 32
92 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
93 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
94 #define MAX_DYNAMIC_BUFFERS \
95 (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
96 #define TU_MAX_DRM_DEVICES 8
98 #define MAX_BIND_POINTS 2 /* compute + graphics */
99 /* The Qualcomm driver exposes 0x20000058 */
100 #define MAX_STORAGE_BUFFER_RANGE 0x20000000
101 /* We use ldc for uniform buffer loads, just like the Qualcomm driver, so
102 * expose the same maximum range.
103 * TODO: The SIZE bitfield is 15 bits, and in 4-dword units, so the actual
104 * range might be higher.
106 #define MAX_UNIFORM_BUFFER_RANGE 0x10000
108 #define A6XX_TEX_CONST_DWORDS 16
109 #define A6XX_TEX_SAMP_DWORDS 4
111 #define tu_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
113 static inline uint32_t
114 tu_minify(uint32_t n
, uint32_t levels
)
116 if (unlikely(n
== 0))
119 return MAX2(n
>> levels
, 1);
122 #define for_each_bit(b, dword) \
123 for (uint32_t __dword = (dword); \
124 (b) = __builtin_ffs(__dword) - 1, __dword; __dword &= ~(1 << (b)))
126 #define typed_memcpy(dest, src, count) \
128 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
129 memcpy((dest), (src), (count) * sizeof(*(src))); \
132 #define COND(bool, val) ((bool) ? (val) : 0)
133 #define BIT(bit) (1u << (bit))
135 /* Whenever we generate an error, pass it through this function. Useful for
136 * debugging, where we can break on it. Only call at error site, not when
137 * propagating errors. Might be useful to plug in a stack trace here.
143 __vk_errorf(struct tu_instance
*instance
,
150 #define vk_error(instance, error) \
151 __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
152 #define vk_errorf(instance, error, format, ...) \
153 __vk_errorf(instance, error, __FILE__, __LINE__, format, ##__VA_ARGS__);
156 __tu_finishme(const char *file
, int line
, const char *format
, ...)
159 tu_loge(const char *format
, ...) tu_printflike(1, 2);
161 tu_logi(const char *format
, ...) tu_printflike(1, 2);
164 * Print a FINISHME message, including its source location.
166 #define tu_finishme(format, ...) \
168 static bool reported = false; \
170 __tu_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
177 tu_finishme("stub %s", __func__); \
181 tu_lookup_entrypoint_unchecked(const char *name
);
183 tu_lookup_entrypoint_checked(
185 uint32_t core_version
,
186 const struct tu_instance_extension_table
*instance
,
187 const struct tu_device_extension_table
*device
);
189 struct tu_physical_device
191 VK_LOADER_DATA _loader_data
;
193 struct tu_instance
*instance
;
196 char name
[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE
];
197 uint8_t driver_uuid
[VK_UUID_SIZE
];
198 uint8_t device_uuid
[VK_UUID_SIZE
];
199 uint8_t cache_uuid
[VK_UUID_SIZE
];
201 struct wsi_device wsi_device
;
209 uint32_t ccu_offset_gmem
;
210 uint32_t ccu_offset_bypass
;
211 /* alignment for size of tiles */
212 uint32_t tile_align_w
;
213 #define TILE_ALIGN_H 16
214 /* gmem store/load granularity */
215 #define GMEM_ALIGN_W 16
216 #define GMEM_ALIGN_H 4
219 uint32_t PC_UNKNOWN_9805
;
220 uint32_t SP_UNKNOWN_A0F8
;
223 int msm_major_version
;
224 int msm_minor_version
;
226 /* This is the drivers on-disk cache used as a fallback as opposed to
227 * the pipeline cache defined by apps.
229 struct disk_cache
*disk_cache
;
231 struct tu_device_extension_table supported_extensions
;
236 TU_DEBUG_STARTUP
= 1 << 0,
237 TU_DEBUG_NIR
= 1 << 1,
238 TU_DEBUG_IR3
= 1 << 2,
239 TU_DEBUG_NOBIN
= 1 << 3,
240 TU_DEBUG_SYSMEM
= 1 << 4,
241 TU_DEBUG_FORCEBIN
= 1 << 5,
242 TU_DEBUG_NOUBWC
= 1 << 6,
247 VK_LOADER_DATA _loader_data
;
249 VkAllocationCallbacks alloc
;
251 uint32_t api_version
;
252 int physical_device_count
;
253 struct tu_physical_device physical_devices
[TU_MAX_DRM_DEVICES
];
255 enum tu_debug_flags debug_flags
;
257 struct vk_debug_report_instance debug_report_callbacks
;
259 struct tu_instance_extension_table enabled_extensions
;
263 tu_wsi_init(struct tu_physical_device
*physical_device
);
265 tu_wsi_finish(struct tu_physical_device
*physical_device
);
268 tu_instance_extension_supported(const char *name
);
270 tu_physical_device_api_version(struct tu_physical_device
*dev
);
272 tu_physical_device_extension_supported(struct tu_physical_device
*dev
,
277 struct tu_pipeline_cache
279 struct tu_device
*device
;
280 pthread_mutex_t mutex
;
284 uint32_t kernel_count
;
285 struct cache_entry
**hash_table
;
288 VkAllocationCallbacks alloc
;
291 struct tu_pipeline_key
297 #define TU_QUEUE_GENERAL 0
299 #define TU_MAX_QUEUE_FAMILIES 1
303 struct wsi_fence
*fence_wsi
;
309 tu_fence_init(struct tu_fence
*fence
, bool signaled
);
311 tu_fence_finish(struct tu_fence
*fence
);
313 tu_fence_update_fd(struct tu_fence
*fence
, int fd
);
315 tu_fence_copy(struct tu_fence
*fence
, const struct tu_fence
*src
);
317 tu_fence_signal(struct tu_fence
*fence
);
319 tu_fence_wait_idle(struct tu_fence
*fence
);
323 VK_LOADER_DATA _loader_data
;
324 struct tu_device
*device
;
325 uint32_t queue_family_index
;
327 VkDeviceQueueCreateFlags flags
;
329 uint32_t msm_queue_id
;
330 struct tu_fence submit_fence
;
343 VK_LOADER_DATA _loader_data
;
345 VkAllocationCallbacks alloc
;
347 struct tu_instance
*instance
;
349 struct tu_queue
*queues
[TU_MAX_QUEUE_FAMILIES
];
350 int queue_count
[TU_MAX_QUEUE_FAMILIES
];
352 struct tu_physical_device
*physical_device
;
354 struct ir3_compiler
*compiler
;
356 /* Backup in-memory cache to be used if the app doesn't provide one */
357 struct tu_pipeline_cache
*mem_cache
;
359 struct tu_bo vsc_draw_strm
;
360 struct tu_bo vsc_prim_strm
;
361 uint32_t vsc_draw_strm_pitch
;
362 uint32_t vsc_prim_strm_pitch
;
364 #define MIN_SCRATCH_BO_SIZE_LOG2 12 /* A page */
366 /* Currently the kernel driver uses a 32-bit GPU address space, but it
367 * should be impossible to go beyond 48 bits.
373 } scratch_bos
[48 - MIN_SCRATCH_BO_SIZE_LOG2
];
375 struct tu_bo border_color
;
377 struct tu_device_extension_table enabled_extensions
;
381 tu_bo_init_new(struct tu_device
*dev
, struct tu_bo
*bo
, uint64_t size
);
383 tu_bo_init_dmabuf(struct tu_device
*dev
,
388 tu_bo_export_dmabuf(struct tu_device
*dev
, struct tu_bo
*bo
);
390 tu_bo_finish(struct tu_device
*dev
, struct tu_bo
*bo
);
392 tu_bo_map(struct tu_device
*dev
, struct tu_bo
*bo
);
394 /* Get a scratch bo for use inside a command buffer. This will always return
395 * the same bo given the same size or similar sizes, so only one scratch bo
396 * can be used at the same time. It's meant for short-lived things where we
397 * need to write to some piece of memory, read from it, and then immediately
401 tu_get_scratch_bo(struct tu_device
*dev
, uint64_t size
, struct tu_bo
**bo
);
406 const struct tu_bo
*bo
;
412 struct tu_cs_memory
{
417 struct tu_draw_state
{
422 enum tu_dynamic_state
424 /* re-use VK_DYNAMIC_STATE_ enums for non-extended dynamic states */
425 TU_DYNAMIC_STATE_SAMPLE_LOCATIONS
= VK_DYNAMIC_STATE_STENCIL_REFERENCE
+ 1,
426 TU_DYNAMIC_STATE_COUNT
,
429 enum tu_draw_state_group_id
431 TU_DRAW_STATE_PROGRAM
,
432 TU_DRAW_STATE_PROGRAM_BINNING
,
436 TU_DRAW_STATE_VI_BINNING
,
440 TU_DRAW_STATE_VS_CONST
,
441 TU_DRAW_STATE_HS_CONST
,
442 TU_DRAW_STATE_DS_CONST
,
443 TU_DRAW_STATE_GS_CONST
,
444 TU_DRAW_STATE_FS_CONST
,
445 TU_DRAW_STATE_DESC_SETS
,
446 TU_DRAW_STATE_DESC_SETS_LOAD
,
447 TU_DRAW_STATE_VS_PARAMS
,
448 TU_DRAW_STATE_INPUT_ATTACHMENTS_GMEM
,
449 TU_DRAW_STATE_INPUT_ATTACHMENTS_SYSMEM
,
451 /* dynamic state related draw states */
452 TU_DRAW_STATE_DYNAMIC
,
453 TU_DRAW_STATE_COUNT
= TU_DRAW_STATE_DYNAMIC
+ TU_DYNAMIC_STATE_COUNT
,
460 * A command stream in TU_CS_MODE_GROW mode grows automatically whenever it
461 * is full. tu_cs_begin must be called before command packet emission and
462 * tu_cs_end must be called after.
464 * This mode may create multiple entries internally. The entries must be
465 * submitted together.
470 * A command stream in TU_CS_MODE_EXTERNAL mode wraps an external,
471 * fixed-size buffer. tu_cs_begin and tu_cs_end are optional and have no
474 * This mode does not create any entry or any BO.
479 * A command stream in TU_CS_MODE_SUB_STREAM mode does not support direct
480 * command packet emission. tu_cs_begin_sub_stream must be called to get a
481 * sub-stream to emit comamnd packets to. When done with the sub-stream,
482 * tu_cs_end_sub_stream must be called.
484 * This mode does not create any entry internally.
486 TU_CS_MODE_SUB_STREAM
,
493 uint32_t *reserved_end
;
496 struct tu_device
*device
;
497 enum tu_cs_mode mode
;
498 uint32_t next_bo_size
;
500 struct tu_cs_entry
*entries
;
501 uint32_t entry_count
;
502 uint32_t entry_capacity
;
506 uint32_t bo_capacity
;
508 /* state for cond_exec_start/cond_exec_end */
510 uint32_t *cond_dwords
;
513 struct tu_device_memory
518 /* for dedicated allocations */
519 struct tu_image
*image
;
520 struct tu_buffer
*buffer
;
527 struct tu_descriptor_range
533 struct tu_descriptor_set
535 const struct tu_descriptor_set_layout
*layout
;
536 struct tu_descriptor_pool
*pool
;
540 uint32_t *mapped_ptr
;
542 uint32_t *dynamic_descriptors
;
544 struct tu_bo
*buffers
[0];
547 struct tu_push_descriptor_set
549 struct tu_descriptor_set set
;
553 struct tu_descriptor_pool_entry
557 struct tu_descriptor_set
*set
;
560 struct tu_descriptor_pool
563 uint64_t current_offset
;
566 uint8_t *host_memory_base
;
567 uint8_t *host_memory_ptr
;
568 uint8_t *host_memory_end
;
570 uint32_t entry_count
;
571 uint32_t max_entry_count
;
572 struct tu_descriptor_pool_entry entries
[0];
575 struct tu_descriptor_update_template_entry
577 VkDescriptorType descriptor_type
;
579 /* The number of descriptors to update */
580 uint32_t descriptor_count
;
582 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array
586 /* In dwords. Not valid/used for dynamic descriptors */
589 uint32_t buffer_offset
;
591 /* Only valid for combined image samplers and samplers */
592 uint16_t has_sampler
;
598 /* For push descriptors */
599 const uint32_t *immutable_samplers
;
602 struct tu_descriptor_update_template
604 uint32_t entry_count
;
605 struct tu_descriptor_update_template_entry entry
[0];
612 VkBufferUsageFlags usage
;
613 VkBufferCreateFlags flags
;
616 VkDeviceSize bo_offset
;
619 static inline uint64_t
620 tu_buffer_iova(struct tu_buffer
*buffer
)
622 return buffer
->bo
->iova
+ buffer
->bo_offset
;
625 struct tu_vertex_binding
627 struct tu_buffer
*buffer
;
632 tu_get_debug_option_name(int id
);
635 tu_get_perftest_option_name(int id
);
637 struct tu_descriptor_state
639 struct tu_descriptor_set
*sets
[MAX_SETS
];
640 uint32_t dynamic_descriptors
[MAX_DYNAMIC_BUFFERS
* A6XX_TEX_CONST_DWORDS
];
651 struct tu_tiling_config
653 VkRect2D render_area
;
655 /* position and size of the first tile */
657 /* number of tiles */
658 VkExtent2D tile_count
;
660 /* size of the first VSC pipe */
662 /* number of VSC pipes */
663 VkExtent2D pipe_count
;
665 /* pipe register values */
666 uint32_t pipe_config
[MAX_VSC_PIPES
];
667 uint32_t pipe_sizes
[MAX_VSC_PIPES
];
669 /* Whether sysmem rendering must be used */
673 enum tu_cmd_dirty_bits
675 TU_CMD_DIRTY_COMPUTE_PIPELINE
= 1 << 1,
676 TU_CMD_DIRTY_VERTEX_BUFFERS
= 1 << 2,
677 TU_CMD_DIRTY_DESCRIPTOR_SETS
= 1 << 3,
678 TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
= 1 << 4,
679 TU_CMD_DIRTY_SHADER_CONSTS
= 1 << 5,
680 /* all draw states were disabled and need to be re-enabled: */
681 TU_CMD_DIRTY_DRAW_STATE
= 1 << 7,
684 /* There are only three cache domains we have to care about: the CCU, or
685 * color cache unit, which is used for color and depth/stencil attachments
686 * and copy/blit destinations, and is split conceptually into color and depth,
687 * and the universal cache or UCHE which is used for pretty much everything
688 * else, except for the CP (uncached) and host. We need to flush whenever data
689 * crosses these boundaries.
692 enum tu_cmd_access_mask
{
693 TU_ACCESS_UCHE_READ
= 1 << 0,
694 TU_ACCESS_UCHE_WRITE
= 1 << 1,
695 TU_ACCESS_CCU_COLOR_READ
= 1 << 2,
696 TU_ACCESS_CCU_COLOR_WRITE
= 1 << 3,
697 TU_ACCESS_CCU_DEPTH_READ
= 1 << 4,
698 TU_ACCESS_CCU_DEPTH_WRITE
= 1 << 5,
700 /* Experiments have shown that while it's safe to avoid flushing the CCU
701 * after each blit/renderpass, it's not safe to assume that subsequent
702 * lookups with a different attachment state will hit unflushed cache
703 * entries. That is, the CCU needs to be flushed and possibly invalidated
704 * when accessing memory with a different attachment state. Writing to an
705 * attachment under the following conditions after clearing using the
706 * normal 2d engine path is known to have issues:
708 * - It isn't the 0'th layer.
709 * - There are more than one attachment, and this isn't the 0'th attachment
710 * (this seems to also depend on the cpp of the attachments).
712 * Our best guess is that the layer/MRT state is used when computing
713 * the location of a cache entry in CCU, to avoid conflicts. We assume that
714 * any access in a renderpass after or before an access by a transfer needs
715 * a flush/invalidate, and use the _INCOHERENT variants to represent access
718 TU_ACCESS_CCU_COLOR_INCOHERENT_READ
= 1 << 6,
719 TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
= 1 << 7,
720 TU_ACCESS_CCU_DEPTH_INCOHERENT_READ
= 1 << 8,
721 TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE
= 1 << 9,
723 TU_ACCESS_SYSMEM_READ
= 1 << 10,
724 TU_ACCESS_SYSMEM_WRITE
= 1 << 11,
726 /* Set if a WFI is required due to data being read by the CP or the 2D
729 TU_ACCESS_WFI_READ
= 1 << 12,
732 TU_ACCESS_UCHE_READ
|
733 TU_ACCESS_CCU_COLOR_READ
|
734 TU_ACCESS_CCU_DEPTH_READ
|
735 TU_ACCESS_CCU_COLOR_INCOHERENT_READ
|
736 TU_ACCESS_CCU_DEPTH_INCOHERENT_READ
|
737 TU_ACCESS_SYSMEM_READ
,
740 TU_ACCESS_UCHE_WRITE
|
741 TU_ACCESS_CCU_COLOR_WRITE
|
742 TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
|
743 TU_ACCESS_CCU_DEPTH_WRITE
|
744 TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE
|
745 TU_ACCESS_SYSMEM_WRITE
,
752 enum tu_cmd_flush_bits
{
753 TU_CMD_FLAG_CCU_FLUSH_DEPTH
= 1 << 0,
754 TU_CMD_FLAG_CCU_FLUSH_COLOR
= 1 << 1,
755 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
= 1 << 2,
756 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
= 1 << 3,
757 TU_CMD_FLAG_CACHE_FLUSH
= 1 << 4,
758 TU_CMD_FLAG_CACHE_INVALIDATE
= 1 << 5,
760 TU_CMD_FLAG_ALL_FLUSH
=
761 TU_CMD_FLAG_CCU_FLUSH_DEPTH
|
762 TU_CMD_FLAG_CCU_FLUSH_COLOR
|
763 TU_CMD_FLAG_CACHE_FLUSH
,
765 TU_CMD_FLAG_ALL_INVALIDATE
=
766 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
|
767 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
|
768 TU_CMD_FLAG_CACHE_INVALIDATE
,
770 TU_CMD_FLAG_WFI
= 1 << 6,
773 /* Changing the CCU from sysmem mode to gmem mode or vice-versa is pretty
774 * heavy, involving a CCU cache flush/invalidate and a WFI in order to change
775 * which part of the gmem is used by the CCU. Here we keep track of what the
778 enum tu_cmd_ccu_state
{
784 struct tu_cache_state
{
785 /* Caches which must be made available (flushed) eventually if there are
786 * any users outside that cache domain, and caches which must be
787 * invalidated eventually if there are any reads.
789 enum tu_cmd_flush_bits pending_flush_bits
;
790 /* Pending flushes */
791 enum tu_cmd_flush_bits flush_bits
;
798 struct tu_pipeline
*pipeline
;
799 struct tu_pipeline
*compute_pipeline
;
804 struct tu_buffer
*buffers
[MAX_VBS
];
805 VkDeviceSize offsets
[MAX_VBS
];
808 /* for dynamic states that can't be emitted directly */
809 uint32_t dynamic_stencil_mask
;
810 uint32_t dynamic_stencil_wrmask
;
811 uint32_t dynamic_stencil_ref
;
812 uint32_t dynamic_gras_su_cntl
;
814 /* saved states to re-emit in TU_CMD_DIRTY_DRAW_STATE case */
815 struct tu_draw_state dynamic_state
[TU_DYNAMIC_STATE_COUNT
];
816 struct tu_cs_entry vertex_buffers_ib
;
817 struct tu_cs_entry shader_const_ib
[MESA_SHADER_STAGES
];
818 struct tu_cs_entry desc_sets_ib
, desc_sets_load_ib
;
819 struct tu_cs_entry ia_gmem_ib
, ia_sysmem_ib
;
821 struct tu_draw_state vs_params
;
825 uint32_t max_index_count
;
828 /* because streamout base has to be 32-byte aligned
829 * there is an extra offset to deal with when it is
832 uint8_t streamout_offset
[IR3_MAX_SO_BUFFERS
];
834 /* Renderpasses are tricky, because we may need to flush differently if
835 * using sysmem vs. gmem and therefore we have to delay any flushing that
836 * happens before a renderpass. So we have to have two copies of the flush
837 * state, one for intra-renderpass flushes (i.e. renderpass dependencies)
838 * and one for outside a renderpass.
840 struct tu_cache_state cache
;
841 struct tu_cache_state renderpass_cache
;
843 enum tu_cmd_ccu_state ccu_state
;
845 const struct tu_render_pass
*pass
;
846 const struct tu_subpass
*subpass
;
847 const struct tu_framebuffer
*framebuffer
;
849 struct tu_tiling_config tiling_config
;
851 struct tu_cs_entry tile_store_ib
;
858 VkAllocationCallbacks alloc
;
859 struct list_head cmd_buffers
;
860 struct list_head free_cmd_buffers
;
861 uint32_t queue_family_index
;
864 struct tu_cmd_buffer_upload
869 struct list_head list
;
872 enum tu_cmd_buffer_status
874 TU_CMD_BUFFER_STATUS_INVALID
,
875 TU_CMD_BUFFER_STATUS_INITIAL
,
876 TU_CMD_BUFFER_STATUS_RECORDING
,
877 TU_CMD_BUFFER_STATUS_EXECUTABLE
,
878 TU_CMD_BUFFER_STATUS_PENDING
,
885 struct drm_msm_gem_submit_bo
*bo_infos
;
888 #define TU_BO_LIST_FAILED (~0)
891 tu_bo_list_init(struct tu_bo_list
*list
);
893 tu_bo_list_destroy(struct tu_bo_list
*list
);
895 tu_bo_list_reset(struct tu_bo_list
*list
);
897 tu_bo_list_add(struct tu_bo_list
*list
,
898 const struct tu_bo
*bo
,
901 tu_bo_list_merge(struct tu_bo_list
*list
, const struct tu_bo_list
*other
);
903 /* This struct defines the layout of the scratch_bo */
906 uint32_t seqno_dummy
; /* dummy seqno for CP_EVENT_WRITE */
908 volatile uint32_t vsc_overflow
;
910 /* flag set from cmdstream when VSC overflow detected: */
911 uint32_t vsc_scratch
;
916 /* scratch space for VPC_SO[i].FLUSH_BASE_LO/HI, start on 32 byte boundary. */
923 #define ctrl_offset(member) offsetof(struct tu6_control, member)
927 VK_LOADER_DATA _loader_data
;
929 struct tu_device
*device
;
931 struct tu_cmd_pool
*pool
;
932 struct list_head pool_link
;
934 VkCommandBufferUsageFlags usage_flags
;
935 VkCommandBufferLevel level
;
936 enum tu_cmd_buffer_status status
;
938 struct tu_cmd_state state
;
939 struct tu_vertex_binding vertex_bindings
[MAX_VBS
];
940 uint32_t vertex_bindings_set
;
941 uint32_t queue_family_index
;
943 uint32_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
/ 4];
944 VkShaderStageFlags push_constant_stages
;
945 struct tu_descriptor_set meta_push_descriptors
;
947 struct tu_descriptor_state descriptors
[MAX_BIND_POINTS
];
949 struct tu_cmd_buffer_upload upload
;
951 VkResult record_result
;
953 struct tu_bo_list bo_list
;
955 struct tu_cs draw_cs
;
956 struct tu_cs draw_epilogue_cs
;
959 struct tu_bo scratch_bo
;
963 struct tu_bo vsc_draw_strm
;
964 struct tu_bo vsc_prim_strm
;
965 uint32_t vsc_draw_strm_pitch
;
966 uint32_t vsc_prim_strm_pitch
;
970 /* Temporary struct for tracking a register state to be written, used by
971 * a6xx-pack.h and tu_cs_emit_regs()
973 struct tu_reg_value
{
984 void tu_emit_cache_flush_renderpass(struct tu_cmd_buffer
*cmd_buffer
,
987 void tu_emit_cache_flush_ccu(struct tu_cmd_buffer
*cmd_buffer
,
989 enum tu_cmd_ccu_state ccu_state
);
992 tu6_emit_event_write(struct tu_cmd_buffer
*cmd
,
994 enum vgt_event_type event
);
996 static inline struct tu_descriptor_state
*
997 tu_get_descriptors_state(struct tu_cmd_buffer
*cmd_buffer
,
998 VkPipelineBindPoint bind_point
)
1000 return &cmd_buffer
->descriptors
[bind_point
];
1008 struct tu_shader_module
1010 unsigned char sha1
[20];
1013 const uint32_t *code
[0];
1016 struct tu_push_constant_range
1024 struct ir3_shader
*ir3_shader
;
1026 struct tu_push_constant_range push_consts
;
1027 uint8_t active_desc_sets
;
1031 tu_shader_create(struct tu_device
*dev
,
1032 gl_shader_stage stage
,
1033 const VkPipelineShaderStageCreateInfo
*stage_info
,
1034 struct tu_pipeline_layout
*layout
,
1035 const VkAllocationCallbacks
*alloc
);
1038 tu_shader_destroy(struct tu_device
*dev
,
1039 struct tu_shader
*shader
,
1040 const VkAllocationCallbacks
*alloc
);
1042 struct tu_program_descriptor_linkage
1044 struct ir3_const_state const_state
;
1048 struct tu_push_constant_range push_consts
;
1055 struct tu_pipeline_layout
*layout
;
1057 bool need_indirect_descriptor_sets
;
1058 VkShaderStageFlags active_stages
;
1059 uint32_t active_desc_sets
;
1061 /* mask of enabled dynamic states
1062 * if BIT(i) is set, pipeline->dynamic_state[i] is *NOT* used
1064 uint32_t dynamic_state_mask
;
1065 struct tu_draw_state dynamic_state
[TU_DYNAMIC_STATE_COUNT
];
1067 /* gras_su_cntl without line width, used for dynamic line width state */
1068 uint32_t gras_su_cntl
;
1072 struct tu_cs_entry state_ib
;
1073 struct tu_cs_entry binning_state_ib
;
1075 struct tu_program_descriptor_linkage link
[MESA_SHADER_STAGES
];
1080 struct tu_cs_entry state_ib
;
1085 struct tu_cs_entry state_ib
;
1086 struct tu_cs_entry binning_state_ib
;
1087 uint32_t bindings_used
;
1092 enum pc_di_primtype primtype
;
1093 bool primitive_restart
;
1098 uint32_t patch_type
;
1099 uint32_t per_vertex_output_size
;
1100 uint32_t per_patch_output_size
;
1101 uint32_t hs_bo_regid
;
1102 uint32_t ds_bo_regid
;
1103 bool upper_left_domain_origin
;
1108 struct tu_cs_entry state_ib
;
1113 struct tu_cs_entry state_ib
;
1118 struct tu_cs_entry state_ib
;
1123 uint32_t local_size
[3];
1128 tu6_emit_viewport(struct tu_cs
*cs
, const VkViewport
*viewport
);
1131 tu6_emit_scissor(struct tu_cs
*cs
, const VkRect2D
*scissor
);
1134 tu6_emit_sample_locations(struct tu_cs
*cs
, const VkSampleLocationsInfoEXT
*samp_loc
);
1137 tu6_emit_depth_bias(struct tu_cs
*cs
,
1138 float constant_factor
,
1140 float slope_factor
);
1142 void tu6_emit_msaa(struct tu_cs
*cs
, VkSampleCountFlagBits samples
);
1144 void tu6_emit_window_scissor(struct tu_cs
*cs
, uint32_t x1
, uint32_t y1
, uint32_t x2
, uint32_t y2
);
1146 void tu6_emit_window_offset(struct tu_cs
*cs
, uint32_t x1
, uint32_t y1
);
1149 tu6_emit_xs_config(struct tu_cs
*cs
,
1150 gl_shader_stage stage
,
1151 const struct ir3_shader_variant
*xs
,
1152 uint64_t binary_iova
);
1155 tu6_emit_vpc(struct tu_cs
*cs
,
1156 const struct ir3_shader_variant
*vs
,
1157 const struct ir3_shader_variant
*hs
,
1158 const struct ir3_shader_variant
*ds
,
1159 const struct ir3_shader_variant
*gs
,
1160 const struct ir3_shader_variant
*fs
);
1163 tu6_emit_fs_inputs(struct tu_cs
*cs
, const struct ir3_shader_variant
*fs
);
1165 struct tu_image_view
;
1168 tu_resolve_sysmem(struct tu_cmd_buffer
*cmd
,
1170 struct tu_image_view
*src
,
1171 struct tu_image_view
*dst
,
1173 const VkRect2D
*rect
);
1176 tu_clear_sysmem_attachment(struct tu_cmd_buffer
*cmd
,
1179 const VkRenderPassBeginInfo
*info
);
1182 tu_clear_gmem_attachment(struct tu_cmd_buffer
*cmd
,
1185 const VkRenderPassBeginInfo
*info
);
1188 tu_load_gmem_attachment(struct tu_cmd_buffer
*cmd
,
1193 /* expose this function to be able to emit load without checking LOAD_OP */
1195 tu_emit_load_gmem_attachment(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
, uint32_t a
);
1197 /* note: gmem store can also resolve */
1199 tu_store_gmem_attachment(struct tu_cmd_buffer
*cmd
,
1204 enum tu_supported_formats
{
1210 struct tu_native_format
1212 enum a6xx_format fmt
: 8;
1213 enum a3xx_color_swap swap
: 8;
1214 enum a6xx_tile_mode tile_mode
: 8;
1215 enum tu_supported_formats supported
: 8;
1218 struct tu_native_format
tu6_format_vtx(VkFormat format
);
1219 struct tu_native_format
tu6_format_color(VkFormat format
, enum a6xx_tile_mode tile_mode
);
1220 struct tu_native_format
tu6_format_texture(VkFormat format
, enum a6xx_tile_mode tile_mode
);
1222 static inline enum a6xx_format
1223 tu6_base_format(VkFormat format
)
1225 /* note: tu6_format_color doesn't care about tiling for .fmt field */
1226 return tu6_format_color(format
, TILE6_LINEAR
).fmt
;
1232 /* The original VkFormat provided by the client. This may not match any
1233 * of the actual surface formats.
1236 VkImageAspectFlags aspects
;
1237 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1238 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1239 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1241 uint32_t level_count
;
1242 uint32_t layer_count
;
1243 VkSampleCountFlagBits samples
;
1245 struct fdl_layout layout
;
1247 unsigned queue_family_mask
;
1251 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1252 VkDeviceMemory owned_memory
;
1254 /* Set when bound */
1256 VkDeviceSize bo_offset
;
1259 static inline uint32_t
1260 tu_get_layerCount(const struct tu_image
*image
,
1261 const VkImageSubresourceRange
*range
)
1263 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
1264 ? image
->layer_count
- range
->baseArrayLayer
1265 : range
->layerCount
;
1268 static inline uint32_t
1269 tu_get_levelCount(const struct tu_image
*image
,
1270 const VkImageSubresourceRange
*range
)
1272 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
1273 ? image
->level_count
- range
->baseMipLevel
1274 : range
->levelCount
;
1277 struct tu_image_view
1279 struct tu_image
*image
; /**< VkImageViewCreateInfo::image */
1283 uint32_t layer_size
;
1284 uint32_t ubwc_layer_size
;
1286 /* used to determine if fast gmem store path can be used */
1292 uint32_t descriptor
[A6XX_TEX_CONST_DWORDS
];
1294 /* Descriptor for use as a storage image as opposed to a sampled image.
1295 * This has a few differences for cube maps (e.g. type).
1297 uint32_t storage_descriptor
[A6XX_TEX_CONST_DWORDS
];
1299 /* pre-filled register values */
1301 uint32_t FLAG_BUFFER_PITCH
;
1303 uint32_t RB_MRT_BUF_INFO
;
1304 uint32_t SP_FS_MRT_REG
;
1306 uint32_t SP_PS_2D_SRC_INFO
;
1307 uint32_t SP_PS_2D_SRC_SIZE
;
1309 uint32_t RB_2D_DST_INFO
;
1311 uint32_t RB_BLIT_DST_INFO
;
1314 struct tu_sampler_ycbcr_conversion
{
1316 VkSamplerYcbcrModelConversion ycbcr_model
;
1317 VkSamplerYcbcrRange ycbcr_range
;
1318 VkComponentMapping components
;
1319 VkChromaLocation chroma_offsets
[2];
1320 VkFilter chroma_filter
;
1324 uint32_t descriptor
[A6XX_TEX_SAMP_DWORDS
];
1325 struct tu_sampler_ycbcr_conversion
*ycbcr_sampler
;
1329 tu_cs_image_ref(struct tu_cs
*cs
, const struct tu_image_view
*iview
, uint32_t layer
);
1332 tu_cs_image_ref_2d(struct tu_cs
*cs
, const struct tu_image_view
*iview
, uint32_t layer
, bool src
);
1335 tu_cs_image_flag_ref(struct tu_cs
*cs
, const struct tu_image_view
*iview
, uint32_t layer
);
1338 tu_image_create(VkDevice _device
,
1339 const VkImageCreateInfo
*pCreateInfo
,
1340 const VkAllocationCallbacks
*alloc
,
1343 const VkSubresourceLayout
*plane_layouts
);
1346 tu_image_from_gralloc(VkDevice device_h
,
1347 const VkImageCreateInfo
*base_info
,
1348 const VkNativeBufferANDROID
*gralloc_info
,
1349 const VkAllocationCallbacks
*alloc
,
1350 VkImage
*out_image_h
);
1353 tu_image_view_init(struct tu_image_view
*view
,
1354 const VkImageViewCreateInfo
*pCreateInfo
);
1356 struct tu_buffer_view
1358 uint32_t descriptor
[A6XX_TEX_CONST_DWORDS
];
1360 struct tu_buffer
*buffer
;
1363 tu_buffer_view_init(struct tu_buffer_view
*view
,
1364 struct tu_device
*device
,
1365 const VkBufferViewCreateInfo
*pCreateInfo
);
1367 struct tu_attachment_info
1369 struct tu_image_view
*attachment
;
1372 struct tu_framebuffer
1378 uint32_t attachment_count
;
1379 struct tu_attachment_info attachments
[0];
1382 struct tu_subpass_barrier
{
1383 VkPipelineStageFlags src_stage_mask
;
1384 VkAccessFlags src_access_mask
;
1385 VkAccessFlags dst_access_mask
;
1386 bool incoherent_ccu_color
, incoherent_ccu_depth
;
1389 struct tu_subpass_attachment
1391 uint32_t attachment
;
1396 uint32_t input_count
;
1397 uint32_t color_count
;
1398 struct tu_subpass_attachment
*input_attachments
;
1399 struct tu_subpass_attachment
*color_attachments
;
1400 struct tu_subpass_attachment
*resolve_attachments
;
1401 struct tu_subpass_attachment depth_stencil_attachment
;
1403 VkSampleCountFlagBits samples
;
1407 struct tu_subpass_barrier start_barrier
;
1410 struct tu_render_pass_attachment
1415 VkImageAspectFlags clear_mask
;
1418 int32_t gmem_offset
;
1421 struct tu_render_pass
1423 uint32_t attachment_count
;
1424 uint32_t subpass_count
;
1425 uint32_t gmem_pixels
;
1426 uint32_t tile_align_w
;
1427 struct tu_subpass_attachment
*subpass_attachments
;
1428 struct tu_render_pass_attachment
*attachments
;
1429 struct tu_subpass_barrier end_barrier
;
1430 struct tu_subpass subpasses
[0];
1433 struct tu_query_pool
1438 uint32_t pipeline_statistics
;
1442 enum tu_semaphore_kind
1445 TU_SEMAPHORE_SYNCOBJ
,
1448 struct tu_semaphore_part
1450 enum tu_semaphore_kind kind
;
1458 struct tu_semaphore_part permanent
;
1459 struct tu_semaphore_part temporary
;
1463 tu_set_descriptor_set(struct tu_cmd_buffer
*cmd_buffer
,
1464 VkPipelineBindPoint bind_point
,
1465 struct tu_descriptor_set
*set
,
1469 tu_update_descriptor_sets(struct tu_device
*device
,
1470 struct tu_cmd_buffer
*cmd_buffer
,
1471 VkDescriptorSet overrideSet
,
1472 uint32_t descriptorWriteCount
,
1473 const VkWriteDescriptorSet
*pDescriptorWrites
,
1474 uint32_t descriptorCopyCount
,
1475 const VkCopyDescriptorSet
*pDescriptorCopies
);
1478 tu_update_descriptor_set_with_template(
1479 struct tu_device
*device
,
1480 struct tu_cmd_buffer
*cmd_buffer
,
1481 struct tu_descriptor_set
*set
,
1482 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
1486 tu_drm_get_gpu_id(const struct tu_physical_device
*dev
, uint32_t *id
);
1489 tu_drm_get_gmem_size(const struct tu_physical_device
*dev
, uint32_t *size
);
1492 tu_drm_get_gmem_base(const struct tu_physical_device
*dev
, uint64_t *base
);
1495 tu_drm_submitqueue_new(const struct tu_device
*dev
,
1497 uint32_t *queue_id
);
1500 tu_drm_submitqueue_close(const struct tu_device
*dev
, uint32_t queue_id
);
1503 tu_gem_new(const struct tu_device
*dev
, uint64_t size
, uint32_t flags
);
1505 tu_gem_import_dmabuf(const struct tu_device
*dev
,
1509 tu_gem_export_dmabuf(const struct tu_device
*dev
, uint32_t gem_handle
);
1511 tu_gem_close(const struct tu_device
*dev
, uint32_t gem_handle
);
1513 tu_gem_info_offset(const struct tu_device
*dev
, uint32_t gem_handle
);
1515 tu_gem_info_iova(const struct tu_device
*dev
, uint32_t gem_handle
);
1517 #define TU_DEFINE_HANDLE_CASTS(__tu_type, __VkType) \
1519 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1521 return (struct __tu_type *) _handle; \
1524 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1526 return (__VkType) _obj; \
1529 #define TU_DEFINE_NONDISP_HANDLE_CASTS(__tu_type, __VkType) \
1531 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1533 return (struct __tu_type *) (uintptr_t) _handle; \
1536 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1538 return (__VkType)(uintptr_t) _obj; \
1541 #define TU_FROM_HANDLE(__tu_type, __name, __handle) \
1542 struct __tu_type *__name = __tu_type##_from_handle(__handle)
1544 TU_DEFINE_HANDLE_CASTS(tu_cmd_buffer
, VkCommandBuffer
)
1545 TU_DEFINE_HANDLE_CASTS(tu_device
, VkDevice
)
1546 TU_DEFINE_HANDLE_CASTS(tu_instance
, VkInstance
)
1547 TU_DEFINE_HANDLE_CASTS(tu_physical_device
, VkPhysicalDevice
)
1548 TU_DEFINE_HANDLE_CASTS(tu_queue
, VkQueue
)
1550 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_cmd_pool
, VkCommandPool
)
1551 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer
, VkBuffer
)
1552 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer_view
, VkBufferView
)
1553 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_pool
, VkDescriptorPool
)
1554 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set
, VkDescriptorSet
)
1555 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set_layout
,
1556 VkDescriptorSetLayout
)
1557 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_update_template
,
1558 VkDescriptorUpdateTemplate
)
1559 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_device_memory
, VkDeviceMemory
)
1560 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_fence
, VkFence
)
1561 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_event
, VkEvent
)
1562 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_framebuffer
, VkFramebuffer
)
1563 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image
, VkImage
)
1564 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image_view
, VkImageView
);
1565 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_cache
, VkPipelineCache
)
1566 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline
, VkPipeline
)
1567 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_layout
, VkPipelineLayout
)
1568 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_query_pool
, VkQueryPool
)
1569 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_render_pass
, VkRenderPass
)
1570 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_sampler
, VkSampler
)
1571 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_sampler_ycbcr_conversion
, VkSamplerYcbcrConversion
)
1572 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_shader_module
, VkShaderModule
)
1573 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_semaphore
, VkSemaphore
)
1575 #endif /* TU_PRIVATE_H */