b00e891a01a060712ccd4cee81dd2b0ac2847ca8
[mesa.git] / src / freedreno / vulkan / tu_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #ifndef TU_PRIVATE_H
29 #define TU_PRIVATE_H
30
31 #include <assert.h>
32 #include <pthread.h>
33 #include <stdbool.h>
34 #include <stdint.h>
35 #include <stdio.h>
36 #include <stdlib.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <memcheck.h>
40 #include <valgrind.h>
41 #define VG(x) x
42 #else
43 #define VG(x) ((void)0)
44 #endif
45
46 #include "c11/threads.h"
47 #include "main/macros.h"
48 #include "util/list.h"
49 #include "util/macros.h"
50 #include "vk_alloc.h"
51 #include "vk_debug_report.h"
52 #include "wsi_common.h"
53
54 #include "drm-uapi/msm_drm.h"
55 #include "ir3/ir3_compiler.h"
56 #include "ir3/ir3_shader.h"
57
58 #include "adreno_common.xml.h"
59 #include "adreno_pm4.xml.h"
60 #include "a6xx.xml.h"
61 #include "fdl/freedreno_layout.h"
62
63 #include "tu_descriptor_set.h"
64 #include "tu_extensions.h"
65 #include "tu_util.h"
66
67 /* Pre-declarations needed for WSI entrypoints */
68 struct wl_surface;
69 struct wl_display;
70 typedef struct xcb_connection_t xcb_connection_t;
71 typedef uint32_t xcb_visualid_t;
72 typedef uint32_t xcb_window_t;
73
74 #include <vulkan/vk_android_native_buffer.h>
75 #include <vulkan/vk_icd.h>
76 #include <vulkan/vulkan.h>
77 #include <vulkan/vulkan_intel.h>
78
79 #include "tu_entrypoints.h"
80
81 #include "vk_format.h"
82
83 #define MAX_VBS 32
84 #define MAX_VERTEX_ATTRIBS 32
85 #define MAX_RTS 8
86 #define MAX_VSC_PIPES 32
87 #define MAX_VIEWPORTS 1
88 #define MAX_SCISSORS 16
89 #define MAX_DISCARD_RECTANGLES 4
90 #define MAX_PUSH_CONSTANTS_SIZE 128
91 #define MAX_PUSH_DESCRIPTORS 32
92 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
93 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
94 #define MAX_DYNAMIC_BUFFERS \
95 (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
96 #define TU_MAX_DRM_DEVICES 8
97 #define MAX_VIEWS 8
98 #define MAX_BIND_POINTS 2 /* compute + graphics */
99 /* The Qualcomm driver exposes 0x20000058 */
100 #define MAX_STORAGE_BUFFER_RANGE 0x20000000
101 /* We use ldc for uniform buffer loads, just like the Qualcomm driver, so
102 * expose the same maximum range.
103 * TODO: The SIZE bitfield is 15 bits, and in 4-dword units, so the actual
104 * range might be higher.
105 */
106 #define MAX_UNIFORM_BUFFER_RANGE 0x10000
107
108 #define A6XX_TEX_CONST_DWORDS 16
109 #define A6XX_TEX_SAMP_DWORDS 4
110
111 #define tu_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
112
113 static inline uint32_t
114 tu_minify(uint32_t n, uint32_t levels)
115 {
116 if (unlikely(n == 0))
117 return 0;
118 else
119 return MAX2(n >> levels, 1);
120 }
121
122 #define for_each_bit(b, dword) \
123 for (uint32_t __dword = (dword); \
124 (b) = __builtin_ffs(__dword) - 1, __dword; __dword &= ~(1 << (b)))
125
126 #define typed_memcpy(dest, src, count) \
127 ({ \
128 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
129 memcpy((dest), (src), (count) * sizeof(*(src))); \
130 })
131
132 #define COND(bool, val) ((bool) ? (val) : 0)
133 #define BIT(bit) (1u << (bit))
134
135 /* Whenever we generate an error, pass it through this function. Useful for
136 * debugging, where we can break on it. Only call at error site, not when
137 * propagating errors. Might be useful to plug in a stack trace here.
138 */
139
140 struct tu_instance;
141
142 VkResult
143 __vk_errorf(struct tu_instance *instance,
144 VkResult error,
145 const char *file,
146 int line,
147 const char *format,
148 ...);
149
150 #define vk_error(instance, error) \
151 __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
152 #define vk_errorf(instance, error, format, ...) \
153 __vk_errorf(instance, error, __FILE__, __LINE__, format, ##__VA_ARGS__);
154
155 void
156 __tu_finishme(const char *file, int line, const char *format, ...)
157 tu_printflike(3, 4);
158 void
159 tu_loge(const char *format, ...) tu_printflike(1, 2);
160 void
161 tu_logi(const char *format, ...) tu_printflike(1, 2);
162
163 /**
164 * Print a FINISHME message, including its source location.
165 */
166 #define tu_finishme(format, ...) \
167 do { \
168 static bool reported = false; \
169 if (!reported) { \
170 __tu_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
171 reported = true; \
172 } \
173 } while (0)
174
175 #define tu_stub() \
176 do { \
177 tu_finishme("stub %s", __func__); \
178 } while (0)
179
180 void *
181 tu_lookup_entrypoint_unchecked(const char *name);
182 void *
183 tu_lookup_entrypoint_checked(
184 const char *name,
185 uint32_t core_version,
186 const struct tu_instance_extension_table *instance,
187 const struct tu_device_extension_table *device);
188
189 struct tu_physical_device
190 {
191 VK_LOADER_DATA _loader_data;
192
193 struct tu_instance *instance;
194
195 char path[20];
196 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
197 uint8_t driver_uuid[VK_UUID_SIZE];
198 uint8_t device_uuid[VK_UUID_SIZE];
199 uint8_t cache_uuid[VK_UUID_SIZE];
200
201 struct wsi_device wsi_device;
202
203 int local_fd;
204 int master_fd;
205
206 unsigned gpu_id;
207 uint32_t gmem_size;
208 uint64_t gmem_base;
209 uint32_t ccu_offset_gmem;
210 uint32_t ccu_offset_bypass;
211 /* alignment for size of tiles */
212 uint32_t tile_align_w;
213 #define TILE_ALIGN_H 16
214 /* gmem store/load granularity */
215 #define GMEM_ALIGN_W 16
216 #define GMEM_ALIGN_H 4
217
218 struct {
219 uint32_t PC_UNKNOWN_9805;
220 uint32_t SP_UNKNOWN_A0F8;
221 } magic;
222
223 /* This is the drivers on-disk cache used as a fallback as opposed to
224 * the pipeline cache defined by apps.
225 */
226 struct disk_cache *disk_cache;
227
228 struct tu_device_extension_table supported_extensions;
229 };
230
231 enum tu_debug_flags
232 {
233 TU_DEBUG_STARTUP = 1 << 0,
234 TU_DEBUG_NIR = 1 << 1,
235 TU_DEBUG_IR3 = 1 << 2,
236 TU_DEBUG_NOBIN = 1 << 3,
237 TU_DEBUG_SYSMEM = 1 << 4,
238 TU_DEBUG_FORCEBIN = 1 << 5,
239 TU_DEBUG_NOUBWC = 1 << 6,
240 };
241
242 struct tu_instance
243 {
244 VK_LOADER_DATA _loader_data;
245
246 VkAllocationCallbacks alloc;
247
248 uint32_t api_version;
249 int physical_device_count;
250 struct tu_physical_device physical_devices[TU_MAX_DRM_DEVICES];
251
252 enum tu_debug_flags debug_flags;
253
254 struct vk_debug_report_instance debug_report_callbacks;
255
256 struct tu_instance_extension_table enabled_extensions;
257 };
258
259 VkResult
260 tu_wsi_init(struct tu_physical_device *physical_device);
261 void
262 tu_wsi_finish(struct tu_physical_device *physical_device);
263
264 bool
265 tu_instance_extension_supported(const char *name);
266 uint32_t
267 tu_physical_device_api_version(struct tu_physical_device *dev);
268 bool
269 tu_physical_device_extension_supported(struct tu_physical_device *dev,
270 const char *name);
271
272 struct cache_entry;
273
274 struct tu_pipeline_cache
275 {
276 struct tu_device *device;
277 pthread_mutex_t mutex;
278
279 uint32_t total_size;
280 uint32_t table_size;
281 uint32_t kernel_count;
282 struct cache_entry **hash_table;
283 bool modified;
284
285 VkAllocationCallbacks alloc;
286 };
287
288 struct tu_pipeline_key
289 {
290 };
291
292
293 /* queue types */
294 #define TU_QUEUE_GENERAL 0
295
296 #define TU_MAX_QUEUE_FAMILIES 1
297
298 struct tu_fence
299 {
300 struct wsi_fence *fence_wsi;
301 bool signaled;
302 int fd;
303 };
304
305 void
306 tu_fence_init(struct tu_fence *fence, bool signaled);
307 void
308 tu_fence_finish(struct tu_fence *fence);
309 void
310 tu_fence_update_fd(struct tu_fence *fence, int fd);
311 void
312 tu_fence_copy(struct tu_fence *fence, const struct tu_fence *src);
313 void
314 tu_fence_signal(struct tu_fence *fence);
315 void
316 tu_fence_wait_idle(struct tu_fence *fence);
317
318 struct tu_queue
319 {
320 VK_LOADER_DATA _loader_data;
321 struct tu_device *device;
322 uint32_t queue_family_index;
323 int queue_idx;
324 VkDeviceQueueCreateFlags flags;
325
326 uint32_t msm_queue_id;
327 struct tu_fence submit_fence;
328 };
329
330 struct tu_bo
331 {
332 uint32_t gem_handle;
333 uint64_t size;
334 uint64_t iova;
335 void *map;
336 };
337
338 struct tu_device
339 {
340 VK_LOADER_DATA _loader_data;
341
342 VkAllocationCallbacks alloc;
343
344 struct tu_instance *instance;
345
346 struct tu_queue *queues[TU_MAX_QUEUE_FAMILIES];
347 int queue_count[TU_MAX_QUEUE_FAMILIES];
348
349 struct tu_physical_device *physical_device;
350
351 struct ir3_compiler *compiler;
352
353 /* Backup in-memory cache to be used if the app doesn't provide one */
354 struct tu_pipeline_cache *mem_cache;
355
356 struct tu_bo vsc_draw_strm;
357 struct tu_bo vsc_prim_strm;
358 uint32_t vsc_draw_strm_pitch;
359 uint32_t vsc_prim_strm_pitch;
360
361 #define MIN_SCRATCH_BO_SIZE_LOG2 12 /* A page */
362
363 /* Currently the kernel driver uses a 32-bit GPU address space, but it
364 * should be impossible to go beyond 48 bits.
365 */
366 struct {
367 struct tu_bo bo;
368 mtx_t construct_mtx;
369 bool initialized;
370 } scratch_bos[48 - MIN_SCRATCH_BO_SIZE_LOG2];
371
372 struct tu_bo border_color;
373
374 struct tu_device_extension_table enabled_extensions;
375 };
376
377 VkResult
378 tu_bo_init_new(struct tu_device *dev, struct tu_bo *bo, uint64_t size);
379 VkResult
380 tu_bo_init_dmabuf(struct tu_device *dev,
381 struct tu_bo *bo,
382 uint64_t size,
383 int fd);
384 int
385 tu_bo_export_dmabuf(struct tu_device *dev, struct tu_bo *bo);
386 void
387 tu_bo_finish(struct tu_device *dev, struct tu_bo *bo);
388 VkResult
389 tu_bo_map(struct tu_device *dev, struct tu_bo *bo);
390
391 /* Get a scratch bo for use inside a command buffer. This will always return
392 * the same bo given the same size or similar sizes, so only one scratch bo
393 * can be used at the same time. It's meant for short-lived things where we
394 * need to write to some piece of memory, read from it, and then immediately
395 * discard it.
396 */
397 VkResult
398 tu_get_scratch_bo(struct tu_device *dev, uint64_t size, struct tu_bo **bo);
399
400 struct tu_cs_entry
401 {
402 /* No ownership */
403 const struct tu_bo *bo;
404
405 uint32_t size;
406 uint32_t offset;
407 };
408
409 struct tu_cs_memory {
410 uint32_t *map;
411 uint64_t iova;
412 };
413
414 struct tu_draw_state {
415 uint64_t iova : 48;
416 uint32_t size : 16;
417 };
418
419 enum tu_dynamic_state
420 {
421 /* re-use VK_DYNAMIC_STATE_ enums for non-extended dynamic states */
422 TU_DYNAMIC_STATE_SAMPLE_LOCATIONS = VK_DYNAMIC_STATE_STENCIL_REFERENCE + 1,
423 TU_DYNAMIC_STATE_COUNT,
424 };
425
426 enum tu_draw_state_group_id
427 {
428 TU_DRAW_STATE_PROGRAM,
429 TU_DRAW_STATE_PROGRAM_BINNING,
430 TU_DRAW_STATE_TESS,
431 TU_DRAW_STATE_VB,
432 TU_DRAW_STATE_VI,
433 TU_DRAW_STATE_VI_BINNING,
434 TU_DRAW_STATE_RAST,
435 TU_DRAW_STATE_DS,
436 TU_DRAW_STATE_BLEND,
437 TU_DRAW_STATE_VS_CONST,
438 TU_DRAW_STATE_HS_CONST,
439 TU_DRAW_STATE_DS_CONST,
440 TU_DRAW_STATE_GS_CONST,
441 TU_DRAW_STATE_FS_CONST,
442 TU_DRAW_STATE_DESC_SETS,
443 TU_DRAW_STATE_DESC_SETS_LOAD,
444 TU_DRAW_STATE_VS_PARAMS,
445 TU_DRAW_STATE_INPUT_ATTACHMENTS_GMEM,
446 TU_DRAW_STATE_INPUT_ATTACHMENTS_SYSMEM,
447
448 /* dynamic state related draw states */
449 TU_DRAW_STATE_DYNAMIC,
450 TU_DRAW_STATE_COUNT = TU_DRAW_STATE_DYNAMIC + TU_DYNAMIC_STATE_COUNT,
451 };
452
453 enum tu_cs_mode
454 {
455
456 /*
457 * A command stream in TU_CS_MODE_GROW mode grows automatically whenever it
458 * is full. tu_cs_begin must be called before command packet emission and
459 * tu_cs_end must be called after.
460 *
461 * This mode may create multiple entries internally. The entries must be
462 * submitted together.
463 */
464 TU_CS_MODE_GROW,
465
466 /*
467 * A command stream in TU_CS_MODE_EXTERNAL mode wraps an external,
468 * fixed-size buffer. tu_cs_begin and tu_cs_end are optional and have no
469 * effect on it.
470 *
471 * This mode does not create any entry or any BO.
472 */
473 TU_CS_MODE_EXTERNAL,
474
475 /*
476 * A command stream in TU_CS_MODE_SUB_STREAM mode does not support direct
477 * command packet emission. tu_cs_begin_sub_stream must be called to get a
478 * sub-stream to emit comamnd packets to. When done with the sub-stream,
479 * tu_cs_end_sub_stream must be called.
480 *
481 * This mode does not create any entry internally.
482 */
483 TU_CS_MODE_SUB_STREAM,
484 };
485
486 struct tu_cs
487 {
488 uint32_t *start;
489 uint32_t *cur;
490 uint32_t *reserved_end;
491 uint32_t *end;
492
493 struct tu_device *device;
494 enum tu_cs_mode mode;
495 uint32_t next_bo_size;
496
497 struct tu_cs_entry *entries;
498 uint32_t entry_count;
499 uint32_t entry_capacity;
500
501 struct tu_bo **bos;
502 uint32_t bo_count;
503 uint32_t bo_capacity;
504
505 /* state for cond_exec_start/cond_exec_end */
506 uint32_t cond_flags;
507 uint32_t *cond_dwords;
508 };
509
510 struct tu_device_memory
511 {
512 struct tu_bo bo;
513 VkDeviceSize size;
514
515 /* for dedicated allocations */
516 struct tu_image *image;
517 struct tu_buffer *buffer;
518
519 uint32_t type_index;
520 void *map;
521 void *user_ptr;
522 };
523
524 struct tu_descriptor_range
525 {
526 uint64_t va;
527 uint32_t size;
528 };
529
530 struct tu_descriptor_set
531 {
532 const struct tu_descriptor_set_layout *layout;
533 struct tu_descriptor_pool *pool;
534 uint32_t size;
535
536 uint64_t va;
537 uint32_t *mapped_ptr;
538
539 uint32_t *dynamic_descriptors;
540
541 struct tu_bo *buffers[0];
542 };
543
544 struct tu_push_descriptor_set
545 {
546 struct tu_descriptor_set set;
547 uint32_t capacity;
548 };
549
550 struct tu_descriptor_pool_entry
551 {
552 uint32_t offset;
553 uint32_t size;
554 struct tu_descriptor_set *set;
555 };
556
557 struct tu_descriptor_pool
558 {
559 struct tu_bo bo;
560 uint64_t current_offset;
561 uint64_t size;
562
563 uint8_t *host_memory_base;
564 uint8_t *host_memory_ptr;
565 uint8_t *host_memory_end;
566
567 uint32_t entry_count;
568 uint32_t max_entry_count;
569 struct tu_descriptor_pool_entry entries[0];
570 };
571
572 struct tu_descriptor_update_template_entry
573 {
574 VkDescriptorType descriptor_type;
575
576 /* The number of descriptors to update */
577 uint32_t descriptor_count;
578
579 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array
580 */
581 uint32_t dst_offset;
582
583 /* In dwords. Not valid/used for dynamic descriptors */
584 uint32_t dst_stride;
585
586 uint32_t buffer_offset;
587
588 /* Only valid for combined image samplers and samplers */
589 uint16_t has_sampler;
590
591 /* In bytes */
592 size_t src_offset;
593 size_t src_stride;
594
595 /* For push descriptors */
596 const uint32_t *immutable_samplers;
597 };
598
599 struct tu_descriptor_update_template
600 {
601 uint32_t entry_count;
602 struct tu_descriptor_update_template_entry entry[0];
603 };
604
605 struct tu_buffer
606 {
607 VkDeviceSize size;
608
609 VkBufferUsageFlags usage;
610 VkBufferCreateFlags flags;
611
612 struct tu_bo *bo;
613 VkDeviceSize bo_offset;
614 };
615
616 static inline uint64_t
617 tu_buffer_iova(struct tu_buffer *buffer)
618 {
619 return buffer->bo->iova + buffer->bo_offset;
620 }
621
622 struct tu_vertex_binding
623 {
624 struct tu_buffer *buffer;
625 VkDeviceSize offset;
626 };
627
628 const char *
629 tu_get_debug_option_name(int id);
630
631 const char *
632 tu_get_perftest_option_name(int id);
633
634 struct tu_descriptor_state
635 {
636 struct tu_descriptor_set *sets[MAX_SETS];
637 uint32_t dynamic_descriptors[MAX_DYNAMIC_BUFFERS * A6XX_TEX_CONST_DWORDS];
638 };
639
640 struct tu_tile
641 {
642 uint8_t pipe;
643 uint8_t slot;
644 VkOffset2D begin;
645 VkOffset2D end;
646 };
647
648 struct tu_tiling_config
649 {
650 VkRect2D render_area;
651
652 /* position and size of the first tile */
653 VkRect2D tile0;
654 /* number of tiles */
655 VkExtent2D tile_count;
656
657 /* size of the first VSC pipe */
658 VkExtent2D pipe0;
659 /* number of VSC pipes */
660 VkExtent2D pipe_count;
661
662 /* pipe register values */
663 uint32_t pipe_config[MAX_VSC_PIPES];
664 uint32_t pipe_sizes[MAX_VSC_PIPES];
665
666 /* Whether sysmem rendering must be used */
667 bool force_sysmem;
668 };
669
670 enum tu_cmd_dirty_bits
671 {
672 TU_CMD_DIRTY_COMPUTE_PIPELINE = 1 << 1,
673 TU_CMD_DIRTY_VERTEX_BUFFERS = 1 << 2,
674 TU_CMD_DIRTY_DESCRIPTOR_SETS = 1 << 3,
675 TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS = 1 << 4,
676 TU_CMD_DIRTY_SHADER_CONSTS = 1 << 5,
677 /* all draw states were disabled and need to be re-enabled: */
678 TU_CMD_DIRTY_DRAW_STATE = 1 << 7,
679 };
680
681 /* There are only three cache domains we have to care about: the CCU, or
682 * color cache unit, which is used for color and depth/stencil attachments
683 * and copy/blit destinations, and is split conceptually into color and depth,
684 * and the universal cache or UCHE which is used for pretty much everything
685 * else, except for the CP (uncached) and host. We need to flush whenever data
686 * crosses these boundaries.
687 */
688
689 enum tu_cmd_access_mask {
690 TU_ACCESS_UCHE_READ = 1 << 0,
691 TU_ACCESS_UCHE_WRITE = 1 << 1,
692 TU_ACCESS_CCU_COLOR_READ = 1 << 2,
693 TU_ACCESS_CCU_COLOR_WRITE = 1 << 3,
694 TU_ACCESS_CCU_DEPTH_READ = 1 << 4,
695 TU_ACCESS_CCU_DEPTH_WRITE = 1 << 5,
696
697 /* Experiments have shown that while it's safe to avoid flushing the CCU
698 * after each blit/renderpass, it's not safe to assume that subsequent
699 * lookups with a different attachment state will hit unflushed cache
700 * entries. That is, the CCU needs to be flushed and possibly invalidated
701 * when accessing memory with a different attachment state. Writing to an
702 * attachment under the following conditions after clearing using the
703 * normal 2d engine path is known to have issues:
704 *
705 * - It isn't the 0'th layer.
706 * - There are more than one attachment, and this isn't the 0'th attachment
707 * (this seems to also depend on the cpp of the attachments).
708 *
709 * Our best guess is that the layer/MRT state is used when computing
710 * the location of a cache entry in CCU, to avoid conflicts. We assume that
711 * any access in a renderpass after or before an access by a transfer needs
712 * a flush/invalidate, and use the _INCOHERENT variants to represent access
713 * by a transfer.
714 */
715 TU_ACCESS_CCU_COLOR_INCOHERENT_READ = 1 << 6,
716 TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE = 1 << 7,
717 TU_ACCESS_CCU_DEPTH_INCOHERENT_READ = 1 << 8,
718 TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE = 1 << 9,
719
720 TU_ACCESS_SYSMEM_READ = 1 << 10,
721 TU_ACCESS_SYSMEM_WRITE = 1 << 11,
722
723 /* Set if a WFI is required due to data being read by the CP or the 2D
724 * engine.
725 */
726 TU_ACCESS_WFI_READ = 1 << 12,
727
728 TU_ACCESS_READ =
729 TU_ACCESS_UCHE_READ |
730 TU_ACCESS_CCU_COLOR_READ |
731 TU_ACCESS_CCU_DEPTH_READ |
732 TU_ACCESS_CCU_COLOR_INCOHERENT_READ |
733 TU_ACCESS_CCU_DEPTH_INCOHERENT_READ |
734 TU_ACCESS_SYSMEM_READ,
735
736 TU_ACCESS_WRITE =
737 TU_ACCESS_UCHE_WRITE |
738 TU_ACCESS_CCU_COLOR_WRITE |
739 TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE |
740 TU_ACCESS_CCU_DEPTH_WRITE |
741 TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE |
742 TU_ACCESS_SYSMEM_WRITE,
743
744 TU_ACCESS_ALL =
745 TU_ACCESS_READ |
746 TU_ACCESS_WRITE,
747 };
748
749 enum tu_cmd_flush_bits {
750 TU_CMD_FLAG_CCU_FLUSH_DEPTH = 1 << 0,
751 TU_CMD_FLAG_CCU_FLUSH_COLOR = 1 << 1,
752 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH = 1 << 2,
753 TU_CMD_FLAG_CCU_INVALIDATE_COLOR = 1 << 3,
754 TU_CMD_FLAG_CACHE_FLUSH = 1 << 4,
755 TU_CMD_FLAG_CACHE_INVALIDATE = 1 << 5,
756
757 TU_CMD_FLAG_ALL_FLUSH =
758 TU_CMD_FLAG_CCU_FLUSH_DEPTH |
759 TU_CMD_FLAG_CCU_FLUSH_COLOR |
760 TU_CMD_FLAG_CACHE_FLUSH,
761
762 TU_CMD_FLAG_ALL_INVALIDATE =
763 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH |
764 TU_CMD_FLAG_CCU_INVALIDATE_COLOR |
765 TU_CMD_FLAG_CACHE_INVALIDATE,
766
767 TU_CMD_FLAG_WFI = 1 << 6,
768 };
769
770 /* Changing the CCU from sysmem mode to gmem mode or vice-versa is pretty
771 * heavy, involving a CCU cache flush/invalidate and a WFI in order to change
772 * which part of the gmem is used by the CCU. Here we keep track of what the
773 * state of the CCU.
774 */
775 enum tu_cmd_ccu_state {
776 TU_CMD_CCU_SYSMEM,
777 TU_CMD_CCU_GMEM,
778 TU_CMD_CCU_UNKNOWN,
779 };
780
781 struct tu_cache_state {
782 /* Caches which must be made available (flushed) eventually if there are
783 * any users outside that cache domain, and caches which must be
784 * invalidated eventually if there are any reads.
785 */
786 enum tu_cmd_flush_bits pending_flush_bits;
787 /* Pending flushes */
788 enum tu_cmd_flush_bits flush_bits;
789 };
790
791 struct tu_cmd_state
792 {
793 uint32_t dirty;
794
795 struct tu_pipeline *pipeline;
796 struct tu_pipeline *compute_pipeline;
797
798 /* Vertex buffers */
799 struct
800 {
801 struct tu_buffer *buffers[MAX_VBS];
802 VkDeviceSize offsets[MAX_VBS];
803 } vb;
804
805 /* for dynamic states that can't be emitted directly */
806 uint32_t dynamic_stencil_mask;
807 uint32_t dynamic_stencil_wrmask;
808 uint32_t dynamic_stencil_ref;
809 uint32_t dynamic_gras_su_cntl;
810
811 /* saved states to re-emit in TU_CMD_DIRTY_DRAW_STATE case */
812 struct tu_draw_state dynamic_state[TU_DYNAMIC_STATE_COUNT];
813 struct tu_cs_entry vertex_buffers_ib;
814 struct tu_cs_entry shader_const_ib[MESA_SHADER_STAGES];
815 struct tu_cs_entry desc_sets_ib, desc_sets_load_ib;
816 struct tu_cs_entry ia_gmem_ib, ia_sysmem_ib;
817
818 struct tu_draw_state vs_params;
819
820 /* Index buffer */
821 uint64_t index_va;
822 uint32_t max_index_count;
823 uint8_t index_size;
824
825 /* because streamout base has to be 32-byte aligned
826 * there is an extra offset to deal with when it is
827 * unaligned
828 */
829 uint8_t streamout_offset[IR3_MAX_SO_BUFFERS];
830
831 /* Renderpasses are tricky, because we may need to flush differently if
832 * using sysmem vs. gmem and therefore we have to delay any flushing that
833 * happens before a renderpass. So we have to have two copies of the flush
834 * state, one for intra-renderpass flushes (i.e. renderpass dependencies)
835 * and one for outside a renderpass.
836 */
837 struct tu_cache_state cache;
838 struct tu_cache_state renderpass_cache;
839
840 enum tu_cmd_ccu_state ccu_state;
841
842 const struct tu_render_pass *pass;
843 const struct tu_subpass *subpass;
844 const struct tu_framebuffer *framebuffer;
845
846 struct tu_tiling_config tiling_config;
847
848 struct tu_cs_entry tile_store_ib;
849
850 bool xfb_used;
851 };
852
853 struct tu_cmd_pool
854 {
855 VkAllocationCallbacks alloc;
856 struct list_head cmd_buffers;
857 struct list_head free_cmd_buffers;
858 uint32_t queue_family_index;
859 };
860
861 struct tu_cmd_buffer_upload
862 {
863 uint8_t *map;
864 unsigned offset;
865 uint64_t size;
866 struct list_head list;
867 };
868
869 enum tu_cmd_buffer_status
870 {
871 TU_CMD_BUFFER_STATUS_INVALID,
872 TU_CMD_BUFFER_STATUS_INITIAL,
873 TU_CMD_BUFFER_STATUS_RECORDING,
874 TU_CMD_BUFFER_STATUS_EXECUTABLE,
875 TU_CMD_BUFFER_STATUS_PENDING,
876 };
877
878 struct tu_bo_list
879 {
880 uint32_t count;
881 uint32_t capacity;
882 struct drm_msm_gem_submit_bo *bo_infos;
883 };
884
885 #define TU_BO_LIST_FAILED (~0)
886
887 void
888 tu_bo_list_init(struct tu_bo_list *list);
889 void
890 tu_bo_list_destroy(struct tu_bo_list *list);
891 void
892 tu_bo_list_reset(struct tu_bo_list *list);
893 uint32_t
894 tu_bo_list_add(struct tu_bo_list *list,
895 const struct tu_bo *bo,
896 uint32_t flags);
897 VkResult
898 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other);
899
900 /* This struct defines the layout of the scratch_bo */
901 struct tu6_control
902 {
903 uint32_t seqno_dummy; /* dummy seqno for CP_EVENT_WRITE */
904 uint32_t _pad0;
905 volatile uint32_t vsc_overflow;
906 uint32_t _pad1;
907 /* flag set from cmdstream when VSC overflow detected: */
908 uint32_t vsc_scratch;
909 uint32_t _pad2;
910 uint32_t _pad3;
911 uint32_t _pad4;
912
913 /* scratch space for VPC_SO[i].FLUSH_BASE_LO/HI, start on 32 byte boundary. */
914 struct {
915 uint32_t offset;
916 uint32_t pad[7];
917 } flush_base[4];
918 };
919
920 #define ctrl_offset(member) offsetof(struct tu6_control, member)
921
922 struct tu_cmd_buffer
923 {
924 VK_LOADER_DATA _loader_data;
925
926 struct tu_device *device;
927
928 struct tu_cmd_pool *pool;
929 struct list_head pool_link;
930
931 VkCommandBufferUsageFlags usage_flags;
932 VkCommandBufferLevel level;
933 enum tu_cmd_buffer_status status;
934
935 struct tu_cmd_state state;
936 struct tu_vertex_binding vertex_bindings[MAX_VBS];
937 uint32_t vertex_bindings_set;
938 uint32_t queue_family_index;
939
940 uint32_t push_constants[MAX_PUSH_CONSTANTS_SIZE / 4];
941 VkShaderStageFlags push_constant_stages;
942 struct tu_descriptor_set meta_push_descriptors;
943
944 struct tu_descriptor_state descriptors[MAX_BIND_POINTS];
945
946 struct tu_cmd_buffer_upload upload;
947
948 VkResult record_result;
949
950 struct tu_bo_list bo_list;
951 struct tu_cs cs;
952 struct tu_cs draw_cs;
953 struct tu_cs draw_epilogue_cs;
954 struct tu_cs sub_cs;
955
956 struct tu_bo scratch_bo;
957
958 bool has_tess;
959
960 struct tu_bo vsc_draw_strm;
961 struct tu_bo vsc_prim_strm;
962 uint32_t vsc_draw_strm_pitch;
963 uint32_t vsc_prim_strm_pitch;
964 bool use_vsc_data;
965 };
966
967 /* Temporary struct for tracking a register state to be written, used by
968 * a6xx-pack.h and tu_cs_emit_regs()
969 */
970 struct tu_reg_value {
971 uint32_t reg;
972 uint64_t value;
973 bool is_address;
974 struct tu_bo *bo;
975 bool bo_write;
976 uint32_t bo_offset;
977 uint32_t bo_shift;
978 };
979
980
981 void tu_emit_cache_flush_renderpass(struct tu_cmd_buffer *cmd_buffer,
982 struct tu_cs *cs);
983
984 void tu_emit_cache_flush_ccu(struct tu_cmd_buffer *cmd_buffer,
985 struct tu_cs *cs,
986 enum tu_cmd_ccu_state ccu_state);
987
988 void
989 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
990 struct tu_cs *cs,
991 enum vgt_event_type event);
992
993 static inline struct tu_descriptor_state *
994 tu_get_descriptors_state(struct tu_cmd_buffer *cmd_buffer,
995 VkPipelineBindPoint bind_point)
996 {
997 return &cmd_buffer->descriptors[bind_point];
998 }
999
1000 struct tu_event
1001 {
1002 struct tu_bo bo;
1003 };
1004
1005 struct tu_shader_module
1006 {
1007 unsigned char sha1[20];
1008
1009 uint32_t code_size;
1010 const uint32_t *code[0];
1011 };
1012
1013 struct tu_push_constant_range
1014 {
1015 uint32_t lo;
1016 uint32_t count;
1017 };
1018
1019 struct tu_shader
1020 {
1021 struct ir3_shader *ir3_shader;
1022
1023 struct tu_push_constant_range push_consts;
1024 uint8_t active_desc_sets;
1025 };
1026
1027 struct tu_shader *
1028 tu_shader_create(struct tu_device *dev,
1029 gl_shader_stage stage,
1030 const VkPipelineShaderStageCreateInfo *stage_info,
1031 struct tu_pipeline_layout *layout,
1032 const VkAllocationCallbacks *alloc);
1033
1034 void
1035 tu_shader_destroy(struct tu_device *dev,
1036 struct tu_shader *shader,
1037 const VkAllocationCallbacks *alloc);
1038
1039 struct tu_program_descriptor_linkage
1040 {
1041 struct ir3_const_state const_state;
1042
1043 uint32_t constlen;
1044
1045 struct tu_push_constant_range push_consts;
1046 };
1047
1048 struct tu_pipeline
1049 {
1050 struct tu_cs cs;
1051
1052 struct tu_pipeline_layout *layout;
1053
1054 bool need_indirect_descriptor_sets;
1055 VkShaderStageFlags active_stages;
1056 uint32_t active_desc_sets;
1057
1058 /* mask of enabled dynamic states
1059 * if BIT(i) is set, pipeline->dynamic_state[i] is *NOT* used
1060 */
1061 uint32_t dynamic_state_mask;
1062 struct tu_draw_state dynamic_state[TU_DYNAMIC_STATE_COUNT];
1063
1064 /* gras_su_cntl without line width, used for dynamic line width state */
1065 uint32_t gras_su_cntl;
1066
1067 struct
1068 {
1069 struct tu_cs_entry state_ib;
1070 struct tu_cs_entry binning_state_ib;
1071
1072 struct tu_program_descriptor_linkage link[MESA_SHADER_STAGES];
1073 } program;
1074
1075 struct
1076 {
1077 struct tu_cs_entry state_ib;
1078 } load_state;
1079
1080 struct
1081 {
1082 struct tu_cs_entry state_ib;
1083 struct tu_cs_entry binning_state_ib;
1084 uint32_t bindings_used;
1085 } vi;
1086
1087 struct
1088 {
1089 enum pc_di_primtype primtype;
1090 bool primitive_restart;
1091 } ia;
1092
1093 struct
1094 {
1095 uint32_t patch_type;
1096 uint32_t per_vertex_output_size;
1097 uint32_t per_patch_output_size;
1098 uint32_t hs_bo_regid;
1099 uint32_t ds_bo_regid;
1100 bool upper_left_domain_origin;
1101 } tess;
1102
1103 struct
1104 {
1105 struct tu_cs_entry state_ib;
1106 } rast;
1107
1108 struct
1109 {
1110 struct tu_cs_entry state_ib;
1111 } ds;
1112
1113 struct
1114 {
1115 struct tu_cs_entry state_ib;
1116 } blend;
1117
1118 struct
1119 {
1120 uint32_t local_size[3];
1121 } compute;
1122 };
1123
1124 void
1125 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport);
1126
1127 void
1128 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor);
1129
1130 void
1131 tu6_emit_sample_locations(struct tu_cs *cs, const VkSampleLocationsInfoEXT *samp_loc);
1132
1133 void
1134 tu6_emit_depth_bias(struct tu_cs *cs,
1135 float constant_factor,
1136 float clamp,
1137 float slope_factor);
1138
1139 void tu6_emit_msaa(struct tu_cs *cs, VkSampleCountFlagBits samples);
1140
1141 void tu6_emit_window_scissor(struct tu_cs *cs, uint32_t x1, uint32_t y1, uint32_t x2, uint32_t y2);
1142
1143 void tu6_emit_window_offset(struct tu_cs *cs, uint32_t x1, uint32_t y1);
1144
1145 void
1146 tu6_emit_xs_config(struct tu_cs *cs,
1147 gl_shader_stage stage,
1148 const struct ir3_shader_variant *xs,
1149 uint64_t binary_iova);
1150
1151 void
1152 tu6_emit_vpc(struct tu_cs *cs,
1153 const struct ir3_shader_variant *vs,
1154 const struct ir3_shader_variant *hs,
1155 const struct ir3_shader_variant *ds,
1156 const struct ir3_shader_variant *gs,
1157 const struct ir3_shader_variant *fs);
1158
1159 void
1160 tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs);
1161
1162 struct tu_image_view;
1163
1164 void
1165 tu_resolve_sysmem(struct tu_cmd_buffer *cmd,
1166 struct tu_cs *cs,
1167 struct tu_image_view *src,
1168 struct tu_image_view *dst,
1169 uint32_t layers,
1170 const VkRect2D *rect);
1171
1172 void
1173 tu_clear_sysmem_attachment(struct tu_cmd_buffer *cmd,
1174 struct tu_cs *cs,
1175 uint32_t a,
1176 const VkRenderPassBeginInfo *info);
1177
1178 void
1179 tu_clear_gmem_attachment(struct tu_cmd_buffer *cmd,
1180 struct tu_cs *cs,
1181 uint32_t a,
1182 const VkRenderPassBeginInfo *info);
1183
1184 void
1185 tu_load_gmem_attachment(struct tu_cmd_buffer *cmd,
1186 struct tu_cs *cs,
1187 uint32_t a,
1188 bool force_load);
1189
1190 /* expose this function to be able to emit load without checking LOAD_OP */
1191 void
1192 tu_emit_load_gmem_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t a);
1193
1194 /* note: gmem store can also resolve */
1195 void
1196 tu_store_gmem_attachment(struct tu_cmd_buffer *cmd,
1197 struct tu_cs *cs,
1198 uint32_t a,
1199 uint32_t gmem_a);
1200
1201 enum tu_supported_formats {
1202 FMT_VERTEX = 1,
1203 FMT_TEXTURE = 2,
1204 FMT_COLOR = 4,
1205 };
1206
1207 struct tu_native_format
1208 {
1209 enum a6xx_format fmt : 8;
1210 enum a3xx_color_swap swap : 8;
1211 enum a6xx_tile_mode tile_mode : 8;
1212 enum tu_supported_formats supported : 8;
1213 };
1214
1215 struct tu_native_format tu6_format_vtx(VkFormat format);
1216 struct tu_native_format tu6_format_color(VkFormat format, enum a6xx_tile_mode tile_mode);
1217 struct tu_native_format tu6_format_texture(VkFormat format, enum a6xx_tile_mode tile_mode);
1218
1219 static inline enum a6xx_format
1220 tu6_base_format(VkFormat format)
1221 {
1222 /* note: tu6_format_color doesn't care about tiling for .fmt field */
1223 return tu6_format_color(format, TILE6_LINEAR).fmt;
1224 }
1225
1226 struct tu_image
1227 {
1228 VkImageType type;
1229 /* The original VkFormat provided by the client. This may not match any
1230 * of the actual surface formats.
1231 */
1232 VkFormat vk_format;
1233 VkImageAspectFlags aspects;
1234 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1235 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1236 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1237 VkExtent3D extent;
1238 uint32_t level_count;
1239 uint32_t layer_count;
1240 VkSampleCountFlagBits samples;
1241
1242 struct fdl_layout layout;
1243
1244 unsigned queue_family_mask;
1245 bool exclusive;
1246 bool shareable;
1247
1248 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1249 VkDeviceMemory owned_memory;
1250
1251 /* Set when bound */
1252 struct tu_bo *bo;
1253 VkDeviceSize bo_offset;
1254 };
1255
1256 static inline uint32_t
1257 tu_get_layerCount(const struct tu_image *image,
1258 const VkImageSubresourceRange *range)
1259 {
1260 return range->layerCount == VK_REMAINING_ARRAY_LAYERS
1261 ? image->layer_count - range->baseArrayLayer
1262 : range->layerCount;
1263 }
1264
1265 static inline uint32_t
1266 tu_get_levelCount(const struct tu_image *image,
1267 const VkImageSubresourceRange *range)
1268 {
1269 return range->levelCount == VK_REMAINING_MIP_LEVELS
1270 ? image->level_count - range->baseMipLevel
1271 : range->levelCount;
1272 }
1273
1274 struct tu_image_view
1275 {
1276 struct tu_image *image; /**< VkImageViewCreateInfo::image */
1277
1278 uint64_t base_addr;
1279 uint64_t ubwc_addr;
1280 uint32_t layer_size;
1281 uint32_t ubwc_layer_size;
1282
1283 /* used to determine if fast gmem store path can be used */
1284 VkExtent2D extent;
1285 bool need_y2_align;
1286
1287 bool ubwc_enabled;
1288
1289 uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
1290
1291 /* Descriptor for use as a storage image as opposed to a sampled image.
1292 * This has a few differences for cube maps (e.g. type).
1293 */
1294 uint32_t storage_descriptor[A6XX_TEX_CONST_DWORDS];
1295
1296 /* pre-filled register values */
1297 uint32_t PITCH;
1298 uint32_t FLAG_BUFFER_PITCH;
1299
1300 uint32_t RB_MRT_BUF_INFO;
1301 uint32_t SP_FS_MRT_REG;
1302
1303 uint32_t SP_PS_2D_SRC_INFO;
1304 uint32_t SP_PS_2D_SRC_SIZE;
1305
1306 uint32_t RB_2D_DST_INFO;
1307
1308 uint32_t RB_BLIT_DST_INFO;
1309 };
1310
1311 struct tu_sampler_ycbcr_conversion {
1312 VkFormat format;
1313 VkSamplerYcbcrModelConversion ycbcr_model;
1314 VkSamplerYcbcrRange ycbcr_range;
1315 VkComponentMapping components;
1316 VkChromaLocation chroma_offsets[2];
1317 VkFilter chroma_filter;
1318 };
1319
1320 struct tu_sampler {
1321 uint32_t descriptor[A6XX_TEX_SAMP_DWORDS];
1322 struct tu_sampler_ycbcr_conversion *ycbcr_sampler;
1323 };
1324
1325 void
1326 tu_cs_image_ref(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer);
1327
1328 void
1329 tu_cs_image_ref_2d(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer, bool src);
1330
1331 void
1332 tu_cs_image_flag_ref(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer);
1333
1334 VkResult
1335 tu_image_create(VkDevice _device,
1336 const VkImageCreateInfo *pCreateInfo,
1337 const VkAllocationCallbacks *alloc,
1338 VkImage *pImage,
1339 uint64_t modifier,
1340 const VkSubresourceLayout *plane_layouts);
1341
1342 VkResult
1343 tu_image_from_gralloc(VkDevice device_h,
1344 const VkImageCreateInfo *base_info,
1345 const VkNativeBufferANDROID *gralloc_info,
1346 const VkAllocationCallbacks *alloc,
1347 VkImage *out_image_h);
1348
1349 void
1350 tu_image_view_init(struct tu_image_view *view,
1351 const VkImageViewCreateInfo *pCreateInfo);
1352
1353 struct tu_buffer_view
1354 {
1355 uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
1356
1357 struct tu_buffer *buffer;
1358 };
1359 void
1360 tu_buffer_view_init(struct tu_buffer_view *view,
1361 struct tu_device *device,
1362 const VkBufferViewCreateInfo *pCreateInfo);
1363
1364 struct tu_attachment_info
1365 {
1366 struct tu_image_view *attachment;
1367 };
1368
1369 struct tu_framebuffer
1370 {
1371 uint32_t width;
1372 uint32_t height;
1373 uint32_t layers;
1374
1375 uint32_t attachment_count;
1376 struct tu_attachment_info attachments[0];
1377 };
1378
1379 struct tu_subpass_barrier {
1380 VkPipelineStageFlags src_stage_mask;
1381 VkAccessFlags src_access_mask;
1382 VkAccessFlags dst_access_mask;
1383 bool incoherent_ccu_color, incoherent_ccu_depth;
1384 };
1385
1386 struct tu_subpass_attachment
1387 {
1388 uint32_t attachment;
1389 };
1390
1391 struct tu_subpass
1392 {
1393 uint32_t input_count;
1394 uint32_t color_count;
1395 struct tu_subpass_attachment *input_attachments;
1396 struct tu_subpass_attachment *color_attachments;
1397 struct tu_subpass_attachment *resolve_attachments;
1398 struct tu_subpass_attachment depth_stencil_attachment;
1399
1400 VkSampleCountFlagBits samples;
1401
1402 uint32_t srgb_cntl;
1403
1404 struct tu_subpass_barrier start_barrier;
1405 };
1406
1407 struct tu_render_pass_attachment
1408 {
1409 VkFormat format;
1410 uint32_t samples;
1411 uint32_t cpp;
1412 VkImageAspectFlags clear_mask;
1413 bool load;
1414 bool store;
1415 int32_t gmem_offset;
1416 };
1417
1418 struct tu_render_pass
1419 {
1420 uint32_t attachment_count;
1421 uint32_t subpass_count;
1422 uint32_t gmem_pixels;
1423 uint32_t tile_align_w;
1424 struct tu_subpass_attachment *subpass_attachments;
1425 struct tu_render_pass_attachment *attachments;
1426 struct tu_subpass_barrier end_barrier;
1427 struct tu_subpass subpasses[0];
1428 };
1429
1430 struct tu_query_pool
1431 {
1432 VkQueryType type;
1433 uint32_t stride;
1434 uint64_t size;
1435 uint32_t pipeline_statistics;
1436 struct tu_bo bo;
1437 };
1438
1439 struct tu_semaphore
1440 {
1441 uint32_t syncobj;
1442 uint32_t temp_syncobj;
1443 };
1444
1445 void
1446 tu_set_descriptor_set(struct tu_cmd_buffer *cmd_buffer,
1447 VkPipelineBindPoint bind_point,
1448 struct tu_descriptor_set *set,
1449 unsigned idx);
1450
1451 void
1452 tu_update_descriptor_sets(struct tu_device *device,
1453 struct tu_cmd_buffer *cmd_buffer,
1454 VkDescriptorSet overrideSet,
1455 uint32_t descriptorWriteCount,
1456 const VkWriteDescriptorSet *pDescriptorWrites,
1457 uint32_t descriptorCopyCount,
1458 const VkCopyDescriptorSet *pDescriptorCopies);
1459
1460 void
1461 tu_update_descriptor_set_with_template(
1462 struct tu_device *device,
1463 struct tu_cmd_buffer *cmd_buffer,
1464 struct tu_descriptor_set *set,
1465 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
1466 const void *pData);
1467
1468 int
1469 tu_drm_get_gpu_id(const struct tu_physical_device *dev, uint32_t *id);
1470
1471 int
1472 tu_drm_get_gmem_size(const struct tu_physical_device *dev, uint32_t *size);
1473
1474 int
1475 tu_drm_get_gmem_base(const struct tu_physical_device *dev, uint64_t *base);
1476
1477 int
1478 tu_drm_submitqueue_new(const struct tu_device *dev,
1479 int priority,
1480 uint32_t *queue_id);
1481
1482 void
1483 tu_drm_submitqueue_close(const struct tu_device *dev, uint32_t queue_id);
1484
1485 uint32_t
1486 tu_gem_new(const struct tu_device *dev, uint64_t size, uint32_t flags);
1487 uint32_t
1488 tu_gem_import_dmabuf(const struct tu_device *dev,
1489 int prime_fd,
1490 uint64_t size);
1491 int
1492 tu_gem_export_dmabuf(const struct tu_device *dev, uint32_t gem_handle);
1493 void
1494 tu_gem_close(const struct tu_device *dev, uint32_t gem_handle);
1495 uint64_t
1496 tu_gem_info_offset(const struct tu_device *dev, uint32_t gem_handle);
1497 uint64_t
1498 tu_gem_info_iova(const struct tu_device *dev, uint32_t gem_handle);
1499
1500 #define TU_DEFINE_HANDLE_CASTS(__tu_type, __VkType) \
1501 \
1502 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1503 { \
1504 return (struct __tu_type *) _handle; \
1505 } \
1506 \
1507 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1508 { \
1509 return (__VkType) _obj; \
1510 }
1511
1512 #define TU_DEFINE_NONDISP_HANDLE_CASTS(__tu_type, __VkType) \
1513 \
1514 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1515 { \
1516 return (struct __tu_type *) (uintptr_t) _handle; \
1517 } \
1518 \
1519 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1520 { \
1521 return (__VkType)(uintptr_t) _obj; \
1522 }
1523
1524 #define TU_FROM_HANDLE(__tu_type, __name, __handle) \
1525 struct __tu_type *__name = __tu_type##_from_handle(__handle)
1526
1527 TU_DEFINE_HANDLE_CASTS(tu_cmd_buffer, VkCommandBuffer)
1528 TU_DEFINE_HANDLE_CASTS(tu_device, VkDevice)
1529 TU_DEFINE_HANDLE_CASTS(tu_instance, VkInstance)
1530 TU_DEFINE_HANDLE_CASTS(tu_physical_device, VkPhysicalDevice)
1531 TU_DEFINE_HANDLE_CASTS(tu_queue, VkQueue)
1532
1533 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_cmd_pool, VkCommandPool)
1534 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer, VkBuffer)
1535 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer_view, VkBufferView)
1536 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_pool, VkDescriptorPool)
1537 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set, VkDescriptorSet)
1538 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set_layout,
1539 VkDescriptorSetLayout)
1540 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_update_template,
1541 VkDescriptorUpdateTemplate)
1542 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_device_memory, VkDeviceMemory)
1543 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_fence, VkFence)
1544 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_event, VkEvent)
1545 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_framebuffer, VkFramebuffer)
1546 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image, VkImage)
1547 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image_view, VkImageView);
1548 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_cache, VkPipelineCache)
1549 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline, VkPipeline)
1550 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_layout, VkPipelineLayout)
1551 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_query_pool, VkQueryPool)
1552 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_render_pass, VkRenderPass)
1553 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_sampler, VkSampler)
1554 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_sampler_ycbcr_conversion, VkSamplerYcbcrConversion)
1555 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_shader_module, VkShaderModule)
1556 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_semaphore, VkSemaphore)
1557
1558 #endif /* TU_PRIVATE_H */