2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
43 #define VG(x) ((void)0)
46 #include "c11/threads.h"
47 #include "main/macros.h"
48 #include "util/list.h"
49 #include "util/macros.h"
50 #include "util/u_atomic.h"
52 #include "vk_object.h"
53 #include "vk_debug_report.h"
54 #include "wsi_common.h"
56 #include "drm-uapi/msm_drm.h"
57 #include "ir3/ir3_compiler.h"
58 #include "ir3/ir3_shader.h"
60 #include "adreno_common.xml.h"
61 #include "adreno_pm4.xml.h"
63 #include "fdl/freedreno_layout.h"
65 #include "tu_descriptor_set.h"
66 #include "tu_extensions.h"
69 /* Pre-declarations needed for WSI entrypoints */
72 typedef struct xcb_connection_t xcb_connection_t
;
73 typedef uint32_t xcb_visualid_t
;
74 typedef uint32_t xcb_window_t
;
76 #include <vulkan/vk_android_native_buffer.h>
77 #include <vulkan/vk_icd.h>
78 #include <vulkan/vulkan.h>
79 #include <vulkan/vulkan_intel.h>
81 #include "tu_entrypoints.h"
83 #include "vk_format.h"
86 #define MAX_VERTEX_ATTRIBS 32
88 #define MAX_VSC_PIPES 32
89 #define MAX_VIEWPORTS 1
90 #define MAX_SCISSORS 16
91 #define MAX_DISCARD_RECTANGLES 4
92 #define MAX_PUSH_CONSTANTS_SIZE 128
93 #define MAX_PUSH_DESCRIPTORS 32
94 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
95 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
96 #define MAX_DYNAMIC_BUFFERS \
97 (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
98 #define TU_MAX_DRM_DEVICES 8
100 #define MAX_BIND_POINTS 2 /* compute + graphics */
101 /* The Qualcomm driver exposes 0x20000058 */
102 #define MAX_STORAGE_BUFFER_RANGE 0x20000000
103 /* We use ldc for uniform buffer loads, just like the Qualcomm driver, so
104 * expose the same maximum range.
105 * TODO: The SIZE bitfield is 15 bits, and in 4-dword units, so the actual
106 * range might be higher.
108 #define MAX_UNIFORM_BUFFER_RANGE 0x10000
110 #define A6XX_TEX_CONST_DWORDS 16
111 #define A6XX_TEX_SAMP_DWORDS 4
113 #define tu_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
115 static inline uint32_t
116 tu_minify(uint32_t n
, uint32_t levels
)
118 if (unlikely(n
== 0))
121 return MAX2(n
>> levels
, 1);
124 #define for_each_bit(b, dword) \
125 for (uint32_t __dword = (dword); \
126 (b) = __builtin_ffs(__dword) - 1, __dword; __dword &= ~(1 << (b)))
128 #define typed_memcpy(dest, src, count) \
130 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
131 memcpy((dest), (src), (count) * sizeof(*(src))); \
134 #define COND(bool, val) ((bool) ? (val) : 0)
135 #define BIT(bit) (1u << (bit))
137 /* Whenever we generate an error, pass it through this function. Useful for
138 * debugging, where we can break on it. Only call at error site, not when
139 * propagating errors. Might be useful to plug in a stack trace here.
145 __vk_errorf(struct tu_instance
*instance
,
152 #define vk_error(instance, error) \
153 __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
154 #define vk_errorf(instance, error, format, ...) \
155 __vk_errorf(instance, error, __FILE__, __LINE__, format, ##__VA_ARGS__);
158 __tu_finishme(const char *file
, int line
, const char *format
, ...)
161 tu_loge(const char *format
, ...) tu_printflike(1, 2);
163 tu_logi(const char *format
, ...) tu_printflike(1, 2);
166 * Print a FINISHME message, including its source location.
168 #define tu_finishme(format, ...) \
170 static bool reported = false; \
172 __tu_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
179 tu_finishme("stub %s", __func__); \
183 tu_lookup_entrypoint_unchecked(const char *name
);
185 tu_lookup_entrypoint_checked(
187 uint32_t core_version
,
188 const struct tu_instance_extension_table
*instance
,
189 const struct tu_device_extension_table
*device
);
191 struct tu_physical_device
193 struct vk_object_base base
;
195 struct tu_instance
*instance
;
198 char name
[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE
];
199 uint8_t driver_uuid
[VK_UUID_SIZE
];
200 uint8_t device_uuid
[VK_UUID_SIZE
];
201 uint8_t cache_uuid
[VK_UUID_SIZE
];
203 struct wsi_device wsi_device
;
211 uint32_t ccu_offset_gmem
;
212 uint32_t ccu_offset_bypass
;
213 /* alignment for size of tiles */
214 uint32_t tile_align_w
;
215 #define TILE_ALIGN_H 16
216 /* gmem store/load granularity */
217 #define GMEM_ALIGN_W 16
218 #define GMEM_ALIGN_H 4
221 uint32_t PC_UNKNOWN_9805
;
222 uint32_t SP_UNKNOWN_A0F8
;
225 int msm_major_version
;
226 int msm_minor_version
;
230 /* This is the drivers on-disk cache used as a fallback as opposed to
231 * the pipeline cache defined by apps.
233 struct disk_cache
*disk_cache
;
235 struct tu_device_extension_table supported_extensions
;
240 TU_DEBUG_STARTUP
= 1 << 0,
241 TU_DEBUG_NIR
= 1 << 1,
242 TU_DEBUG_IR3
= 1 << 2,
243 TU_DEBUG_NOBIN
= 1 << 3,
244 TU_DEBUG_SYSMEM
= 1 << 4,
245 TU_DEBUG_FORCEBIN
= 1 << 5,
246 TU_DEBUG_NOUBWC
= 1 << 6,
251 struct vk_object_base base
;
253 VkAllocationCallbacks alloc
;
255 uint32_t api_version
;
256 int physical_device_count
;
257 struct tu_physical_device physical_devices
[TU_MAX_DRM_DEVICES
];
259 enum tu_debug_flags debug_flags
;
261 struct vk_debug_report_instance debug_report_callbacks
;
263 struct tu_instance_extension_table enabled_extensions
;
267 tu_wsi_init(struct tu_physical_device
*physical_device
);
269 tu_wsi_finish(struct tu_physical_device
*physical_device
);
272 tu_instance_extension_supported(const char *name
);
274 tu_physical_device_api_version(struct tu_physical_device
*dev
);
276 tu_physical_device_extension_supported(struct tu_physical_device
*dev
,
281 struct tu_pipeline_cache
283 struct vk_object_base base
;
285 struct tu_device
*device
;
286 pthread_mutex_t mutex
;
290 uint32_t kernel_count
;
291 struct cache_entry
**hash_table
;
294 VkAllocationCallbacks alloc
;
297 struct tu_pipeline_key
303 #define TU_QUEUE_GENERAL 0
305 #define TU_MAX_QUEUE_FAMILIES 1
309 struct vk_object_base base
;
310 struct wsi_fence
*fence_wsi
;
316 tu_fence_init(struct tu_fence
*fence
, bool signaled
);
318 tu_fence_finish(struct tu_fence
*fence
);
320 tu_fence_update_fd(struct tu_fence
*fence
, int fd
);
322 tu_fence_copy(struct tu_fence
*fence
, const struct tu_fence
*src
);
324 tu_fence_signal(struct tu_fence
*fence
);
326 tu_fence_wait_idle(struct tu_fence
*fence
);
330 struct vk_object_base base
;
332 struct tu_device
*device
;
333 uint32_t queue_family_index
;
335 VkDeviceQueueCreateFlags flags
;
337 uint32_t msm_queue_id
;
338 struct tu_fence submit_fence
;
353 GLOBAL_SH_FS_CLEAR_MAX
= GLOBAL_SH_FS_CLEAR0
+ MAX_RTS
,
357 /* This struct defines the layout of the global_bo */
360 /* 6 bcolor_entry entries, one for each VK_BORDER_COLOR */
361 uint8_t border_color
[128 * 6];
363 /* clear/blit shaders, all <= 16 instrs (16 instr = 1 instrlen unit) */
364 instr_t shaders
[GLOBAL_SH_COUNT
][16];
366 uint32_t seqno_dummy
; /* dummy seqno for CP_EVENT_WRITE */
368 volatile uint32_t vsc_draw_overflow
;
370 volatile uint32_t vsc_prim_overflow
;
373 /* scratch space for VPC_SO[i].FLUSH_BASE_LO/HI, start on 32 byte boundary. */
379 #define gb_offset(member) offsetof(struct tu6_global, member)
380 #define global_iova(cmd, member) ((cmd)->device->global_bo.iova + gb_offset(member))
382 void tu_init_clear_blit_shaders(struct tu6_global
*global
);
384 /* extra space in vsc draw/prim streams */
390 struct tu_instance
*instance
;
392 struct tu_queue
*queues
[TU_MAX_QUEUE_FAMILIES
];
393 int queue_count
[TU_MAX_QUEUE_FAMILIES
];
395 struct tu_physical_device
*physical_device
;
398 struct ir3_compiler
*compiler
;
400 /* Backup in-memory cache to be used if the app doesn't provide one */
401 struct tu_pipeline_cache
*mem_cache
;
403 #define MIN_SCRATCH_BO_SIZE_LOG2 12 /* A page */
405 /* Currently the kernel driver uses a 32-bit GPU address space, but it
406 * should be impossible to go beyond 48 bits.
412 } scratch_bos
[48 - MIN_SCRATCH_BO_SIZE_LOG2
];
414 struct tu_bo global_bo
;
416 struct tu_device_extension_table enabled_extensions
;
418 uint32_t vsc_draw_strm_pitch
;
419 uint32_t vsc_prim_strm_pitch
;
423 VkResult
_tu_device_set_lost(struct tu_device
*device
,
424 const char *file
, int line
,
425 const char *msg
, ...) PRINTFLIKE(4, 5);
426 #define tu_device_set_lost(dev, ...) \
427 _tu_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
430 tu_device_is_lost(struct tu_device
*device
)
432 return unlikely(p_atomic_read(&device
->_lost
));
436 tu_bo_init_new(struct tu_device
*dev
, struct tu_bo
*bo
, uint64_t size
);
438 tu_bo_init_dmabuf(struct tu_device
*dev
,
443 tu_bo_export_dmabuf(struct tu_device
*dev
, struct tu_bo
*bo
);
445 tu_bo_finish(struct tu_device
*dev
, struct tu_bo
*bo
);
447 tu_bo_map(struct tu_device
*dev
, struct tu_bo
*bo
);
449 /* Get a scratch bo for use inside a command buffer. This will always return
450 * the same bo given the same size or similar sizes, so only one scratch bo
451 * can be used at the same time. It's meant for short-lived things where we
452 * need to write to some piece of memory, read from it, and then immediately
456 tu_get_scratch_bo(struct tu_device
*dev
, uint64_t size
, struct tu_bo
**bo
);
461 const struct tu_bo
*bo
;
467 struct tu_cs_memory
{
472 struct tu_draw_state
{
477 enum tu_dynamic_state
479 /* re-use VK_DYNAMIC_STATE_ enums for non-extended dynamic states */
480 TU_DYNAMIC_STATE_SAMPLE_LOCATIONS
= VK_DYNAMIC_STATE_STENCIL_REFERENCE
+ 1,
481 TU_DYNAMIC_STATE_COUNT
,
484 enum tu_draw_state_group_id
486 TU_DRAW_STATE_PROGRAM
,
487 TU_DRAW_STATE_PROGRAM_BINNING
,
491 TU_DRAW_STATE_VI_BINNING
,
495 TU_DRAW_STATE_VS_CONST
,
496 TU_DRAW_STATE_HS_CONST
,
497 TU_DRAW_STATE_DS_CONST
,
498 TU_DRAW_STATE_GS_CONST
,
499 TU_DRAW_STATE_FS_CONST
,
500 TU_DRAW_STATE_DESC_SETS
,
501 TU_DRAW_STATE_DESC_SETS_LOAD
,
502 TU_DRAW_STATE_VS_PARAMS
,
503 TU_DRAW_STATE_INPUT_ATTACHMENTS_GMEM
,
504 TU_DRAW_STATE_INPUT_ATTACHMENTS_SYSMEM
,
506 /* dynamic state related draw states */
507 TU_DRAW_STATE_DYNAMIC
,
508 TU_DRAW_STATE_COUNT
= TU_DRAW_STATE_DYNAMIC
+ TU_DYNAMIC_STATE_COUNT
,
515 * A command stream in TU_CS_MODE_GROW mode grows automatically whenever it
516 * is full. tu_cs_begin must be called before command packet emission and
517 * tu_cs_end must be called after.
519 * This mode may create multiple entries internally. The entries must be
520 * submitted together.
525 * A command stream in TU_CS_MODE_EXTERNAL mode wraps an external,
526 * fixed-size buffer. tu_cs_begin and tu_cs_end are optional and have no
529 * This mode does not create any entry or any BO.
534 * A command stream in TU_CS_MODE_SUB_STREAM mode does not support direct
535 * command packet emission. tu_cs_begin_sub_stream must be called to get a
536 * sub-stream to emit comamnd packets to. When done with the sub-stream,
537 * tu_cs_end_sub_stream must be called.
539 * This mode does not create any entry internally.
541 TU_CS_MODE_SUB_STREAM
,
548 uint32_t *reserved_end
;
551 struct tu_device
*device
;
552 enum tu_cs_mode mode
;
553 uint32_t next_bo_size
;
555 struct tu_cs_entry
*entries
;
556 uint32_t entry_count
;
557 uint32_t entry_capacity
;
561 uint32_t bo_capacity
;
563 /* state for cond_exec_start/cond_exec_end */
565 uint32_t *cond_dwords
;
568 struct tu_device_memory
570 struct vk_object_base base
;
575 /* for dedicated allocations */
576 struct tu_image
*image
;
577 struct tu_buffer
*buffer
;
584 struct tu_descriptor_range
590 struct tu_descriptor_set
592 struct vk_object_base base
;
594 const struct tu_descriptor_set_layout
*layout
;
595 struct tu_descriptor_pool
*pool
;
599 uint32_t *mapped_ptr
;
601 uint32_t *dynamic_descriptors
;
603 struct tu_bo
*buffers
[0];
606 struct tu_push_descriptor_set
608 struct tu_descriptor_set set
;
612 struct tu_descriptor_pool_entry
616 struct tu_descriptor_set
*set
;
619 struct tu_descriptor_pool
621 struct vk_object_base base
;
624 uint64_t current_offset
;
627 uint8_t *host_memory_base
;
628 uint8_t *host_memory_ptr
;
629 uint8_t *host_memory_end
;
631 uint32_t entry_count
;
632 uint32_t max_entry_count
;
633 struct tu_descriptor_pool_entry entries
[0];
636 struct tu_descriptor_update_template_entry
638 VkDescriptorType descriptor_type
;
640 /* The number of descriptors to update */
641 uint32_t descriptor_count
;
643 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array
647 /* In dwords. Not valid/used for dynamic descriptors */
650 uint32_t buffer_offset
;
652 /* Only valid for combined image samplers and samplers */
653 uint16_t has_sampler
;
659 /* For push descriptors */
660 const uint32_t *immutable_samplers
;
663 struct tu_descriptor_update_template
665 struct vk_object_base base
;
667 uint32_t entry_count
;
668 struct tu_descriptor_update_template_entry entry
[0];
673 struct vk_object_base base
;
677 VkBufferUsageFlags usage
;
678 VkBufferCreateFlags flags
;
681 VkDeviceSize bo_offset
;
684 static inline uint64_t
685 tu_buffer_iova(struct tu_buffer
*buffer
)
687 return buffer
->bo
->iova
+ buffer
->bo_offset
;
690 struct tu_vertex_binding
692 struct tu_buffer
*buffer
;
697 tu_get_debug_option_name(int id
);
700 tu_get_perftest_option_name(int id
);
702 struct tu_descriptor_state
704 struct tu_descriptor_set
*sets
[MAX_SETS
];
705 uint32_t dynamic_descriptors
[MAX_DYNAMIC_BUFFERS
* A6XX_TEX_CONST_DWORDS
];
708 enum tu_cmd_dirty_bits
710 TU_CMD_DIRTY_VERTEX_BUFFERS
= 1 << 2,
711 TU_CMD_DIRTY_DESC_SETS_LOAD
= 1 << 3,
712 TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD
= 1 << 4,
713 TU_CMD_DIRTY_SHADER_CONSTS
= 1 << 5,
714 /* all draw states were disabled and need to be re-enabled: */
715 TU_CMD_DIRTY_DRAW_STATE
= 1 << 7,
718 /* There are only three cache domains we have to care about: the CCU, or
719 * color cache unit, which is used for color and depth/stencil attachments
720 * and copy/blit destinations, and is split conceptually into color and depth,
721 * and the universal cache or UCHE which is used for pretty much everything
722 * else, except for the CP (uncached) and host. We need to flush whenever data
723 * crosses these boundaries.
726 enum tu_cmd_access_mask
{
727 TU_ACCESS_UCHE_READ
= 1 << 0,
728 TU_ACCESS_UCHE_WRITE
= 1 << 1,
729 TU_ACCESS_CCU_COLOR_READ
= 1 << 2,
730 TU_ACCESS_CCU_COLOR_WRITE
= 1 << 3,
731 TU_ACCESS_CCU_DEPTH_READ
= 1 << 4,
732 TU_ACCESS_CCU_DEPTH_WRITE
= 1 << 5,
734 /* Experiments have shown that while it's safe to avoid flushing the CCU
735 * after each blit/renderpass, it's not safe to assume that subsequent
736 * lookups with a different attachment state will hit unflushed cache
737 * entries. That is, the CCU needs to be flushed and possibly invalidated
738 * when accessing memory with a different attachment state. Writing to an
739 * attachment under the following conditions after clearing using the
740 * normal 2d engine path is known to have issues:
742 * - It isn't the 0'th layer.
743 * - There are more than one attachment, and this isn't the 0'th attachment
744 * (this seems to also depend on the cpp of the attachments).
746 * Our best guess is that the layer/MRT state is used when computing
747 * the location of a cache entry in CCU, to avoid conflicts. We assume that
748 * any access in a renderpass after or before an access by a transfer needs
749 * a flush/invalidate, and use the _INCOHERENT variants to represent access
752 TU_ACCESS_CCU_COLOR_INCOHERENT_READ
= 1 << 6,
753 TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
= 1 << 7,
754 TU_ACCESS_CCU_DEPTH_INCOHERENT_READ
= 1 << 8,
755 TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE
= 1 << 9,
757 /* Accesses by the host */
758 TU_ACCESS_HOST_READ
= 1 << 10,
759 TU_ACCESS_HOST_WRITE
= 1 << 11,
761 /* Accesses by a GPU engine which bypasses any cache. e.g. writes via
762 * CP_EVENT_WRITE::BLIT and the CP are SYSMEM_WRITE.
764 TU_ACCESS_SYSMEM_READ
= 1 << 12,
765 TU_ACCESS_SYSMEM_WRITE
= 1 << 13,
767 /* Set if a WFI is required. This can be required for:
768 * - 2D engine which (on some models) doesn't wait for flushes to complete
770 * - CP draw indirect opcodes, where we need to wait for any flushes to
771 * complete but the CP implicitly waits for WFI's to complete and
772 * therefore we only need a WFI after the flushes.
774 TU_ACCESS_WFI_READ
= 1 << 14,
776 /* Set if a CP_WAIT_FOR_ME is required due to the data being read by the CP
777 * without it waiting for any WFI.
779 TU_ACCESS_WFM_READ
= 1 << 15,
781 /* Memory writes from the CP start in-order with draws and event writes,
782 * but execute asynchronously and hence need a CP_WAIT_MEM_WRITES if read.
784 TU_ACCESS_CP_WRITE
= 1 << 16,
787 TU_ACCESS_UCHE_READ
|
788 TU_ACCESS_CCU_COLOR_READ
|
789 TU_ACCESS_CCU_DEPTH_READ
|
790 TU_ACCESS_CCU_COLOR_INCOHERENT_READ
|
791 TU_ACCESS_CCU_DEPTH_INCOHERENT_READ
|
792 TU_ACCESS_HOST_READ
|
793 TU_ACCESS_SYSMEM_READ
|
798 TU_ACCESS_UCHE_WRITE
|
799 TU_ACCESS_CCU_COLOR_WRITE
|
800 TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
|
801 TU_ACCESS_CCU_DEPTH_WRITE
|
802 TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE
|
803 TU_ACCESS_HOST_WRITE
|
804 TU_ACCESS_SYSMEM_WRITE
|
812 enum tu_cmd_flush_bits
{
813 TU_CMD_FLAG_CCU_FLUSH_DEPTH
= 1 << 0,
814 TU_CMD_FLAG_CCU_FLUSH_COLOR
= 1 << 1,
815 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
= 1 << 2,
816 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
= 1 << 3,
817 TU_CMD_FLAG_CACHE_FLUSH
= 1 << 4,
818 TU_CMD_FLAG_CACHE_INVALIDATE
= 1 << 5,
819 TU_CMD_FLAG_WAIT_MEM_WRITES
= 1 << 6,
820 TU_CMD_FLAG_WAIT_FOR_IDLE
= 1 << 7,
821 TU_CMD_FLAG_WAIT_FOR_ME
= 1 << 8,
823 TU_CMD_FLAG_ALL_FLUSH
=
824 TU_CMD_FLAG_CCU_FLUSH_DEPTH
|
825 TU_CMD_FLAG_CCU_FLUSH_COLOR
|
826 TU_CMD_FLAG_CACHE_FLUSH
|
827 /* Treat the CP as a sort of "cache" which may need to be "flushed" via
828 * waiting for writes to land with WAIT_FOR_MEM_WRITES.
830 TU_CMD_FLAG_WAIT_MEM_WRITES
,
832 TU_CMD_FLAG_GPU_INVALIDATE
=
833 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
|
834 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
|
835 TU_CMD_FLAG_CACHE_INVALIDATE
,
837 TU_CMD_FLAG_ALL_INVALIDATE
=
838 TU_CMD_FLAG_GPU_INVALIDATE
|
839 /* Treat the CP as a sort of "cache" which may need to be "invalidated"
840 * via waiting for UCHE/CCU flushes to land with WFI/WFM.
842 TU_CMD_FLAG_WAIT_FOR_IDLE
|
843 TU_CMD_FLAG_WAIT_FOR_ME
,
846 /* Changing the CCU from sysmem mode to gmem mode or vice-versa is pretty
847 * heavy, involving a CCU cache flush/invalidate and a WFI in order to change
848 * which part of the gmem is used by the CCU. Here we keep track of what the
851 enum tu_cmd_ccu_state
{
857 struct tu_cache_state
{
858 /* Caches which must be made available (flushed) eventually if there are
859 * any users outside that cache domain, and caches which must be
860 * invalidated eventually if there are any reads.
862 enum tu_cmd_flush_bits pending_flush_bits
;
863 /* Pending flushes */
864 enum tu_cmd_flush_bits flush_bits
;
871 struct tu_pipeline
*pipeline
;
872 struct tu_pipeline
*compute_pipeline
;
877 struct tu_buffer
*buffers
[MAX_VBS
];
878 VkDeviceSize offsets
[MAX_VBS
];
881 /* for dynamic states that can't be emitted directly */
882 uint32_t dynamic_stencil_mask
;
883 uint32_t dynamic_stencil_wrmask
;
884 uint32_t dynamic_stencil_ref
;
885 uint32_t dynamic_gras_su_cntl
;
887 /* saved states to re-emit in TU_CMD_DIRTY_DRAW_STATE case */
888 struct tu_draw_state dynamic_state
[TU_DYNAMIC_STATE_COUNT
];
889 struct tu_draw_state vertex_buffers
;
890 struct tu_draw_state shader_const
[MESA_SHADER_STAGES
];
891 struct tu_draw_state desc_sets
;
893 struct tu_draw_state vs_params
;
897 uint32_t max_index_count
;
900 /* because streamout base has to be 32-byte aligned
901 * there is an extra offset to deal with when it is
904 uint8_t streamout_offset
[IR3_MAX_SO_BUFFERS
];
906 /* Renderpasses are tricky, because we may need to flush differently if
907 * using sysmem vs. gmem and therefore we have to delay any flushing that
908 * happens before a renderpass. So we have to have two copies of the flush
909 * state, one for intra-renderpass flushes (i.e. renderpass dependencies)
910 * and one for outside a renderpass.
912 struct tu_cache_state cache
;
913 struct tu_cache_state renderpass_cache
;
915 enum tu_cmd_ccu_state ccu_state
;
917 const struct tu_render_pass
*pass
;
918 const struct tu_subpass
*subpass
;
919 const struct tu_framebuffer
*framebuffer
;
920 VkRect2D render_area
;
922 struct tu_cs_entry tile_store_ib
;
930 struct vk_object_base base
;
932 VkAllocationCallbacks alloc
;
933 struct list_head cmd_buffers
;
934 struct list_head free_cmd_buffers
;
935 uint32_t queue_family_index
;
938 struct tu_cmd_buffer_upload
943 struct list_head list
;
946 enum tu_cmd_buffer_status
948 TU_CMD_BUFFER_STATUS_INVALID
,
949 TU_CMD_BUFFER_STATUS_INITIAL
,
950 TU_CMD_BUFFER_STATUS_RECORDING
,
951 TU_CMD_BUFFER_STATUS_EXECUTABLE
,
952 TU_CMD_BUFFER_STATUS_PENDING
,
959 struct drm_msm_gem_submit_bo
*bo_infos
;
962 #define TU_BO_LIST_FAILED (~0)
965 tu_bo_list_init(struct tu_bo_list
*list
);
967 tu_bo_list_destroy(struct tu_bo_list
*list
);
969 tu_bo_list_reset(struct tu_bo_list
*list
);
971 tu_bo_list_add(struct tu_bo_list
*list
,
972 const struct tu_bo
*bo
,
975 tu_bo_list_merge(struct tu_bo_list
*list
, const struct tu_bo_list
*other
);
979 struct vk_object_base base
;
981 struct tu_device
*device
;
983 struct tu_cmd_pool
*pool
;
984 struct list_head pool_link
;
986 VkCommandBufferUsageFlags usage_flags
;
987 VkCommandBufferLevel level
;
988 enum tu_cmd_buffer_status status
;
990 struct tu_cmd_state state
;
991 struct tu_vertex_binding vertex_bindings
[MAX_VBS
];
992 uint32_t vertex_bindings_set
;
993 uint32_t queue_family_index
;
995 uint32_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
/ 4];
996 VkShaderStageFlags push_constant_stages
;
997 struct tu_descriptor_set meta_push_descriptors
;
999 struct tu_descriptor_state descriptors
[MAX_BIND_POINTS
];
1001 struct tu_cmd_buffer_upload upload
;
1003 VkResult record_result
;
1005 struct tu_bo_list bo_list
;
1007 struct tu_cs draw_cs
;
1008 struct tu_cs draw_epilogue_cs
;
1009 struct tu_cs sub_cs
;
1011 uint32_t vsc_draw_strm_pitch
;
1012 uint32_t vsc_prim_strm_pitch
;
1015 /* Temporary struct for tracking a register state to be written, used by
1016 * a6xx-pack.h and tu_cs_emit_regs()
1018 struct tu_reg_value
{
1029 void tu_emit_cache_flush_renderpass(struct tu_cmd_buffer
*cmd_buffer
,
1032 void tu_emit_cache_flush_ccu(struct tu_cmd_buffer
*cmd_buffer
,
1034 enum tu_cmd_ccu_state ccu_state
);
1037 tu6_emit_event_write(struct tu_cmd_buffer
*cmd
,
1039 enum vgt_event_type event
);
1041 static inline struct tu_descriptor_state
*
1042 tu_get_descriptors_state(struct tu_cmd_buffer
*cmd_buffer
,
1043 VkPipelineBindPoint bind_point
)
1045 return &cmd_buffer
->descriptors
[bind_point
];
1050 struct vk_object_base base
;
1054 struct tu_shader_module
1056 struct vk_object_base base
;
1058 unsigned char sha1
[20];
1061 const uint32_t *code
[0];
1064 struct tu_push_constant_range
1072 struct ir3_shader
*ir3_shader
;
1074 struct tu_push_constant_range push_consts
;
1075 uint8_t active_desc_sets
;
1079 tu_shader_create(struct tu_device
*dev
,
1080 gl_shader_stage stage
,
1081 const VkPipelineShaderStageCreateInfo
*stage_info
,
1082 struct tu_pipeline_layout
*layout
,
1083 const VkAllocationCallbacks
*alloc
);
1086 tu_shader_destroy(struct tu_device
*dev
,
1087 struct tu_shader
*shader
,
1088 const VkAllocationCallbacks
*alloc
);
1090 struct tu_program_descriptor_linkage
1092 struct ir3_const_state const_state
;
1096 struct tu_push_constant_range push_consts
;
1101 struct vk_object_base base
;
1105 struct tu_pipeline_layout
*layout
;
1107 bool need_indirect_descriptor_sets
;
1108 VkShaderStageFlags active_stages
;
1109 uint32_t active_desc_sets
;
1111 /* mask of enabled dynamic states
1112 * if BIT(i) is set, pipeline->dynamic_state[i] is *NOT* used
1114 uint32_t dynamic_state_mask
;
1115 struct tu_draw_state dynamic_state
[TU_DYNAMIC_STATE_COUNT
];
1117 /* gras_su_cntl without line width, used for dynamic line width state */
1118 uint32_t gras_su_cntl
;
1120 /* draw states for the pipeline */
1121 struct tu_draw_state load_state
, rast_state
, ds_state
, blend_state
;
1125 struct tu_draw_state state
;
1126 struct tu_draw_state binning_state
;
1128 struct tu_program_descriptor_linkage link
[MESA_SHADER_STAGES
];
1133 struct tu_draw_state state
;
1134 struct tu_draw_state binning_state
;
1135 uint32_t bindings_used
;
1140 enum pc_di_primtype primtype
;
1141 bool primitive_restart
;
1146 uint32_t patch_type
;
1147 uint32_t param_stride
;
1148 uint32_t hs_bo_regid
;
1149 uint32_t ds_bo_regid
;
1150 bool upper_left_domain_origin
;
1155 uint32_t local_size
[3];
1160 tu6_emit_viewport(struct tu_cs
*cs
, const VkViewport
*viewport
);
1163 tu6_emit_scissor(struct tu_cs
*cs
, const VkRect2D
*scissor
);
1166 tu6_emit_sample_locations(struct tu_cs
*cs
, const VkSampleLocationsInfoEXT
*samp_loc
);
1169 tu6_emit_depth_bias(struct tu_cs
*cs
,
1170 float constant_factor
,
1172 float slope_factor
);
1174 void tu6_emit_msaa(struct tu_cs
*cs
, VkSampleCountFlagBits samples
);
1176 void tu6_emit_window_scissor(struct tu_cs
*cs
, uint32_t x1
, uint32_t y1
, uint32_t x2
, uint32_t y2
);
1178 void tu6_emit_window_offset(struct tu_cs
*cs
, uint32_t x1
, uint32_t y1
);
1181 tu6_emit_xs_config(struct tu_cs
*cs
,
1182 gl_shader_stage stage
,
1183 const struct ir3_shader_variant
*xs
,
1184 uint64_t binary_iova
);
1187 tu6_emit_vpc(struct tu_cs
*cs
,
1188 const struct ir3_shader_variant
*vs
,
1189 const struct ir3_shader_variant
*hs
,
1190 const struct ir3_shader_variant
*ds
,
1191 const struct ir3_shader_variant
*gs
,
1192 const struct ir3_shader_variant
*fs
,
1193 uint32_t patch_control_points
,
1194 bool vshs_workgroup
);
1197 tu6_emit_fs_inputs(struct tu_cs
*cs
, const struct ir3_shader_variant
*fs
);
1199 struct tu_image_view
;
1202 tu_resolve_sysmem(struct tu_cmd_buffer
*cmd
,
1204 struct tu_image_view
*src
,
1205 struct tu_image_view
*dst
,
1207 const VkRect2D
*rect
);
1210 tu_clear_sysmem_attachment(struct tu_cmd_buffer
*cmd
,
1213 const VkRenderPassBeginInfo
*info
);
1216 tu_clear_gmem_attachment(struct tu_cmd_buffer
*cmd
,
1219 const VkRenderPassBeginInfo
*info
);
1222 tu_load_gmem_attachment(struct tu_cmd_buffer
*cmd
,
1227 /* expose this function to be able to emit load without checking LOAD_OP */
1229 tu_emit_load_gmem_attachment(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
, uint32_t a
);
1231 /* note: gmem store can also resolve */
1233 tu_store_gmem_attachment(struct tu_cmd_buffer
*cmd
,
1238 enum tu_supported_formats
{
1244 struct tu_native_format
1246 enum a6xx_format fmt
: 8;
1247 enum a3xx_color_swap swap
: 8;
1248 enum a6xx_tile_mode tile_mode
: 8;
1249 enum tu_supported_formats supported
: 8;
1252 struct tu_native_format
tu6_format_vtx(VkFormat format
);
1253 struct tu_native_format
tu6_format_color(VkFormat format
, enum a6xx_tile_mode tile_mode
);
1254 struct tu_native_format
tu6_format_texture(VkFormat format
, enum a6xx_tile_mode tile_mode
);
1256 static inline enum a6xx_format
1257 tu6_base_format(VkFormat format
)
1259 /* note: tu6_format_color doesn't care about tiling for .fmt field */
1260 return tu6_format_color(format
, TILE6_LINEAR
).fmt
;
1265 struct vk_object_base base
;
1268 /* The original VkFormat provided by the client. This may not match any
1269 * of the actual surface formats.
1272 VkImageAspectFlags aspects
;
1273 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1274 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1275 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1277 uint32_t level_count
;
1278 uint32_t layer_count
;
1279 VkSampleCountFlagBits samples
;
1281 struct fdl_layout layout
[3];
1282 uint32_t total_size
;
1284 unsigned queue_family_mask
;
1288 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1289 VkDeviceMemory owned_memory
;
1291 /* Set when bound */
1293 VkDeviceSize bo_offset
;
1296 static inline uint32_t
1297 tu_get_layerCount(const struct tu_image
*image
,
1298 const VkImageSubresourceRange
*range
)
1300 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
1301 ? image
->layer_count
- range
->baseArrayLayer
1302 : range
->layerCount
;
1305 static inline uint32_t
1306 tu_get_levelCount(const struct tu_image
*image
,
1307 const VkImageSubresourceRange
*range
)
1309 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
1310 ? image
->level_count
- range
->baseMipLevel
1311 : range
->levelCount
;
1314 struct tu_image_view
1316 struct vk_object_base base
;
1318 struct tu_image
*image
; /**< VkImageViewCreateInfo::image */
1322 uint32_t layer_size
;
1323 uint32_t ubwc_layer_size
;
1325 /* used to determine if fast gmem store path can be used */
1331 uint32_t descriptor
[A6XX_TEX_CONST_DWORDS
];
1333 /* Descriptor for use as a storage image as opposed to a sampled image.
1334 * This has a few differences for cube maps (e.g. type).
1336 uint32_t storage_descriptor
[A6XX_TEX_CONST_DWORDS
];
1338 /* pre-filled register values */
1340 uint32_t FLAG_BUFFER_PITCH
;
1342 uint32_t RB_MRT_BUF_INFO
;
1343 uint32_t SP_FS_MRT_REG
;
1345 uint32_t SP_PS_2D_SRC_INFO
;
1346 uint32_t SP_PS_2D_SRC_SIZE
;
1348 uint32_t RB_2D_DST_INFO
;
1350 uint32_t RB_BLIT_DST_INFO
;
1352 /* for d32s8 separate stencil */
1353 uint64_t stencil_base_addr
;
1354 uint32_t stencil_layer_size
;
1355 uint32_t stencil_PITCH
;
1358 struct tu_sampler_ycbcr_conversion
{
1359 struct vk_object_base base
;
1362 VkSamplerYcbcrModelConversion ycbcr_model
;
1363 VkSamplerYcbcrRange ycbcr_range
;
1364 VkComponentMapping components
;
1365 VkChromaLocation chroma_offsets
[2];
1366 VkFilter chroma_filter
;
1370 struct vk_object_base base
;
1372 uint32_t descriptor
[A6XX_TEX_SAMP_DWORDS
];
1373 struct tu_sampler_ycbcr_conversion
*ycbcr_sampler
;
1377 tu_cs_image_ref(struct tu_cs
*cs
, const struct tu_image_view
*iview
, uint32_t layer
);
1380 tu_cs_image_ref_2d(struct tu_cs
*cs
, const struct tu_image_view
*iview
, uint32_t layer
, bool src
);
1383 tu_cs_image_flag_ref(struct tu_cs
*cs
, const struct tu_image_view
*iview
, uint32_t layer
);
1386 tu_cs_image_stencil_ref(struct tu_cs
*cs
, const struct tu_image_view
*iview
, uint32_t layer
);
1388 #define tu_image_view_stencil(iview, x) \
1389 ((iview->x & ~A6XX_##x##_COLOR_FORMAT__MASK) | A6XX_##x##_COLOR_FORMAT(FMT6_8_UINT))
1392 tu_image_create(VkDevice _device
,
1393 const VkImageCreateInfo
*pCreateInfo
,
1394 const VkAllocationCallbacks
*alloc
,
1397 const VkSubresourceLayout
*plane_layouts
);
1400 tu_image_from_gralloc(VkDevice device_h
,
1401 const VkImageCreateInfo
*base_info
,
1402 const VkNativeBufferANDROID
*gralloc_info
,
1403 const VkAllocationCallbacks
*alloc
,
1404 VkImage
*out_image_h
);
1407 tu_image_view_init(struct tu_image_view
*iview
,
1408 const VkImageViewCreateInfo
*pCreateInfo
,
1409 bool limited_z24s8
);
1411 struct tu_buffer_view
1413 struct vk_object_base base
;
1415 uint32_t descriptor
[A6XX_TEX_CONST_DWORDS
];
1417 struct tu_buffer
*buffer
;
1420 tu_buffer_view_init(struct tu_buffer_view
*view
,
1421 struct tu_device
*device
,
1422 const VkBufferViewCreateInfo
*pCreateInfo
);
1424 struct tu_attachment_info
1426 struct tu_image_view
*attachment
;
1429 struct tu_framebuffer
1431 struct vk_object_base base
;
1437 /* size of the first tile */
1439 /* number of tiles */
1440 VkExtent2D tile_count
;
1442 /* size of the first VSC pipe */
1444 /* number of VSC pipes */
1445 VkExtent2D pipe_count
;
1447 /* pipe register values */
1448 uint32_t pipe_config
[MAX_VSC_PIPES
];
1449 uint32_t pipe_sizes
[MAX_VSC_PIPES
];
1451 uint32_t attachment_count
;
1452 struct tu_attachment_info attachments
[0];
1456 tu_framebuffer_tiling_config(struct tu_framebuffer
*fb
,
1457 const struct tu_device
*device
,
1458 const struct tu_render_pass
*pass
);
1460 struct tu_subpass_barrier
{
1461 VkPipelineStageFlags src_stage_mask
;
1462 VkAccessFlags src_access_mask
;
1463 VkAccessFlags dst_access_mask
;
1464 bool incoherent_ccu_color
, incoherent_ccu_depth
;
1467 struct tu_subpass_attachment
1469 uint32_t attachment
;
1474 uint32_t input_count
;
1475 uint32_t color_count
;
1476 struct tu_subpass_attachment
*input_attachments
;
1477 struct tu_subpass_attachment
*color_attachments
;
1478 struct tu_subpass_attachment
*resolve_attachments
;
1479 struct tu_subpass_attachment depth_stencil_attachment
;
1481 VkSampleCountFlagBits samples
;
1485 struct tu_subpass_barrier start_barrier
;
1488 struct tu_render_pass_attachment
1493 VkImageAspectFlags clear_mask
;
1496 int32_t gmem_offset
;
1497 /* for D32S8 separate stencil: */
1500 int32_t gmem_offset_stencil
;
1503 struct tu_render_pass
1505 struct vk_object_base base
;
1507 uint32_t attachment_count
;
1508 uint32_t subpass_count
;
1509 uint32_t gmem_pixels
;
1510 uint32_t tile_align_w
;
1511 struct tu_subpass_attachment
*subpass_attachments
;
1512 struct tu_render_pass_attachment
*attachments
;
1513 struct tu_subpass_barrier end_barrier
;
1514 struct tu_subpass subpasses
[0];
1517 struct tu_query_pool
1519 struct vk_object_base base
;
1524 uint32_t pipeline_statistics
;
1528 enum tu_semaphore_kind
1531 TU_SEMAPHORE_SYNCOBJ
,
1534 struct tu_semaphore_part
1536 enum tu_semaphore_kind kind
;
1544 struct vk_object_base base
;
1546 struct tu_semaphore_part permanent
;
1547 struct tu_semaphore_part temporary
;
1551 tu_set_descriptor_set(struct tu_cmd_buffer
*cmd_buffer
,
1552 VkPipelineBindPoint bind_point
,
1553 struct tu_descriptor_set
*set
,
1557 tu_update_descriptor_sets(struct tu_device
*device
,
1558 struct tu_cmd_buffer
*cmd_buffer
,
1559 VkDescriptorSet overrideSet
,
1560 uint32_t descriptorWriteCount
,
1561 const VkWriteDescriptorSet
*pDescriptorWrites
,
1562 uint32_t descriptorCopyCount
,
1563 const VkCopyDescriptorSet
*pDescriptorCopies
);
1566 tu_update_descriptor_set_with_template(
1567 struct tu_device
*device
,
1568 struct tu_cmd_buffer
*cmd_buffer
,
1569 struct tu_descriptor_set
*set
,
1570 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
1574 tu_drm_get_gpu_id(const struct tu_physical_device
*dev
, uint32_t *id
);
1577 tu_drm_get_gmem_size(const struct tu_physical_device
*dev
, uint32_t *size
);
1580 tu_drm_get_gmem_base(const struct tu_physical_device
*dev
, uint64_t *base
);
1583 tu_drm_submitqueue_new(const struct tu_device
*dev
,
1585 uint32_t *queue_id
);
1588 tu_drm_submitqueue_close(const struct tu_device
*dev
, uint32_t queue_id
);
1591 tu_gem_new(const struct tu_device
*dev
, uint64_t size
, uint32_t flags
);
1593 tu_gem_import_dmabuf(const struct tu_device
*dev
,
1597 tu_gem_export_dmabuf(const struct tu_device
*dev
, uint32_t gem_handle
);
1599 tu_gem_close(const struct tu_device
*dev
, uint32_t gem_handle
);
1601 tu_gem_info_offset(const struct tu_device
*dev
, uint32_t gem_handle
);
1603 tu_gem_info_iova(const struct tu_device
*dev
, uint32_t gem_handle
);
1605 #define TU_DEFINE_HANDLE_CASTS(__tu_type, __VkType) \
1607 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1609 return (struct __tu_type *) _handle; \
1612 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1614 return (__VkType) _obj; \
1617 #define TU_DEFINE_NONDISP_HANDLE_CASTS(__tu_type, __VkType) \
1619 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1621 return (struct __tu_type *) (uintptr_t) _handle; \
1624 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1626 return (__VkType)(uintptr_t) _obj; \
1629 #define TU_FROM_HANDLE(__tu_type, __name, __handle) \
1630 struct __tu_type *__name = __tu_type##_from_handle(__handle)
1632 TU_DEFINE_HANDLE_CASTS(tu_cmd_buffer
, VkCommandBuffer
)
1633 TU_DEFINE_HANDLE_CASTS(tu_device
, VkDevice
)
1634 TU_DEFINE_HANDLE_CASTS(tu_instance
, VkInstance
)
1635 TU_DEFINE_HANDLE_CASTS(tu_physical_device
, VkPhysicalDevice
)
1636 TU_DEFINE_HANDLE_CASTS(tu_queue
, VkQueue
)
1638 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_cmd_pool
, VkCommandPool
)
1639 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer
, VkBuffer
)
1640 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer_view
, VkBufferView
)
1641 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_pool
, VkDescriptorPool
)
1642 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set
, VkDescriptorSet
)
1643 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set_layout
,
1644 VkDescriptorSetLayout
)
1645 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_update_template
,
1646 VkDescriptorUpdateTemplate
)
1647 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_device_memory
, VkDeviceMemory
)
1648 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_fence
, VkFence
)
1649 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_event
, VkEvent
)
1650 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_framebuffer
, VkFramebuffer
)
1651 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image
, VkImage
)
1652 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image_view
, VkImageView
);
1653 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_cache
, VkPipelineCache
)
1654 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline
, VkPipeline
)
1655 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_layout
, VkPipelineLayout
)
1656 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_query_pool
, VkQueryPool
)
1657 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_render_pass
, VkRenderPass
)
1658 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_sampler
, VkSampler
)
1659 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_sampler_ycbcr_conversion
, VkSamplerYcbcrConversion
)
1660 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_shader_module
, VkShaderModule
)
1661 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_semaphore
, VkSemaphore
)
1663 #endif /* TU_PRIVATE_H */