turnip: use dirty bits for dynamic viewport/scissor state
[mesa.git] / src / freedreno / vulkan / tu_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #ifndef TU_PRIVATE_H
29 #define TU_PRIVATE_H
30
31 #include <assert.h>
32 #include <pthread.h>
33 #include <stdbool.h>
34 #include <stdint.h>
35 #include <stdio.h>
36 #include <stdlib.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <memcheck.h>
40 #include <valgrind.h>
41 #define VG(x) x
42 #else
43 #define VG(x) ((void)0)
44 #endif
45
46 #include "c11/threads.h"
47 #include "main/macros.h"
48 #include "util/list.h"
49 #include "util/macros.h"
50 #include "vk_alloc.h"
51 #include "vk_debug_report.h"
52 #include "wsi_common.h"
53
54 #include "drm-uapi/msm_drm.h"
55 #include "ir3/ir3_compiler.h"
56 #include "ir3/ir3_shader.h"
57
58 #include "adreno_common.xml.h"
59 #include "adreno_pm4.xml.h"
60 #include "a6xx.xml.h"
61 #include "fdl/freedreno_layout.h"
62
63 #include "tu_descriptor_set.h"
64 #include "tu_extensions.h"
65
66 /* Pre-declarations needed for WSI entrypoints */
67 struct wl_surface;
68 struct wl_display;
69 typedef struct xcb_connection_t xcb_connection_t;
70 typedef uint32_t xcb_visualid_t;
71 typedef uint32_t xcb_window_t;
72
73 #include <vulkan/vk_android_native_buffer.h>
74 #include <vulkan/vk_icd.h>
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77
78 #include "tu_entrypoints.h"
79
80 #define MAX_VBS 32
81 #define MAX_VERTEX_ATTRIBS 32
82 #define MAX_RTS 8
83 #define MAX_VSC_PIPES 32
84 #define MAX_VIEWPORTS 1
85 #define MAX_SCISSORS 16
86 #define MAX_DISCARD_RECTANGLES 4
87 #define MAX_PUSH_CONSTANTS_SIZE 128
88 #define MAX_PUSH_DESCRIPTORS 32
89 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
90 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
91 #define MAX_DYNAMIC_BUFFERS \
92 (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
93 #define MAX_SAMPLES_LOG2 4
94 #define NUM_META_FS_KEYS 13
95 #define TU_MAX_DRM_DEVICES 8
96 #define MAX_VIEWS 8
97 /* The Qualcomm driver exposes 0x20000058 */
98 #define MAX_STORAGE_BUFFER_RANGE 0x20000000
99
100 #define NUM_DEPTH_CLEAR_PIPELINES 3
101
102 /*
103 * This is the point we switch from using CP to compute shader
104 * for certain buffer operations.
105 */
106 #define TU_BUFFER_OPS_CS_THRESHOLD 4096
107
108 #define A6XX_TEX_CONST_DWORDS 16
109 #define A6XX_TEX_SAMP_DWORDS 4
110
111 enum tu_mem_heap
112 {
113 TU_MEM_HEAP_VRAM,
114 TU_MEM_HEAP_VRAM_CPU_ACCESS,
115 TU_MEM_HEAP_GTT,
116 TU_MEM_HEAP_COUNT
117 };
118
119 enum tu_mem_type
120 {
121 TU_MEM_TYPE_VRAM,
122 TU_MEM_TYPE_GTT_WRITE_COMBINE,
123 TU_MEM_TYPE_VRAM_CPU_ACCESS,
124 TU_MEM_TYPE_GTT_CACHED,
125 TU_MEM_TYPE_COUNT
126 };
127
128 #define tu_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
129
130 static inline uint32_t
131 align_u32(uint32_t v, uint32_t a)
132 {
133 assert(a != 0 && a == (a & -a));
134 return (v + a - 1) & ~(a - 1);
135 }
136
137 static inline uint32_t
138 align_u32_npot(uint32_t v, uint32_t a)
139 {
140 return (v + a - 1) / a * a;
141 }
142
143 static inline uint64_t
144 align_u64(uint64_t v, uint64_t a)
145 {
146 assert(a != 0 && a == (a & -a));
147 return (v + a - 1) & ~(a - 1);
148 }
149
150 static inline int32_t
151 align_i32(int32_t v, int32_t a)
152 {
153 assert(a != 0 && a == (a & -a));
154 return (v + a - 1) & ~(a - 1);
155 }
156
157 /** Alignment must be a power of 2. */
158 static inline bool
159 tu_is_aligned(uintmax_t n, uintmax_t a)
160 {
161 assert(a == (a & -a));
162 return (n & (a - 1)) == 0;
163 }
164
165 static inline uint32_t
166 round_up_u32(uint32_t v, uint32_t a)
167 {
168 return (v + a - 1) / a;
169 }
170
171 static inline uint64_t
172 round_up_u64(uint64_t v, uint64_t a)
173 {
174 return (v + a - 1) / a;
175 }
176
177 static inline uint32_t
178 tu_minify(uint32_t n, uint32_t levels)
179 {
180 if (unlikely(n == 0))
181 return 0;
182 else
183 return MAX2(n >> levels, 1);
184 }
185 static inline float
186 tu_clamp_f(float f, float min, float max)
187 {
188 assert(min < max);
189
190 if (f > max)
191 return max;
192 else if (f < min)
193 return min;
194 else
195 return f;
196 }
197
198 static inline bool
199 tu_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
200 {
201 if (*inout_mask & clear_mask) {
202 *inout_mask &= ~clear_mask;
203 return true;
204 } else {
205 return false;
206 }
207 }
208
209 #define for_each_bit(b, dword) \
210 for (uint32_t __dword = (dword); \
211 (b) = __builtin_ffs(__dword) - 1, __dword; __dword &= ~(1 << (b)))
212
213 #define typed_memcpy(dest, src, count) \
214 ({ \
215 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
216 memcpy((dest), (src), (count) * sizeof(*(src))); \
217 })
218
219 #define COND(bool, val) ((bool) ? (val) : 0)
220
221 /* Whenever we generate an error, pass it through this function. Useful for
222 * debugging, where we can break on it. Only call at error site, not when
223 * propagating errors. Might be useful to plug in a stack trace here.
224 */
225
226 struct tu_instance;
227
228 VkResult
229 __vk_errorf(struct tu_instance *instance,
230 VkResult error,
231 const char *file,
232 int line,
233 const char *format,
234 ...);
235
236 #define vk_error(instance, error) \
237 __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
238 #define vk_errorf(instance, error, format, ...) \
239 __vk_errorf(instance, error, __FILE__, __LINE__, format, ##__VA_ARGS__);
240
241 void
242 __tu_finishme(const char *file, int line, const char *format, ...)
243 tu_printflike(3, 4);
244 void
245 tu_loge(const char *format, ...) tu_printflike(1, 2);
246 void
247 tu_loge_v(const char *format, va_list va);
248 void
249 tu_logi(const char *format, ...) tu_printflike(1, 2);
250 void
251 tu_logi_v(const char *format, va_list va);
252
253 /**
254 * Print a FINISHME message, including its source location.
255 */
256 #define tu_finishme(format, ...) \
257 do { \
258 static bool reported = false; \
259 if (!reported) { \
260 __tu_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
261 reported = true; \
262 } \
263 } while (0)
264
265 /* A non-fatal assert. Useful for debugging. */
266 #ifdef DEBUG
267 #define tu_assert(x) \
268 ({ \
269 if (unlikely(!(x))) \
270 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
271 })
272 #else
273 #define tu_assert(x)
274 #endif
275
276 /* Suppress -Wunused in stub functions */
277 #define tu_use_args(...) __tu_use_args(0, ##__VA_ARGS__)
278 static inline void
279 __tu_use_args(int ignore, ...)
280 {
281 }
282
283 #define tu_stub() \
284 do { \
285 tu_finishme("stub %s", __func__); \
286 } while (0)
287
288 void *
289 tu_lookup_entrypoint_unchecked(const char *name);
290 void *
291 tu_lookup_entrypoint_checked(
292 const char *name,
293 uint32_t core_version,
294 const struct tu_instance_extension_table *instance,
295 const struct tu_device_extension_table *device);
296
297 struct tu_physical_device
298 {
299 VK_LOADER_DATA _loader_data;
300
301 struct tu_instance *instance;
302
303 char path[20];
304 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
305 uint8_t driver_uuid[VK_UUID_SIZE];
306 uint8_t device_uuid[VK_UUID_SIZE];
307 uint8_t cache_uuid[VK_UUID_SIZE];
308
309 struct wsi_device wsi_device;
310
311 int local_fd;
312 int master_fd;
313
314 unsigned gpu_id;
315 uint32_t gmem_size;
316 uint64_t gmem_base;
317 uint32_t ccu_offset_gmem;
318 uint32_t ccu_offset_bypass;
319 #define GMEM_ALIGN_W 16
320 #define GMEM_ALIGN_H 4
321
322 struct {
323 uint32_t RB_UNKNOWN_8E04_blit; /* for CP_BLIT's */
324 uint32_t PC_UNKNOWN_9805;
325 uint32_t SP_UNKNOWN_A0F8;
326 } magic;
327
328 /* This is the drivers on-disk cache used as a fallback as opposed to
329 * the pipeline cache defined by apps.
330 */
331 struct disk_cache *disk_cache;
332
333 struct tu_device_extension_table supported_extensions;
334 };
335
336 enum tu_debug_flags
337 {
338 TU_DEBUG_STARTUP = 1 << 0,
339 TU_DEBUG_NIR = 1 << 1,
340 TU_DEBUG_IR3 = 1 << 2,
341 TU_DEBUG_NOBIN = 1 << 3,
342 TU_DEBUG_SYSMEM = 1 << 4,
343 TU_DEBUG_FORCEBIN = 1 << 5,
344 };
345
346 struct tu_instance
347 {
348 VK_LOADER_DATA _loader_data;
349
350 VkAllocationCallbacks alloc;
351
352 uint32_t api_version;
353 int physical_device_count;
354 struct tu_physical_device physical_devices[TU_MAX_DRM_DEVICES];
355
356 enum tu_debug_flags debug_flags;
357
358 struct vk_debug_report_instance debug_report_callbacks;
359
360 struct tu_instance_extension_table enabled_extensions;
361 };
362
363 VkResult
364 tu_wsi_init(struct tu_physical_device *physical_device);
365 void
366 tu_wsi_finish(struct tu_physical_device *physical_device);
367
368 bool
369 tu_instance_extension_supported(const char *name);
370 uint32_t
371 tu_physical_device_api_version(struct tu_physical_device *dev);
372 bool
373 tu_physical_device_extension_supported(struct tu_physical_device *dev,
374 const char *name);
375
376 struct cache_entry;
377
378 struct tu_pipeline_cache
379 {
380 struct tu_device *device;
381 pthread_mutex_t mutex;
382
383 uint32_t total_size;
384 uint32_t table_size;
385 uint32_t kernel_count;
386 struct cache_entry **hash_table;
387 bool modified;
388
389 VkAllocationCallbacks alloc;
390 };
391
392 struct tu_pipeline_key
393 {
394 };
395
396 void
397 tu_pipeline_cache_init(struct tu_pipeline_cache *cache,
398 struct tu_device *device);
399 void
400 tu_pipeline_cache_finish(struct tu_pipeline_cache *cache);
401 void
402 tu_pipeline_cache_load(struct tu_pipeline_cache *cache,
403 const void *data,
404 size_t size);
405
406 struct tu_shader_variant;
407
408 bool
409 tu_create_shader_variants_from_pipeline_cache(
410 struct tu_device *device,
411 struct tu_pipeline_cache *cache,
412 const unsigned char *sha1,
413 struct tu_shader_variant **variants);
414
415 void
416 tu_pipeline_cache_insert_shaders(struct tu_device *device,
417 struct tu_pipeline_cache *cache,
418 const unsigned char *sha1,
419 struct tu_shader_variant **variants,
420 const void *const *codes,
421 const unsigned *code_sizes);
422
423 struct tu_meta_state
424 {
425 VkAllocationCallbacks alloc;
426
427 struct tu_pipeline_cache cache;
428 };
429
430 /* queue types */
431 #define TU_QUEUE_GENERAL 0
432
433 #define TU_MAX_QUEUE_FAMILIES 1
434
435 struct tu_fence
436 {
437 struct wsi_fence *fence_wsi;
438 bool signaled;
439 int fd;
440 };
441
442 void
443 tu_fence_init(struct tu_fence *fence, bool signaled);
444 void
445 tu_fence_finish(struct tu_fence *fence);
446 void
447 tu_fence_update_fd(struct tu_fence *fence, int fd);
448 void
449 tu_fence_copy(struct tu_fence *fence, const struct tu_fence *src);
450 void
451 tu_fence_signal(struct tu_fence *fence);
452 void
453 tu_fence_wait_idle(struct tu_fence *fence);
454
455 struct tu_queue
456 {
457 VK_LOADER_DATA _loader_data;
458 struct tu_device *device;
459 uint32_t queue_family_index;
460 int queue_idx;
461 VkDeviceQueueCreateFlags flags;
462
463 uint32_t msm_queue_id;
464 struct tu_fence submit_fence;
465 };
466
467 struct tu_bo
468 {
469 uint32_t gem_handle;
470 uint64_t size;
471 uint64_t iova;
472 void *map;
473 };
474
475 struct tu_device
476 {
477 VK_LOADER_DATA _loader_data;
478
479 VkAllocationCallbacks alloc;
480
481 struct tu_instance *instance;
482
483 struct tu_meta_state meta_state;
484
485 struct tu_queue *queues[TU_MAX_QUEUE_FAMILIES];
486 int queue_count[TU_MAX_QUEUE_FAMILIES];
487
488 struct tu_physical_device *physical_device;
489
490 struct ir3_compiler *compiler;
491
492 /* Backup in-memory cache to be used if the app doesn't provide one */
493 struct tu_pipeline_cache *mem_cache;
494
495 struct tu_bo vsc_data;
496 struct tu_bo vsc_data2;
497 uint32_t vsc_data_pitch;
498 uint32_t vsc_data2_pitch;
499
500 struct tu_bo border_color;
501
502 struct list_head shader_slabs;
503 mtx_t shader_slab_mutex;
504
505 struct tu_device_extension_table enabled_extensions;
506 };
507
508 VkResult
509 tu_bo_init_new(struct tu_device *dev, struct tu_bo *bo, uint64_t size);
510 VkResult
511 tu_bo_init_dmabuf(struct tu_device *dev,
512 struct tu_bo *bo,
513 uint64_t size,
514 int fd);
515 int
516 tu_bo_export_dmabuf(struct tu_device *dev, struct tu_bo *bo);
517 void
518 tu_bo_finish(struct tu_device *dev, struct tu_bo *bo);
519 VkResult
520 tu_bo_map(struct tu_device *dev, struct tu_bo *bo);
521
522 struct tu_cs_entry
523 {
524 /* No ownership */
525 const struct tu_bo *bo;
526
527 uint32_t size;
528 uint32_t offset;
529 };
530
531 struct ts_cs_memory {
532 uint32_t *map;
533 uint64_t iova;
534 };
535
536 enum tu_cs_mode
537 {
538
539 /*
540 * A command stream in TU_CS_MODE_GROW mode grows automatically whenever it
541 * is full. tu_cs_begin must be called before command packet emission and
542 * tu_cs_end must be called after.
543 *
544 * This mode may create multiple entries internally. The entries must be
545 * submitted together.
546 */
547 TU_CS_MODE_GROW,
548
549 /*
550 * A command stream in TU_CS_MODE_EXTERNAL mode wraps an external,
551 * fixed-size buffer. tu_cs_begin and tu_cs_end are optional and have no
552 * effect on it.
553 *
554 * This mode does not create any entry or any BO.
555 */
556 TU_CS_MODE_EXTERNAL,
557
558 /*
559 * A command stream in TU_CS_MODE_SUB_STREAM mode does not support direct
560 * command packet emission. tu_cs_begin_sub_stream must be called to get a
561 * sub-stream to emit comamnd packets to. When done with the sub-stream,
562 * tu_cs_end_sub_stream must be called.
563 *
564 * This mode does not create any entry internally.
565 */
566 TU_CS_MODE_SUB_STREAM,
567 };
568
569 struct tu_cs
570 {
571 uint32_t *start;
572 uint32_t *cur;
573 uint32_t *reserved_end;
574 uint32_t *end;
575
576 struct tu_device *device;
577 enum tu_cs_mode mode;
578 uint32_t next_bo_size;
579
580 struct tu_cs_entry *entries;
581 uint32_t entry_count;
582 uint32_t entry_capacity;
583
584 struct tu_bo **bos;
585 uint32_t bo_count;
586 uint32_t bo_capacity;
587
588 /* state for cond_exec_start/cond_exec_end */
589 uint32_t cond_flags;
590 uint32_t *cond_dwords;
591 };
592
593 struct tu_device_memory
594 {
595 struct tu_bo bo;
596 VkDeviceSize size;
597
598 /* for dedicated allocations */
599 struct tu_image *image;
600 struct tu_buffer *buffer;
601
602 uint32_t type_index;
603 void *map;
604 void *user_ptr;
605 };
606
607 struct tu_descriptor_range
608 {
609 uint64_t va;
610 uint32_t size;
611 };
612
613 struct tu_descriptor_set
614 {
615 const struct tu_descriptor_set_layout *layout;
616 uint32_t size;
617
618 uint64_t va;
619 uint32_t *mapped_ptr;
620 struct tu_descriptor_range *dynamic_descriptors;
621
622 struct tu_bo *descriptors[0];
623 };
624
625 struct tu_push_descriptor_set
626 {
627 struct tu_descriptor_set set;
628 uint32_t capacity;
629 };
630
631 struct tu_descriptor_pool_entry
632 {
633 uint32_t offset;
634 uint32_t size;
635 struct tu_descriptor_set *set;
636 };
637
638 struct tu_descriptor_pool
639 {
640 struct tu_bo bo;
641 uint64_t current_offset;
642 uint64_t size;
643
644 uint8_t *host_memory_base;
645 uint8_t *host_memory_ptr;
646 uint8_t *host_memory_end;
647
648 uint32_t entry_count;
649 uint32_t max_entry_count;
650 struct tu_descriptor_pool_entry entries[0];
651 };
652
653 struct tu_descriptor_update_template_entry
654 {
655 VkDescriptorType descriptor_type;
656
657 /* The number of descriptors to update */
658 uint32_t descriptor_count;
659
660 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array
661 */
662 uint32_t dst_offset;
663
664 /* In dwords. Not valid/used for dynamic descriptors */
665 uint32_t dst_stride;
666
667 uint32_t buffer_offset;
668
669 /* Only valid for combined image samplers and samplers */
670 uint16_t has_sampler;
671
672 /* In bytes */
673 size_t src_offset;
674 size_t src_stride;
675
676 /* For push descriptors */
677 const uint32_t *immutable_samplers;
678 };
679
680 struct tu_descriptor_update_template
681 {
682 uint32_t entry_count;
683 VkPipelineBindPoint bind_point;
684 struct tu_descriptor_update_template_entry entry[0];
685 };
686
687 struct tu_buffer
688 {
689 VkDeviceSize size;
690
691 VkBufferUsageFlags usage;
692 VkBufferCreateFlags flags;
693
694 struct tu_bo *bo;
695 VkDeviceSize bo_offset;
696 };
697
698 static inline uint64_t
699 tu_buffer_iova(struct tu_buffer *buffer)
700 {
701 return buffer->bo->iova + buffer->bo_offset;
702 }
703
704 enum tu_dynamic_state_bits
705 {
706 TU_DYNAMIC_VIEWPORT = 1 << 0,
707 TU_DYNAMIC_SCISSOR = 1 << 1,
708 TU_DYNAMIC_LINE_WIDTH = 1 << 2,
709 TU_DYNAMIC_DEPTH_BIAS = 1 << 3,
710 TU_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
711 TU_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
712 TU_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
713 TU_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
714 TU_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
715 TU_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
716 TU_DYNAMIC_ALL = (1 << 10) - 1,
717 };
718
719 struct tu_vertex_binding
720 {
721 struct tu_buffer *buffer;
722 VkDeviceSize offset;
723 };
724
725 struct tu_viewport_state
726 {
727 uint32_t count;
728 VkViewport viewports[MAX_VIEWPORTS];
729 };
730
731 struct tu_scissor_state
732 {
733 uint32_t count;
734 VkRect2D scissors[MAX_SCISSORS];
735 };
736
737 struct tu_discard_rectangle_state
738 {
739 uint32_t count;
740 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
741 };
742
743 struct tu_dynamic_state
744 {
745 /**
746 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
747 * Defines the set of saved dynamic state.
748 */
749 uint32_t mask;
750
751 struct tu_viewport_state viewport;
752
753 struct tu_scissor_state scissor;
754
755 float line_width;
756
757 struct
758 {
759 float bias;
760 float clamp;
761 float slope;
762 } depth_bias;
763
764 float blend_constants[4];
765
766 struct
767 {
768 float min;
769 float max;
770 } depth_bounds;
771
772 struct
773 {
774 uint32_t front;
775 uint32_t back;
776 } stencil_compare_mask;
777
778 struct
779 {
780 uint32_t front;
781 uint32_t back;
782 } stencil_write_mask;
783
784 struct
785 {
786 uint32_t front;
787 uint32_t back;
788 } stencil_reference;
789
790 struct tu_discard_rectangle_state discard_rectangle;
791 };
792
793 extern const struct tu_dynamic_state default_dynamic_state;
794
795 const char *
796 tu_get_debug_option_name(int id);
797
798 const char *
799 tu_get_perftest_option_name(int id);
800
801 struct tu_descriptor_state
802 {
803 struct tu_descriptor_set *sets[MAX_SETS];
804 uint32_t valid;
805 struct tu_push_descriptor_set push_set;
806 bool push_dirty;
807 uint64_t dynamic_buffers[MAX_DYNAMIC_BUFFERS];
808 };
809
810 struct tu_tile
811 {
812 uint8_t pipe;
813 uint8_t slot;
814 VkOffset2D begin;
815 VkOffset2D end;
816 };
817
818 struct tu_tiling_config
819 {
820 VkRect2D render_area;
821
822 /* position and size of the first tile */
823 VkRect2D tile0;
824 /* number of tiles */
825 VkExtent2D tile_count;
826
827 /* size of the first VSC pipe */
828 VkExtent2D pipe0;
829 /* number of VSC pipes */
830 VkExtent2D pipe_count;
831
832 /* pipe register values */
833 uint32_t pipe_config[MAX_VSC_PIPES];
834 uint32_t pipe_sizes[MAX_VSC_PIPES];
835
836 /* Whether sysmem rendering must be used */
837 bool force_sysmem;
838 };
839
840 enum tu_cmd_dirty_bits
841 {
842 TU_CMD_DIRTY_PIPELINE = 1 << 0,
843 TU_CMD_DIRTY_COMPUTE_PIPELINE = 1 << 1,
844 TU_CMD_DIRTY_VERTEX_BUFFERS = 1 << 2,
845 TU_CMD_DIRTY_DESCRIPTOR_SETS = 1 << 3,
846 TU_CMD_DIRTY_PUSH_CONSTANTS = 1 << 4,
847 TU_CMD_DIRTY_STREAMOUT_BUFFERS = 1 << 5,
848
849 TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 16,
850 TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 17,
851 TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 18,
852 TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 19,
853 TU_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 20,
854 TU_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 21,
855 };
856
857 struct tu_streamout_state {
858 uint16_t stride[IR3_MAX_SO_BUFFERS];
859 uint32_t ncomp[IR3_MAX_SO_BUFFERS];
860 uint32_t prog[IR3_MAX_SO_OUTPUTS * 2];
861 uint32_t prog_count;
862 uint32_t vpc_so_buf_cntl;
863 };
864
865 struct tu_cmd_state
866 {
867 uint32_t dirty;
868
869 struct tu_pipeline *pipeline;
870 struct tu_pipeline *compute_pipeline;
871
872 /* Vertex buffers */
873 struct
874 {
875 struct tu_buffer *buffers[MAX_VBS];
876 VkDeviceSize offsets[MAX_VBS];
877 } vb;
878
879 struct tu_dynamic_state dynamic;
880
881 /* Stream output buffers */
882 struct
883 {
884 struct tu_buffer *buffers[IR3_MAX_SO_BUFFERS];
885 VkDeviceSize offsets[IR3_MAX_SO_BUFFERS];
886 VkDeviceSize sizes[IR3_MAX_SO_BUFFERS];
887 } streamout_buf;
888
889 uint8_t streamout_reset;
890 uint8_t streamout_enabled;
891
892 /* Index buffer */
893 struct tu_buffer *index_buffer;
894 uint64_t index_offset;
895 uint32_t index_type;
896 uint32_t max_index_count;
897 uint64_t index_va;
898
899 const struct tu_render_pass *pass;
900 const struct tu_subpass *subpass;
901 const struct tu_framebuffer *framebuffer;
902
903 struct tu_tiling_config tiling_config;
904
905 struct tu_cs_entry tile_store_ib;
906 };
907
908 struct tu_cmd_pool
909 {
910 VkAllocationCallbacks alloc;
911 struct list_head cmd_buffers;
912 struct list_head free_cmd_buffers;
913 uint32_t queue_family_index;
914 };
915
916 struct tu_cmd_buffer_upload
917 {
918 uint8_t *map;
919 unsigned offset;
920 uint64_t size;
921 struct list_head list;
922 };
923
924 enum tu_cmd_buffer_status
925 {
926 TU_CMD_BUFFER_STATUS_INVALID,
927 TU_CMD_BUFFER_STATUS_INITIAL,
928 TU_CMD_BUFFER_STATUS_RECORDING,
929 TU_CMD_BUFFER_STATUS_EXECUTABLE,
930 TU_CMD_BUFFER_STATUS_PENDING,
931 };
932
933 struct tu_bo_list
934 {
935 uint32_t count;
936 uint32_t capacity;
937 struct drm_msm_gem_submit_bo *bo_infos;
938 };
939
940 #define TU_BO_LIST_FAILED (~0)
941
942 void
943 tu_bo_list_init(struct tu_bo_list *list);
944 void
945 tu_bo_list_destroy(struct tu_bo_list *list);
946 void
947 tu_bo_list_reset(struct tu_bo_list *list);
948 uint32_t
949 tu_bo_list_add(struct tu_bo_list *list,
950 const struct tu_bo *bo,
951 uint32_t flags);
952 VkResult
953 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other);
954
955 /* This struct defines the layout of the scratch_bo */
956 struct tu6_control
957 {
958 uint32_t seqno; /* seqno for async CP_EVENT_WRITE, etc */
959 uint32_t _pad0;
960 volatile uint32_t vsc_overflow;
961 uint32_t _pad1;
962 /* flag set from cmdstream when VSC overflow detected: */
963 uint32_t vsc_scratch;
964 uint32_t _pad2;
965 uint32_t _pad3;
966 uint32_t _pad4;
967
968 /* scratch space for VPC_SO[i].FLUSH_BASE_LO/HI, start on 32 byte boundary. */
969 struct {
970 uint32_t offset;
971 uint32_t pad[7];
972 } flush_base[4];
973 };
974
975 #define ctrl_offset(member) offsetof(struct tu6_control, member)
976
977 struct tu_cmd_buffer
978 {
979 VK_LOADER_DATA _loader_data;
980
981 struct tu_device *device;
982
983 struct tu_cmd_pool *pool;
984 struct list_head pool_link;
985
986 VkCommandBufferUsageFlags usage_flags;
987 VkCommandBufferLevel level;
988 enum tu_cmd_buffer_status status;
989
990 struct tu_cmd_state state;
991 struct tu_vertex_binding vertex_bindings[MAX_VBS];
992 uint32_t queue_family_index;
993
994 uint32_t push_constants[MAX_PUSH_CONSTANTS_SIZE / 4];
995 VkShaderStageFlags push_constant_stages;
996 struct tu_descriptor_set meta_push_descriptors;
997
998 struct tu_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
999
1000 struct tu_cmd_buffer_upload upload;
1001
1002 VkResult record_result;
1003
1004 struct tu_bo_list bo_list;
1005 struct tu_cs cs;
1006 struct tu_cs draw_cs;
1007 struct tu_cs draw_epilogue_cs;
1008 struct tu_cs sub_cs;
1009
1010 struct tu_bo scratch_bo;
1011 uint32_t scratch_seqno;
1012
1013 struct tu_bo vsc_data;
1014 struct tu_bo vsc_data2;
1015 uint32_t vsc_data_pitch;
1016 uint32_t vsc_data2_pitch;
1017 bool use_vsc_data;
1018
1019 bool wait_for_idle;
1020 };
1021
1022 /* Temporary struct for tracking a register state to be written, used by
1023 * a6xx-pack.h and tu_cs_emit_regs()
1024 */
1025 struct tu_reg_value {
1026 uint32_t reg;
1027 uint64_t value;
1028 bool is_address;
1029 struct tu_bo *bo;
1030 bool bo_write;
1031 uint32_t bo_offset;
1032 uint32_t bo_shift;
1033 };
1034
1035 unsigned
1036 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
1037 struct tu_cs *cs,
1038 enum vgt_event_type event,
1039 bool need_seqno);
1040
1041 bool
1042 tu_get_memory_fd(struct tu_device *device,
1043 struct tu_device_memory *memory,
1044 int *pFD);
1045
1046 static inline struct tu_descriptor_state *
1047 tu_get_descriptors_state(struct tu_cmd_buffer *cmd_buffer,
1048 VkPipelineBindPoint bind_point)
1049 {
1050 return &cmd_buffer->descriptors[bind_point];
1051 }
1052
1053 /*
1054 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1055 *
1056 * Limitations: Can't call normal dispatch functions without binding or
1057 * rebinding
1058 * the compute pipeline.
1059 */
1060 void
1061 tu_unaligned_dispatch(struct tu_cmd_buffer *cmd_buffer,
1062 uint32_t x,
1063 uint32_t y,
1064 uint32_t z);
1065
1066 struct tu_event
1067 {
1068 struct tu_bo bo;
1069 };
1070
1071 struct tu_shader_module;
1072
1073 #define TU_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1074 #define TU_HASH_SHADER_SISCHED (1 << 1)
1075 #define TU_HASH_SHADER_UNSAFE_MATH (1 << 2)
1076 void
1077 tu_hash_shaders(unsigned char *hash,
1078 const VkPipelineShaderStageCreateInfo **stages,
1079 const struct tu_pipeline_layout *layout,
1080 const struct tu_pipeline_key *key,
1081 uint32_t flags);
1082
1083 static inline gl_shader_stage
1084 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1085 {
1086 assert(__builtin_popcount(vk_stage) == 1);
1087 return ffs(vk_stage) - 1;
1088 }
1089
1090 static inline VkShaderStageFlagBits
1091 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1092 {
1093 return (1 << mesa_stage);
1094 }
1095
1096 #define TU_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1097
1098 #define tu_foreach_stage(stage, stage_bits) \
1099 for (gl_shader_stage stage, \
1100 __tmp = (gl_shader_stage)((stage_bits) &TU_STAGE_MASK); \
1101 stage = __builtin_ffs(__tmp) - 1, __tmp; __tmp &= ~(1 << (stage)))
1102
1103 struct tu_shader_module
1104 {
1105 unsigned char sha1[20];
1106
1107 uint32_t code_size;
1108 const uint32_t *code[0];
1109 };
1110
1111 struct tu_shader_compile_options
1112 {
1113 struct ir3_shader_key key;
1114
1115 bool optimize;
1116 bool include_binning_pass;
1117 };
1118
1119 struct tu_descriptor_map
1120 {
1121 /* TODO: avoid fixed size array/justify the size */
1122 unsigned num; /* number of array entries */
1123 unsigned num_desc; /* Number of descriptors (sum of array_size[]) */
1124 int set[128];
1125 int binding[128];
1126 int value[128];
1127 int array_size[128];
1128 };
1129
1130 struct tu_shader
1131 {
1132 struct ir3_shader ir3_shader;
1133
1134 struct tu_descriptor_map texture_map;
1135 struct tu_descriptor_map sampler_map;
1136 struct tu_descriptor_map ubo_map;
1137 struct tu_descriptor_map ssbo_map;
1138 struct tu_descriptor_map image_map;
1139
1140 /* This may be true for vertex shaders. When true, variants[1] is the
1141 * binning variant and binning_binary is non-NULL.
1142 */
1143 bool has_binning_pass;
1144
1145 void *binary;
1146 void *binning_binary;
1147
1148 struct ir3_shader_variant variants[0];
1149 };
1150
1151 struct tu_shader *
1152 tu_shader_create(struct tu_device *dev,
1153 gl_shader_stage stage,
1154 const VkPipelineShaderStageCreateInfo *stage_info,
1155 struct tu_pipeline_layout *layout,
1156 const VkAllocationCallbacks *alloc);
1157
1158 void
1159 tu_shader_destroy(struct tu_device *dev,
1160 struct tu_shader *shader,
1161 const VkAllocationCallbacks *alloc);
1162
1163 void
1164 tu_shader_compile_options_init(
1165 struct tu_shader_compile_options *options,
1166 const VkGraphicsPipelineCreateInfo *pipeline_info);
1167
1168 VkResult
1169 tu_shader_compile(struct tu_device *dev,
1170 struct tu_shader *shader,
1171 const struct tu_shader *next_stage,
1172 const struct tu_shader_compile_options *options,
1173 const VkAllocationCallbacks *alloc);
1174
1175 struct tu_program_descriptor_linkage
1176 {
1177 struct ir3_ubo_analysis_state ubo_state;
1178 struct ir3_const_state const_state;
1179
1180 uint32_t constlen;
1181
1182 struct tu_descriptor_map texture_map;
1183 struct tu_descriptor_map sampler_map;
1184 struct tu_descriptor_map ubo_map;
1185 struct tu_descriptor_map ssbo_map;
1186 struct tu_descriptor_map image_map;
1187 };
1188
1189 struct tu_pipeline
1190 {
1191 struct tu_cs cs;
1192
1193 struct tu_dynamic_state dynamic_state;
1194
1195 struct tu_pipeline_layout *layout;
1196
1197 bool need_indirect_descriptor_sets;
1198 VkShaderStageFlags active_stages;
1199
1200 struct tu_streamout_state streamout;
1201
1202 struct
1203 {
1204 struct tu_bo binary_bo;
1205 struct tu_cs_entry state_ib;
1206 struct tu_cs_entry binning_state_ib;
1207
1208 struct tu_program_descriptor_linkage link[MESA_SHADER_STAGES];
1209 } program;
1210
1211 struct
1212 {
1213 uint8_t bindings[MAX_VERTEX_ATTRIBS];
1214 uint32_t count;
1215
1216 uint8_t binning_bindings[MAX_VERTEX_ATTRIBS];
1217 uint32_t binning_count;
1218
1219 struct tu_cs_entry state_ib;
1220 struct tu_cs_entry binning_state_ib;
1221 } vi;
1222
1223 struct
1224 {
1225 enum pc_di_primtype primtype;
1226 bool primitive_restart;
1227 } ia;
1228
1229 struct
1230 {
1231 struct tu_cs_entry state_ib;
1232 } vp;
1233
1234 struct
1235 {
1236 uint32_t gras_su_cntl;
1237 struct tu_cs_entry state_ib;
1238 } rast;
1239
1240 struct
1241 {
1242 struct tu_cs_entry state_ib;
1243 } ds;
1244
1245 struct
1246 {
1247 struct tu_cs_entry state_ib;
1248 } blend;
1249
1250 struct
1251 {
1252 uint32_t local_size[3];
1253 } compute;
1254 };
1255
1256 void
1257 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport);
1258
1259 void
1260 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor);
1261
1262 void
1263 tu6_emit_gras_su_cntl(struct tu_cs *cs,
1264 uint32_t gras_su_cntl,
1265 float line_width);
1266
1267 void
1268 tu6_emit_depth_bias(struct tu_cs *cs,
1269 float constant_factor,
1270 float clamp,
1271 float slope_factor);
1272
1273 void
1274 tu6_emit_stencil_compare_mask(struct tu_cs *cs,
1275 uint32_t front,
1276 uint32_t back);
1277
1278 void
1279 tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back);
1280
1281 void
1282 tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back);
1283
1284 void
1285 tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4]);
1286
1287 struct tu_userdata_info *
1288 tu_lookup_user_sgpr(struct tu_pipeline *pipeline,
1289 gl_shader_stage stage,
1290 int idx);
1291
1292 struct tu_shader_variant *
1293 tu_get_shader(struct tu_pipeline *pipeline, gl_shader_stage stage);
1294
1295 struct tu_graphics_pipeline_create_info
1296 {
1297 bool use_rectlist;
1298 bool db_depth_clear;
1299 bool db_stencil_clear;
1300 bool db_depth_disable_expclear;
1301 bool db_stencil_disable_expclear;
1302 bool db_flush_depth_inplace;
1303 bool db_flush_stencil_inplace;
1304 bool db_resummarize;
1305 uint32_t custom_blend_mode;
1306 };
1307
1308 enum tu_supported_formats {
1309 FMT_VERTEX = 1,
1310 FMT_TEXTURE = 2,
1311 FMT_COLOR = 4,
1312 };
1313
1314 struct tu_native_format
1315 {
1316 enum a6xx_format fmt : 8;
1317 enum a3xx_color_swap swap : 8;
1318 enum tu_supported_formats supported : 8;
1319 };
1320
1321 struct tu_native_format tu6_get_native_format(VkFormat format);
1322 struct tu_native_format tu6_format_vtx(VkFormat format);
1323 enum a6xx_format tu6_format_gmem(VkFormat format);
1324 struct tu_native_format tu6_format_color(VkFormat format, bool tiled);
1325 struct tu_native_format tu6_format_texture(VkFormat format, bool tiled);
1326
1327 void
1328 tu_pack_clear_value(const VkClearValue *val,
1329 VkFormat format,
1330 uint32_t buf[4]);
1331
1332 void
1333 tu_2d_clear_color(const VkClearColorValue *val, VkFormat format, uint32_t buf[4]);
1334
1335 void
1336 tu_2d_clear_zs(const VkClearDepthStencilValue *val, VkFormat format, uint32_t buf[4]);
1337
1338 enum a6xx_2d_ifmt tu6_fmt_to_ifmt(enum a6xx_format fmt);
1339 enum a6xx_depth_format tu6_pipe2depth(VkFormat format);
1340
1341 struct tu_image
1342 {
1343 VkImageType type;
1344 /* The original VkFormat provided by the client. This may not match any
1345 * of the actual surface formats.
1346 */
1347 VkFormat vk_format;
1348 VkImageAspectFlags aspects;
1349 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1350 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1351 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1352 VkExtent3D extent;
1353 uint32_t level_count;
1354 uint32_t layer_count;
1355 VkSampleCountFlagBits samples;
1356
1357 struct fdl_layout layout;
1358
1359 unsigned queue_family_mask;
1360 bool exclusive;
1361 bool shareable;
1362
1363 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1364 VkDeviceMemory owned_memory;
1365
1366 /* Set when bound */
1367 struct tu_bo *bo;
1368 VkDeviceSize bo_offset;
1369 };
1370
1371 unsigned
1372 tu_image_queue_family_mask(const struct tu_image *image,
1373 uint32_t family,
1374 uint32_t queue_family);
1375
1376 static inline uint32_t
1377 tu_get_layerCount(const struct tu_image *image,
1378 const VkImageSubresourceRange *range)
1379 {
1380 return range->layerCount == VK_REMAINING_ARRAY_LAYERS
1381 ? image->layer_count - range->baseArrayLayer
1382 : range->layerCount;
1383 }
1384
1385 static inline uint32_t
1386 tu_get_levelCount(const struct tu_image *image,
1387 const VkImageSubresourceRange *range)
1388 {
1389 return range->levelCount == VK_REMAINING_MIP_LEVELS
1390 ? image->level_count - range->baseMipLevel
1391 : range->levelCount;
1392 }
1393
1394 static inline VkDeviceSize
1395 tu_layer_size(struct tu_image *image, int level)
1396 {
1397 return fdl_layer_stride(&image->layout, level);
1398 }
1399
1400 static inline uint32_t
1401 tu_image_stride(struct tu_image *image, int level)
1402 {
1403 return image->layout.slices[level].pitch * image->layout.cpp;
1404 }
1405
1406 static inline uint64_t
1407 tu_image_base(struct tu_image *image, int level, int layer)
1408 {
1409 return image->bo->iova + image->bo_offset +
1410 fdl_surface_offset(&image->layout, level, layer);
1411 }
1412
1413 #define tu_image_base_ref(image, level, layer) \
1414 .bo = image->bo, \
1415 .bo_offset = (image->bo_offset + fdl_surface_offset(&image->layout, \
1416 level, layer))
1417
1418 #define tu_image_view_base_ref(iview) \
1419 tu_image_base_ref(iview->image, iview->base_mip, iview->base_layer)
1420
1421 static inline VkDeviceSize
1422 tu_image_ubwc_size(struct tu_image *image, int level)
1423 {
1424 return image->layout.ubwc_layer_size;
1425 }
1426
1427 static inline uint32_t
1428 tu_image_ubwc_pitch(struct tu_image *image, int level)
1429 {
1430 return image->layout.ubwc_slices[level].pitch;
1431 }
1432
1433 static inline uint64_t
1434 tu_image_ubwc_surface_offset(struct tu_image *image, int level, int layer)
1435 {
1436 return image->layout.ubwc_slices[level].offset +
1437 layer * tu_image_ubwc_size(image, level);
1438 }
1439
1440 static inline uint64_t
1441 tu_image_ubwc_base(struct tu_image *image, int level, int layer)
1442 {
1443 return image->bo->iova + image->bo_offset +
1444 tu_image_ubwc_surface_offset(image, level, layer);
1445 }
1446
1447 #define tu_image_ubwc_base_ref(image, level, layer) \
1448 .bo = image->bo, \
1449 .bo_offset = (image->bo_offset + tu_image_ubwc_surface_offset(image, \
1450 level, layer))
1451
1452 #define tu_image_view_ubwc_base_ref(iview) \
1453 tu_image_ubwc_base_ref(iview->image, iview->base_mip, iview->base_layer)
1454
1455 enum a6xx_tile_mode
1456 tu6_get_image_tile_mode(struct tu_image *image, int level);
1457 enum a3xx_msaa_samples
1458 tu_msaa_samples(uint32_t samples);
1459
1460 struct tu_image_view
1461 {
1462 struct tu_image *image; /**< VkImageViewCreateInfo::image */
1463
1464 VkImageViewType type;
1465 VkImageAspectFlags aspect_mask;
1466 VkFormat vk_format;
1467 uint32_t base_layer;
1468 uint32_t layer_count;
1469 uint32_t base_mip;
1470 uint32_t level_count;
1471 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1472
1473 uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
1474
1475 /* Descriptor for use as a storage image as opposed to a sampled image.
1476 * This has a few differences for cube maps (e.g. type).
1477 */
1478 uint32_t storage_descriptor[A6XX_TEX_CONST_DWORDS];
1479 };
1480
1481 struct tu_sampler {
1482 uint32_t descriptor[A6XX_TEX_SAMP_DWORDS];
1483 };
1484
1485 VkResult
1486 tu_image_create(VkDevice _device,
1487 const VkImageCreateInfo *pCreateInfo,
1488 const VkAllocationCallbacks *alloc,
1489 VkImage *pImage,
1490 uint64_t modifier);
1491
1492 VkResult
1493 tu_image_from_gralloc(VkDevice device_h,
1494 const VkImageCreateInfo *base_info,
1495 const VkNativeBufferANDROID *gralloc_info,
1496 const VkAllocationCallbacks *alloc,
1497 VkImage *out_image_h);
1498
1499 void
1500 tu_image_view_init(struct tu_image_view *view,
1501 struct tu_device *device,
1502 const VkImageViewCreateInfo *pCreateInfo);
1503
1504 struct tu_buffer_view
1505 {
1506 uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
1507
1508 struct tu_buffer *buffer;
1509 };
1510 void
1511 tu_buffer_view_init(struct tu_buffer_view *view,
1512 struct tu_device *device,
1513 const VkBufferViewCreateInfo *pCreateInfo);
1514
1515 static inline struct VkExtent3D
1516 tu_sanitize_image_extent(const VkImageType imageType,
1517 const struct VkExtent3D imageExtent)
1518 {
1519 switch (imageType) {
1520 case VK_IMAGE_TYPE_1D:
1521 return (VkExtent3D) { imageExtent.width, 1, 1 };
1522 case VK_IMAGE_TYPE_2D:
1523 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1524 case VK_IMAGE_TYPE_3D:
1525 return imageExtent;
1526 default:
1527 unreachable("invalid image type");
1528 }
1529 }
1530
1531 static inline struct VkOffset3D
1532 tu_sanitize_image_offset(const VkImageType imageType,
1533 const struct VkOffset3D imageOffset)
1534 {
1535 switch (imageType) {
1536 case VK_IMAGE_TYPE_1D:
1537 return (VkOffset3D) { imageOffset.x, 0, 0 };
1538 case VK_IMAGE_TYPE_2D:
1539 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1540 case VK_IMAGE_TYPE_3D:
1541 return imageOffset;
1542 default:
1543 unreachable("invalid image type");
1544 }
1545 }
1546
1547 struct tu_attachment_info
1548 {
1549 struct tu_image_view *attachment;
1550 };
1551
1552 struct tu_framebuffer
1553 {
1554 uint32_t width;
1555 uint32_t height;
1556 uint32_t layers;
1557
1558 uint32_t attachment_count;
1559 struct tu_attachment_info attachments[0];
1560 };
1561
1562 struct tu_subpass_attachment
1563 {
1564 uint32_t attachment;
1565 };
1566
1567 struct tu_subpass
1568 {
1569 uint32_t input_count;
1570 uint32_t color_count;
1571 struct tu_subpass_attachment *input_attachments;
1572 struct tu_subpass_attachment *color_attachments;
1573 struct tu_subpass_attachment *resolve_attachments;
1574 struct tu_subpass_attachment depth_stencil_attachment;
1575
1576 VkSampleCountFlagBits samples;
1577 };
1578
1579 struct tu_render_pass_attachment
1580 {
1581 VkFormat format;
1582 uint32_t samples;
1583 uint32_t cpp;
1584 VkAttachmentLoadOp load_op;
1585 VkAttachmentLoadOp stencil_load_op;
1586 VkAttachmentStoreOp store_op;
1587 VkAttachmentStoreOp stencil_store_op;
1588 int32_t gmem_offset;
1589 };
1590
1591 struct tu_render_pass
1592 {
1593 uint32_t attachment_count;
1594 uint32_t subpass_count;
1595 uint32_t gmem_pixels;
1596 struct tu_subpass_attachment *subpass_attachments;
1597 struct tu_render_pass_attachment *attachments;
1598 struct tu_subpass subpasses[0];
1599 };
1600
1601 VkResult
1602 tu_device_init_meta(struct tu_device *device);
1603 void
1604 tu_device_finish_meta(struct tu_device *device);
1605
1606 struct tu_query_pool
1607 {
1608 VkQueryType type;
1609 uint32_t stride;
1610 uint64_t size;
1611 uint32_t pipeline_statistics;
1612 struct tu_bo bo;
1613 };
1614
1615 struct tu_semaphore
1616 {
1617 uint32_t syncobj;
1618 uint32_t temp_syncobj;
1619 };
1620
1621 void
1622 tu_set_descriptor_set(struct tu_cmd_buffer *cmd_buffer,
1623 VkPipelineBindPoint bind_point,
1624 struct tu_descriptor_set *set,
1625 unsigned idx);
1626
1627 void
1628 tu_update_descriptor_sets(struct tu_device *device,
1629 struct tu_cmd_buffer *cmd_buffer,
1630 VkDescriptorSet overrideSet,
1631 uint32_t descriptorWriteCount,
1632 const VkWriteDescriptorSet *pDescriptorWrites,
1633 uint32_t descriptorCopyCount,
1634 const VkCopyDescriptorSet *pDescriptorCopies);
1635
1636 void
1637 tu_update_descriptor_set_with_template(
1638 struct tu_device *device,
1639 struct tu_cmd_buffer *cmd_buffer,
1640 struct tu_descriptor_set *set,
1641 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
1642 const void *pData);
1643
1644 void
1645 tu_meta_push_descriptor_set(struct tu_cmd_buffer *cmd_buffer,
1646 VkPipelineBindPoint pipelineBindPoint,
1647 VkPipelineLayout _layout,
1648 uint32_t set,
1649 uint32_t descriptorWriteCount,
1650 const VkWriteDescriptorSet *pDescriptorWrites);
1651
1652 int
1653 tu_drm_get_gpu_id(const struct tu_physical_device *dev, uint32_t *id);
1654
1655 int
1656 tu_drm_get_gmem_size(const struct tu_physical_device *dev, uint32_t *size);
1657
1658 int
1659 tu_drm_get_gmem_base(const struct tu_physical_device *dev, uint64_t *base);
1660
1661 int
1662 tu_drm_submitqueue_new(const struct tu_device *dev,
1663 int priority,
1664 uint32_t *queue_id);
1665
1666 void
1667 tu_drm_submitqueue_close(const struct tu_device *dev, uint32_t queue_id);
1668
1669 uint32_t
1670 tu_gem_new(const struct tu_device *dev, uint64_t size, uint32_t flags);
1671 uint32_t
1672 tu_gem_import_dmabuf(const struct tu_device *dev,
1673 int prime_fd,
1674 uint64_t size);
1675 int
1676 tu_gem_export_dmabuf(const struct tu_device *dev, uint32_t gem_handle);
1677 void
1678 tu_gem_close(const struct tu_device *dev, uint32_t gem_handle);
1679 uint64_t
1680 tu_gem_info_offset(const struct tu_device *dev, uint32_t gem_handle);
1681 uint64_t
1682 tu_gem_info_iova(const struct tu_device *dev, uint32_t gem_handle);
1683
1684
1685 void
1686 tu_clear_sysmem_attachment(struct tu_cmd_buffer *cmd,
1687 struct tu_cs *cs,
1688 uint32_t attachment,
1689 const VkClearValue *value,
1690 const VkClearRect *rect);
1691
1692 void
1693 tu_clear_gmem_attachment(struct tu_cmd_buffer *cmd,
1694 struct tu_cs *cs,
1695 uint32_t attachment,
1696 uint8_t component_mask,
1697 const VkClearValue *value);
1698
1699 #define TU_DEFINE_HANDLE_CASTS(__tu_type, __VkType) \
1700 \
1701 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1702 { \
1703 return (struct __tu_type *) _handle; \
1704 } \
1705 \
1706 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1707 { \
1708 return (__VkType) _obj; \
1709 }
1710
1711 #define TU_DEFINE_NONDISP_HANDLE_CASTS(__tu_type, __VkType) \
1712 \
1713 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1714 { \
1715 return (struct __tu_type *) (uintptr_t) _handle; \
1716 } \
1717 \
1718 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1719 { \
1720 return (__VkType)(uintptr_t) _obj; \
1721 }
1722
1723 #define TU_FROM_HANDLE(__tu_type, __name, __handle) \
1724 struct __tu_type *__name = __tu_type##_from_handle(__handle)
1725
1726 TU_DEFINE_HANDLE_CASTS(tu_cmd_buffer, VkCommandBuffer)
1727 TU_DEFINE_HANDLE_CASTS(tu_device, VkDevice)
1728 TU_DEFINE_HANDLE_CASTS(tu_instance, VkInstance)
1729 TU_DEFINE_HANDLE_CASTS(tu_physical_device, VkPhysicalDevice)
1730 TU_DEFINE_HANDLE_CASTS(tu_queue, VkQueue)
1731
1732 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_cmd_pool, VkCommandPool)
1733 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer, VkBuffer)
1734 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer_view, VkBufferView)
1735 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_pool, VkDescriptorPool)
1736 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set, VkDescriptorSet)
1737 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set_layout,
1738 VkDescriptorSetLayout)
1739 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_update_template,
1740 VkDescriptorUpdateTemplate)
1741 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_device_memory, VkDeviceMemory)
1742 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_fence, VkFence)
1743 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_event, VkEvent)
1744 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_framebuffer, VkFramebuffer)
1745 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image, VkImage)
1746 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image_view, VkImageView);
1747 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_cache, VkPipelineCache)
1748 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline, VkPipeline)
1749 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_layout, VkPipelineLayout)
1750 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_query_pool, VkQueryPool)
1751 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_render_pass, VkRenderPass)
1752 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_sampler, VkSampler)
1753 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_shader_module, VkShaderModule)
1754 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_semaphore, VkSemaphore)
1755
1756 #endif /* TU_PRIVATE_H */