2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
43 #define VG(x) ((void)0)
46 #include "c11/threads.h"
47 #include "main/macros.h"
48 #include "util/list.h"
49 #include "util/macros.h"
51 #include "vk_debug_report.h"
52 #include "wsi_common.h"
54 #include "drm-uapi/msm_drm.h"
55 #include "ir3/ir3_compiler.h"
56 #include "ir3/ir3_shader.h"
58 #include "adreno_common.xml.h"
59 #include "adreno_pm4.xml.h"
61 #include "fdl/freedreno_layout.h"
63 #include "tu_descriptor_set.h"
64 #include "tu_extensions.h"
66 /* Pre-declarations needed for WSI entrypoints */
69 typedef struct xcb_connection_t xcb_connection_t
;
70 typedef uint32_t xcb_visualid_t
;
71 typedef uint32_t xcb_window_t
;
73 #include <vulkan/vk_android_native_buffer.h>
74 #include <vulkan/vk_icd.h>
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
78 #include "tu_entrypoints.h"
80 #include "vk_format.h"
83 #define MAX_VERTEX_ATTRIBS 32
85 #define MAX_VSC_PIPES 32
86 #define MAX_VIEWPORTS 1
87 #define MAX_SCISSORS 16
88 #define MAX_DISCARD_RECTANGLES 4
89 #define MAX_PUSH_CONSTANTS_SIZE 128
90 #define MAX_PUSH_DESCRIPTORS 32
91 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
92 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
93 #define MAX_DYNAMIC_BUFFERS \
94 (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
95 #define MAX_SAMPLES_LOG2 4
96 #define NUM_META_FS_KEYS 13
97 #define TU_MAX_DRM_DEVICES 8
99 #define MAX_BIND_POINTS 2 /* compute + graphics */
100 /* The Qualcomm driver exposes 0x20000058 */
101 #define MAX_STORAGE_BUFFER_RANGE 0x20000000
102 /* We use ldc for uniform buffer loads, just like the Qualcomm driver, so
103 * expose the same maximum range.
104 * TODO: The SIZE bitfield is 15 bits, and in 4-dword units, so the actual
105 * range might be higher.
107 #define MAX_UNIFORM_BUFFER_RANGE 0x10000
109 #define NUM_DEPTH_CLEAR_PIPELINES 3
112 * This is the point we switch from using CP to compute shader
113 * for certain buffer operations.
115 #define TU_BUFFER_OPS_CS_THRESHOLD 4096
117 #define A6XX_TEX_CONST_DWORDS 16
118 #define A6XX_TEX_SAMP_DWORDS 4
123 TU_MEM_HEAP_VRAM_CPU_ACCESS
,
131 TU_MEM_TYPE_GTT_WRITE_COMBINE
,
132 TU_MEM_TYPE_VRAM_CPU_ACCESS
,
133 TU_MEM_TYPE_GTT_CACHED
,
137 #define tu_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
139 static inline uint32_t
140 align_u32(uint32_t v
, uint32_t a
)
142 assert(a
!= 0 && a
== (a
& -a
));
143 return (v
+ a
- 1) & ~(a
- 1);
146 static inline uint32_t
147 align_u32_npot(uint32_t v
, uint32_t a
)
149 return (v
+ a
- 1) / a
* a
;
152 static inline uint64_t
153 align_u64(uint64_t v
, uint64_t a
)
155 assert(a
!= 0 && a
== (a
& -a
));
156 return (v
+ a
- 1) & ~(a
- 1);
159 static inline int32_t
160 align_i32(int32_t v
, int32_t a
)
162 assert(a
!= 0 && a
== (a
& -a
));
163 return (v
+ a
- 1) & ~(a
- 1);
166 /** Alignment must be a power of 2. */
168 tu_is_aligned(uintmax_t n
, uintmax_t a
)
170 assert(a
== (a
& -a
));
171 return (n
& (a
- 1)) == 0;
174 static inline uint32_t
175 round_up_u32(uint32_t v
, uint32_t a
)
177 return (v
+ a
- 1) / a
;
180 static inline uint64_t
181 round_up_u64(uint64_t v
, uint64_t a
)
183 return (v
+ a
- 1) / a
;
186 static inline uint32_t
187 tu_minify(uint32_t n
, uint32_t levels
)
189 if (unlikely(n
== 0))
192 return MAX2(n
>> levels
, 1);
195 tu_clamp_f(float f
, float min
, float max
)
208 tu_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
210 if (*inout_mask
& clear_mask
) {
211 *inout_mask
&= ~clear_mask
;
218 #define for_each_bit(b, dword) \
219 for (uint32_t __dword = (dword); \
220 (b) = __builtin_ffs(__dword) - 1, __dword; __dword &= ~(1 << (b)))
222 #define typed_memcpy(dest, src, count) \
224 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
225 memcpy((dest), (src), (count) * sizeof(*(src))); \
228 #define COND(bool, val) ((bool) ? (val) : 0)
230 /* Whenever we generate an error, pass it through this function. Useful for
231 * debugging, where we can break on it. Only call at error site, not when
232 * propagating errors. Might be useful to plug in a stack trace here.
238 __vk_errorf(struct tu_instance
*instance
,
245 #define vk_error(instance, error) \
246 __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
247 #define vk_errorf(instance, error, format, ...) \
248 __vk_errorf(instance, error, __FILE__, __LINE__, format, ##__VA_ARGS__);
251 __tu_finishme(const char *file
, int line
, const char *format
, ...)
254 tu_loge(const char *format
, ...) tu_printflike(1, 2);
256 tu_loge_v(const char *format
, va_list va
);
258 tu_logi(const char *format
, ...) tu_printflike(1, 2);
260 tu_logi_v(const char *format
, va_list va
);
263 * Print a FINISHME message, including its source location.
265 #define tu_finishme(format, ...) \
267 static bool reported = false; \
269 __tu_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
274 /* A non-fatal assert. Useful for debugging. */
276 #define tu_assert(x) \
278 if (unlikely(!(x))) \
279 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
285 /* Suppress -Wunused in stub functions */
286 #define tu_use_args(...) __tu_use_args(0, ##__VA_ARGS__)
288 __tu_use_args(int ignore
, ...)
294 tu_finishme("stub %s", __func__); \
298 tu_lookup_entrypoint_unchecked(const char *name
);
300 tu_lookup_entrypoint_checked(
302 uint32_t core_version
,
303 const struct tu_instance_extension_table
*instance
,
304 const struct tu_device_extension_table
*device
);
306 struct tu_physical_device
308 VK_LOADER_DATA _loader_data
;
310 struct tu_instance
*instance
;
313 char name
[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE
];
314 uint8_t driver_uuid
[VK_UUID_SIZE
];
315 uint8_t device_uuid
[VK_UUID_SIZE
];
316 uint8_t cache_uuid
[VK_UUID_SIZE
];
318 struct wsi_device wsi_device
;
326 uint32_t ccu_offset_gmem
;
327 uint32_t ccu_offset_bypass
;
328 /* alignment for size of tiles */
329 uint32_t tile_align_w
;
330 #define TILE_ALIGN_H 16
331 /* gmem store/load granularity */
332 #define GMEM_ALIGN_W 16
333 #define GMEM_ALIGN_H 4
336 uint32_t PC_UNKNOWN_9805
;
337 uint32_t SP_UNKNOWN_A0F8
;
340 /* This is the drivers on-disk cache used as a fallback as opposed to
341 * the pipeline cache defined by apps.
343 struct disk_cache
*disk_cache
;
345 struct tu_device_extension_table supported_extensions
;
350 TU_DEBUG_STARTUP
= 1 << 0,
351 TU_DEBUG_NIR
= 1 << 1,
352 TU_DEBUG_IR3
= 1 << 2,
353 TU_DEBUG_NOBIN
= 1 << 3,
354 TU_DEBUG_SYSMEM
= 1 << 4,
355 TU_DEBUG_FORCEBIN
= 1 << 5,
356 TU_DEBUG_NOUBWC
= 1 << 6,
361 VK_LOADER_DATA _loader_data
;
363 VkAllocationCallbacks alloc
;
365 uint32_t api_version
;
366 int physical_device_count
;
367 struct tu_physical_device physical_devices
[TU_MAX_DRM_DEVICES
];
369 enum tu_debug_flags debug_flags
;
371 struct vk_debug_report_instance debug_report_callbacks
;
373 struct tu_instance_extension_table enabled_extensions
;
377 tu_wsi_init(struct tu_physical_device
*physical_device
);
379 tu_wsi_finish(struct tu_physical_device
*physical_device
);
382 tu_instance_extension_supported(const char *name
);
384 tu_physical_device_api_version(struct tu_physical_device
*dev
);
386 tu_physical_device_extension_supported(struct tu_physical_device
*dev
,
391 struct tu_pipeline_cache
393 struct tu_device
*device
;
394 pthread_mutex_t mutex
;
398 uint32_t kernel_count
;
399 struct cache_entry
**hash_table
;
402 VkAllocationCallbacks alloc
;
405 struct tu_pipeline_key
410 tu_pipeline_cache_init(struct tu_pipeline_cache
*cache
,
411 struct tu_device
*device
);
413 tu_pipeline_cache_finish(struct tu_pipeline_cache
*cache
);
415 tu_pipeline_cache_load(struct tu_pipeline_cache
*cache
,
419 struct tu_shader_variant
;
422 tu_create_shader_variants_from_pipeline_cache(
423 struct tu_device
*device
,
424 struct tu_pipeline_cache
*cache
,
425 const unsigned char *sha1
,
426 struct tu_shader_variant
**variants
);
429 tu_pipeline_cache_insert_shaders(struct tu_device
*device
,
430 struct tu_pipeline_cache
*cache
,
431 const unsigned char *sha1
,
432 struct tu_shader_variant
**variants
,
433 const void *const *codes
,
434 const unsigned *code_sizes
);
438 VkAllocationCallbacks alloc
;
440 struct tu_pipeline_cache cache
;
444 #define TU_QUEUE_GENERAL 0
446 #define TU_MAX_QUEUE_FAMILIES 1
450 struct wsi_fence
*fence_wsi
;
456 tu_fence_init(struct tu_fence
*fence
, bool signaled
);
458 tu_fence_finish(struct tu_fence
*fence
);
460 tu_fence_update_fd(struct tu_fence
*fence
, int fd
);
462 tu_fence_copy(struct tu_fence
*fence
, const struct tu_fence
*src
);
464 tu_fence_signal(struct tu_fence
*fence
);
466 tu_fence_wait_idle(struct tu_fence
*fence
);
470 VK_LOADER_DATA _loader_data
;
471 struct tu_device
*device
;
472 uint32_t queue_family_index
;
474 VkDeviceQueueCreateFlags flags
;
476 uint32_t msm_queue_id
;
477 struct tu_fence submit_fence
;
490 VK_LOADER_DATA _loader_data
;
492 VkAllocationCallbacks alloc
;
494 struct tu_instance
*instance
;
496 struct tu_meta_state meta_state
;
498 struct tu_queue
*queues
[TU_MAX_QUEUE_FAMILIES
];
499 int queue_count
[TU_MAX_QUEUE_FAMILIES
];
501 struct tu_physical_device
*physical_device
;
503 struct ir3_compiler
*compiler
;
505 /* Backup in-memory cache to be used if the app doesn't provide one */
506 struct tu_pipeline_cache
*mem_cache
;
508 struct tu_bo vsc_draw_strm
;
509 struct tu_bo vsc_prim_strm
;
510 uint32_t vsc_draw_strm_pitch
;
511 uint32_t vsc_prim_strm_pitch
;
513 #define MIN_SCRATCH_BO_SIZE_LOG2 12 /* A page */
515 /* Currently the kernel driver uses a 32-bit GPU address space, but it
516 * should be impossible to go beyond 48 bits.
522 } scratch_bos
[48 - MIN_SCRATCH_BO_SIZE_LOG2
];
524 struct tu_bo border_color
;
526 struct list_head shader_slabs
;
527 mtx_t shader_slab_mutex
;
529 struct tu_device_extension_table enabled_extensions
;
533 tu_bo_init_new(struct tu_device
*dev
, struct tu_bo
*bo
, uint64_t size
);
535 tu_bo_init_dmabuf(struct tu_device
*dev
,
540 tu_bo_export_dmabuf(struct tu_device
*dev
, struct tu_bo
*bo
);
542 tu_bo_finish(struct tu_device
*dev
, struct tu_bo
*bo
);
544 tu_bo_map(struct tu_device
*dev
, struct tu_bo
*bo
);
546 /* Get a scratch bo for use inside a command buffer. This will always return
547 * the same bo given the same size or similar sizes, so only one scratch bo
548 * can be used at the same time. It's meant for short-lived things where we
549 * need to write to some piece of memory, read from it, and then immediately
553 tu_get_scratch_bo(struct tu_device
*dev
, uint64_t size
, struct tu_bo
**bo
);
558 const struct tu_bo
*bo
;
564 struct ts_cs_memory
{
573 * A command stream in TU_CS_MODE_GROW mode grows automatically whenever it
574 * is full. tu_cs_begin must be called before command packet emission and
575 * tu_cs_end must be called after.
577 * This mode may create multiple entries internally. The entries must be
578 * submitted together.
583 * A command stream in TU_CS_MODE_EXTERNAL mode wraps an external,
584 * fixed-size buffer. tu_cs_begin and tu_cs_end are optional and have no
587 * This mode does not create any entry or any BO.
592 * A command stream in TU_CS_MODE_SUB_STREAM mode does not support direct
593 * command packet emission. tu_cs_begin_sub_stream must be called to get a
594 * sub-stream to emit comamnd packets to. When done with the sub-stream,
595 * tu_cs_end_sub_stream must be called.
597 * This mode does not create any entry internally.
599 TU_CS_MODE_SUB_STREAM
,
606 uint32_t *reserved_end
;
609 struct tu_device
*device
;
610 enum tu_cs_mode mode
;
611 uint32_t next_bo_size
;
613 struct tu_cs_entry
*entries
;
614 uint32_t entry_count
;
615 uint32_t entry_capacity
;
619 uint32_t bo_capacity
;
621 /* state for cond_exec_start/cond_exec_end */
623 uint32_t *cond_dwords
;
626 struct tu_device_memory
631 /* for dedicated allocations */
632 struct tu_image
*image
;
633 struct tu_buffer
*buffer
;
640 struct tu_descriptor_range
646 struct tu_descriptor_set
648 const struct tu_descriptor_set_layout
*layout
;
649 struct tu_descriptor_pool
*pool
;
653 uint32_t *mapped_ptr
;
655 uint32_t *dynamic_descriptors
;
657 struct tu_bo
*buffers
[0];
660 struct tu_push_descriptor_set
662 struct tu_descriptor_set set
;
666 struct tu_descriptor_pool_entry
670 struct tu_descriptor_set
*set
;
673 struct tu_descriptor_pool
676 uint64_t current_offset
;
679 uint8_t *host_memory_base
;
680 uint8_t *host_memory_ptr
;
681 uint8_t *host_memory_end
;
683 uint32_t entry_count
;
684 uint32_t max_entry_count
;
685 struct tu_descriptor_pool_entry entries
[0];
688 struct tu_descriptor_update_template_entry
690 VkDescriptorType descriptor_type
;
692 /* The number of descriptors to update */
693 uint32_t descriptor_count
;
695 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array
699 /* In dwords. Not valid/used for dynamic descriptors */
702 uint32_t buffer_offset
;
704 /* Only valid for combined image samplers and samplers */
705 uint16_t has_sampler
;
711 /* For push descriptors */
712 const uint32_t *immutable_samplers
;
715 struct tu_descriptor_update_template
717 uint32_t entry_count
;
718 struct tu_descriptor_update_template_entry entry
[0];
725 VkBufferUsageFlags usage
;
726 VkBufferCreateFlags flags
;
729 VkDeviceSize bo_offset
;
732 static inline uint64_t
733 tu_buffer_iova(struct tu_buffer
*buffer
)
735 return buffer
->bo
->iova
+ buffer
->bo_offset
;
738 enum tu_dynamic_state_bits
740 TU_DYNAMIC_VIEWPORT
= 1 << 0,
741 TU_DYNAMIC_SCISSOR
= 1 << 1,
742 TU_DYNAMIC_LINE_WIDTH
= 1 << 2,
743 TU_DYNAMIC_DEPTH_BIAS
= 1 << 3,
744 TU_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
745 TU_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
746 TU_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
747 TU_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
748 TU_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
749 TU_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
750 TU_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
751 TU_DYNAMIC_ALL
= (1 << 11) - 1,
754 struct tu_vertex_binding
756 struct tu_buffer
*buffer
;
760 struct tu_viewport_state
763 VkViewport viewports
[MAX_VIEWPORTS
];
766 struct tu_scissor_state
769 VkRect2D scissors
[MAX_SCISSORS
];
772 struct tu_discard_rectangle_state
775 VkRect2D rectangles
[MAX_DISCARD_RECTANGLES
];
778 struct tu_dynamic_state
781 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
782 * Defines the set of saved dynamic state.
786 struct tu_viewport_state viewport
;
788 struct tu_scissor_state scissor
;
799 float blend_constants
[4];
811 } stencil_compare_mask
;
817 } stencil_write_mask
;
825 struct tu_discard_rectangle_state discard_rectangle
;
828 extern const struct tu_dynamic_state default_dynamic_state
;
831 tu_get_debug_option_name(int id
);
834 tu_get_perftest_option_name(int id
);
836 struct tu_descriptor_state
838 struct tu_descriptor_set
*sets
[MAX_SETS
];
840 struct tu_push_descriptor_set push_set
;
842 uint32_t dynamic_descriptors
[MAX_DYNAMIC_BUFFERS
* A6XX_TEX_CONST_DWORDS
];
843 uint32_t input_attachments
[MAX_RTS
* A6XX_TEX_CONST_DWORDS
];
854 struct tu_tiling_config
856 VkRect2D render_area
;
858 /* position and size of the first tile */
860 /* number of tiles */
861 VkExtent2D tile_count
;
863 /* size of the first VSC pipe */
865 /* number of VSC pipes */
866 VkExtent2D pipe_count
;
868 /* pipe register values */
869 uint32_t pipe_config
[MAX_VSC_PIPES
];
870 uint32_t pipe_sizes
[MAX_VSC_PIPES
];
872 /* Whether sysmem rendering must be used */
876 enum tu_cmd_dirty_bits
878 TU_CMD_DIRTY_PIPELINE
= 1 << 0,
879 TU_CMD_DIRTY_COMPUTE_PIPELINE
= 1 << 1,
880 TU_CMD_DIRTY_VERTEX_BUFFERS
= 1 << 2,
882 TU_CMD_DIRTY_DESCRIPTOR_SETS
= 1 << 3,
883 TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
= 1 << 4,
884 TU_CMD_DIRTY_PUSH_CONSTANTS
= 1 << 5,
885 TU_CMD_DIRTY_STREAMOUT_BUFFERS
= 1 << 6,
886 TU_CMD_DIRTY_INPUT_ATTACHMENTS
= 1 << 7,
888 TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 16,
889 TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 17,
890 TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 18,
891 TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 19,
892 TU_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 20,
893 TU_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 21,
896 struct tu_streamout_state
{
897 uint16_t stride
[IR3_MAX_SO_BUFFERS
];
898 uint32_t ncomp
[IR3_MAX_SO_BUFFERS
];
899 uint32_t prog
[IR3_MAX_SO_OUTPUTS
* 2];
901 uint32_t vpc_so_buf_cntl
;
904 /* There are only three cache domains we have to care about: the CCU, or
905 * color cache unit, which is used for color and depth/stencil attachments
906 * and copy/blit destinations, and is split conceptually into color and depth,
907 * and the universal cache or UCHE which is used for pretty much everything
908 * else, except for the CP (uncached) and host. We need to flush whenever data
909 * crosses these boundaries.
912 enum tu_cmd_access_mask
{
913 TU_ACCESS_UCHE_READ
= 1 << 0,
914 TU_ACCESS_UCHE_WRITE
= 1 << 1,
915 TU_ACCESS_CCU_COLOR_READ
= 1 << 2,
916 TU_ACCESS_CCU_COLOR_WRITE
= 1 << 3,
917 TU_ACCESS_CCU_DEPTH_READ
= 1 << 4,
918 TU_ACCESS_CCU_DEPTH_WRITE
= 1 << 5,
920 /* Experiments have shown that while it's safe to avoid flushing the CCU
921 * after each blit/renderpass, it's not safe to assume that subsequent
922 * lookups with a different attachment state will hit unflushed cache
923 * entries. That is, the CCU needs to be flushed and possibly invalidated
924 * when accessing memory with a different attachment state. Writing to an
925 * attachment under the following conditions after clearing using the
926 * normal 2d engine path is known to have issues:
928 * - It isn't the 0'th layer.
929 * - There are more than one attachment, and this isn't the 0'th attachment
930 * (this seems to also depend on the cpp of the attachments).
932 * Our best guess is that the layer/MRT state is used when computing
933 * the location of a cache entry in CCU, to avoid conflicts. We assume that
934 * any access in a renderpass after or before an access by a transfer needs
935 * a flush/invalidate, and use the _INCOHERENT variants to represent access
938 TU_ACCESS_CCU_COLOR_INCOHERENT_READ
= 1 << 6,
939 TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
= 1 << 7,
940 TU_ACCESS_CCU_DEPTH_INCOHERENT_READ
= 1 << 8,
941 TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE
= 1 << 9,
943 TU_ACCESS_SYSMEM_READ
= 1 << 10,
944 TU_ACCESS_SYSMEM_WRITE
= 1 << 11,
946 /* Set if a WFI is required due to data being read by the CP or the 2D
949 TU_ACCESS_WFI_READ
= 1 << 12,
952 TU_ACCESS_UCHE_READ
|
953 TU_ACCESS_CCU_COLOR_READ
|
954 TU_ACCESS_CCU_DEPTH_READ
|
955 TU_ACCESS_CCU_COLOR_INCOHERENT_READ
|
956 TU_ACCESS_CCU_DEPTH_INCOHERENT_READ
|
957 TU_ACCESS_SYSMEM_READ
,
960 TU_ACCESS_UCHE_WRITE
|
961 TU_ACCESS_CCU_COLOR_WRITE
|
962 TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
|
963 TU_ACCESS_CCU_DEPTH_WRITE
|
964 TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE
|
965 TU_ACCESS_SYSMEM_WRITE
,
972 enum tu_cmd_flush_bits
{
973 TU_CMD_FLAG_CCU_FLUSH_DEPTH
= 1 << 0,
974 TU_CMD_FLAG_CCU_FLUSH_COLOR
= 1 << 1,
975 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
= 1 << 2,
976 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
= 1 << 3,
977 TU_CMD_FLAG_CACHE_FLUSH
= 1 << 4,
978 TU_CMD_FLAG_CACHE_INVALIDATE
= 1 << 5,
980 TU_CMD_FLAG_ALL_FLUSH
=
981 TU_CMD_FLAG_CCU_FLUSH_DEPTH
|
982 TU_CMD_FLAG_CCU_FLUSH_COLOR
|
983 TU_CMD_FLAG_CACHE_FLUSH
,
985 TU_CMD_FLAG_ALL_INVALIDATE
=
986 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
|
987 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
|
988 TU_CMD_FLAG_CACHE_INVALIDATE
,
990 TU_CMD_FLAG_WFI
= 1 << 6,
993 /* Changing the CCU from sysmem mode to gmem mode or vice-versa is pretty
994 * heavy, involving a CCU cache flush/invalidate and a WFI in order to change
995 * which part of the gmem is used by the CCU. Here we keep track of what the
998 enum tu_cmd_ccu_state
{
1004 struct tu_cache_state
{
1005 /* Caches which must be made available (flushed) eventually if there are
1006 * any users outside that cache domain, and caches which must be
1007 * invalidated eventually if there are any reads.
1009 enum tu_cmd_flush_bits pending_flush_bits
;
1010 /* Pending flushes */
1011 enum tu_cmd_flush_bits flush_bits
;
1018 struct tu_pipeline
*pipeline
;
1019 struct tu_pipeline
*compute_pipeline
;
1021 /* Vertex buffers */
1024 struct tu_buffer
*buffers
[MAX_VBS
];
1025 VkDeviceSize offsets
[MAX_VBS
];
1028 struct tu_dynamic_state dynamic
;
1030 /* Stream output buffers */
1033 struct tu_buffer
*buffers
[IR3_MAX_SO_BUFFERS
];
1034 VkDeviceSize offsets
[IR3_MAX_SO_BUFFERS
];
1035 VkDeviceSize sizes
[IR3_MAX_SO_BUFFERS
];
1038 uint8_t streamout_reset
;
1039 uint8_t streamout_enabled
;
1042 struct tu_buffer
*index_buffer
;
1043 uint64_t index_offset
;
1044 uint32_t index_type
;
1045 uint32_t max_index_count
;
1048 /* Renderpasses are tricky, because we may need to flush differently if
1049 * using sysmem vs. gmem and therefore we have to delay any flushing that
1050 * happens before a renderpass. So we have to have two copies of the flush
1051 * state, one for intra-renderpass flushes (i.e. renderpass dependencies)
1052 * and one for outside a renderpass.
1054 struct tu_cache_state cache
;
1055 struct tu_cache_state renderpass_cache
;
1057 enum tu_cmd_ccu_state ccu_state
;
1059 const struct tu_render_pass
*pass
;
1060 const struct tu_subpass
*subpass
;
1061 const struct tu_framebuffer
*framebuffer
;
1063 struct tu_tiling_config tiling_config
;
1065 struct tu_cs_entry tile_store_ib
;
1070 VkAllocationCallbacks alloc
;
1071 struct list_head cmd_buffers
;
1072 struct list_head free_cmd_buffers
;
1073 uint32_t queue_family_index
;
1076 struct tu_cmd_buffer_upload
1081 struct list_head list
;
1084 enum tu_cmd_buffer_status
1086 TU_CMD_BUFFER_STATUS_INVALID
,
1087 TU_CMD_BUFFER_STATUS_INITIAL
,
1088 TU_CMD_BUFFER_STATUS_RECORDING
,
1089 TU_CMD_BUFFER_STATUS_EXECUTABLE
,
1090 TU_CMD_BUFFER_STATUS_PENDING
,
1097 struct drm_msm_gem_submit_bo
*bo_infos
;
1100 #define TU_BO_LIST_FAILED (~0)
1103 tu_bo_list_init(struct tu_bo_list
*list
);
1105 tu_bo_list_destroy(struct tu_bo_list
*list
);
1107 tu_bo_list_reset(struct tu_bo_list
*list
);
1109 tu_bo_list_add(struct tu_bo_list
*list
,
1110 const struct tu_bo
*bo
,
1113 tu_bo_list_merge(struct tu_bo_list
*list
, const struct tu_bo_list
*other
);
1115 /* This struct defines the layout of the scratch_bo */
1118 uint32_t seqno_dummy
; /* dummy seqno for CP_EVENT_WRITE */
1120 volatile uint32_t vsc_overflow
;
1122 /* flag set from cmdstream when VSC overflow detected: */
1123 uint32_t vsc_scratch
;
1128 /* scratch space for VPC_SO[i].FLUSH_BASE_LO/HI, start on 32 byte boundary. */
1135 #define ctrl_offset(member) offsetof(struct tu6_control, member)
1137 struct tu_cmd_buffer
1139 VK_LOADER_DATA _loader_data
;
1141 struct tu_device
*device
;
1143 struct tu_cmd_pool
*pool
;
1144 struct list_head pool_link
;
1146 VkCommandBufferUsageFlags usage_flags
;
1147 VkCommandBufferLevel level
;
1148 enum tu_cmd_buffer_status status
;
1150 struct tu_cmd_state state
;
1151 struct tu_vertex_binding vertex_bindings
[MAX_VBS
];
1152 uint32_t vertex_bindings_set
;
1153 uint32_t queue_family_index
;
1155 uint32_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
/ 4];
1156 VkShaderStageFlags push_constant_stages
;
1157 struct tu_descriptor_set meta_push_descriptors
;
1159 struct tu_descriptor_state descriptors
[MAX_BIND_POINTS
];
1161 struct tu_cmd_buffer_upload upload
;
1163 VkResult record_result
;
1165 struct tu_bo_list bo_list
;
1167 struct tu_cs draw_cs
;
1168 struct tu_cs draw_epilogue_cs
;
1169 struct tu_cs sub_cs
;
1171 struct tu_bo scratch_bo
;
1173 struct tu_bo vsc_draw_strm
;
1174 struct tu_bo vsc_prim_strm
;
1175 uint32_t vsc_draw_strm_pitch
;
1176 uint32_t vsc_prim_strm_pitch
;
1180 /* Temporary struct for tracking a register state to be written, used by
1181 * a6xx-pack.h and tu_cs_emit_regs()
1183 struct tu_reg_value
{
1193 void tu_emit_cache_flush_ccu(struct tu_cmd_buffer
*cmd_buffer
,
1195 enum tu_cmd_ccu_state ccu_state
);
1198 tu6_emit_event_write(struct tu_cmd_buffer
*cmd
,
1200 enum vgt_event_type event
);
1203 tu_get_memory_fd(struct tu_device
*device
,
1204 struct tu_device_memory
*memory
,
1207 static inline struct tu_descriptor_state
*
1208 tu_get_descriptors_state(struct tu_cmd_buffer
*cmd_buffer
,
1209 VkPipelineBindPoint bind_point
)
1211 return &cmd_buffer
->descriptors
[bind_point
];
1215 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1217 * Limitations: Can't call normal dispatch functions without binding or
1219 * the compute pipeline.
1222 tu_unaligned_dispatch(struct tu_cmd_buffer
*cmd_buffer
,
1232 struct tu_shader_module
;
1234 #define TU_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1235 #define TU_HASH_SHADER_SISCHED (1 << 1)
1236 #define TU_HASH_SHADER_UNSAFE_MATH (1 << 2)
1238 tu_hash_shaders(unsigned char *hash
,
1239 const VkPipelineShaderStageCreateInfo
**stages
,
1240 const struct tu_pipeline_layout
*layout
,
1241 const struct tu_pipeline_key
*key
,
1244 static inline gl_shader_stage
1245 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1247 assert(__builtin_popcount(vk_stage
) == 1);
1248 return ffs(vk_stage
) - 1;
1251 static inline VkShaderStageFlagBits
1252 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1254 return (1 << mesa_stage
);
1257 #define TU_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1259 #define tu_foreach_stage(stage, stage_bits) \
1260 for (gl_shader_stage stage, \
1261 __tmp = (gl_shader_stage)((stage_bits) &TU_STAGE_MASK); \
1262 stage = __builtin_ffs(__tmp) - 1, __tmp; __tmp &= ~(1 << (stage)))
1264 struct tu_shader_module
1266 unsigned char sha1
[20];
1269 const uint32_t *code
[0];
1272 struct tu_shader_compile_options
1274 struct ir3_shader_key key
;
1277 bool include_binning_pass
;
1280 struct tu_push_constant_range
1288 struct ir3_shader ir3_shader
;
1290 struct tu_push_constant_range push_consts
;
1291 unsigned attachment_idx
[MAX_RTS
];
1292 uint8_t active_desc_sets
;
1294 /* This may be true for vertex shaders. When true, variants[1] is the
1295 * binning variant and binning_binary is non-NULL.
1297 bool has_binning_pass
;
1300 void *binning_binary
;
1302 struct ir3_shader_variant variants
[0];
1306 tu_shader_create(struct tu_device
*dev
,
1307 gl_shader_stage stage
,
1308 const VkPipelineShaderStageCreateInfo
*stage_info
,
1309 struct tu_pipeline_layout
*layout
,
1310 const VkAllocationCallbacks
*alloc
);
1313 tu_shader_destroy(struct tu_device
*dev
,
1314 struct tu_shader
*shader
,
1315 const VkAllocationCallbacks
*alloc
);
1318 tu_shader_compile_options_init(
1319 struct tu_shader_compile_options
*options
,
1320 const VkGraphicsPipelineCreateInfo
*pipeline_info
);
1323 tu_shader_compile(struct tu_device
*dev
,
1324 struct tu_shader
*shader
,
1325 const struct tu_shader
*next_stage
,
1326 const struct tu_shader_compile_options
*options
,
1327 const VkAllocationCallbacks
*alloc
);
1329 struct tu_program_descriptor_linkage
1331 struct ir3_ubo_analysis_state ubo_state
;
1332 struct ir3_const_state const_state
;
1336 struct tu_push_constant_range push_consts
;
1343 struct tu_dynamic_state dynamic_state
;
1345 struct tu_pipeline_layout
*layout
;
1347 bool need_indirect_descriptor_sets
;
1348 VkShaderStageFlags active_stages
;
1349 uint32_t active_desc_sets
;
1351 struct tu_streamout_state streamout
;
1355 struct tu_bo binary_bo
;
1356 struct tu_cs_entry state_ib
;
1357 struct tu_cs_entry binning_state_ib
;
1359 struct tu_program_descriptor_linkage link
[MESA_SHADER_STAGES
];
1360 unsigned input_attachment_idx
[MAX_RTS
];
1365 struct tu_cs_entry state_ib
;
1370 struct tu_cs_entry state_ib
;
1371 struct tu_cs_entry binning_state_ib
;
1372 uint32_t bindings_used
;
1377 enum pc_di_primtype primtype
;
1378 bool primitive_restart
;
1383 struct tu_cs_entry state_ib
;
1388 uint32_t gras_su_cntl
;
1389 struct tu_cs_entry state_ib
;
1394 struct tu_cs_entry state_ib
;
1399 struct tu_cs_entry state_ib
;
1404 uint32_t local_size
[3];
1409 tu6_emit_viewport(struct tu_cs
*cs
, const VkViewport
*viewport
);
1412 tu6_emit_scissor(struct tu_cs
*cs
, const VkRect2D
*scissor
);
1415 tu6_emit_sample_locations(struct tu_cs
*cs
, const VkSampleLocationsInfoEXT
*samp_loc
);
1418 tu6_emit_gras_su_cntl(struct tu_cs
*cs
,
1419 uint32_t gras_su_cntl
,
1423 tu6_emit_depth_bias(struct tu_cs
*cs
,
1424 float constant_factor
,
1426 float slope_factor
);
1429 tu6_emit_stencil_compare_mask(struct tu_cs
*cs
,
1434 tu6_emit_stencil_write_mask(struct tu_cs
*cs
, uint32_t front
, uint32_t back
);
1437 tu6_emit_stencil_reference(struct tu_cs
*cs
, uint32_t front
, uint32_t back
);
1440 tu6_emit_blend_constants(struct tu_cs
*cs
, const float constants
[4]);
1442 void tu6_emit_msaa(struct tu_cs
*cs
, VkSampleCountFlagBits samples
);
1444 void tu6_emit_window_scissor(struct tu_cs
*cs
, uint32_t x1
, uint32_t y1
, uint32_t x2
, uint32_t y2
);
1446 void tu6_emit_window_offset(struct tu_cs
*cs
, uint32_t x1
, uint32_t y1
);
1449 tu6_emit_xs_config(struct tu_cs
*cs
,
1450 gl_shader_stage stage
,
1451 const struct ir3_shader_variant
*xs
,
1452 uint64_t binary_iova
);
1455 tu6_emit_vpc(struct tu_cs
*cs
,
1456 const struct ir3_shader_variant
*vs
,
1457 const struct ir3_shader_variant
*gs
,
1458 const struct ir3_shader_variant
*fs
,
1459 struct tu_streamout_state
*tf
);
1462 tu6_emit_fs_inputs(struct tu_cs
*cs
, const struct ir3_shader_variant
*fs
);
1464 struct tu_image_view
;
1467 tu_resolve_sysmem(struct tu_cmd_buffer
*cmd
,
1469 struct tu_image_view
*src
,
1470 struct tu_image_view
*dst
,
1472 const VkRect2D
*rect
);
1475 tu_clear_sysmem_attachment(struct tu_cmd_buffer
*cmd
,
1478 const VkRenderPassBeginInfo
*info
);
1481 tu_clear_gmem_attachment(struct tu_cmd_buffer
*cmd
,
1484 const VkRenderPassBeginInfo
*info
);
1487 tu_load_gmem_attachment(struct tu_cmd_buffer
*cmd
,
1492 /* expose this function to be able to emit load without checking LOAD_OP */
1494 tu_emit_load_gmem_attachment(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
, uint32_t a
);
1496 /* note: gmem store can also resolve */
1498 tu_store_gmem_attachment(struct tu_cmd_buffer
*cmd
,
1503 struct tu_userdata_info
*
1504 tu_lookup_user_sgpr(struct tu_pipeline
*pipeline
,
1505 gl_shader_stage stage
,
1508 struct tu_shader_variant
*
1509 tu_get_shader(struct tu_pipeline
*pipeline
, gl_shader_stage stage
);
1511 struct tu_graphics_pipeline_create_info
1514 bool db_depth_clear
;
1515 bool db_stencil_clear
;
1516 bool db_depth_disable_expclear
;
1517 bool db_stencil_disable_expclear
;
1518 bool db_flush_depth_inplace
;
1519 bool db_flush_stencil_inplace
;
1520 bool db_resummarize
;
1521 uint32_t custom_blend_mode
;
1524 enum tu_supported_formats
{
1530 struct tu_native_format
1532 enum a6xx_format fmt
: 8;
1533 enum a3xx_color_swap swap
: 8;
1534 enum a6xx_tile_mode tile_mode
: 8;
1535 enum tu_supported_formats supported
: 8;
1538 struct tu_native_format
tu6_format_vtx(VkFormat format
);
1539 struct tu_native_format
tu6_format_color(VkFormat format
, enum a6xx_tile_mode tile_mode
);
1540 struct tu_native_format
tu6_format_texture(VkFormat format
, enum a6xx_tile_mode tile_mode
);
1542 static inline enum a6xx_format
1543 tu6_base_format(VkFormat format
)
1545 /* note: tu6_format_color doesn't care about tiling for .fmt field */
1546 return tu6_format_color(format
, TILE6_LINEAR
).fmt
;
1549 enum a6xx_depth_format
tu6_pipe2depth(VkFormat format
);
1554 /* The original VkFormat provided by the client. This may not match any
1555 * of the actual surface formats.
1558 VkImageAspectFlags aspects
;
1559 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1560 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1561 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1563 uint32_t level_count
;
1564 uint32_t layer_count
;
1565 VkSampleCountFlagBits samples
;
1567 struct fdl_layout layout
;
1569 unsigned queue_family_mask
;
1573 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1574 VkDeviceMemory owned_memory
;
1576 /* Set when bound */
1578 VkDeviceSize bo_offset
;
1582 tu_image_queue_family_mask(const struct tu_image
*image
,
1584 uint32_t queue_family
);
1586 static inline uint32_t
1587 tu_get_layerCount(const struct tu_image
*image
,
1588 const VkImageSubresourceRange
*range
)
1590 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
1591 ? image
->layer_count
- range
->baseArrayLayer
1592 : range
->layerCount
;
1595 static inline uint32_t
1596 tu_get_levelCount(const struct tu_image
*image
,
1597 const VkImageSubresourceRange
*range
)
1599 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
1600 ? image
->level_count
- range
->baseMipLevel
1601 : range
->levelCount
;
1604 enum a3xx_msaa_samples
1605 tu_msaa_samples(uint32_t samples
);
1606 enum a6xx_tex_fetchsize
1607 tu6_fetchsize(VkFormat format
);
1609 struct tu_image_view
1611 struct tu_image
*image
; /**< VkImageViewCreateInfo::image */
1615 uint32_t layer_size
;
1616 uint32_t ubwc_layer_size
;
1618 /* used to determine if fast gmem store path can be used */
1624 uint32_t descriptor
[A6XX_TEX_CONST_DWORDS
];
1626 /* Descriptor for use as a storage image as opposed to a sampled image.
1627 * This has a few differences for cube maps (e.g. type).
1629 uint32_t storage_descriptor
[A6XX_TEX_CONST_DWORDS
];
1631 /* pre-filled register values */
1633 uint32_t FLAG_BUFFER_PITCH
;
1635 uint32_t RB_MRT_BUF_INFO
;
1636 uint32_t SP_FS_MRT_REG
;
1638 uint32_t SP_PS_2D_SRC_INFO
;
1639 uint32_t SP_PS_2D_SRC_SIZE
;
1641 uint32_t RB_2D_DST_INFO
;
1643 uint32_t RB_BLIT_DST_INFO
;
1646 struct tu_sampler_ycbcr_conversion
{
1648 VkSamplerYcbcrModelConversion ycbcr_model
;
1649 VkSamplerYcbcrRange ycbcr_range
;
1650 VkComponentMapping components
;
1651 VkChromaLocation chroma_offsets
[2];
1652 VkFilter chroma_filter
;
1656 uint32_t descriptor
[A6XX_TEX_SAMP_DWORDS
];
1657 struct tu_sampler_ycbcr_conversion
*ycbcr_sampler
;
1661 tu_cs_image_ref(struct tu_cs
*cs
, const struct tu_image_view
*iview
, uint32_t layer
);
1664 tu_cs_image_ref_2d(struct tu_cs
*cs
, const struct tu_image_view
*iview
, uint32_t layer
, bool src
);
1667 tu_cs_image_flag_ref(struct tu_cs
*cs
, const struct tu_image_view
*iview
, uint32_t layer
);
1670 tu_image_create(VkDevice _device
,
1671 const VkImageCreateInfo
*pCreateInfo
,
1672 const VkAllocationCallbacks
*alloc
,
1675 const VkSubresourceLayout
*plane_layouts
);
1678 tu_image_from_gralloc(VkDevice device_h
,
1679 const VkImageCreateInfo
*base_info
,
1680 const VkNativeBufferANDROID
*gralloc_info
,
1681 const VkAllocationCallbacks
*alloc
,
1682 VkImage
*out_image_h
);
1685 tu_image_view_init(struct tu_image_view
*view
,
1686 const VkImageViewCreateInfo
*pCreateInfo
);
1688 struct tu_buffer_view
1690 uint32_t descriptor
[A6XX_TEX_CONST_DWORDS
];
1692 struct tu_buffer
*buffer
;
1695 tu_buffer_view_init(struct tu_buffer_view
*view
,
1696 struct tu_device
*device
,
1697 const VkBufferViewCreateInfo
*pCreateInfo
);
1699 static inline struct VkExtent3D
1700 tu_sanitize_image_extent(const VkImageType imageType
,
1701 const struct VkExtent3D imageExtent
)
1703 switch (imageType
) {
1704 case VK_IMAGE_TYPE_1D
:
1705 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
1706 case VK_IMAGE_TYPE_2D
:
1707 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
1708 case VK_IMAGE_TYPE_3D
:
1711 unreachable("invalid image type");
1715 static inline struct VkOffset3D
1716 tu_sanitize_image_offset(const VkImageType imageType
,
1717 const struct VkOffset3D imageOffset
)
1719 switch (imageType
) {
1720 case VK_IMAGE_TYPE_1D
:
1721 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
1722 case VK_IMAGE_TYPE_2D
:
1723 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
1724 case VK_IMAGE_TYPE_3D
:
1727 unreachable("invalid image type");
1731 struct tu_attachment_info
1733 struct tu_image_view
*attachment
;
1736 struct tu_framebuffer
1742 uint32_t attachment_count
;
1743 struct tu_attachment_info attachments
[0];
1746 struct tu_subpass_barrier
{
1747 VkPipelineStageFlags src_stage_mask
;
1748 VkAccessFlags src_access_mask
;
1749 VkAccessFlags dst_access_mask
;
1750 bool incoherent_ccu_color
, incoherent_ccu_depth
;
1753 struct tu_subpass_attachment
1755 uint32_t attachment
;
1756 VkImageLayout layout
;
1761 uint32_t input_count
;
1762 uint32_t color_count
;
1763 struct tu_subpass_attachment
*input_attachments
;
1764 struct tu_subpass_attachment
*color_attachments
;
1765 struct tu_subpass_attachment
*resolve_attachments
;
1766 struct tu_subpass_attachment depth_stencil_attachment
;
1768 VkSampleCountFlagBits samples
;
1769 bool has_external_src
, has_external_dst
;
1773 struct tu_subpass_barrier start_barrier
;
1776 struct tu_render_pass_attachment
1781 VkImageAspectFlags clear_mask
;
1784 VkImageLayout initial_layout
, final_layout
;
1785 int32_t gmem_offset
;
1788 struct tu_render_pass
1790 uint32_t attachment_count
;
1791 uint32_t subpass_count
;
1792 uint32_t gmem_pixels
;
1793 uint32_t tile_align_w
;
1794 struct tu_subpass_attachment
*subpass_attachments
;
1795 struct tu_render_pass_attachment
*attachments
;
1796 struct tu_subpass_barrier end_barrier
;
1797 struct tu_subpass subpasses
[0];
1801 tu_device_init_meta(struct tu_device
*device
);
1803 tu_device_finish_meta(struct tu_device
*device
);
1805 struct tu_query_pool
1810 uint32_t pipeline_statistics
;
1817 uint32_t temp_syncobj
;
1821 tu_set_descriptor_set(struct tu_cmd_buffer
*cmd_buffer
,
1822 VkPipelineBindPoint bind_point
,
1823 struct tu_descriptor_set
*set
,
1827 tu_update_descriptor_sets(struct tu_device
*device
,
1828 struct tu_cmd_buffer
*cmd_buffer
,
1829 VkDescriptorSet overrideSet
,
1830 uint32_t descriptorWriteCount
,
1831 const VkWriteDescriptorSet
*pDescriptorWrites
,
1832 uint32_t descriptorCopyCount
,
1833 const VkCopyDescriptorSet
*pDescriptorCopies
);
1836 tu_update_descriptor_set_with_template(
1837 struct tu_device
*device
,
1838 struct tu_cmd_buffer
*cmd_buffer
,
1839 struct tu_descriptor_set
*set
,
1840 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
1844 tu_meta_push_descriptor_set(struct tu_cmd_buffer
*cmd_buffer
,
1845 VkPipelineBindPoint pipelineBindPoint
,
1846 VkPipelineLayout _layout
,
1848 uint32_t descriptorWriteCount
,
1849 const VkWriteDescriptorSet
*pDescriptorWrites
);
1852 tu_drm_get_gpu_id(const struct tu_physical_device
*dev
, uint32_t *id
);
1855 tu_drm_get_gmem_size(const struct tu_physical_device
*dev
, uint32_t *size
);
1858 tu_drm_get_gmem_base(const struct tu_physical_device
*dev
, uint64_t *base
);
1861 tu_drm_submitqueue_new(const struct tu_device
*dev
,
1863 uint32_t *queue_id
);
1866 tu_drm_submitqueue_close(const struct tu_device
*dev
, uint32_t queue_id
);
1869 tu_gem_new(const struct tu_device
*dev
, uint64_t size
, uint32_t flags
);
1871 tu_gem_import_dmabuf(const struct tu_device
*dev
,
1875 tu_gem_export_dmabuf(const struct tu_device
*dev
, uint32_t gem_handle
);
1877 tu_gem_close(const struct tu_device
*dev
, uint32_t gem_handle
);
1879 tu_gem_info_offset(const struct tu_device
*dev
, uint32_t gem_handle
);
1881 tu_gem_info_iova(const struct tu_device
*dev
, uint32_t gem_handle
);
1883 #define TU_DEFINE_HANDLE_CASTS(__tu_type, __VkType) \
1885 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1887 return (struct __tu_type *) _handle; \
1890 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1892 return (__VkType) _obj; \
1895 #define TU_DEFINE_NONDISP_HANDLE_CASTS(__tu_type, __VkType) \
1897 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1899 return (struct __tu_type *) (uintptr_t) _handle; \
1902 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1904 return (__VkType)(uintptr_t) _obj; \
1907 #define TU_FROM_HANDLE(__tu_type, __name, __handle) \
1908 struct __tu_type *__name = __tu_type##_from_handle(__handle)
1910 TU_DEFINE_HANDLE_CASTS(tu_cmd_buffer
, VkCommandBuffer
)
1911 TU_DEFINE_HANDLE_CASTS(tu_device
, VkDevice
)
1912 TU_DEFINE_HANDLE_CASTS(tu_instance
, VkInstance
)
1913 TU_DEFINE_HANDLE_CASTS(tu_physical_device
, VkPhysicalDevice
)
1914 TU_DEFINE_HANDLE_CASTS(tu_queue
, VkQueue
)
1916 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_cmd_pool
, VkCommandPool
)
1917 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer
, VkBuffer
)
1918 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer_view
, VkBufferView
)
1919 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_pool
, VkDescriptorPool
)
1920 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set
, VkDescriptorSet
)
1921 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set_layout
,
1922 VkDescriptorSetLayout
)
1923 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_update_template
,
1924 VkDescriptorUpdateTemplate
)
1925 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_device_memory
, VkDeviceMemory
)
1926 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_fence
, VkFence
)
1927 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_event
, VkEvent
)
1928 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_framebuffer
, VkFramebuffer
)
1929 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image
, VkImage
)
1930 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image_view
, VkImageView
);
1931 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_cache
, VkPipelineCache
)
1932 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline
, VkPipeline
)
1933 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_layout
, VkPipelineLayout
)
1934 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_query_pool
, VkQueryPool
)
1935 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_render_pass
, VkRenderPass
)
1936 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_sampler
, VkSampler
)
1937 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_sampler_ycbcr_conversion
, VkSamplerYcbcrConversion
)
1938 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_shader_module
, VkShaderModule
)
1939 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_semaphore
, VkSemaphore
)
1941 #endif /* TU_PRIVATE_H */