turnip: move tile_load_ib/sysmem_clear_ib into draw_cs
[mesa.git] / src / freedreno / vulkan / tu_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #ifndef TU_PRIVATE_H
29 #define TU_PRIVATE_H
30
31 #include <assert.h>
32 #include <pthread.h>
33 #include <stdbool.h>
34 #include <stdint.h>
35 #include <stdio.h>
36 #include <stdlib.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <memcheck.h>
40 #include <valgrind.h>
41 #define VG(x) x
42 #else
43 #define VG(x) ((void)0)
44 #endif
45
46 #include "c11/threads.h"
47 #include "main/macros.h"
48 #include "util/list.h"
49 #include "util/macros.h"
50 #include "vk_alloc.h"
51 #include "vk_debug_report.h"
52 #include "wsi_common.h"
53
54 #include "drm-uapi/msm_drm.h"
55 #include "ir3/ir3_compiler.h"
56 #include "ir3/ir3_shader.h"
57
58 #include "adreno_common.xml.h"
59 #include "adreno_pm4.xml.h"
60 #include "a6xx.xml.h"
61 #include "fdl/freedreno_layout.h"
62
63 #include "tu_descriptor_set.h"
64 #include "tu_extensions.h"
65
66 /* Pre-declarations needed for WSI entrypoints */
67 struct wl_surface;
68 struct wl_display;
69 typedef struct xcb_connection_t xcb_connection_t;
70 typedef uint32_t xcb_visualid_t;
71 typedef uint32_t xcb_window_t;
72
73 #include <vulkan/vk_android_native_buffer.h>
74 #include <vulkan/vk_icd.h>
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77
78 #include "tu_entrypoints.h"
79
80 #define MAX_VBS 32
81 #define MAX_VERTEX_ATTRIBS 32
82 #define MAX_RTS 8
83 #define MAX_VSC_PIPES 32
84 #define MAX_VIEWPORTS 1
85 #define MAX_SCISSORS 16
86 #define MAX_DISCARD_RECTANGLES 4
87 #define MAX_PUSH_CONSTANTS_SIZE 128
88 #define MAX_PUSH_DESCRIPTORS 32
89 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
90 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
91 #define MAX_DYNAMIC_BUFFERS \
92 (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
93 #define MAX_SAMPLES_LOG2 4
94 #define NUM_META_FS_KEYS 13
95 #define TU_MAX_DRM_DEVICES 8
96 #define MAX_VIEWS 8
97 /* The Qualcomm driver exposes 0x20000058 */
98 #define MAX_STORAGE_BUFFER_RANGE 0x20000000
99
100 #define NUM_DEPTH_CLEAR_PIPELINES 3
101
102 /*
103 * This is the point we switch from using CP to compute shader
104 * for certain buffer operations.
105 */
106 #define TU_BUFFER_OPS_CS_THRESHOLD 4096
107
108 #define A6XX_TEX_CONST_DWORDS 16
109 #define A6XX_TEX_SAMP_DWORDS 4
110
111 enum tu_mem_heap
112 {
113 TU_MEM_HEAP_VRAM,
114 TU_MEM_HEAP_VRAM_CPU_ACCESS,
115 TU_MEM_HEAP_GTT,
116 TU_MEM_HEAP_COUNT
117 };
118
119 enum tu_mem_type
120 {
121 TU_MEM_TYPE_VRAM,
122 TU_MEM_TYPE_GTT_WRITE_COMBINE,
123 TU_MEM_TYPE_VRAM_CPU_ACCESS,
124 TU_MEM_TYPE_GTT_CACHED,
125 TU_MEM_TYPE_COUNT
126 };
127
128 #define tu_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
129
130 static inline uint32_t
131 align_u32(uint32_t v, uint32_t a)
132 {
133 assert(a != 0 && a == (a & -a));
134 return (v + a - 1) & ~(a - 1);
135 }
136
137 static inline uint32_t
138 align_u32_npot(uint32_t v, uint32_t a)
139 {
140 return (v + a - 1) / a * a;
141 }
142
143 static inline uint64_t
144 align_u64(uint64_t v, uint64_t a)
145 {
146 assert(a != 0 && a == (a & -a));
147 return (v + a - 1) & ~(a - 1);
148 }
149
150 static inline int32_t
151 align_i32(int32_t v, int32_t a)
152 {
153 assert(a != 0 && a == (a & -a));
154 return (v + a - 1) & ~(a - 1);
155 }
156
157 /** Alignment must be a power of 2. */
158 static inline bool
159 tu_is_aligned(uintmax_t n, uintmax_t a)
160 {
161 assert(a == (a & -a));
162 return (n & (a - 1)) == 0;
163 }
164
165 static inline uint32_t
166 round_up_u32(uint32_t v, uint32_t a)
167 {
168 return (v + a - 1) / a;
169 }
170
171 static inline uint64_t
172 round_up_u64(uint64_t v, uint64_t a)
173 {
174 return (v + a - 1) / a;
175 }
176
177 static inline uint32_t
178 tu_minify(uint32_t n, uint32_t levels)
179 {
180 if (unlikely(n == 0))
181 return 0;
182 else
183 return MAX2(n >> levels, 1);
184 }
185 static inline float
186 tu_clamp_f(float f, float min, float max)
187 {
188 assert(min < max);
189
190 if (f > max)
191 return max;
192 else if (f < min)
193 return min;
194 else
195 return f;
196 }
197
198 static inline bool
199 tu_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
200 {
201 if (*inout_mask & clear_mask) {
202 *inout_mask &= ~clear_mask;
203 return true;
204 } else {
205 return false;
206 }
207 }
208
209 #define for_each_bit(b, dword) \
210 for (uint32_t __dword = (dword); \
211 (b) = __builtin_ffs(__dword) - 1, __dword; __dword &= ~(1 << (b)))
212
213 #define typed_memcpy(dest, src, count) \
214 ({ \
215 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
216 memcpy((dest), (src), (count) * sizeof(*(src))); \
217 })
218
219 #define COND(bool, val) ((bool) ? (val) : 0)
220
221 /* Whenever we generate an error, pass it through this function. Useful for
222 * debugging, where we can break on it. Only call at error site, not when
223 * propagating errors. Might be useful to plug in a stack trace here.
224 */
225
226 struct tu_instance;
227
228 VkResult
229 __vk_errorf(struct tu_instance *instance,
230 VkResult error,
231 const char *file,
232 int line,
233 const char *format,
234 ...);
235
236 #define vk_error(instance, error) \
237 __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
238 #define vk_errorf(instance, error, format, ...) \
239 __vk_errorf(instance, error, __FILE__, __LINE__, format, ##__VA_ARGS__);
240
241 void
242 __tu_finishme(const char *file, int line, const char *format, ...)
243 tu_printflike(3, 4);
244 void
245 tu_loge(const char *format, ...) tu_printflike(1, 2);
246 void
247 tu_loge_v(const char *format, va_list va);
248 void
249 tu_logi(const char *format, ...) tu_printflike(1, 2);
250 void
251 tu_logi_v(const char *format, va_list va);
252
253 /**
254 * Print a FINISHME message, including its source location.
255 */
256 #define tu_finishme(format, ...) \
257 do { \
258 static bool reported = false; \
259 if (!reported) { \
260 __tu_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
261 reported = true; \
262 } \
263 } while (0)
264
265 /* A non-fatal assert. Useful for debugging. */
266 #ifdef DEBUG
267 #define tu_assert(x) \
268 ({ \
269 if (unlikely(!(x))) \
270 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
271 })
272 #else
273 #define tu_assert(x)
274 #endif
275
276 /* Suppress -Wunused in stub functions */
277 #define tu_use_args(...) __tu_use_args(0, ##__VA_ARGS__)
278 static inline void
279 __tu_use_args(int ignore, ...)
280 {
281 }
282
283 #define tu_stub() \
284 do { \
285 tu_finishme("stub %s", __func__); \
286 } while (0)
287
288 void *
289 tu_lookup_entrypoint_unchecked(const char *name);
290 void *
291 tu_lookup_entrypoint_checked(
292 const char *name,
293 uint32_t core_version,
294 const struct tu_instance_extension_table *instance,
295 const struct tu_device_extension_table *device);
296
297 struct tu_physical_device
298 {
299 VK_LOADER_DATA _loader_data;
300
301 struct tu_instance *instance;
302
303 char path[20];
304 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
305 uint8_t driver_uuid[VK_UUID_SIZE];
306 uint8_t device_uuid[VK_UUID_SIZE];
307 uint8_t cache_uuid[VK_UUID_SIZE];
308
309 struct wsi_device wsi_device;
310
311 int local_fd;
312 int master_fd;
313
314 unsigned gpu_id;
315 uint32_t gmem_size;
316 uint32_t tile_align_w;
317 uint32_t tile_align_h;
318
319 struct {
320 uint32_t RB_UNKNOWN_8E04_blit; /* for CP_BLIT's */
321 uint32_t RB_CCU_CNTL_gmem; /* for GMEM */
322 uint32_t PC_UNKNOWN_9805;
323 uint32_t SP_UNKNOWN_A0F8;
324 } magic;
325
326 /* This is the drivers on-disk cache used as a fallback as opposed to
327 * the pipeline cache defined by apps.
328 */
329 struct disk_cache *disk_cache;
330
331 struct tu_device_extension_table supported_extensions;
332 };
333
334 enum tu_debug_flags
335 {
336 TU_DEBUG_STARTUP = 1 << 0,
337 TU_DEBUG_NIR = 1 << 1,
338 TU_DEBUG_IR3 = 1 << 2,
339 TU_DEBUG_NOBIN = 1 << 3,
340 TU_DEBUG_SYSMEM = 1 << 4,
341 TU_DEBUG_FORCEBIN = 1 << 5,
342 };
343
344 struct tu_instance
345 {
346 VK_LOADER_DATA _loader_data;
347
348 VkAllocationCallbacks alloc;
349
350 uint32_t api_version;
351 int physical_device_count;
352 struct tu_physical_device physical_devices[TU_MAX_DRM_DEVICES];
353
354 enum tu_debug_flags debug_flags;
355
356 struct vk_debug_report_instance debug_report_callbacks;
357
358 struct tu_instance_extension_table enabled_extensions;
359 };
360
361 VkResult
362 tu_wsi_init(struct tu_physical_device *physical_device);
363 void
364 tu_wsi_finish(struct tu_physical_device *physical_device);
365
366 bool
367 tu_instance_extension_supported(const char *name);
368 uint32_t
369 tu_physical_device_api_version(struct tu_physical_device *dev);
370 bool
371 tu_physical_device_extension_supported(struct tu_physical_device *dev,
372 const char *name);
373
374 struct cache_entry;
375
376 struct tu_pipeline_cache
377 {
378 struct tu_device *device;
379 pthread_mutex_t mutex;
380
381 uint32_t total_size;
382 uint32_t table_size;
383 uint32_t kernel_count;
384 struct cache_entry **hash_table;
385 bool modified;
386
387 VkAllocationCallbacks alloc;
388 };
389
390 struct tu_pipeline_key
391 {
392 };
393
394 void
395 tu_pipeline_cache_init(struct tu_pipeline_cache *cache,
396 struct tu_device *device);
397 void
398 tu_pipeline_cache_finish(struct tu_pipeline_cache *cache);
399 void
400 tu_pipeline_cache_load(struct tu_pipeline_cache *cache,
401 const void *data,
402 size_t size);
403
404 struct tu_shader_variant;
405
406 bool
407 tu_create_shader_variants_from_pipeline_cache(
408 struct tu_device *device,
409 struct tu_pipeline_cache *cache,
410 const unsigned char *sha1,
411 struct tu_shader_variant **variants);
412
413 void
414 tu_pipeline_cache_insert_shaders(struct tu_device *device,
415 struct tu_pipeline_cache *cache,
416 const unsigned char *sha1,
417 struct tu_shader_variant **variants,
418 const void *const *codes,
419 const unsigned *code_sizes);
420
421 struct tu_meta_state
422 {
423 VkAllocationCallbacks alloc;
424
425 struct tu_pipeline_cache cache;
426 };
427
428 /* queue types */
429 #define TU_QUEUE_GENERAL 0
430
431 #define TU_MAX_QUEUE_FAMILIES 1
432
433 struct tu_fence
434 {
435 struct wsi_fence *fence_wsi;
436 bool signaled;
437 int fd;
438 };
439
440 void
441 tu_fence_init(struct tu_fence *fence, bool signaled);
442 void
443 tu_fence_finish(struct tu_fence *fence);
444 void
445 tu_fence_update_fd(struct tu_fence *fence, int fd);
446 void
447 tu_fence_copy(struct tu_fence *fence, const struct tu_fence *src);
448 void
449 tu_fence_signal(struct tu_fence *fence);
450 void
451 tu_fence_wait_idle(struct tu_fence *fence);
452
453 struct tu_queue
454 {
455 VK_LOADER_DATA _loader_data;
456 struct tu_device *device;
457 uint32_t queue_family_index;
458 int queue_idx;
459 VkDeviceQueueCreateFlags flags;
460
461 uint32_t msm_queue_id;
462 struct tu_fence submit_fence;
463 };
464
465 struct tu_bo
466 {
467 uint32_t gem_handle;
468 uint64_t size;
469 uint64_t iova;
470 void *map;
471 };
472
473 struct tu_device
474 {
475 VK_LOADER_DATA _loader_data;
476
477 VkAllocationCallbacks alloc;
478
479 struct tu_instance *instance;
480
481 struct tu_meta_state meta_state;
482
483 struct tu_queue *queues[TU_MAX_QUEUE_FAMILIES];
484 int queue_count[TU_MAX_QUEUE_FAMILIES];
485
486 struct tu_physical_device *physical_device;
487
488 struct ir3_compiler *compiler;
489
490 /* Backup in-memory cache to be used if the app doesn't provide one */
491 struct tu_pipeline_cache *mem_cache;
492
493 struct tu_bo vsc_data;
494 struct tu_bo vsc_data2;
495 uint32_t vsc_data_pitch;
496 uint32_t vsc_data2_pitch;
497
498 struct list_head shader_slabs;
499 mtx_t shader_slab_mutex;
500
501 struct tu_device_extension_table enabled_extensions;
502 };
503
504 VkResult
505 tu_bo_init_new(struct tu_device *dev, struct tu_bo *bo, uint64_t size);
506 VkResult
507 tu_bo_init_dmabuf(struct tu_device *dev,
508 struct tu_bo *bo,
509 uint64_t size,
510 int fd);
511 int
512 tu_bo_export_dmabuf(struct tu_device *dev, struct tu_bo *bo);
513 void
514 tu_bo_finish(struct tu_device *dev, struct tu_bo *bo);
515 VkResult
516 tu_bo_map(struct tu_device *dev, struct tu_bo *bo);
517
518 struct tu_cs_entry
519 {
520 /* No ownership */
521 const struct tu_bo *bo;
522
523 uint32_t size;
524 uint32_t offset;
525 };
526
527 struct ts_cs_memory {
528 uint32_t *map;
529 uint64_t iova;
530 };
531
532 enum tu_cs_mode
533 {
534
535 /*
536 * A command stream in TU_CS_MODE_GROW mode grows automatically whenever it
537 * is full. tu_cs_begin must be called before command packet emission and
538 * tu_cs_end must be called after.
539 *
540 * This mode may create multiple entries internally. The entries must be
541 * submitted together.
542 */
543 TU_CS_MODE_GROW,
544
545 /*
546 * A command stream in TU_CS_MODE_EXTERNAL mode wraps an external,
547 * fixed-size buffer. tu_cs_begin and tu_cs_end are optional and have no
548 * effect on it.
549 *
550 * This mode does not create any entry or any BO.
551 */
552 TU_CS_MODE_EXTERNAL,
553
554 /*
555 * A command stream in TU_CS_MODE_SUB_STREAM mode does not support direct
556 * command packet emission. tu_cs_begin_sub_stream must be called to get a
557 * sub-stream to emit comamnd packets to. When done with the sub-stream,
558 * tu_cs_end_sub_stream must be called.
559 *
560 * This mode does not create any entry internally.
561 */
562 TU_CS_MODE_SUB_STREAM,
563 };
564
565 struct tu_cs
566 {
567 uint32_t *start;
568 uint32_t *cur;
569 uint32_t *reserved_end;
570 uint32_t *end;
571
572 struct tu_device *device;
573 enum tu_cs_mode mode;
574 uint32_t next_bo_size;
575
576 struct tu_cs_entry *entries;
577 uint32_t entry_count;
578 uint32_t entry_capacity;
579
580 struct tu_bo **bos;
581 uint32_t bo_count;
582 uint32_t bo_capacity;
583
584 /* state for cond_exec_start/cond_exec_end */
585 uint32_t cond_flags;
586 uint32_t *cond_dwords;
587 };
588
589 struct tu_device_memory
590 {
591 struct tu_bo bo;
592 VkDeviceSize size;
593
594 /* for dedicated allocations */
595 struct tu_image *image;
596 struct tu_buffer *buffer;
597
598 uint32_t type_index;
599 void *map;
600 void *user_ptr;
601 };
602
603 struct tu_descriptor_range
604 {
605 uint64_t va;
606 uint32_t size;
607 };
608
609 struct tu_descriptor_set
610 {
611 const struct tu_descriptor_set_layout *layout;
612 uint32_t size;
613
614 uint64_t va;
615 uint32_t *mapped_ptr;
616 struct tu_descriptor_range *dynamic_descriptors;
617
618 struct tu_bo *descriptors[0];
619 };
620
621 struct tu_push_descriptor_set
622 {
623 struct tu_descriptor_set set;
624 uint32_t capacity;
625 };
626
627 struct tu_descriptor_pool_entry
628 {
629 uint32_t offset;
630 uint32_t size;
631 struct tu_descriptor_set *set;
632 };
633
634 struct tu_descriptor_pool
635 {
636 struct tu_bo bo;
637 uint64_t current_offset;
638 uint64_t size;
639
640 uint8_t *host_memory_base;
641 uint8_t *host_memory_ptr;
642 uint8_t *host_memory_end;
643
644 uint32_t entry_count;
645 uint32_t max_entry_count;
646 struct tu_descriptor_pool_entry entries[0];
647 };
648
649 struct tu_descriptor_update_template_entry
650 {
651 VkDescriptorType descriptor_type;
652
653 /* The number of descriptors to update */
654 uint32_t descriptor_count;
655
656 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array
657 */
658 uint32_t dst_offset;
659
660 /* In dwords. Not valid/used for dynamic descriptors */
661 uint32_t dst_stride;
662
663 uint32_t buffer_offset;
664
665 /* Only valid for combined image samplers and samplers */
666 uint16_t has_sampler;
667
668 /* In bytes */
669 size_t src_offset;
670 size_t src_stride;
671
672 /* For push descriptors */
673 const uint32_t *immutable_samplers;
674 };
675
676 struct tu_descriptor_update_template
677 {
678 uint32_t entry_count;
679 VkPipelineBindPoint bind_point;
680 struct tu_descriptor_update_template_entry entry[0];
681 };
682
683 struct tu_buffer
684 {
685 VkDeviceSize size;
686
687 VkBufferUsageFlags usage;
688 VkBufferCreateFlags flags;
689
690 struct tu_bo *bo;
691 VkDeviceSize bo_offset;
692 };
693
694 static inline uint64_t
695 tu_buffer_iova(struct tu_buffer *buffer)
696 {
697 return buffer->bo->iova + buffer->bo_offset;
698 }
699
700 enum tu_dynamic_state_bits
701 {
702 TU_DYNAMIC_VIEWPORT = 1 << 0,
703 TU_DYNAMIC_SCISSOR = 1 << 1,
704 TU_DYNAMIC_LINE_WIDTH = 1 << 2,
705 TU_DYNAMIC_DEPTH_BIAS = 1 << 3,
706 TU_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
707 TU_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
708 TU_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
709 TU_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
710 TU_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
711 TU_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
712 TU_DYNAMIC_ALL = (1 << 10) - 1,
713 };
714
715 struct tu_vertex_binding
716 {
717 struct tu_buffer *buffer;
718 VkDeviceSize offset;
719 };
720
721 struct tu_viewport_state
722 {
723 uint32_t count;
724 VkViewport viewports[MAX_VIEWPORTS];
725 };
726
727 struct tu_scissor_state
728 {
729 uint32_t count;
730 VkRect2D scissors[MAX_SCISSORS];
731 };
732
733 struct tu_discard_rectangle_state
734 {
735 uint32_t count;
736 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
737 };
738
739 struct tu_dynamic_state
740 {
741 /**
742 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
743 * Defines the set of saved dynamic state.
744 */
745 uint32_t mask;
746
747 struct tu_viewport_state viewport;
748
749 struct tu_scissor_state scissor;
750
751 float line_width;
752
753 struct
754 {
755 float bias;
756 float clamp;
757 float slope;
758 } depth_bias;
759
760 float blend_constants[4];
761
762 struct
763 {
764 float min;
765 float max;
766 } depth_bounds;
767
768 struct
769 {
770 uint32_t front;
771 uint32_t back;
772 } stencil_compare_mask;
773
774 struct
775 {
776 uint32_t front;
777 uint32_t back;
778 } stencil_write_mask;
779
780 struct
781 {
782 uint32_t front;
783 uint32_t back;
784 } stencil_reference;
785
786 struct tu_discard_rectangle_state discard_rectangle;
787 };
788
789 extern const struct tu_dynamic_state default_dynamic_state;
790
791 const char *
792 tu_get_debug_option_name(int id);
793
794 const char *
795 tu_get_perftest_option_name(int id);
796
797 struct tu_descriptor_state
798 {
799 struct tu_descriptor_set *sets[MAX_SETS];
800 uint32_t valid;
801 struct tu_push_descriptor_set push_set;
802 bool push_dirty;
803 uint64_t dynamic_buffers[MAX_DYNAMIC_BUFFERS];
804 };
805
806 struct tu_tile
807 {
808 uint8_t pipe;
809 uint8_t slot;
810 VkOffset2D begin;
811 VkOffset2D end;
812 };
813
814 struct tu_tiling_config
815 {
816 VkRect2D render_area;
817
818 /* position and size of the first tile */
819 VkRect2D tile0;
820 /* number of tiles */
821 VkExtent2D tile_count;
822
823 /* size of the first VSC pipe */
824 VkExtent2D pipe0;
825 /* number of VSC pipes */
826 VkExtent2D pipe_count;
827
828 /* pipe register values */
829 uint32_t pipe_config[MAX_VSC_PIPES];
830 uint32_t pipe_sizes[MAX_VSC_PIPES];
831
832 /* Whether sysmem rendering must be used */
833 bool force_sysmem;
834 };
835
836 enum tu_cmd_dirty_bits
837 {
838 TU_CMD_DIRTY_PIPELINE = 1 << 0,
839 TU_CMD_DIRTY_COMPUTE_PIPELINE = 1 << 1,
840 TU_CMD_DIRTY_VERTEX_BUFFERS = 1 << 2,
841 TU_CMD_DIRTY_DESCRIPTOR_SETS = 1 << 3,
842 TU_CMD_DIRTY_PUSH_CONSTANTS = 1 << 4,
843
844 TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 16,
845 TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 17,
846 TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 18,
847 TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 19,
848 };
849
850 struct tu_cmd_state
851 {
852 uint32_t dirty;
853
854 struct tu_pipeline *pipeline;
855 struct tu_pipeline *compute_pipeline;
856
857 /* Vertex buffers */
858 struct
859 {
860 struct tu_buffer *buffers[MAX_VBS];
861 VkDeviceSize offsets[MAX_VBS];
862 } vb;
863
864 struct tu_dynamic_state dynamic;
865
866 /* Index buffer */
867 struct tu_buffer *index_buffer;
868 uint64_t index_offset;
869 uint32_t index_type;
870 uint32_t max_index_count;
871 uint64_t index_va;
872
873 const struct tu_render_pass *pass;
874 const struct tu_subpass *subpass;
875 const struct tu_framebuffer *framebuffer;
876
877 struct tu_tiling_config tiling_config;
878
879 struct tu_cs_entry tile_store_ib;
880 };
881
882 struct tu_cmd_pool
883 {
884 VkAllocationCallbacks alloc;
885 struct list_head cmd_buffers;
886 struct list_head free_cmd_buffers;
887 uint32_t queue_family_index;
888 };
889
890 struct tu_cmd_buffer_upload
891 {
892 uint8_t *map;
893 unsigned offset;
894 uint64_t size;
895 struct list_head list;
896 };
897
898 enum tu_cmd_buffer_status
899 {
900 TU_CMD_BUFFER_STATUS_INVALID,
901 TU_CMD_BUFFER_STATUS_INITIAL,
902 TU_CMD_BUFFER_STATUS_RECORDING,
903 TU_CMD_BUFFER_STATUS_EXECUTABLE,
904 TU_CMD_BUFFER_STATUS_PENDING,
905 };
906
907 struct tu_bo_list
908 {
909 uint32_t count;
910 uint32_t capacity;
911 struct drm_msm_gem_submit_bo *bo_infos;
912 };
913
914 #define TU_BO_LIST_FAILED (~0)
915
916 void
917 tu_bo_list_init(struct tu_bo_list *list);
918 void
919 tu_bo_list_destroy(struct tu_bo_list *list);
920 void
921 tu_bo_list_reset(struct tu_bo_list *list);
922 uint32_t
923 tu_bo_list_add(struct tu_bo_list *list,
924 const struct tu_bo *bo,
925 uint32_t flags);
926 VkResult
927 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other);
928
929 struct tu_cmd_buffer
930 {
931 VK_LOADER_DATA _loader_data;
932
933 struct tu_device *device;
934
935 struct tu_cmd_pool *pool;
936 struct list_head pool_link;
937
938 VkCommandBufferUsageFlags usage_flags;
939 VkCommandBufferLevel level;
940 enum tu_cmd_buffer_status status;
941
942 struct tu_cmd_state state;
943 struct tu_vertex_binding vertex_bindings[MAX_VBS];
944 uint32_t queue_family_index;
945
946 uint32_t push_constants[MAX_PUSH_CONSTANTS_SIZE / 4];
947 VkShaderStageFlags push_constant_stages;
948 struct tu_descriptor_set meta_push_descriptors;
949
950 struct tu_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
951
952 struct tu_cmd_buffer_upload upload;
953
954 VkResult record_result;
955
956 struct tu_bo_list bo_list;
957 struct tu_cs cs;
958 struct tu_cs draw_cs;
959 struct tu_cs draw_epilogue_cs;
960 struct tu_cs sub_cs;
961
962 struct tu_bo scratch_bo;
963 uint32_t scratch_seqno;
964 #define VSC_OVERFLOW 0x8
965 #define VSC_SCRATCH 0x10
966
967 struct tu_bo vsc_data;
968 struct tu_bo vsc_data2;
969 uint32_t vsc_data_pitch;
970 uint32_t vsc_data2_pitch;
971 bool use_vsc_data;
972
973 bool wait_for_idle;
974 };
975
976 /* Temporary struct for tracking a register state to be written, used by
977 * a6xx-pack.h and tu_cs_emit_regs()
978 */
979 struct tu_reg_value {
980 uint32_t reg;
981 uint64_t value;
982 bool is_address;
983 struct tu_bo *bo;
984 bool bo_write;
985 uint32_t bo_offset;
986 uint32_t bo_shift;
987 };
988
989 unsigned
990 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
991 struct tu_cs *cs,
992 enum vgt_event_type event,
993 bool need_seqno);
994
995 bool
996 tu_get_memory_fd(struct tu_device *device,
997 struct tu_device_memory *memory,
998 int *pFD);
999
1000 static inline struct tu_descriptor_state *
1001 tu_get_descriptors_state(struct tu_cmd_buffer *cmd_buffer,
1002 VkPipelineBindPoint bind_point)
1003 {
1004 return &cmd_buffer->descriptors[bind_point];
1005 }
1006
1007 /*
1008 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1009 *
1010 * Limitations: Can't call normal dispatch functions without binding or
1011 * rebinding
1012 * the compute pipeline.
1013 */
1014 void
1015 tu_unaligned_dispatch(struct tu_cmd_buffer *cmd_buffer,
1016 uint32_t x,
1017 uint32_t y,
1018 uint32_t z);
1019
1020 struct tu_event
1021 {
1022 struct tu_bo bo;
1023 };
1024
1025 struct tu_shader_module;
1026
1027 #define TU_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1028 #define TU_HASH_SHADER_SISCHED (1 << 1)
1029 #define TU_HASH_SHADER_UNSAFE_MATH (1 << 2)
1030 void
1031 tu_hash_shaders(unsigned char *hash,
1032 const VkPipelineShaderStageCreateInfo **stages,
1033 const struct tu_pipeline_layout *layout,
1034 const struct tu_pipeline_key *key,
1035 uint32_t flags);
1036
1037 static inline gl_shader_stage
1038 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1039 {
1040 assert(__builtin_popcount(vk_stage) == 1);
1041 return ffs(vk_stage) - 1;
1042 }
1043
1044 static inline VkShaderStageFlagBits
1045 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1046 {
1047 return (1 << mesa_stage);
1048 }
1049
1050 #define TU_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1051
1052 #define tu_foreach_stage(stage, stage_bits) \
1053 for (gl_shader_stage stage, \
1054 __tmp = (gl_shader_stage)((stage_bits) &TU_STAGE_MASK); \
1055 stage = __builtin_ffs(__tmp) - 1, __tmp; __tmp &= ~(1 << (stage)))
1056
1057 struct tu_shader_module
1058 {
1059 unsigned char sha1[20];
1060
1061 uint32_t code_size;
1062 const uint32_t *code[0];
1063 };
1064
1065 struct tu_shader_compile_options
1066 {
1067 struct ir3_shader_key key;
1068
1069 bool optimize;
1070 bool include_binning_pass;
1071 };
1072
1073 struct tu_descriptor_map
1074 {
1075 /* TODO: avoid fixed size array/justify the size */
1076 unsigned num; /* number of array entries */
1077 unsigned num_desc; /* Number of descriptors (sum of array_size[]) */
1078 int set[64];
1079 int binding[64];
1080 int value[64];
1081 int array_size[64];
1082 };
1083
1084 struct tu_shader
1085 {
1086 struct ir3_shader ir3_shader;
1087
1088 struct tu_descriptor_map texture_map;
1089 struct tu_descriptor_map sampler_map;
1090 struct tu_descriptor_map ubo_map;
1091 struct tu_descriptor_map ssbo_map;
1092 struct tu_descriptor_map image_map;
1093
1094 /* This may be true for vertex shaders. When true, variants[1] is the
1095 * binning variant and binning_binary is non-NULL.
1096 */
1097 bool has_binning_pass;
1098
1099 void *binary;
1100 void *binning_binary;
1101
1102 struct ir3_shader_variant variants[0];
1103 };
1104
1105 struct tu_shader *
1106 tu_shader_create(struct tu_device *dev,
1107 gl_shader_stage stage,
1108 const VkPipelineShaderStageCreateInfo *stage_info,
1109 struct tu_pipeline_layout *layout,
1110 const VkAllocationCallbacks *alloc);
1111
1112 void
1113 tu_shader_destroy(struct tu_device *dev,
1114 struct tu_shader *shader,
1115 const VkAllocationCallbacks *alloc);
1116
1117 void
1118 tu_shader_compile_options_init(
1119 struct tu_shader_compile_options *options,
1120 const VkGraphicsPipelineCreateInfo *pipeline_info);
1121
1122 VkResult
1123 tu_shader_compile(struct tu_device *dev,
1124 struct tu_shader *shader,
1125 const struct tu_shader *next_stage,
1126 const struct tu_shader_compile_options *options,
1127 const VkAllocationCallbacks *alloc);
1128
1129 struct tu_program_descriptor_linkage
1130 {
1131 struct ir3_ubo_analysis_state ubo_state;
1132 struct ir3_const_state const_state;
1133
1134 uint32_t constlen;
1135
1136 struct tu_descriptor_map texture_map;
1137 struct tu_descriptor_map sampler_map;
1138 struct tu_descriptor_map ubo_map;
1139 struct tu_descriptor_map ssbo_map;
1140 struct tu_descriptor_map image_map;
1141 };
1142
1143 struct tu_pipeline
1144 {
1145 struct tu_cs cs;
1146
1147 struct tu_dynamic_state dynamic_state;
1148
1149 struct tu_pipeline_layout *layout;
1150
1151 bool need_indirect_descriptor_sets;
1152 VkShaderStageFlags active_stages;
1153
1154 struct
1155 {
1156 struct tu_bo binary_bo;
1157 struct tu_cs_entry state_ib;
1158 struct tu_cs_entry binning_state_ib;
1159
1160 struct tu_program_descriptor_linkage link[MESA_SHADER_STAGES];
1161 } program;
1162
1163 struct
1164 {
1165 uint8_t bindings[MAX_VERTEX_ATTRIBS];
1166 uint16_t strides[MAX_VERTEX_ATTRIBS];
1167 uint16_t offsets[MAX_VERTEX_ATTRIBS];
1168 uint32_t count;
1169
1170 uint8_t binning_bindings[MAX_VERTEX_ATTRIBS];
1171 uint16_t binning_strides[MAX_VERTEX_ATTRIBS];
1172 uint16_t binning_offsets[MAX_VERTEX_ATTRIBS];
1173 uint32_t binning_count;
1174
1175 struct tu_cs_entry state_ib;
1176 struct tu_cs_entry binning_state_ib;
1177 } vi;
1178
1179 struct
1180 {
1181 enum pc_di_primtype primtype;
1182 bool primitive_restart;
1183 } ia;
1184
1185 struct
1186 {
1187 struct tu_cs_entry state_ib;
1188 } vp;
1189
1190 struct
1191 {
1192 uint32_t gras_su_cntl;
1193 struct tu_cs_entry state_ib;
1194 } rast;
1195
1196 struct
1197 {
1198 struct tu_cs_entry state_ib;
1199 } ds;
1200
1201 struct
1202 {
1203 struct tu_cs_entry state_ib;
1204 } blend;
1205
1206 struct
1207 {
1208 uint32_t local_size[3];
1209 } compute;
1210 };
1211
1212 void
1213 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport);
1214
1215 void
1216 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor);
1217
1218 void
1219 tu6_emit_gras_su_cntl(struct tu_cs *cs,
1220 uint32_t gras_su_cntl,
1221 float line_width);
1222
1223 void
1224 tu6_emit_depth_bias(struct tu_cs *cs,
1225 float constant_factor,
1226 float clamp,
1227 float slope_factor);
1228
1229 void
1230 tu6_emit_stencil_compare_mask(struct tu_cs *cs,
1231 uint32_t front,
1232 uint32_t back);
1233
1234 void
1235 tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back);
1236
1237 void
1238 tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back);
1239
1240 void
1241 tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4]);
1242
1243 struct tu_userdata_info *
1244 tu_lookup_user_sgpr(struct tu_pipeline *pipeline,
1245 gl_shader_stage stage,
1246 int idx);
1247
1248 struct tu_shader_variant *
1249 tu_get_shader(struct tu_pipeline *pipeline, gl_shader_stage stage);
1250
1251 struct tu_graphics_pipeline_create_info
1252 {
1253 bool use_rectlist;
1254 bool db_depth_clear;
1255 bool db_stencil_clear;
1256 bool db_depth_disable_expclear;
1257 bool db_stencil_disable_expclear;
1258 bool db_flush_depth_inplace;
1259 bool db_flush_stencil_inplace;
1260 bool db_resummarize;
1261 uint32_t custom_blend_mode;
1262 };
1263
1264 struct tu_native_format
1265 {
1266 int vtx; /* VFMTn_xxx or -1 */
1267 int tex; /* TFMTn_xxx or -1 */
1268 int rb; /* RBn_xxx or -1 */
1269 int swap; /* enum a3xx_color_swap */
1270 bool present; /* internal only; always true to external users */
1271 };
1272
1273 const struct tu_native_format *
1274 tu6_get_native_format(VkFormat format);
1275
1276 void
1277 tu_pack_clear_value(const VkClearValue *val,
1278 VkFormat format,
1279 uint32_t buf[4]);
1280
1281 void
1282 tu_2d_clear_color(const VkClearColorValue *val, VkFormat format, uint32_t buf[4]);
1283
1284 void
1285 tu_2d_clear_zs(const VkClearDepthStencilValue *val, VkFormat format, uint32_t buf[4]);
1286
1287 enum a6xx_2d_ifmt tu6_fmt_to_ifmt(enum a6xx_format fmt);
1288 enum a6xx_depth_format tu6_pipe2depth(VkFormat format);
1289
1290 struct tu_image_level
1291 {
1292 VkDeviceSize offset;
1293 VkDeviceSize size;
1294 uint32_t pitch;
1295 };
1296
1297 struct tu_image
1298 {
1299 VkImageType type;
1300 /* The original VkFormat provided by the client. This may not match any
1301 * of the actual surface formats.
1302 */
1303 VkFormat vk_format;
1304 VkImageAspectFlags aspects;
1305 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1306 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1307 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1308 VkExtent3D extent;
1309 uint32_t level_count;
1310 uint32_t layer_count;
1311 VkSampleCountFlagBits samples;
1312
1313
1314 uint32_t alignment;
1315
1316 struct fdl_layout layout;
1317
1318 unsigned queue_family_mask;
1319 bool exclusive;
1320 bool shareable;
1321
1322 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1323 VkDeviceMemory owned_memory;
1324
1325 /* Set when bound */
1326 struct tu_bo *bo;
1327 VkDeviceSize bo_offset;
1328 };
1329
1330 unsigned
1331 tu_image_queue_family_mask(const struct tu_image *image,
1332 uint32_t family,
1333 uint32_t queue_family);
1334
1335 static inline uint32_t
1336 tu_get_layerCount(const struct tu_image *image,
1337 const VkImageSubresourceRange *range)
1338 {
1339 return range->layerCount == VK_REMAINING_ARRAY_LAYERS
1340 ? image->layer_count - range->baseArrayLayer
1341 : range->layerCount;
1342 }
1343
1344 static inline uint32_t
1345 tu_get_levelCount(const struct tu_image *image,
1346 const VkImageSubresourceRange *range)
1347 {
1348 return range->levelCount == VK_REMAINING_MIP_LEVELS
1349 ? image->level_count - range->baseMipLevel
1350 : range->levelCount;
1351 }
1352
1353 static inline VkDeviceSize
1354 tu_layer_size(struct tu_image *image, int level)
1355 {
1356 return fdl_layer_stride(&image->layout, level);
1357 }
1358
1359 static inline uint32_t
1360 tu_image_stride(struct tu_image *image, int level)
1361 {
1362 return image->layout.slices[level].pitch * image->layout.cpp;
1363 }
1364
1365 static inline uint64_t
1366 tu_image_base(struct tu_image *image, int level, int layer)
1367 {
1368 return image->bo->iova + image->bo_offset +
1369 fdl_surface_offset(&image->layout, level, layer);
1370 }
1371
1372 #define tu_image_base_ref(image, level, layer) \
1373 .bo = image->bo, \
1374 .bo_offset = (image->bo_offset + fdl_surface_offset(&image->layout, \
1375 level, layer))
1376
1377 #define tu_image_view_base_ref(iview) \
1378 tu_image_base_ref(iview->image, iview->base_mip, iview->base_layer)
1379
1380 static inline VkDeviceSize
1381 tu_image_ubwc_size(struct tu_image *image, int level)
1382 {
1383 return image->layout.ubwc_layer_size;
1384 }
1385
1386 static inline uint32_t
1387 tu_image_ubwc_pitch(struct tu_image *image, int level)
1388 {
1389 return image->layout.ubwc_slices[level].pitch;
1390 }
1391
1392 static inline uint64_t
1393 tu_image_ubwc_surface_offset(struct tu_image *image, int level, int layer)
1394 {
1395 return image->layout.ubwc_slices[level].offset +
1396 layer * tu_image_ubwc_size(image, level);
1397 }
1398
1399 static inline uint64_t
1400 tu_image_ubwc_base(struct tu_image *image, int level, int layer)
1401 {
1402 return image->bo->iova + image->bo_offset +
1403 tu_image_ubwc_surface_offset(image, level, layer);
1404 }
1405
1406 #define tu_image_ubwc_base_ref(image, level, layer) \
1407 .bo = image->bo, \
1408 .bo_offset = (image->bo_offset + tu_image_ubwc_surface_offset(image, \
1409 level, layer))
1410
1411 #define tu_image_view_ubwc_base_ref(iview) \
1412 tu_image_ubwc_base_ref(iview->image, iview->base_mip, iview->base_layer)
1413
1414 enum a6xx_tile_mode
1415 tu6_get_image_tile_mode(struct tu_image *image, int level);
1416 enum a3xx_msaa_samples
1417 tu_msaa_samples(uint32_t samples);
1418
1419 struct tu_image_view
1420 {
1421 struct tu_image *image; /**< VkImageViewCreateInfo::image */
1422
1423 VkImageViewType type;
1424 VkImageAspectFlags aspect_mask;
1425 VkFormat vk_format;
1426 uint32_t base_layer;
1427 uint32_t layer_count;
1428 uint32_t base_mip;
1429 uint32_t level_count;
1430 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1431
1432 uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
1433
1434 /* Descriptor for use as a storage image as opposed to a sampled image.
1435 * This has a few differences for cube maps (e.g. type).
1436 */
1437 uint32_t storage_descriptor[A6XX_TEX_CONST_DWORDS];
1438 };
1439
1440 struct tu_sampler
1441 {
1442 uint32_t state[A6XX_TEX_SAMP_DWORDS];
1443
1444 bool needs_border;
1445 VkBorderColor border;
1446 };
1447
1448 VkResult
1449 tu_image_create(VkDevice _device,
1450 const VkImageCreateInfo *pCreateInfo,
1451 const VkAllocationCallbacks *alloc,
1452 VkImage *pImage,
1453 uint64_t modifier);
1454
1455 VkResult
1456 tu_image_from_gralloc(VkDevice device_h,
1457 const VkImageCreateInfo *base_info,
1458 const VkNativeBufferANDROID *gralloc_info,
1459 const VkAllocationCallbacks *alloc,
1460 VkImage *out_image_h);
1461
1462 void
1463 tu_image_view_init(struct tu_image_view *view,
1464 struct tu_device *device,
1465 const VkImageViewCreateInfo *pCreateInfo);
1466
1467 struct tu_buffer_view
1468 {
1469 uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
1470
1471 struct tu_buffer *buffer;
1472 };
1473 void
1474 tu_buffer_view_init(struct tu_buffer_view *view,
1475 struct tu_device *device,
1476 const VkBufferViewCreateInfo *pCreateInfo);
1477
1478 static inline struct VkExtent3D
1479 tu_sanitize_image_extent(const VkImageType imageType,
1480 const struct VkExtent3D imageExtent)
1481 {
1482 switch (imageType) {
1483 case VK_IMAGE_TYPE_1D:
1484 return (VkExtent3D) { imageExtent.width, 1, 1 };
1485 case VK_IMAGE_TYPE_2D:
1486 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1487 case VK_IMAGE_TYPE_3D:
1488 return imageExtent;
1489 default:
1490 unreachable("invalid image type");
1491 }
1492 }
1493
1494 static inline struct VkOffset3D
1495 tu_sanitize_image_offset(const VkImageType imageType,
1496 const struct VkOffset3D imageOffset)
1497 {
1498 switch (imageType) {
1499 case VK_IMAGE_TYPE_1D:
1500 return (VkOffset3D) { imageOffset.x, 0, 0 };
1501 case VK_IMAGE_TYPE_2D:
1502 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1503 case VK_IMAGE_TYPE_3D:
1504 return imageOffset;
1505 default:
1506 unreachable("invalid image type");
1507 }
1508 }
1509
1510 struct tu_attachment_info
1511 {
1512 struct tu_image_view *attachment;
1513 };
1514
1515 struct tu_framebuffer
1516 {
1517 uint32_t width;
1518 uint32_t height;
1519 uint32_t layers;
1520
1521 uint32_t attachment_count;
1522 struct tu_attachment_info attachments[0];
1523 };
1524
1525 struct tu_subpass_attachment
1526 {
1527 uint32_t attachment;
1528 };
1529
1530 struct tu_subpass
1531 {
1532 uint32_t input_count;
1533 uint32_t color_count;
1534 struct tu_subpass_attachment *input_attachments;
1535 struct tu_subpass_attachment *color_attachments;
1536 struct tu_subpass_attachment *resolve_attachments;
1537 struct tu_subpass_attachment depth_stencil_attachment;
1538
1539 VkSampleCountFlagBits samples;
1540 };
1541
1542 struct tu_render_pass_attachment
1543 {
1544 VkFormat format;
1545 uint32_t cpp;
1546 VkAttachmentLoadOp load_op;
1547 VkAttachmentLoadOp stencil_load_op;
1548 VkAttachmentStoreOp store_op;
1549 VkAttachmentStoreOp stencil_store_op;
1550 int32_t gmem_offset;
1551 };
1552
1553 struct tu_render_pass
1554 {
1555 uint32_t attachment_count;
1556 uint32_t subpass_count;
1557 uint32_t gmem_pixels;
1558 struct tu_subpass_attachment *subpass_attachments;
1559 struct tu_render_pass_attachment *attachments;
1560 struct tu_subpass subpasses[0];
1561 };
1562
1563 VkResult
1564 tu_device_init_meta(struct tu_device *device);
1565 void
1566 tu_device_finish_meta(struct tu_device *device);
1567
1568 struct tu_query_pool
1569 {
1570 VkQueryType type;
1571 uint32_t stride;
1572 uint64_t size;
1573 uint32_t pipeline_statistics;
1574 struct tu_bo bo;
1575 };
1576
1577 struct tu_semaphore
1578 {
1579 uint32_t syncobj;
1580 uint32_t temp_syncobj;
1581 };
1582
1583 void
1584 tu_set_descriptor_set(struct tu_cmd_buffer *cmd_buffer,
1585 VkPipelineBindPoint bind_point,
1586 struct tu_descriptor_set *set,
1587 unsigned idx);
1588
1589 void
1590 tu_update_descriptor_sets(struct tu_device *device,
1591 struct tu_cmd_buffer *cmd_buffer,
1592 VkDescriptorSet overrideSet,
1593 uint32_t descriptorWriteCount,
1594 const VkWriteDescriptorSet *pDescriptorWrites,
1595 uint32_t descriptorCopyCount,
1596 const VkCopyDescriptorSet *pDescriptorCopies);
1597
1598 void
1599 tu_update_descriptor_set_with_template(
1600 struct tu_device *device,
1601 struct tu_cmd_buffer *cmd_buffer,
1602 struct tu_descriptor_set *set,
1603 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
1604 const void *pData);
1605
1606 void
1607 tu_meta_push_descriptor_set(struct tu_cmd_buffer *cmd_buffer,
1608 VkPipelineBindPoint pipelineBindPoint,
1609 VkPipelineLayout _layout,
1610 uint32_t set,
1611 uint32_t descriptorWriteCount,
1612 const VkWriteDescriptorSet *pDescriptorWrites);
1613
1614 int
1615 tu_drm_get_gpu_id(const struct tu_physical_device *dev, uint32_t *id);
1616
1617 int
1618 tu_drm_get_gmem_size(const struct tu_physical_device *dev, uint32_t *size);
1619
1620 int
1621 tu_drm_submitqueue_new(const struct tu_device *dev,
1622 int priority,
1623 uint32_t *queue_id);
1624
1625 void
1626 tu_drm_submitqueue_close(const struct tu_device *dev, uint32_t queue_id);
1627
1628 uint32_t
1629 tu_gem_new(const struct tu_device *dev, uint64_t size, uint32_t flags);
1630 uint32_t
1631 tu_gem_import_dmabuf(const struct tu_device *dev,
1632 int prime_fd,
1633 uint64_t size);
1634 int
1635 tu_gem_export_dmabuf(const struct tu_device *dev, uint32_t gem_handle);
1636 void
1637 tu_gem_close(const struct tu_device *dev, uint32_t gem_handle);
1638 uint64_t
1639 tu_gem_info_offset(const struct tu_device *dev, uint32_t gem_handle);
1640 uint64_t
1641 tu_gem_info_iova(const struct tu_device *dev, uint32_t gem_handle);
1642
1643
1644 void
1645 tu_clear_sysmem_attachment(struct tu_cmd_buffer *cmd,
1646 struct tu_cs *cs,
1647 uint32_t attachment,
1648 const VkClearValue *value,
1649 const VkClearRect *rect);
1650
1651 void
1652 tu_clear_gmem_attachment(struct tu_cmd_buffer *cmd,
1653 struct tu_cs *cs,
1654 uint32_t attachment,
1655 uint8_t component_mask,
1656 const VkClearValue *value);
1657
1658 #define TU_DEFINE_HANDLE_CASTS(__tu_type, __VkType) \
1659 \
1660 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1661 { \
1662 return (struct __tu_type *) _handle; \
1663 } \
1664 \
1665 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1666 { \
1667 return (__VkType) _obj; \
1668 }
1669
1670 #define TU_DEFINE_NONDISP_HANDLE_CASTS(__tu_type, __VkType) \
1671 \
1672 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1673 { \
1674 return (struct __tu_type *) (uintptr_t) _handle; \
1675 } \
1676 \
1677 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1678 { \
1679 return (__VkType)(uintptr_t) _obj; \
1680 }
1681
1682 #define TU_FROM_HANDLE(__tu_type, __name, __handle) \
1683 struct __tu_type *__name = __tu_type##_from_handle(__handle)
1684
1685 TU_DEFINE_HANDLE_CASTS(tu_cmd_buffer, VkCommandBuffer)
1686 TU_DEFINE_HANDLE_CASTS(tu_device, VkDevice)
1687 TU_DEFINE_HANDLE_CASTS(tu_instance, VkInstance)
1688 TU_DEFINE_HANDLE_CASTS(tu_physical_device, VkPhysicalDevice)
1689 TU_DEFINE_HANDLE_CASTS(tu_queue, VkQueue)
1690
1691 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_cmd_pool, VkCommandPool)
1692 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer, VkBuffer)
1693 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer_view, VkBufferView)
1694 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_pool, VkDescriptorPool)
1695 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set, VkDescriptorSet)
1696 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set_layout,
1697 VkDescriptorSetLayout)
1698 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_update_template,
1699 VkDescriptorUpdateTemplate)
1700 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_device_memory, VkDeviceMemory)
1701 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_fence, VkFence)
1702 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_event, VkEvent)
1703 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_framebuffer, VkFramebuffer)
1704 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image, VkImage)
1705 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image_view, VkImageView);
1706 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_cache, VkPipelineCache)
1707 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline, VkPipeline)
1708 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_layout, VkPipelineLayout)
1709 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_query_pool, VkQueryPool)
1710 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_render_pass, VkRenderPass)
1711 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_sampler, VkSampler)
1712 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_shader_module, VkShaderModule)
1713 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_semaphore, VkSemaphore)
1714
1715 #endif /* TU_PRIVATE_H */