freedreno/a6xx: use single format enum
[mesa.git] / src / freedreno / vulkan / tu_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #ifndef TU_PRIVATE_H
29 #define TU_PRIVATE_H
30
31 #include <assert.h>
32 #include <pthread.h>
33 #include <stdbool.h>
34 #include <stdint.h>
35 #include <stdio.h>
36 #include <stdlib.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <memcheck.h>
40 #include <valgrind.h>
41 #define VG(x) x
42 #else
43 #define VG(x) ((void)0)
44 #endif
45
46 #include "c11/threads.h"
47 #include "main/macros.h"
48 #include "util/list.h"
49 #include "util/macros.h"
50 #include "vk_alloc.h"
51 #include "vk_debug_report.h"
52 #include "wsi_common.h"
53
54 #include "drm-uapi/msm_drm.h"
55 #include "ir3/ir3_compiler.h"
56 #include "ir3/ir3_shader.h"
57
58 #include "adreno_common.xml.h"
59 #include "adreno_pm4.xml.h"
60 #include "a6xx.xml.h"
61 #include "fdl/freedreno_layout.h"
62
63 #include "tu_descriptor_set.h"
64 #include "tu_extensions.h"
65
66 /* Pre-declarations needed for WSI entrypoints */
67 struct wl_surface;
68 struct wl_display;
69 typedef struct xcb_connection_t xcb_connection_t;
70 typedef uint32_t xcb_visualid_t;
71 typedef uint32_t xcb_window_t;
72
73 #include <vulkan/vk_android_native_buffer.h>
74 #include <vulkan/vk_icd.h>
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77
78 #include "tu_entrypoints.h"
79
80 #define MAX_VBS 32
81 #define MAX_VERTEX_ATTRIBS 32
82 #define MAX_RTS 8
83 #define MAX_VSC_PIPES 32
84 #define MAX_VIEWPORTS 1
85 #define MAX_SCISSORS 16
86 #define MAX_DISCARD_RECTANGLES 4
87 #define MAX_PUSH_CONSTANTS_SIZE 128
88 #define MAX_PUSH_DESCRIPTORS 32
89 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
90 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
91 #define MAX_DYNAMIC_BUFFERS \
92 (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
93 #define MAX_SAMPLES_LOG2 4
94 #define NUM_META_FS_KEYS 13
95 #define TU_MAX_DRM_DEVICES 8
96 #define MAX_VIEWS 8
97 /* The Qualcomm driver exposes 0x20000058 */
98 #define MAX_STORAGE_BUFFER_RANGE 0x20000000
99
100 #define NUM_DEPTH_CLEAR_PIPELINES 3
101
102 /*
103 * This is the point we switch from using CP to compute shader
104 * for certain buffer operations.
105 */
106 #define TU_BUFFER_OPS_CS_THRESHOLD 4096
107
108 #define A6XX_TEX_CONST_DWORDS 16
109 #define A6XX_TEX_SAMP_DWORDS 4
110
111 enum tu_mem_heap
112 {
113 TU_MEM_HEAP_VRAM,
114 TU_MEM_HEAP_VRAM_CPU_ACCESS,
115 TU_MEM_HEAP_GTT,
116 TU_MEM_HEAP_COUNT
117 };
118
119 enum tu_mem_type
120 {
121 TU_MEM_TYPE_VRAM,
122 TU_MEM_TYPE_GTT_WRITE_COMBINE,
123 TU_MEM_TYPE_VRAM_CPU_ACCESS,
124 TU_MEM_TYPE_GTT_CACHED,
125 TU_MEM_TYPE_COUNT
126 };
127
128 #define tu_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
129
130 static inline uint32_t
131 align_u32(uint32_t v, uint32_t a)
132 {
133 assert(a != 0 && a == (a & -a));
134 return (v + a - 1) & ~(a - 1);
135 }
136
137 static inline uint32_t
138 align_u32_npot(uint32_t v, uint32_t a)
139 {
140 return (v + a - 1) / a * a;
141 }
142
143 static inline uint64_t
144 align_u64(uint64_t v, uint64_t a)
145 {
146 assert(a != 0 && a == (a & -a));
147 return (v + a - 1) & ~(a - 1);
148 }
149
150 static inline int32_t
151 align_i32(int32_t v, int32_t a)
152 {
153 assert(a != 0 && a == (a & -a));
154 return (v + a - 1) & ~(a - 1);
155 }
156
157 /** Alignment must be a power of 2. */
158 static inline bool
159 tu_is_aligned(uintmax_t n, uintmax_t a)
160 {
161 assert(a == (a & -a));
162 return (n & (a - 1)) == 0;
163 }
164
165 static inline uint32_t
166 round_up_u32(uint32_t v, uint32_t a)
167 {
168 return (v + a - 1) / a;
169 }
170
171 static inline uint64_t
172 round_up_u64(uint64_t v, uint64_t a)
173 {
174 return (v + a - 1) / a;
175 }
176
177 static inline uint32_t
178 tu_minify(uint32_t n, uint32_t levels)
179 {
180 if (unlikely(n == 0))
181 return 0;
182 else
183 return MAX2(n >> levels, 1);
184 }
185 static inline float
186 tu_clamp_f(float f, float min, float max)
187 {
188 assert(min < max);
189
190 if (f > max)
191 return max;
192 else if (f < min)
193 return min;
194 else
195 return f;
196 }
197
198 static inline bool
199 tu_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
200 {
201 if (*inout_mask & clear_mask) {
202 *inout_mask &= ~clear_mask;
203 return true;
204 } else {
205 return false;
206 }
207 }
208
209 #define for_each_bit(b, dword) \
210 for (uint32_t __dword = (dword); \
211 (b) = __builtin_ffs(__dword) - 1, __dword; __dword &= ~(1 << (b)))
212
213 #define typed_memcpy(dest, src, count) \
214 ({ \
215 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
216 memcpy((dest), (src), (count) * sizeof(*(src))); \
217 })
218
219 #define COND(bool, val) ((bool) ? (val) : 0)
220
221 /* Whenever we generate an error, pass it through this function. Useful for
222 * debugging, where we can break on it. Only call at error site, not when
223 * propagating errors. Might be useful to plug in a stack trace here.
224 */
225
226 struct tu_instance;
227
228 VkResult
229 __vk_errorf(struct tu_instance *instance,
230 VkResult error,
231 const char *file,
232 int line,
233 const char *format,
234 ...);
235
236 #define vk_error(instance, error) \
237 __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
238 #define vk_errorf(instance, error, format, ...) \
239 __vk_errorf(instance, error, __FILE__, __LINE__, format, ##__VA_ARGS__);
240
241 void
242 __tu_finishme(const char *file, int line, const char *format, ...)
243 tu_printflike(3, 4);
244 void
245 tu_loge(const char *format, ...) tu_printflike(1, 2);
246 void
247 tu_loge_v(const char *format, va_list va);
248 void
249 tu_logi(const char *format, ...) tu_printflike(1, 2);
250 void
251 tu_logi_v(const char *format, va_list va);
252
253 /**
254 * Print a FINISHME message, including its source location.
255 */
256 #define tu_finishme(format, ...) \
257 do { \
258 static bool reported = false; \
259 if (!reported) { \
260 __tu_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
261 reported = true; \
262 } \
263 } while (0)
264
265 /* A non-fatal assert. Useful for debugging. */
266 #ifdef DEBUG
267 #define tu_assert(x) \
268 ({ \
269 if (unlikely(!(x))) \
270 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
271 })
272 #else
273 #define tu_assert(x)
274 #endif
275
276 /* Suppress -Wunused in stub functions */
277 #define tu_use_args(...) __tu_use_args(0, ##__VA_ARGS__)
278 static inline void
279 __tu_use_args(int ignore, ...)
280 {
281 }
282
283 #define tu_stub() \
284 do { \
285 tu_finishme("stub %s", __func__); \
286 } while (0)
287
288 void *
289 tu_lookup_entrypoint_unchecked(const char *name);
290 void *
291 tu_lookup_entrypoint_checked(
292 const char *name,
293 uint32_t core_version,
294 const struct tu_instance_extension_table *instance,
295 const struct tu_device_extension_table *device);
296
297 struct tu_physical_device
298 {
299 VK_LOADER_DATA _loader_data;
300
301 struct tu_instance *instance;
302
303 char path[20];
304 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
305 uint8_t driver_uuid[VK_UUID_SIZE];
306 uint8_t device_uuid[VK_UUID_SIZE];
307 uint8_t cache_uuid[VK_UUID_SIZE];
308
309 struct wsi_device wsi_device;
310
311 int local_fd;
312 int master_fd;
313
314 unsigned gpu_id;
315 uint32_t gmem_size;
316 uint32_t tile_align_w;
317 uint32_t tile_align_h;
318
319 /* This is the drivers on-disk cache used as a fallback as opposed to
320 * the pipeline cache defined by apps.
321 */
322 struct disk_cache *disk_cache;
323
324 struct tu_device_extension_table supported_extensions;
325 };
326
327 enum tu_debug_flags
328 {
329 TU_DEBUG_STARTUP = 1 << 0,
330 TU_DEBUG_NIR = 1 << 1,
331 TU_DEBUG_IR3 = 1 << 2,
332 TU_DEBUG_NOBIN = 1 << 3,
333 };
334
335 struct tu_instance
336 {
337 VK_LOADER_DATA _loader_data;
338
339 VkAllocationCallbacks alloc;
340
341 uint32_t api_version;
342 int physical_device_count;
343 struct tu_physical_device physical_devices[TU_MAX_DRM_DEVICES];
344
345 enum tu_debug_flags debug_flags;
346
347 struct vk_debug_report_instance debug_report_callbacks;
348
349 struct tu_instance_extension_table enabled_extensions;
350 };
351
352 VkResult
353 tu_wsi_init(struct tu_physical_device *physical_device);
354 void
355 tu_wsi_finish(struct tu_physical_device *physical_device);
356
357 bool
358 tu_instance_extension_supported(const char *name);
359 uint32_t
360 tu_physical_device_api_version(struct tu_physical_device *dev);
361 bool
362 tu_physical_device_extension_supported(struct tu_physical_device *dev,
363 const char *name);
364
365 struct cache_entry;
366
367 struct tu_pipeline_cache
368 {
369 struct tu_device *device;
370 pthread_mutex_t mutex;
371
372 uint32_t total_size;
373 uint32_t table_size;
374 uint32_t kernel_count;
375 struct cache_entry **hash_table;
376 bool modified;
377
378 VkAllocationCallbacks alloc;
379 };
380
381 struct tu_pipeline_key
382 {
383 };
384
385 void
386 tu_pipeline_cache_init(struct tu_pipeline_cache *cache,
387 struct tu_device *device);
388 void
389 tu_pipeline_cache_finish(struct tu_pipeline_cache *cache);
390 void
391 tu_pipeline_cache_load(struct tu_pipeline_cache *cache,
392 const void *data,
393 size_t size);
394
395 struct tu_shader_variant;
396
397 bool
398 tu_create_shader_variants_from_pipeline_cache(
399 struct tu_device *device,
400 struct tu_pipeline_cache *cache,
401 const unsigned char *sha1,
402 struct tu_shader_variant **variants);
403
404 void
405 tu_pipeline_cache_insert_shaders(struct tu_device *device,
406 struct tu_pipeline_cache *cache,
407 const unsigned char *sha1,
408 struct tu_shader_variant **variants,
409 const void *const *codes,
410 const unsigned *code_sizes);
411
412 struct tu_meta_state
413 {
414 VkAllocationCallbacks alloc;
415
416 struct tu_pipeline_cache cache;
417 };
418
419 /* queue types */
420 #define TU_QUEUE_GENERAL 0
421
422 #define TU_MAX_QUEUE_FAMILIES 1
423
424 struct tu_fence
425 {
426 struct wsi_fence *fence_wsi;
427 bool signaled;
428 int fd;
429 };
430
431 void
432 tu_fence_init(struct tu_fence *fence, bool signaled);
433 void
434 tu_fence_finish(struct tu_fence *fence);
435 void
436 tu_fence_update_fd(struct tu_fence *fence, int fd);
437 void
438 tu_fence_copy(struct tu_fence *fence, const struct tu_fence *src);
439 void
440 tu_fence_signal(struct tu_fence *fence);
441 void
442 tu_fence_wait_idle(struct tu_fence *fence);
443
444 struct tu_queue
445 {
446 VK_LOADER_DATA _loader_data;
447 struct tu_device *device;
448 uint32_t queue_family_index;
449 int queue_idx;
450 VkDeviceQueueCreateFlags flags;
451
452 uint32_t msm_queue_id;
453 struct tu_fence submit_fence;
454 };
455
456 struct tu_bo
457 {
458 uint32_t gem_handle;
459 uint64_t size;
460 uint64_t iova;
461 void *map;
462 };
463
464 struct tu_device
465 {
466 VK_LOADER_DATA _loader_data;
467
468 VkAllocationCallbacks alloc;
469
470 struct tu_instance *instance;
471
472 struct tu_meta_state meta_state;
473
474 struct tu_queue *queues[TU_MAX_QUEUE_FAMILIES];
475 int queue_count[TU_MAX_QUEUE_FAMILIES];
476
477 struct tu_physical_device *physical_device;
478
479 struct ir3_compiler *compiler;
480
481 /* Backup in-memory cache to be used if the app doesn't provide one */
482 struct tu_pipeline_cache *mem_cache;
483
484 struct tu_bo vsc_data;
485 struct tu_bo vsc_data2;
486 uint32_t vsc_data_pitch;
487 uint32_t vsc_data2_pitch;
488
489 struct list_head shader_slabs;
490 mtx_t shader_slab_mutex;
491
492 struct tu_device_extension_table enabled_extensions;
493 };
494
495 VkResult
496 tu_bo_init_new(struct tu_device *dev, struct tu_bo *bo, uint64_t size);
497 VkResult
498 tu_bo_init_dmabuf(struct tu_device *dev,
499 struct tu_bo *bo,
500 uint64_t size,
501 int fd);
502 int
503 tu_bo_export_dmabuf(struct tu_device *dev, struct tu_bo *bo);
504 void
505 tu_bo_finish(struct tu_device *dev, struct tu_bo *bo);
506 VkResult
507 tu_bo_map(struct tu_device *dev, struct tu_bo *bo);
508
509 struct tu_cs_entry
510 {
511 /* No ownership */
512 const struct tu_bo *bo;
513
514 uint32_t size;
515 uint32_t offset;
516 };
517
518 struct ts_cs_memory {
519 uint32_t *map;
520 uint64_t iova;
521 };
522
523 enum tu_cs_mode
524 {
525
526 /*
527 * A command stream in TU_CS_MODE_GROW mode grows automatically whenever it
528 * is full. tu_cs_begin must be called before command packet emission and
529 * tu_cs_end must be called after.
530 *
531 * This mode may create multiple entries internally. The entries must be
532 * submitted together.
533 */
534 TU_CS_MODE_GROW,
535
536 /*
537 * A command stream in TU_CS_MODE_EXTERNAL mode wraps an external,
538 * fixed-size buffer. tu_cs_begin and tu_cs_end are optional and have no
539 * effect on it.
540 *
541 * This mode does not create any entry or any BO.
542 */
543 TU_CS_MODE_EXTERNAL,
544
545 /*
546 * A command stream in TU_CS_MODE_SUB_STREAM mode does not support direct
547 * command packet emission. tu_cs_begin_sub_stream must be called to get a
548 * sub-stream to emit comamnd packets to. When done with the sub-stream,
549 * tu_cs_end_sub_stream must be called.
550 *
551 * This mode does not create any entry internally.
552 */
553 TU_CS_MODE_SUB_STREAM,
554 };
555
556 struct tu_cs
557 {
558 uint32_t *start;
559 uint32_t *cur;
560 uint32_t *reserved_end;
561 uint32_t *end;
562
563 enum tu_cs_mode mode;
564 uint32_t next_bo_size;
565
566 struct tu_cs_entry *entries;
567 uint32_t entry_count;
568 uint32_t entry_capacity;
569
570 struct tu_bo **bos;
571 uint32_t bo_count;
572 uint32_t bo_capacity;
573 };
574
575 struct tu_device_memory
576 {
577 struct tu_bo bo;
578 VkDeviceSize size;
579
580 /* for dedicated allocations */
581 struct tu_image *image;
582 struct tu_buffer *buffer;
583
584 uint32_t type_index;
585 void *map;
586 void *user_ptr;
587 };
588
589 struct tu_descriptor_range
590 {
591 uint64_t va;
592 uint32_t size;
593 };
594
595 struct tu_descriptor_set
596 {
597 const struct tu_descriptor_set_layout *layout;
598 uint32_t size;
599
600 uint64_t va;
601 uint32_t *mapped_ptr;
602 struct tu_descriptor_range *dynamic_descriptors;
603
604 struct tu_bo *descriptors[0];
605 };
606
607 struct tu_push_descriptor_set
608 {
609 struct tu_descriptor_set set;
610 uint32_t capacity;
611 };
612
613 struct tu_descriptor_pool_entry
614 {
615 uint32_t offset;
616 uint32_t size;
617 struct tu_descriptor_set *set;
618 };
619
620 struct tu_descriptor_pool
621 {
622 struct tu_bo bo;
623 uint64_t current_offset;
624 uint64_t size;
625
626 uint8_t *host_memory_base;
627 uint8_t *host_memory_ptr;
628 uint8_t *host_memory_end;
629
630 uint32_t entry_count;
631 uint32_t max_entry_count;
632 struct tu_descriptor_pool_entry entries[0];
633 };
634
635 struct tu_descriptor_update_template_entry
636 {
637 VkDescriptorType descriptor_type;
638
639 /* The number of descriptors to update */
640 uint32_t descriptor_count;
641
642 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array
643 */
644 uint32_t dst_offset;
645
646 /* In dwords. Not valid/used for dynamic descriptors */
647 uint32_t dst_stride;
648
649 uint32_t buffer_offset;
650
651 /* Only valid for combined image samplers and samplers */
652 uint16_t has_sampler;
653
654 /* In bytes */
655 size_t src_offset;
656 size_t src_stride;
657
658 /* For push descriptors */
659 const uint32_t *immutable_samplers;
660 };
661
662 struct tu_descriptor_update_template
663 {
664 uint32_t entry_count;
665 VkPipelineBindPoint bind_point;
666 struct tu_descriptor_update_template_entry entry[0];
667 };
668
669 struct tu_buffer
670 {
671 VkDeviceSize size;
672
673 VkBufferUsageFlags usage;
674 VkBufferCreateFlags flags;
675
676 struct tu_bo *bo;
677 VkDeviceSize bo_offset;
678 };
679
680 static inline uint64_t
681 tu_buffer_iova(struct tu_buffer *buffer)
682 {
683 return buffer->bo->iova + buffer->bo_offset;
684 }
685
686 enum tu_dynamic_state_bits
687 {
688 TU_DYNAMIC_VIEWPORT = 1 << 0,
689 TU_DYNAMIC_SCISSOR = 1 << 1,
690 TU_DYNAMIC_LINE_WIDTH = 1 << 2,
691 TU_DYNAMIC_DEPTH_BIAS = 1 << 3,
692 TU_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
693 TU_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
694 TU_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
695 TU_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
696 TU_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
697 TU_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
698 TU_DYNAMIC_ALL = (1 << 10) - 1,
699 };
700
701 struct tu_vertex_binding
702 {
703 struct tu_buffer *buffer;
704 VkDeviceSize offset;
705 };
706
707 struct tu_viewport_state
708 {
709 uint32_t count;
710 VkViewport viewports[MAX_VIEWPORTS];
711 };
712
713 struct tu_scissor_state
714 {
715 uint32_t count;
716 VkRect2D scissors[MAX_SCISSORS];
717 };
718
719 struct tu_discard_rectangle_state
720 {
721 uint32_t count;
722 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
723 };
724
725 struct tu_dynamic_state
726 {
727 /**
728 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
729 * Defines the set of saved dynamic state.
730 */
731 uint32_t mask;
732
733 struct tu_viewport_state viewport;
734
735 struct tu_scissor_state scissor;
736
737 float line_width;
738
739 struct
740 {
741 float bias;
742 float clamp;
743 float slope;
744 } depth_bias;
745
746 float blend_constants[4];
747
748 struct
749 {
750 float min;
751 float max;
752 } depth_bounds;
753
754 struct
755 {
756 uint32_t front;
757 uint32_t back;
758 } stencil_compare_mask;
759
760 struct
761 {
762 uint32_t front;
763 uint32_t back;
764 } stencil_write_mask;
765
766 struct
767 {
768 uint32_t front;
769 uint32_t back;
770 } stencil_reference;
771
772 struct tu_discard_rectangle_state discard_rectangle;
773 };
774
775 extern const struct tu_dynamic_state default_dynamic_state;
776
777 const char *
778 tu_get_debug_option_name(int id);
779
780 const char *
781 tu_get_perftest_option_name(int id);
782
783 struct tu_descriptor_state
784 {
785 struct tu_descriptor_set *sets[MAX_SETS];
786 uint32_t valid;
787 struct tu_push_descriptor_set push_set;
788 bool push_dirty;
789 uint64_t dynamic_buffers[MAX_DYNAMIC_BUFFERS];
790 };
791
792 struct tu_tile
793 {
794 uint8_t pipe;
795 uint8_t slot;
796 VkOffset2D begin;
797 VkOffset2D end;
798 };
799
800 struct tu_tiling_config
801 {
802 VkRect2D render_area;
803
804 /* position and size of the first tile */
805 VkRect2D tile0;
806 /* number of tiles */
807 VkExtent2D tile_count;
808
809 /* size of the first VSC pipe */
810 VkExtent2D pipe0;
811 /* number of VSC pipes */
812 VkExtent2D pipe_count;
813
814 /* pipe register values */
815 uint32_t pipe_config[MAX_VSC_PIPES];
816 uint32_t pipe_sizes[MAX_VSC_PIPES];
817 };
818
819 enum tu_cmd_dirty_bits
820 {
821 TU_CMD_DIRTY_PIPELINE = 1 << 0,
822 TU_CMD_DIRTY_COMPUTE_PIPELINE = 1 << 1,
823 TU_CMD_DIRTY_VERTEX_BUFFERS = 1 << 2,
824 TU_CMD_DIRTY_DESCRIPTOR_SETS = 1 << 3,
825 TU_CMD_DIRTY_PUSH_CONSTANTS = 1 << 4,
826
827 TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 16,
828 TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 17,
829 TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 18,
830 TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 19,
831 };
832
833 struct tu_cmd_state
834 {
835 uint32_t dirty;
836
837 struct tu_pipeline *pipeline;
838 struct tu_pipeline *compute_pipeline;
839
840 /* Vertex buffers */
841 struct
842 {
843 struct tu_buffer *buffers[MAX_VBS];
844 VkDeviceSize offsets[MAX_VBS];
845 } vb;
846
847 struct tu_dynamic_state dynamic;
848
849 /* Index buffer */
850 struct tu_buffer *index_buffer;
851 uint64_t index_offset;
852 uint32_t index_type;
853 uint32_t max_index_count;
854 uint64_t index_va;
855
856 const struct tu_render_pass *pass;
857 const struct tu_subpass *subpass;
858 const struct tu_framebuffer *framebuffer;
859
860 struct tu_tiling_config tiling_config;
861
862 struct tu_cs_entry tile_load_ib;
863 struct tu_cs_entry tile_store_ib;
864 };
865
866 struct tu_cmd_pool
867 {
868 VkAllocationCallbacks alloc;
869 struct list_head cmd_buffers;
870 struct list_head free_cmd_buffers;
871 uint32_t queue_family_index;
872 };
873
874 struct tu_cmd_buffer_upload
875 {
876 uint8_t *map;
877 unsigned offset;
878 uint64_t size;
879 struct list_head list;
880 };
881
882 enum tu_cmd_buffer_status
883 {
884 TU_CMD_BUFFER_STATUS_INVALID,
885 TU_CMD_BUFFER_STATUS_INITIAL,
886 TU_CMD_BUFFER_STATUS_RECORDING,
887 TU_CMD_BUFFER_STATUS_EXECUTABLE,
888 TU_CMD_BUFFER_STATUS_PENDING,
889 };
890
891 struct tu_bo_list
892 {
893 uint32_t count;
894 uint32_t capacity;
895 struct drm_msm_gem_submit_bo *bo_infos;
896 };
897
898 #define TU_BO_LIST_FAILED (~0)
899
900 void
901 tu_bo_list_init(struct tu_bo_list *list);
902 void
903 tu_bo_list_destroy(struct tu_bo_list *list);
904 void
905 tu_bo_list_reset(struct tu_bo_list *list);
906 uint32_t
907 tu_bo_list_add(struct tu_bo_list *list,
908 const struct tu_bo *bo,
909 uint32_t flags);
910 VkResult
911 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other);
912
913 struct tu_cmd_buffer
914 {
915 VK_LOADER_DATA _loader_data;
916
917 struct tu_device *device;
918
919 struct tu_cmd_pool *pool;
920 struct list_head pool_link;
921
922 VkCommandBufferUsageFlags usage_flags;
923 VkCommandBufferLevel level;
924 enum tu_cmd_buffer_status status;
925
926 struct tu_cmd_state state;
927 struct tu_vertex_binding vertex_bindings[MAX_VBS];
928 uint32_t queue_family_index;
929
930 uint32_t push_constants[MAX_PUSH_CONSTANTS_SIZE / 4];
931 VkShaderStageFlags push_constant_stages;
932 struct tu_descriptor_set meta_push_descriptors;
933
934 struct tu_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
935
936 struct tu_cmd_buffer_upload upload;
937
938 VkResult record_result;
939
940 struct tu_bo_list bo_list;
941 struct tu_cs cs;
942 struct tu_cs draw_cs;
943 struct tu_cs draw_epilogue_cs;
944 struct tu_cs sub_cs;
945
946 uint16_t marker_reg;
947 uint32_t marker_seqno;
948
949 struct tu_bo scratch_bo;
950 uint32_t scratch_seqno;
951 #define VSC_OVERFLOW 0x8
952 #define VSC_SCRATCH 0x10
953
954 struct tu_bo vsc_data;
955 struct tu_bo vsc_data2;
956 uint32_t vsc_data_pitch;
957 uint32_t vsc_data2_pitch;
958 bool use_vsc_data;
959
960 bool wait_for_idle;
961 };
962
963 /* Temporary struct for tracking a register state to be written, used by
964 * a6xx-pack.h and tu_cs_emit_regs()
965 */
966 struct tu_reg_value {
967 uint32_t reg;
968 uint64_t value;
969 bool is_address;
970 struct tu_bo *bo;
971 bool bo_write;
972 uint32_t bo_offset;
973 uint32_t bo_shift;
974 };
975
976 unsigned
977 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
978 struct tu_cs *cs,
979 enum vgt_event_type event,
980 bool need_seqno);
981
982 bool
983 tu_get_memory_fd(struct tu_device *device,
984 struct tu_device_memory *memory,
985 int *pFD);
986
987 static inline struct tu_descriptor_state *
988 tu_get_descriptors_state(struct tu_cmd_buffer *cmd_buffer,
989 VkPipelineBindPoint bind_point)
990 {
991 return &cmd_buffer->descriptors[bind_point];
992 }
993
994 /*
995 * Takes x,y,z as exact numbers of invocations, instead of blocks.
996 *
997 * Limitations: Can't call normal dispatch functions without binding or
998 * rebinding
999 * the compute pipeline.
1000 */
1001 void
1002 tu_unaligned_dispatch(struct tu_cmd_buffer *cmd_buffer,
1003 uint32_t x,
1004 uint32_t y,
1005 uint32_t z);
1006
1007 struct tu_event
1008 {
1009 struct tu_bo bo;
1010 };
1011
1012 struct tu_shader_module;
1013
1014 #define TU_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1015 #define TU_HASH_SHADER_SISCHED (1 << 1)
1016 #define TU_HASH_SHADER_UNSAFE_MATH (1 << 2)
1017 void
1018 tu_hash_shaders(unsigned char *hash,
1019 const VkPipelineShaderStageCreateInfo **stages,
1020 const struct tu_pipeline_layout *layout,
1021 const struct tu_pipeline_key *key,
1022 uint32_t flags);
1023
1024 static inline gl_shader_stage
1025 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1026 {
1027 assert(__builtin_popcount(vk_stage) == 1);
1028 return ffs(vk_stage) - 1;
1029 }
1030
1031 static inline VkShaderStageFlagBits
1032 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1033 {
1034 return (1 << mesa_stage);
1035 }
1036
1037 #define TU_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1038
1039 #define tu_foreach_stage(stage, stage_bits) \
1040 for (gl_shader_stage stage, \
1041 __tmp = (gl_shader_stage)((stage_bits) &TU_STAGE_MASK); \
1042 stage = __builtin_ffs(__tmp) - 1, __tmp; __tmp &= ~(1 << (stage)))
1043
1044 struct tu_shader_module
1045 {
1046 unsigned char sha1[20];
1047
1048 uint32_t code_size;
1049 const uint32_t *code[0];
1050 };
1051
1052 struct tu_shader_compile_options
1053 {
1054 struct ir3_shader_key key;
1055
1056 bool optimize;
1057 bool include_binning_pass;
1058 };
1059
1060 struct tu_descriptor_map
1061 {
1062 /* TODO: avoid fixed size array/justify the size */
1063 unsigned num; /* number of array entries */
1064 unsigned num_desc; /* Number of descriptors (sum of array_size[]) */
1065 int set[64];
1066 int binding[64];
1067 int value[64];
1068 int array_size[64];
1069 };
1070
1071 struct tu_shader
1072 {
1073 struct ir3_shader ir3_shader;
1074
1075 struct tu_descriptor_map texture_map;
1076 struct tu_descriptor_map sampler_map;
1077 struct tu_descriptor_map ubo_map;
1078 struct tu_descriptor_map ssbo_map;
1079 struct tu_descriptor_map image_map;
1080
1081 /* This may be true for vertex shaders. When true, variants[1] is the
1082 * binning variant and binning_binary is non-NULL.
1083 */
1084 bool has_binning_pass;
1085
1086 void *binary;
1087 void *binning_binary;
1088
1089 struct ir3_shader_variant variants[0];
1090 };
1091
1092 struct tu_shader *
1093 tu_shader_create(struct tu_device *dev,
1094 gl_shader_stage stage,
1095 const VkPipelineShaderStageCreateInfo *stage_info,
1096 struct tu_pipeline_layout *layout,
1097 const VkAllocationCallbacks *alloc);
1098
1099 void
1100 tu_shader_destroy(struct tu_device *dev,
1101 struct tu_shader *shader,
1102 const VkAllocationCallbacks *alloc);
1103
1104 void
1105 tu_shader_compile_options_init(
1106 struct tu_shader_compile_options *options,
1107 const VkGraphicsPipelineCreateInfo *pipeline_info);
1108
1109 VkResult
1110 tu_shader_compile(struct tu_device *dev,
1111 struct tu_shader *shader,
1112 const struct tu_shader *next_stage,
1113 const struct tu_shader_compile_options *options,
1114 const VkAllocationCallbacks *alloc);
1115
1116 struct tu_program_descriptor_linkage
1117 {
1118 struct ir3_ubo_analysis_state ubo_state;
1119 struct ir3_const_state const_state;
1120
1121 uint32_t constlen;
1122
1123 struct tu_descriptor_map texture_map;
1124 struct tu_descriptor_map sampler_map;
1125 struct tu_descriptor_map ubo_map;
1126 struct tu_descriptor_map ssbo_map;
1127 struct tu_descriptor_map image_map;
1128 };
1129
1130 struct tu_pipeline
1131 {
1132 struct tu_cs cs;
1133
1134 struct tu_dynamic_state dynamic_state;
1135
1136 struct tu_pipeline_layout *layout;
1137
1138 bool need_indirect_descriptor_sets;
1139 VkShaderStageFlags active_stages;
1140
1141 struct
1142 {
1143 struct tu_bo binary_bo;
1144 struct tu_cs_entry state_ib;
1145 struct tu_cs_entry binning_state_ib;
1146
1147 struct tu_program_descriptor_linkage link[MESA_SHADER_STAGES];
1148 } program;
1149
1150 struct
1151 {
1152 uint8_t bindings[MAX_VERTEX_ATTRIBS];
1153 uint16_t strides[MAX_VERTEX_ATTRIBS];
1154 uint16_t offsets[MAX_VERTEX_ATTRIBS];
1155 uint32_t count;
1156
1157 uint8_t binning_bindings[MAX_VERTEX_ATTRIBS];
1158 uint16_t binning_strides[MAX_VERTEX_ATTRIBS];
1159 uint16_t binning_offsets[MAX_VERTEX_ATTRIBS];
1160 uint32_t binning_count;
1161
1162 struct tu_cs_entry state_ib;
1163 struct tu_cs_entry binning_state_ib;
1164 } vi;
1165
1166 struct
1167 {
1168 enum pc_di_primtype primtype;
1169 bool primitive_restart;
1170 } ia;
1171
1172 struct
1173 {
1174 struct tu_cs_entry state_ib;
1175 } vp;
1176
1177 struct
1178 {
1179 uint32_t gras_su_cntl;
1180 struct tu_cs_entry state_ib;
1181 } rast;
1182
1183 struct
1184 {
1185 struct tu_cs_entry state_ib;
1186 } ds;
1187
1188 struct
1189 {
1190 struct tu_cs_entry state_ib;
1191 } blend;
1192
1193 struct
1194 {
1195 uint32_t local_size[3];
1196 } compute;
1197 };
1198
1199 void
1200 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport);
1201
1202 void
1203 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor);
1204
1205 void
1206 tu6_emit_gras_su_cntl(struct tu_cs *cs,
1207 uint32_t gras_su_cntl,
1208 float line_width);
1209
1210 void
1211 tu6_emit_depth_bias(struct tu_cs *cs,
1212 float constant_factor,
1213 float clamp,
1214 float slope_factor);
1215
1216 void
1217 tu6_emit_stencil_compare_mask(struct tu_cs *cs,
1218 uint32_t front,
1219 uint32_t back);
1220
1221 void
1222 tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back);
1223
1224 void
1225 tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back);
1226
1227 void
1228 tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4]);
1229
1230 struct tu_userdata_info *
1231 tu_lookup_user_sgpr(struct tu_pipeline *pipeline,
1232 gl_shader_stage stage,
1233 int idx);
1234
1235 struct tu_shader_variant *
1236 tu_get_shader(struct tu_pipeline *pipeline, gl_shader_stage stage);
1237
1238 struct tu_graphics_pipeline_create_info
1239 {
1240 bool use_rectlist;
1241 bool db_depth_clear;
1242 bool db_stencil_clear;
1243 bool db_depth_disable_expclear;
1244 bool db_stencil_disable_expclear;
1245 bool db_flush_depth_inplace;
1246 bool db_flush_stencil_inplace;
1247 bool db_resummarize;
1248 uint32_t custom_blend_mode;
1249 };
1250
1251 struct tu_native_format
1252 {
1253 int vtx; /* VFMTn_xxx or -1 */
1254 int tex; /* TFMTn_xxx or -1 */
1255 int rb; /* RBn_xxx or -1 */
1256 int swap; /* enum a3xx_color_swap */
1257 bool present; /* internal only; always true to external users */
1258 };
1259
1260 const struct tu_native_format *
1261 tu6_get_native_format(VkFormat format);
1262
1263 void
1264 tu_pack_clear_value(const VkClearValue *val,
1265 VkFormat format,
1266 uint32_t buf[4]);
1267
1268 void
1269 tu_2d_clear_color(const VkClearColorValue *val, VkFormat format, uint32_t buf[4]);
1270
1271 void
1272 tu_2d_clear_zs(const VkClearDepthStencilValue *val, VkFormat format, uint32_t buf[4]);
1273
1274 enum a6xx_2d_ifmt tu6_fmt_to_ifmt(enum a6xx_format fmt);
1275 enum a6xx_depth_format tu6_pipe2depth(VkFormat format);
1276
1277 struct tu_image_level
1278 {
1279 VkDeviceSize offset;
1280 VkDeviceSize size;
1281 uint32_t pitch;
1282 };
1283
1284 struct tu_image
1285 {
1286 VkImageType type;
1287 /* The original VkFormat provided by the client. This may not match any
1288 * of the actual surface formats.
1289 */
1290 VkFormat vk_format;
1291 VkImageAspectFlags aspects;
1292 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1293 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1294 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1295 VkExtent3D extent;
1296 uint32_t level_count;
1297 uint32_t layer_count;
1298 VkSampleCountFlagBits samples;
1299
1300
1301 uint32_t alignment;
1302
1303 struct fdl_layout layout;
1304
1305 unsigned queue_family_mask;
1306 bool exclusive;
1307 bool shareable;
1308
1309 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1310 VkDeviceMemory owned_memory;
1311
1312 /* Set when bound */
1313 struct tu_bo *bo;
1314 VkDeviceSize bo_offset;
1315 };
1316
1317 unsigned
1318 tu_image_queue_family_mask(const struct tu_image *image,
1319 uint32_t family,
1320 uint32_t queue_family);
1321
1322 static inline uint32_t
1323 tu_get_layerCount(const struct tu_image *image,
1324 const VkImageSubresourceRange *range)
1325 {
1326 return range->layerCount == VK_REMAINING_ARRAY_LAYERS
1327 ? image->layer_count - range->baseArrayLayer
1328 : range->layerCount;
1329 }
1330
1331 static inline uint32_t
1332 tu_get_levelCount(const struct tu_image *image,
1333 const VkImageSubresourceRange *range)
1334 {
1335 return range->levelCount == VK_REMAINING_MIP_LEVELS
1336 ? image->level_count - range->baseMipLevel
1337 : range->levelCount;
1338 }
1339
1340 static inline VkDeviceSize
1341 tu_layer_size(struct tu_image *image, int level)
1342 {
1343 return fdl_layer_stride(&image->layout, level);
1344 }
1345
1346 static inline uint32_t
1347 tu_image_stride(struct tu_image *image, int level)
1348 {
1349 return image->layout.slices[level].pitch * image->layout.cpp;
1350 }
1351
1352 static inline uint64_t
1353 tu_image_base(struct tu_image *image, int level, int layer)
1354 {
1355 return image->bo->iova + image->bo_offset +
1356 fdl_surface_offset(&image->layout, level, layer);
1357 }
1358
1359 #define tu_image_base_ref(image, level, layer) \
1360 .bo = image->bo, \
1361 .bo_offset = (image->bo_offset + fdl_surface_offset(&image->layout, \
1362 level, layer))
1363
1364 #define tu_image_view_base_ref(iview) \
1365 tu_image_base_ref(iview->image, iview->base_mip, iview->base_layer)
1366
1367 static inline VkDeviceSize
1368 tu_image_ubwc_size(struct tu_image *image, int level)
1369 {
1370 return image->layout.ubwc_layer_size;
1371 }
1372
1373 static inline uint32_t
1374 tu_image_ubwc_pitch(struct tu_image *image, int level)
1375 {
1376 return image->layout.ubwc_slices[level].pitch;
1377 }
1378
1379 static inline uint64_t
1380 tu_image_ubwc_surface_offset(struct tu_image *image, int level, int layer)
1381 {
1382 return image->layout.ubwc_slices[level].offset +
1383 layer * tu_image_ubwc_size(image, level);
1384 }
1385
1386 static inline uint64_t
1387 tu_image_ubwc_base(struct tu_image *image, int level, int layer)
1388 {
1389 return image->bo->iova + image->bo_offset +
1390 tu_image_ubwc_surface_offset(image, level, layer);
1391 }
1392
1393 #define tu_image_ubwc_base_ref(image, level, layer) \
1394 .bo = image->bo, \
1395 .bo_offset = (image->bo_offset + tu_image_ubwc_surface_offset(image, \
1396 level, layer))
1397
1398 #define tu_image_view_ubwc_base_ref(iview) \
1399 tu_image_ubwc_base_ref(iview->image, iview->base_mip, iview->base_layer)
1400
1401 enum a6xx_tile_mode
1402 tu6_get_image_tile_mode(struct tu_image *image, int level);
1403 enum a3xx_msaa_samples
1404 tu_msaa_samples(uint32_t samples);
1405
1406 struct tu_image_view
1407 {
1408 struct tu_image *image; /**< VkImageViewCreateInfo::image */
1409
1410 VkImageViewType type;
1411 VkImageAspectFlags aspect_mask;
1412 VkFormat vk_format;
1413 uint32_t base_layer;
1414 uint32_t layer_count;
1415 uint32_t base_mip;
1416 uint32_t level_count;
1417 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1418
1419 uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
1420
1421 /* Descriptor for use as a storage image as opposed to a sampled image.
1422 * This has a few differences for cube maps (e.g. type).
1423 */
1424 uint32_t storage_descriptor[A6XX_TEX_CONST_DWORDS];
1425 };
1426
1427 struct tu_sampler
1428 {
1429 uint32_t state[A6XX_TEX_SAMP_DWORDS];
1430
1431 bool needs_border;
1432 VkBorderColor border;
1433 };
1434
1435 VkResult
1436 tu_image_create(VkDevice _device,
1437 const VkImageCreateInfo *pCreateInfo,
1438 const VkAllocationCallbacks *alloc,
1439 VkImage *pImage,
1440 uint64_t modifier);
1441
1442 VkResult
1443 tu_image_from_gralloc(VkDevice device_h,
1444 const VkImageCreateInfo *base_info,
1445 const VkNativeBufferANDROID *gralloc_info,
1446 const VkAllocationCallbacks *alloc,
1447 VkImage *out_image_h);
1448
1449 void
1450 tu_image_view_init(struct tu_image_view *view,
1451 struct tu_device *device,
1452 const VkImageViewCreateInfo *pCreateInfo);
1453
1454 struct tu_buffer_view
1455 {
1456 uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
1457
1458 struct tu_buffer *buffer;
1459 };
1460 void
1461 tu_buffer_view_init(struct tu_buffer_view *view,
1462 struct tu_device *device,
1463 const VkBufferViewCreateInfo *pCreateInfo);
1464
1465 static inline struct VkExtent3D
1466 tu_sanitize_image_extent(const VkImageType imageType,
1467 const struct VkExtent3D imageExtent)
1468 {
1469 switch (imageType) {
1470 case VK_IMAGE_TYPE_1D:
1471 return (VkExtent3D) { imageExtent.width, 1, 1 };
1472 case VK_IMAGE_TYPE_2D:
1473 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1474 case VK_IMAGE_TYPE_3D:
1475 return imageExtent;
1476 default:
1477 unreachable("invalid image type");
1478 }
1479 }
1480
1481 static inline struct VkOffset3D
1482 tu_sanitize_image_offset(const VkImageType imageType,
1483 const struct VkOffset3D imageOffset)
1484 {
1485 switch (imageType) {
1486 case VK_IMAGE_TYPE_1D:
1487 return (VkOffset3D) { imageOffset.x, 0, 0 };
1488 case VK_IMAGE_TYPE_2D:
1489 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1490 case VK_IMAGE_TYPE_3D:
1491 return imageOffset;
1492 default:
1493 unreachable("invalid image type");
1494 }
1495 }
1496
1497 struct tu_attachment_info
1498 {
1499 struct tu_image_view *attachment;
1500 };
1501
1502 struct tu_framebuffer
1503 {
1504 uint32_t width;
1505 uint32_t height;
1506 uint32_t layers;
1507
1508 uint32_t attachment_count;
1509 struct tu_attachment_info attachments[0];
1510 };
1511
1512 struct tu_subpass_attachment
1513 {
1514 uint32_t attachment;
1515 };
1516
1517 struct tu_subpass
1518 {
1519 uint32_t input_count;
1520 uint32_t color_count;
1521 struct tu_subpass_attachment *input_attachments;
1522 struct tu_subpass_attachment *color_attachments;
1523 struct tu_subpass_attachment *resolve_attachments;
1524 struct tu_subpass_attachment depth_stencil_attachment;
1525
1526 VkSampleCountFlagBits samples;
1527 };
1528
1529 struct tu_render_pass_attachment
1530 {
1531 VkFormat format;
1532 uint32_t cpp;
1533 VkAttachmentLoadOp load_op;
1534 VkAttachmentLoadOp stencil_load_op;
1535 VkAttachmentStoreOp store_op;
1536 VkAttachmentStoreOp stencil_store_op;
1537 int32_t gmem_offset;
1538 };
1539
1540 struct tu_render_pass
1541 {
1542 uint32_t attachment_count;
1543 uint32_t subpass_count;
1544 uint32_t gmem_pixels;
1545 struct tu_subpass_attachment *subpass_attachments;
1546 struct tu_render_pass_attachment *attachments;
1547 struct tu_subpass subpasses[0];
1548 };
1549
1550 VkResult
1551 tu_device_init_meta(struct tu_device *device);
1552 void
1553 tu_device_finish_meta(struct tu_device *device);
1554
1555 struct tu_query_pool
1556 {
1557 VkQueryType type;
1558 uint32_t stride;
1559 uint64_t size;
1560 uint32_t pipeline_statistics;
1561 struct tu_bo bo;
1562 };
1563
1564 struct tu_semaphore
1565 {
1566 uint32_t syncobj;
1567 uint32_t temp_syncobj;
1568 };
1569
1570 void
1571 tu_set_descriptor_set(struct tu_cmd_buffer *cmd_buffer,
1572 VkPipelineBindPoint bind_point,
1573 struct tu_descriptor_set *set,
1574 unsigned idx);
1575
1576 void
1577 tu_update_descriptor_sets(struct tu_device *device,
1578 struct tu_cmd_buffer *cmd_buffer,
1579 VkDescriptorSet overrideSet,
1580 uint32_t descriptorWriteCount,
1581 const VkWriteDescriptorSet *pDescriptorWrites,
1582 uint32_t descriptorCopyCount,
1583 const VkCopyDescriptorSet *pDescriptorCopies);
1584
1585 void
1586 tu_update_descriptor_set_with_template(
1587 struct tu_device *device,
1588 struct tu_cmd_buffer *cmd_buffer,
1589 struct tu_descriptor_set *set,
1590 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
1591 const void *pData);
1592
1593 void
1594 tu_meta_push_descriptor_set(struct tu_cmd_buffer *cmd_buffer,
1595 VkPipelineBindPoint pipelineBindPoint,
1596 VkPipelineLayout _layout,
1597 uint32_t set,
1598 uint32_t descriptorWriteCount,
1599 const VkWriteDescriptorSet *pDescriptorWrites);
1600
1601 int
1602 tu_drm_get_gpu_id(const struct tu_physical_device *dev, uint32_t *id);
1603
1604 int
1605 tu_drm_get_gmem_size(const struct tu_physical_device *dev, uint32_t *size);
1606
1607 int
1608 tu_drm_submitqueue_new(const struct tu_device *dev,
1609 int priority,
1610 uint32_t *queue_id);
1611
1612 void
1613 tu_drm_submitqueue_close(const struct tu_device *dev, uint32_t queue_id);
1614
1615 uint32_t
1616 tu_gem_new(const struct tu_device *dev, uint64_t size, uint32_t flags);
1617 uint32_t
1618 tu_gem_import_dmabuf(const struct tu_device *dev,
1619 int prime_fd,
1620 uint64_t size);
1621 int
1622 tu_gem_export_dmabuf(const struct tu_device *dev, uint32_t gem_handle);
1623 void
1624 tu_gem_close(const struct tu_device *dev, uint32_t gem_handle);
1625 uint64_t
1626 tu_gem_info_offset(const struct tu_device *dev, uint32_t gem_handle);
1627 uint64_t
1628 tu_gem_info_iova(const struct tu_device *dev, uint32_t gem_handle);
1629
1630 #define TU_DEFINE_HANDLE_CASTS(__tu_type, __VkType) \
1631 \
1632 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1633 { \
1634 return (struct __tu_type *) _handle; \
1635 } \
1636 \
1637 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1638 { \
1639 return (__VkType) _obj; \
1640 }
1641
1642 #define TU_DEFINE_NONDISP_HANDLE_CASTS(__tu_type, __VkType) \
1643 \
1644 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1645 { \
1646 return (struct __tu_type *) (uintptr_t) _handle; \
1647 } \
1648 \
1649 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1650 { \
1651 return (__VkType)(uintptr_t) _obj; \
1652 }
1653
1654 #define TU_FROM_HANDLE(__tu_type, __name, __handle) \
1655 struct __tu_type *__name = __tu_type##_from_handle(__handle)
1656
1657 TU_DEFINE_HANDLE_CASTS(tu_cmd_buffer, VkCommandBuffer)
1658 TU_DEFINE_HANDLE_CASTS(tu_device, VkDevice)
1659 TU_DEFINE_HANDLE_CASTS(tu_instance, VkInstance)
1660 TU_DEFINE_HANDLE_CASTS(tu_physical_device, VkPhysicalDevice)
1661 TU_DEFINE_HANDLE_CASTS(tu_queue, VkQueue)
1662
1663 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_cmd_pool, VkCommandPool)
1664 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer, VkBuffer)
1665 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer_view, VkBufferView)
1666 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_pool, VkDescriptorPool)
1667 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set, VkDescriptorSet)
1668 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set_layout,
1669 VkDescriptorSetLayout)
1670 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_update_template,
1671 VkDescriptorUpdateTemplate)
1672 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_device_memory, VkDeviceMemory)
1673 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_fence, VkFence)
1674 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_event, VkEvent)
1675 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_framebuffer, VkFramebuffer)
1676 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image, VkImage)
1677 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image_view, VkImageView);
1678 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_cache, VkPipelineCache)
1679 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline, VkPipeline)
1680 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_layout, VkPipelineLayout)
1681 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_query_pool, VkQueryPool)
1682 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_render_pass, VkRenderPass)
1683 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_sampler, VkSampler)
1684 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_shader_module, VkShaderModule)
1685 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_semaphore, VkSemaphore)
1686
1687 #endif /* TU_PRIVATE_H */