turnip: add tu_device pointer to tu_cs
[mesa.git] / src / freedreno / vulkan / tu_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #ifndef TU_PRIVATE_H
29 #define TU_PRIVATE_H
30
31 #include <assert.h>
32 #include <pthread.h>
33 #include <stdbool.h>
34 #include <stdint.h>
35 #include <stdio.h>
36 #include <stdlib.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <memcheck.h>
40 #include <valgrind.h>
41 #define VG(x) x
42 #else
43 #define VG(x) ((void)0)
44 #endif
45
46 #include "c11/threads.h"
47 #include "main/macros.h"
48 #include "util/list.h"
49 #include "util/macros.h"
50 #include "vk_alloc.h"
51 #include "vk_debug_report.h"
52 #include "wsi_common.h"
53
54 #include "drm-uapi/msm_drm.h"
55 #include "ir3/ir3_compiler.h"
56 #include "ir3/ir3_shader.h"
57
58 #include "adreno_common.xml.h"
59 #include "adreno_pm4.xml.h"
60 #include "a6xx.xml.h"
61 #include "fdl/freedreno_layout.h"
62
63 #include "tu_descriptor_set.h"
64 #include "tu_extensions.h"
65
66 /* Pre-declarations needed for WSI entrypoints */
67 struct wl_surface;
68 struct wl_display;
69 typedef struct xcb_connection_t xcb_connection_t;
70 typedef uint32_t xcb_visualid_t;
71 typedef uint32_t xcb_window_t;
72
73 #include <vulkan/vk_android_native_buffer.h>
74 #include <vulkan/vk_icd.h>
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77
78 #include "tu_entrypoints.h"
79
80 #define MAX_VBS 32
81 #define MAX_VERTEX_ATTRIBS 32
82 #define MAX_RTS 8
83 #define MAX_VSC_PIPES 32
84 #define MAX_VIEWPORTS 1
85 #define MAX_SCISSORS 16
86 #define MAX_DISCARD_RECTANGLES 4
87 #define MAX_PUSH_CONSTANTS_SIZE 128
88 #define MAX_PUSH_DESCRIPTORS 32
89 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
90 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
91 #define MAX_DYNAMIC_BUFFERS \
92 (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
93 #define MAX_SAMPLES_LOG2 4
94 #define NUM_META_FS_KEYS 13
95 #define TU_MAX_DRM_DEVICES 8
96 #define MAX_VIEWS 8
97 /* The Qualcomm driver exposes 0x20000058 */
98 #define MAX_STORAGE_BUFFER_RANGE 0x20000000
99
100 #define NUM_DEPTH_CLEAR_PIPELINES 3
101
102 /*
103 * This is the point we switch from using CP to compute shader
104 * for certain buffer operations.
105 */
106 #define TU_BUFFER_OPS_CS_THRESHOLD 4096
107
108 #define A6XX_TEX_CONST_DWORDS 16
109 #define A6XX_TEX_SAMP_DWORDS 4
110
111 enum tu_mem_heap
112 {
113 TU_MEM_HEAP_VRAM,
114 TU_MEM_HEAP_VRAM_CPU_ACCESS,
115 TU_MEM_HEAP_GTT,
116 TU_MEM_HEAP_COUNT
117 };
118
119 enum tu_mem_type
120 {
121 TU_MEM_TYPE_VRAM,
122 TU_MEM_TYPE_GTT_WRITE_COMBINE,
123 TU_MEM_TYPE_VRAM_CPU_ACCESS,
124 TU_MEM_TYPE_GTT_CACHED,
125 TU_MEM_TYPE_COUNT
126 };
127
128 #define tu_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
129
130 static inline uint32_t
131 align_u32(uint32_t v, uint32_t a)
132 {
133 assert(a != 0 && a == (a & -a));
134 return (v + a - 1) & ~(a - 1);
135 }
136
137 static inline uint32_t
138 align_u32_npot(uint32_t v, uint32_t a)
139 {
140 return (v + a - 1) / a * a;
141 }
142
143 static inline uint64_t
144 align_u64(uint64_t v, uint64_t a)
145 {
146 assert(a != 0 && a == (a & -a));
147 return (v + a - 1) & ~(a - 1);
148 }
149
150 static inline int32_t
151 align_i32(int32_t v, int32_t a)
152 {
153 assert(a != 0 && a == (a & -a));
154 return (v + a - 1) & ~(a - 1);
155 }
156
157 /** Alignment must be a power of 2. */
158 static inline bool
159 tu_is_aligned(uintmax_t n, uintmax_t a)
160 {
161 assert(a == (a & -a));
162 return (n & (a - 1)) == 0;
163 }
164
165 static inline uint32_t
166 round_up_u32(uint32_t v, uint32_t a)
167 {
168 return (v + a - 1) / a;
169 }
170
171 static inline uint64_t
172 round_up_u64(uint64_t v, uint64_t a)
173 {
174 return (v + a - 1) / a;
175 }
176
177 static inline uint32_t
178 tu_minify(uint32_t n, uint32_t levels)
179 {
180 if (unlikely(n == 0))
181 return 0;
182 else
183 return MAX2(n >> levels, 1);
184 }
185 static inline float
186 tu_clamp_f(float f, float min, float max)
187 {
188 assert(min < max);
189
190 if (f > max)
191 return max;
192 else if (f < min)
193 return min;
194 else
195 return f;
196 }
197
198 static inline bool
199 tu_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
200 {
201 if (*inout_mask & clear_mask) {
202 *inout_mask &= ~clear_mask;
203 return true;
204 } else {
205 return false;
206 }
207 }
208
209 #define for_each_bit(b, dword) \
210 for (uint32_t __dword = (dword); \
211 (b) = __builtin_ffs(__dword) - 1, __dword; __dword &= ~(1 << (b)))
212
213 #define typed_memcpy(dest, src, count) \
214 ({ \
215 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
216 memcpy((dest), (src), (count) * sizeof(*(src))); \
217 })
218
219 #define COND(bool, val) ((bool) ? (val) : 0)
220
221 /* Whenever we generate an error, pass it through this function. Useful for
222 * debugging, where we can break on it. Only call at error site, not when
223 * propagating errors. Might be useful to plug in a stack trace here.
224 */
225
226 struct tu_instance;
227
228 VkResult
229 __vk_errorf(struct tu_instance *instance,
230 VkResult error,
231 const char *file,
232 int line,
233 const char *format,
234 ...);
235
236 #define vk_error(instance, error) \
237 __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
238 #define vk_errorf(instance, error, format, ...) \
239 __vk_errorf(instance, error, __FILE__, __LINE__, format, ##__VA_ARGS__);
240
241 void
242 __tu_finishme(const char *file, int line, const char *format, ...)
243 tu_printflike(3, 4);
244 void
245 tu_loge(const char *format, ...) tu_printflike(1, 2);
246 void
247 tu_loge_v(const char *format, va_list va);
248 void
249 tu_logi(const char *format, ...) tu_printflike(1, 2);
250 void
251 tu_logi_v(const char *format, va_list va);
252
253 /**
254 * Print a FINISHME message, including its source location.
255 */
256 #define tu_finishme(format, ...) \
257 do { \
258 static bool reported = false; \
259 if (!reported) { \
260 __tu_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
261 reported = true; \
262 } \
263 } while (0)
264
265 /* A non-fatal assert. Useful for debugging. */
266 #ifdef DEBUG
267 #define tu_assert(x) \
268 ({ \
269 if (unlikely(!(x))) \
270 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
271 })
272 #else
273 #define tu_assert(x)
274 #endif
275
276 /* Suppress -Wunused in stub functions */
277 #define tu_use_args(...) __tu_use_args(0, ##__VA_ARGS__)
278 static inline void
279 __tu_use_args(int ignore, ...)
280 {
281 }
282
283 #define tu_stub() \
284 do { \
285 tu_finishme("stub %s", __func__); \
286 } while (0)
287
288 void *
289 tu_lookup_entrypoint_unchecked(const char *name);
290 void *
291 tu_lookup_entrypoint_checked(
292 const char *name,
293 uint32_t core_version,
294 const struct tu_instance_extension_table *instance,
295 const struct tu_device_extension_table *device);
296
297 struct tu_physical_device
298 {
299 VK_LOADER_DATA _loader_data;
300
301 struct tu_instance *instance;
302
303 char path[20];
304 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
305 uint8_t driver_uuid[VK_UUID_SIZE];
306 uint8_t device_uuid[VK_UUID_SIZE];
307 uint8_t cache_uuid[VK_UUID_SIZE];
308
309 struct wsi_device wsi_device;
310
311 int local_fd;
312 int master_fd;
313
314 unsigned gpu_id;
315 uint32_t gmem_size;
316 uint32_t tile_align_w;
317 uint32_t tile_align_h;
318
319 struct {
320 uint32_t RB_UNKNOWN_8E04_blit; /* for CP_BLIT's */
321 uint32_t RB_CCU_CNTL_gmem; /* for GMEM */
322 uint32_t PC_UNKNOWN_9805;
323 uint32_t SP_UNKNOWN_A0F8;
324 } magic;
325
326 /* This is the drivers on-disk cache used as a fallback as opposed to
327 * the pipeline cache defined by apps.
328 */
329 struct disk_cache *disk_cache;
330
331 struct tu_device_extension_table supported_extensions;
332 };
333
334 enum tu_debug_flags
335 {
336 TU_DEBUG_STARTUP = 1 << 0,
337 TU_DEBUG_NIR = 1 << 1,
338 TU_DEBUG_IR3 = 1 << 2,
339 TU_DEBUG_NOBIN = 1 << 3,
340 TU_DEBUG_SYSMEM = 1 << 4,
341 TU_DEBUG_FORCEBIN = 1 << 5,
342 };
343
344 struct tu_instance
345 {
346 VK_LOADER_DATA _loader_data;
347
348 VkAllocationCallbacks alloc;
349
350 uint32_t api_version;
351 int physical_device_count;
352 struct tu_physical_device physical_devices[TU_MAX_DRM_DEVICES];
353
354 enum tu_debug_flags debug_flags;
355
356 struct vk_debug_report_instance debug_report_callbacks;
357
358 struct tu_instance_extension_table enabled_extensions;
359 };
360
361 VkResult
362 tu_wsi_init(struct tu_physical_device *physical_device);
363 void
364 tu_wsi_finish(struct tu_physical_device *physical_device);
365
366 bool
367 tu_instance_extension_supported(const char *name);
368 uint32_t
369 tu_physical_device_api_version(struct tu_physical_device *dev);
370 bool
371 tu_physical_device_extension_supported(struct tu_physical_device *dev,
372 const char *name);
373
374 struct cache_entry;
375
376 struct tu_pipeline_cache
377 {
378 struct tu_device *device;
379 pthread_mutex_t mutex;
380
381 uint32_t total_size;
382 uint32_t table_size;
383 uint32_t kernel_count;
384 struct cache_entry **hash_table;
385 bool modified;
386
387 VkAllocationCallbacks alloc;
388 };
389
390 struct tu_pipeline_key
391 {
392 };
393
394 void
395 tu_pipeline_cache_init(struct tu_pipeline_cache *cache,
396 struct tu_device *device);
397 void
398 tu_pipeline_cache_finish(struct tu_pipeline_cache *cache);
399 void
400 tu_pipeline_cache_load(struct tu_pipeline_cache *cache,
401 const void *data,
402 size_t size);
403
404 struct tu_shader_variant;
405
406 bool
407 tu_create_shader_variants_from_pipeline_cache(
408 struct tu_device *device,
409 struct tu_pipeline_cache *cache,
410 const unsigned char *sha1,
411 struct tu_shader_variant **variants);
412
413 void
414 tu_pipeline_cache_insert_shaders(struct tu_device *device,
415 struct tu_pipeline_cache *cache,
416 const unsigned char *sha1,
417 struct tu_shader_variant **variants,
418 const void *const *codes,
419 const unsigned *code_sizes);
420
421 struct tu_meta_state
422 {
423 VkAllocationCallbacks alloc;
424
425 struct tu_pipeline_cache cache;
426 };
427
428 /* queue types */
429 #define TU_QUEUE_GENERAL 0
430
431 #define TU_MAX_QUEUE_FAMILIES 1
432
433 struct tu_fence
434 {
435 struct wsi_fence *fence_wsi;
436 bool signaled;
437 int fd;
438 };
439
440 void
441 tu_fence_init(struct tu_fence *fence, bool signaled);
442 void
443 tu_fence_finish(struct tu_fence *fence);
444 void
445 tu_fence_update_fd(struct tu_fence *fence, int fd);
446 void
447 tu_fence_copy(struct tu_fence *fence, const struct tu_fence *src);
448 void
449 tu_fence_signal(struct tu_fence *fence);
450 void
451 tu_fence_wait_idle(struct tu_fence *fence);
452
453 struct tu_queue
454 {
455 VK_LOADER_DATA _loader_data;
456 struct tu_device *device;
457 uint32_t queue_family_index;
458 int queue_idx;
459 VkDeviceQueueCreateFlags flags;
460
461 uint32_t msm_queue_id;
462 struct tu_fence submit_fence;
463 };
464
465 struct tu_bo
466 {
467 uint32_t gem_handle;
468 uint64_t size;
469 uint64_t iova;
470 void *map;
471 };
472
473 struct tu_device
474 {
475 VK_LOADER_DATA _loader_data;
476
477 VkAllocationCallbacks alloc;
478
479 struct tu_instance *instance;
480
481 struct tu_meta_state meta_state;
482
483 struct tu_queue *queues[TU_MAX_QUEUE_FAMILIES];
484 int queue_count[TU_MAX_QUEUE_FAMILIES];
485
486 struct tu_physical_device *physical_device;
487
488 struct ir3_compiler *compiler;
489
490 /* Backup in-memory cache to be used if the app doesn't provide one */
491 struct tu_pipeline_cache *mem_cache;
492
493 struct tu_bo vsc_data;
494 struct tu_bo vsc_data2;
495 uint32_t vsc_data_pitch;
496 uint32_t vsc_data2_pitch;
497
498 struct list_head shader_slabs;
499 mtx_t shader_slab_mutex;
500
501 struct tu_device_extension_table enabled_extensions;
502 };
503
504 VkResult
505 tu_bo_init_new(struct tu_device *dev, struct tu_bo *bo, uint64_t size);
506 VkResult
507 tu_bo_init_dmabuf(struct tu_device *dev,
508 struct tu_bo *bo,
509 uint64_t size,
510 int fd);
511 int
512 tu_bo_export_dmabuf(struct tu_device *dev, struct tu_bo *bo);
513 void
514 tu_bo_finish(struct tu_device *dev, struct tu_bo *bo);
515 VkResult
516 tu_bo_map(struct tu_device *dev, struct tu_bo *bo);
517
518 struct tu_cs_entry
519 {
520 /* No ownership */
521 const struct tu_bo *bo;
522
523 uint32_t size;
524 uint32_t offset;
525 };
526
527 struct ts_cs_memory {
528 uint32_t *map;
529 uint64_t iova;
530 };
531
532 enum tu_cs_mode
533 {
534
535 /*
536 * A command stream in TU_CS_MODE_GROW mode grows automatically whenever it
537 * is full. tu_cs_begin must be called before command packet emission and
538 * tu_cs_end must be called after.
539 *
540 * This mode may create multiple entries internally. The entries must be
541 * submitted together.
542 */
543 TU_CS_MODE_GROW,
544
545 /*
546 * A command stream in TU_CS_MODE_EXTERNAL mode wraps an external,
547 * fixed-size buffer. tu_cs_begin and tu_cs_end are optional and have no
548 * effect on it.
549 *
550 * This mode does not create any entry or any BO.
551 */
552 TU_CS_MODE_EXTERNAL,
553
554 /*
555 * A command stream in TU_CS_MODE_SUB_STREAM mode does not support direct
556 * command packet emission. tu_cs_begin_sub_stream must be called to get a
557 * sub-stream to emit comamnd packets to. When done with the sub-stream,
558 * tu_cs_end_sub_stream must be called.
559 *
560 * This mode does not create any entry internally.
561 */
562 TU_CS_MODE_SUB_STREAM,
563 };
564
565 struct tu_cs
566 {
567 uint32_t *start;
568 uint32_t *cur;
569 uint32_t *reserved_end;
570 uint32_t *end;
571
572 struct tu_device *device;
573 enum tu_cs_mode mode;
574 uint32_t next_bo_size;
575
576 struct tu_cs_entry *entries;
577 uint32_t entry_count;
578 uint32_t entry_capacity;
579
580 struct tu_bo **bos;
581 uint32_t bo_count;
582 uint32_t bo_capacity;
583 };
584
585 struct tu_device_memory
586 {
587 struct tu_bo bo;
588 VkDeviceSize size;
589
590 /* for dedicated allocations */
591 struct tu_image *image;
592 struct tu_buffer *buffer;
593
594 uint32_t type_index;
595 void *map;
596 void *user_ptr;
597 };
598
599 struct tu_descriptor_range
600 {
601 uint64_t va;
602 uint32_t size;
603 };
604
605 struct tu_descriptor_set
606 {
607 const struct tu_descriptor_set_layout *layout;
608 uint32_t size;
609
610 uint64_t va;
611 uint32_t *mapped_ptr;
612 struct tu_descriptor_range *dynamic_descriptors;
613
614 struct tu_bo *descriptors[0];
615 };
616
617 struct tu_push_descriptor_set
618 {
619 struct tu_descriptor_set set;
620 uint32_t capacity;
621 };
622
623 struct tu_descriptor_pool_entry
624 {
625 uint32_t offset;
626 uint32_t size;
627 struct tu_descriptor_set *set;
628 };
629
630 struct tu_descriptor_pool
631 {
632 struct tu_bo bo;
633 uint64_t current_offset;
634 uint64_t size;
635
636 uint8_t *host_memory_base;
637 uint8_t *host_memory_ptr;
638 uint8_t *host_memory_end;
639
640 uint32_t entry_count;
641 uint32_t max_entry_count;
642 struct tu_descriptor_pool_entry entries[0];
643 };
644
645 struct tu_descriptor_update_template_entry
646 {
647 VkDescriptorType descriptor_type;
648
649 /* The number of descriptors to update */
650 uint32_t descriptor_count;
651
652 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array
653 */
654 uint32_t dst_offset;
655
656 /* In dwords. Not valid/used for dynamic descriptors */
657 uint32_t dst_stride;
658
659 uint32_t buffer_offset;
660
661 /* Only valid for combined image samplers and samplers */
662 uint16_t has_sampler;
663
664 /* In bytes */
665 size_t src_offset;
666 size_t src_stride;
667
668 /* For push descriptors */
669 const uint32_t *immutable_samplers;
670 };
671
672 struct tu_descriptor_update_template
673 {
674 uint32_t entry_count;
675 VkPipelineBindPoint bind_point;
676 struct tu_descriptor_update_template_entry entry[0];
677 };
678
679 struct tu_buffer
680 {
681 VkDeviceSize size;
682
683 VkBufferUsageFlags usage;
684 VkBufferCreateFlags flags;
685
686 struct tu_bo *bo;
687 VkDeviceSize bo_offset;
688 };
689
690 static inline uint64_t
691 tu_buffer_iova(struct tu_buffer *buffer)
692 {
693 return buffer->bo->iova + buffer->bo_offset;
694 }
695
696 enum tu_dynamic_state_bits
697 {
698 TU_DYNAMIC_VIEWPORT = 1 << 0,
699 TU_DYNAMIC_SCISSOR = 1 << 1,
700 TU_DYNAMIC_LINE_WIDTH = 1 << 2,
701 TU_DYNAMIC_DEPTH_BIAS = 1 << 3,
702 TU_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
703 TU_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
704 TU_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
705 TU_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
706 TU_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
707 TU_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
708 TU_DYNAMIC_ALL = (1 << 10) - 1,
709 };
710
711 struct tu_vertex_binding
712 {
713 struct tu_buffer *buffer;
714 VkDeviceSize offset;
715 };
716
717 struct tu_viewport_state
718 {
719 uint32_t count;
720 VkViewport viewports[MAX_VIEWPORTS];
721 };
722
723 struct tu_scissor_state
724 {
725 uint32_t count;
726 VkRect2D scissors[MAX_SCISSORS];
727 };
728
729 struct tu_discard_rectangle_state
730 {
731 uint32_t count;
732 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
733 };
734
735 struct tu_dynamic_state
736 {
737 /**
738 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
739 * Defines the set of saved dynamic state.
740 */
741 uint32_t mask;
742
743 struct tu_viewport_state viewport;
744
745 struct tu_scissor_state scissor;
746
747 float line_width;
748
749 struct
750 {
751 float bias;
752 float clamp;
753 float slope;
754 } depth_bias;
755
756 float blend_constants[4];
757
758 struct
759 {
760 float min;
761 float max;
762 } depth_bounds;
763
764 struct
765 {
766 uint32_t front;
767 uint32_t back;
768 } stencil_compare_mask;
769
770 struct
771 {
772 uint32_t front;
773 uint32_t back;
774 } stencil_write_mask;
775
776 struct
777 {
778 uint32_t front;
779 uint32_t back;
780 } stencil_reference;
781
782 struct tu_discard_rectangle_state discard_rectangle;
783 };
784
785 extern const struct tu_dynamic_state default_dynamic_state;
786
787 const char *
788 tu_get_debug_option_name(int id);
789
790 const char *
791 tu_get_perftest_option_name(int id);
792
793 struct tu_descriptor_state
794 {
795 struct tu_descriptor_set *sets[MAX_SETS];
796 uint32_t valid;
797 struct tu_push_descriptor_set push_set;
798 bool push_dirty;
799 uint64_t dynamic_buffers[MAX_DYNAMIC_BUFFERS];
800 };
801
802 struct tu_tile
803 {
804 uint8_t pipe;
805 uint8_t slot;
806 VkOffset2D begin;
807 VkOffset2D end;
808 };
809
810 struct tu_tiling_config
811 {
812 VkRect2D render_area;
813
814 /* position and size of the first tile */
815 VkRect2D tile0;
816 /* number of tiles */
817 VkExtent2D tile_count;
818
819 /* size of the first VSC pipe */
820 VkExtent2D pipe0;
821 /* number of VSC pipes */
822 VkExtent2D pipe_count;
823
824 /* pipe register values */
825 uint32_t pipe_config[MAX_VSC_PIPES];
826 uint32_t pipe_sizes[MAX_VSC_PIPES];
827
828 /* Whether sysmem rendering must be used */
829 bool force_sysmem;
830 };
831
832 enum tu_cmd_dirty_bits
833 {
834 TU_CMD_DIRTY_PIPELINE = 1 << 0,
835 TU_CMD_DIRTY_COMPUTE_PIPELINE = 1 << 1,
836 TU_CMD_DIRTY_VERTEX_BUFFERS = 1 << 2,
837 TU_CMD_DIRTY_DESCRIPTOR_SETS = 1 << 3,
838 TU_CMD_DIRTY_PUSH_CONSTANTS = 1 << 4,
839
840 TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 16,
841 TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 17,
842 TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 18,
843 TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 19,
844 };
845
846 struct tu_cmd_state
847 {
848 uint32_t dirty;
849
850 struct tu_pipeline *pipeline;
851 struct tu_pipeline *compute_pipeline;
852
853 /* Vertex buffers */
854 struct
855 {
856 struct tu_buffer *buffers[MAX_VBS];
857 VkDeviceSize offsets[MAX_VBS];
858 } vb;
859
860 struct tu_dynamic_state dynamic;
861
862 /* Index buffer */
863 struct tu_buffer *index_buffer;
864 uint64_t index_offset;
865 uint32_t index_type;
866 uint32_t max_index_count;
867 uint64_t index_va;
868
869 const struct tu_render_pass *pass;
870 const struct tu_subpass *subpass;
871 const struct tu_framebuffer *framebuffer;
872
873 struct tu_tiling_config tiling_config;
874
875 struct tu_cs_entry tile_load_ib;
876 struct tu_cs_entry tile_store_ib;
877 struct tu_cs_entry sysmem_clear_ib;
878 };
879
880 struct tu_cmd_pool
881 {
882 VkAllocationCallbacks alloc;
883 struct list_head cmd_buffers;
884 struct list_head free_cmd_buffers;
885 uint32_t queue_family_index;
886 };
887
888 struct tu_cmd_buffer_upload
889 {
890 uint8_t *map;
891 unsigned offset;
892 uint64_t size;
893 struct list_head list;
894 };
895
896 enum tu_cmd_buffer_status
897 {
898 TU_CMD_BUFFER_STATUS_INVALID,
899 TU_CMD_BUFFER_STATUS_INITIAL,
900 TU_CMD_BUFFER_STATUS_RECORDING,
901 TU_CMD_BUFFER_STATUS_EXECUTABLE,
902 TU_CMD_BUFFER_STATUS_PENDING,
903 };
904
905 struct tu_bo_list
906 {
907 uint32_t count;
908 uint32_t capacity;
909 struct drm_msm_gem_submit_bo *bo_infos;
910 };
911
912 #define TU_BO_LIST_FAILED (~0)
913
914 void
915 tu_bo_list_init(struct tu_bo_list *list);
916 void
917 tu_bo_list_destroy(struct tu_bo_list *list);
918 void
919 tu_bo_list_reset(struct tu_bo_list *list);
920 uint32_t
921 tu_bo_list_add(struct tu_bo_list *list,
922 const struct tu_bo *bo,
923 uint32_t flags);
924 VkResult
925 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other);
926
927 struct tu_cmd_buffer
928 {
929 VK_LOADER_DATA _loader_data;
930
931 struct tu_device *device;
932
933 struct tu_cmd_pool *pool;
934 struct list_head pool_link;
935
936 VkCommandBufferUsageFlags usage_flags;
937 VkCommandBufferLevel level;
938 enum tu_cmd_buffer_status status;
939
940 struct tu_cmd_state state;
941 struct tu_vertex_binding vertex_bindings[MAX_VBS];
942 uint32_t queue_family_index;
943
944 uint32_t push_constants[MAX_PUSH_CONSTANTS_SIZE / 4];
945 VkShaderStageFlags push_constant_stages;
946 struct tu_descriptor_set meta_push_descriptors;
947
948 struct tu_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
949
950 struct tu_cmd_buffer_upload upload;
951
952 VkResult record_result;
953
954 struct tu_bo_list bo_list;
955 struct tu_cs cs;
956 struct tu_cs draw_cs;
957 struct tu_cs draw_epilogue_cs;
958 struct tu_cs sub_cs;
959
960 uint16_t marker_reg;
961 uint32_t marker_seqno;
962
963 struct tu_bo scratch_bo;
964 uint32_t scratch_seqno;
965 #define VSC_OVERFLOW 0x8
966 #define VSC_SCRATCH 0x10
967
968 struct tu_bo vsc_data;
969 struct tu_bo vsc_data2;
970 uint32_t vsc_data_pitch;
971 uint32_t vsc_data2_pitch;
972 bool use_vsc_data;
973
974 bool wait_for_idle;
975 };
976
977 /* Temporary struct for tracking a register state to be written, used by
978 * a6xx-pack.h and tu_cs_emit_regs()
979 */
980 struct tu_reg_value {
981 uint32_t reg;
982 uint64_t value;
983 bool is_address;
984 struct tu_bo *bo;
985 bool bo_write;
986 uint32_t bo_offset;
987 uint32_t bo_shift;
988 };
989
990 unsigned
991 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
992 struct tu_cs *cs,
993 enum vgt_event_type event,
994 bool need_seqno);
995
996 bool
997 tu_get_memory_fd(struct tu_device *device,
998 struct tu_device_memory *memory,
999 int *pFD);
1000
1001 static inline struct tu_descriptor_state *
1002 tu_get_descriptors_state(struct tu_cmd_buffer *cmd_buffer,
1003 VkPipelineBindPoint bind_point)
1004 {
1005 return &cmd_buffer->descriptors[bind_point];
1006 }
1007
1008 /*
1009 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1010 *
1011 * Limitations: Can't call normal dispatch functions without binding or
1012 * rebinding
1013 * the compute pipeline.
1014 */
1015 void
1016 tu_unaligned_dispatch(struct tu_cmd_buffer *cmd_buffer,
1017 uint32_t x,
1018 uint32_t y,
1019 uint32_t z);
1020
1021 struct tu_event
1022 {
1023 struct tu_bo bo;
1024 };
1025
1026 struct tu_shader_module;
1027
1028 #define TU_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1029 #define TU_HASH_SHADER_SISCHED (1 << 1)
1030 #define TU_HASH_SHADER_UNSAFE_MATH (1 << 2)
1031 void
1032 tu_hash_shaders(unsigned char *hash,
1033 const VkPipelineShaderStageCreateInfo **stages,
1034 const struct tu_pipeline_layout *layout,
1035 const struct tu_pipeline_key *key,
1036 uint32_t flags);
1037
1038 static inline gl_shader_stage
1039 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1040 {
1041 assert(__builtin_popcount(vk_stage) == 1);
1042 return ffs(vk_stage) - 1;
1043 }
1044
1045 static inline VkShaderStageFlagBits
1046 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1047 {
1048 return (1 << mesa_stage);
1049 }
1050
1051 #define TU_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1052
1053 #define tu_foreach_stage(stage, stage_bits) \
1054 for (gl_shader_stage stage, \
1055 __tmp = (gl_shader_stage)((stage_bits) &TU_STAGE_MASK); \
1056 stage = __builtin_ffs(__tmp) - 1, __tmp; __tmp &= ~(1 << (stage)))
1057
1058 struct tu_shader_module
1059 {
1060 unsigned char sha1[20];
1061
1062 uint32_t code_size;
1063 const uint32_t *code[0];
1064 };
1065
1066 struct tu_shader_compile_options
1067 {
1068 struct ir3_shader_key key;
1069
1070 bool optimize;
1071 bool include_binning_pass;
1072 };
1073
1074 struct tu_descriptor_map
1075 {
1076 /* TODO: avoid fixed size array/justify the size */
1077 unsigned num; /* number of array entries */
1078 unsigned num_desc; /* Number of descriptors (sum of array_size[]) */
1079 int set[64];
1080 int binding[64];
1081 int value[64];
1082 int array_size[64];
1083 };
1084
1085 struct tu_shader
1086 {
1087 struct ir3_shader ir3_shader;
1088
1089 struct tu_descriptor_map texture_map;
1090 struct tu_descriptor_map sampler_map;
1091 struct tu_descriptor_map ubo_map;
1092 struct tu_descriptor_map ssbo_map;
1093 struct tu_descriptor_map image_map;
1094
1095 /* This may be true for vertex shaders. When true, variants[1] is the
1096 * binning variant and binning_binary is non-NULL.
1097 */
1098 bool has_binning_pass;
1099
1100 void *binary;
1101 void *binning_binary;
1102
1103 struct ir3_shader_variant variants[0];
1104 };
1105
1106 struct tu_shader *
1107 tu_shader_create(struct tu_device *dev,
1108 gl_shader_stage stage,
1109 const VkPipelineShaderStageCreateInfo *stage_info,
1110 struct tu_pipeline_layout *layout,
1111 const VkAllocationCallbacks *alloc);
1112
1113 void
1114 tu_shader_destroy(struct tu_device *dev,
1115 struct tu_shader *shader,
1116 const VkAllocationCallbacks *alloc);
1117
1118 void
1119 tu_shader_compile_options_init(
1120 struct tu_shader_compile_options *options,
1121 const VkGraphicsPipelineCreateInfo *pipeline_info);
1122
1123 VkResult
1124 tu_shader_compile(struct tu_device *dev,
1125 struct tu_shader *shader,
1126 const struct tu_shader *next_stage,
1127 const struct tu_shader_compile_options *options,
1128 const VkAllocationCallbacks *alloc);
1129
1130 struct tu_program_descriptor_linkage
1131 {
1132 struct ir3_ubo_analysis_state ubo_state;
1133 struct ir3_const_state const_state;
1134
1135 uint32_t constlen;
1136
1137 struct tu_descriptor_map texture_map;
1138 struct tu_descriptor_map sampler_map;
1139 struct tu_descriptor_map ubo_map;
1140 struct tu_descriptor_map ssbo_map;
1141 struct tu_descriptor_map image_map;
1142 };
1143
1144 struct tu_pipeline
1145 {
1146 struct tu_cs cs;
1147
1148 struct tu_dynamic_state dynamic_state;
1149
1150 struct tu_pipeline_layout *layout;
1151
1152 bool need_indirect_descriptor_sets;
1153 VkShaderStageFlags active_stages;
1154
1155 struct
1156 {
1157 struct tu_bo binary_bo;
1158 struct tu_cs_entry state_ib;
1159 struct tu_cs_entry binning_state_ib;
1160
1161 struct tu_program_descriptor_linkage link[MESA_SHADER_STAGES];
1162 } program;
1163
1164 struct
1165 {
1166 uint8_t bindings[MAX_VERTEX_ATTRIBS];
1167 uint16_t strides[MAX_VERTEX_ATTRIBS];
1168 uint16_t offsets[MAX_VERTEX_ATTRIBS];
1169 uint32_t count;
1170
1171 uint8_t binning_bindings[MAX_VERTEX_ATTRIBS];
1172 uint16_t binning_strides[MAX_VERTEX_ATTRIBS];
1173 uint16_t binning_offsets[MAX_VERTEX_ATTRIBS];
1174 uint32_t binning_count;
1175
1176 struct tu_cs_entry state_ib;
1177 struct tu_cs_entry binning_state_ib;
1178 } vi;
1179
1180 struct
1181 {
1182 enum pc_di_primtype primtype;
1183 bool primitive_restart;
1184 } ia;
1185
1186 struct
1187 {
1188 struct tu_cs_entry state_ib;
1189 } vp;
1190
1191 struct
1192 {
1193 uint32_t gras_su_cntl;
1194 struct tu_cs_entry state_ib;
1195 } rast;
1196
1197 struct
1198 {
1199 struct tu_cs_entry state_ib;
1200 } ds;
1201
1202 struct
1203 {
1204 struct tu_cs_entry state_ib;
1205 } blend;
1206
1207 struct
1208 {
1209 uint32_t local_size[3];
1210 } compute;
1211 };
1212
1213 void
1214 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport);
1215
1216 void
1217 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor);
1218
1219 void
1220 tu6_emit_gras_su_cntl(struct tu_cs *cs,
1221 uint32_t gras_su_cntl,
1222 float line_width);
1223
1224 void
1225 tu6_emit_depth_bias(struct tu_cs *cs,
1226 float constant_factor,
1227 float clamp,
1228 float slope_factor);
1229
1230 void
1231 tu6_emit_stencil_compare_mask(struct tu_cs *cs,
1232 uint32_t front,
1233 uint32_t back);
1234
1235 void
1236 tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back);
1237
1238 void
1239 tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back);
1240
1241 void
1242 tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4]);
1243
1244 struct tu_userdata_info *
1245 tu_lookup_user_sgpr(struct tu_pipeline *pipeline,
1246 gl_shader_stage stage,
1247 int idx);
1248
1249 struct tu_shader_variant *
1250 tu_get_shader(struct tu_pipeline *pipeline, gl_shader_stage stage);
1251
1252 struct tu_graphics_pipeline_create_info
1253 {
1254 bool use_rectlist;
1255 bool db_depth_clear;
1256 bool db_stencil_clear;
1257 bool db_depth_disable_expclear;
1258 bool db_stencil_disable_expclear;
1259 bool db_flush_depth_inplace;
1260 bool db_flush_stencil_inplace;
1261 bool db_resummarize;
1262 uint32_t custom_blend_mode;
1263 };
1264
1265 struct tu_native_format
1266 {
1267 int vtx; /* VFMTn_xxx or -1 */
1268 int tex; /* TFMTn_xxx or -1 */
1269 int rb; /* RBn_xxx or -1 */
1270 int swap; /* enum a3xx_color_swap */
1271 bool present; /* internal only; always true to external users */
1272 };
1273
1274 const struct tu_native_format *
1275 tu6_get_native_format(VkFormat format);
1276
1277 void
1278 tu_pack_clear_value(const VkClearValue *val,
1279 VkFormat format,
1280 uint32_t buf[4]);
1281
1282 void
1283 tu_2d_clear_color(const VkClearColorValue *val, VkFormat format, uint32_t buf[4]);
1284
1285 void
1286 tu_2d_clear_zs(const VkClearDepthStencilValue *val, VkFormat format, uint32_t buf[4]);
1287
1288 enum a6xx_2d_ifmt tu6_fmt_to_ifmt(enum a6xx_format fmt);
1289 enum a6xx_depth_format tu6_pipe2depth(VkFormat format);
1290
1291 struct tu_image_level
1292 {
1293 VkDeviceSize offset;
1294 VkDeviceSize size;
1295 uint32_t pitch;
1296 };
1297
1298 struct tu_image
1299 {
1300 VkImageType type;
1301 /* The original VkFormat provided by the client. This may not match any
1302 * of the actual surface formats.
1303 */
1304 VkFormat vk_format;
1305 VkImageAspectFlags aspects;
1306 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1307 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1308 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1309 VkExtent3D extent;
1310 uint32_t level_count;
1311 uint32_t layer_count;
1312 VkSampleCountFlagBits samples;
1313
1314
1315 uint32_t alignment;
1316
1317 struct fdl_layout layout;
1318
1319 unsigned queue_family_mask;
1320 bool exclusive;
1321 bool shareable;
1322
1323 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1324 VkDeviceMemory owned_memory;
1325
1326 /* Set when bound */
1327 struct tu_bo *bo;
1328 VkDeviceSize bo_offset;
1329 };
1330
1331 unsigned
1332 tu_image_queue_family_mask(const struct tu_image *image,
1333 uint32_t family,
1334 uint32_t queue_family);
1335
1336 static inline uint32_t
1337 tu_get_layerCount(const struct tu_image *image,
1338 const VkImageSubresourceRange *range)
1339 {
1340 return range->layerCount == VK_REMAINING_ARRAY_LAYERS
1341 ? image->layer_count - range->baseArrayLayer
1342 : range->layerCount;
1343 }
1344
1345 static inline uint32_t
1346 tu_get_levelCount(const struct tu_image *image,
1347 const VkImageSubresourceRange *range)
1348 {
1349 return range->levelCount == VK_REMAINING_MIP_LEVELS
1350 ? image->level_count - range->baseMipLevel
1351 : range->levelCount;
1352 }
1353
1354 static inline VkDeviceSize
1355 tu_layer_size(struct tu_image *image, int level)
1356 {
1357 return fdl_layer_stride(&image->layout, level);
1358 }
1359
1360 static inline uint32_t
1361 tu_image_stride(struct tu_image *image, int level)
1362 {
1363 return image->layout.slices[level].pitch * image->layout.cpp;
1364 }
1365
1366 static inline uint64_t
1367 tu_image_base(struct tu_image *image, int level, int layer)
1368 {
1369 return image->bo->iova + image->bo_offset +
1370 fdl_surface_offset(&image->layout, level, layer);
1371 }
1372
1373 #define tu_image_base_ref(image, level, layer) \
1374 .bo = image->bo, \
1375 .bo_offset = (image->bo_offset + fdl_surface_offset(&image->layout, \
1376 level, layer))
1377
1378 #define tu_image_view_base_ref(iview) \
1379 tu_image_base_ref(iview->image, iview->base_mip, iview->base_layer)
1380
1381 static inline VkDeviceSize
1382 tu_image_ubwc_size(struct tu_image *image, int level)
1383 {
1384 return image->layout.ubwc_layer_size;
1385 }
1386
1387 static inline uint32_t
1388 tu_image_ubwc_pitch(struct tu_image *image, int level)
1389 {
1390 return image->layout.ubwc_slices[level].pitch;
1391 }
1392
1393 static inline uint64_t
1394 tu_image_ubwc_surface_offset(struct tu_image *image, int level, int layer)
1395 {
1396 return image->layout.ubwc_slices[level].offset +
1397 layer * tu_image_ubwc_size(image, level);
1398 }
1399
1400 static inline uint64_t
1401 tu_image_ubwc_base(struct tu_image *image, int level, int layer)
1402 {
1403 return image->bo->iova + image->bo_offset +
1404 tu_image_ubwc_surface_offset(image, level, layer);
1405 }
1406
1407 #define tu_image_ubwc_base_ref(image, level, layer) \
1408 .bo = image->bo, \
1409 .bo_offset = (image->bo_offset + tu_image_ubwc_surface_offset(image, \
1410 level, layer))
1411
1412 #define tu_image_view_ubwc_base_ref(iview) \
1413 tu_image_ubwc_base_ref(iview->image, iview->base_mip, iview->base_layer)
1414
1415 enum a6xx_tile_mode
1416 tu6_get_image_tile_mode(struct tu_image *image, int level);
1417 enum a3xx_msaa_samples
1418 tu_msaa_samples(uint32_t samples);
1419
1420 struct tu_image_view
1421 {
1422 struct tu_image *image; /**< VkImageViewCreateInfo::image */
1423
1424 VkImageViewType type;
1425 VkImageAspectFlags aspect_mask;
1426 VkFormat vk_format;
1427 uint32_t base_layer;
1428 uint32_t layer_count;
1429 uint32_t base_mip;
1430 uint32_t level_count;
1431 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1432
1433 uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
1434
1435 /* Descriptor for use as a storage image as opposed to a sampled image.
1436 * This has a few differences for cube maps (e.g. type).
1437 */
1438 uint32_t storage_descriptor[A6XX_TEX_CONST_DWORDS];
1439 };
1440
1441 struct tu_sampler
1442 {
1443 uint32_t state[A6XX_TEX_SAMP_DWORDS];
1444
1445 bool needs_border;
1446 VkBorderColor border;
1447 };
1448
1449 VkResult
1450 tu_image_create(VkDevice _device,
1451 const VkImageCreateInfo *pCreateInfo,
1452 const VkAllocationCallbacks *alloc,
1453 VkImage *pImage,
1454 uint64_t modifier);
1455
1456 VkResult
1457 tu_image_from_gralloc(VkDevice device_h,
1458 const VkImageCreateInfo *base_info,
1459 const VkNativeBufferANDROID *gralloc_info,
1460 const VkAllocationCallbacks *alloc,
1461 VkImage *out_image_h);
1462
1463 void
1464 tu_image_view_init(struct tu_image_view *view,
1465 struct tu_device *device,
1466 const VkImageViewCreateInfo *pCreateInfo);
1467
1468 struct tu_buffer_view
1469 {
1470 uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
1471
1472 struct tu_buffer *buffer;
1473 };
1474 void
1475 tu_buffer_view_init(struct tu_buffer_view *view,
1476 struct tu_device *device,
1477 const VkBufferViewCreateInfo *pCreateInfo);
1478
1479 static inline struct VkExtent3D
1480 tu_sanitize_image_extent(const VkImageType imageType,
1481 const struct VkExtent3D imageExtent)
1482 {
1483 switch (imageType) {
1484 case VK_IMAGE_TYPE_1D:
1485 return (VkExtent3D) { imageExtent.width, 1, 1 };
1486 case VK_IMAGE_TYPE_2D:
1487 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1488 case VK_IMAGE_TYPE_3D:
1489 return imageExtent;
1490 default:
1491 unreachable("invalid image type");
1492 }
1493 }
1494
1495 static inline struct VkOffset3D
1496 tu_sanitize_image_offset(const VkImageType imageType,
1497 const struct VkOffset3D imageOffset)
1498 {
1499 switch (imageType) {
1500 case VK_IMAGE_TYPE_1D:
1501 return (VkOffset3D) { imageOffset.x, 0, 0 };
1502 case VK_IMAGE_TYPE_2D:
1503 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1504 case VK_IMAGE_TYPE_3D:
1505 return imageOffset;
1506 default:
1507 unreachable("invalid image type");
1508 }
1509 }
1510
1511 struct tu_attachment_info
1512 {
1513 struct tu_image_view *attachment;
1514 };
1515
1516 struct tu_framebuffer
1517 {
1518 uint32_t width;
1519 uint32_t height;
1520 uint32_t layers;
1521
1522 uint32_t attachment_count;
1523 struct tu_attachment_info attachments[0];
1524 };
1525
1526 struct tu_subpass_attachment
1527 {
1528 uint32_t attachment;
1529 };
1530
1531 struct tu_subpass
1532 {
1533 uint32_t input_count;
1534 uint32_t color_count;
1535 struct tu_subpass_attachment *input_attachments;
1536 struct tu_subpass_attachment *color_attachments;
1537 struct tu_subpass_attachment *resolve_attachments;
1538 struct tu_subpass_attachment depth_stencil_attachment;
1539
1540 VkSampleCountFlagBits samples;
1541 };
1542
1543 struct tu_render_pass_attachment
1544 {
1545 VkFormat format;
1546 uint32_t cpp;
1547 VkAttachmentLoadOp load_op;
1548 VkAttachmentLoadOp stencil_load_op;
1549 VkAttachmentStoreOp store_op;
1550 VkAttachmentStoreOp stencil_store_op;
1551 int32_t gmem_offset;
1552 };
1553
1554 struct tu_render_pass
1555 {
1556 uint32_t attachment_count;
1557 uint32_t subpass_count;
1558 uint32_t gmem_pixels;
1559 struct tu_subpass_attachment *subpass_attachments;
1560 struct tu_render_pass_attachment *attachments;
1561 struct tu_subpass subpasses[0];
1562 };
1563
1564 VkResult
1565 tu_device_init_meta(struct tu_device *device);
1566 void
1567 tu_device_finish_meta(struct tu_device *device);
1568
1569 struct tu_query_pool
1570 {
1571 VkQueryType type;
1572 uint32_t stride;
1573 uint64_t size;
1574 uint32_t pipeline_statistics;
1575 struct tu_bo bo;
1576 };
1577
1578 struct tu_semaphore
1579 {
1580 uint32_t syncobj;
1581 uint32_t temp_syncobj;
1582 };
1583
1584 void
1585 tu_set_descriptor_set(struct tu_cmd_buffer *cmd_buffer,
1586 VkPipelineBindPoint bind_point,
1587 struct tu_descriptor_set *set,
1588 unsigned idx);
1589
1590 void
1591 tu_update_descriptor_sets(struct tu_device *device,
1592 struct tu_cmd_buffer *cmd_buffer,
1593 VkDescriptorSet overrideSet,
1594 uint32_t descriptorWriteCount,
1595 const VkWriteDescriptorSet *pDescriptorWrites,
1596 uint32_t descriptorCopyCount,
1597 const VkCopyDescriptorSet *pDescriptorCopies);
1598
1599 void
1600 tu_update_descriptor_set_with_template(
1601 struct tu_device *device,
1602 struct tu_cmd_buffer *cmd_buffer,
1603 struct tu_descriptor_set *set,
1604 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
1605 const void *pData);
1606
1607 void
1608 tu_meta_push_descriptor_set(struct tu_cmd_buffer *cmd_buffer,
1609 VkPipelineBindPoint pipelineBindPoint,
1610 VkPipelineLayout _layout,
1611 uint32_t set,
1612 uint32_t descriptorWriteCount,
1613 const VkWriteDescriptorSet *pDescriptorWrites);
1614
1615 int
1616 tu_drm_get_gpu_id(const struct tu_physical_device *dev, uint32_t *id);
1617
1618 int
1619 tu_drm_get_gmem_size(const struct tu_physical_device *dev, uint32_t *size);
1620
1621 int
1622 tu_drm_submitqueue_new(const struct tu_device *dev,
1623 int priority,
1624 uint32_t *queue_id);
1625
1626 void
1627 tu_drm_submitqueue_close(const struct tu_device *dev, uint32_t queue_id);
1628
1629 uint32_t
1630 tu_gem_new(const struct tu_device *dev, uint64_t size, uint32_t flags);
1631 uint32_t
1632 tu_gem_import_dmabuf(const struct tu_device *dev,
1633 int prime_fd,
1634 uint64_t size);
1635 int
1636 tu_gem_export_dmabuf(const struct tu_device *dev, uint32_t gem_handle);
1637 void
1638 tu_gem_close(const struct tu_device *dev, uint32_t gem_handle);
1639 uint64_t
1640 tu_gem_info_offset(const struct tu_device *dev, uint32_t gem_handle);
1641 uint64_t
1642 tu_gem_info_iova(const struct tu_device *dev, uint32_t gem_handle);
1643
1644
1645 void
1646 tu_clear_sysmem_attachment(struct tu_cmd_buffer *cmd,
1647 struct tu_cs *cs,
1648 uint32_t attachment,
1649 const VkClearValue *value,
1650 const VkClearRect *rect);
1651
1652 void
1653 tu_clear_gmem_attachment(struct tu_cmd_buffer *cmd,
1654 struct tu_cs *cs,
1655 uint32_t attachment,
1656 uint8_t component_mask,
1657 const VkClearValue *value);
1658
1659 #define TU_DEFINE_HANDLE_CASTS(__tu_type, __VkType) \
1660 \
1661 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1662 { \
1663 return (struct __tu_type *) _handle; \
1664 } \
1665 \
1666 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1667 { \
1668 return (__VkType) _obj; \
1669 }
1670
1671 #define TU_DEFINE_NONDISP_HANDLE_CASTS(__tu_type, __VkType) \
1672 \
1673 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1674 { \
1675 return (struct __tu_type *) (uintptr_t) _handle; \
1676 } \
1677 \
1678 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1679 { \
1680 return (__VkType)(uintptr_t) _obj; \
1681 }
1682
1683 #define TU_FROM_HANDLE(__tu_type, __name, __handle) \
1684 struct __tu_type *__name = __tu_type##_from_handle(__handle)
1685
1686 TU_DEFINE_HANDLE_CASTS(tu_cmd_buffer, VkCommandBuffer)
1687 TU_DEFINE_HANDLE_CASTS(tu_device, VkDevice)
1688 TU_DEFINE_HANDLE_CASTS(tu_instance, VkInstance)
1689 TU_DEFINE_HANDLE_CASTS(tu_physical_device, VkPhysicalDevice)
1690 TU_DEFINE_HANDLE_CASTS(tu_queue, VkQueue)
1691
1692 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_cmd_pool, VkCommandPool)
1693 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer, VkBuffer)
1694 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer_view, VkBufferView)
1695 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_pool, VkDescriptorPool)
1696 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set, VkDescriptorSet)
1697 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set_layout,
1698 VkDescriptorSetLayout)
1699 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_update_template,
1700 VkDescriptorUpdateTemplate)
1701 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_device_memory, VkDeviceMemory)
1702 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_fence, VkFence)
1703 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_event, VkEvent)
1704 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_framebuffer, VkFramebuffer)
1705 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image, VkImage)
1706 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image_view, VkImageView);
1707 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_cache, VkPipelineCache)
1708 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline, VkPipeline)
1709 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_layout, VkPipelineLayout)
1710 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_query_pool, VkQueryPool)
1711 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_render_pass, VkRenderPass)
1712 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_sampler, VkSampler)
1713 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_shader_module, VkShaderModule)
1714 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_semaphore, VkSemaphore)
1715
1716 #endif /* TU_PRIVATE_H */