2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
43 #define VG(x) ((void)0)
46 #include "c11/threads.h"
47 #include "main/macros.h"
48 #include "util/list.h"
49 #include "util/macros.h"
51 #include "vk_debug_report.h"
52 #include "wsi_common.h"
54 #include "drm-uapi/msm_drm.h"
55 #include "ir3/ir3_compiler.h"
56 #include "ir3/ir3_shader.h"
58 #include "adreno_common.xml.h"
59 #include "adreno_pm4.xml.h"
61 #include "fdl/freedreno_layout.h"
63 #include "tu_descriptor_set.h"
64 #include "tu_extensions.h"
66 /* Pre-declarations needed for WSI entrypoints */
69 typedef struct xcb_connection_t xcb_connection_t
;
70 typedef uint32_t xcb_visualid_t
;
71 typedef uint32_t xcb_window_t
;
73 #include <vulkan/vk_android_native_buffer.h>
74 #include <vulkan/vk_icd.h>
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
78 #include "tu_entrypoints.h"
80 #include "vk_format.h"
83 #define MAX_VERTEX_ATTRIBS 32
85 #define MAX_VSC_PIPES 32
86 #define MAX_VIEWPORTS 1
87 #define MAX_SCISSORS 16
88 #define MAX_DISCARD_RECTANGLES 4
89 #define MAX_PUSH_CONSTANTS_SIZE 128
90 #define MAX_PUSH_DESCRIPTORS 32
91 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
92 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
93 #define MAX_DYNAMIC_BUFFERS \
94 (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
95 #define TU_MAX_DRM_DEVICES 8
97 #define MAX_BIND_POINTS 2 /* compute + graphics */
98 /* The Qualcomm driver exposes 0x20000058 */
99 #define MAX_STORAGE_BUFFER_RANGE 0x20000000
100 /* We use ldc for uniform buffer loads, just like the Qualcomm driver, so
101 * expose the same maximum range.
102 * TODO: The SIZE bitfield is 15 bits, and in 4-dword units, so the actual
103 * range might be higher.
105 #define MAX_UNIFORM_BUFFER_RANGE 0x10000
107 #define A6XX_TEX_CONST_DWORDS 16
108 #define A6XX_TEX_SAMP_DWORDS 4
110 #define tu_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
112 static inline uint32_t
113 tu_minify(uint32_t n
, uint32_t levels
)
115 if (unlikely(n
== 0))
118 return MAX2(n
>> levels
, 1);
121 #define for_each_bit(b, dword) \
122 for (uint32_t __dword = (dword); \
123 (b) = __builtin_ffs(__dword) - 1, __dword; __dword &= ~(1 << (b)))
125 #define typed_memcpy(dest, src, count) \
127 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
128 memcpy((dest), (src), (count) * sizeof(*(src))); \
131 #define COND(bool, val) ((bool) ? (val) : 0)
133 /* Whenever we generate an error, pass it through this function. Useful for
134 * debugging, where we can break on it. Only call at error site, not when
135 * propagating errors. Might be useful to plug in a stack trace here.
141 __vk_errorf(struct tu_instance
*instance
,
148 #define vk_error(instance, error) \
149 __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
150 #define vk_errorf(instance, error, format, ...) \
151 __vk_errorf(instance, error, __FILE__, __LINE__, format, ##__VA_ARGS__);
154 __tu_finishme(const char *file
, int line
, const char *format
, ...)
157 tu_loge(const char *format
, ...) tu_printflike(1, 2);
159 tu_logi(const char *format
, ...) tu_printflike(1, 2);
162 * Print a FINISHME message, including its source location.
164 #define tu_finishme(format, ...) \
166 static bool reported = false; \
168 __tu_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
173 /* Suppress -Wunused in stub functions */
174 #define tu_use_args(...) __tu_use_args(0, ##__VA_ARGS__)
176 __tu_use_args(int ignore
, ...)
182 tu_finishme("stub %s", __func__); \
186 tu_lookup_entrypoint_unchecked(const char *name
);
188 tu_lookup_entrypoint_checked(
190 uint32_t core_version
,
191 const struct tu_instance_extension_table
*instance
,
192 const struct tu_device_extension_table
*device
);
194 struct tu_physical_device
196 VK_LOADER_DATA _loader_data
;
198 struct tu_instance
*instance
;
201 char name
[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE
];
202 uint8_t driver_uuid
[VK_UUID_SIZE
];
203 uint8_t device_uuid
[VK_UUID_SIZE
];
204 uint8_t cache_uuid
[VK_UUID_SIZE
];
206 struct wsi_device wsi_device
;
214 uint32_t ccu_offset_gmem
;
215 uint32_t ccu_offset_bypass
;
216 /* alignment for size of tiles */
217 uint32_t tile_align_w
;
218 #define TILE_ALIGN_H 16
219 /* gmem store/load granularity */
220 #define GMEM_ALIGN_W 16
221 #define GMEM_ALIGN_H 4
224 uint32_t PC_UNKNOWN_9805
;
225 uint32_t SP_UNKNOWN_A0F8
;
228 /* This is the drivers on-disk cache used as a fallback as opposed to
229 * the pipeline cache defined by apps.
231 struct disk_cache
*disk_cache
;
233 struct tu_device_extension_table supported_extensions
;
238 TU_DEBUG_STARTUP
= 1 << 0,
239 TU_DEBUG_NIR
= 1 << 1,
240 TU_DEBUG_IR3
= 1 << 2,
241 TU_DEBUG_NOBIN
= 1 << 3,
242 TU_DEBUG_SYSMEM
= 1 << 4,
243 TU_DEBUG_FORCEBIN
= 1 << 5,
244 TU_DEBUG_NOUBWC
= 1 << 6,
249 VK_LOADER_DATA _loader_data
;
251 VkAllocationCallbacks alloc
;
253 uint32_t api_version
;
254 int physical_device_count
;
255 struct tu_physical_device physical_devices
[TU_MAX_DRM_DEVICES
];
257 enum tu_debug_flags debug_flags
;
259 struct vk_debug_report_instance debug_report_callbacks
;
261 struct tu_instance_extension_table enabled_extensions
;
265 tu_wsi_init(struct tu_physical_device
*physical_device
);
267 tu_wsi_finish(struct tu_physical_device
*physical_device
);
270 tu_instance_extension_supported(const char *name
);
272 tu_physical_device_api_version(struct tu_physical_device
*dev
);
274 tu_physical_device_extension_supported(struct tu_physical_device
*dev
,
279 struct tu_pipeline_cache
281 struct tu_device
*device
;
282 pthread_mutex_t mutex
;
286 uint32_t kernel_count
;
287 struct cache_entry
**hash_table
;
290 VkAllocationCallbacks alloc
;
293 struct tu_pipeline_key
299 #define TU_QUEUE_GENERAL 0
301 #define TU_MAX_QUEUE_FAMILIES 1
305 struct wsi_fence
*fence_wsi
;
311 tu_fence_init(struct tu_fence
*fence
, bool signaled
);
313 tu_fence_finish(struct tu_fence
*fence
);
315 tu_fence_update_fd(struct tu_fence
*fence
, int fd
);
317 tu_fence_copy(struct tu_fence
*fence
, const struct tu_fence
*src
);
319 tu_fence_signal(struct tu_fence
*fence
);
321 tu_fence_wait_idle(struct tu_fence
*fence
);
325 VK_LOADER_DATA _loader_data
;
326 struct tu_device
*device
;
327 uint32_t queue_family_index
;
329 VkDeviceQueueCreateFlags flags
;
331 uint32_t msm_queue_id
;
332 struct tu_fence submit_fence
;
345 VK_LOADER_DATA _loader_data
;
347 VkAllocationCallbacks alloc
;
349 struct tu_instance
*instance
;
351 struct tu_queue
*queues
[TU_MAX_QUEUE_FAMILIES
];
352 int queue_count
[TU_MAX_QUEUE_FAMILIES
];
354 struct tu_physical_device
*physical_device
;
356 struct ir3_compiler
*compiler
;
358 /* Backup in-memory cache to be used if the app doesn't provide one */
359 struct tu_pipeline_cache
*mem_cache
;
361 struct tu_bo vsc_draw_strm
;
362 struct tu_bo vsc_prim_strm
;
363 uint32_t vsc_draw_strm_pitch
;
364 uint32_t vsc_prim_strm_pitch
;
366 #define MIN_SCRATCH_BO_SIZE_LOG2 12 /* A page */
368 /* Currently the kernel driver uses a 32-bit GPU address space, but it
369 * should be impossible to go beyond 48 bits.
375 } scratch_bos
[48 - MIN_SCRATCH_BO_SIZE_LOG2
];
377 struct tu_bo border_color
;
379 struct tu_device_extension_table enabled_extensions
;
383 tu_bo_init_new(struct tu_device
*dev
, struct tu_bo
*bo
, uint64_t size
);
385 tu_bo_init_dmabuf(struct tu_device
*dev
,
390 tu_bo_export_dmabuf(struct tu_device
*dev
, struct tu_bo
*bo
);
392 tu_bo_finish(struct tu_device
*dev
, struct tu_bo
*bo
);
394 tu_bo_map(struct tu_device
*dev
, struct tu_bo
*bo
);
396 /* Get a scratch bo for use inside a command buffer. This will always return
397 * the same bo given the same size or similar sizes, so only one scratch bo
398 * can be used at the same time. It's meant for short-lived things where we
399 * need to write to some piece of memory, read from it, and then immediately
403 tu_get_scratch_bo(struct tu_device
*dev
, uint64_t size
, struct tu_bo
**bo
);
408 const struct tu_bo
*bo
;
414 struct ts_cs_memory
{
423 * A command stream in TU_CS_MODE_GROW mode grows automatically whenever it
424 * is full. tu_cs_begin must be called before command packet emission and
425 * tu_cs_end must be called after.
427 * This mode may create multiple entries internally. The entries must be
428 * submitted together.
433 * A command stream in TU_CS_MODE_EXTERNAL mode wraps an external,
434 * fixed-size buffer. tu_cs_begin and tu_cs_end are optional and have no
437 * This mode does not create any entry or any BO.
442 * A command stream in TU_CS_MODE_SUB_STREAM mode does not support direct
443 * command packet emission. tu_cs_begin_sub_stream must be called to get a
444 * sub-stream to emit comamnd packets to. When done with the sub-stream,
445 * tu_cs_end_sub_stream must be called.
447 * This mode does not create any entry internally.
449 TU_CS_MODE_SUB_STREAM
,
456 uint32_t *reserved_end
;
459 struct tu_device
*device
;
460 enum tu_cs_mode mode
;
461 uint32_t next_bo_size
;
463 struct tu_cs_entry
*entries
;
464 uint32_t entry_count
;
465 uint32_t entry_capacity
;
469 uint32_t bo_capacity
;
471 /* state for cond_exec_start/cond_exec_end */
473 uint32_t *cond_dwords
;
476 struct tu_device_memory
481 /* for dedicated allocations */
482 struct tu_image
*image
;
483 struct tu_buffer
*buffer
;
490 struct tu_descriptor_range
496 struct tu_descriptor_set
498 const struct tu_descriptor_set_layout
*layout
;
499 struct tu_descriptor_pool
*pool
;
503 uint32_t *mapped_ptr
;
505 uint32_t *dynamic_descriptors
;
507 struct tu_bo
*buffers
[0];
510 struct tu_push_descriptor_set
512 struct tu_descriptor_set set
;
516 struct tu_descriptor_pool_entry
520 struct tu_descriptor_set
*set
;
523 struct tu_descriptor_pool
526 uint64_t current_offset
;
529 uint8_t *host_memory_base
;
530 uint8_t *host_memory_ptr
;
531 uint8_t *host_memory_end
;
533 uint32_t entry_count
;
534 uint32_t max_entry_count
;
535 struct tu_descriptor_pool_entry entries
[0];
538 struct tu_descriptor_update_template_entry
540 VkDescriptorType descriptor_type
;
542 /* The number of descriptors to update */
543 uint32_t descriptor_count
;
545 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array
549 /* In dwords. Not valid/used for dynamic descriptors */
552 uint32_t buffer_offset
;
554 /* Only valid for combined image samplers and samplers */
555 uint16_t has_sampler
;
561 /* For push descriptors */
562 const uint32_t *immutable_samplers
;
565 struct tu_descriptor_update_template
567 uint32_t entry_count
;
568 struct tu_descriptor_update_template_entry entry
[0];
575 VkBufferUsageFlags usage
;
576 VkBufferCreateFlags flags
;
579 VkDeviceSize bo_offset
;
582 static inline uint64_t
583 tu_buffer_iova(struct tu_buffer
*buffer
)
585 return buffer
->bo
->iova
+ buffer
->bo_offset
;
588 enum tu_dynamic_state_bits
590 TU_DYNAMIC_VIEWPORT
= 1 << 0,
591 TU_DYNAMIC_SCISSOR
= 1 << 1,
592 TU_DYNAMIC_LINE_WIDTH
= 1 << 2,
593 TU_DYNAMIC_DEPTH_BIAS
= 1 << 3,
594 TU_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
595 TU_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
596 TU_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
597 TU_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
598 TU_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
599 TU_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
600 TU_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
601 TU_DYNAMIC_ALL
= (1 << 11) - 1,
604 struct tu_vertex_binding
606 struct tu_buffer
*buffer
;
610 struct tu_viewport_state
613 VkViewport viewports
[MAX_VIEWPORTS
];
616 struct tu_scissor_state
619 VkRect2D scissors
[MAX_SCISSORS
];
622 struct tu_discard_rectangle_state
625 VkRect2D rectangles
[MAX_DISCARD_RECTANGLES
];
628 struct tu_dynamic_state
631 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
632 * Defines the set of saved dynamic state.
636 struct tu_viewport_state viewport
;
638 struct tu_scissor_state scissor
;
649 float blend_constants
[4];
661 } stencil_compare_mask
;
667 } stencil_write_mask
;
675 struct tu_discard_rectangle_state discard_rectangle
;
678 extern const struct tu_dynamic_state default_dynamic_state
;
681 tu_get_debug_option_name(int id
);
684 tu_get_perftest_option_name(int id
);
686 struct tu_descriptor_state
688 struct tu_descriptor_set
*sets
[MAX_SETS
];
690 struct tu_push_descriptor_set push_set
;
692 uint32_t dynamic_descriptors
[MAX_DYNAMIC_BUFFERS
* A6XX_TEX_CONST_DWORDS
];
693 uint32_t input_attachments
[MAX_RTS
* A6XX_TEX_CONST_DWORDS
];
704 struct tu_tiling_config
706 VkRect2D render_area
;
708 /* position and size of the first tile */
710 /* number of tiles */
711 VkExtent2D tile_count
;
713 /* size of the first VSC pipe */
715 /* number of VSC pipes */
716 VkExtent2D pipe_count
;
718 /* pipe register values */
719 uint32_t pipe_config
[MAX_VSC_PIPES
];
720 uint32_t pipe_sizes
[MAX_VSC_PIPES
];
722 /* Whether sysmem rendering must be used */
726 enum tu_cmd_dirty_bits
728 TU_CMD_DIRTY_PIPELINE
= 1 << 0,
729 TU_CMD_DIRTY_COMPUTE_PIPELINE
= 1 << 1,
730 TU_CMD_DIRTY_VERTEX_BUFFERS
= 1 << 2,
732 TU_CMD_DIRTY_DESCRIPTOR_SETS
= 1 << 3,
733 TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
= 1 << 4,
734 TU_CMD_DIRTY_PUSH_CONSTANTS
= 1 << 5,
735 TU_CMD_DIRTY_STREAMOUT_BUFFERS
= 1 << 6,
736 TU_CMD_DIRTY_INPUT_ATTACHMENTS
= 1 << 7,
738 TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 16,
739 TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 17,
740 TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 18,
741 TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 19,
742 TU_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 20,
743 TU_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 21,
746 struct tu_streamout_state
{
747 uint16_t stride
[IR3_MAX_SO_BUFFERS
];
748 uint32_t ncomp
[IR3_MAX_SO_BUFFERS
];
749 uint32_t prog
[IR3_MAX_SO_OUTPUTS
* 2];
751 uint32_t vpc_so_buf_cntl
;
754 /* There are only three cache domains we have to care about: the CCU, or
755 * color cache unit, which is used for color and depth/stencil attachments
756 * and copy/blit destinations, and is split conceptually into color and depth,
757 * and the universal cache or UCHE which is used for pretty much everything
758 * else, except for the CP (uncached) and host. We need to flush whenever data
759 * crosses these boundaries.
762 enum tu_cmd_access_mask
{
763 TU_ACCESS_UCHE_READ
= 1 << 0,
764 TU_ACCESS_UCHE_WRITE
= 1 << 1,
765 TU_ACCESS_CCU_COLOR_READ
= 1 << 2,
766 TU_ACCESS_CCU_COLOR_WRITE
= 1 << 3,
767 TU_ACCESS_CCU_DEPTH_READ
= 1 << 4,
768 TU_ACCESS_CCU_DEPTH_WRITE
= 1 << 5,
770 /* Experiments have shown that while it's safe to avoid flushing the CCU
771 * after each blit/renderpass, it's not safe to assume that subsequent
772 * lookups with a different attachment state will hit unflushed cache
773 * entries. That is, the CCU needs to be flushed and possibly invalidated
774 * when accessing memory with a different attachment state. Writing to an
775 * attachment under the following conditions after clearing using the
776 * normal 2d engine path is known to have issues:
778 * - It isn't the 0'th layer.
779 * - There are more than one attachment, and this isn't the 0'th attachment
780 * (this seems to also depend on the cpp of the attachments).
782 * Our best guess is that the layer/MRT state is used when computing
783 * the location of a cache entry in CCU, to avoid conflicts. We assume that
784 * any access in a renderpass after or before an access by a transfer needs
785 * a flush/invalidate, and use the _INCOHERENT variants to represent access
788 TU_ACCESS_CCU_COLOR_INCOHERENT_READ
= 1 << 6,
789 TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
= 1 << 7,
790 TU_ACCESS_CCU_DEPTH_INCOHERENT_READ
= 1 << 8,
791 TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE
= 1 << 9,
793 TU_ACCESS_SYSMEM_READ
= 1 << 10,
794 TU_ACCESS_SYSMEM_WRITE
= 1 << 11,
796 /* Set if a WFI is required due to data being read by the CP or the 2D
799 TU_ACCESS_WFI_READ
= 1 << 12,
802 TU_ACCESS_UCHE_READ
|
803 TU_ACCESS_CCU_COLOR_READ
|
804 TU_ACCESS_CCU_DEPTH_READ
|
805 TU_ACCESS_CCU_COLOR_INCOHERENT_READ
|
806 TU_ACCESS_CCU_DEPTH_INCOHERENT_READ
|
807 TU_ACCESS_SYSMEM_READ
,
810 TU_ACCESS_UCHE_WRITE
|
811 TU_ACCESS_CCU_COLOR_WRITE
|
812 TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
|
813 TU_ACCESS_CCU_DEPTH_WRITE
|
814 TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE
|
815 TU_ACCESS_SYSMEM_WRITE
,
822 enum tu_cmd_flush_bits
{
823 TU_CMD_FLAG_CCU_FLUSH_DEPTH
= 1 << 0,
824 TU_CMD_FLAG_CCU_FLUSH_COLOR
= 1 << 1,
825 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
= 1 << 2,
826 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
= 1 << 3,
827 TU_CMD_FLAG_CACHE_FLUSH
= 1 << 4,
828 TU_CMD_FLAG_CACHE_INVALIDATE
= 1 << 5,
830 TU_CMD_FLAG_ALL_FLUSH
=
831 TU_CMD_FLAG_CCU_FLUSH_DEPTH
|
832 TU_CMD_FLAG_CCU_FLUSH_COLOR
|
833 TU_CMD_FLAG_CACHE_FLUSH
,
835 TU_CMD_FLAG_ALL_INVALIDATE
=
836 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
|
837 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
|
838 TU_CMD_FLAG_CACHE_INVALIDATE
,
840 TU_CMD_FLAG_WFI
= 1 << 6,
843 /* Changing the CCU from sysmem mode to gmem mode or vice-versa is pretty
844 * heavy, involving a CCU cache flush/invalidate and a WFI in order to change
845 * which part of the gmem is used by the CCU. Here we keep track of what the
848 enum tu_cmd_ccu_state
{
854 struct tu_cache_state
{
855 /* Caches which must be made available (flushed) eventually if there are
856 * any users outside that cache domain, and caches which must be
857 * invalidated eventually if there are any reads.
859 enum tu_cmd_flush_bits pending_flush_bits
;
860 /* Pending flushes */
861 enum tu_cmd_flush_bits flush_bits
;
868 struct tu_pipeline
*pipeline
;
869 struct tu_pipeline
*compute_pipeline
;
874 struct tu_buffer
*buffers
[MAX_VBS
];
875 VkDeviceSize offsets
[MAX_VBS
];
878 struct tu_dynamic_state dynamic
;
880 /* Stream output buffers */
883 struct tu_buffer
*buffers
[IR3_MAX_SO_BUFFERS
];
884 VkDeviceSize offsets
[IR3_MAX_SO_BUFFERS
];
885 VkDeviceSize sizes
[IR3_MAX_SO_BUFFERS
];
888 uint8_t streamout_reset
;
889 uint8_t streamout_enabled
;
892 struct tu_buffer
*index_buffer
;
893 uint64_t index_offset
;
895 uint32_t max_index_count
;
898 /* Renderpasses are tricky, because we may need to flush differently if
899 * using sysmem vs. gmem and therefore we have to delay any flushing that
900 * happens before a renderpass. So we have to have two copies of the flush
901 * state, one for intra-renderpass flushes (i.e. renderpass dependencies)
902 * and one for outside a renderpass.
904 struct tu_cache_state cache
;
905 struct tu_cache_state renderpass_cache
;
907 enum tu_cmd_ccu_state ccu_state
;
909 const struct tu_render_pass
*pass
;
910 const struct tu_subpass
*subpass
;
911 const struct tu_framebuffer
*framebuffer
;
913 struct tu_tiling_config tiling_config
;
915 struct tu_cs_entry tile_store_ib
;
920 VkAllocationCallbacks alloc
;
921 struct list_head cmd_buffers
;
922 struct list_head free_cmd_buffers
;
923 uint32_t queue_family_index
;
926 struct tu_cmd_buffer_upload
931 struct list_head list
;
934 enum tu_cmd_buffer_status
936 TU_CMD_BUFFER_STATUS_INVALID
,
937 TU_CMD_BUFFER_STATUS_INITIAL
,
938 TU_CMD_BUFFER_STATUS_RECORDING
,
939 TU_CMD_BUFFER_STATUS_EXECUTABLE
,
940 TU_CMD_BUFFER_STATUS_PENDING
,
947 struct drm_msm_gem_submit_bo
*bo_infos
;
950 #define TU_BO_LIST_FAILED (~0)
953 tu_bo_list_init(struct tu_bo_list
*list
);
955 tu_bo_list_destroy(struct tu_bo_list
*list
);
957 tu_bo_list_reset(struct tu_bo_list
*list
);
959 tu_bo_list_add(struct tu_bo_list
*list
,
960 const struct tu_bo
*bo
,
963 tu_bo_list_merge(struct tu_bo_list
*list
, const struct tu_bo_list
*other
);
965 /* This struct defines the layout of the scratch_bo */
968 uint32_t seqno_dummy
; /* dummy seqno for CP_EVENT_WRITE */
970 volatile uint32_t vsc_overflow
;
972 /* flag set from cmdstream when VSC overflow detected: */
973 uint32_t vsc_scratch
;
978 /* scratch space for VPC_SO[i].FLUSH_BASE_LO/HI, start on 32 byte boundary. */
985 #define ctrl_offset(member) offsetof(struct tu6_control, member)
989 VK_LOADER_DATA _loader_data
;
991 struct tu_device
*device
;
993 struct tu_cmd_pool
*pool
;
994 struct list_head pool_link
;
996 VkCommandBufferUsageFlags usage_flags
;
997 VkCommandBufferLevel level
;
998 enum tu_cmd_buffer_status status
;
1000 struct tu_cmd_state state
;
1001 struct tu_vertex_binding vertex_bindings
[MAX_VBS
];
1002 uint32_t vertex_bindings_set
;
1003 uint32_t queue_family_index
;
1005 uint32_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
/ 4];
1006 VkShaderStageFlags push_constant_stages
;
1007 struct tu_descriptor_set meta_push_descriptors
;
1009 struct tu_descriptor_state descriptors
[MAX_BIND_POINTS
];
1011 struct tu_cmd_buffer_upload upload
;
1013 VkResult record_result
;
1015 struct tu_bo_list bo_list
;
1017 struct tu_cs draw_cs
;
1018 struct tu_cs draw_epilogue_cs
;
1019 struct tu_cs sub_cs
;
1021 struct tu_bo scratch_bo
;
1023 struct tu_bo vsc_draw_strm
;
1024 struct tu_bo vsc_prim_strm
;
1025 uint32_t vsc_draw_strm_pitch
;
1026 uint32_t vsc_prim_strm_pitch
;
1030 /* Temporary struct for tracking a register state to be written, used by
1031 * a6xx-pack.h and tu_cs_emit_regs()
1033 struct tu_reg_value
{
1044 void tu_emit_cache_flush_renderpass(struct tu_cmd_buffer
*cmd_buffer
,
1047 void tu_emit_cache_flush_ccu(struct tu_cmd_buffer
*cmd_buffer
,
1049 enum tu_cmd_ccu_state ccu_state
);
1052 tu6_emit_event_write(struct tu_cmd_buffer
*cmd
,
1054 enum vgt_event_type event
);
1056 static inline struct tu_descriptor_state
*
1057 tu_get_descriptors_state(struct tu_cmd_buffer
*cmd_buffer
,
1058 VkPipelineBindPoint bind_point
)
1060 return &cmd_buffer
->descriptors
[bind_point
];
1068 static inline gl_shader_stage
1069 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1071 assert(__builtin_popcount(vk_stage
) == 1);
1072 return ffs(vk_stage
) - 1;
1075 static inline VkShaderStageFlagBits
1076 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1078 return (1 << mesa_stage
);
1081 #define TU_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1083 #define tu_foreach_stage(stage, stage_bits) \
1084 for (gl_shader_stage stage, \
1085 __tmp = (gl_shader_stage)((stage_bits) &TU_STAGE_MASK); \
1086 stage = __builtin_ffs(__tmp) - 1, __tmp; __tmp &= ~(1 << (stage)))
1089 tu6_stage2opcode(gl_shader_stage type
);
1090 enum a6xx_state_block
1091 tu6_stage2shadersb(gl_shader_stage type
);
1093 struct tu_shader_module
1095 unsigned char sha1
[20];
1098 const uint32_t *code
[0];
1101 struct tu_shader_compile_options
1103 struct ir3_shader_key key
;
1106 bool include_binning_pass
;
1109 struct tu_push_constant_range
1117 struct ir3_shader
*ir3_shader
;
1119 struct tu_push_constant_range push_consts
;
1120 unsigned attachment_idx
[MAX_RTS
];
1121 uint8_t active_desc_sets
;
1125 tu_shader_create(struct tu_device
*dev
,
1126 gl_shader_stage stage
,
1127 const VkPipelineShaderStageCreateInfo
*stage_info
,
1128 struct tu_pipeline_layout
*layout
,
1129 const VkAllocationCallbacks
*alloc
);
1132 tu_shader_destroy(struct tu_device
*dev
,
1133 struct tu_shader
*shader
,
1134 const VkAllocationCallbacks
*alloc
);
1137 tu_shader_compile_options_init(
1138 struct tu_shader_compile_options
*options
,
1139 const VkGraphicsPipelineCreateInfo
*pipeline_info
);
1141 struct tu_program_descriptor_linkage
1143 struct ir3_ubo_analysis_state ubo_state
;
1144 struct ir3_const_state const_state
;
1148 struct tu_push_constant_range push_consts
;
1155 struct tu_dynamic_state dynamic_state
;
1157 struct tu_pipeline_layout
*layout
;
1159 bool need_indirect_descriptor_sets
;
1160 VkShaderStageFlags active_stages
;
1161 uint32_t active_desc_sets
;
1163 struct tu_streamout_state streamout
;
1167 struct tu_bo binary_bo
;
1168 struct tu_cs_entry state_ib
;
1169 struct tu_cs_entry binning_state_ib
;
1171 struct tu_program_descriptor_linkage link
[MESA_SHADER_STAGES
];
1172 unsigned input_attachment_idx
[MAX_RTS
];
1177 struct tu_cs_entry state_ib
;
1182 struct tu_cs_entry state_ib
;
1183 struct tu_cs_entry binning_state_ib
;
1184 uint32_t bindings_used
;
1189 enum pc_di_primtype primtype
;
1190 bool primitive_restart
;
1195 struct tu_cs_entry state_ib
;
1200 uint32_t gras_su_cntl
;
1201 struct tu_cs_entry state_ib
;
1206 struct tu_cs_entry state_ib
;
1211 struct tu_cs_entry state_ib
;
1216 uint32_t local_size
[3];
1221 tu6_emit_viewport(struct tu_cs
*cs
, const VkViewport
*viewport
);
1224 tu6_emit_scissor(struct tu_cs
*cs
, const VkRect2D
*scissor
);
1227 tu6_emit_sample_locations(struct tu_cs
*cs
, const VkSampleLocationsInfoEXT
*samp_loc
);
1230 tu6_emit_gras_su_cntl(struct tu_cs
*cs
,
1231 uint32_t gras_su_cntl
,
1235 tu6_emit_depth_bias(struct tu_cs
*cs
,
1236 float constant_factor
,
1238 float slope_factor
);
1241 tu6_emit_stencil_compare_mask(struct tu_cs
*cs
,
1246 tu6_emit_stencil_write_mask(struct tu_cs
*cs
, uint32_t front
, uint32_t back
);
1249 tu6_emit_stencil_reference(struct tu_cs
*cs
, uint32_t front
, uint32_t back
);
1252 tu6_emit_blend_constants(struct tu_cs
*cs
, const float constants
[4]);
1254 void tu6_emit_msaa(struct tu_cs
*cs
, VkSampleCountFlagBits samples
);
1256 void tu6_emit_window_scissor(struct tu_cs
*cs
, uint32_t x1
, uint32_t y1
, uint32_t x2
, uint32_t y2
);
1258 void tu6_emit_window_offset(struct tu_cs
*cs
, uint32_t x1
, uint32_t y1
);
1261 tu6_emit_xs_config(struct tu_cs
*cs
,
1262 gl_shader_stage stage
,
1263 const struct ir3_shader_variant
*xs
,
1264 uint64_t binary_iova
);
1267 tu6_emit_vpc(struct tu_cs
*cs
,
1268 const struct ir3_shader_variant
*vs
,
1269 const struct ir3_shader_variant
*gs
,
1270 const struct ir3_shader_variant
*fs
,
1271 struct tu_streamout_state
*tf
);
1274 tu6_emit_fs_inputs(struct tu_cs
*cs
, const struct ir3_shader_variant
*fs
);
1276 struct tu_image_view
;
1279 tu_resolve_sysmem(struct tu_cmd_buffer
*cmd
,
1281 struct tu_image_view
*src
,
1282 struct tu_image_view
*dst
,
1284 const VkRect2D
*rect
);
1287 tu_clear_sysmem_attachment(struct tu_cmd_buffer
*cmd
,
1290 const VkRenderPassBeginInfo
*info
);
1293 tu_clear_gmem_attachment(struct tu_cmd_buffer
*cmd
,
1296 const VkRenderPassBeginInfo
*info
);
1299 tu_load_gmem_attachment(struct tu_cmd_buffer
*cmd
,
1304 /* expose this function to be able to emit load without checking LOAD_OP */
1306 tu_emit_load_gmem_attachment(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
, uint32_t a
);
1308 /* note: gmem store can also resolve */
1310 tu_store_gmem_attachment(struct tu_cmd_buffer
*cmd
,
1315 enum tu_supported_formats
{
1321 struct tu_native_format
1323 enum a6xx_format fmt
: 8;
1324 enum a3xx_color_swap swap
: 8;
1325 enum a6xx_tile_mode tile_mode
: 8;
1326 enum tu_supported_formats supported
: 8;
1329 struct tu_native_format
tu6_format_vtx(VkFormat format
);
1330 struct tu_native_format
tu6_format_color(VkFormat format
, enum a6xx_tile_mode tile_mode
);
1331 struct tu_native_format
tu6_format_texture(VkFormat format
, enum a6xx_tile_mode tile_mode
);
1333 static inline enum a6xx_format
1334 tu6_base_format(VkFormat format
)
1336 /* note: tu6_format_color doesn't care about tiling for .fmt field */
1337 return tu6_format_color(format
, TILE6_LINEAR
).fmt
;
1340 enum a6xx_depth_format
tu6_pipe2depth(VkFormat format
);
1345 /* The original VkFormat provided by the client. This may not match any
1346 * of the actual surface formats.
1349 VkImageAspectFlags aspects
;
1350 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1351 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1352 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1354 uint32_t level_count
;
1355 uint32_t layer_count
;
1356 VkSampleCountFlagBits samples
;
1358 struct fdl_layout layout
;
1360 unsigned queue_family_mask
;
1364 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1365 VkDeviceMemory owned_memory
;
1367 /* Set when bound */
1369 VkDeviceSize bo_offset
;
1372 static inline uint32_t
1373 tu_get_layerCount(const struct tu_image
*image
,
1374 const VkImageSubresourceRange
*range
)
1376 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
1377 ? image
->layer_count
- range
->baseArrayLayer
1378 : range
->layerCount
;
1381 static inline uint32_t
1382 tu_get_levelCount(const struct tu_image
*image
,
1383 const VkImageSubresourceRange
*range
)
1385 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
1386 ? image
->level_count
- range
->baseMipLevel
1387 : range
->levelCount
;
1390 enum a3xx_msaa_samples
1391 tu_msaa_samples(uint32_t samples
);
1392 enum a6xx_tex_fetchsize
1393 tu6_fetchsize(VkFormat format
);
1395 struct tu_image_view
1397 struct tu_image
*image
; /**< VkImageViewCreateInfo::image */
1401 uint32_t layer_size
;
1402 uint32_t ubwc_layer_size
;
1404 /* used to determine if fast gmem store path can be used */
1410 uint32_t descriptor
[A6XX_TEX_CONST_DWORDS
];
1412 /* Descriptor for use as a storage image as opposed to a sampled image.
1413 * This has a few differences for cube maps (e.g. type).
1415 uint32_t storage_descriptor
[A6XX_TEX_CONST_DWORDS
];
1417 /* pre-filled register values */
1419 uint32_t FLAG_BUFFER_PITCH
;
1421 uint32_t RB_MRT_BUF_INFO
;
1422 uint32_t SP_FS_MRT_REG
;
1424 uint32_t SP_PS_2D_SRC_INFO
;
1425 uint32_t SP_PS_2D_SRC_SIZE
;
1427 uint32_t RB_2D_DST_INFO
;
1429 uint32_t RB_BLIT_DST_INFO
;
1432 struct tu_sampler_ycbcr_conversion
{
1434 VkSamplerYcbcrModelConversion ycbcr_model
;
1435 VkSamplerYcbcrRange ycbcr_range
;
1436 VkComponentMapping components
;
1437 VkChromaLocation chroma_offsets
[2];
1438 VkFilter chroma_filter
;
1442 uint32_t descriptor
[A6XX_TEX_SAMP_DWORDS
];
1443 struct tu_sampler_ycbcr_conversion
*ycbcr_sampler
;
1447 tu_cs_image_ref(struct tu_cs
*cs
, const struct tu_image_view
*iview
, uint32_t layer
);
1450 tu_cs_image_ref_2d(struct tu_cs
*cs
, const struct tu_image_view
*iview
, uint32_t layer
, bool src
);
1453 tu_cs_image_flag_ref(struct tu_cs
*cs
, const struct tu_image_view
*iview
, uint32_t layer
);
1455 enum a6xx_tex_filter
1456 tu6_tex_filter(VkFilter filter
, unsigned aniso
);
1459 tu_image_create(VkDevice _device
,
1460 const VkImageCreateInfo
*pCreateInfo
,
1461 const VkAllocationCallbacks
*alloc
,
1464 const VkSubresourceLayout
*plane_layouts
);
1467 tu_image_from_gralloc(VkDevice device_h
,
1468 const VkImageCreateInfo
*base_info
,
1469 const VkNativeBufferANDROID
*gralloc_info
,
1470 const VkAllocationCallbacks
*alloc
,
1471 VkImage
*out_image_h
);
1474 tu_image_view_init(struct tu_image_view
*view
,
1475 const VkImageViewCreateInfo
*pCreateInfo
);
1477 struct tu_buffer_view
1479 uint32_t descriptor
[A6XX_TEX_CONST_DWORDS
];
1481 struct tu_buffer
*buffer
;
1484 tu_buffer_view_init(struct tu_buffer_view
*view
,
1485 struct tu_device
*device
,
1486 const VkBufferViewCreateInfo
*pCreateInfo
);
1488 struct tu_attachment_info
1490 struct tu_image_view
*attachment
;
1493 struct tu_framebuffer
1499 uint32_t attachment_count
;
1500 struct tu_attachment_info attachments
[0];
1503 struct tu_subpass_barrier
{
1504 VkPipelineStageFlags src_stage_mask
;
1505 VkAccessFlags src_access_mask
;
1506 VkAccessFlags dst_access_mask
;
1507 bool incoherent_ccu_color
, incoherent_ccu_depth
;
1510 struct tu_subpass_attachment
1512 uint32_t attachment
;
1513 VkImageLayout layout
;
1518 uint32_t input_count
;
1519 uint32_t color_count
;
1520 struct tu_subpass_attachment
*input_attachments
;
1521 struct tu_subpass_attachment
*color_attachments
;
1522 struct tu_subpass_attachment
*resolve_attachments
;
1523 struct tu_subpass_attachment depth_stencil_attachment
;
1525 VkSampleCountFlagBits samples
;
1526 bool has_external_src
, has_external_dst
;
1530 struct tu_subpass_barrier start_barrier
;
1533 struct tu_render_pass_attachment
1538 VkImageAspectFlags clear_mask
;
1541 VkImageLayout initial_layout
, final_layout
;
1542 int32_t gmem_offset
;
1545 struct tu_render_pass
1547 uint32_t attachment_count
;
1548 uint32_t subpass_count
;
1549 uint32_t gmem_pixels
;
1550 uint32_t tile_align_w
;
1551 struct tu_subpass_attachment
*subpass_attachments
;
1552 struct tu_render_pass_attachment
*attachments
;
1553 struct tu_subpass_barrier end_barrier
;
1554 struct tu_subpass subpasses
[0];
1557 struct tu_query_pool
1562 uint32_t pipeline_statistics
;
1569 uint32_t temp_syncobj
;
1573 tu_set_descriptor_set(struct tu_cmd_buffer
*cmd_buffer
,
1574 VkPipelineBindPoint bind_point
,
1575 struct tu_descriptor_set
*set
,
1579 tu_update_descriptor_sets(struct tu_device
*device
,
1580 struct tu_cmd_buffer
*cmd_buffer
,
1581 VkDescriptorSet overrideSet
,
1582 uint32_t descriptorWriteCount
,
1583 const VkWriteDescriptorSet
*pDescriptorWrites
,
1584 uint32_t descriptorCopyCount
,
1585 const VkCopyDescriptorSet
*pDescriptorCopies
);
1588 tu_update_descriptor_set_with_template(
1589 struct tu_device
*device
,
1590 struct tu_cmd_buffer
*cmd_buffer
,
1591 struct tu_descriptor_set
*set
,
1592 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
1596 tu_drm_get_gpu_id(const struct tu_physical_device
*dev
, uint32_t *id
);
1599 tu_drm_get_gmem_size(const struct tu_physical_device
*dev
, uint32_t *size
);
1602 tu_drm_get_gmem_base(const struct tu_physical_device
*dev
, uint64_t *base
);
1605 tu_drm_submitqueue_new(const struct tu_device
*dev
,
1607 uint32_t *queue_id
);
1610 tu_drm_submitqueue_close(const struct tu_device
*dev
, uint32_t queue_id
);
1613 tu_gem_new(const struct tu_device
*dev
, uint64_t size
, uint32_t flags
);
1615 tu_gem_import_dmabuf(const struct tu_device
*dev
,
1619 tu_gem_export_dmabuf(const struct tu_device
*dev
, uint32_t gem_handle
);
1621 tu_gem_close(const struct tu_device
*dev
, uint32_t gem_handle
);
1623 tu_gem_info_offset(const struct tu_device
*dev
, uint32_t gem_handle
);
1625 tu_gem_info_iova(const struct tu_device
*dev
, uint32_t gem_handle
);
1627 #define TU_DEFINE_HANDLE_CASTS(__tu_type, __VkType) \
1629 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1631 return (struct __tu_type *) _handle; \
1634 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1636 return (__VkType) _obj; \
1639 #define TU_DEFINE_NONDISP_HANDLE_CASTS(__tu_type, __VkType) \
1641 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1643 return (struct __tu_type *) (uintptr_t) _handle; \
1646 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1648 return (__VkType)(uintptr_t) _obj; \
1651 #define TU_FROM_HANDLE(__tu_type, __name, __handle) \
1652 struct __tu_type *__name = __tu_type##_from_handle(__handle)
1654 TU_DEFINE_HANDLE_CASTS(tu_cmd_buffer
, VkCommandBuffer
)
1655 TU_DEFINE_HANDLE_CASTS(tu_device
, VkDevice
)
1656 TU_DEFINE_HANDLE_CASTS(tu_instance
, VkInstance
)
1657 TU_DEFINE_HANDLE_CASTS(tu_physical_device
, VkPhysicalDevice
)
1658 TU_DEFINE_HANDLE_CASTS(tu_queue
, VkQueue
)
1660 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_cmd_pool
, VkCommandPool
)
1661 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer
, VkBuffer
)
1662 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer_view
, VkBufferView
)
1663 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_pool
, VkDescriptorPool
)
1664 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set
, VkDescriptorSet
)
1665 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set_layout
,
1666 VkDescriptorSetLayout
)
1667 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_update_template
,
1668 VkDescriptorUpdateTemplate
)
1669 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_device_memory
, VkDeviceMemory
)
1670 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_fence
, VkFence
)
1671 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_event
, VkEvent
)
1672 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_framebuffer
, VkFramebuffer
)
1673 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image
, VkImage
)
1674 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image_view
, VkImageView
);
1675 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_cache
, VkPipelineCache
)
1676 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline
, VkPipeline
)
1677 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_layout
, VkPipelineLayout
)
1678 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_query_pool
, VkQueryPool
)
1679 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_render_pass
, VkRenderPass
)
1680 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_sampler
, VkSampler
)
1681 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_sampler_ycbcr_conversion
, VkSamplerYcbcrConversion
)
1682 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_shader_module
, VkShaderModule
)
1683 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_semaphore
, VkSemaphore
)
1685 #endif /* TU_PRIVATE_H */