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[mesa.git] / src / freedreno / vulkan / tu_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #ifndef TU_PRIVATE_H
29 #define TU_PRIVATE_H
30
31 #include <assert.h>
32 #include <pthread.h>
33 #include <stdbool.h>
34 #include <stdint.h>
35 #include <stdio.h>
36 #include <stdlib.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <memcheck.h>
40 #include <valgrind.h>
41 #define VG(x) x
42 #else
43 #define VG(x) ((void)0)
44 #endif
45
46 #include "c11/threads.h"
47 #include "main/macros.h"
48 #include "util/list.h"
49 #include "util/macros.h"
50 #include "vk_alloc.h"
51 #include "vk_debug_report.h"
52 #include "wsi_common.h"
53
54 #include "drm-uapi/msm_drm.h"
55 #include "ir3/ir3_compiler.h"
56 #include "ir3/ir3_shader.h"
57
58 #include "adreno_common.xml.h"
59 #include "adreno_pm4.xml.h"
60 #include "a6xx.xml.h"
61 #include "fdl/freedreno_layout.h"
62
63 #include "tu_descriptor_set.h"
64 #include "tu_extensions.h"
65
66 /* Pre-declarations needed for WSI entrypoints */
67 struct wl_surface;
68 struct wl_display;
69 typedef struct xcb_connection_t xcb_connection_t;
70 typedef uint32_t xcb_visualid_t;
71 typedef uint32_t xcb_window_t;
72
73 #include <vulkan/vk_android_native_buffer.h>
74 #include <vulkan/vk_icd.h>
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77
78 #include "tu_entrypoints.h"
79
80 #include "vk_format.h"
81
82 #define MAX_VBS 32
83 #define MAX_VERTEX_ATTRIBS 32
84 #define MAX_RTS 8
85 #define MAX_VSC_PIPES 32
86 #define MAX_VIEWPORTS 1
87 #define MAX_SCISSORS 16
88 #define MAX_DISCARD_RECTANGLES 4
89 #define MAX_PUSH_CONSTANTS_SIZE 128
90 #define MAX_PUSH_DESCRIPTORS 32
91 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
92 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
93 #define MAX_DYNAMIC_BUFFERS \
94 (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
95 #define MAX_SAMPLES_LOG2 4
96 #define NUM_META_FS_KEYS 13
97 #define TU_MAX_DRM_DEVICES 8
98 #define MAX_VIEWS 8
99 /* The Qualcomm driver exposes 0x20000058 */
100 #define MAX_STORAGE_BUFFER_RANGE 0x20000000
101 /* We use ldc for uniform buffer loads, just like the Qualcomm driver, so
102 * expose the same maximum range.
103 * TODO: The SIZE bitfield is 15 bits, and in 4-dword units, so the actual
104 * range might be higher.
105 */
106 #define MAX_UNIFORM_BUFFER_RANGE 0x10000
107
108 #define NUM_DEPTH_CLEAR_PIPELINES 3
109
110 /*
111 * This is the point we switch from using CP to compute shader
112 * for certain buffer operations.
113 */
114 #define TU_BUFFER_OPS_CS_THRESHOLD 4096
115
116 #define A6XX_TEX_CONST_DWORDS 16
117 #define A6XX_TEX_SAMP_DWORDS 4
118
119 enum tu_mem_heap
120 {
121 TU_MEM_HEAP_VRAM,
122 TU_MEM_HEAP_VRAM_CPU_ACCESS,
123 TU_MEM_HEAP_GTT,
124 TU_MEM_HEAP_COUNT
125 };
126
127 enum tu_mem_type
128 {
129 TU_MEM_TYPE_VRAM,
130 TU_MEM_TYPE_GTT_WRITE_COMBINE,
131 TU_MEM_TYPE_VRAM_CPU_ACCESS,
132 TU_MEM_TYPE_GTT_CACHED,
133 TU_MEM_TYPE_COUNT
134 };
135
136 #define tu_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
137
138 static inline uint32_t
139 align_u32(uint32_t v, uint32_t a)
140 {
141 assert(a != 0 && a == (a & -a));
142 return (v + a - 1) & ~(a - 1);
143 }
144
145 static inline uint32_t
146 align_u32_npot(uint32_t v, uint32_t a)
147 {
148 return (v + a - 1) / a * a;
149 }
150
151 static inline uint64_t
152 align_u64(uint64_t v, uint64_t a)
153 {
154 assert(a != 0 && a == (a & -a));
155 return (v + a - 1) & ~(a - 1);
156 }
157
158 static inline int32_t
159 align_i32(int32_t v, int32_t a)
160 {
161 assert(a != 0 && a == (a & -a));
162 return (v + a - 1) & ~(a - 1);
163 }
164
165 /** Alignment must be a power of 2. */
166 static inline bool
167 tu_is_aligned(uintmax_t n, uintmax_t a)
168 {
169 assert(a == (a & -a));
170 return (n & (a - 1)) == 0;
171 }
172
173 static inline uint32_t
174 round_up_u32(uint32_t v, uint32_t a)
175 {
176 return (v + a - 1) / a;
177 }
178
179 static inline uint64_t
180 round_up_u64(uint64_t v, uint64_t a)
181 {
182 return (v + a - 1) / a;
183 }
184
185 static inline uint32_t
186 tu_minify(uint32_t n, uint32_t levels)
187 {
188 if (unlikely(n == 0))
189 return 0;
190 else
191 return MAX2(n >> levels, 1);
192 }
193 static inline float
194 tu_clamp_f(float f, float min, float max)
195 {
196 assert(min < max);
197
198 if (f > max)
199 return max;
200 else if (f < min)
201 return min;
202 else
203 return f;
204 }
205
206 static inline bool
207 tu_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
208 {
209 if (*inout_mask & clear_mask) {
210 *inout_mask &= ~clear_mask;
211 return true;
212 } else {
213 return false;
214 }
215 }
216
217 #define for_each_bit(b, dword) \
218 for (uint32_t __dword = (dword); \
219 (b) = __builtin_ffs(__dword) - 1, __dword; __dword &= ~(1 << (b)))
220
221 #define typed_memcpy(dest, src, count) \
222 ({ \
223 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
224 memcpy((dest), (src), (count) * sizeof(*(src))); \
225 })
226
227 #define COND(bool, val) ((bool) ? (val) : 0)
228
229 /* Whenever we generate an error, pass it through this function. Useful for
230 * debugging, where we can break on it. Only call at error site, not when
231 * propagating errors. Might be useful to plug in a stack trace here.
232 */
233
234 struct tu_instance;
235
236 VkResult
237 __vk_errorf(struct tu_instance *instance,
238 VkResult error,
239 const char *file,
240 int line,
241 const char *format,
242 ...);
243
244 #define vk_error(instance, error) \
245 __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
246 #define vk_errorf(instance, error, format, ...) \
247 __vk_errorf(instance, error, __FILE__, __LINE__, format, ##__VA_ARGS__);
248
249 void
250 __tu_finishme(const char *file, int line, const char *format, ...)
251 tu_printflike(3, 4);
252 void
253 tu_loge(const char *format, ...) tu_printflike(1, 2);
254 void
255 tu_loge_v(const char *format, va_list va);
256 void
257 tu_logi(const char *format, ...) tu_printflike(1, 2);
258 void
259 tu_logi_v(const char *format, va_list va);
260
261 /**
262 * Print a FINISHME message, including its source location.
263 */
264 #define tu_finishme(format, ...) \
265 do { \
266 static bool reported = false; \
267 if (!reported) { \
268 __tu_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
269 reported = true; \
270 } \
271 } while (0)
272
273 /* A non-fatal assert. Useful for debugging. */
274 #ifdef DEBUG
275 #define tu_assert(x) \
276 ({ \
277 if (unlikely(!(x))) \
278 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
279 })
280 #else
281 #define tu_assert(x)
282 #endif
283
284 /* Suppress -Wunused in stub functions */
285 #define tu_use_args(...) __tu_use_args(0, ##__VA_ARGS__)
286 static inline void
287 __tu_use_args(int ignore, ...)
288 {
289 }
290
291 #define tu_stub() \
292 do { \
293 tu_finishme("stub %s", __func__); \
294 } while (0)
295
296 void *
297 tu_lookup_entrypoint_unchecked(const char *name);
298 void *
299 tu_lookup_entrypoint_checked(
300 const char *name,
301 uint32_t core_version,
302 const struct tu_instance_extension_table *instance,
303 const struct tu_device_extension_table *device);
304
305 struct tu_physical_device
306 {
307 VK_LOADER_DATA _loader_data;
308
309 struct tu_instance *instance;
310
311 char path[20];
312 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
313 uint8_t driver_uuid[VK_UUID_SIZE];
314 uint8_t device_uuid[VK_UUID_SIZE];
315 uint8_t cache_uuid[VK_UUID_SIZE];
316
317 struct wsi_device wsi_device;
318
319 int local_fd;
320 int master_fd;
321
322 unsigned gpu_id;
323 uint32_t gmem_size;
324 uint64_t gmem_base;
325 uint32_t ccu_offset_gmem;
326 uint32_t ccu_offset_bypass;
327 /* alignment for size of tiles */
328 uint32_t tile_align_w;
329 #define TILE_ALIGN_H 16
330 /* gmem store/load granularity */
331 #define GMEM_ALIGN_W 16
332 #define GMEM_ALIGN_H 4
333
334 struct {
335 uint32_t PC_UNKNOWN_9805;
336 uint32_t SP_UNKNOWN_A0F8;
337 } magic;
338
339 /* This is the drivers on-disk cache used as a fallback as opposed to
340 * the pipeline cache defined by apps.
341 */
342 struct disk_cache *disk_cache;
343
344 struct tu_device_extension_table supported_extensions;
345 };
346
347 enum tu_debug_flags
348 {
349 TU_DEBUG_STARTUP = 1 << 0,
350 TU_DEBUG_NIR = 1 << 1,
351 TU_DEBUG_IR3 = 1 << 2,
352 TU_DEBUG_NOBIN = 1 << 3,
353 TU_DEBUG_SYSMEM = 1 << 4,
354 TU_DEBUG_FORCEBIN = 1 << 5,
355 };
356
357 struct tu_instance
358 {
359 VK_LOADER_DATA _loader_data;
360
361 VkAllocationCallbacks alloc;
362
363 uint32_t api_version;
364 int physical_device_count;
365 struct tu_physical_device physical_devices[TU_MAX_DRM_DEVICES];
366
367 enum tu_debug_flags debug_flags;
368
369 struct vk_debug_report_instance debug_report_callbacks;
370
371 struct tu_instance_extension_table enabled_extensions;
372 };
373
374 VkResult
375 tu_wsi_init(struct tu_physical_device *physical_device);
376 void
377 tu_wsi_finish(struct tu_physical_device *physical_device);
378
379 bool
380 tu_instance_extension_supported(const char *name);
381 uint32_t
382 tu_physical_device_api_version(struct tu_physical_device *dev);
383 bool
384 tu_physical_device_extension_supported(struct tu_physical_device *dev,
385 const char *name);
386
387 struct cache_entry;
388
389 struct tu_pipeline_cache
390 {
391 struct tu_device *device;
392 pthread_mutex_t mutex;
393
394 uint32_t total_size;
395 uint32_t table_size;
396 uint32_t kernel_count;
397 struct cache_entry **hash_table;
398 bool modified;
399
400 VkAllocationCallbacks alloc;
401 };
402
403 struct tu_pipeline_key
404 {
405 };
406
407 void
408 tu_pipeline_cache_init(struct tu_pipeline_cache *cache,
409 struct tu_device *device);
410 void
411 tu_pipeline_cache_finish(struct tu_pipeline_cache *cache);
412 void
413 tu_pipeline_cache_load(struct tu_pipeline_cache *cache,
414 const void *data,
415 size_t size);
416
417 struct tu_shader_variant;
418
419 bool
420 tu_create_shader_variants_from_pipeline_cache(
421 struct tu_device *device,
422 struct tu_pipeline_cache *cache,
423 const unsigned char *sha1,
424 struct tu_shader_variant **variants);
425
426 void
427 tu_pipeline_cache_insert_shaders(struct tu_device *device,
428 struct tu_pipeline_cache *cache,
429 const unsigned char *sha1,
430 struct tu_shader_variant **variants,
431 const void *const *codes,
432 const unsigned *code_sizes);
433
434 struct tu_meta_state
435 {
436 VkAllocationCallbacks alloc;
437
438 struct tu_pipeline_cache cache;
439 };
440
441 /* queue types */
442 #define TU_QUEUE_GENERAL 0
443
444 #define TU_MAX_QUEUE_FAMILIES 1
445
446 struct tu_fence
447 {
448 struct wsi_fence *fence_wsi;
449 bool signaled;
450 int fd;
451 };
452
453 void
454 tu_fence_init(struct tu_fence *fence, bool signaled);
455 void
456 tu_fence_finish(struct tu_fence *fence);
457 void
458 tu_fence_update_fd(struct tu_fence *fence, int fd);
459 void
460 tu_fence_copy(struct tu_fence *fence, const struct tu_fence *src);
461 void
462 tu_fence_signal(struct tu_fence *fence);
463 void
464 tu_fence_wait_idle(struct tu_fence *fence);
465
466 struct tu_queue
467 {
468 VK_LOADER_DATA _loader_data;
469 struct tu_device *device;
470 uint32_t queue_family_index;
471 int queue_idx;
472 VkDeviceQueueCreateFlags flags;
473
474 uint32_t msm_queue_id;
475 struct tu_fence submit_fence;
476 };
477
478 struct tu_bo
479 {
480 uint32_t gem_handle;
481 uint64_t size;
482 uint64_t iova;
483 void *map;
484 };
485
486 struct tu_device
487 {
488 VK_LOADER_DATA _loader_data;
489
490 VkAllocationCallbacks alloc;
491
492 struct tu_instance *instance;
493
494 struct tu_meta_state meta_state;
495
496 struct tu_queue *queues[TU_MAX_QUEUE_FAMILIES];
497 int queue_count[TU_MAX_QUEUE_FAMILIES];
498
499 struct tu_physical_device *physical_device;
500
501 struct ir3_compiler *compiler;
502
503 /* Backup in-memory cache to be used if the app doesn't provide one */
504 struct tu_pipeline_cache *mem_cache;
505
506 struct tu_bo vsc_draw_strm;
507 struct tu_bo vsc_prim_strm;
508 uint32_t vsc_draw_strm_pitch;
509 uint32_t vsc_prim_strm_pitch;
510
511 struct tu_bo border_color;
512
513 struct list_head shader_slabs;
514 mtx_t shader_slab_mutex;
515
516 struct tu_device_extension_table enabled_extensions;
517 };
518
519 VkResult
520 tu_bo_init_new(struct tu_device *dev, struct tu_bo *bo, uint64_t size);
521 VkResult
522 tu_bo_init_dmabuf(struct tu_device *dev,
523 struct tu_bo *bo,
524 uint64_t size,
525 int fd);
526 int
527 tu_bo_export_dmabuf(struct tu_device *dev, struct tu_bo *bo);
528 void
529 tu_bo_finish(struct tu_device *dev, struct tu_bo *bo);
530 VkResult
531 tu_bo_map(struct tu_device *dev, struct tu_bo *bo);
532
533 struct tu_cs_entry
534 {
535 /* No ownership */
536 const struct tu_bo *bo;
537
538 uint32_t size;
539 uint32_t offset;
540 };
541
542 struct ts_cs_memory {
543 uint32_t *map;
544 uint64_t iova;
545 };
546
547 enum tu_cs_mode
548 {
549
550 /*
551 * A command stream in TU_CS_MODE_GROW mode grows automatically whenever it
552 * is full. tu_cs_begin must be called before command packet emission and
553 * tu_cs_end must be called after.
554 *
555 * This mode may create multiple entries internally. The entries must be
556 * submitted together.
557 */
558 TU_CS_MODE_GROW,
559
560 /*
561 * A command stream in TU_CS_MODE_EXTERNAL mode wraps an external,
562 * fixed-size buffer. tu_cs_begin and tu_cs_end are optional and have no
563 * effect on it.
564 *
565 * This mode does not create any entry or any BO.
566 */
567 TU_CS_MODE_EXTERNAL,
568
569 /*
570 * A command stream in TU_CS_MODE_SUB_STREAM mode does not support direct
571 * command packet emission. tu_cs_begin_sub_stream must be called to get a
572 * sub-stream to emit comamnd packets to. When done with the sub-stream,
573 * tu_cs_end_sub_stream must be called.
574 *
575 * This mode does not create any entry internally.
576 */
577 TU_CS_MODE_SUB_STREAM,
578 };
579
580 struct tu_cs
581 {
582 uint32_t *start;
583 uint32_t *cur;
584 uint32_t *reserved_end;
585 uint32_t *end;
586
587 struct tu_device *device;
588 enum tu_cs_mode mode;
589 uint32_t next_bo_size;
590
591 struct tu_cs_entry *entries;
592 uint32_t entry_count;
593 uint32_t entry_capacity;
594
595 struct tu_bo **bos;
596 uint32_t bo_count;
597 uint32_t bo_capacity;
598
599 /* state for cond_exec_start/cond_exec_end */
600 uint32_t cond_flags;
601 uint32_t *cond_dwords;
602 };
603
604 struct tu_device_memory
605 {
606 struct tu_bo bo;
607 VkDeviceSize size;
608
609 /* for dedicated allocations */
610 struct tu_image *image;
611 struct tu_buffer *buffer;
612
613 uint32_t type_index;
614 void *map;
615 void *user_ptr;
616 };
617
618 struct tu_descriptor_range
619 {
620 uint64_t va;
621 uint32_t size;
622 };
623
624 struct tu_descriptor_set
625 {
626 const struct tu_descriptor_set_layout *layout;
627 struct tu_descriptor_pool *pool;
628 uint32_t size;
629
630 uint64_t va;
631 uint32_t *mapped_ptr;
632
633 uint32_t *dynamic_descriptors;
634
635 struct tu_bo *buffers[0];
636 };
637
638 struct tu_push_descriptor_set
639 {
640 struct tu_descriptor_set set;
641 uint32_t capacity;
642 };
643
644 struct tu_descriptor_pool_entry
645 {
646 uint32_t offset;
647 uint32_t size;
648 struct tu_descriptor_set *set;
649 };
650
651 struct tu_descriptor_pool
652 {
653 struct tu_bo bo;
654 uint64_t current_offset;
655 uint64_t size;
656
657 uint8_t *host_memory_base;
658 uint8_t *host_memory_ptr;
659 uint8_t *host_memory_end;
660
661 uint32_t entry_count;
662 uint32_t max_entry_count;
663 struct tu_descriptor_pool_entry entries[0];
664 };
665
666 struct tu_descriptor_update_template_entry
667 {
668 VkDescriptorType descriptor_type;
669
670 /* The number of descriptors to update */
671 uint32_t descriptor_count;
672
673 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array
674 */
675 uint32_t dst_offset;
676
677 /* In dwords. Not valid/used for dynamic descriptors */
678 uint32_t dst_stride;
679
680 uint32_t buffer_offset;
681
682 /* Only valid for combined image samplers and samplers */
683 uint16_t has_sampler;
684
685 /* In bytes */
686 size_t src_offset;
687 size_t src_stride;
688
689 /* For push descriptors */
690 const uint32_t *immutable_samplers;
691 };
692
693 struct tu_descriptor_update_template
694 {
695 uint32_t entry_count;
696 struct tu_descriptor_update_template_entry entry[0];
697 };
698
699 struct tu_buffer
700 {
701 VkDeviceSize size;
702
703 VkBufferUsageFlags usage;
704 VkBufferCreateFlags flags;
705
706 struct tu_bo *bo;
707 VkDeviceSize bo_offset;
708 };
709
710 static inline uint64_t
711 tu_buffer_iova(struct tu_buffer *buffer)
712 {
713 return buffer->bo->iova + buffer->bo_offset;
714 }
715
716 enum tu_dynamic_state_bits
717 {
718 TU_DYNAMIC_VIEWPORT = 1 << 0,
719 TU_DYNAMIC_SCISSOR = 1 << 1,
720 TU_DYNAMIC_LINE_WIDTH = 1 << 2,
721 TU_DYNAMIC_DEPTH_BIAS = 1 << 3,
722 TU_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
723 TU_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
724 TU_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
725 TU_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
726 TU_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
727 TU_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
728 TU_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
729 TU_DYNAMIC_ALL = (1 << 11) - 1,
730 };
731
732 struct tu_vertex_binding
733 {
734 struct tu_buffer *buffer;
735 VkDeviceSize offset;
736 };
737
738 struct tu_viewport_state
739 {
740 uint32_t count;
741 VkViewport viewports[MAX_VIEWPORTS];
742 };
743
744 struct tu_scissor_state
745 {
746 uint32_t count;
747 VkRect2D scissors[MAX_SCISSORS];
748 };
749
750 struct tu_discard_rectangle_state
751 {
752 uint32_t count;
753 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
754 };
755
756 struct tu_dynamic_state
757 {
758 /**
759 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
760 * Defines the set of saved dynamic state.
761 */
762 uint32_t mask;
763
764 struct tu_viewport_state viewport;
765
766 struct tu_scissor_state scissor;
767
768 float line_width;
769
770 struct
771 {
772 float bias;
773 float clamp;
774 float slope;
775 } depth_bias;
776
777 float blend_constants[4];
778
779 struct
780 {
781 float min;
782 float max;
783 } depth_bounds;
784
785 struct
786 {
787 uint32_t front;
788 uint32_t back;
789 } stencil_compare_mask;
790
791 struct
792 {
793 uint32_t front;
794 uint32_t back;
795 } stencil_write_mask;
796
797 struct
798 {
799 uint32_t front;
800 uint32_t back;
801 } stencil_reference;
802
803 struct tu_discard_rectangle_state discard_rectangle;
804 };
805
806 extern const struct tu_dynamic_state default_dynamic_state;
807
808 const char *
809 tu_get_debug_option_name(int id);
810
811 const char *
812 tu_get_perftest_option_name(int id);
813
814 struct tu_descriptor_state
815 {
816 struct tu_descriptor_set *sets[MAX_SETS];
817 uint32_t valid;
818 struct tu_push_descriptor_set push_set;
819 bool push_dirty;
820 uint32_t dynamic_descriptors[MAX_DYNAMIC_BUFFERS * A6XX_TEX_CONST_DWORDS];
821 uint32_t input_attachments[MAX_RTS * A6XX_TEX_CONST_DWORDS];
822 };
823
824 struct tu_tile
825 {
826 uint8_t pipe;
827 uint8_t slot;
828 VkOffset2D begin;
829 VkOffset2D end;
830 };
831
832 struct tu_tiling_config
833 {
834 VkRect2D render_area;
835
836 /* position and size of the first tile */
837 VkRect2D tile0;
838 /* number of tiles */
839 VkExtent2D tile_count;
840
841 /* size of the first VSC pipe */
842 VkExtent2D pipe0;
843 /* number of VSC pipes */
844 VkExtent2D pipe_count;
845
846 /* pipe register values */
847 uint32_t pipe_config[MAX_VSC_PIPES];
848 uint32_t pipe_sizes[MAX_VSC_PIPES];
849
850 /* Whether sysmem rendering must be used */
851 bool force_sysmem;
852 };
853
854 enum tu_cmd_dirty_bits
855 {
856 TU_CMD_DIRTY_PIPELINE = 1 << 0,
857 TU_CMD_DIRTY_COMPUTE_PIPELINE = 1 << 1,
858 TU_CMD_DIRTY_VERTEX_BUFFERS = 1 << 2,
859 TU_CMD_DIRTY_DESCRIPTOR_SETS = 1 << 3,
860 TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS = 1 << 4,
861 TU_CMD_DIRTY_PUSH_CONSTANTS = 1 << 5,
862 TU_CMD_DIRTY_STREAMOUT_BUFFERS = 1 << 6,
863 TU_CMD_DIRTY_INPUT_ATTACHMENTS = 1 << 7,
864
865 TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 16,
866 TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 17,
867 TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 18,
868 TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 19,
869 TU_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 20,
870 TU_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 21,
871 };
872
873 struct tu_streamout_state {
874 uint16_t stride[IR3_MAX_SO_BUFFERS];
875 uint32_t ncomp[IR3_MAX_SO_BUFFERS];
876 uint32_t prog[IR3_MAX_SO_OUTPUTS * 2];
877 uint32_t prog_count;
878 uint32_t vpc_so_buf_cntl;
879 };
880
881 struct tu_cmd_state
882 {
883 uint32_t dirty;
884
885 struct tu_pipeline *pipeline;
886 struct tu_pipeline *compute_pipeline;
887
888 /* Vertex buffers */
889 struct
890 {
891 struct tu_buffer *buffers[MAX_VBS];
892 VkDeviceSize offsets[MAX_VBS];
893 } vb;
894
895 struct tu_dynamic_state dynamic;
896
897 /* Stream output buffers */
898 struct
899 {
900 struct tu_buffer *buffers[IR3_MAX_SO_BUFFERS];
901 VkDeviceSize offsets[IR3_MAX_SO_BUFFERS];
902 VkDeviceSize sizes[IR3_MAX_SO_BUFFERS];
903 } streamout_buf;
904
905 uint8_t streamout_reset;
906 uint8_t streamout_enabled;
907
908 /* Index buffer */
909 struct tu_buffer *index_buffer;
910 uint64_t index_offset;
911 uint32_t index_type;
912 uint32_t max_index_count;
913 uint64_t index_va;
914
915 const struct tu_render_pass *pass;
916 const struct tu_subpass *subpass;
917 const struct tu_framebuffer *framebuffer;
918
919 struct tu_tiling_config tiling_config;
920
921 struct tu_cs_entry tile_store_ib;
922 };
923
924 struct tu_cmd_pool
925 {
926 VkAllocationCallbacks alloc;
927 struct list_head cmd_buffers;
928 struct list_head free_cmd_buffers;
929 uint32_t queue_family_index;
930 };
931
932 struct tu_cmd_buffer_upload
933 {
934 uint8_t *map;
935 unsigned offset;
936 uint64_t size;
937 struct list_head list;
938 };
939
940 enum tu_cmd_buffer_status
941 {
942 TU_CMD_BUFFER_STATUS_INVALID,
943 TU_CMD_BUFFER_STATUS_INITIAL,
944 TU_CMD_BUFFER_STATUS_RECORDING,
945 TU_CMD_BUFFER_STATUS_EXECUTABLE,
946 TU_CMD_BUFFER_STATUS_PENDING,
947 };
948
949 struct tu_bo_list
950 {
951 uint32_t count;
952 uint32_t capacity;
953 struct drm_msm_gem_submit_bo *bo_infos;
954 };
955
956 #define TU_BO_LIST_FAILED (~0)
957
958 void
959 tu_bo_list_init(struct tu_bo_list *list);
960 void
961 tu_bo_list_destroy(struct tu_bo_list *list);
962 void
963 tu_bo_list_reset(struct tu_bo_list *list);
964 uint32_t
965 tu_bo_list_add(struct tu_bo_list *list,
966 const struct tu_bo *bo,
967 uint32_t flags);
968 VkResult
969 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other);
970
971 /* This struct defines the layout of the scratch_bo */
972 struct tu6_control
973 {
974 uint32_t seqno; /* seqno for async CP_EVENT_WRITE, etc */
975 uint32_t _pad0;
976 volatile uint32_t vsc_overflow;
977 uint32_t _pad1;
978 /* flag set from cmdstream when VSC overflow detected: */
979 uint32_t vsc_scratch;
980 uint32_t _pad2;
981 uint32_t _pad3;
982 uint32_t _pad4;
983
984 /* scratch space for VPC_SO[i].FLUSH_BASE_LO/HI, start on 32 byte boundary. */
985 struct {
986 uint32_t offset;
987 uint32_t pad[7];
988 } flush_base[4];
989 };
990
991 #define ctrl_offset(member) offsetof(struct tu6_control, member)
992
993 struct tu_cmd_buffer
994 {
995 VK_LOADER_DATA _loader_data;
996
997 struct tu_device *device;
998
999 struct tu_cmd_pool *pool;
1000 struct list_head pool_link;
1001
1002 VkCommandBufferUsageFlags usage_flags;
1003 VkCommandBufferLevel level;
1004 enum tu_cmd_buffer_status status;
1005
1006 struct tu_cmd_state state;
1007 struct tu_vertex_binding vertex_bindings[MAX_VBS];
1008 uint32_t queue_family_index;
1009
1010 uint32_t push_constants[MAX_PUSH_CONSTANTS_SIZE / 4];
1011 VkShaderStageFlags push_constant_stages;
1012 struct tu_descriptor_set meta_push_descriptors;
1013
1014 struct tu_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1015
1016 struct tu_cmd_buffer_upload upload;
1017
1018 VkResult record_result;
1019
1020 struct tu_bo_list bo_list;
1021 struct tu_cs cs;
1022 struct tu_cs draw_cs;
1023 struct tu_cs draw_epilogue_cs;
1024 struct tu_cs sub_cs;
1025
1026 struct tu_bo scratch_bo;
1027 uint32_t scratch_seqno;
1028
1029 struct tu_bo vsc_draw_strm;
1030 struct tu_bo vsc_prim_strm;
1031 uint32_t vsc_draw_strm_pitch;
1032 uint32_t vsc_prim_strm_pitch;
1033 bool use_vsc_data;
1034
1035 bool wait_for_idle;
1036 };
1037
1038 /* Temporary struct for tracking a register state to be written, used by
1039 * a6xx-pack.h and tu_cs_emit_regs()
1040 */
1041 struct tu_reg_value {
1042 uint32_t reg;
1043 uint64_t value;
1044 bool is_address;
1045 struct tu_bo *bo;
1046 bool bo_write;
1047 uint32_t bo_offset;
1048 uint32_t bo_shift;
1049 };
1050
1051 unsigned
1052 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
1053 struct tu_cs *cs,
1054 enum vgt_event_type event,
1055 bool need_seqno);
1056
1057 bool
1058 tu_get_memory_fd(struct tu_device *device,
1059 struct tu_device_memory *memory,
1060 int *pFD);
1061
1062 static inline struct tu_descriptor_state *
1063 tu_get_descriptors_state(struct tu_cmd_buffer *cmd_buffer,
1064 VkPipelineBindPoint bind_point)
1065 {
1066 return &cmd_buffer->descriptors[bind_point];
1067 }
1068
1069 /*
1070 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1071 *
1072 * Limitations: Can't call normal dispatch functions without binding or
1073 * rebinding
1074 * the compute pipeline.
1075 */
1076 void
1077 tu_unaligned_dispatch(struct tu_cmd_buffer *cmd_buffer,
1078 uint32_t x,
1079 uint32_t y,
1080 uint32_t z);
1081
1082 struct tu_event
1083 {
1084 struct tu_bo bo;
1085 };
1086
1087 struct tu_shader_module;
1088
1089 #define TU_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1090 #define TU_HASH_SHADER_SISCHED (1 << 1)
1091 #define TU_HASH_SHADER_UNSAFE_MATH (1 << 2)
1092 void
1093 tu_hash_shaders(unsigned char *hash,
1094 const VkPipelineShaderStageCreateInfo **stages,
1095 const struct tu_pipeline_layout *layout,
1096 const struct tu_pipeline_key *key,
1097 uint32_t flags);
1098
1099 static inline gl_shader_stage
1100 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1101 {
1102 assert(__builtin_popcount(vk_stage) == 1);
1103 return ffs(vk_stage) - 1;
1104 }
1105
1106 static inline VkShaderStageFlagBits
1107 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1108 {
1109 return (1 << mesa_stage);
1110 }
1111
1112 #define TU_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1113
1114 #define tu_foreach_stage(stage, stage_bits) \
1115 for (gl_shader_stage stage, \
1116 __tmp = (gl_shader_stage)((stage_bits) &TU_STAGE_MASK); \
1117 stage = __builtin_ffs(__tmp) - 1, __tmp; __tmp &= ~(1 << (stage)))
1118
1119 struct tu_shader_module
1120 {
1121 unsigned char sha1[20];
1122
1123 uint32_t code_size;
1124 const uint32_t *code[0];
1125 };
1126
1127 struct tu_shader_compile_options
1128 {
1129 struct ir3_shader_key key;
1130
1131 bool optimize;
1132 bool include_binning_pass;
1133 };
1134
1135 struct tu_push_constant_range
1136 {
1137 uint32_t lo;
1138 uint32_t count;
1139 };
1140
1141 struct tu_shader
1142 {
1143 struct ir3_shader ir3_shader;
1144
1145 struct tu_push_constant_range push_consts;
1146 unsigned attachment_idx[MAX_RTS];
1147
1148 /* This may be true for vertex shaders. When true, variants[1] is the
1149 * binning variant and binning_binary is non-NULL.
1150 */
1151 bool has_binning_pass;
1152
1153 void *binary;
1154 void *binning_binary;
1155
1156 struct ir3_shader_variant variants[0];
1157 };
1158
1159 struct tu_shader *
1160 tu_shader_create(struct tu_device *dev,
1161 gl_shader_stage stage,
1162 const VkPipelineShaderStageCreateInfo *stage_info,
1163 struct tu_pipeline_layout *layout,
1164 const VkAllocationCallbacks *alloc);
1165
1166 void
1167 tu_shader_destroy(struct tu_device *dev,
1168 struct tu_shader *shader,
1169 const VkAllocationCallbacks *alloc);
1170
1171 void
1172 tu_shader_compile_options_init(
1173 struct tu_shader_compile_options *options,
1174 const VkGraphicsPipelineCreateInfo *pipeline_info);
1175
1176 VkResult
1177 tu_shader_compile(struct tu_device *dev,
1178 struct tu_shader *shader,
1179 const struct tu_shader *next_stage,
1180 const struct tu_shader_compile_options *options,
1181 const VkAllocationCallbacks *alloc);
1182
1183 struct tu_program_descriptor_linkage
1184 {
1185 struct ir3_ubo_analysis_state ubo_state;
1186 struct ir3_const_state const_state;
1187
1188 uint32_t constlen;
1189
1190 struct tu_push_constant_range push_consts;
1191 };
1192
1193 struct tu_pipeline
1194 {
1195 struct tu_cs cs;
1196
1197 struct tu_dynamic_state dynamic_state;
1198
1199 struct tu_pipeline_layout *layout;
1200
1201 bool need_indirect_descriptor_sets;
1202 VkShaderStageFlags active_stages;
1203
1204 struct tu_streamout_state streamout;
1205
1206 struct
1207 {
1208 struct tu_bo binary_bo;
1209 struct tu_cs_entry state_ib;
1210 struct tu_cs_entry binning_state_ib;
1211
1212 struct tu_program_descriptor_linkage link[MESA_SHADER_STAGES];
1213 unsigned input_attachment_idx[MAX_RTS];
1214 } program;
1215
1216 struct
1217 {
1218 struct tu_cs_entry state_ib;
1219 } load_state;
1220
1221 struct
1222 {
1223 uint8_t bindings[MAX_VERTEX_ATTRIBS];
1224 uint32_t count;
1225
1226 uint8_t binning_bindings[MAX_VERTEX_ATTRIBS];
1227 uint32_t binning_count;
1228
1229 struct tu_cs_entry state_ib;
1230 struct tu_cs_entry binning_state_ib;
1231 } vi;
1232
1233 struct
1234 {
1235 enum pc_di_primtype primtype;
1236 bool primitive_restart;
1237 } ia;
1238
1239 struct
1240 {
1241 struct tu_cs_entry state_ib;
1242 } vp;
1243
1244 struct
1245 {
1246 uint32_t gras_su_cntl;
1247 struct tu_cs_entry state_ib;
1248 } rast;
1249
1250 struct
1251 {
1252 struct tu_cs_entry state_ib;
1253 } ds;
1254
1255 struct
1256 {
1257 struct tu_cs_entry state_ib;
1258 } blend;
1259
1260 struct
1261 {
1262 uint32_t local_size[3];
1263 } compute;
1264 };
1265
1266 void
1267 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport);
1268
1269 void
1270 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor);
1271
1272 void
1273 tu6_emit_sample_locations(struct tu_cs *cs, const VkSampleLocationsInfoEXT *samp_loc);
1274
1275 void
1276 tu6_emit_gras_su_cntl(struct tu_cs *cs,
1277 uint32_t gras_su_cntl,
1278 float line_width);
1279
1280 void
1281 tu6_emit_depth_bias(struct tu_cs *cs,
1282 float constant_factor,
1283 float clamp,
1284 float slope_factor);
1285
1286 void
1287 tu6_emit_stencil_compare_mask(struct tu_cs *cs,
1288 uint32_t front,
1289 uint32_t back);
1290
1291 void
1292 tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back);
1293
1294 void
1295 tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back);
1296
1297 void
1298 tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4]);
1299
1300 void tu6_emit_msaa(struct tu_cs *cs, VkSampleCountFlagBits samples);
1301
1302 void tu6_emit_window_scissor(struct tu_cs *cs, uint32_t x1, uint32_t y1, uint32_t x2, uint32_t y2);
1303
1304 void tu6_emit_window_offset(struct tu_cs *cs, uint32_t x1, uint32_t y1);
1305
1306 struct tu_image_view;
1307
1308 void
1309 tu_resolve_sysmem(struct tu_cmd_buffer *cmd,
1310 struct tu_cs *cs,
1311 struct tu_image_view *src,
1312 struct tu_image_view *dst,
1313 uint32_t layers,
1314 const VkRect2D *rect);
1315
1316 void
1317 tu_clear_sysmem_attachment(struct tu_cmd_buffer *cmd,
1318 struct tu_cs *cs,
1319 uint32_t a,
1320 const VkRenderPassBeginInfo *info);
1321
1322 void
1323 tu_clear_gmem_attachment(struct tu_cmd_buffer *cmd,
1324 struct tu_cs *cs,
1325 uint32_t a,
1326 const VkRenderPassBeginInfo *info);
1327
1328 void
1329 tu_load_gmem_attachment(struct tu_cmd_buffer *cmd,
1330 struct tu_cs *cs,
1331 uint32_t a,
1332 bool force_load);
1333
1334 /* expose this function to be able to emit load without checking LOAD_OP */
1335 void
1336 tu_emit_load_gmem_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t a);
1337
1338 /* note: gmem store can also resolve */
1339 void
1340 tu_store_gmem_attachment(struct tu_cmd_buffer *cmd,
1341 struct tu_cs *cs,
1342 uint32_t a,
1343 uint32_t gmem_a);
1344
1345 struct tu_userdata_info *
1346 tu_lookup_user_sgpr(struct tu_pipeline *pipeline,
1347 gl_shader_stage stage,
1348 int idx);
1349
1350 struct tu_shader_variant *
1351 tu_get_shader(struct tu_pipeline *pipeline, gl_shader_stage stage);
1352
1353 struct tu_graphics_pipeline_create_info
1354 {
1355 bool use_rectlist;
1356 bool db_depth_clear;
1357 bool db_stencil_clear;
1358 bool db_depth_disable_expclear;
1359 bool db_stencil_disable_expclear;
1360 bool db_flush_depth_inplace;
1361 bool db_flush_stencil_inplace;
1362 bool db_resummarize;
1363 uint32_t custom_blend_mode;
1364 };
1365
1366 enum tu_supported_formats {
1367 FMT_VERTEX = 1,
1368 FMT_TEXTURE = 2,
1369 FMT_COLOR = 4,
1370 };
1371
1372 struct tu_native_format
1373 {
1374 enum a6xx_format fmt : 8;
1375 enum a3xx_color_swap swap : 8;
1376 enum a6xx_tile_mode tile_mode : 8;
1377 enum tu_supported_formats supported : 8;
1378 };
1379
1380 struct tu_native_format tu6_format_vtx(VkFormat format);
1381 struct tu_native_format tu6_format_color(VkFormat format, enum a6xx_tile_mode tile_mode);
1382 struct tu_native_format tu6_format_texture(VkFormat format, enum a6xx_tile_mode tile_mode);
1383
1384 static inline enum a6xx_format
1385 tu6_base_format(VkFormat format)
1386 {
1387 /* note: tu6_format_color doesn't care about tiling for .fmt field */
1388 return tu6_format_color(format, TILE6_LINEAR).fmt;
1389 }
1390
1391 enum a6xx_depth_format tu6_pipe2depth(VkFormat format);
1392
1393 struct tu_image
1394 {
1395 VkImageType type;
1396 /* The original VkFormat provided by the client. This may not match any
1397 * of the actual surface formats.
1398 */
1399 VkFormat vk_format;
1400 VkImageAspectFlags aspects;
1401 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1402 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1403 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1404 VkExtent3D extent;
1405 uint32_t level_count;
1406 uint32_t layer_count;
1407 VkSampleCountFlagBits samples;
1408
1409 struct fdl_layout layout;
1410
1411 unsigned queue_family_mask;
1412 bool exclusive;
1413 bool shareable;
1414
1415 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1416 VkDeviceMemory owned_memory;
1417
1418 /* Set when bound */
1419 struct tu_bo *bo;
1420 VkDeviceSize bo_offset;
1421 };
1422
1423 unsigned
1424 tu_image_queue_family_mask(const struct tu_image *image,
1425 uint32_t family,
1426 uint32_t queue_family);
1427
1428 static inline uint32_t
1429 tu_get_layerCount(const struct tu_image *image,
1430 const VkImageSubresourceRange *range)
1431 {
1432 return range->layerCount == VK_REMAINING_ARRAY_LAYERS
1433 ? image->layer_count - range->baseArrayLayer
1434 : range->layerCount;
1435 }
1436
1437 static inline uint32_t
1438 tu_get_levelCount(const struct tu_image *image,
1439 const VkImageSubresourceRange *range)
1440 {
1441 return range->levelCount == VK_REMAINING_MIP_LEVELS
1442 ? image->level_count - range->baseMipLevel
1443 : range->levelCount;
1444 }
1445
1446 enum a3xx_msaa_samples
1447 tu_msaa_samples(uint32_t samples);
1448 enum a6xx_tex_fetchsize
1449 tu6_fetchsize(VkFormat format);
1450
1451 struct tu_image_view
1452 {
1453 struct tu_image *image; /**< VkImageViewCreateInfo::image */
1454
1455 uint64_t base_addr;
1456 uint64_t ubwc_addr;
1457 uint32_t layer_size;
1458 uint32_t ubwc_layer_size;
1459
1460 /* used to determine if fast gmem store path can be used */
1461 VkExtent2D extent;
1462 bool need_y2_align;
1463
1464 bool ubwc_enabled;
1465
1466 uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
1467
1468 /* Descriptor for use as a storage image as opposed to a sampled image.
1469 * This has a few differences for cube maps (e.g. type).
1470 */
1471 uint32_t storage_descriptor[A6XX_TEX_CONST_DWORDS];
1472
1473 /* pre-filled register values */
1474 uint32_t PITCH;
1475 uint32_t FLAG_BUFFER_PITCH;
1476
1477 uint32_t RB_MRT_BUF_INFO;
1478 uint32_t SP_FS_MRT_REG;
1479
1480 uint32_t SP_PS_2D_SRC_INFO;
1481 uint32_t SP_PS_2D_SRC_SIZE;
1482
1483 uint32_t RB_2D_DST_INFO;
1484
1485 uint32_t RB_BLIT_DST_INFO;
1486 };
1487
1488 struct tu_sampler {
1489 uint32_t descriptor[A6XX_TEX_SAMP_DWORDS];
1490 };
1491
1492 void
1493 tu_cs_image_ref(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer);
1494
1495 void
1496 tu_cs_image_ref_2d(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer, bool src);
1497
1498 void
1499 tu_cs_image_flag_ref(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer);
1500
1501 VkResult
1502 tu_image_create(VkDevice _device,
1503 const VkImageCreateInfo *pCreateInfo,
1504 const VkAllocationCallbacks *alloc,
1505 VkImage *pImage,
1506 uint64_t modifier);
1507
1508 VkResult
1509 tu_image_from_gralloc(VkDevice device_h,
1510 const VkImageCreateInfo *base_info,
1511 const VkNativeBufferANDROID *gralloc_info,
1512 const VkAllocationCallbacks *alloc,
1513 VkImage *out_image_h);
1514
1515 void
1516 tu_image_view_init(struct tu_image_view *view,
1517 const VkImageViewCreateInfo *pCreateInfo);
1518
1519 struct tu_buffer_view
1520 {
1521 uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
1522
1523 struct tu_buffer *buffer;
1524 };
1525 void
1526 tu_buffer_view_init(struct tu_buffer_view *view,
1527 struct tu_device *device,
1528 const VkBufferViewCreateInfo *pCreateInfo);
1529
1530 static inline struct VkExtent3D
1531 tu_sanitize_image_extent(const VkImageType imageType,
1532 const struct VkExtent3D imageExtent)
1533 {
1534 switch (imageType) {
1535 case VK_IMAGE_TYPE_1D:
1536 return (VkExtent3D) { imageExtent.width, 1, 1 };
1537 case VK_IMAGE_TYPE_2D:
1538 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1539 case VK_IMAGE_TYPE_3D:
1540 return imageExtent;
1541 default:
1542 unreachable("invalid image type");
1543 }
1544 }
1545
1546 static inline struct VkOffset3D
1547 tu_sanitize_image_offset(const VkImageType imageType,
1548 const struct VkOffset3D imageOffset)
1549 {
1550 switch (imageType) {
1551 case VK_IMAGE_TYPE_1D:
1552 return (VkOffset3D) { imageOffset.x, 0, 0 };
1553 case VK_IMAGE_TYPE_2D:
1554 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1555 case VK_IMAGE_TYPE_3D:
1556 return imageOffset;
1557 default:
1558 unreachable("invalid image type");
1559 }
1560 }
1561
1562 struct tu_attachment_info
1563 {
1564 struct tu_image_view *attachment;
1565 };
1566
1567 struct tu_framebuffer
1568 {
1569 uint32_t width;
1570 uint32_t height;
1571 uint32_t layers;
1572
1573 uint32_t attachment_count;
1574 struct tu_attachment_info attachments[0];
1575 };
1576
1577 struct tu_subpass_attachment
1578 {
1579 uint32_t attachment;
1580 };
1581
1582 struct tu_subpass
1583 {
1584 uint32_t input_count;
1585 uint32_t color_count;
1586 struct tu_subpass_attachment *input_attachments;
1587 struct tu_subpass_attachment *color_attachments;
1588 struct tu_subpass_attachment *resolve_attachments;
1589 struct tu_subpass_attachment depth_stencil_attachment;
1590
1591 VkSampleCountFlagBits samples;
1592
1593 /* pre-filled register values */
1594 uint32_t render_components;
1595 uint32_t srgb_cntl;
1596 };
1597
1598 struct tu_render_pass_attachment
1599 {
1600 VkFormat format;
1601 uint32_t samples;
1602 uint32_t cpp;
1603 VkImageAspectFlags clear_mask;
1604 bool load;
1605 bool store;
1606 int32_t gmem_offset;
1607 };
1608
1609 struct tu_render_pass
1610 {
1611 uint32_t attachment_count;
1612 uint32_t subpass_count;
1613 uint32_t gmem_pixels;
1614 uint32_t tile_align_w;
1615 struct tu_subpass_attachment *subpass_attachments;
1616 struct tu_render_pass_attachment *attachments;
1617 struct tu_subpass subpasses[0];
1618 };
1619
1620 VkResult
1621 tu_device_init_meta(struct tu_device *device);
1622 void
1623 tu_device_finish_meta(struct tu_device *device);
1624
1625 struct tu_query_pool
1626 {
1627 VkQueryType type;
1628 uint32_t stride;
1629 uint64_t size;
1630 uint32_t pipeline_statistics;
1631 struct tu_bo bo;
1632 };
1633
1634 struct tu_semaphore
1635 {
1636 uint32_t syncobj;
1637 uint32_t temp_syncobj;
1638 };
1639
1640 void
1641 tu_set_descriptor_set(struct tu_cmd_buffer *cmd_buffer,
1642 VkPipelineBindPoint bind_point,
1643 struct tu_descriptor_set *set,
1644 unsigned idx);
1645
1646 void
1647 tu_update_descriptor_sets(struct tu_device *device,
1648 struct tu_cmd_buffer *cmd_buffer,
1649 VkDescriptorSet overrideSet,
1650 uint32_t descriptorWriteCount,
1651 const VkWriteDescriptorSet *pDescriptorWrites,
1652 uint32_t descriptorCopyCount,
1653 const VkCopyDescriptorSet *pDescriptorCopies);
1654
1655 void
1656 tu_update_descriptor_set_with_template(
1657 struct tu_device *device,
1658 struct tu_cmd_buffer *cmd_buffer,
1659 struct tu_descriptor_set *set,
1660 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
1661 const void *pData);
1662
1663 void
1664 tu_meta_push_descriptor_set(struct tu_cmd_buffer *cmd_buffer,
1665 VkPipelineBindPoint pipelineBindPoint,
1666 VkPipelineLayout _layout,
1667 uint32_t set,
1668 uint32_t descriptorWriteCount,
1669 const VkWriteDescriptorSet *pDescriptorWrites);
1670
1671 int
1672 tu_drm_get_gpu_id(const struct tu_physical_device *dev, uint32_t *id);
1673
1674 int
1675 tu_drm_get_gmem_size(const struct tu_physical_device *dev, uint32_t *size);
1676
1677 int
1678 tu_drm_get_gmem_base(const struct tu_physical_device *dev, uint64_t *base);
1679
1680 int
1681 tu_drm_submitqueue_new(const struct tu_device *dev,
1682 int priority,
1683 uint32_t *queue_id);
1684
1685 void
1686 tu_drm_submitqueue_close(const struct tu_device *dev, uint32_t queue_id);
1687
1688 uint32_t
1689 tu_gem_new(const struct tu_device *dev, uint64_t size, uint32_t flags);
1690 uint32_t
1691 tu_gem_import_dmabuf(const struct tu_device *dev,
1692 int prime_fd,
1693 uint64_t size);
1694 int
1695 tu_gem_export_dmabuf(const struct tu_device *dev, uint32_t gem_handle);
1696 void
1697 tu_gem_close(const struct tu_device *dev, uint32_t gem_handle);
1698 uint64_t
1699 tu_gem_info_offset(const struct tu_device *dev, uint32_t gem_handle);
1700 uint64_t
1701 tu_gem_info_iova(const struct tu_device *dev, uint32_t gem_handle);
1702
1703 #define TU_DEFINE_HANDLE_CASTS(__tu_type, __VkType) \
1704 \
1705 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1706 { \
1707 return (struct __tu_type *) _handle; \
1708 } \
1709 \
1710 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1711 { \
1712 return (__VkType) _obj; \
1713 }
1714
1715 #define TU_DEFINE_NONDISP_HANDLE_CASTS(__tu_type, __VkType) \
1716 \
1717 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1718 { \
1719 return (struct __tu_type *) (uintptr_t) _handle; \
1720 } \
1721 \
1722 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1723 { \
1724 return (__VkType)(uintptr_t) _obj; \
1725 }
1726
1727 #define TU_FROM_HANDLE(__tu_type, __name, __handle) \
1728 struct __tu_type *__name = __tu_type##_from_handle(__handle)
1729
1730 TU_DEFINE_HANDLE_CASTS(tu_cmd_buffer, VkCommandBuffer)
1731 TU_DEFINE_HANDLE_CASTS(tu_device, VkDevice)
1732 TU_DEFINE_HANDLE_CASTS(tu_instance, VkInstance)
1733 TU_DEFINE_HANDLE_CASTS(tu_physical_device, VkPhysicalDevice)
1734 TU_DEFINE_HANDLE_CASTS(tu_queue, VkQueue)
1735
1736 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_cmd_pool, VkCommandPool)
1737 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer, VkBuffer)
1738 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer_view, VkBufferView)
1739 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_pool, VkDescriptorPool)
1740 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set, VkDescriptorSet)
1741 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set_layout,
1742 VkDescriptorSetLayout)
1743 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_update_template,
1744 VkDescriptorUpdateTemplate)
1745 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_device_memory, VkDeviceMemory)
1746 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_fence, VkFence)
1747 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_event, VkEvent)
1748 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_framebuffer, VkFramebuffer)
1749 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image, VkImage)
1750 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image_view, VkImageView);
1751 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_cache, VkPipelineCache)
1752 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline, VkPipeline)
1753 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_layout, VkPipelineLayout)
1754 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_query_pool, VkQueryPool)
1755 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_render_pass, VkRenderPass)
1756 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_sampler, VkSampler)
1757 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_shader_module, VkShaderModule)
1758 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_semaphore, VkSemaphore)
1759
1760 #endif /* TU_PRIVATE_H */