2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
43 #define VG(x) ((void)0)
46 #include "c11/threads.h"
47 #include "main/macros.h"
48 #include "util/list.h"
49 #include "util/macros.h"
51 #include "vk_debug_report.h"
52 #include "wsi_common.h"
54 #include "drm-uapi/msm_drm.h"
55 #include "ir3/ir3_compiler.h"
56 #include "ir3/ir3_shader.h"
58 #include "adreno_common.xml.h"
59 #include "adreno_pm4.xml.h"
61 #include "fdl/freedreno_layout.h"
63 #include "tu_descriptor_set.h"
64 #include "tu_extensions.h"
67 /* Pre-declarations needed for WSI entrypoints */
70 typedef struct xcb_connection_t xcb_connection_t
;
71 typedef uint32_t xcb_visualid_t
;
72 typedef uint32_t xcb_window_t
;
74 #include <vulkan/vk_android_native_buffer.h>
75 #include <vulkan/vk_icd.h>
76 #include <vulkan/vulkan.h>
77 #include <vulkan/vulkan_intel.h>
79 #include "tu_entrypoints.h"
81 #include "vk_format.h"
84 #define MAX_VERTEX_ATTRIBS 32
86 #define MAX_VSC_PIPES 32
87 #define MAX_VIEWPORTS 1
88 #define MAX_SCISSORS 16
89 #define MAX_DISCARD_RECTANGLES 4
90 #define MAX_PUSH_CONSTANTS_SIZE 128
91 #define MAX_PUSH_DESCRIPTORS 32
92 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
93 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
94 #define MAX_DYNAMIC_BUFFERS \
95 (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
96 #define TU_MAX_DRM_DEVICES 8
98 #define MAX_BIND_POINTS 2 /* compute + graphics */
99 /* The Qualcomm driver exposes 0x20000058 */
100 #define MAX_STORAGE_BUFFER_RANGE 0x20000000
101 /* We use ldc for uniform buffer loads, just like the Qualcomm driver, so
102 * expose the same maximum range.
103 * TODO: The SIZE bitfield is 15 bits, and in 4-dword units, so the actual
104 * range might be higher.
106 #define MAX_UNIFORM_BUFFER_RANGE 0x10000
108 #define A6XX_TEX_CONST_DWORDS 16
109 #define A6XX_TEX_SAMP_DWORDS 4
111 #define tu_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
113 static inline uint32_t
114 tu_minify(uint32_t n
, uint32_t levels
)
116 if (unlikely(n
== 0))
119 return MAX2(n
>> levels
, 1);
122 #define for_each_bit(b, dword) \
123 for (uint32_t __dword = (dword); \
124 (b) = __builtin_ffs(__dword) - 1, __dword; __dword &= ~(1 << (b)))
126 #define typed_memcpy(dest, src, count) \
128 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
129 memcpy((dest), (src), (count) * sizeof(*(src))); \
132 #define COND(bool, val) ((bool) ? (val) : 0)
133 #define BIT(bit) (1u << (bit))
135 /* Whenever we generate an error, pass it through this function. Useful for
136 * debugging, where we can break on it. Only call at error site, not when
137 * propagating errors. Might be useful to plug in a stack trace here.
143 __vk_errorf(struct tu_instance
*instance
,
150 #define vk_error(instance, error) \
151 __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
152 #define vk_errorf(instance, error, format, ...) \
153 __vk_errorf(instance, error, __FILE__, __LINE__, format, ##__VA_ARGS__);
156 __tu_finishme(const char *file
, int line
, const char *format
, ...)
159 tu_loge(const char *format
, ...) tu_printflike(1, 2);
161 tu_logi(const char *format
, ...) tu_printflike(1, 2);
164 * Print a FINISHME message, including its source location.
166 #define tu_finishme(format, ...) \
168 static bool reported = false; \
170 __tu_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
177 tu_finishme("stub %s", __func__); \
181 tu_lookup_entrypoint_unchecked(const char *name
);
183 tu_lookup_entrypoint_checked(
185 uint32_t core_version
,
186 const struct tu_instance_extension_table
*instance
,
187 const struct tu_device_extension_table
*device
);
189 struct tu_physical_device
191 VK_LOADER_DATA _loader_data
;
193 struct tu_instance
*instance
;
196 char name
[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE
];
197 uint8_t driver_uuid
[VK_UUID_SIZE
];
198 uint8_t device_uuid
[VK_UUID_SIZE
];
199 uint8_t cache_uuid
[VK_UUID_SIZE
];
201 struct wsi_device wsi_device
;
209 uint32_t ccu_offset_gmem
;
210 uint32_t ccu_offset_bypass
;
211 /* alignment for size of tiles */
212 uint32_t tile_align_w
;
213 #define TILE_ALIGN_H 16
214 /* gmem store/load granularity */
215 #define GMEM_ALIGN_W 16
216 #define GMEM_ALIGN_H 4
219 uint32_t PC_UNKNOWN_9805
;
220 uint32_t SP_UNKNOWN_A0F8
;
223 /* This is the drivers on-disk cache used as a fallback as opposed to
224 * the pipeline cache defined by apps.
226 struct disk_cache
*disk_cache
;
228 struct tu_device_extension_table supported_extensions
;
233 TU_DEBUG_STARTUP
= 1 << 0,
234 TU_DEBUG_NIR
= 1 << 1,
235 TU_DEBUG_IR3
= 1 << 2,
236 TU_DEBUG_NOBIN
= 1 << 3,
237 TU_DEBUG_SYSMEM
= 1 << 4,
238 TU_DEBUG_FORCEBIN
= 1 << 5,
239 TU_DEBUG_NOUBWC
= 1 << 6,
244 VK_LOADER_DATA _loader_data
;
246 VkAllocationCallbacks alloc
;
248 uint32_t api_version
;
249 int physical_device_count
;
250 struct tu_physical_device physical_devices
[TU_MAX_DRM_DEVICES
];
252 enum tu_debug_flags debug_flags
;
254 struct vk_debug_report_instance debug_report_callbacks
;
256 struct tu_instance_extension_table enabled_extensions
;
260 tu_wsi_init(struct tu_physical_device
*physical_device
);
262 tu_wsi_finish(struct tu_physical_device
*physical_device
);
265 tu_instance_extension_supported(const char *name
);
267 tu_physical_device_api_version(struct tu_physical_device
*dev
);
269 tu_physical_device_extension_supported(struct tu_physical_device
*dev
,
274 struct tu_pipeline_cache
276 struct tu_device
*device
;
277 pthread_mutex_t mutex
;
281 uint32_t kernel_count
;
282 struct cache_entry
**hash_table
;
285 VkAllocationCallbacks alloc
;
288 struct tu_pipeline_key
294 #define TU_QUEUE_GENERAL 0
296 #define TU_MAX_QUEUE_FAMILIES 1
300 struct wsi_fence
*fence_wsi
;
306 tu_fence_init(struct tu_fence
*fence
, bool signaled
);
308 tu_fence_finish(struct tu_fence
*fence
);
310 tu_fence_update_fd(struct tu_fence
*fence
, int fd
);
312 tu_fence_copy(struct tu_fence
*fence
, const struct tu_fence
*src
);
314 tu_fence_signal(struct tu_fence
*fence
);
316 tu_fence_wait_idle(struct tu_fence
*fence
);
320 VK_LOADER_DATA _loader_data
;
321 struct tu_device
*device
;
322 uint32_t queue_family_index
;
324 VkDeviceQueueCreateFlags flags
;
326 uint32_t msm_queue_id
;
327 struct tu_fence submit_fence
;
340 VK_LOADER_DATA _loader_data
;
342 VkAllocationCallbacks alloc
;
344 struct tu_instance
*instance
;
346 struct tu_queue
*queues
[TU_MAX_QUEUE_FAMILIES
];
347 int queue_count
[TU_MAX_QUEUE_FAMILIES
];
349 struct tu_physical_device
*physical_device
;
351 struct ir3_compiler
*compiler
;
353 /* Backup in-memory cache to be used if the app doesn't provide one */
354 struct tu_pipeline_cache
*mem_cache
;
356 struct tu_bo vsc_draw_strm
;
357 struct tu_bo vsc_prim_strm
;
358 uint32_t vsc_draw_strm_pitch
;
359 uint32_t vsc_prim_strm_pitch
;
361 #define MIN_SCRATCH_BO_SIZE_LOG2 12 /* A page */
363 /* Currently the kernel driver uses a 32-bit GPU address space, but it
364 * should be impossible to go beyond 48 bits.
370 } scratch_bos
[48 - MIN_SCRATCH_BO_SIZE_LOG2
];
372 struct tu_bo border_color
;
374 struct tu_device_extension_table enabled_extensions
;
378 tu_bo_init_new(struct tu_device
*dev
, struct tu_bo
*bo
, uint64_t size
);
380 tu_bo_init_dmabuf(struct tu_device
*dev
,
385 tu_bo_export_dmabuf(struct tu_device
*dev
, struct tu_bo
*bo
);
387 tu_bo_finish(struct tu_device
*dev
, struct tu_bo
*bo
);
389 tu_bo_map(struct tu_device
*dev
, struct tu_bo
*bo
);
391 /* Get a scratch bo for use inside a command buffer. This will always return
392 * the same bo given the same size or similar sizes, so only one scratch bo
393 * can be used at the same time. It's meant for short-lived things where we
394 * need to write to some piece of memory, read from it, and then immediately
398 tu_get_scratch_bo(struct tu_device
*dev
, uint64_t size
, struct tu_bo
**bo
);
403 const struct tu_bo
*bo
;
409 struct tu_cs_memory
{
414 struct tu_draw_state
{
419 enum tu_dynamic_state
421 /* re-use VK_DYNAMIC_STATE_ enums for non-extended dynamic states */
422 TU_DYNAMIC_STATE_SAMPLE_LOCATIONS
= VK_DYNAMIC_STATE_STENCIL_REFERENCE
+ 1,
423 TU_DYNAMIC_STATE_COUNT
,
426 enum tu_draw_state_group_id
428 TU_DRAW_STATE_PROGRAM
,
429 TU_DRAW_STATE_PROGRAM_BINNING
,
433 TU_DRAW_STATE_VI_BINNING
,
437 TU_DRAW_STATE_VS_CONST
,
438 TU_DRAW_STATE_HS_CONST
,
439 TU_DRAW_STATE_DS_CONST
,
440 TU_DRAW_STATE_GS_CONST
,
441 TU_DRAW_STATE_FS_CONST
,
442 TU_DRAW_STATE_DESC_SETS
,
443 TU_DRAW_STATE_DESC_SETS_LOAD
,
444 TU_DRAW_STATE_VS_PARAMS
,
445 TU_DRAW_STATE_INPUT_ATTACHMENTS_GMEM
,
446 TU_DRAW_STATE_INPUT_ATTACHMENTS_SYSMEM
,
448 /* dynamic state related draw states */
449 TU_DRAW_STATE_DYNAMIC
,
450 TU_DRAW_STATE_COUNT
= TU_DRAW_STATE_DYNAMIC
+ TU_DYNAMIC_STATE_COUNT
,
457 * A command stream in TU_CS_MODE_GROW mode grows automatically whenever it
458 * is full. tu_cs_begin must be called before command packet emission and
459 * tu_cs_end must be called after.
461 * This mode may create multiple entries internally. The entries must be
462 * submitted together.
467 * A command stream in TU_CS_MODE_EXTERNAL mode wraps an external,
468 * fixed-size buffer. tu_cs_begin and tu_cs_end are optional and have no
471 * This mode does not create any entry or any BO.
476 * A command stream in TU_CS_MODE_SUB_STREAM mode does not support direct
477 * command packet emission. tu_cs_begin_sub_stream must be called to get a
478 * sub-stream to emit comamnd packets to. When done with the sub-stream,
479 * tu_cs_end_sub_stream must be called.
481 * This mode does not create any entry internally.
483 TU_CS_MODE_SUB_STREAM
,
490 uint32_t *reserved_end
;
493 struct tu_device
*device
;
494 enum tu_cs_mode mode
;
495 uint32_t next_bo_size
;
497 struct tu_cs_entry
*entries
;
498 uint32_t entry_count
;
499 uint32_t entry_capacity
;
503 uint32_t bo_capacity
;
505 /* state for cond_exec_start/cond_exec_end */
507 uint32_t *cond_dwords
;
510 struct tu_device_memory
515 /* for dedicated allocations */
516 struct tu_image
*image
;
517 struct tu_buffer
*buffer
;
524 struct tu_descriptor_range
530 struct tu_descriptor_set
532 const struct tu_descriptor_set_layout
*layout
;
533 struct tu_descriptor_pool
*pool
;
537 uint32_t *mapped_ptr
;
539 uint32_t *dynamic_descriptors
;
541 struct tu_bo
*buffers
[0];
544 struct tu_push_descriptor_set
546 struct tu_descriptor_set set
;
550 struct tu_descriptor_pool_entry
554 struct tu_descriptor_set
*set
;
557 struct tu_descriptor_pool
560 uint64_t current_offset
;
563 uint8_t *host_memory_base
;
564 uint8_t *host_memory_ptr
;
565 uint8_t *host_memory_end
;
567 uint32_t entry_count
;
568 uint32_t max_entry_count
;
569 struct tu_descriptor_pool_entry entries
[0];
572 struct tu_descriptor_update_template_entry
574 VkDescriptorType descriptor_type
;
576 /* The number of descriptors to update */
577 uint32_t descriptor_count
;
579 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array
583 /* In dwords. Not valid/used for dynamic descriptors */
586 uint32_t buffer_offset
;
588 /* Only valid for combined image samplers and samplers */
589 uint16_t has_sampler
;
595 /* For push descriptors */
596 const uint32_t *immutable_samplers
;
599 struct tu_descriptor_update_template
601 uint32_t entry_count
;
602 struct tu_descriptor_update_template_entry entry
[0];
609 VkBufferUsageFlags usage
;
610 VkBufferCreateFlags flags
;
613 VkDeviceSize bo_offset
;
616 static inline uint64_t
617 tu_buffer_iova(struct tu_buffer
*buffer
)
619 return buffer
->bo
->iova
+ buffer
->bo_offset
;
622 struct tu_vertex_binding
624 struct tu_buffer
*buffer
;
629 tu_get_debug_option_name(int id
);
632 tu_get_perftest_option_name(int id
);
634 struct tu_descriptor_state
636 struct tu_descriptor_set
*sets
[MAX_SETS
];
637 uint32_t dynamic_descriptors
[MAX_DYNAMIC_BUFFERS
* A6XX_TEX_CONST_DWORDS
];
648 struct tu_tiling_config
650 VkRect2D render_area
;
652 /* position and size of the first tile */
654 /* number of tiles */
655 VkExtent2D tile_count
;
657 /* size of the first VSC pipe */
659 /* number of VSC pipes */
660 VkExtent2D pipe_count
;
662 /* pipe register values */
663 uint32_t pipe_config
[MAX_VSC_PIPES
];
664 uint32_t pipe_sizes
[MAX_VSC_PIPES
];
666 /* Whether sysmem rendering must be used */
670 enum tu_cmd_dirty_bits
672 TU_CMD_DIRTY_COMPUTE_PIPELINE
= 1 << 1,
673 TU_CMD_DIRTY_VERTEX_BUFFERS
= 1 << 2,
674 TU_CMD_DIRTY_DESCRIPTOR_SETS
= 1 << 3,
675 TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS
= 1 << 4,
676 TU_CMD_DIRTY_SHADER_CONSTS
= 1 << 5,
677 /* all draw states were disabled and need to be re-enabled: */
678 TU_CMD_DIRTY_DRAW_STATE
= 1 << 7,
681 /* There are only three cache domains we have to care about: the CCU, or
682 * color cache unit, which is used for color and depth/stencil attachments
683 * and copy/blit destinations, and is split conceptually into color and depth,
684 * and the universal cache or UCHE which is used for pretty much everything
685 * else, except for the CP (uncached) and host. We need to flush whenever data
686 * crosses these boundaries.
689 enum tu_cmd_access_mask
{
690 TU_ACCESS_UCHE_READ
= 1 << 0,
691 TU_ACCESS_UCHE_WRITE
= 1 << 1,
692 TU_ACCESS_CCU_COLOR_READ
= 1 << 2,
693 TU_ACCESS_CCU_COLOR_WRITE
= 1 << 3,
694 TU_ACCESS_CCU_DEPTH_READ
= 1 << 4,
695 TU_ACCESS_CCU_DEPTH_WRITE
= 1 << 5,
697 /* Experiments have shown that while it's safe to avoid flushing the CCU
698 * after each blit/renderpass, it's not safe to assume that subsequent
699 * lookups with a different attachment state will hit unflushed cache
700 * entries. That is, the CCU needs to be flushed and possibly invalidated
701 * when accessing memory with a different attachment state. Writing to an
702 * attachment under the following conditions after clearing using the
703 * normal 2d engine path is known to have issues:
705 * - It isn't the 0'th layer.
706 * - There are more than one attachment, and this isn't the 0'th attachment
707 * (this seems to also depend on the cpp of the attachments).
709 * Our best guess is that the layer/MRT state is used when computing
710 * the location of a cache entry in CCU, to avoid conflicts. We assume that
711 * any access in a renderpass after or before an access by a transfer needs
712 * a flush/invalidate, and use the _INCOHERENT variants to represent access
715 TU_ACCESS_CCU_COLOR_INCOHERENT_READ
= 1 << 6,
716 TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
= 1 << 7,
717 TU_ACCESS_CCU_DEPTH_INCOHERENT_READ
= 1 << 8,
718 TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE
= 1 << 9,
720 TU_ACCESS_SYSMEM_READ
= 1 << 10,
721 TU_ACCESS_SYSMEM_WRITE
= 1 << 11,
723 /* Set if a WFI is required due to data being read by the CP or the 2D
726 TU_ACCESS_WFI_READ
= 1 << 12,
729 TU_ACCESS_UCHE_READ
|
730 TU_ACCESS_CCU_COLOR_READ
|
731 TU_ACCESS_CCU_DEPTH_READ
|
732 TU_ACCESS_CCU_COLOR_INCOHERENT_READ
|
733 TU_ACCESS_CCU_DEPTH_INCOHERENT_READ
|
734 TU_ACCESS_SYSMEM_READ
,
737 TU_ACCESS_UCHE_WRITE
|
738 TU_ACCESS_CCU_COLOR_WRITE
|
739 TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
|
740 TU_ACCESS_CCU_DEPTH_WRITE
|
741 TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE
|
742 TU_ACCESS_SYSMEM_WRITE
,
749 enum tu_cmd_flush_bits
{
750 TU_CMD_FLAG_CCU_FLUSH_DEPTH
= 1 << 0,
751 TU_CMD_FLAG_CCU_FLUSH_COLOR
= 1 << 1,
752 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
= 1 << 2,
753 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
= 1 << 3,
754 TU_CMD_FLAG_CACHE_FLUSH
= 1 << 4,
755 TU_CMD_FLAG_CACHE_INVALIDATE
= 1 << 5,
757 TU_CMD_FLAG_ALL_FLUSH
=
758 TU_CMD_FLAG_CCU_FLUSH_DEPTH
|
759 TU_CMD_FLAG_CCU_FLUSH_COLOR
|
760 TU_CMD_FLAG_CACHE_FLUSH
,
762 TU_CMD_FLAG_ALL_INVALIDATE
=
763 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
|
764 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
|
765 TU_CMD_FLAG_CACHE_INVALIDATE
,
767 TU_CMD_FLAG_WFI
= 1 << 6,
770 /* Changing the CCU from sysmem mode to gmem mode or vice-versa is pretty
771 * heavy, involving a CCU cache flush/invalidate and a WFI in order to change
772 * which part of the gmem is used by the CCU. Here we keep track of what the
775 enum tu_cmd_ccu_state
{
781 struct tu_cache_state
{
782 /* Caches which must be made available (flushed) eventually if there are
783 * any users outside that cache domain, and caches which must be
784 * invalidated eventually if there are any reads.
786 enum tu_cmd_flush_bits pending_flush_bits
;
787 /* Pending flushes */
788 enum tu_cmd_flush_bits flush_bits
;
795 struct tu_pipeline
*pipeline
;
796 struct tu_pipeline
*compute_pipeline
;
801 struct tu_buffer
*buffers
[MAX_VBS
];
802 VkDeviceSize offsets
[MAX_VBS
];
805 /* for dynamic states that can't be emitted directly */
806 uint32_t dynamic_stencil_mask
;
807 uint32_t dynamic_stencil_wrmask
;
808 uint32_t dynamic_stencil_ref
;
809 uint32_t dynamic_gras_su_cntl
;
811 /* saved states to re-emit in TU_CMD_DIRTY_DRAW_STATE case */
812 struct tu_draw_state dynamic_state
[TU_DYNAMIC_STATE_COUNT
];
813 struct tu_cs_entry vertex_buffers_ib
;
814 struct tu_cs_entry shader_const_ib
[MESA_SHADER_STAGES
];
815 struct tu_cs_entry desc_sets_ib
, desc_sets_load_ib
;
816 struct tu_cs_entry ia_gmem_ib
, ia_sysmem_ib
;
820 uint32_t max_index_count
;
821 uint8_t index_size
, index_shift
;
823 /* because streamout base has to be 32-byte aligned
824 * there is an extra offset to deal with when it is
827 uint8_t streamout_offset
[IR3_MAX_SO_BUFFERS
];
829 /* Renderpasses are tricky, because we may need to flush differently if
830 * using sysmem vs. gmem and therefore we have to delay any flushing that
831 * happens before a renderpass. So we have to have two copies of the flush
832 * state, one for intra-renderpass flushes (i.e. renderpass dependencies)
833 * and one for outside a renderpass.
835 struct tu_cache_state cache
;
836 struct tu_cache_state renderpass_cache
;
838 enum tu_cmd_ccu_state ccu_state
;
840 const struct tu_render_pass
*pass
;
841 const struct tu_subpass
*subpass
;
842 const struct tu_framebuffer
*framebuffer
;
844 struct tu_tiling_config tiling_config
;
846 struct tu_cs_entry tile_store_ib
;
853 VkAllocationCallbacks alloc
;
854 struct list_head cmd_buffers
;
855 struct list_head free_cmd_buffers
;
856 uint32_t queue_family_index
;
859 struct tu_cmd_buffer_upload
864 struct list_head list
;
867 enum tu_cmd_buffer_status
869 TU_CMD_BUFFER_STATUS_INVALID
,
870 TU_CMD_BUFFER_STATUS_INITIAL
,
871 TU_CMD_BUFFER_STATUS_RECORDING
,
872 TU_CMD_BUFFER_STATUS_EXECUTABLE
,
873 TU_CMD_BUFFER_STATUS_PENDING
,
880 struct drm_msm_gem_submit_bo
*bo_infos
;
883 #define TU_BO_LIST_FAILED (~0)
886 tu_bo_list_init(struct tu_bo_list
*list
);
888 tu_bo_list_destroy(struct tu_bo_list
*list
);
890 tu_bo_list_reset(struct tu_bo_list
*list
);
892 tu_bo_list_add(struct tu_bo_list
*list
,
893 const struct tu_bo
*bo
,
896 tu_bo_list_merge(struct tu_bo_list
*list
, const struct tu_bo_list
*other
);
898 /* This struct defines the layout of the scratch_bo */
901 uint32_t seqno_dummy
; /* dummy seqno for CP_EVENT_WRITE */
903 volatile uint32_t vsc_overflow
;
905 /* flag set from cmdstream when VSC overflow detected: */
906 uint32_t vsc_scratch
;
911 /* scratch space for VPC_SO[i].FLUSH_BASE_LO/HI, start on 32 byte boundary. */
918 #define ctrl_offset(member) offsetof(struct tu6_control, member)
922 VK_LOADER_DATA _loader_data
;
924 struct tu_device
*device
;
926 struct tu_cmd_pool
*pool
;
927 struct list_head pool_link
;
929 VkCommandBufferUsageFlags usage_flags
;
930 VkCommandBufferLevel level
;
931 enum tu_cmd_buffer_status status
;
933 struct tu_cmd_state state
;
934 struct tu_vertex_binding vertex_bindings
[MAX_VBS
];
935 uint32_t vertex_bindings_set
;
936 uint32_t queue_family_index
;
938 uint32_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
/ 4];
939 VkShaderStageFlags push_constant_stages
;
940 struct tu_descriptor_set meta_push_descriptors
;
942 struct tu_descriptor_state descriptors
[MAX_BIND_POINTS
];
944 struct tu_cmd_buffer_upload upload
;
946 VkResult record_result
;
948 struct tu_bo_list bo_list
;
950 struct tu_cs draw_cs
;
951 struct tu_cs draw_epilogue_cs
;
954 struct tu_bo scratch_bo
;
958 struct tu_bo vsc_draw_strm
;
959 struct tu_bo vsc_prim_strm
;
960 uint32_t vsc_draw_strm_pitch
;
961 uint32_t vsc_prim_strm_pitch
;
965 /* Temporary struct for tracking a register state to be written, used by
966 * a6xx-pack.h and tu_cs_emit_regs()
968 struct tu_reg_value
{
979 void tu_emit_cache_flush_renderpass(struct tu_cmd_buffer
*cmd_buffer
,
982 void tu_emit_cache_flush_ccu(struct tu_cmd_buffer
*cmd_buffer
,
984 enum tu_cmd_ccu_state ccu_state
);
987 tu6_emit_event_write(struct tu_cmd_buffer
*cmd
,
989 enum vgt_event_type event
);
991 static inline struct tu_descriptor_state
*
992 tu_get_descriptors_state(struct tu_cmd_buffer
*cmd_buffer
,
993 VkPipelineBindPoint bind_point
)
995 return &cmd_buffer
->descriptors
[bind_point
];
1003 struct tu_shader_module
1005 unsigned char sha1
[20];
1008 const uint32_t *code
[0];
1011 struct tu_push_constant_range
1019 struct ir3_shader
*ir3_shader
;
1021 struct tu_push_constant_range push_consts
;
1022 uint8_t active_desc_sets
;
1026 tu_shader_create(struct tu_device
*dev
,
1027 gl_shader_stage stage
,
1028 const VkPipelineShaderStageCreateInfo
*stage_info
,
1029 struct tu_pipeline_layout
*layout
,
1030 const VkAllocationCallbacks
*alloc
);
1033 tu_shader_destroy(struct tu_device
*dev
,
1034 struct tu_shader
*shader
,
1035 const VkAllocationCallbacks
*alloc
);
1037 struct tu_program_descriptor_linkage
1039 struct ir3_const_state const_state
;
1043 struct tu_push_constant_range push_consts
;
1050 struct tu_pipeline_layout
*layout
;
1052 bool need_indirect_descriptor_sets
;
1053 VkShaderStageFlags active_stages
;
1054 uint32_t active_desc_sets
;
1056 /* mask of enabled dynamic states
1057 * if BIT(i) is set, pipeline->dynamic_state[i] is *NOT* used
1059 uint32_t dynamic_state_mask
;
1060 struct tu_draw_state dynamic_state
[TU_DYNAMIC_STATE_COUNT
];
1062 /* gras_su_cntl without line width, used for dynamic line width state */
1063 uint32_t gras_su_cntl
;
1067 struct tu_cs_entry state_ib
;
1068 struct tu_cs_entry binning_state_ib
;
1070 struct tu_program_descriptor_linkage link
[MESA_SHADER_STAGES
];
1075 struct tu_cs_entry state_ib
;
1080 struct tu_cs_entry state_ib
;
1081 struct tu_cs_entry binning_state_ib
;
1082 uint32_t bindings_used
;
1087 enum pc_di_primtype primtype
;
1088 bool primitive_restart
;
1093 uint32_t patch_type
;
1094 uint32_t per_vertex_output_size
;
1095 uint32_t per_patch_output_size
;
1096 uint32_t hs_bo_regid
;
1097 uint32_t ds_bo_regid
;
1098 bool upper_left_domain_origin
;
1103 struct tu_cs_entry state_ib
;
1108 struct tu_cs_entry state_ib
;
1113 struct tu_cs_entry state_ib
;
1118 uint32_t local_size
[3];
1123 tu6_emit_viewport(struct tu_cs
*cs
, const VkViewport
*viewport
);
1126 tu6_emit_scissor(struct tu_cs
*cs
, const VkRect2D
*scissor
);
1129 tu6_emit_sample_locations(struct tu_cs
*cs
, const VkSampleLocationsInfoEXT
*samp_loc
);
1132 tu6_emit_depth_bias(struct tu_cs
*cs
,
1133 float constant_factor
,
1135 float slope_factor
);
1137 void tu6_emit_msaa(struct tu_cs
*cs
, VkSampleCountFlagBits samples
);
1139 void tu6_emit_window_scissor(struct tu_cs
*cs
, uint32_t x1
, uint32_t y1
, uint32_t x2
, uint32_t y2
);
1141 void tu6_emit_window_offset(struct tu_cs
*cs
, uint32_t x1
, uint32_t y1
);
1144 tu6_emit_xs_config(struct tu_cs
*cs
,
1145 gl_shader_stage stage
,
1146 const struct ir3_shader_variant
*xs
,
1147 uint64_t binary_iova
);
1150 tu6_emit_vpc(struct tu_cs
*cs
,
1151 const struct ir3_shader_variant
*vs
,
1152 const struct ir3_shader_variant
*hs
,
1153 const struct ir3_shader_variant
*ds
,
1154 const struct ir3_shader_variant
*gs
,
1155 const struct ir3_shader_variant
*fs
);
1158 tu6_emit_fs_inputs(struct tu_cs
*cs
, const struct ir3_shader_variant
*fs
);
1160 struct tu_image_view
;
1163 tu_resolve_sysmem(struct tu_cmd_buffer
*cmd
,
1165 struct tu_image_view
*src
,
1166 struct tu_image_view
*dst
,
1168 const VkRect2D
*rect
);
1171 tu_clear_sysmem_attachment(struct tu_cmd_buffer
*cmd
,
1174 const VkRenderPassBeginInfo
*info
);
1177 tu_clear_gmem_attachment(struct tu_cmd_buffer
*cmd
,
1180 const VkRenderPassBeginInfo
*info
);
1183 tu_load_gmem_attachment(struct tu_cmd_buffer
*cmd
,
1188 /* expose this function to be able to emit load without checking LOAD_OP */
1190 tu_emit_load_gmem_attachment(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
, uint32_t a
);
1192 /* note: gmem store can also resolve */
1194 tu_store_gmem_attachment(struct tu_cmd_buffer
*cmd
,
1199 enum tu_supported_formats
{
1205 struct tu_native_format
1207 enum a6xx_format fmt
: 8;
1208 enum a3xx_color_swap swap
: 8;
1209 enum a6xx_tile_mode tile_mode
: 8;
1210 enum tu_supported_formats supported
: 8;
1213 struct tu_native_format
tu6_format_vtx(VkFormat format
);
1214 struct tu_native_format
tu6_format_color(VkFormat format
, enum a6xx_tile_mode tile_mode
);
1215 struct tu_native_format
tu6_format_texture(VkFormat format
, enum a6xx_tile_mode tile_mode
);
1217 static inline enum a6xx_format
1218 tu6_base_format(VkFormat format
)
1220 /* note: tu6_format_color doesn't care about tiling for .fmt field */
1221 return tu6_format_color(format
, TILE6_LINEAR
).fmt
;
1227 /* The original VkFormat provided by the client. This may not match any
1228 * of the actual surface formats.
1231 VkImageAspectFlags aspects
;
1232 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1233 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1234 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1236 uint32_t level_count
;
1237 uint32_t layer_count
;
1238 VkSampleCountFlagBits samples
;
1240 struct fdl_layout layout
;
1242 unsigned queue_family_mask
;
1246 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1247 VkDeviceMemory owned_memory
;
1249 /* Set when bound */
1251 VkDeviceSize bo_offset
;
1254 static inline uint32_t
1255 tu_get_layerCount(const struct tu_image
*image
,
1256 const VkImageSubresourceRange
*range
)
1258 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
1259 ? image
->layer_count
- range
->baseArrayLayer
1260 : range
->layerCount
;
1263 static inline uint32_t
1264 tu_get_levelCount(const struct tu_image
*image
,
1265 const VkImageSubresourceRange
*range
)
1267 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
1268 ? image
->level_count
- range
->baseMipLevel
1269 : range
->levelCount
;
1272 struct tu_image_view
1274 struct tu_image
*image
; /**< VkImageViewCreateInfo::image */
1278 uint32_t layer_size
;
1279 uint32_t ubwc_layer_size
;
1281 /* used to determine if fast gmem store path can be used */
1287 uint32_t descriptor
[A6XX_TEX_CONST_DWORDS
];
1289 /* Descriptor for use as a storage image as opposed to a sampled image.
1290 * This has a few differences for cube maps (e.g. type).
1292 uint32_t storage_descriptor
[A6XX_TEX_CONST_DWORDS
];
1294 /* pre-filled register values */
1296 uint32_t FLAG_BUFFER_PITCH
;
1298 uint32_t RB_MRT_BUF_INFO
;
1299 uint32_t SP_FS_MRT_REG
;
1301 uint32_t SP_PS_2D_SRC_INFO
;
1302 uint32_t SP_PS_2D_SRC_SIZE
;
1304 uint32_t RB_2D_DST_INFO
;
1306 uint32_t RB_BLIT_DST_INFO
;
1309 struct tu_sampler_ycbcr_conversion
{
1311 VkSamplerYcbcrModelConversion ycbcr_model
;
1312 VkSamplerYcbcrRange ycbcr_range
;
1313 VkComponentMapping components
;
1314 VkChromaLocation chroma_offsets
[2];
1315 VkFilter chroma_filter
;
1319 uint32_t descriptor
[A6XX_TEX_SAMP_DWORDS
];
1320 struct tu_sampler_ycbcr_conversion
*ycbcr_sampler
;
1324 tu_cs_image_ref(struct tu_cs
*cs
, const struct tu_image_view
*iview
, uint32_t layer
);
1327 tu_cs_image_ref_2d(struct tu_cs
*cs
, const struct tu_image_view
*iview
, uint32_t layer
, bool src
);
1330 tu_cs_image_flag_ref(struct tu_cs
*cs
, const struct tu_image_view
*iview
, uint32_t layer
);
1333 tu_image_create(VkDevice _device
,
1334 const VkImageCreateInfo
*pCreateInfo
,
1335 const VkAllocationCallbacks
*alloc
,
1338 const VkSubresourceLayout
*plane_layouts
);
1341 tu_image_from_gralloc(VkDevice device_h
,
1342 const VkImageCreateInfo
*base_info
,
1343 const VkNativeBufferANDROID
*gralloc_info
,
1344 const VkAllocationCallbacks
*alloc
,
1345 VkImage
*out_image_h
);
1348 tu_image_view_init(struct tu_image_view
*view
,
1349 const VkImageViewCreateInfo
*pCreateInfo
);
1351 struct tu_buffer_view
1353 uint32_t descriptor
[A6XX_TEX_CONST_DWORDS
];
1355 struct tu_buffer
*buffer
;
1358 tu_buffer_view_init(struct tu_buffer_view
*view
,
1359 struct tu_device
*device
,
1360 const VkBufferViewCreateInfo
*pCreateInfo
);
1362 struct tu_attachment_info
1364 struct tu_image_view
*attachment
;
1367 struct tu_framebuffer
1373 uint32_t attachment_count
;
1374 struct tu_attachment_info attachments
[0];
1377 struct tu_subpass_barrier
{
1378 VkPipelineStageFlags src_stage_mask
;
1379 VkAccessFlags src_access_mask
;
1380 VkAccessFlags dst_access_mask
;
1381 bool incoherent_ccu_color
, incoherent_ccu_depth
;
1384 struct tu_subpass_attachment
1386 uint32_t attachment
;
1391 uint32_t input_count
;
1392 uint32_t color_count
;
1393 struct tu_subpass_attachment
*input_attachments
;
1394 struct tu_subpass_attachment
*color_attachments
;
1395 struct tu_subpass_attachment
*resolve_attachments
;
1396 struct tu_subpass_attachment depth_stencil_attachment
;
1398 VkSampleCountFlagBits samples
;
1402 struct tu_subpass_barrier start_barrier
;
1405 struct tu_render_pass_attachment
1410 VkImageAspectFlags clear_mask
;
1413 int32_t gmem_offset
;
1416 struct tu_render_pass
1418 uint32_t attachment_count
;
1419 uint32_t subpass_count
;
1420 uint32_t gmem_pixels
;
1421 uint32_t tile_align_w
;
1422 struct tu_subpass_attachment
*subpass_attachments
;
1423 struct tu_render_pass_attachment
*attachments
;
1424 struct tu_subpass_barrier end_barrier
;
1425 struct tu_subpass subpasses
[0];
1428 struct tu_query_pool
1433 uint32_t pipeline_statistics
;
1440 uint32_t temp_syncobj
;
1444 tu_set_descriptor_set(struct tu_cmd_buffer
*cmd_buffer
,
1445 VkPipelineBindPoint bind_point
,
1446 struct tu_descriptor_set
*set
,
1450 tu_update_descriptor_sets(struct tu_device
*device
,
1451 struct tu_cmd_buffer
*cmd_buffer
,
1452 VkDescriptorSet overrideSet
,
1453 uint32_t descriptorWriteCount
,
1454 const VkWriteDescriptorSet
*pDescriptorWrites
,
1455 uint32_t descriptorCopyCount
,
1456 const VkCopyDescriptorSet
*pDescriptorCopies
);
1459 tu_update_descriptor_set_with_template(
1460 struct tu_device
*device
,
1461 struct tu_cmd_buffer
*cmd_buffer
,
1462 struct tu_descriptor_set
*set
,
1463 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
1467 tu_drm_get_gpu_id(const struct tu_physical_device
*dev
, uint32_t *id
);
1470 tu_drm_get_gmem_size(const struct tu_physical_device
*dev
, uint32_t *size
);
1473 tu_drm_get_gmem_base(const struct tu_physical_device
*dev
, uint64_t *base
);
1476 tu_drm_submitqueue_new(const struct tu_device
*dev
,
1478 uint32_t *queue_id
);
1481 tu_drm_submitqueue_close(const struct tu_device
*dev
, uint32_t queue_id
);
1484 tu_gem_new(const struct tu_device
*dev
, uint64_t size
, uint32_t flags
);
1486 tu_gem_import_dmabuf(const struct tu_device
*dev
,
1490 tu_gem_export_dmabuf(const struct tu_device
*dev
, uint32_t gem_handle
);
1492 tu_gem_close(const struct tu_device
*dev
, uint32_t gem_handle
);
1494 tu_gem_info_offset(const struct tu_device
*dev
, uint32_t gem_handle
);
1496 tu_gem_info_iova(const struct tu_device
*dev
, uint32_t gem_handle
);
1498 #define TU_DEFINE_HANDLE_CASTS(__tu_type, __VkType) \
1500 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1502 return (struct __tu_type *) _handle; \
1505 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1507 return (__VkType) _obj; \
1510 #define TU_DEFINE_NONDISP_HANDLE_CASTS(__tu_type, __VkType) \
1512 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1514 return (struct __tu_type *) (uintptr_t) _handle; \
1517 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1519 return (__VkType)(uintptr_t) _obj; \
1522 #define TU_FROM_HANDLE(__tu_type, __name, __handle) \
1523 struct __tu_type *__name = __tu_type##_from_handle(__handle)
1525 TU_DEFINE_HANDLE_CASTS(tu_cmd_buffer
, VkCommandBuffer
)
1526 TU_DEFINE_HANDLE_CASTS(tu_device
, VkDevice
)
1527 TU_DEFINE_HANDLE_CASTS(tu_instance
, VkInstance
)
1528 TU_DEFINE_HANDLE_CASTS(tu_physical_device
, VkPhysicalDevice
)
1529 TU_DEFINE_HANDLE_CASTS(tu_queue
, VkQueue
)
1531 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_cmd_pool
, VkCommandPool
)
1532 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer
, VkBuffer
)
1533 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer_view
, VkBufferView
)
1534 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_pool
, VkDescriptorPool
)
1535 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set
, VkDescriptorSet
)
1536 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set_layout
,
1537 VkDescriptorSetLayout
)
1538 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_update_template
,
1539 VkDescriptorUpdateTemplate
)
1540 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_device_memory
, VkDeviceMemory
)
1541 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_fence
, VkFence
)
1542 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_event
, VkEvent
)
1543 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_framebuffer
, VkFramebuffer
)
1544 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image
, VkImage
)
1545 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image_view
, VkImageView
);
1546 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_cache
, VkPipelineCache
)
1547 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline
, VkPipeline
)
1548 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_layout
, VkPipelineLayout
)
1549 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_query_pool
, VkQueryPool
)
1550 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_render_pass
, VkRenderPass
)
1551 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_sampler
, VkSampler
)
1552 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_sampler_ycbcr_conversion
, VkSamplerYcbcrConversion
)
1553 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_shader_module
, VkShaderModule
)
1554 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_semaphore
, VkSemaphore
)
1556 #endif /* TU_PRIVATE_H */