turnip: support VkImageDrmFormatModifierExplicitCreateInfoEXT
[mesa.git] / src / freedreno / vulkan / tu_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #ifndef TU_PRIVATE_H
29 #define TU_PRIVATE_H
30
31 #include <assert.h>
32 #include <pthread.h>
33 #include <stdbool.h>
34 #include <stdint.h>
35 #include <stdio.h>
36 #include <stdlib.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <memcheck.h>
40 #include <valgrind.h>
41 #define VG(x) x
42 #else
43 #define VG(x) ((void)0)
44 #endif
45
46 #include "c11/threads.h"
47 #include "main/macros.h"
48 #include "util/list.h"
49 #include "util/macros.h"
50 #include "vk_alloc.h"
51 #include "vk_debug_report.h"
52 #include "wsi_common.h"
53
54 #include "drm-uapi/msm_drm.h"
55 #include "ir3/ir3_compiler.h"
56 #include "ir3/ir3_shader.h"
57
58 #include "adreno_common.xml.h"
59 #include "adreno_pm4.xml.h"
60 #include "a6xx.xml.h"
61 #include "fdl/freedreno_layout.h"
62
63 #include "tu_descriptor_set.h"
64 #include "tu_extensions.h"
65
66 /* Pre-declarations needed for WSI entrypoints */
67 struct wl_surface;
68 struct wl_display;
69 typedef struct xcb_connection_t xcb_connection_t;
70 typedef uint32_t xcb_visualid_t;
71 typedef uint32_t xcb_window_t;
72
73 #include <vulkan/vk_android_native_buffer.h>
74 #include <vulkan/vk_icd.h>
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77
78 #include "tu_entrypoints.h"
79
80 #include "vk_format.h"
81
82 #define MAX_VBS 32
83 #define MAX_VERTEX_ATTRIBS 32
84 #define MAX_RTS 8
85 #define MAX_VSC_PIPES 32
86 #define MAX_VIEWPORTS 1
87 #define MAX_SCISSORS 16
88 #define MAX_DISCARD_RECTANGLES 4
89 #define MAX_PUSH_CONSTANTS_SIZE 128
90 #define MAX_PUSH_DESCRIPTORS 32
91 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
92 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
93 #define MAX_DYNAMIC_BUFFERS \
94 (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
95 #define MAX_SAMPLES_LOG2 4
96 #define NUM_META_FS_KEYS 13
97 #define TU_MAX_DRM_DEVICES 8
98 #define MAX_VIEWS 8
99 #define MAX_BIND_POINTS 2 /* compute + graphics */
100 /* The Qualcomm driver exposes 0x20000058 */
101 #define MAX_STORAGE_BUFFER_RANGE 0x20000000
102 /* We use ldc for uniform buffer loads, just like the Qualcomm driver, so
103 * expose the same maximum range.
104 * TODO: The SIZE bitfield is 15 bits, and in 4-dword units, so the actual
105 * range might be higher.
106 */
107 #define MAX_UNIFORM_BUFFER_RANGE 0x10000
108
109 #define NUM_DEPTH_CLEAR_PIPELINES 3
110
111 /*
112 * This is the point we switch from using CP to compute shader
113 * for certain buffer operations.
114 */
115 #define TU_BUFFER_OPS_CS_THRESHOLD 4096
116
117 #define A6XX_TEX_CONST_DWORDS 16
118 #define A6XX_TEX_SAMP_DWORDS 4
119
120 enum tu_mem_heap
121 {
122 TU_MEM_HEAP_VRAM,
123 TU_MEM_HEAP_VRAM_CPU_ACCESS,
124 TU_MEM_HEAP_GTT,
125 TU_MEM_HEAP_COUNT
126 };
127
128 enum tu_mem_type
129 {
130 TU_MEM_TYPE_VRAM,
131 TU_MEM_TYPE_GTT_WRITE_COMBINE,
132 TU_MEM_TYPE_VRAM_CPU_ACCESS,
133 TU_MEM_TYPE_GTT_CACHED,
134 TU_MEM_TYPE_COUNT
135 };
136
137 #define tu_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
138
139 static inline uint32_t
140 align_u32(uint32_t v, uint32_t a)
141 {
142 assert(a != 0 && a == (a & -a));
143 return (v + a - 1) & ~(a - 1);
144 }
145
146 static inline uint32_t
147 align_u32_npot(uint32_t v, uint32_t a)
148 {
149 return (v + a - 1) / a * a;
150 }
151
152 static inline uint64_t
153 align_u64(uint64_t v, uint64_t a)
154 {
155 assert(a != 0 && a == (a & -a));
156 return (v + a - 1) & ~(a - 1);
157 }
158
159 static inline int32_t
160 align_i32(int32_t v, int32_t a)
161 {
162 assert(a != 0 && a == (a & -a));
163 return (v + a - 1) & ~(a - 1);
164 }
165
166 /** Alignment must be a power of 2. */
167 static inline bool
168 tu_is_aligned(uintmax_t n, uintmax_t a)
169 {
170 assert(a == (a & -a));
171 return (n & (a - 1)) == 0;
172 }
173
174 static inline uint32_t
175 round_up_u32(uint32_t v, uint32_t a)
176 {
177 return (v + a - 1) / a;
178 }
179
180 static inline uint64_t
181 round_up_u64(uint64_t v, uint64_t a)
182 {
183 return (v + a - 1) / a;
184 }
185
186 static inline uint32_t
187 tu_minify(uint32_t n, uint32_t levels)
188 {
189 if (unlikely(n == 0))
190 return 0;
191 else
192 return MAX2(n >> levels, 1);
193 }
194 static inline float
195 tu_clamp_f(float f, float min, float max)
196 {
197 assert(min < max);
198
199 if (f > max)
200 return max;
201 else if (f < min)
202 return min;
203 else
204 return f;
205 }
206
207 static inline bool
208 tu_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
209 {
210 if (*inout_mask & clear_mask) {
211 *inout_mask &= ~clear_mask;
212 return true;
213 } else {
214 return false;
215 }
216 }
217
218 #define for_each_bit(b, dword) \
219 for (uint32_t __dword = (dword); \
220 (b) = __builtin_ffs(__dword) - 1, __dword; __dword &= ~(1 << (b)))
221
222 #define typed_memcpy(dest, src, count) \
223 ({ \
224 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
225 memcpy((dest), (src), (count) * sizeof(*(src))); \
226 })
227
228 #define COND(bool, val) ((bool) ? (val) : 0)
229
230 /* Whenever we generate an error, pass it through this function. Useful for
231 * debugging, where we can break on it. Only call at error site, not when
232 * propagating errors. Might be useful to plug in a stack trace here.
233 */
234
235 struct tu_instance;
236
237 VkResult
238 __vk_errorf(struct tu_instance *instance,
239 VkResult error,
240 const char *file,
241 int line,
242 const char *format,
243 ...);
244
245 #define vk_error(instance, error) \
246 __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
247 #define vk_errorf(instance, error, format, ...) \
248 __vk_errorf(instance, error, __FILE__, __LINE__, format, ##__VA_ARGS__);
249
250 void
251 __tu_finishme(const char *file, int line, const char *format, ...)
252 tu_printflike(3, 4);
253 void
254 tu_loge(const char *format, ...) tu_printflike(1, 2);
255 void
256 tu_loge_v(const char *format, va_list va);
257 void
258 tu_logi(const char *format, ...) tu_printflike(1, 2);
259 void
260 tu_logi_v(const char *format, va_list va);
261
262 /**
263 * Print a FINISHME message, including its source location.
264 */
265 #define tu_finishme(format, ...) \
266 do { \
267 static bool reported = false; \
268 if (!reported) { \
269 __tu_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
270 reported = true; \
271 } \
272 } while (0)
273
274 /* A non-fatal assert. Useful for debugging. */
275 #ifdef DEBUG
276 #define tu_assert(x) \
277 ({ \
278 if (unlikely(!(x))) \
279 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
280 })
281 #else
282 #define tu_assert(x)
283 #endif
284
285 /* Suppress -Wunused in stub functions */
286 #define tu_use_args(...) __tu_use_args(0, ##__VA_ARGS__)
287 static inline void
288 __tu_use_args(int ignore, ...)
289 {
290 }
291
292 #define tu_stub() \
293 do { \
294 tu_finishme("stub %s", __func__); \
295 } while (0)
296
297 void *
298 tu_lookup_entrypoint_unchecked(const char *name);
299 void *
300 tu_lookup_entrypoint_checked(
301 const char *name,
302 uint32_t core_version,
303 const struct tu_instance_extension_table *instance,
304 const struct tu_device_extension_table *device);
305
306 struct tu_physical_device
307 {
308 VK_LOADER_DATA _loader_data;
309
310 struct tu_instance *instance;
311
312 char path[20];
313 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
314 uint8_t driver_uuid[VK_UUID_SIZE];
315 uint8_t device_uuid[VK_UUID_SIZE];
316 uint8_t cache_uuid[VK_UUID_SIZE];
317
318 struct wsi_device wsi_device;
319
320 int local_fd;
321 int master_fd;
322
323 unsigned gpu_id;
324 uint32_t gmem_size;
325 uint64_t gmem_base;
326 uint32_t ccu_offset_gmem;
327 uint32_t ccu_offset_bypass;
328 /* alignment for size of tiles */
329 uint32_t tile_align_w;
330 #define TILE_ALIGN_H 16
331 /* gmem store/load granularity */
332 #define GMEM_ALIGN_W 16
333 #define GMEM_ALIGN_H 4
334
335 struct {
336 uint32_t PC_UNKNOWN_9805;
337 uint32_t SP_UNKNOWN_A0F8;
338 } magic;
339
340 /* This is the drivers on-disk cache used as a fallback as opposed to
341 * the pipeline cache defined by apps.
342 */
343 struct disk_cache *disk_cache;
344
345 struct tu_device_extension_table supported_extensions;
346 };
347
348 enum tu_debug_flags
349 {
350 TU_DEBUG_STARTUP = 1 << 0,
351 TU_DEBUG_NIR = 1 << 1,
352 TU_DEBUG_IR3 = 1 << 2,
353 TU_DEBUG_NOBIN = 1 << 3,
354 TU_DEBUG_SYSMEM = 1 << 4,
355 TU_DEBUG_FORCEBIN = 1 << 5,
356 TU_DEBUG_NOUBWC = 1 << 6,
357 };
358
359 struct tu_instance
360 {
361 VK_LOADER_DATA _loader_data;
362
363 VkAllocationCallbacks alloc;
364
365 uint32_t api_version;
366 int physical_device_count;
367 struct tu_physical_device physical_devices[TU_MAX_DRM_DEVICES];
368
369 enum tu_debug_flags debug_flags;
370
371 struct vk_debug_report_instance debug_report_callbacks;
372
373 struct tu_instance_extension_table enabled_extensions;
374 };
375
376 VkResult
377 tu_wsi_init(struct tu_physical_device *physical_device);
378 void
379 tu_wsi_finish(struct tu_physical_device *physical_device);
380
381 bool
382 tu_instance_extension_supported(const char *name);
383 uint32_t
384 tu_physical_device_api_version(struct tu_physical_device *dev);
385 bool
386 tu_physical_device_extension_supported(struct tu_physical_device *dev,
387 const char *name);
388
389 struct cache_entry;
390
391 struct tu_pipeline_cache
392 {
393 struct tu_device *device;
394 pthread_mutex_t mutex;
395
396 uint32_t total_size;
397 uint32_t table_size;
398 uint32_t kernel_count;
399 struct cache_entry **hash_table;
400 bool modified;
401
402 VkAllocationCallbacks alloc;
403 };
404
405 struct tu_pipeline_key
406 {
407 };
408
409 void
410 tu_pipeline_cache_init(struct tu_pipeline_cache *cache,
411 struct tu_device *device);
412 void
413 tu_pipeline_cache_finish(struct tu_pipeline_cache *cache);
414 void
415 tu_pipeline_cache_load(struct tu_pipeline_cache *cache,
416 const void *data,
417 size_t size);
418
419 struct tu_shader_variant;
420
421 bool
422 tu_create_shader_variants_from_pipeline_cache(
423 struct tu_device *device,
424 struct tu_pipeline_cache *cache,
425 const unsigned char *sha1,
426 struct tu_shader_variant **variants);
427
428 void
429 tu_pipeline_cache_insert_shaders(struct tu_device *device,
430 struct tu_pipeline_cache *cache,
431 const unsigned char *sha1,
432 struct tu_shader_variant **variants,
433 const void *const *codes,
434 const unsigned *code_sizes);
435
436 struct tu_meta_state
437 {
438 VkAllocationCallbacks alloc;
439
440 struct tu_pipeline_cache cache;
441 };
442
443 /* queue types */
444 #define TU_QUEUE_GENERAL 0
445
446 #define TU_MAX_QUEUE_FAMILIES 1
447
448 struct tu_fence
449 {
450 struct wsi_fence *fence_wsi;
451 bool signaled;
452 int fd;
453 };
454
455 void
456 tu_fence_init(struct tu_fence *fence, bool signaled);
457 void
458 tu_fence_finish(struct tu_fence *fence);
459 void
460 tu_fence_update_fd(struct tu_fence *fence, int fd);
461 void
462 tu_fence_copy(struct tu_fence *fence, const struct tu_fence *src);
463 void
464 tu_fence_signal(struct tu_fence *fence);
465 void
466 tu_fence_wait_idle(struct tu_fence *fence);
467
468 struct tu_queue
469 {
470 VK_LOADER_DATA _loader_data;
471 struct tu_device *device;
472 uint32_t queue_family_index;
473 int queue_idx;
474 VkDeviceQueueCreateFlags flags;
475
476 uint32_t msm_queue_id;
477 struct tu_fence submit_fence;
478 };
479
480 struct tu_bo
481 {
482 uint32_t gem_handle;
483 uint64_t size;
484 uint64_t iova;
485 void *map;
486 };
487
488 struct tu_device
489 {
490 VK_LOADER_DATA _loader_data;
491
492 VkAllocationCallbacks alloc;
493
494 struct tu_instance *instance;
495
496 struct tu_meta_state meta_state;
497
498 struct tu_queue *queues[TU_MAX_QUEUE_FAMILIES];
499 int queue_count[TU_MAX_QUEUE_FAMILIES];
500
501 struct tu_physical_device *physical_device;
502
503 struct ir3_compiler *compiler;
504
505 /* Backup in-memory cache to be used if the app doesn't provide one */
506 struct tu_pipeline_cache *mem_cache;
507
508 struct tu_bo vsc_draw_strm;
509 struct tu_bo vsc_prim_strm;
510 uint32_t vsc_draw_strm_pitch;
511 uint32_t vsc_prim_strm_pitch;
512
513 #define MIN_SCRATCH_BO_SIZE_LOG2 12 /* A page */
514
515 /* Currently the kernel driver uses a 32-bit GPU address space, but it
516 * should be impossible to go beyond 48 bits.
517 */
518 struct {
519 struct tu_bo bo;
520 mtx_t construct_mtx;
521 bool initialized;
522 } scratch_bos[48 - MIN_SCRATCH_BO_SIZE_LOG2];
523
524 struct tu_bo border_color;
525
526 struct list_head shader_slabs;
527 mtx_t shader_slab_mutex;
528
529 struct tu_device_extension_table enabled_extensions;
530 };
531
532 VkResult
533 tu_bo_init_new(struct tu_device *dev, struct tu_bo *bo, uint64_t size);
534 VkResult
535 tu_bo_init_dmabuf(struct tu_device *dev,
536 struct tu_bo *bo,
537 uint64_t size,
538 int fd);
539 int
540 tu_bo_export_dmabuf(struct tu_device *dev, struct tu_bo *bo);
541 void
542 tu_bo_finish(struct tu_device *dev, struct tu_bo *bo);
543 VkResult
544 tu_bo_map(struct tu_device *dev, struct tu_bo *bo);
545
546 /* Get a scratch bo for use inside a command buffer. This will always return
547 * the same bo given the same size or similar sizes, so only one scratch bo
548 * can be used at the same time. It's meant for short-lived things where we
549 * need to write to some piece of memory, read from it, and then immediately
550 * discard it.
551 */
552 VkResult
553 tu_get_scratch_bo(struct tu_device *dev, uint64_t size, struct tu_bo **bo);
554
555 struct tu_cs_entry
556 {
557 /* No ownership */
558 const struct tu_bo *bo;
559
560 uint32_t size;
561 uint32_t offset;
562 };
563
564 struct ts_cs_memory {
565 uint32_t *map;
566 uint64_t iova;
567 };
568
569 enum tu_cs_mode
570 {
571
572 /*
573 * A command stream in TU_CS_MODE_GROW mode grows automatically whenever it
574 * is full. tu_cs_begin must be called before command packet emission and
575 * tu_cs_end must be called after.
576 *
577 * This mode may create multiple entries internally. The entries must be
578 * submitted together.
579 */
580 TU_CS_MODE_GROW,
581
582 /*
583 * A command stream in TU_CS_MODE_EXTERNAL mode wraps an external,
584 * fixed-size buffer. tu_cs_begin and tu_cs_end are optional and have no
585 * effect on it.
586 *
587 * This mode does not create any entry or any BO.
588 */
589 TU_CS_MODE_EXTERNAL,
590
591 /*
592 * A command stream in TU_CS_MODE_SUB_STREAM mode does not support direct
593 * command packet emission. tu_cs_begin_sub_stream must be called to get a
594 * sub-stream to emit comamnd packets to. When done with the sub-stream,
595 * tu_cs_end_sub_stream must be called.
596 *
597 * This mode does not create any entry internally.
598 */
599 TU_CS_MODE_SUB_STREAM,
600 };
601
602 struct tu_cs
603 {
604 uint32_t *start;
605 uint32_t *cur;
606 uint32_t *reserved_end;
607 uint32_t *end;
608
609 struct tu_device *device;
610 enum tu_cs_mode mode;
611 uint32_t next_bo_size;
612
613 struct tu_cs_entry *entries;
614 uint32_t entry_count;
615 uint32_t entry_capacity;
616
617 struct tu_bo **bos;
618 uint32_t bo_count;
619 uint32_t bo_capacity;
620
621 /* state for cond_exec_start/cond_exec_end */
622 uint32_t cond_flags;
623 uint32_t *cond_dwords;
624 };
625
626 struct tu_device_memory
627 {
628 struct tu_bo bo;
629 VkDeviceSize size;
630
631 /* for dedicated allocations */
632 struct tu_image *image;
633 struct tu_buffer *buffer;
634
635 uint32_t type_index;
636 void *map;
637 void *user_ptr;
638 };
639
640 struct tu_descriptor_range
641 {
642 uint64_t va;
643 uint32_t size;
644 };
645
646 struct tu_descriptor_set
647 {
648 const struct tu_descriptor_set_layout *layout;
649 struct tu_descriptor_pool *pool;
650 uint32_t size;
651
652 uint64_t va;
653 uint32_t *mapped_ptr;
654
655 uint32_t *dynamic_descriptors;
656
657 struct tu_bo *buffers[0];
658 };
659
660 struct tu_push_descriptor_set
661 {
662 struct tu_descriptor_set set;
663 uint32_t capacity;
664 };
665
666 struct tu_descriptor_pool_entry
667 {
668 uint32_t offset;
669 uint32_t size;
670 struct tu_descriptor_set *set;
671 };
672
673 struct tu_descriptor_pool
674 {
675 struct tu_bo bo;
676 uint64_t current_offset;
677 uint64_t size;
678
679 uint8_t *host_memory_base;
680 uint8_t *host_memory_ptr;
681 uint8_t *host_memory_end;
682
683 uint32_t entry_count;
684 uint32_t max_entry_count;
685 struct tu_descriptor_pool_entry entries[0];
686 };
687
688 struct tu_descriptor_update_template_entry
689 {
690 VkDescriptorType descriptor_type;
691
692 /* The number of descriptors to update */
693 uint32_t descriptor_count;
694
695 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array
696 */
697 uint32_t dst_offset;
698
699 /* In dwords. Not valid/used for dynamic descriptors */
700 uint32_t dst_stride;
701
702 uint32_t buffer_offset;
703
704 /* Only valid for combined image samplers and samplers */
705 uint16_t has_sampler;
706
707 /* In bytes */
708 size_t src_offset;
709 size_t src_stride;
710
711 /* For push descriptors */
712 const uint32_t *immutable_samplers;
713 };
714
715 struct tu_descriptor_update_template
716 {
717 uint32_t entry_count;
718 struct tu_descriptor_update_template_entry entry[0];
719 };
720
721 struct tu_buffer
722 {
723 VkDeviceSize size;
724
725 VkBufferUsageFlags usage;
726 VkBufferCreateFlags flags;
727
728 struct tu_bo *bo;
729 VkDeviceSize bo_offset;
730 };
731
732 static inline uint64_t
733 tu_buffer_iova(struct tu_buffer *buffer)
734 {
735 return buffer->bo->iova + buffer->bo_offset;
736 }
737
738 enum tu_dynamic_state_bits
739 {
740 TU_DYNAMIC_VIEWPORT = 1 << 0,
741 TU_DYNAMIC_SCISSOR = 1 << 1,
742 TU_DYNAMIC_LINE_WIDTH = 1 << 2,
743 TU_DYNAMIC_DEPTH_BIAS = 1 << 3,
744 TU_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
745 TU_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
746 TU_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
747 TU_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
748 TU_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
749 TU_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
750 TU_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
751 TU_DYNAMIC_ALL = (1 << 11) - 1,
752 };
753
754 struct tu_vertex_binding
755 {
756 struct tu_buffer *buffer;
757 VkDeviceSize offset;
758 };
759
760 struct tu_viewport_state
761 {
762 uint32_t count;
763 VkViewport viewports[MAX_VIEWPORTS];
764 };
765
766 struct tu_scissor_state
767 {
768 uint32_t count;
769 VkRect2D scissors[MAX_SCISSORS];
770 };
771
772 struct tu_discard_rectangle_state
773 {
774 uint32_t count;
775 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
776 };
777
778 struct tu_dynamic_state
779 {
780 /**
781 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
782 * Defines the set of saved dynamic state.
783 */
784 uint32_t mask;
785
786 struct tu_viewport_state viewport;
787
788 struct tu_scissor_state scissor;
789
790 float line_width;
791
792 struct
793 {
794 float bias;
795 float clamp;
796 float slope;
797 } depth_bias;
798
799 float blend_constants[4];
800
801 struct
802 {
803 float min;
804 float max;
805 } depth_bounds;
806
807 struct
808 {
809 uint32_t front;
810 uint32_t back;
811 } stencil_compare_mask;
812
813 struct
814 {
815 uint32_t front;
816 uint32_t back;
817 } stencil_write_mask;
818
819 struct
820 {
821 uint32_t front;
822 uint32_t back;
823 } stencil_reference;
824
825 struct tu_discard_rectangle_state discard_rectangle;
826 };
827
828 extern const struct tu_dynamic_state default_dynamic_state;
829
830 const char *
831 tu_get_debug_option_name(int id);
832
833 const char *
834 tu_get_perftest_option_name(int id);
835
836 struct tu_descriptor_state
837 {
838 struct tu_descriptor_set *sets[MAX_SETS];
839 uint32_t valid;
840 struct tu_push_descriptor_set push_set;
841 bool push_dirty;
842 uint32_t dynamic_descriptors[MAX_DYNAMIC_BUFFERS * A6XX_TEX_CONST_DWORDS];
843 uint32_t input_attachments[MAX_RTS * A6XX_TEX_CONST_DWORDS];
844 };
845
846 struct tu_tile
847 {
848 uint8_t pipe;
849 uint8_t slot;
850 VkOffset2D begin;
851 VkOffset2D end;
852 };
853
854 struct tu_tiling_config
855 {
856 VkRect2D render_area;
857
858 /* position and size of the first tile */
859 VkRect2D tile0;
860 /* number of tiles */
861 VkExtent2D tile_count;
862
863 /* size of the first VSC pipe */
864 VkExtent2D pipe0;
865 /* number of VSC pipes */
866 VkExtent2D pipe_count;
867
868 /* pipe register values */
869 uint32_t pipe_config[MAX_VSC_PIPES];
870 uint32_t pipe_sizes[MAX_VSC_PIPES];
871
872 /* Whether sysmem rendering must be used */
873 bool force_sysmem;
874 };
875
876 enum tu_cmd_dirty_bits
877 {
878 TU_CMD_DIRTY_PIPELINE = 1 << 0,
879 TU_CMD_DIRTY_COMPUTE_PIPELINE = 1 << 1,
880 TU_CMD_DIRTY_VERTEX_BUFFERS = 1 << 2,
881 TU_CMD_DIRTY_DESCRIPTOR_SETS = 1 << 3,
882 TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS = 1 << 4,
883 TU_CMD_DIRTY_PUSH_CONSTANTS = 1 << 5,
884 TU_CMD_DIRTY_STREAMOUT_BUFFERS = 1 << 6,
885 TU_CMD_DIRTY_INPUT_ATTACHMENTS = 1 << 7,
886
887 TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 16,
888 TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 17,
889 TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 18,
890 TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 19,
891 TU_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 20,
892 TU_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 21,
893 };
894
895 struct tu_streamout_state {
896 uint16_t stride[IR3_MAX_SO_BUFFERS];
897 uint32_t ncomp[IR3_MAX_SO_BUFFERS];
898 uint32_t prog[IR3_MAX_SO_OUTPUTS * 2];
899 uint32_t prog_count;
900 uint32_t vpc_so_buf_cntl;
901 };
902
903 struct tu_cmd_state
904 {
905 uint32_t dirty;
906
907 struct tu_pipeline *pipeline;
908 struct tu_pipeline *compute_pipeline;
909
910 /* Vertex buffers */
911 struct
912 {
913 struct tu_buffer *buffers[MAX_VBS];
914 VkDeviceSize offsets[MAX_VBS];
915 } vb;
916
917 struct tu_dynamic_state dynamic;
918
919 /* Stream output buffers */
920 struct
921 {
922 struct tu_buffer *buffers[IR3_MAX_SO_BUFFERS];
923 VkDeviceSize offsets[IR3_MAX_SO_BUFFERS];
924 VkDeviceSize sizes[IR3_MAX_SO_BUFFERS];
925 } streamout_buf;
926
927 uint8_t streamout_reset;
928 uint8_t streamout_enabled;
929
930 /* Index buffer */
931 struct tu_buffer *index_buffer;
932 uint64_t index_offset;
933 uint32_t index_type;
934 uint32_t max_index_count;
935 uint64_t index_va;
936
937 const struct tu_render_pass *pass;
938 const struct tu_subpass *subpass;
939 const struct tu_framebuffer *framebuffer;
940
941 struct tu_tiling_config tiling_config;
942
943 struct tu_cs_entry tile_store_ib;
944 };
945
946 struct tu_cmd_pool
947 {
948 VkAllocationCallbacks alloc;
949 struct list_head cmd_buffers;
950 struct list_head free_cmd_buffers;
951 uint32_t queue_family_index;
952 };
953
954 struct tu_cmd_buffer_upload
955 {
956 uint8_t *map;
957 unsigned offset;
958 uint64_t size;
959 struct list_head list;
960 };
961
962 enum tu_cmd_buffer_status
963 {
964 TU_CMD_BUFFER_STATUS_INVALID,
965 TU_CMD_BUFFER_STATUS_INITIAL,
966 TU_CMD_BUFFER_STATUS_RECORDING,
967 TU_CMD_BUFFER_STATUS_EXECUTABLE,
968 TU_CMD_BUFFER_STATUS_PENDING,
969 };
970
971 struct tu_bo_list
972 {
973 uint32_t count;
974 uint32_t capacity;
975 struct drm_msm_gem_submit_bo *bo_infos;
976 };
977
978 #define TU_BO_LIST_FAILED (~0)
979
980 void
981 tu_bo_list_init(struct tu_bo_list *list);
982 void
983 tu_bo_list_destroy(struct tu_bo_list *list);
984 void
985 tu_bo_list_reset(struct tu_bo_list *list);
986 uint32_t
987 tu_bo_list_add(struct tu_bo_list *list,
988 const struct tu_bo *bo,
989 uint32_t flags);
990 VkResult
991 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other);
992
993 /* This struct defines the layout of the scratch_bo */
994 struct tu6_control
995 {
996 uint32_t seqno; /* seqno for async CP_EVENT_WRITE, etc */
997 uint32_t _pad0;
998 volatile uint32_t vsc_overflow;
999 uint32_t _pad1;
1000 /* flag set from cmdstream when VSC overflow detected: */
1001 uint32_t vsc_scratch;
1002 uint32_t _pad2;
1003 uint32_t _pad3;
1004 uint32_t _pad4;
1005
1006 /* scratch space for VPC_SO[i].FLUSH_BASE_LO/HI, start on 32 byte boundary. */
1007 struct {
1008 uint32_t offset;
1009 uint32_t pad[7];
1010 } flush_base[4];
1011 };
1012
1013 #define ctrl_offset(member) offsetof(struct tu6_control, member)
1014
1015 struct tu_cmd_buffer
1016 {
1017 VK_LOADER_DATA _loader_data;
1018
1019 struct tu_device *device;
1020
1021 struct tu_cmd_pool *pool;
1022 struct list_head pool_link;
1023
1024 VkCommandBufferUsageFlags usage_flags;
1025 VkCommandBufferLevel level;
1026 enum tu_cmd_buffer_status status;
1027
1028 struct tu_cmd_state state;
1029 struct tu_vertex_binding vertex_bindings[MAX_VBS];
1030 uint32_t queue_family_index;
1031
1032 uint32_t push_constants[MAX_PUSH_CONSTANTS_SIZE / 4];
1033 VkShaderStageFlags push_constant_stages;
1034 struct tu_descriptor_set meta_push_descriptors;
1035
1036 struct tu_descriptor_state descriptors[MAX_BIND_POINTS];
1037
1038 struct tu_cmd_buffer_upload upload;
1039
1040 VkResult record_result;
1041
1042 struct tu_bo_list bo_list;
1043 struct tu_cs cs;
1044 struct tu_cs draw_cs;
1045 struct tu_cs draw_epilogue_cs;
1046 struct tu_cs sub_cs;
1047
1048 struct tu_bo scratch_bo;
1049 uint32_t scratch_seqno;
1050
1051 struct tu_bo vsc_draw_strm;
1052 struct tu_bo vsc_prim_strm;
1053 uint32_t vsc_draw_strm_pitch;
1054 uint32_t vsc_prim_strm_pitch;
1055 bool use_vsc_data;
1056
1057 bool wait_for_idle;
1058 };
1059
1060 /* Temporary struct for tracking a register state to be written, used by
1061 * a6xx-pack.h and tu_cs_emit_regs()
1062 */
1063 struct tu_reg_value {
1064 uint32_t reg;
1065 uint64_t value;
1066 bool is_address;
1067 struct tu_bo *bo;
1068 bool bo_write;
1069 uint32_t bo_offset;
1070 uint32_t bo_shift;
1071 };
1072
1073 unsigned
1074 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
1075 struct tu_cs *cs,
1076 enum vgt_event_type event,
1077 bool need_seqno);
1078
1079 bool
1080 tu_get_memory_fd(struct tu_device *device,
1081 struct tu_device_memory *memory,
1082 int *pFD);
1083
1084 static inline struct tu_descriptor_state *
1085 tu_get_descriptors_state(struct tu_cmd_buffer *cmd_buffer,
1086 VkPipelineBindPoint bind_point)
1087 {
1088 return &cmd_buffer->descriptors[bind_point];
1089 }
1090
1091 /*
1092 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1093 *
1094 * Limitations: Can't call normal dispatch functions without binding or
1095 * rebinding
1096 * the compute pipeline.
1097 */
1098 void
1099 tu_unaligned_dispatch(struct tu_cmd_buffer *cmd_buffer,
1100 uint32_t x,
1101 uint32_t y,
1102 uint32_t z);
1103
1104 struct tu_event
1105 {
1106 struct tu_bo bo;
1107 };
1108
1109 struct tu_shader_module;
1110
1111 #define TU_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1112 #define TU_HASH_SHADER_SISCHED (1 << 1)
1113 #define TU_HASH_SHADER_UNSAFE_MATH (1 << 2)
1114 void
1115 tu_hash_shaders(unsigned char *hash,
1116 const VkPipelineShaderStageCreateInfo **stages,
1117 const struct tu_pipeline_layout *layout,
1118 const struct tu_pipeline_key *key,
1119 uint32_t flags);
1120
1121 static inline gl_shader_stage
1122 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1123 {
1124 assert(__builtin_popcount(vk_stage) == 1);
1125 return ffs(vk_stage) - 1;
1126 }
1127
1128 static inline VkShaderStageFlagBits
1129 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1130 {
1131 return (1 << mesa_stage);
1132 }
1133
1134 #define TU_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1135
1136 #define tu_foreach_stage(stage, stage_bits) \
1137 for (gl_shader_stage stage, \
1138 __tmp = (gl_shader_stage)((stage_bits) &TU_STAGE_MASK); \
1139 stage = __builtin_ffs(__tmp) - 1, __tmp; __tmp &= ~(1 << (stage)))
1140
1141 struct tu_shader_module
1142 {
1143 unsigned char sha1[20];
1144
1145 uint32_t code_size;
1146 const uint32_t *code[0];
1147 };
1148
1149 struct tu_shader_compile_options
1150 {
1151 struct ir3_shader_key key;
1152
1153 bool optimize;
1154 bool include_binning_pass;
1155 };
1156
1157 struct tu_push_constant_range
1158 {
1159 uint32_t lo;
1160 uint32_t count;
1161 };
1162
1163 struct tu_shader
1164 {
1165 struct ir3_shader ir3_shader;
1166
1167 struct tu_push_constant_range push_consts;
1168 unsigned attachment_idx[MAX_RTS];
1169
1170 /* This may be true for vertex shaders. When true, variants[1] is the
1171 * binning variant and binning_binary is non-NULL.
1172 */
1173 bool has_binning_pass;
1174
1175 void *binary;
1176 void *binning_binary;
1177
1178 struct ir3_shader_variant variants[0];
1179 };
1180
1181 struct tu_shader *
1182 tu_shader_create(struct tu_device *dev,
1183 gl_shader_stage stage,
1184 const VkPipelineShaderStageCreateInfo *stage_info,
1185 struct tu_pipeline_layout *layout,
1186 const VkAllocationCallbacks *alloc);
1187
1188 void
1189 tu_shader_destroy(struct tu_device *dev,
1190 struct tu_shader *shader,
1191 const VkAllocationCallbacks *alloc);
1192
1193 void
1194 tu_shader_compile_options_init(
1195 struct tu_shader_compile_options *options,
1196 const VkGraphicsPipelineCreateInfo *pipeline_info);
1197
1198 VkResult
1199 tu_shader_compile(struct tu_device *dev,
1200 struct tu_shader *shader,
1201 const struct tu_shader *next_stage,
1202 const struct tu_shader_compile_options *options,
1203 const VkAllocationCallbacks *alloc);
1204
1205 struct tu_program_descriptor_linkage
1206 {
1207 struct ir3_ubo_analysis_state ubo_state;
1208 struct ir3_const_state const_state;
1209
1210 uint32_t constlen;
1211
1212 struct tu_push_constant_range push_consts;
1213 };
1214
1215 struct tu_pipeline
1216 {
1217 struct tu_cs cs;
1218
1219 struct tu_dynamic_state dynamic_state;
1220
1221 struct tu_pipeline_layout *layout;
1222
1223 bool need_indirect_descriptor_sets;
1224 VkShaderStageFlags active_stages;
1225
1226 struct tu_streamout_state streamout;
1227
1228 struct
1229 {
1230 struct tu_bo binary_bo;
1231 struct tu_cs_entry state_ib;
1232 struct tu_cs_entry binning_state_ib;
1233
1234 struct tu_program_descriptor_linkage link[MESA_SHADER_STAGES];
1235 unsigned input_attachment_idx[MAX_RTS];
1236 } program;
1237
1238 struct
1239 {
1240 struct tu_cs_entry state_ib;
1241 } load_state;
1242
1243 struct
1244 {
1245 uint8_t bindings[MAX_VERTEX_ATTRIBS];
1246 uint32_t count;
1247
1248 uint8_t binning_bindings[MAX_VERTEX_ATTRIBS];
1249 uint32_t binning_count;
1250
1251 struct tu_cs_entry state_ib;
1252 struct tu_cs_entry binning_state_ib;
1253 } vi;
1254
1255 struct
1256 {
1257 enum pc_di_primtype primtype;
1258 bool primitive_restart;
1259 } ia;
1260
1261 struct
1262 {
1263 struct tu_cs_entry state_ib;
1264 } vp;
1265
1266 struct
1267 {
1268 uint32_t gras_su_cntl;
1269 struct tu_cs_entry state_ib;
1270 } rast;
1271
1272 struct
1273 {
1274 struct tu_cs_entry state_ib;
1275 } ds;
1276
1277 struct
1278 {
1279 struct tu_cs_entry state_ib;
1280 } blend;
1281
1282 struct
1283 {
1284 uint32_t local_size[3];
1285 } compute;
1286 };
1287
1288 void
1289 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport);
1290
1291 void
1292 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor);
1293
1294 void
1295 tu6_emit_sample_locations(struct tu_cs *cs, const VkSampleLocationsInfoEXT *samp_loc);
1296
1297 void
1298 tu6_emit_gras_su_cntl(struct tu_cs *cs,
1299 uint32_t gras_su_cntl,
1300 float line_width);
1301
1302 void
1303 tu6_emit_depth_bias(struct tu_cs *cs,
1304 float constant_factor,
1305 float clamp,
1306 float slope_factor);
1307
1308 void
1309 tu6_emit_stencil_compare_mask(struct tu_cs *cs,
1310 uint32_t front,
1311 uint32_t back);
1312
1313 void
1314 tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back);
1315
1316 void
1317 tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back);
1318
1319 void
1320 tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4]);
1321
1322 void tu6_emit_msaa(struct tu_cs *cs, VkSampleCountFlagBits samples);
1323
1324 void tu6_emit_window_scissor(struct tu_cs *cs, uint32_t x1, uint32_t y1, uint32_t x2, uint32_t y2);
1325
1326 void tu6_emit_window_offset(struct tu_cs *cs, uint32_t x1, uint32_t y1);
1327
1328 struct tu_image_view;
1329
1330 void
1331 tu_resolve_sysmem(struct tu_cmd_buffer *cmd,
1332 struct tu_cs *cs,
1333 struct tu_image_view *src,
1334 struct tu_image_view *dst,
1335 uint32_t layers,
1336 const VkRect2D *rect);
1337
1338 void
1339 tu_clear_sysmem_attachment(struct tu_cmd_buffer *cmd,
1340 struct tu_cs *cs,
1341 uint32_t a,
1342 const VkRenderPassBeginInfo *info);
1343
1344 void
1345 tu_clear_gmem_attachment(struct tu_cmd_buffer *cmd,
1346 struct tu_cs *cs,
1347 uint32_t a,
1348 const VkRenderPassBeginInfo *info);
1349
1350 void
1351 tu_load_gmem_attachment(struct tu_cmd_buffer *cmd,
1352 struct tu_cs *cs,
1353 uint32_t a,
1354 bool force_load);
1355
1356 /* expose this function to be able to emit load without checking LOAD_OP */
1357 void
1358 tu_emit_load_gmem_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t a);
1359
1360 /* note: gmem store can also resolve */
1361 void
1362 tu_store_gmem_attachment(struct tu_cmd_buffer *cmd,
1363 struct tu_cs *cs,
1364 uint32_t a,
1365 uint32_t gmem_a);
1366
1367 struct tu_userdata_info *
1368 tu_lookup_user_sgpr(struct tu_pipeline *pipeline,
1369 gl_shader_stage stage,
1370 int idx);
1371
1372 struct tu_shader_variant *
1373 tu_get_shader(struct tu_pipeline *pipeline, gl_shader_stage stage);
1374
1375 struct tu_graphics_pipeline_create_info
1376 {
1377 bool use_rectlist;
1378 bool db_depth_clear;
1379 bool db_stencil_clear;
1380 bool db_depth_disable_expclear;
1381 bool db_stencil_disable_expclear;
1382 bool db_flush_depth_inplace;
1383 bool db_flush_stencil_inplace;
1384 bool db_resummarize;
1385 uint32_t custom_blend_mode;
1386 };
1387
1388 enum tu_supported_formats {
1389 FMT_VERTEX = 1,
1390 FMT_TEXTURE = 2,
1391 FMT_COLOR = 4,
1392 };
1393
1394 struct tu_native_format
1395 {
1396 enum a6xx_format fmt : 8;
1397 enum a3xx_color_swap swap : 8;
1398 enum a6xx_tile_mode tile_mode : 8;
1399 enum tu_supported_formats supported : 8;
1400 };
1401
1402 struct tu_native_format tu6_format_vtx(VkFormat format);
1403 struct tu_native_format tu6_format_color(VkFormat format, enum a6xx_tile_mode tile_mode);
1404 struct tu_native_format tu6_format_texture(VkFormat format, enum a6xx_tile_mode tile_mode);
1405
1406 static inline enum a6xx_format
1407 tu6_base_format(VkFormat format)
1408 {
1409 /* note: tu6_format_color doesn't care about tiling for .fmt field */
1410 return tu6_format_color(format, TILE6_LINEAR).fmt;
1411 }
1412
1413 enum a6xx_depth_format tu6_pipe2depth(VkFormat format);
1414
1415 struct tu_image
1416 {
1417 VkImageType type;
1418 /* The original VkFormat provided by the client. This may not match any
1419 * of the actual surface formats.
1420 */
1421 VkFormat vk_format;
1422 VkImageAspectFlags aspects;
1423 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1424 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1425 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1426 VkExtent3D extent;
1427 uint32_t level_count;
1428 uint32_t layer_count;
1429 VkSampleCountFlagBits samples;
1430
1431 struct fdl_layout layout;
1432
1433 unsigned queue_family_mask;
1434 bool exclusive;
1435 bool shareable;
1436
1437 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1438 VkDeviceMemory owned_memory;
1439
1440 /* Set when bound */
1441 struct tu_bo *bo;
1442 VkDeviceSize bo_offset;
1443 };
1444
1445 unsigned
1446 tu_image_queue_family_mask(const struct tu_image *image,
1447 uint32_t family,
1448 uint32_t queue_family);
1449
1450 static inline uint32_t
1451 tu_get_layerCount(const struct tu_image *image,
1452 const VkImageSubresourceRange *range)
1453 {
1454 return range->layerCount == VK_REMAINING_ARRAY_LAYERS
1455 ? image->layer_count - range->baseArrayLayer
1456 : range->layerCount;
1457 }
1458
1459 static inline uint32_t
1460 tu_get_levelCount(const struct tu_image *image,
1461 const VkImageSubresourceRange *range)
1462 {
1463 return range->levelCount == VK_REMAINING_MIP_LEVELS
1464 ? image->level_count - range->baseMipLevel
1465 : range->levelCount;
1466 }
1467
1468 enum a3xx_msaa_samples
1469 tu_msaa_samples(uint32_t samples);
1470 enum a6xx_tex_fetchsize
1471 tu6_fetchsize(VkFormat format);
1472
1473 struct tu_image_view
1474 {
1475 struct tu_image *image; /**< VkImageViewCreateInfo::image */
1476
1477 uint64_t base_addr;
1478 uint64_t ubwc_addr;
1479 uint32_t layer_size;
1480 uint32_t ubwc_layer_size;
1481
1482 /* used to determine if fast gmem store path can be used */
1483 VkExtent2D extent;
1484 bool need_y2_align;
1485
1486 bool ubwc_enabled;
1487
1488 uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
1489
1490 /* Descriptor for use as a storage image as opposed to a sampled image.
1491 * This has a few differences for cube maps (e.g. type).
1492 */
1493 uint32_t storage_descriptor[A6XX_TEX_CONST_DWORDS];
1494
1495 /* pre-filled register values */
1496 uint32_t PITCH;
1497 uint32_t FLAG_BUFFER_PITCH;
1498
1499 uint32_t RB_MRT_BUF_INFO;
1500 uint32_t SP_FS_MRT_REG;
1501
1502 uint32_t SP_PS_2D_SRC_INFO;
1503 uint32_t SP_PS_2D_SRC_SIZE;
1504
1505 uint32_t RB_2D_DST_INFO;
1506
1507 uint32_t RB_BLIT_DST_INFO;
1508 };
1509
1510 struct tu_sampler_ycbcr_conversion {
1511 VkFormat format;
1512 VkSamplerYcbcrModelConversion ycbcr_model;
1513 VkSamplerYcbcrRange ycbcr_range;
1514 VkComponentMapping components;
1515 VkChromaLocation chroma_offsets[2];
1516 VkFilter chroma_filter;
1517 };
1518
1519 struct tu_sampler {
1520 uint32_t descriptor[A6XX_TEX_SAMP_DWORDS];
1521 struct tu_sampler_ycbcr_conversion *ycbcr_sampler;
1522 };
1523
1524 void
1525 tu_cs_image_ref(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer);
1526
1527 void
1528 tu_cs_image_ref_2d(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer, bool src);
1529
1530 void
1531 tu_cs_image_flag_ref(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer);
1532
1533 VkResult
1534 tu_image_create(VkDevice _device,
1535 const VkImageCreateInfo *pCreateInfo,
1536 const VkAllocationCallbacks *alloc,
1537 VkImage *pImage,
1538 uint64_t modifier,
1539 const VkSubresourceLayout *plane_layouts);
1540
1541 VkResult
1542 tu_image_from_gralloc(VkDevice device_h,
1543 const VkImageCreateInfo *base_info,
1544 const VkNativeBufferANDROID *gralloc_info,
1545 const VkAllocationCallbacks *alloc,
1546 VkImage *out_image_h);
1547
1548 void
1549 tu_image_view_init(struct tu_image_view *view,
1550 const VkImageViewCreateInfo *pCreateInfo);
1551
1552 struct tu_buffer_view
1553 {
1554 uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
1555
1556 struct tu_buffer *buffer;
1557 };
1558 void
1559 tu_buffer_view_init(struct tu_buffer_view *view,
1560 struct tu_device *device,
1561 const VkBufferViewCreateInfo *pCreateInfo);
1562
1563 static inline struct VkExtent3D
1564 tu_sanitize_image_extent(const VkImageType imageType,
1565 const struct VkExtent3D imageExtent)
1566 {
1567 switch (imageType) {
1568 case VK_IMAGE_TYPE_1D:
1569 return (VkExtent3D) { imageExtent.width, 1, 1 };
1570 case VK_IMAGE_TYPE_2D:
1571 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1572 case VK_IMAGE_TYPE_3D:
1573 return imageExtent;
1574 default:
1575 unreachable("invalid image type");
1576 }
1577 }
1578
1579 static inline struct VkOffset3D
1580 tu_sanitize_image_offset(const VkImageType imageType,
1581 const struct VkOffset3D imageOffset)
1582 {
1583 switch (imageType) {
1584 case VK_IMAGE_TYPE_1D:
1585 return (VkOffset3D) { imageOffset.x, 0, 0 };
1586 case VK_IMAGE_TYPE_2D:
1587 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1588 case VK_IMAGE_TYPE_3D:
1589 return imageOffset;
1590 default:
1591 unreachable("invalid image type");
1592 }
1593 }
1594
1595 struct tu_attachment_info
1596 {
1597 struct tu_image_view *attachment;
1598 };
1599
1600 struct tu_framebuffer
1601 {
1602 uint32_t width;
1603 uint32_t height;
1604 uint32_t layers;
1605
1606 uint32_t attachment_count;
1607 struct tu_attachment_info attachments[0];
1608 };
1609
1610 struct tu_subpass_attachment
1611 {
1612 uint32_t attachment;
1613 };
1614
1615 struct tu_subpass
1616 {
1617 uint32_t input_count;
1618 uint32_t color_count;
1619 struct tu_subpass_attachment *input_attachments;
1620 struct tu_subpass_attachment *color_attachments;
1621 struct tu_subpass_attachment *resolve_attachments;
1622 struct tu_subpass_attachment depth_stencil_attachment;
1623
1624 VkSampleCountFlagBits samples;
1625
1626 uint32_t srgb_cntl;
1627 };
1628
1629 struct tu_render_pass_attachment
1630 {
1631 VkFormat format;
1632 uint32_t samples;
1633 uint32_t cpp;
1634 VkImageAspectFlags clear_mask;
1635 bool load;
1636 bool store;
1637 int32_t gmem_offset;
1638 };
1639
1640 struct tu_render_pass
1641 {
1642 uint32_t attachment_count;
1643 uint32_t subpass_count;
1644 uint32_t gmem_pixels;
1645 uint32_t tile_align_w;
1646 struct tu_subpass_attachment *subpass_attachments;
1647 struct tu_render_pass_attachment *attachments;
1648 struct tu_subpass subpasses[0];
1649 };
1650
1651 VkResult
1652 tu_device_init_meta(struct tu_device *device);
1653 void
1654 tu_device_finish_meta(struct tu_device *device);
1655
1656 struct tu_query_pool
1657 {
1658 VkQueryType type;
1659 uint32_t stride;
1660 uint64_t size;
1661 uint32_t pipeline_statistics;
1662 struct tu_bo bo;
1663 };
1664
1665 struct tu_semaphore
1666 {
1667 uint32_t syncobj;
1668 uint32_t temp_syncobj;
1669 };
1670
1671 void
1672 tu_set_descriptor_set(struct tu_cmd_buffer *cmd_buffer,
1673 VkPipelineBindPoint bind_point,
1674 struct tu_descriptor_set *set,
1675 unsigned idx);
1676
1677 void
1678 tu_update_descriptor_sets(struct tu_device *device,
1679 struct tu_cmd_buffer *cmd_buffer,
1680 VkDescriptorSet overrideSet,
1681 uint32_t descriptorWriteCount,
1682 const VkWriteDescriptorSet *pDescriptorWrites,
1683 uint32_t descriptorCopyCount,
1684 const VkCopyDescriptorSet *pDescriptorCopies);
1685
1686 void
1687 tu_update_descriptor_set_with_template(
1688 struct tu_device *device,
1689 struct tu_cmd_buffer *cmd_buffer,
1690 struct tu_descriptor_set *set,
1691 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
1692 const void *pData);
1693
1694 void
1695 tu_meta_push_descriptor_set(struct tu_cmd_buffer *cmd_buffer,
1696 VkPipelineBindPoint pipelineBindPoint,
1697 VkPipelineLayout _layout,
1698 uint32_t set,
1699 uint32_t descriptorWriteCount,
1700 const VkWriteDescriptorSet *pDescriptorWrites);
1701
1702 int
1703 tu_drm_get_gpu_id(const struct tu_physical_device *dev, uint32_t *id);
1704
1705 int
1706 tu_drm_get_gmem_size(const struct tu_physical_device *dev, uint32_t *size);
1707
1708 int
1709 tu_drm_get_gmem_base(const struct tu_physical_device *dev, uint64_t *base);
1710
1711 int
1712 tu_drm_submitqueue_new(const struct tu_device *dev,
1713 int priority,
1714 uint32_t *queue_id);
1715
1716 void
1717 tu_drm_submitqueue_close(const struct tu_device *dev, uint32_t queue_id);
1718
1719 uint32_t
1720 tu_gem_new(const struct tu_device *dev, uint64_t size, uint32_t flags);
1721 uint32_t
1722 tu_gem_import_dmabuf(const struct tu_device *dev,
1723 int prime_fd,
1724 uint64_t size);
1725 int
1726 tu_gem_export_dmabuf(const struct tu_device *dev, uint32_t gem_handle);
1727 void
1728 tu_gem_close(const struct tu_device *dev, uint32_t gem_handle);
1729 uint64_t
1730 tu_gem_info_offset(const struct tu_device *dev, uint32_t gem_handle);
1731 uint64_t
1732 tu_gem_info_iova(const struct tu_device *dev, uint32_t gem_handle);
1733
1734 #define TU_DEFINE_HANDLE_CASTS(__tu_type, __VkType) \
1735 \
1736 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1737 { \
1738 return (struct __tu_type *) _handle; \
1739 } \
1740 \
1741 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1742 { \
1743 return (__VkType) _obj; \
1744 }
1745
1746 #define TU_DEFINE_NONDISP_HANDLE_CASTS(__tu_type, __VkType) \
1747 \
1748 static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1749 { \
1750 return (struct __tu_type *) (uintptr_t) _handle; \
1751 } \
1752 \
1753 static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj) \
1754 { \
1755 return (__VkType)(uintptr_t) _obj; \
1756 }
1757
1758 #define TU_FROM_HANDLE(__tu_type, __name, __handle) \
1759 struct __tu_type *__name = __tu_type##_from_handle(__handle)
1760
1761 TU_DEFINE_HANDLE_CASTS(tu_cmd_buffer, VkCommandBuffer)
1762 TU_DEFINE_HANDLE_CASTS(tu_device, VkDevice)
1763 TU_DEFINE_HANDLE_CASTS(tu_instance, VkInstance)
1764 TU_DEFINE_HANDLE_CASTS(tu_physical_device, VkPhysicalDevice)
1765 TU_DEFINE_HANDLE_CASTS(tu_queue, VkQueue)
1766
1767 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_cmd_pool, VkCommandPool)
1768 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer, VkBuffer)
1769 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer_view, VkBufferView)
1770 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_pool, VkDescriptorPool)
1771 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set, VkDescriptorSet)
1772 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set_layout,
1773 VkDescriptorSetLayout)
1774 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_update_template,
1775 VkDescriptorUpdateTemplate)
1776 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_device_memory, VkDeviceMemory)
1777 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_fence, VkFence)
1778 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_event, VkEvent)
1779 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_framebuffer, VkFramebuffer)
1780 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image, VkImage)
1781 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image_view, VkImageView);
1782 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_cache, VkPipelineCache)
1783 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline, VkPipeline)
1784 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_layout, VkPipelineLayout)
1785 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_query_pool, VkQueryPool)
1786 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_render_pass, VkRenderPass)
1787 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_sampler, VkSampler)
1788 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_sampler_ycbcr_conversion, VkSamplerYcbcrConversion)
1789 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_shader_module, VkShaderModule)
1790 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_semaphore, VkSemaphore)
1791
1792 #endif /* TU_PRIVATE_H */