src/freedreno/vulkan/tu_private.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  */
  27
  28 #ifndef TU_PRIVATE_H
  29 #define TU_PRIVATE_H
  30
  31 #include <assert.h>
  32 #include <pthread.h>
  33 #include <stdbool.h>
  34 #include <stdint.h>
  35 #include <stdio.h>
  36 #include <stdlib.h>
  37 #include <string.h>
  38 #ifdef HAVE_VALGRIND
  39 #include <memcheck.h>
  40 #include <valgrind.h>
  41 #define VG(x) x
  42 #else
  43 #define VG(x) ((void)0)
  44 #endif
  45
  46 #include "c11/threads.h"
  47 #include "main/macros.h"
  48 #include "util/list.h"
  49 #include "util/macros.h"
  50 #include "vk_alloc.h"
  51 #include "vk_debug_report.h"
  52 #include "wsi_common.h"
  53
  54 #include "drm-uapi/msm_drm.h"
  55 #include "ir3/ir3_compiler.h"
  56 #include "ir3/ir3_shader.h"
  57
  58 #include "adreno_common.xml.h"
  59 #include "adreno_pm4.xml.h"
  60 #include "a6xx.xml.h"
  61 #include "fdl/freedreno_layout.h"
  62
  63 #include "tu_descriptor_set.h"
  64 #include "tu_extensions.h"
  65 #include "tu_util.h"
  66
  67 /* Pre-declarations needed for WSI entrypoints */
  68 struct wl_surface;
  69 struct wl_display;
  70 typedef struct xcb_connection_t xcb_connection_t;
  71 typedef uint32_t xcb_visualid_t;
  72 typedef uint32_t xcb_window_t;
  73
  74 #include <vulkan/vk_android_native_buffer.h>
  75 #include <vulkan/vk_icd.h>
  76 #include <vulkan/vulkan.h>
  77 #include <vulkan/vulkan_intel.h>
  78
  79 #include "tu_entrypoints.h"
  80
  81 #include "vk_format.h"
  82
  83 #define MAX_VBS 32
  84 #define MAX_VERTEX_ATTRIBS 32
  85 #define MAX_RTS 8
  86 #define MAX_VSC_PIPES 32
  87 #define MAX_VIEWPORTS 1
  88 #define MAX_SCISSORS 16
  89 #define MAX_DISCARD_RECTANGLES 4
  90 #define MAX_PUSH_CONSTANTS_SIZE 128
  91 #define MAX_PUSH_DESCRIPTORS 32
  92 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
  93 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
  94 #define MAX_DYNAMIC_BUFFERS                                                  \
  95    (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
  96 #define TU_MAX_DRM_DEVICES 8
  97 #define MAX_VIEWS 8
  98 #define MAX_BIND_POINTS 2 /* compute + graphics */
  99 /* The Qualcomm driver exposes 0x20000058 */
 100 #define MAX_STORAGE_BUFFER_RANGE 0x20000000
 101 /* We use ldc for uniform buffer loads, just like the Qualcomm driver, so
 102  * expose the same maximum range.
 103  * TODO: The SIZE bitfield is 15 bits, and in 4-dword units, so the actual
 104  * range might be higher.
 105  */
 106 #define MAX_UNIFORM_BUFFER_RANGE 0x10000
 107
 108 #define A6XX_TEX_CONST_DWORDS 16
 109 #define A6XX_TEX_SAMP_DWORDS 4
 110
 111 #define tu_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
 112
 113 static inline uint32_t
 114 tu_minify(uint32_t n, uint32_t levels)
 115 {
 116    if (unlikely(n == 0))
 117       return 0;
 118    else
 119       return MAX2(n >> levels, 1);
 120 }
 121
 122 #define for_each_bit(b, dword)                                               \
 123    for (uint32_t __dword = (dword);                                          \
 124         (b) = __builtin_ffs(__dword) - 1, __dword; __dword &= ~(1 << (b)))
 125
 126 #define typed_memcpy(dest, src, count)                                       \
 127    ({                                                                        \
 128       STATIC_ASSERT(sizeof(*src) == sizeof(*dest));                          \
 129       memcpy((dest), (src), (count) * sizeof(*(src)));                       \
 130    })
 131
 132 #define COND(bool, val) ((bool) ? (val) : 0)
 133 #define BIT(bit) (1u << (bit))
 134
 135 /* Whenever we generate an error, pass it through this function. Useful for
 136  * debugging, where we can break on it. Only call at error site, not when
 137  * propagating errors. Might be useful to plug in a stack trace here.
 138  */
 139
 140 struct tu_instance;
 141
 142 VkResult
 143 __vk_errorf(struct tu_instance *instance,
 144             VkResult error,
 145             const char *file,
 146             int line,
 147             const char *format,
 148             ...);
 149
 150 #define vk_error(instance, error)                                            \
 151    __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
 152 #define vk_errorf(instance, error, format, ...)                              \
 153    __vk_errorf(instance, error, __FILE__, __LINE__, format, ##__VA_ARGS__);
 154
 155 void
 156 __tu_finishme(const char *file, int line, const char *format, ...)
 157    tu_printflike(3, 4);
 158 void
 159 tu_loge(const char *format, ...) tu_printflike(1, 2);
 160 void
 161 tu_logi(const char *format, ...) tu_printflike(1, 2);
 162
 163 /**
 164  * Print a FINISHME message, including its source location.
 165  */
 166 #define tu_finishme(format, ...)                                             \
 167    do {                                                                      \
 168       static bool reported = false;                                          \
 169       if (!reported) {                                                       \
 170          __tu_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__);           \
 171          reported = true;                                                    \
 172       }                                                                      \
 173    } while (0)
 174
 175 #define tu_stub()                                                            \
 176    do {                                                                      \
 177       tu_finishme("stub %s", __func__);                                      \
 178    } while (0)
 179
 180 void *
 181 tu_lookup_entrypoint_unchecked(const char *name);
 182 void *
 183 tu_lookup_entrypoint_checked(
 184    const char *name,
 185    uint32_t core_version,
 186    const struct tu_instance_extension_table *instance,
 187    const struct tu_device_extension_table *device);
 188
 189 struct tu_physical_device
 190 {
 191    VK_LOADER_DATA _loader_data;
 192
 193    struct tu_instance *instance;
 194
 195    char path[20];
 196    char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
 197    uint8_t driver_uuid[VK_UUID_SIZE];
 198    uint8_t device_uuid[VK_UUID_SIZE];
 199    uint8_t cache_uuid[VK_UUID_SIZE];
 200
 201    struct wsi_device wsi_device;
 202
 203    int local_fd;
 204    int master_fd;
 205
 206    unsigned gpu_id;
 207    uint32_t gmem_size;
 208    uint64_t gmem_base;
 209    uint32_t ccu_offset_gmem;
 210    uint32_t ccu_offset_bypass;
 211    /* alignment for size of tiles */
 212    uint32_t tile_align_w;
 213 #define TILE_ALIGN_H 16
 214    /* gmem store/load granularity */
 215 #define GMEM_ALIGN_W 16
 216 #define GMEM_ALIGN_H 4
 217
 218    struct {
 219       uint32_t PC_UNKNOWN_9805;
 220       uint32_t SP_UNKNOWN_A0F8;
 221    } magic;
 222
 223    /* This is the drivers on-disk cache used as a fallback as opposed to
 224     * the pipeline cache defined by apps.
 225     */
 226    struct disk_cache *disk_cache;
 227
 228    struct tu_device_extension_table supported_extensions;
 229 };
 230
 231 enum tu_debug_flags
 232 {
 233    TU_DEBUG_STARTUP = 1 << 0,
 234    TU_DEBUG_NIR = 1 << 1,
 235    TU_DEBUG_IR3 = 1 << 2,
 236    TU_DEBUG_NOBIN = 1 << 3,
 237    TU_DEBUG_SYSMEM = 1 << 4,
 238    TU_DEBUG_FORCEBIN = 1 << 5,
 239    TU_DEBUG_NOUBWC = 1 << 6,
 240 };
 241
 242 struct tu_instance
 243 {
 244    VK_LOADER_DATA _loader_data;
 245
 246    VkAllocationCallbacks alloc;
 247
 248    uint32_t api_version;
 249    int physical_device_count;
 250    struct tu_physical_device physical_devices[TU_MAX_DRM_DEVICES];
 251
 252    enum tu_debug_flags debug_flags;
 253
 254    struct vk_debug_report_instance debug_report_callbacks;
 255
 256    struct tu_instance_extension_table enabled_extensions;
 257 };
 258
 259 VkResult
 260 tu_wsi_init(struct tu_physical_device *physical_device);
 261 void
 262 tu_wsi_finish(struct tu_physical_device *physical_device);
 263
 264 bool
 265 tu_instance_extension_supported(const char *name);
 266 uint32_t
 267 tu_physical_device_api_version(struct tu_physical_device *dev);
 268 bool
 269 tu_physical_device_extension_supported(struct tu_physical_device *dev,
 270                                        const char *name);
 271
 272 struct cache_entry;
 273
 274 struct tu_pipeline_cache
 275 {
 276    struct tu_device *device;
 277    pthread_mutex_t mutex;
 278
 279    uint32_t total_size;
 280    uint32_t table_size;
 281    uint32_t kernel_count;
 282    struct cache_entry **hash_table;
 283    bool modified;
 284
 285    VkAllocationCallbacks alloc;
 286 };
 287
 288 struct tu_pipeline_key
 289 {
 290 };
 291
 292
 293 /* queue types */
 294 #define TU_QUEUE_GENERAL 0
 295
 296 #define TU_MAX_QUEUE_FAMILIES 1
 297
 298 struct tu_fence
 299 {
 300    struct wsi_fence *fence_wsi;
 301    bool signaled;
 302    int fd;
 303 };
 304
 305 void
 306 tu_fence_init(struct tu_fence *fence, bool signaled);
 307 void
 308 tu_fence_finish(struct tu_fence *fence);
 309 void
 310 tu_fence_update_fd(struct tu_fence *fence, int fd);
 311 void
 312 tu_fence_copy(struct tu_fence *fence, const struct tu_fence *src);
 313 void
 314 tu_fence_signal(struct tu_fence *fence);
 315 void
 316 tu_fence_wait_idle(struct tu_fence *fence);
 317
 318 struct tu_queue
 319 {
 320    VK_LOADER_DATA _loader_data;
 321    struct tu_device *device;
 322    uint32_t queue_family_index;
 323    int queue_idx;
 324    VkDeviceQueueCreateFlags flags;
 325
 326    uint32_t msm_queue_id;
 327    struct tu_fence submit_fence;
 328 };
 329
 330 struct tu_bo
 331 {
 332    uint32_t gem_handle;
 333    uint64_t size;
 334    uint64_t iova;
 335    void *map;
 336 };
 337
 338 struct tu_device
 339 {
 340    VK_LOADER_DATA _loader_data;
 341
 342    VkAllocationCallbacks alloc;
 343
 344    struct tu_instance *instance;
 345
 346    struct tu_queue *queues[TU_MAX_QUEUE_FAMILIES];
 347    int queue_count[TU_MAX_QUEUE_FAMILIES];
 348
 349    struct tu_physical_device *physical_device;
 350
 351    struct ir3_compiler *compiler;
 352
 353    /* Backup in-memory cache to be used if the app doesn't provide one */
 354    struct tu_pipeline_cache *mem_cache;
 355
 356    struct tu_bo vsc_draw_strm;
 357    struct tu_bo vsc_prim_strm;
 358    uint32_t vsc_draw_strm_pitch;
 359    uint32_t vsc_prim_strm_pitch;
 360
 361 #define MIN_SCRATCH_BO_SIZE_LOG2 12 /* A page */
 362
 363    /* Currently the kernel driver uses a 32-bit GPU address space, but it
 364     * should be impossible to go beyond 48 bits.
 365     */
 366    struct {
 367       struct tu_bo bo;
 368       mtx_t construct_mtx;
 369       bool initialized;
 370    } scratch_bos[48 - MIN_SCRATCH_BO_SIZE_LOG2];
 371
 372    struct tu_bo border_color;
 373
 374    struct tu_device_extension_table enabled_extensions;
 375 };
 376
 377 VkResult
 378 tu_bo_init_new(struct tu_device *dev, struct tu_bo *bo, uint64_t size);
 379 VkResult
 380 tu_bo_init_dmabuf(struct tu_device *dev,
 381                   struct tu_bo *bo,
 382                   uint64_t size,
 383                   int fd);
 384 int
 385 tu_bo_export_dmabuf(struct tu_device *dev, struct tu_bo *bo);
 386 void
 387 tu_bo_finish(struct tu_device *dev, struct tu_bo *bo);
 388 VkResult
 389 tu_bo_map(struct tu_device *dev, struct tu_bo *bo);
 390
 391 /* Get a scratch bo for use inside a command buffer. This will always return
 392  * the same bo given the same size or similar sizes, so only one scratch bo
 393  * can be used at the same time. It's meant for short-lived things where we
 394  * need to write to some piece of memory, read from it, and then immediately
 395  * discard it.
 396  */
 397 VkResult
 398 tu_get_scratch_bo(struct tu_device *dev, uint64_t size, struct tu_bo **bo);
 399
 400 struct tu_cs_entry
 401 {
 402    /* No ownership */
 403    const struct tu_bo *bo;
 404
 405    uint32_t size;
 406    uint32_t offset;
 407 };
 408
 409 struct ts_cs_memory {
 410    uint32_t *map;
 411    uint64_t iova;
 412 };
 413
 414 struct tu_draw_state {
 415    uint64_t iova : 48;
 416    uint32_t size : 16;
 417 };
 418
 419 enum tu_dynamic_state
 420 {
 421    /* re-use VK_DYNAMIC_STATE_ enums for non-extended dynamic states */
 422    TU_DYNAMIC_STATE_SAMPLE_LOCATIONS = VK_DYNAMIC_STATE_STENCIL_REFERENCE + 1,
 423    TU_DYNAMIC_STATE_COUNT,
 424 };
 425
 426 enum tu_draw_state_group_id
 427 {
 428    TU_DRAW_STATE_PROGRAM,
 429    TU_DRAW_STATE_PROGRAM_BINNING,
 430    TU_DRAW_STATE_VB,
 431    TU_DRAW_STATE_VI,
 432    TU_DRAW_STATE_VI_BINNING,
 433    TU_DRAW_STATE_RAST,
 434    TU_DRAW_STATE_DS,
 435    TU_DRAW_STATE_BLEND,
 436    TU_DRAW_STATE_VS_CONST,
 437    TU_DRAW_STATE_GS_CONST,
 438    TU_DRAW_STATE_FS_CONST,
 439    TU_DRAW_STATE_DESC_SETS,
 440    TU_DRAW_STATE_DESC_SETS_LOAD,
 441    TU_DRAW_STATE_VS_PARAMS,
 442    TU_DRAW_STATE_INPUT_ATTACHMENTS_GMEM,
 443    TU_DRAW_STATE_INPUT_ATTACHMENTS_SYSMEM,
 444
 445    /* dynamic state related draw states */
 446    TU_DRAW_STATE_DYNAMIC,
 447    TU_DRAW_STATE_COUNT = TU_DRAW_STATE_DYNAMIC + TU_DYNAMIC_STATE_COUNT,
 448 };
 449
 450 enum tu_cs_mode
 451 {
 452
 453    /*
 454     * A command stream in TU_CS_MODE_GROW mode grows automatically whenever it
 455     * is full.  tu_cs_begin must be called before command packet emission and
 456     * tu_cs_end must be called after.
 457     *
 458     * This mode may create multiple entries internally.  The entries must be
 459     * submitted together.
 460     */
 461    TU_CS_MODE_GROW,
 462
 463    /*
 464     * A command stream in TU_CS_MODE_EXTERNAL mode wraps an external,
 465     * fixed-size buffer.  tu_cs_begin and tu_cs_end are optional and have no
 466     * effect on it.
 467     *
 468     * This mode does not create any entry or any BO.
 469     */
 470    TU_CS_MODE_EXTERNAL,
 471
 472    /*
 473     * A command stream in TU_CS_MODE_SUB_STREAM mode does not support direct
 474     * command packet emission.  tu_cs_begin_sub_stream must be called to get a
 475     * sub-stream to emit comamnd packets to.  When done with the sub-stream,
 476     * tu_cs_end_sub_stream must be called.
 477     *
 478     * This mode does not create any entry internally.
 479     */
 480    TU_CS_MODE_SUB_STREAM,
 481 };
 482
 483 struct tu_cs
 484 {
 485    uint32_t *start;
 486    uint32_t *cur;
 487    uint32_t *reserved_end;
 488    uint32_t *end;
 489
 490    struct tu_device *device;
 491    enum tu_cs_mode mode;
 492    uint32_t next_bo_size;
 493
 494    struct tu_cs_entry *entries;
 495    uint32_t entry_count;
 496    uint32_t entry_capacity;
 497
 498    struct tu_bo **bos;
 499    uint32_t bo_count;
 500    uint32_t bo_capacity;
 501
 502    /* state for cond_exec_start/cond_exec_end */
 503    uint32_t cond_flags;
 504    uint32_t *cond_dwords;
 505 };
 506
 507 struct tu_device_memory
 508 {
 509    struct tu_bo bo;
 510    VkDeviceSize size;
 511
 512    /* for dedicated allocations */
 513    struct tu_image *image;
 514    struct tu_buffer *buffer;
 515
 516    uint32_t type_index;
 517    void *map;
 518    void *user_ptr;
 519 };
 520
 521 struct tu_descriptor_range
 522 {
 523    uint64_t va;
 524    uint32_t size;
 525 };
 526
 527 struct tu_descriptor_set
 528 {
 529    const struct tu_descriptor_set_layout *layout;
 530    struct tu_descriptor_pool *pool;
 531    uint32_t size;
 532
 533    uint64_t va;
 534    uint32_t *mapped_ptr;
 535
 536    uint32_t *dynamic_descriptors;
 537
 538    struct tu_bo *buffers[0];
 539 };
 540
 541 struct tu_push_descriptor_set
 542 {
 543    struct tu_descriptor_set set;
 544    uint32_t capacity;
 545 };
 546
 547 struct tu_descriptor_pool_entry
 548 {
 549    uint32_t offset;
 550    uint32_t size;
 551    struct tu_descriptor_set *set;
 552 };
 553
 554 struct tu_descriptor_pool
 555 {
 556    struct tu_bo bo;
 557    uint64_t current_offset;
 558    uint64_t size;
 559
 560    uint8_t *host_memory_base;
 561    uint8_t *host_memory_ptr;
 562    uint8_t *host_memory_end;
 563
 564    uint32_t entry_count;
 565    uint32_t max_entry_count;
 566    struct tu_descriptor_pool_entry entries[0];
 567 };
 568
 569 struct tu_descriptor_update_template_entry
 570 {
 571    VkDescriptorType descriptor_type;
 572
 573    /* The number of descriptors to update */
 574    uint32_t descriptor_count;
 575
 576    /* Into mapped_ptr or dynamic_descriptors, in units of the respective array
 577     */
 578    uint32_t dst_offset;
 579
 580    /* In dwords. Not valid/used for dynamic descriptors */
 581    uint32_t dst_stride;
 582
 583    uint32_t buffer_offset;
 584
 585    /* Only valid for combined image samplers and samplers */
 586    uint16_t has_sampler;
 587
 588    /* In bytes */
 589    size_t src_offset;
 590    size_t src_stride;
 591
 592    /* For push descriptors */
 593    const uint32_t *immutable_samplers;
 594 };
 595
 596 struct tu_descriptor_update_template
 597 {
 598    uint32_t entry_count;
 599    struct tu_descriptor_update_template_entry entry[0];
 600 };
 601
 602 struct tu_buffer
 603 {
 604    VkDeviceSize size;
 605
 606    VkBufferUsageFlags usage;
 607    VkBufferCreateFlags flags;
 608
 609    struct tu_bo *bo;
 610    VkDeviceSize bo_offset;
 611 };
 612
 613 static inline uint64_t
 614 tu_buffer_iova(struct tu_buffer *buffer)
 615 {
 616    return buffer->bo->iova + buffer->bo_offset;
 617 }
 618
 619 struct tu_vertex_binding
 620 {
 621    struct tu_buffer *buffer;
 622    VkDeviceSize offset;
 623 };
 624
 625 const char *
 626 tu_get_debug_option_name(int id);
 627
 628 const char *
 629 tu_get_perftest_option_name(int id);
 630
 631 struct tu_descriptor_state
 632 {
 633    struct tu_descriptor_set *sets[MAX_SETS];
 634    uint32_t dynamic_descriptors[MAX_DYNAMIC_BUFFERS * A6XX_TEX_CONST_DWORDS];
 635 };
 636
 637 struct tu_tile
 638 {
 639    uint8_t pipe;
 640    uint8_t slot;
 641    VkOffset2D begin;
 642    VkOffset2D end;
 643 };
 644
 645 struct tu_tiling_config
 646 {
 647    VkRect2D render_area;
 648
 649    /* position and size of the first tile */
 650    VkRect2D tile0;
 651    /* number of tiles */
 652    VkExtent2D tile_count;
 653
 654    /* size of the first VSC pipe */
 655    VkExtent2D pipe0;
 656    /* number of VSC pipes */
 657    VkExtent2D pipe_count;
 658
 659    /* pipe register values */
 660    uint32_t pipe_config[MAX_VSC_PIPES];
 661    uint32_t pipe_sizes[MAX_VSC_PIPES];
 662
 663    /* Whether sysmem rendering must be used */
 664    bool force_sysmem;
 665 };
 666
 667 enum tu_cmd_dirty_bits
 668 {
 669    TU_CMD_DIRTY_COMPUTE_PIPELINE = 1 << 1,
 670    TU_CMD_DIRTY_VERTEX_BUFFERS = 1 << 2,
 671    TU_CMD_DIRTY_DESCRIPTOR_SETS = 1 << 3,
 672    TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS = 1 << 4,
 673    TU_CMD_DIRTY_SHADER_CONSTS = 1 << 5,
 674    TU_CMD_DIRTY_STREAMOUT_BUFFERS = 1 << 6,
 675    /* all draw states were disabled and need to be re-enabled: */
 676    TU_CMD_DIRTY_DRAW_STATE = 1 << 7,
 677 };
 678
 679 struct tu_streamout_state {
 680    uint16_t stride[IR3_MAX_SO_BUFFERS];
 681    uint32_t ncomp[IR3_MAX_SO_BUFFERS];
 682    uint32_t prog[IR3_MAX_SO_OUTPUTS * 2];
 683    uint32_t prog_count;
 684    uint32_t vpc_so_buf_cntl;
 685 };
 686
 687 /* There are only three cache domains we have to care about: the CCU, or
 688  * color cache unit, which is used for color and depth/stencil attachments
 689  * and copy/blit destinations, and is split conceptually into color and depth,
 690  * and the universal cache or UCHE which is used for pretty much everything
 691  * else, except for the CP (uncached) and host. We need to flush whenever data
 692  * crosses these boundaries.
 693  */
 694
 695 enum tu_cmd_access_mask {
 696    TU_ACCESS_UCHE_READ = 1 << 0,
 697    TU_ACCESS_UCHE_WRITE = 1 << 1,
 698    TU_ACCESS_CCU_COLOR_READ = 1 << 2,
 699    TU_ACCESS_CCU_COLOR_WRITE = 1 << 3,
 700    TU_ACCESS_CCU_DEPTH_READ = 1 << 4,
 701    TU_ACCESS_CCU_DEPTH_WRITE = 1 << 5,
 702
 703    /* Experiments have shown that while it's safe to avoid flushing the CCU
 704     * after each blit/renderpass, it's not safe to assume that subsequent
 705     * lookups with a different attachment state will hit unflushed cache
 706     * entries. That is, the CCU needs to be flushed and possibly invalidated
 707     * when accessing memory with a different attachment state. Writing to an
 708     * attachment under the following conditions after clearing using the
 709     * normal 2d engine path is known to have issues:
 710     *
 711     * - It isn't the 0'th layer.
 712     * - There are more than one attachment, and this isn't the 0'th attachment
 713     *   (this seems to also depend on the cpp of the attachments).
 714     *
 715     * Our best guess is that the layer/MRT state is used when computing
 716     * the location of a cache entry in CCU, to avoid conflicts. We assume that
 717     * any access in a renderpass after or before an access by a transfer needs
 718     * a flush/invalidate, and use the _INCOHERENT variants to represent access
 719     * by a transfer.
 720     */
 721    TU_ACCESS_CCU_COLOR_INCOHERENT_READ = 1 << 6,
 722    TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE = 1 << 7,
 723    TU_ACCESS_CCU_DEPTH_INCOHERENT_READ = 1 << 8,
 724    TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE = 1 << 9,
 725
 726    TU_ACCESS_SYSMEM_READ = 1 << 10,
 727    TU_ACCESS_SYSMEM_WRITE = 1 << 11,
 728
 729    /* Set if a WFI is required due to data being read by the CP or the 2D
 730     * engine.
 731     */
 732    TU_ACCESS_WFI_READ = 1 << 12,
 733
 734    TU_ACCESS_READ =
 735       TU_ACCESS_UCHE_READ |
 736       TU_ACCESS_CCU_COLOR_READ |
 737       TU_ACCESS_CCU_DEPTH_READ |
 738       TU_ACCESS_CCU_COLOR_INCOHERENT_READ |
 739       TU_ACCESS_CCU_DEPTH_INCOHERENT_READ |
 740       TU_ACCESS_SYSMEM_READ,
 741
 742    TU_ACCESS_WRITE =
 743       TU_ACCESS_UCHE_WRITE |
 744       TU_ACCESS_CCU_COLOR_WRITE |
 745       TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE |
 746       TU_ACCESS_CCU_DEPTH_WRITE |
 747       TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE |
 748       TU_ACCESS_SYSMEM_WRITE,
 749
 750    TU_ACCESS_ALL =
 751       TU_ACCESS_READ |
 752       TU_ACCESS_WRITE,
 753 };
 754
 755 enum tu_cmd_flush_bits {
 756    TU_CMD_FLAG_CCU_FLUSH_DEPTH = 1 << 0,
 757    TU_CMD_FLAG_CCU_FLUSH_COLOR = 1 << 1,
 758    TU_CMD_FLAG_CCU_INVALIDATE_DEPTH = 1 << 2,
 759    TU_CMD_FLAG_CCU_INVALIDATE_COLOR = 1 << 3,
 760    TU_CMD_FLAG_CACHE_FLUSH = 1 << 4,
 761    TU_CMD_FLAG_CACHE_INVALIDATE = 1 << 5,
 762
 763    TU_CMD_FLAG_ALL_FLUSH =
 764       TU_CMD_FLAG_CCU_FLUSH_DEPTH |
 765       TU_CMD_FLAG_CCU_FLUSH_COLOR |
 766       TU_CMD_FLAG_CACHE_FLUSH,
 767
 768    TU_CMD_FLAG_ALL_INVALIDATE =
 769       TU_CMD_FLAG_CCU_INVALIDATE_DEPTH |
 770       TU_CMD_FLAG_CCU_INVALIDATE_COLOR |
 771       TU_CMD_FLAG_CACHE_INVALIDATE,
 772
 773    TU_CMD_FLAG_WFI = 1 << 6,
 774 };
 775
 776 /* Changing the CCU from sysmem mode to gmem mode or vice-versa is pretty
 777  * heavy, involving a CCU cache flush/invalidate and a WFI in order to change
 778  * which part of the gmem is used by the CCU. Here we keep track of what the
 779  * state of the CCU.
 780  */
 781 enum tu_cmd_ccu_state {
 782    TU_CMD_CCU_SYSMEM,
 783    TU_CMD_CCU_GMEM,
 784    TU_CMD_CCU_UNKNOWN,
 785 };
 786
 787 struct tu_cache_state {
 788    /* Caches which must be made available (flushed) eventually if there are
 789     * any users outside that cache domain, and caches which must be
 790     * invalidated eventually if there are any reads.
 791     */
 792    enum tu_cmd_flush_bits pending_flush_bits;
 793    /* Pending flushes */
 794    enum tu_cmd_flush_bits flush_bits;
 795 };
 796
 797 struct tu_cmd_state
 798 {
 799    uint32_t dirty;
 800
 801    struct tu_pipeline *pipeline;
 802    struct tu_pipeline *compute_pipeline;
 803
 804    /* Vertex buffers */
 805    struct
 806    {
 807       struct tu_buffer *buffers[MAX_VBS];
 808       VkDeviceSize offsets[MAX_VBS];
 809    } vb;
 810
 811    /* for dynamic states that can't be emitted directly */
 812    uint32_t dynamic_stencil_mask;
 813    uint32_t dynamic_stencil_wrmask;
 814    uint32_t dynamic_stencil_ref;
 815    uint32_t dynamic_gras_su_cntl;
 816
 817    /* saved states to re-emit in TU_CMD_DIRTY_DRAW_STATE case */
 818    struct tu_draw_state dynamic_state[TU_DYNAMIC_STATE_COUNT];
 819    struct tu_cs_entry vertex_buffers_ib;
 820    struct tu_cs_entry shader_const_ib[MESA_SHADER_STAGES];
 821    struct tu_cs_entry desc_sets_ib, desc_sets_load_ib;
 822    struct tu_cs_entry ia_gmem_ib, ia_sysmem_ib;
 823
 824    /* Stream output buffers */
 825    struct
 826    {
 827       struct tu_buffer *buffers[IR3_MAX_SO_BUFFERS];
 828       VkDeviceSize offsets[IR3_MAX_SO_BUFFERS];
 829       VkDeviceSize sizes[IR3_MAX_SO_BUFFERS];
 830    } streamout_buf;
 831
 832    uint8_t streamout_reset;
 833    uint8_t streamout_enabled;
 834
 835    /* Index buffer */
 836    struct tu_buffer *index_buffer;
 837    uint64_t index_offset;
 838    uint32_t index_type;
 839    uint32_t max_index_count;
 840    uint64_t index_va;
 841
 842    /* Renderpasses are tricky, because we may need to flush differently if
 843     * using sysmem vs. gmem and therefore we have to delay any flushing that
 844     * happens before a renderpass. So we have to have two copies of the flush
 845     * state, one for intra-renderpass flushes (i.e. renderpass dependencies)
 846     * and one for outside a renderpass.
 847     */
 848    struct tu_cache_state cache;
 849    struct tu_cache_state renderpass_cache;
 850
 851    enum tu_cmd_ccu_state ccu_state;
 852
 853    const struct tu_render_pass *pass;
 854    const struct tu_subpass *subpass;
 855    const struct tu_framebuffer *framebuffer;
 856
 857    struct tu_tiling_config tiling_config;
 858
 859    struct tu_cs_entry tile_store_ib;
 860 };
 861
 862 struct tu_cmd_pool
 863 {
 864    VkAllocationCallbacks alloc;
 865    struct list_head cmd_buffers;
 866    struct list_head free_cmd_buffers;
 867    uint32_t queue_family_index;
 868 };
 869
 870 struct tu_cmd_buffer_upload
 871 {
 872    uint8_t *map;
 873    unsigned offset;
 874    uint64_t size;
 875    struct list_head list;
 876 };
 877
 878 enum tu_cmd_buffer_status
 879 {
 880    TU_CMD_BUFFER_STATUS_INVALID,
 881    TU_CMD_BUFFER_STATUS_INITIAL,
 882    TU_CMD_BUFFER_STATUS_RECORDING,
 883    TU_CMD_BUFFER_STATUS_EXECUTABLE,
 884    TU_CMD_BUFFER_STATUS_PENDING,
 885 };
 886
 887 struct tu_bo_list
 888 {
 889    uint32_t count;
 890    uint32_t capacity;
 891    struct drm_msm_gem_submit_bo *bo_infos;
 892 };
 893
 894 #define TU_BO_LIST_FAILED (~0)
 895
 896 void
 897 tu_bo_list_init(struct tu_bo_list *list);
 898 void
 899 tu_bo_list_destroy(struct tu_bo_list *list);
 900 void
 901 tu_bo_list_reset(struct tu_bo_list *list);
 902 uint32_t
 903 tu_bo_list_add(struct tu_bo_list *list,
 904                const struct tu_bo *bo,
 905                uint32_t flags);
 906 VkResult
 907 tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other);
 908
 909 /* This struct defines the layout of the scratch_bo */
 910 struct tu6_control
 911 {
 912    uint32_t seqno_dummy;          /* dummy seqno for CP_EVENT_WRITE */
 913    uint32_t _pad0;
 914    volatile uint32_t vsc_overflow;
 915    uint32_t _pad1;
 916    /* flag set from cmdstream when VSC overflow detected: */
 917    uint32_t vsc_scratch;
 918    uint32_t _pad2;
 919    uint32_t _pad3;
 920    uint32_t _pad4;
 921
 922    /* scratch space for VPC_SO[i].FLUSH_BASE_LO/HI, start on 32 byte boundary. */
 923    struct {
 924       uint32_t offset;
 925       uint32_t pad[7];
 926    } flush_base[4];
 927 };
 928
 929 #define ctrl_offset(member) offsetof(struct tu6_control, member)
 930
 931 struct tu_cmd_buffer
 932 {
 933    VK_LOADER_DATA _loader_data;
 934
 935    struct tu_device *device;
 936
 937    struct tu_cmd_pool *pool;
 938    struct list_head pool_link;
 939
 940    VkCommandBufferUsageFlags usage_flags;
 941    VkCommandBufferLevel level;
 942    enum tu_cmd_buffer_status status;
 943
 944    struct tu_cmd_state state;
 945    struct tu_vertex_binding vertex_bindings[MAX_VBS];
 946    uint32_t vertex_bindings_set;
 947    uint32_t queue_family_index;
 948
 949    uint32_t push_constants[MAX_PUSH_CONSTANTS_SIZE / 4];
 950    VkShaderStageFlags push_constant_stages;
 951    struct tu_descriptor_set meta_push_descriptors;
 952
 953    struct tu_descriptor_state descriptors[MAX_BIND_POINTS];
 954
 955    struct tu_cmd_buffer_upload upload;
 956
 957    VkResult record_result;
 958
 959    struct tu_bo_list bo_list;
 960    struct tu_cs cs;
 961    struct tu_cs draw_cs;
 962    struct tu_cs draw_epilogue_cs;
 963    struct tu_cs sub_cs;
 964
 965    struct tu_bo scratch_bo;
 966
 967    struct tu_bo vsc_draw_strm;
 968    struct tu_bo vsc_prim_strm;
 969    uint32_t vsc_draw_strm_pitch;
 970    uint32_t vsc_prim_strm_pitch;
 971    bool use_vsc_data;
 972 };
 973
 974 /* Temporary struct for tracking a register state to be written, used by
 975  * a6xx-pack.h and tu_cs_emit_regs()
 976  */
 977 struct tu_reg_value {
 978    uint32_t reg;
 979    uint64_t value;
 980    bool is_address;
 981    struct tu_bo *bo;
 982    bool bo_write;
 983    uint32_t bo_offset;
 984    uint32_t bo_shift;
 985 };
 986
 987
 988 void tu_emit_cache_flush_renderpass(struct tu_cmd_buffer *cmd_buffer,
 989                                     struct tu_cs *cs);
 990
 991 void tu_emit_cache_flush_ccu(struct tu_cmd_buffer *cmd_buffer,
 992                              struct tu_cs *cs,
 993                              enum tu_cmd_ccu_state ccu_state);
 994
 995 void
 996 tu6_emit_event_write(struct tu_cmd_buffer *cmd,
 997                      struct tu_cs *cs,
 998                      enum vgt_event_type event);
 999
1000 static inline struct tu_descriptor_state *
1001 tu_get_descriptors_state(struct tu_cmd_buffer *cmd_buffer,
1002                          VkPipelineBindPoint bind_point)
1003 {
1004    return &cmd_buffer->descriptors[bind_point];
1005 }
1006
1007 struct tu_event
1008 {
1009    struct tu_bo bo;
1010 };
1011
1012 struct tu_shader_module
1013 {
1014    unsigned char sha1[20];
1015
1016    uint32_t code_size;
1017    const uint32_t *code[0];
1018 };
1019
1020 struct tu_push_constant_range
1021 {
1022    uint32_t lo;
1023    uint32_t count;
1024 };
1025
1026 struct tu_shader
1027 {
1028    struct ir3_shader *ir3_shader;
1029
1030    struct tu_push_constant_range push_consts;
1031    uint8_t active_desc_sets;
1032 };
1033
1034 struct tu_shader *
1035 tu_shader_create(struct tu_device *dev,
1036                  gl_shader_stage stage,
1037                  const VkPipelineShaderStageCreateInfo *stage_info,
1038                  struct tu_pipeline_layout *layout,
1039                  const VkAllocationCallbacks *alloc);
1040
1041 void
1042 tu_shader_destroy(struct tu_device *dev,
1043                   struct tu_shader *shader,
1044                   const VkAllocationCallbacks *alloc);
1045
1046 struct tu_program_descriptor_linkage
1047 {
1048    struct ir3_ubo_analysis_state ubo_state;
1049    struct ir3_const_state const_state;
1050
1051    uint32_t constlen;
1052
1053    struct tu_push_constant_range push_consts;
1054 };
1055
1056 struct tu_pipeline
1057 {
1058    struct tu_cs cs;
1059
1060    struct tu_pipeline_layout *layout;
1061
1062    bool need_indirect_descriptor_sets;
1063    VkShaderStageFlags active_stages;
1064    uint32_t active_desc_sets;
1065
1066    struct tu_streamout_state streamout;
1067
1068    /* mask of enabled dynamic states
1069     * if BIT(i) is set, pipeline->dynamic_state[i] is *NOT* used
1070     */
1071    uint32_t dynamic_state_mask;
1072    struct tu_draw_state dynamic_state[TU_DYNAMIC_STATE_COUNT];
1073
1074    /* gras_su_cntl without line width, used for dynamic line width state */
1075    uint32_t gras_su_cntl;
1076
1077    struct
1078    {
1079       struct tu_bo binary_bo;
1080       struct tu_cs_entry state_ib;
1081       struct tu_cs_entry binning_state_ib;
1082
1083       struct tu_program_descriptor_linkage link[MESA_SHADER_STAGES];
1084    } program;
1085
1086    struct
1087    {
1088       struct tu_cs_entry state_ib;
1089    } load_state;
1090
1091    struct
1092    {
1093       struct tu_cs_entry state_ib;
1094       struct tu_cs_entry binning_state_ib;
1095       uint32_t bindings_used;
1096    } vi;
1097
1098    struct
1099    {
1100       enum pc_di_primtype primtype;
1101       bool primitive_restart;
1102    } ia;
1103
1104    struct
1105    {
1106       struct tu_cs_entry state_ib;
1107    } rast;
1108
1109    struct
1110    {
1111       struct tu_cs_entry state_ib;
1112    } ds;
1113
1114    struct
1115    {
1116       struct tu_cs_entry state_ib;
1117    } blend;
1118
1119    struct
1120    {
1121       uint32_t local_size[3];
1122    } compute;
1123 };
1124
1125 void
1126 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport);
1127
1128 void
1129 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor);
1130
1131 void
1132 tu6_emit_sample_locations(struct tu_cs *cs, const VkSampleLocationsInfoEXT *samp_loc);
1133
1134 void
1135 tu6_emit_depth_bias(struct tu_cs *cs,
1136                     float constant_factor,
1137                     float clamp,
1138                     float slope_factor);
1139
1140 void tu6_emit_msaa(struct tu_cs *cs, VkSampleCountFlagBits samples);
1141
1142 void tu6_emit_window_scissor(struct tu_cs *cs, uint32_t x1, uint32_t y1, uint32_t x2, uint32_t y2);
1143
1144 void tu6_emit_window_offset(struct tu_cs *cs, uint32_t x1, uint32_t y1);
1145
1146 void
1147 tu6_emit_xs_config(struct tu_cs *cs,
1148                    gl_shader_stage stage,
1149                    const struct ir3_shader_variant *xs,
1150                    uint64_t binary_iova);
1151
1152 void
1153 tu6_emit_vpc(struct tu_cs *cs,
1154              const struct ir3_shader_variant *vs,
1155              const struct ir3_shader_variant *gs,
1156              const struct ir3_shader_variant *fs,
1157              struct tu_streamout_state *tf);
1158
1159 void
1160 tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs);
1161
1162 struct tu_image_view;
1163
1164 void
1165 tu_resolve_sysmem(struct tu_cmd_buffer *cmd,
1166                   struct tu_cs *cs,
1167                   struct tu_image_view *src,
1168                   struct tu_image_view *dst,
1169                   uint32_t layers,
1170                   const VkRect2D *rect);
1171
1172 void
1173 tu_clear_sysmem_attachment(struct tu_cmd_buffer *cmd,
1174                            struct tu_cs *cs,
1175                            uint32_t a,
1176                            const VkRenderPassBeginInfo *info);
1177
1178 void
1179 tu_clear_gmem_attachment(struct tu_cmd_buffer *cmd,
1180                          struct tu_cs *cs,
1181                          uint32_t a,
1182                          const VkRenderPassBeginInfo *info);
1183
1184 void
1185 tu_load_gmem_attachment(struct tu_cmd_buffer *cmd,
1186                         struct tu_cs *cs,
1187                         uint32_t a,
1188                         bool force_load);
1189
1190 /* expose this function to be able to emit load without checking LOAD_OP */
1191 void
1192 tu_emit_load_gmem_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t a);
1193
1194 /* note: gmem store can also resolve */
1195 void
1196 tu_store_gmem_attachment(struct tu_cmd_buffer *cmd,
1197                          struct tu_cs *cs,
1198                          uint32_t a,
1199                          uint32_t gmem_a);
1200
1201 enum tu_supported_formats {
1202    FMT_VERTEX = 1,
1203    FMT_TEXTURE = 2,
1204    FMT_COLOR = 4,
1205 };
1206
1207 struct tu_native_format
1208 {
1209    enum a6xx_format fmt : 8;
1210    enum a3xx_color_swap swap : 8;
1211    enum a6xx_tile_mode tile_mode : 8;
1212    enum tu_supported_formats supported : 8;
1213 };
1214
1215 struct tu_native_format tu6_format_vtx(VkFormat format);
1216 struct tu_native_format tu6_format_color(VkFormat format, enum a6xx_tile_mode tile_mode);
1217 struct tu_native_format tu6_format_texture(VkFormat format, enum a6xx_tile_mode tile_mode);
1218
1219 static inline enum a6xx_format
1220 tu6_base_format(VkFormat format)
1221 {
1222    /* note: tu6_format_color doesn't care about tiling for .fmt field */
1223    return tu6_format_color(format, TILE6_LINEAR).fmt;
1224 }
1225
1226 struct tu_image
1227 {
1228    VkImageType type;
1229    /* The original VkFormat provided by the client.  This may not match any
1230     * of the actual surface formats.
1231     */
1232    VkFormat vk_format;
1233    VkImageAspectFlags aspects;
1234    VkImageUsageFlags usage;  /**< Superset of VkImageCreateInfo::usage. */
1235    VkImageTiling tiling;     /** VkImageCreateInfo::tiling */
1236    VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1237    VkExtent3D extent;
1238    uint32_t level_count;
1239    uint32_t layer_count;
1240    VkSampleCountFlagBits samples;
1241
1242    struct fdl_layout layout;
1243
1244    unsigned queue_family_mask;
1245    bool exclusive;
1246    bool shareable;
1247
1248    /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1249    VkDeviceMemory owned_memory;
1250
1251    /* Set when bound */
1252    struct tu_bo *bo;
1253    VkDeviceSize bo_offset;
1254 };
1255
1256 static inline uint32_t
1257 tu_get_layerCount(const struct tu_image *image,
1258                   const VkImageSubresourceRange *range)
1259 {
1260    return range->layerCount == VK_REMAINING_ARRAY_LAYERS
1261              ? image->layer_count - range->baseArrayLayer
1262              : range->layerCount;
1263 }
1264
1265 static inline uint32_t
1266 tu_get_levelCount(const struct tu_image *image,
1267                   const VkImageSubresourceRange *range)
1268 {
1269    return range->levelCount == VK_REMAINING_MIP_LEVELS
1270              ? image->level_count - range->baseMipLevel
1271              : range->levelCount;
1272 }
1273
1274 struct tu_image_view
1275 {
1276    struct tu_image *image; /**< VkImageViewCreateInfo::image */
1277
1278    uint64_t base_addr;
1279    uint64_t ubwc_addr;
1280    uint32_t layer_size;
1281    uint32_t ubwc_layer_size;
1282
1283    /* used to determine if fast gmem store path can be used */
1284    VkExtent2D extent;
1285    bool need_y2_align;
1286
1287    bool ubwc_enabled;
1288
1289    uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
1290
1291    /* Descriptor for use as a storage image as opposed to a sampled image.
1292     * This has a few differences for cube maps (e.g. type).
1293     */
1294    uint32_t storage_descriptor[A6XX_TEX_CONST_DWORDS];
1295
1296    /* pre-filled register values */
1297    uint32_t PITCH;
1298    uint32_t FLAG_BUFFER_PITCH;
1299
1300    uint32_t RB_MRT_BUF_INFO;
1301    uint32_t SP_FS_MRT_REG;
1302
1303    uint32_t SP_PS_2D_SRC_INFO;
1304    uint32_t SP_PS_2D_SRC_SIZE;
1305
1306    uint32_t RB_2D_DST_INFO;
1307
1308    uint32_t RB_BLIT_DST_INFO;
1309 };
1310
1311 struct tu_sampler_ycbcr_conversion {
1312    VkFormat format;
1313    VkSamplerYcbcrModelConversion ycbcr_model;
1314    VkSamplerYcbcrRange ycbcr_range;
1315    VkComponentMapping components;
1316    VkChromaLocation chroma_offsets[2];
1317    VkFilter chroma_filter;
1318 };
1319
1320 struct tu_sampler {
1321    uint32_t descriptor[A6XX_TEX_SAMP_DWORDS];
1322    struct tu_sampler_ycbcr_conversion *ycbcr_sampler;
1323 };
1324
1325 void
1326 tu_cs_image_ref(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer);
1327
1328 void
1329 tu_cs_image_ref_2d(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer, bool src);
1330
1331 void
1332 tu_cs_image_flag_ref(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer);
1333
1334 VkResult
1335 tu_image_create(VkDevice _device,
1336                 const VkImageCreateInfo *pCreateInfo,
1337                 const VkAllocationCallbacks *alloc,
1338                 VkImage *pImage,
1339                 uint64_t modifier,
1340                 const VkSubresourceLayout *plane_layouts);
1341
1342 VkResult
1343 tu_image_from_gralloc(VkDevice device_h,
1344                       const VkImageCreateInfo *base_info,
1345                       const VkNativeBufferANDROID *gralloc_info,
1346                       const VkAllocationCallbacks *alloc,
1347                       VkImage *out_image_h);
1348
1349 void
1350 tu_image_view_init(struct tu_image_view *view,
1351                    const VkImageViewCreateInfo *pCreateInfo);
1352
1353 struct tu_buffer_view
1354 {
1355    uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
1356
1357    struct tu_buffer *buffer;
1358 };
1359 void
1360 tu_buffer_view_init(struct tu_buffer_view *view,
1361                     struct tu_device *device,
1362                     const VkBufferViewCreateInfo *pCreateInfo);
1363
1364 struct tu_attachment_info
1365 {
1366    struct tu_image_view *attachment;
1367 };
1368
1369 struct tu_framebuffer
1370 {
1371    uint32_t width;
1372    uint32_t height;
1373    uint32_t layers;
1374
1375    uint32_t attachment_count;
1376    struct tu_attachment_info attachments[0];
1377 };
1378
1379 struct tu_subpass_barrier {
1380    VkPipelineStageFlags src_stage_mask;
1381    VkAccessFlags src_access_mask;
1382    VkAccessFlags dst_access_mask;
1383    bool incoherent_ccu_color, incoherent_ccu_depth;
1384 };
1385
1386 struct tu_subpass_attachment
1387 {
1388    uint32_t attachment;
1389    VkImageLayout layout;
1390 };
1391
1392 struct tu_subpass
1393 {
1394    uint32_t input_count;
1395    uint32_t color_count;
1396    struct tu_subpass_attachment *input_attachments;
1397    struct tu_subpass_attachment *color_attachments;
1398    struct tu_subpass_attachment *resolve_attachments;
1399    struct tu_subpass_attachment depth_stencil_attachment;
1400
1401    VkSampleCountFlagBits samples;
1402    bool has_external_src, has_external_dst;
1403
1404    uint32_t srgb_cntl;
1405
1406    struct tu_subpass_barrier start_barrier;
1407 };
1408
1409 struct tu_render_pass_attachment
1410 {
1411    VkFormat format;
1412    uint32_t samples;
1413    uint32_t cpp;
1414    VkImageAspectFlags clear_mask;
1415    bool load;
1416    bool store;
1417    VkImageLayout initial_layout, final_layout;
1418    int32_t gmem_offset;
1419 };
1420
1421 struct tu_render_pass
1422 {
1423    uint32_t attachment_count;
1424    uint32_t subpass_count;
1425    uint32_t gmem_pixels;
1426    uint32_t tile_align_w;
1427    struct tu_subpass_attachment *subpass_attachments;
1428    struct tu_render_pass_attachment *attachments;
1429    struct tu_subpass_barrier end_barrier;
1430    struct tu_subpass subpasses[0];
1431 };
1432
1433 struct tu_query_pool
1434 {
1435    VkQueryType type;
1436    uint32_t stride;
1437    uint64_t size;
1438    uint32_t pipeline_statistics;
1439    struct tu_bo bo;
1440 };
1441
1442 struct tu_semaphore
1443 {
1444    uint32_t syncobj;
1445    uint32_t temp_syncobj;
1446 };
1447
1448 void
1449 tu_set_descriptor_set(struct tu_cmd_buffer *cmd_buffer,
1450                       VkPipelineBindPoint bind_point,
1451                       struct tu_descriptor_set *set,
1452                       unsigned idx);
1453
1454 void
1455 tu_update_descriptor_sets(struct tu_device *device,
1456                           struct tu_cmd_buffer *cmd_buffer,
1457                           VkDescriptorSet overrideSet,
1458                           uint32_t descriptorWriteCount,
1459                           const VkWriteDescriptorSet *pDescriptorWrites,
1460                           uint32_t descriptorCopyCount,
1461                           const VkCopyDescriptorSet *pDescriptorCopies);
1462
1463 void
1464 tu_update_descriptor_set_with_template(
1465    struct tu_device *device,
1466    struct tu_cmd_buffer *cmd_buffer,
1467    struct tu_descriptor_set *set,
1468    VkDescriptorUpdateTemplate descriptorUpdateTemplate,
1469    const void *pData);
1470
1471 int
1472 tu_drm_get_gpu_id(const struct tu_physical_device *dev, uint32_t *id);
1473
1474 int
1475 tu_drm_get_gmem_size(const struct tu_physical_device *dev, uint32_t *size);
1476
1477 int
1478 tu_drm_get_gmem_base(const struct tu_physical_device *dev, uint64_t *base);
1479
1480 int
1481 tu_drm_submitqueue_new(const struct tu_device *dev,
1482                        int priority,
1483                        uint32_t *queue_id);
1484
1485 void
1486 tu_drm_submitqueue_close(const struct tu_device *dev, uint32_t queue_id);
1487
1488 uint32_t
1489 tu_gem_new(const struct tu_device *dev, uint64_t size, uint32_t flags);
1490 uint32_t
1491 tu_gem_import_dmabuf(const struct tu_device *dev,
1492                      int prime_fd,
1493                      uint64_t size);
1494 int
1495 tu_gem_export_dmabuf(const struct tu_device *dev, uint32_t gem_handle);
1496 void
1497 tu_gem_close(const struct tu_device *dev, uint32_t gem_handle);
1498 uint64_t
1499 tu_gem_info_offset(const struct tu_device *dev, uint32_t gem_handle);
1500 uint64_t
1501 tu_gem_info_iova(const struct tu_device *dev, uint32_t gem_handle);
1502
1503 #define TU_DEFINE_HANDLE_CASTS(__tu_type, __VkType)                          \
1504                                                                              \
1505    static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1506    {                                                                         \
1507       return (struct __tu_type *) _handle;                                   \
1508    }                                                                         \
1509                                                                              \
1510    static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj)      \
1511    {                                                                         \
1512       return (__VkType) _obj;                                                \
1513    }
1514
1515 #define TU_DEFINE_NONDISP_HANDLE_CASTS(__tu_type, __VkType)                  \
1516                                                                              \
1517    static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
1518    {                                                                         \
1519       return (struct __tu_type *) (uintptr_t) _handle;                       \
1520    }                                                                         \
1521                                                                              \
1522    static inline __VkType __tu_type##_to_handle(struct __tu_type *_obj)      \
1523    {                                                                         \
1524       return (__VkType)(uintptr_t) _obj;                                     \
1525    }
1526
1527 #define TU_FROM_HANDLE(__tu_type, __name, __handle)                          \
1528    struct __tu_type *__name = __tu_type##_from_handle(__handle)
1529
1530 TU_DEFINE_HANDLE_CASTS(tu_cmd_buffer, VkCommandBuffer)
1531 TU_DEFINE_HANDLE_CASTS(tu_device, VkDevice)
1532 TU_DEFINE_HANDLE_CASTS(tu_instance, VkInstance)
1533 TU_DEFINE_HANDLE_CASTS(tu_physical_device, VkPhysicalDevice)
1534 TU_DEFINE_HANDLE_CASTS(tu_queue, VkQueue)
1535
1536 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_cmd_pool, VkCommandPool)
1537 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer, VkBuffer)
1538 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_buffer_view, VkBufferView)
1539 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_pool, VkDescriptorPool)
1540 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set, VkDescriptorSet)
1541 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_set_layout,
1542                                VkDescriptorSetLayout)
1543 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_descriptor_update_template,
1544                                VkDescriptorUpdateTemplate)
1545 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_device_memory, VkDeviceMemory)
1546 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_fence, VkFence)
1547 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_event, VkEvent)
1548 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_framebuffer, VkFramebuffer)
1549 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image, VkImage)
1550 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_image_view, VkImageView);
1551 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_cache, VkPipelineCache)
1552 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline, VkPipeline)
1553 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_layout, VkPipelineLayout)
1554 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_query_pool, VkQueryPool)
1555 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_render_pass, VkRenderPass)
1556 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_sampler, VkSampler)
1557 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_sampler_ycbcr_conversion, VkSamplerYcbcrConversion)
1558 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_shader_module, VkShaderModule)
1559 TU_DEFINE_NONDISP_HANDLE_CASTS(tu_semaphore, VkSemaphore)
1560
1561 #endif /* TU_PRIVATE_H */