2 * Copyright © 2019 Google LLC
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include "tu_private.h"
26 #include "spirv/nir_spirv.h"
27 #include "util/mesa-sha1.h"
28 #include "nir/nir_xfb_info.h"
29 #include "nir/nir_vulkan.h"
32 #include "ir3/ir3_nir.h"
35 tu_spirv_to_nir(struct ir3_compiler
*compiler
,
36 const uint32_t *words
,
38 gl_shader_stage stage
,
39 const char *entry_point_name
,
40 const VkSpecializationInfo
*spec_info
)
42 /* TODO these are made-up */
43 const struct spirv_to_nir_options spirv_options
= {
44 .frag_coord_is_sysval
= true,
45 .lower_ubo_ssbo_access_to_offsets
= true,
47 .transform_feedback
= compiler
->gpu_id
>= 600,
50 const nir_shader_compiler_options
*nir_options
=
51 ir3_get_compiler_options(compiler
);
53 /* convert VkSpecializationInfo */
54 struct nir_spirv_specialization
*spec
= NULL
;
55 uint32_t num_spec
= 0;
56 if (spec_info
&& spec_info
->mapEntryCount
) {
57 spec
= calloc(spec_info
->mapEntryCount
, sizeof(*spec
));
61 for (uint32_t i
= 0; i
< spec_info
->mapEntryCount
; i
++) {
62 const VkSpecializationMapEntry
*entry
= &spec_info
->pMapEntries
[i
];
63 const void *data
= spec_info
->pData
+ entry
->offset
;
64 assert(data
+ entry
->size
<= spec_info
->pData
+ spec_info
->dataSize
);
65 spec
[i
].id
= entry
->constantID
;
66 switch (entry
->size
) {
68 spec
[i
].value
.u64
= *(const uint64_t *)data
;
71 spec
[i
].value
.u32
= *(const uint32_t *)data
;
74 spec
[i
].value
.u16
= *(const uint16_t *)data
;
77 spec
[i
].value
.u8
= *(const uint8_t *)data
;
80 assert(!"Invalid spec constant size");
83 spec
[i
].defined_on_module
= false;
86 num_spec
= spec_info
->mapEntryCount
;
90 spirv_to_nir(words
, word_count
, spec
, num_spec
, stage
, entry_point_name
,
91 &spirv_options
, nir_options
);
95 assert(nir
->info
.stage
== stage
);
96 nir_validate_shader(nir
, "after spirv_to_nir");
102 lower_load_push_constant(nir_builder
*b
, nir_intrinsic_instr
*instr
,
103 struct tu_shader
*shader
)
105 nir_intrinsic_instr
*load
=
106 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_load_uniform
);
107 load
->num_components
= instr
->num_components
;
108 uint32_t base
= nir_intrinsic_base(instr
);
109 assert(base
% 4 == 0);
110 assert(base
>= shader
->push_consts
.lo
* 16);
111 base
-= shader
->push_consts
.lo
* 16;
112 nir_intrinsic_set_base(load
, base
/ 4);
114 nir_src_for_ssa(nir_ushr(b
, instr
->src
[0].ssa
, nir_imm_int(b
, 2)));
115 nir_ssa_dest_init(&load
->instr
, &load
->dest
,
116 load
->num_components
, instr
->dest
.ssa
.bit_size
,
117 instr
->dest
.ssa
.name
);
118 nir_builder_instr_insert(b
, &load
->instr
);
119 nir_ssa_def_rewrite_uses(&instr
->dest
.ssa
, nir_src_for_ssa(&load
->dest
.ssa
));
121 nir_instr_remove(&instr
->instr
);
125 lower_vulkan_resource_index(nir_builder
*b
, nir_intrinsic_instr
*instr
,
126 struct tu_shader
*shader
,
127 const struct tu_pipeline_layout
*layout
)
129 nir_ssa_def
*vulkan_idx
= instr
->src
[0].ssa
;
131 unsigned set
= nir_intrinsic_desc_set(instr
);
132 unsigned binding
= nir_intrinsic_binding(instr
);
133 struct tu_descriptor_set_layout
*set_layout
= layout
->set
[set
].layout
;
134 struct tu_descriptor_set_binding_layout
*binding_layout
=
135 &set_layout
->binding
[binding
];
138 switch (binding_layout
->type
) {
139 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
140 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
141 base
= layout
->set
[set
].dynamic_offset_start
+
142 binding_layout
->dynamic_offset_offset
+
143 layout
->input_attachment_count
;
147 base
= binding_layout
->offset
/ (4 * A6XX_TEX_CONST_DWORDS
);
151 nir_intrinsic_instr
*bindless
=
152 nir_intrinsic_instr_create(b
->shader
,
153 nir_intrinsic_bindless_resource_ir3
);
154 bindless
->num_components
= 1;
155 nir_ssa_dest_init(&bindless
->instr
, &bindless
->dest
,
157 nir_intrinsic_set_desc_set(bindless
, set
);
158 bindless
->src
[0] = nir_src_for_ssa(nir_iadd(b
, nir_imm_int(b
, base
), vulkan_idx
));
159 nir_builder_instr_insert(b
, &bindless
->instr
);
161 nir_ssa_def_rewrite_uses(&instr
->dest
.ssa
,
162 nir_src_for_ssa(&bindless
->dest
.ssa
));
163 nir_instr_remove(&instr
->instr
);
167 build_bindless(nir_builder
*b
, nir_deref_instr
*deref
, bool is_sampler
,
168 struct tu_shader
*shader
,
169 const struct tu_pipeline_layout
*layout
)
171 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
173 unsigned set
= var
->data
.descriptor_set
;
174 unsigned binding
= var
->data
.binding
;
175 const struct tu_descriptor_set_binding_layout
*bind_layout
=
176 &layout
->set
[set
].layout
->binding
[binding
];
178 nir_ssa_def
*desc_offset
;
179 unsigned descriptor_stride
;
180 if (bind_layout
->type
== VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
) {
182 layout
->set
[set
].input_attachment_start
+
183 bind_layout
->input_attachment_offset
;
184 desc_offset
= nir_imm_int(b
, offset
);
186 descriptor_stride
= 1;
189 /* Samplers come second in combined image/sampler descriptors, see
190 * write_combined_image_sampler_descriptor().
192 if (is_sampler
&& bind_layout
->type
==
193 VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
) {
197 nir_imm_int(b
, (bind_layout
->offset
/ (4 * A6XX_TEX_CONST_DWORDS
)) +
199 descriptor_stride
= bind_layout
->size
/ (4 * A6XX_TEX_CONST_DWORDS
);
202 if (deref
->deref_type
!= nir_deref_type_var
) {
203 assert(deref
->deref_type
== nir_deref_type_array
);
205 nir_ssa_def
*arr_index
= nir_ssa_for_src(b
, deref
->arr
.index
, 1);
206 desc_offset
= nir_iadd(b
, desc_offset
,
207 nir_imul_imm(b
, arr_index
, descriptor_stride
));
210 nir_intrinsic_instr
*bindless
=
211 nir_intrinsic_instr_create(b
->shader
,
212 nir_intrinsic_bindless_resource_ir3
);
213 bindless
->num_components
= 1;
214 nir_ssa_dest_init(&bindless
->instr
, &bindless
->dest
,
216 nir_intrinsic_set_desc_set(bindless
, set
);
217 bindless
->src
[0] = nir_src_for_ssa(desc_offset
);
218 nir_builder_instr_insert(b
, &bindless
->instr
);
220 return &bindless
->dest
.ssa
;
224 lower_image_deref(nir_builder
*b
,
225 nir_intrinsic_instr
*instr
, struct tu_shader
*shader
,
226 const struct tu_pipeline_layout
*layout
)
228 nir_deref_instr
*deref
= nir_src_as_deref(instr
->src
[0]);
229 nir_ssa_def
*bindless
= build_bindless(b
, deref
, false, shader
, layout
);
230 nir_rewrite_image_intrinsic(instr
, bindless
, true);
234 lower_intrinsic(nir_builder
*b
, nir_intrinsic_instr
*instr
,
235 struct tu_shader
*shader
,
236 const struct tu_pipeline_layout
*layout
)
238 switch (instr
->intrinsic
) {
239 case nir_intrinsic_load_layer_id
:
240 /* TODO: remove this when layered rendering is implemented */
241 nir_ssa_def_rewrite_uses(&instr
->dest
.ssa
,
242 nir_src_for_ssa(nir_imm_int(b
, 0)));
243 nir_instr_remove(&instr
->instr
);
246 case nir_intrinsic_load_push_constant
:
247 lower_load_push_constant(b
, instr
, shader
);
250 case nir_intrinsic_vulkan_resource_index
:
251 lower_vulkan_resource_index(b
, instr
, shader
, layout
);
254 case nir_intrinsic_image_deref_load
:
255 case nir_intrinsic_image_deref_store
:
256 case nir_intrinsic_image_deref_atomic_add
:
257 case nir_intrinsic_image_deref_atomic_imin
:
258 case nir_intrinsic_image_deref_atomic_umin
:
259 case nir_intrinsic_image_deref_atomic_imax
:
260 case nir_intrinsic_image_deref_atomic_umax
:
261 case nir_intrinsic_image_deref_atomic_and
:
262 case nir_intrinsic_image_deref_atomic_or
:
263 case nir_intrinsic_image_deref_atomic_xor
:
264 case nir_intrinsic_image_deref_atomic_exchange
:
265 case nir_intrinsic_image_deref_atomic_comp_swap
:
266 case nir_intrinsic_image_deref_size
:
267 case nir_intrinsic_image_deref_samples
:
268 lower_image_deref(b
, instr
, shader
, layout
);
277 lower_tex_ycbcr(const struct tu_pipeline_layout
*layout
,
278 nir_builder
*builder
,
281 int deref_src_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_texture_deref
);
282 assert(deref_src_idx
>= 0);
283 nir_deref_instr
*deref
= nir_src_as_deref(tex
->src
[deref_src_idx
].src
);
285 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
286 const struct tu_descriptor_set_layout
*set_layout
=
287 layout
->set
[var
->data
.descriptor_set
].layout
;
288 const struct tu_descriptor_set_binding_layout
*binding
=
289 &set_layout
->binding
[var
->data
.binding
];
290 const struct tu_sampler_ycbcr_conversion
*ycbcr_samplers
=
291 tu_immutable_ycbcr_samplers(set_layout
, binding
);
296 /* For the following instructions, we don't apply any change */
297 if (tex
->op
== nir_texop_txs
||
298 tex
->op
== nir_texop_query_levels
||
299 tex
->op
== nir_texop_lod
)
302 assert(tex
->texture_index
== 0);
303 unsigned array_index
= 0;
304 if (deref
->deref_type
!= nir_deref_type_var
) {
305 assert(deref
->deref_type
== nir_deref_type_array
);
306 if (!nir_src_is_const(deref
->arr
.index
))
308 array_index
= nir_src_as_uint(deref
->arr
.index
);
309 array_index
= MIN2(array_index
, binding
->array_size
- 1);
311 const struct tu_sampler_ycbcr_conversion
*ycbcr_sampler
= ycbcr_samplers
+ array_index
;
313 if (ycbcr_sampler
->ycbcr_model
== VK_SAMPLER_YCBCR_MODEL_CONVERSION_RGB_IDENTITY
)
316 builder
->cursor
= nir_after_instr(&tex
->instr
);
318 uint8_t bits
= vk_format_get_component_bits(ycbcr_sampler
->format
,
319 UTIL_FORMAT_COLORSPACE_RGB
,
321 uint32_t bpcs
[3] = {bits
, bits
, bits
}; /* TODO: use right bpc for each channel ? */
322 nir_ssa_def
*result
= nir_convert_ycbcr_to_rgb(builder
,
323 ycbcr_sampler
->ycbcr_model
,
324 ycbcr_sampler
->ycbcr_range
,
327 nir_ssa_def_rewrite_uses_after(&tex
->dest
.ssa
, nir_src_for_ssa(result
),
328 result
->parent_instr
);
330 builder
->cursor
= nir_before_instr(&tex
->instr
);
334 lower_tex(nir_builder
*b
, nir_tex_instr
*tex
,
335 struct tu_shader
*shader
, const struct tu_pipeline_layout
*layout
)
337 lower_tex_ycbcr(layout
, b
, tex
);
339 int sampler_src_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_sampler_deref
);
340 if (sampler_src_idx
>= 0) {
341 nir_deref_instr
*deref
= nir_src_as_deref(tex
->src
[sampler_src_idx
].src
);
342 nir_ssa_def
*bindless
= build_bindless(b
, deref
, true, shader
, layout
);
343 nir_instr_rewrite_src(&tex
->instr
, &tex
->src
[sampler_src_idx
].src
,
344 nir_src_for_ssa(bindless
));
345 tex
->src
[sampler_src_idx
].src_type
= nir_tex_src_sampler_handle
;
348 int tex_src_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_texture_deref
);
349 if (tex_src_idx
>= 0) {
350 nir_deref_instr
*deref
= nir_src_as_deref(tex
->src
[tex_src_idx
].src
);
351 nir_ssa_def
*bindless
= build_bindless(b
, deref
, false, shader
, layout
);
352 nir_instr_rewrite_src(&tex
->instr
, &tex
->src
[tex_src_idx
].src
,
353 nir_src_for_ssa(bindless
));
354 tex
->src
[tex_src_idx
].src_type
= nir_tex_src_texture_handle
;
361 lower_impl(nir_function_impl
*impl
, struct tu_shader
*shader
,
362 const struct tu_pipeline_layout
*layout
)
365 nir_builder_init(&b
, impl
);
366 bool progress
= false;
368 nir_foreach_block(block
, impl
) {
369 nir_foreach_instr_safe(instr
, block
) {
370 b
.cursor
= nir_before_instr(instr
);
371 switch (instr
->type
) {
372 case nir_instr_type_tex
:
373 progress
|= lower_tex(&b
, nir_instr_as_tex(instr
), shader
, layout
);
375 case nir_instr_type_intrinsic
:
376 progress
|= lower_intrinsic(&b
, nir_instr_as_intrinsic(instr
), shader
, layout
);
388 /* Figure out the range of push constants that we're actually going to push to
389 * the shader, and tell the backend to reserve this range when pushing UBO
394 gather_push_constants(nir_shader
*shader
, struct tu_shader
*tu_shader
)
396 uint32_t min
= UINT32_MAX
, max
= 0;
397 nir_foreach_function(function
, shader
) {
401 nir_foreach_block(block
, function
->impl
) {
402 nir_foreach_instr_safe(instr
, block
) {
403 if (instr
->type
!= nir_instr_type_intrinsic
)
406 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
407 if (intrin
->intrinsic
!= nir_intrinsic_load_push_constant
)
410 uint32_t base
= nir_intrinsic_base(intrin
);
411 uint32_t range
= nir_intrinsic_range(intrin
);
412 min
= MIN2(min
, base
);
413 max
= MAX2(max
, base
+ range
);
420 tu_shader
->push_consts
.lo
= 0;
421 tu_shader
->push_consts
.count
= 0;
422 tu_shader
->ir3_shader
.const_state
.num_reserved_user_consts
= 0;
426 /* CP_LOAD_STATE OFFSET and NUM_UNIT are in units of vec4 (4 dwords),
427 * however there's an alignment requirement of 4 on OFFSET. Expand the
428 * range and change units accordingly.
430 tu_shader
->push_consts
.lo
= (min
/ 16) / 4 * 4;
431 tu_shader
->push_consts
.count
=
432 align(max
, 16) / 16 - tu_shader
->push_consts
.lo
;
433 tu_shader
->ir3_shader
.const_state
.num_reserved_user_consts
=
434 align(tu_shader
->push_consts
.count
, 4);
437 /* Gather the InputAttachmentIndex for each input attachment from the NIR
438 * shader and organize the info in a way so that draw-time patching is easy.
441 gather_input_attachments(nir_shader
*shader
, struct tu_shader
*tu_shader
,
442 const struct tu_pipeline_layout
*layout
)
444 nir_foreach_variable(var
, &shader
->uniforms
) {
445 const struct glsl_type
*glsl_type
= glsl_without_array(var
->type
);
447 if (!glsl_type_is_image(glsl_type
))
450 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(glsl_type
);
452 const uint32_t set
= var
->data
.descriptor_set
;
453 const uint32_t binding
= var
->data
.binding
;
454 const struct tu_descriptor_set_binding_layout
*bind_layout
=
455 &layout
->set
[set
].layout
->binding
[binding
];
456 const uint32_t array_size
= bind_layout
->array_size
;
458 if (dim
== GLSL_SAMPLER_DIM_SUBPASS
||
459 dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) {
461 layout
->set
[set
].input_attachment_start
+
462 bind_layout
->input_attachment_offset
;
463 for (unsigned i
= 0; i
< array_size
; i
++)
464 tu_shader
->attachment_idx
[offset
+ i
] = var
->data
.index
+ i
;
470 tu_lower_io(nir_shader
*shader
, struct tu_shader
*tu_shader
,
471 const struct tu_pipeline_layout
*layout
)
473 bool progress
= false;
475 gather_push_constants(shader
, tu_shader
);
476 gather_input_attachments(shader
, tu_shader
, layout
);
478 nir_foreach_function(function
, shader
) {
480 progress
|= lower_impl(function
->impl
, tu_shader
, layout
);
487 tu_gather_xfb_info(nir_shader
*nir
, struct tu_shader
*shader
)
489 struct ir3_stream_output_info
*info
= &shader
->ir3_shader
.stream_output
;
490 nir_xfb_info
*xfb
= nir_gather_xfb_info(nir
, NULL
);
495 /* creating a map from VARYING_SLOT_* enums to consecutive index */
496 uint8_t num_outputs
= 0;
497 uint64_t outputs_written
= 0;
498 for (int i
= 0; i
< xfb
->output_count
; i
++)
499 outputs_written
|= BITFIELD64_BIT(xfb
->outputs
[i
].location
);
501 uint8_t output_map
[VARYING_SLOT_TESS_MAX
];
502 memset(output_map
, 0, sizeof(output_map
));
504 for (unsigned attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
505 if (outputs_written
& BITFIELD64_BIT(attr
))
506 output_map
[attr
] = num_outputs
++;
509 assert(xfb
->output_count
< IR3_MAX_SO_OUTPUTS
);
510 info
->num_outputs
= xfb
->output_count
;
512 for (int i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++)
513 info
->stride
[i
] = xfb
->buffers
[i
].stride
/ 4;
515 for (int i
= 0; i
< xfb
->output_count
; i
++) {
516 info
->output
[i
].register_index
= output_map
[xfb
->outputs
[i
].location
];
517 info
->output
[i
].start_component
= xfb
->outputs
[i
].component_offset
;
518 info
->output
[i
].num_components
=
519 util_bitcount(xfb
->outputs
[i
].component_mask
);
520 info
->output
[i
].output_buffer
= xfb
->outputs
[i
].buffer
;
521 info
->output
[i
].dst_offset
= xfb
->outputs
[i
].offset
/ 4;
522 info
->output
[i
].stream
= xfb
->buffer_to_stream
[xfb
->outputs
[i
].buffer
];
529 tu_shader_create(struct tu_device
*dev
,
530 gl_shader_stage stage
,
531 const VkPipelineShaderStageCreateInfo
*stage_info
,
532 struct tu_pipeline_layout
*layout
,
533 const VkAllocationCallbacks
*alloc
)
535 struct tu_shader
*shader
;
537 const uint32_t max_variant_count
= (stage
== MESA_SHADER_VERTEX
) ? 2 : 1;
540 sizeof(*shader
) + sizeof(struct ir3_shader_variant
) * max_variant_count
,
541 8, VK_SYSTEM_ALLOCATION_SCOPE_COMMAND
);
547 /* translate SPIR-V to NIR */
548 const struct tu_shader_module
*module
=
549 tu_shader_module_from_handle(stage_info
->module
);
550 assert(module
->code_size
% 4 == 0);
551 nir
= tu_spirv_to_nir(
552 dev
->compiler
, (const uint32_t *) module
->code
, module
->code_size
/ 4,
553 stage
, stage_info
->pName
, stage_info
->pSpecializationInfo
);
555 assert(stage
== MESA_SHADER_FRAGMENT
);
557 const nir_shader_compiler_options
*nir_options
=
558 ir3_get_compiler_options(dev
->compiler
);
559 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, nir_options
);
560 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "noop_fs");
565 vk_free2(&dev
->alloc
, alloc
, shader
);
569 if (unlikely(dev
->physical_device
->instance
->debug_flags
& TU_DEBUG_NIR
)) {
570 fprintf(stderr
, "translated nir:\n");
571 nir_print_shader(nir
, stderr
);
574 /* multi step inlining procedure */
575 NIR_PASS_V(nir
, nir_lower_variable_initializers
, nir_var_function_temp
);
576 NIR_PASS_V(nir
, nir_lower_returns
);
577 NIR_PASS_V(nir
, nir_inline_functions
);
578 NIR_PASS_V(nir
, nir_opt_deref
);
579 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
580 if (!func
->is_entrypoint
)
581 exec_node_remove(&func
->node
);
583 assert(exec_list_length(&nir
->functions
) == 1);
584 NIR_PASS_V(nir
, nir_lower_variable_initializers
, ~nir_var_function_temp
);
586 /* Split member structs. We do this before lower_io_to_temporaries so that
587 * it doesn't lower system values to temporaries by accident.
589 NIR_PASS_V(nir
, nir_split_var_copies
);
590 NIR_PASS_V(nir
, nir_split_per_member_structs
);
592 NIR_PASS_V(nir
, nir_remove_dead_variables
,
593 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
| nir_var_mem_shared
,
596 /* Gather information for transform feedback.
597 * This should be called after nir_split_per_member_structs.
598 * Also needs to be called after nir_remove_dead_variables with varyings,
599 * so that we could align stream outputs correctly.
601 if (nir
->info
.stage
== MESA_SHADER_VERTEX
||
602 nir
->info
.stage
== MESA_SHADER_TESS_EVAL
||
603 nir
->info
.stage
== MESA_SHADER_GEOMETRY
)
604 tu_gather_xfb_info(nir
, shader
);
606 NIR_PASS_V(nir
, nir_propagate_invariant
);
608 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
, nir_shader_get_entrypoint(nir
), true, true);
610 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
611 NIR_PASS_V(nir
, nir_split_var_copies
);
612 NIR_PASS_V(nir
, nir_lower_var_copies
);
614 NIR_PASS_V(nir
, nir_opt_copy_prop_vars
);
615 NIR_PASS_V(nir
, nir_opt_combine_stores
, nir_var_all
);
617 /* ir3 doesn't support indirect input/output */
618 NIR_PASS_V(nir
, nir_lower_indirect_derefs
, nir_var_shader_in
| nir_var_shader_out
);
620 NIR_PASS_V(nir
, nir_lower_io_arrays_to_elements_no_indirects
, false);
622 nir_assign_io_var_locations(&nir
->inputs
, &nir
->num_inputs
, stage
);
623 nir_assign_io_var_locations(&nir
->outputs
, &nir
->num_outputs
, stage
);
625 NIR_PASS_V(nir
, nir_lower_system_values
);
626 NIR_PASS_V(nir
, nir_lower_frexp
);
628 if (stage
== MESA_SHADER_FRAGMENT
)
629 NIR_PASS_V(nir
, nir_lower_input_attachments
, true);
631 if (stage
== MESA_SHADER_GEOMETRY
)
632 NIR_PASS_V(nir
, ir3_nir_lower_gs
);
634 NIR_PASS_V(nir
, tu_lower_io
, shader
, layout
);
636 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, ir3_glsl_type_size
, 0);
638 if (stage
== MESA_SHADER_FRAGMENT
) {
639 /* NOTE: lower load_barycentric_at_sample first, since it
640 * produces load_barycentric_at_offset:
642 NIR_PASS_V(nir
, ir3_nir_lower_load_barycentric_at_sample
);
643 NIR_PASS_V(nir
, ir3_nir_lower_load_barycentric_at_offset
);
645 NIR_PASS_V(nir
, ir3_nir_move_varying_inputs
);
648 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
650 /* num_uniforms only used by ir3 for size of ubo 0 (push constants) */
651 nir
->num_uniforms
= MAX_PUSH_CONSTANTS_SIZE
/ 16;
653 shader
->ir3_shader
.compiler
= dev
->compiler
;
654 shader
->ir3_shader
.type
= stage
;
655 shader
->ir3_shader
.nir
= nir
;
661 tu_shader_destroy(struct tu_device
*dev
,
662 struct tu_shader
*shader
,
663 const VkAllocationCallbacks
*alloc
)
665 if (shader
->ir3_shader
.nir
)
666 ralloc_free(shader
->ir3_shader
.nir
);
668 for (uint32_t i
= 0; i
< 1 + shader
->has_binning_pass
; i
++) {
669 if (shader
->variants
[i
].ir
)
670 ir3_destroy(shader
->variants
[i
].ir
);
673 if (shader
->ir3_shader
.const_state
.immediates
)
674 free(shader
->ir3_shader
.const_state
.immediates
);
676 free(shader
->binary
);
677 if (shader
->binning_binary
)
678 free(shader
->binning_binary
);
680 vk_free2(&dev
->alloc
, alloc
, shader
);
684 tu_shader_compile_options_init(
685 struct tu_shader_compile_options
*options
,
686 const VkGraphicsPipelineCreateInfo
*pipeline_info
)
691 for (uint32_t i
= 0; i
< pipeline_info
->stageCount
; i
++) {
692 if (pipeline_info
->pStages
[i
].stage
== VK_SHADER_STAGE_GEOMETRY_BIT
) {
698 const VkPipelineMultisampleStateCreateInfo
*msaa_info
= pipeline_info
->pMultisampleState
;
699 const struct VkPipelineSampleLocationsStateCreateInfoEXT
*sample_locations
=
700 vk_find_struct_const(msaa_info
->pNext
, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
);
701 if (!pipeline_info
->pRasterizationState
->rasterizerDiscardEnable
&&
702 (msaa_info
->rasterizationSamples
> 1 ||
703 /* also set msaa key when sample location is not the default
704 * since this affects varying interpolation */
705 (sample_locations
&& sample_locations
->sampleLocationsEnable
))) {
710 *options
= (struct tu_shader_compile_options
) {
711 /* TODO: Populate the remaining fields of ir3_shader_key. */
716 /* TODO: VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
717 * some optimizations need to happen otherwise shader might not compile
720 .include_binning_pass
= true,
725 tu_compile_shader_variant(struct ir3_shader
*shader
,
726 const struct ir3_shader_key
*key
,
727 struct ir3_shader_variant
*nonbinning
,
728 struct ir3_shader_variant
*variant
)
730 variant
->shader
= shader
;
731 variant
->type
= shader
->type
;
733 variant
->binning_pass
= !!nonbinning
;
734 variant
->nonbinning
= nonbinning
;
736 int ret
= ir3_compile_shader_nir(shader
->compiler
, variant
);
740 /* when assemble fails, we rely on tu_shader_destroy to clean up the
743 return ir3_shader_assemble(variant
, shader
->compiler
->gpu_id
);
747 tu_shader_compile(struct tu_device
*dev
,
748 struct tu_shader
*shader
,
749 const struct tu_shader
*next_stage
,
750 const struct tu_shader_compile_options
*options
,
751 const VkAllocationCallbacks
*alloc
)
753 if (options
->optimize
) {
754 /* ignore the key for the first pass of optimization */
755 ir3_optimize_nir(&shader
->ir3_shader
, shader
->ir3_shader
.nir
, NULL
);
757 if (unlikely(dev
->physical_device
->instance
->debug_flags
&
759 fprintf(stderr
, "optimized nir:\n");
760 nir_print_shader(shader
->ir3_shader
.nir
, stderr
);
764 shader
->binary
= tu_compile_shader_variant(
765 &shader
->ir3_shader
, &options
->key
, NULL
, &shader
->variants
[0]);
767 return VK_ERROR_OUT_OF_HOST_MEMORY
;
769 if (shader_debug_enabled(shader
->ir3_shader
.type
)) {
770 fprintf(stdout
, "Native code for unnamed %s shader %s:\n",
771 ir3_shader_stage(&shader
->variants
[0]), shader
->ir3_shader
.nir
->info
.name
);
772 if (shader
->ir3_shader
.type
== MESA_SHADER_FRAGMENT
)
773 fprintf(stdout
, "SIMD0\n");
774 ir3_shader_disasm(&shader
->variants
[0], shader
->binary
, stdout
);
777 /* compile another variant for the binning pass */
778 if (options
->include_binning_pass
&&
779 shader
->ir3_shader
.type
== MESA_SHADER_VERTEX
) {
780 shader
->binning_binary
= tu_compile_shader_variant(
781 &shader
->ir3_shader
, &options
->key
, &shader
->variants
[0],
782 &shader
->variants
[1]);
783 if (!shader
->binning_binary
)
784 return VK_ERROR_OUT_OF_HOST_MEMORY
;
786 shader
->has_binning_pass
= true;
788 if (shader_debug_enabled(MESA_SHADER_VERTEX
)) {
789 fprintf(stdout
, "Native code for unnamed binning shader %s:\n",
790 shader
->ir3_shader
.nir
->info
.name
);
791 ir3_shader_disasm(&shader
->variants
[1], shader
->binary
, stdout
);
795 if (unlikely(dev
->physical_device
->instance
->debug_flags
& TU_DEBUG_IR3
)) {
796 fprintf(stderr
, "disassembled ir3:\n");
797 fprintf(stderr
, "shader: %s\n",
798 gl_shader_stage_name(shader
->ir3_shader
.type
));
799 ir3_shader_disasm(&shader
->variants
[0], shader
->binary
, stderr
);
801 if (shader
->has_binning_pass
) {
802 fprintf(stderr
, "disassembled ir3:\n");
803 fprintf(stderr
, "shader: %s (binning)\n",
804 gl_shader_stage_name(shader
->ir3_shader
.type
));
805 ir3_shader_disasm(&shader
->variants
[1], shader
->binning_binary
,
814 tu_CreateShaderModule(VkDevice _device
,
815 const VkShaderModuleCreateInfo
*pCreateInfo
,
816 const VkAllocationCallbacks
*pAllocator
,
817 VkShaderModule
*pShaderModule
)
819 TU_FROM_HANDLE(tu_device
, device
, _device
);
820 struct tu_shader_module
*module
;
822 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
823 assert(pCreateInfo
->flags
== 0);
824 assert(pCreateInfo
->codeSize
% 4 == 0);
826 module
= vk_alloc2(&device
->alloc
, pAllocator
,
827 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
828 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
830 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
832 module
->code_size
= pCreateInfo
->codeSize
;
833 memcpy(module
->code
, pCreateInfo
->pCode
, pCreateInfo
->codeSize
);
835 _mesa_sha1_compute(module
->code
, module
->code_size
, module
->sha1
);
837 *pShaderModule
= tu_shader_module_to_handle(module
);
843 tu_DestroyShaderModule(VkDevice _device
,
844 VkShaderModule _module
,
845 const VkAllocationCallbacks
*pAllocator
)
847 TU_FROM_HANDLE(tu_device
, device
, _device
);
848 TU_FROM_HANDLE(tu_shader_module
, module
, _module
);
853 vk_free2(&device
->alloc
, pAllocator
, module
);