src/freedreno/vulkan/tu_shader.c

   1 /*
   2  * Copyright © 2019 Google LLC
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "tu_private.h"
  25
  26 #include "spirv/nir_spirv.h"
  27 #include "util/mesa-sha1.h"
  28 #include "nir/nir_xfb_info.h"
  29 #include "nir/nir_vulkan.h"
  30 #include "vk_util.h"
  31
  32 #include "ir3/ir3_nir.h"
  33
  34 static nir_shader *
  35 tu_spirv_to_nir(struct ir3_compiler *compiler,
  36                 const uint32_t *words,
  37                 size_t word_count,
  38                 gl_shader_stage stage,
  39                 const char *entry_point_name,
  40                 const VkSpecializationInfo *spec_info)
  41 {
  42    /* TODO these are made-up */
  43    const struct spirv_to_nir_options spirv_options = {
  44       .frag_coord_is_sysval = true,
  45       .lower_ubo_ssbo_access_to_offsets = false,
  46
  47       .ubo_addr_format = nir_address_format_vec2_index_32bit_offset,
  48       .ssbo_addr_format = nir_address_format_vec2_index_32bit_offset,
  49
  50       /* Accessed via stg/ldg */
  51       .phys_ssbo_addr_format = nir_address_format_64bit_global,
  52
  53       /* Accessed via the const register file */
  54       .push_const_addr_format = nir_address_format_logical,
  55
  56       /* Accessed via ldl/stl */
  57       .shared_addr_format = nir_address_format_32bit_offset,
  58
  59       /* Accessed via stg/ldg (not used with Vulkan?) */
  60       .global_addr_format = nir_address_format_64bit_global,
  61
  62       /* ViewID is a sysval in geometry stages and an input in the FS */
  63       .view_index_is_input = stage == MESA_SHADER_FRAGMENT,
  64       .caps = {
  65          .transform_feedback = true,
  66          .tessellation = true,
  67          .draw_parameters = true,
  68          .variable_pointers = true,
  69          .stencil_export = true,
  70          .multiview = true,
  71       },
  72    };
  73    const nir_shader_compiler_options *nir_options =
  74       ir3_get_compiler_options(compiler);
  75
  76    /* convert VkSpecializationInfo */
  77    struct nir_spirv_specialization *spec = NULL;
  78    uint32_t num_spec = 0;
  79    if (spec_info && spec_info->mapEntryCount) {
  80       spec = calloc(spec_info->mapEntryCount, sizeof(*spec));
  81       if (!spec)
  82          return NULL;
  83
  84       for (uint32_t i = 0; i < spec_info->mapEntryCount; i++) {
  85          const VkSpecializationMapEntry *entry = &spec_info->pMapEntries[i];
  86          const void *data = spec_info->pData + entry->offset;
  87          assert(data + entry->size <= spec_info->pData + spec_info->dataSize);
  88          spec[i].id = entry->constantID;
  89          switch (entry->size) {
  90          case 8:
  91             spec[i].value.u64 = *(const uint64_t *)data;
  92             break;
  93          case 4:
  94             spec[i].value.u32 = *(const uint32_t *)data;
  95             break;
  96          case 2:
  97             spec[i].value.u16 = *(const uint16_t *)data;
  98             break;
  99          case 1:
 100             spec[i].value.u8 = *(const uint8_t *)data;
 101             break;
 102          default:
 103             assert(!"Invalid spec constant size");
 104             break;
 105          }
 106          spec[i].defined_on_module = false;
 107       }
 108
 109       num_spec = spec_info->mapEntryCount;
 110    }
 111
 112    nir_shader *nir =
 113       spirv_to_nir(words, word_count, spec, num_spec, stage, entry_point_name,
 114                    &spirv_options, nir_options);
 115
 116    free(spec);
 117
 118    assert(nir->info.stage == stage);
 119    nir_validate_shader(nir, "after spirv_to_nir");
 120
 121    return nir;
 122 }
 123
 124 static void
 125 lower_load_push_constant(nir_builder *b, nir_intrinsic_instr *instr,
 126                          struct tu_shader *shader)
 127 {
 128    nir_intrinsic_instr *load =
 129       nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_uniform);
 130    load->num_components = instr->num_components;
 131    uint32_t base = nir_intrinsic_base(instr);
 132    assert(base % 4 == 0);
 133    assert(base >= shader->push_consts.lo * 16);
 134    base -= shader->push_consts.lo * 16;
 135    nir_intrinsic_set_base(load, base / 4);
 136    load->src[0] =
 137       nir_src_for_ssa(nir_ushr(b, instr->src[0].ssa, nir_imm_int(b, 2)));
 138    nir_ssa_dest_init(&load->instr, &load->dest,
 139                      load->num_components, instr->dest.ssa.bit_size,
 140                      instr->dest.ssa.name);
 141    nir_builder_instr_insert(b, &load->instr);
 142    nir_ssa_def_rewrite_uses(&instr->dest.ssa, nir_src_for_ssa(&load->dest.ssa));
 143
 144    nir_instr_remove(&instr->instr);
 145 }
 146
 147 static void
 148 lower_vulkan_resource_index(nir_builder *b, nir_intrinsic_instr *instr,
 149                             struct tu_shader *shader,
 150                             const struct tu_pipeline_layout *layout)
 151 {
 152    nir_ssa_def *vulkan_idx = instr->src[0].ssa;
 153
 154    unsigned set = nir_intrinsic_desc_set(instr);
 155    unsigned binding = nir_intrinsic_binding(instr);
 156    struct tu_descriptor_set_layout *set_layout = layout->set[set].layout;
 157    struct tu_descriptor_set_binding_layout *binding_layout =
 158       &set_layout->binding[binding];
 159    uint32_t base;
 160
 161    shader->active_desc_sets |= 1u << set;
 162
 163    switch (binding_layout->type) {
 164    case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
 165    case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
 166       base = layout->set[set].dynamic_offset_start +
 167          binding_layout->dynamic_offset_offset;
 168       set = MAX_SETS;
 169       break;
 170    default:
 171       base = binding_layout->offset / (4 * A6XX_TEX_CONST_DWORDS);
 172       break;
 173    }
 174
 175    nir_ssa_def *def = nir_vec3(b, nir_imm_int(b, set),
 176                                nir_iadd(b, nir_imm_int(b, base), vulkan_idx),
 177                                nir_imm_int(b, 0));
 178
 179    nir_ssa_def_rewrite_uses(&instr->dest.ssa, nir_src_for_ssa(def));
 180    nir_instr_remove(&instr->instr);
 181 }
 182
 183 static void
 184 lower_load_vulkan_descriptor(nir_intrinsic_instr *intrin)
 185 {
 186    /* Loading the descriptor happens as part of the load/store instruction so
 187     * this is a no-op.
 188     */
 189    nir_ssa_def_rewrite_uses(&intrin->dest.ssa, intrin->src[0]);
 190    nir_instr_remove(&intrin->instr);
 191 }
 192
 193 static void
 194 lower_ssbo_ubo_intrinsic(nir_builder *b, nir_intrinsic_instr *intrin)
 195 {
 196    const nir_intrinsic_info *info = &nir_intrinsic_infos[intrin->intrinsic];
 197
 198    /* The bindless base is part of the instruction, which means that part of
 199     * the "pointer" has to be constant. We solve this in the same way the blob
 200     * does, by generating a bunch of if-statements. In the usual case where
 201     * the descriptor set is constant this will get optimized out.
 202     */
 203
 204    unsigned buffer_src;
 205    if (intrin->intrinsic == nir_intrinsic_store_ssbo) {
 206       /* This has the value first */
 207       buffer_src = 1;
 208    } else {
 209       buffer_src = 0;
 210    }
 211
 212    nir_ssa_def *base_idx = nir_channel(b, intrin->src[buffer_src].ssa, 0);
 213    nir_ssa_def *descriptor_idx = nir_channel(b, intrin->src[buffer_src].ssa, 1);
 214
 215    nir_ssa_def *results[MAX_SETS + 1] = { NULL };
 216
 217    for (unsigned i = 0; i < MAX_SETS + 1; i++) {
 218       /* if (base_idx == i) { ... */
 219       nir_if *nif = nir_push_if(b, nir_ieq(b, base_idx, nir_imm_int(b, i)));
 220
 221       nir_intrinsic_instr *bindless =
 222          nir_intrinsic_instr_create(b->shader,
 223                                     nir_intrinsic_bindless_resource_ir3);
 224       bindless->num_components = 0;
 225       nir_ssa_dest_init(&bindless->instr, &bindless->dest,
 226                         1, 32, NULL);
 227       nir_intrinsic_set_desc_set(bindless, i);
 228       bindless->src[0] = nir_src_for_ssa(descriptor_idx);
 229       nir_builder_instr_insert(b, &bindless->instr);
 230
 231       nir_intrinsic_instr *copy =
 232          nir_intrinsic_instr_create(b->shader, intrin->intrinsic);
 233
 234       copy->num_components = intrin->num_components;
 235
 236       for (unsigned src = 0; src < info->num_srcs; src++) {
 237          if (src == buffer_src)
 238             copy->src[src] = nir_src_for_ssa(&bindless->dest.ssa);
 239          else
 240             copy->src[src] = nir_src_for_ssa(intrin->src[src].ssa);
 241       }
 242
 243       for (unsigned idx = 0; idx < info->num_indices; idx++) {
 244          copy->const_index[idx] = intrin->const_index[idx];
 245       }
 246
 247       if (info->has_dest) {
 248          nir_ssa_dest_init(&copy->instr, &copy->dest,
 249                            intrin->dest.ssa.num_components,
 250                            intrin->dest.ssa.bit_size,
 251                            intrin->dest.ssa.name);
 252          results[i] = &copy->dest.ssa;
 253       }
 254
 255       nir_builder_instr_insert(b, &copy->instr);
 256
 257       /* } else { ... */
 258       nir_push_else(b, nif);
 259    }
 260
 261    nir_ssa_def *result =
 262       nir_ssa_undef(b, intrin->dest.ssa.num_components, intrin->dest.ssa.bit_size);
 263    for (int i = MAX_SETS; i >= 0; i--) {
 264       nir_pop_if(b, NULL);
 265       if (info->has_dest)
 266          result = nir_if_phi(b, results[i], result);
 267    }
 268
 269    if (info->has_dest)
 270       nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(result));
 271    nir_instr_remove(&intrin->instr);
 272 }
 273
 274 static nir_ssa_def *
 275 build_bindless(nir_builder *b, nir_deref_instr *deref, bool is_sampler,
 276                struct tu_shader *shader,
 277                const struct tu_pipeline_layout *layout)
 278 {
 279    nir_variable *var = nir_deref_instr_get_variable(deref);
 280
 281    unsigned set = var->data.descriptor_set;
 282    unsigned binding = var->data.binding;
 283    const struct tu_descriptor_set_binding_layout *bind_layout =
 284       &layout->set[set].layout->binding[binding];
 285
 286    /* input attachments use non bindless workaround */
 287    if (bind_layout->type == VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT) {
 288       const struct glsl_type *glsl_type = glsl_without_array(var->type);
 289       uint32_t idx = var->data.index * 2;
 290
 291       b->shader->info.textures_used |=
 292          ((1ull << (bind_layout->array_size * 2)) - 1) << (idx * 2);
 293
 294       /* D24S8 workaround: stencil of D24S8 will be sampled as uint */
 295       if (glsl_get_sampler_result_type(glsl_type) == GLSL_TYPE_UINT)
 296          idx += 1;
 297
 298       if (deref->deref_type == nir_deref_type_var)
 299          return nir_imm_int(b, idx);
 300
 301       nir_ssa_def *arr_index = nir_ssa_for_src(b, deref->arr.index, 1);
 302       return nir_iadd(b, nir_imm_int(b, idx),
 303                       nir_imul_imm(b, arr_index, 2));
 304    }
 305
 306    shader->active_desc_sets |= 1u << set;
 307
 308    nir_ssa_def *desc_offset;
 309    unsigned descriptor_stride;
 310    unsigned offset = 0;
 311    /* Samplers come second in combined image/sampler descriptors, see
 312       * write_combined_image_sampler_descriptor().
 313       */
 314    if (is_sampler && bind_layout->type ==
 315          VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER) {
 316       offset = 1;
 317    }
 318    desc_offset =
 319       nir_imm_int(b, (bind_layout->offset / (4 * A6XX_TEX_CONST_DWORDS)) +
 320                   offset);
 321    descriptor_stride = bind_layout->size / (4 * A6XX_TEX_CONST_DWORDS);
 322
 323    if (deref->deref_type != nir_deref_type_var) {
 324       assert(deref->deref_type == nir_deref_type_array);
 325
 326       nir_ssa_def *arr_index = nir_ssa_for_src(b, deref->arr.index, 1);
 327       desc_offset = nir_iadd(b, desc_offset,
 328                              nir_imul_imm(b, arr_index, descriptor_stride));
 329    }
 330
 331    nir_intrinsic_instr *bindless =
 332       nir_intrinsic_instr_create(b->shader,
 333                                  nir_intrinsic_bindless_resource_ir3);
 334    bindless->num_components = 0;
 335    nir_ssa_dest_init(&bindless->instr, &bindless->dest,
 336                      1, 32, NULL);
 337    nir_intrinsic_set_desc_set(bindless, set);
 338    bindless->src[0] = nir_src_for_ssa(desc_offset);
 339    nir_builder_instr_insert(b, &bindless->instr);
 340
 341    return &bindless->dest.ssa;
 342 }
 343
 344 static void
 345 lower_image_deref(nir_builder *b,
 346                   nir_intrinsic_instr *instr, struct tu_shader *shader,
 347                   const struct tu_pipeline_layout *layout)
 348 {
 349    nir_deref_instr *deref = nir_src_as_deref(instr->src[0]);
 350    nir_ssa_def *bindless = build_bindless(b, deref, false, shader, layout);
 351    nir_rewrite_image_intrinsic(instr, bindless, true);
 352 }
 353
 354 static bool
 355 lower_intrinsic(nir_builder *b, nir_intrinsic_instr *instr,
 356                 struct tu_shader *shader,
 357                 const struct tu_pipeline_layout *layout)
 358 {
 359    switch (instr->intrinsic) {
 360    case nir_intrinsic_load_push_constant:
 361       lower_load_push_constant(b, instr, shader);
 362       return true;
 363
 364    case nir_intrinsic_load_vulkan_descriptor:
 365       lower_load_vulkan_descriptor(instr);
 366       return true;
 367
 368    case nir_intrinsic_vulkan_resource_index:
 369       lower_vulkan_resource_index(b, instr, shader, layout);
 370       return true;
 371
 372    case nir_intrinsic_load_ubo:
 373    case nir_intrinsic_load_ssbo:
 374    case nir_intrinsic_store_ssbo:
 375    case nir_intrinsic_ssbo_atomic_add:
 376    case nir_intrinsic_ssbo_atomic_imin:
 377    case nir_intrinsic_ssbo_atomic_umin:
 378    case nir_intrinsic_ssbo_atomic_imax:
 379    case nir_intrinsic_ssbo_atomic_umax:
 380    case nir_intrinsic_ssbo_atomic_and:
 381    case nir_intrinsic_ssbo_atomic_or:
 382    case nir_intrinsic_ssbo_atomic_xor:
 383    case nir_intrinsic_ssbo_atomic_exchange:
 384    case nir_intrinsic_ssbo_atomic_comp_swap:
 385    case nir_intrinsic_ssbo_atomic_fadd:
 386    case nir_intrinsic_ssbo_atomic_fmin:
 387    case nir_intrinsic_ssbo_atomic_fmax:
 388    case nir_intrinsic_ssbo_atomic_fcomp_swap:
 389    case nir_intrinsic_get_buffer_size:
 390       lower_ssbo_ubo_intrinsic(b, instr);
 391       return true;
 392
 393    case nir_intrinsic_image_deref_load:
 394    case nir_intrinsic_image_deref_store:
 395    case nir_intrinsic_image_deref_atomic_add:
 396    case nir_intrinsic_image_deref_atomic_imin:
 397    case nir_intrinsic_image_deref_atomic_umin:
 398    case nir_intrinsic_image_deref_atomic_imax:
 399    case nir_intrinsic_image_deref_atomic_umax:
 400    case nir_intrinsic_image_deref_atomic_and:
 401    case nir_intrinsic_image_deref_atomic_or:
 402    case nir_intrinsic_image_deref_atomic_xor:
 403    case nir_intrinsic_image_deref_atomic_exchange:
 404    case nir_intrinsic_image_deref_atomic_comp_swap:
 405    case nir_intrinsic_image_deref_size:
 406    case nir_intrinsic_image_deref_samples:
 407       lower_image_deref(b, instr, shader, layout);
 408       return true;
 409
 410    default:
 411       return false;
 412    }
 413 }
 414
 415 static void
 416 lower_tex_ycbcr(const struct tu_pipeline_layout *layout,
 417                 nir_builder *builder,
 418                 nir_tex_instr *tex)
 419 {
 420    int deref_src_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_deref);
 421    assert(deref_src_idx >= 0);
 422    nir_deref_instr *deref = nir_src_as_deref(tex->src[deref_src_idx].src);
 423
 424    nir_variable *var = nir_deref_instr_get_variable(deref);
 425    const struct tu_descriptor_set_layout *set_layout =
 426       layout->set[var->data.descriptor_set].layout;
 427    const struct tu_descriptor_set_binding_layout *binding =
 428       &set_layout->binding[var->data.binding];
 429    const struct tu_sampler_ycbcr_conversion *ycbcr_samplers =
 430       tu_immutable_ycbcr_samplers(set_layout, binding);
 431
 432    if (!ycbcr_samplers)
 433       return;
 434
 435    /* For the following instructions, we don't apply any change */
 436    if (tex->op == nir_texop_txs ||
 437        tex->op == nir_texop_query_levels ||
 438        tex->op == nir_texop_lod)
 439       return;
 440
 441    assert(tex->texture_index == 0);
 442    unsigned array_index = 0;
 443    if (deref->deref_type != nir_deref_type_var) {
 444       assert(deref->deref_type == nir_deref_type_array);
 445       if (!nir_src_is_const(deref->arr.index))
 446          return;
 447       array_index = nir_src_as_uint(deref->arr.index);
 448       array_index = MIN2(array_index, binding->array_size - 1);
 449    }
 450    const struct tu_sampler_ycbcr_conversion *ycbcr_sampler = ycbcr_samplers + array_index;
 451
 452    if (ycbcr_sampler->ycbcr_model == VK_SAMPLER_YCBCR_MODEL_CONVERSION_RGB_IDENTITY)
 453       return;
 454
 455    builder->cursor = nir_after_instr(&tex->instr);
 456
 457    uint8_t bits = vk_format_get_component_bits(ycbcr_sampler->format,
 458                                                UTIL_FORMAT_COLORSPACE_RGB,
 459                                                PIPE_SWIZZLE_X);
 460    uint32_t bpcs[3] = {bits, bits, bits}; /* TODO: use right bpc for each channel ? */
 461    nir_ssa_def *result = nir_convert_ycbcr_to_rgb(builder,
 462                                                   ycbcr_sampler->ycbcr_model,
 463                                                   ycbcr_sampler->ycbcr_range,
 464                                                   &tex->dest.ssa,
 465                                                   bpcs);
 466    nir_ssa_def_rewrite_uses_after(&tex->dest.ssa, nir_src_for_ssa(result),
 467                                   result->parent_instr);
 468
 469    builder->cursor = nir_before_instr(&tex->instr);
 470 }
 471
 472 static bool
 473 lower_tex(nir_builder *b, nir_tex_instr *tex,
 474           struct tu_shader *shader, const struct tu_pipeline_layout *layout)
 475 {
 476    lower_tex_ycbcr(layout, b, tex);
 477
 478    int sampler_src_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_deref);
 479    if (sampler_src_idx >= 0) {
 480       nir_deref_instr *deref = nir_src_as_deref(tex->src[sampler_src_idx].src);
 481       nir_ssa_def *bindless = build_bindless(b, deref, true, shader, layout);
 482       nir_instr_rewrite_src(&tex->instr, &tex->src[sampler_src_idx].src,
 483                             nir_src_for_ssa(bindless));
 484       tex->src[sampler_src_idx].src_type = nir_tex_src_sampler_handle;
 485    }
 486
 487    int tex_src_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_deref);
 488    if (tex_src_idx >= 0) {
 489       nir_deref_instr *deref = nir_src_as_deref(tex->src[tex_src_idx].src);
 490       nir_ssa_def *bindless = build_bindless(b, deref, false, shader, layout);
 491       nir_instr_rewrite_src(&tex->instr, &tex->src[tex_src_idx].src,
 492                             nir_src_for_ssa(bindless));
 493       tex->src[tex_src_idx].src_type = nir_tex_src_texture_handle;
 494
 495       /* for the input attachment case: */
 496       if (bindless->parent_instr->type != nir_instr_type_intrinsic)
 497          tex->src[tex_src_idx].src_type = nir_tex_src_texture_offset;
 498    }
 499
 500    return true;
 501 }
 502
 503 static bool
 504 lower_impl(nir_function_impl *impl, struct tu_shader *shader,
 505             const struct tu_pipeline_layout *layout)
 506 {
 507    nir_builder b;
 508    nir_builder_init(&b, impl);
 509    bool progress = false;
 510
 511    nir_foreach_block(block, impl) {
 512       nir_foreach_instr_safe(instr, block) {
 513          b.cursor = nir_before_instr(instr);
 514          switch (instr->type) {
 515          case nir_instr_type_tex:
 516             progress |= lower_tex(&b, nir_instr_as_tex(instr), shader, layout);
 517             break;
 518          case nir_instr_type_intrinsic:
 519             progress |= lower_intrinsic(&b, nir_instr_as_intrinsic(instr), shader, layout);
 520             break;
 521          default:
 522             break;
 523          }
 524       }
 525    }
 526
 527    if (progress)
 528       nir_metadata_preserve(impl, nir_metadata_none);
 529    else
 530       nir_metadata_preserve(impl, nir_metadata_all);
 531
 532    return progress;
 533 }
 534
 535
 536 /* Figure out the range of push constants that we're actually going to push to
 537  * the shader, and tell the backend to reserve this range when pushing UBO
 538  * constants.
 539  */
 540
 541 static void
 542 gather_push_constants(nir_shader *shader, struct tu_shader *tu_shader)
 543 {
 544    uint32_t min = UINT32_MAX, max = 0;
 545    nir_foreach_function(function, shader) {
 546       if (!function->impl)
 547          continue;
 548
 549       nir_foreach_block(block, function->impl) {
 550          nir_foreach_instr_safe(instr, block) {
 551             if (instr->type != nir_instr_type_intrinsic)
 552                continue;
 553
 554             nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
 555             if (intrin->intrinsic != nir_intrinsic_load_push_constant)
 556                continue;
 557
 558             uint32_t base = nir_intrinsic_base(intrin);
 559             uint32_t range = nir_intrinsic_range(intrin);
 560             min = MIN2(min, base);
 561             max = MAX2(max, base + range);
 562             break;
 563          }
 564       }
 565    }
 566
 567    if (min >= max) {
 568       tu_shader->push_consts.lo = 0;
 569       tu_shader->push_consts.count = 0;
 570       return;
 571    }
 572
 573    /* CP_LOAD_STATE OFFSET and NUM_UNIT are in units of vec4 (4 dwords),
 574     * however there's an alignment requirement of 4 on OFFSET. Expand the
 575     * range and change units accordingly.
 576     */
 577    tu_shader->push_consts.lo = (min / 16) / 4 * 4;
 578    tu_shader->push_consts.count =
 579       align(max, 16) / 16 - tu_shader->push_consts.lo;
 580 }
 581
 582 static bool
 583 tu_lower_io(nir_shader *shader, struct tu_shader *tu_shader,
 584             const struct tu_pipeline_layout *layout)
 585 {
 586    bool progress = false;
 587
 588    gather_push_constants(shader, tu_shader);
 589
 590    nir_foreach_function(function, shader) {
 591       if (function->impl)
 592          progress |= lower_impl(function->impl, tu_shader, layout);
 593    }
 594
 595    /* Remove now-unused variables so that when we gather the shader info later
 596     * they won't be counted.
 597     */
 598
 599    if (progress)
 600       nir_opt_dce(shader);
 601
 602    progress |=
 603       nir_remove_dead_variables(shader,
 604                                 nir_var_uniform | nir_var_mem_ubo | nir_var_mem_ssbo,
 605                                 NULL);
 606
 607    return progress;
 608 }
 609
 610 static void
 611 shared_type_info(const struct glsl_type *type, unsigned *size, unsigned *align)
 612 {
 613    assert(glsl_type_is_vector_or_scalar(type));
 614
 615    unsigned comp_size =
 616       glsl_type_is_boolean(type) ? 4 : glsl_get_bit_size(type) / 8;
 617    unsigned length = glsl_get_vector_elements(type);
 618    *size = comp_size * length;
 619    *align = 4;
 620 }
 621
 622 static void
 623 tu_gather_xfb_info(nir_shader *nir, struct ir3_stream_output_info *info)
 624 {
 625    nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
 626
 627    if (!xfb)
 628       return;
 629
 630    /* creating a map from VARYING_SLOT_* enums to consecutive index */
 631    uint8_t num_outputs = 0;
 632    uint64_t outputs_written = 0;
 633    for (int i = 0; i < xfb->output_count; i++)
 634       outputs_written |= BITFIELD64_BIT(xfb->outputs[i].location);
 635
 636    uint8_t output_map[VARYING_SLOT_TESS_MAX];
 637    memset(output_map, 0, sizeof(output_map));
 638
 639    for (unsigned attr = 0; attr < VARYING_SLOT_MAX; attr++) {
 640       if (outputs_written & BITFIELD64_BIT(attr))
 641          output_map[attr] = num_outputs++;
 642    }
 643
 644    assert(xfb->output_count < IR3_MAX_SO_OUTPUTS);
 645    info->num_outputs = xfb->output_count;
 646
 647    for (int i = 0; i < IR3_MAX_SO_BUFFERS; i++)
 648       info->stride[i] = xfb->buffers[i].stride / 4;
 649
 650    for (int i = 0; i < xfb->output_count; i++) {
 651       info->output[i].register_index = output_map[xfb->outputs[i].location];
 652       info->output[i].start_component = xfb->outputs[i].component_offset;
 653       info->output[i].num_components =
 654                            util_bitcount(xfb->outputs[i].component_mask);
 655       info->output[i].output_buffer  = xfb->outputs[i].buffer;
 656       info->output[i].dst_offset = xfb->outputs[i].offset / 4;
 657       info->output[i].stream = xfb->buffer_to_stream[xfb->outputs[i].buffer];
 658    }
 659
 660    ralloc_free(xfb);
 661 }
 662
 663 struct tu_shader *
 664 tu_shader_create(struct tu_device *dev,
 665                  gl_shader_stage stage,
 666                  const VkPipelineShaderStageCreateInfo *stage_info,
 667                  unsigned multiview_mask,
 668                  struct tu_pipeline_layout *layout,
 669                  const VkAllocationCallbacks *alloc)
 670 {
 671    struct tu_shader *shader;
 672
 673    shader = vk_zalloc2(
 674       &dev->vk.alloc, alloc,
 675       sizeof(*shader),
 676       8, VK_SYSTEM_ALLOCATION_SCOPE_COMMAND);
 677    if (!shader)
 678       return NULL;
 679
 680    nir_shader *nir;
 681    if (stage_info) {
 682       /* translate SPIR-V to NIR */
 683       const struct tu_shader_module *module =
 684          tu_shader_module_from_handle(stage_info->module);
 685       assert(module->code_size % 4 == 0);
 686       nir = tu_spirv_to_nir(
 687          dev->compiler, (const uint32_t *) module->code, module->code_size / 4,
 688          stage, stage_info->pName, stage_info->pSpecializationInfo);
 689    } else {
 690       assert(stage == MESA_SHADER_FRAGMENT);
 691       nir_builder fs_b;
 692       const nir_shader_compiler_options *nir_options =
 693          ir3_get_compiler_options(dev->compiler);
 694       nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, nir_options);
 695       fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
 696       nir = fs_b.shader;
 697    }
 698
 699    if (!nir) {
 700       vk_free2(&dev->vk.alloc, alloc, shader);
 701       return NULL;
 702    }
 703
 704    if (unlikely(dev->physical_device->instance->debug_flags & TU_DEBUG_NIR)) {
 705       fprintf(stderr, "translated nir:\n");
 706       nir_print_shader(nir, stderr);
 707    }
 708
 709    /* multi step inlining procedure */
 710    NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_function_temp);
 711    NIR_PASS_V(nir, nir_lower_returns);
 712    NIR_PASS_V(nir, nir_inline_functions);
 713    NIR_PASS_V(nir, nir_copy_prop);
 714    NIR_PASS_V(nir, nir_opt_deref);
 715    foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
 716       if (!func->is_entrypoint)
 717          exec_node_remove(&func->node);
 718    }
 719    assert(exec_list_length(&nir->functions) == 1);
 720    NIR_PASS_V(nir, nir_lower_variable_initializers, ~nir_var_function_temp);
 721
 722    /* Split member structs.  We do this before lower_io_to_temporaries so that
 723     * it doesn't lower system values to temporaries by accident.
 724     */
 725    NIR_PASS_V(nir, nir_split_var_copies);
 726    NIR_PASS_V(nir, nir_split_per_member_structs);
 727
 728    NIR_PASS_V(nir, nir_remove_dead_variables,
 729               nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared,
 730               NULL);
 731
 732    /* Gather information for transform feedback.
 733     * This should be called after nir_split_per_member_structs.
 734     * Also needs to be called after nir_remove_dead_variables with varyings,
 735     * so that we could align stream outputs correctly.
 736     */
 737    struct ir3_stream_output_info so_info = {};
 738    if (nir->info.stage == MESA_SHADER_VERTEX ||
 739          nir->info.stage == MESA_SHADER_TESS_EVAL ||
 740          nir->info.stage == MESA_SHADER_GEOMETRY)
 741       tu_gather_xfb_info(nir, &so_info);
 742
 743    NIR_PASS_V(nir, nir_propagate_invariant);
 744
 745    NIR_PASS_V(nir, nir_lower_io_to_temporaries, nir_shader_get_entrypoint(nir), true, true);
 746
 747    NIR_PASS_V(nir, nir_lower_global_vars_to_local);
 748    NIR_PASS_V(nir, nir_split_var_copies);
 749    NIR_PASS_V(nir, nir_lower_var_copies);
 750
 751    NIR_PASS_V(nir, nir_opt_copy_prop_vars);
 752    NIR_PASS_V(nir, nir_opt_combine_stores, nir_var_all);
 753
 754    /* ir3 doesn't support indirect input/output */
 755    /* TODO: We shouldn't perform this lowering pass on gl_TessLevelInner
 756     * and gl_TessLevelOuter. Since the tess levels are actually stored in
 757     * a global BO, they can be directly accessed via stg and ldg.
 758     * nir_lower_indirect_derefs will instead generate a big if-ladder which
 759     * isn't *incorrect* but is much less efficient. */
 760    NIR_PASS_V(nir, nir_lower_indirect_derefs, nir_var_shader_in | nir_var_shader_out);
 761
 762    NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects, false);
 763
 764    nir_assign_io_var_locations(nir, nir_var_shader_in, &nir->num_inputs, stage);
 765    nir_assign_io_var_locations(nir, nir_var_shader_out, &nir->num_outputs, stage);
 766
 767    NIR_PASS_V(nir, nir_lower_system_values);
 768    NIR_PASS_V(nir, nir_lower_compute_system_values);
 769
 770    NIR_PASS_V(nir, nir_lower_frexp);
 771
 772    if (stage == MESA_SHADER_FRAGMENT) {
 773       NIR_PASS_V(nir, nir_lower_input_attachments,
 774                  &(nir_input_attachment_options) {
 775                      .use_fragcoord_sysval = true,
 776                      .use_layer_id_sysval = false,
 777                      /* When using multiview rendering, we must use
 778                       * gl_ViewIndex as the layer id to pass to the texture
 779                       * sampling function. gl_Layer doesn't work when
 780                       * multiview is enabled.
 781                       */
 782                      .use_view_id_for_layer = multiview_mask != 0,
 783                  });
 784    }
 785
 786    if (stage == MESA_SHADER_VERTEX && multiview_mask) {
 787       NIR_PASS_V(nir, tu_nir_lower_multiview, multiview_mask, dev);
 788    }
 789
 790    NIR_PASS_V(nir, nir_lower_explicit_io,
 791               nir_var_mem_ubo | nir_var_mem_ssbo,
 792               nir_address_format_vec2_index_32bit_offset);
 793
 794    if (nir->info.stage == MESA_SHADER_COMPUTE) {
 795       NIR_PASS_V(nir, nir_lower_vars_to_explicit_types,
 796                  nir_var_mem_shared, shared_type_info);
 797       NIR_PASS_V(nir, nir_lower_explicit_io,
 798                  nir_var_mem_shared,
 799                  nir_address_format_32bit_offset);
 800    }
 801
 802    NIR_PASS_V(nir, tu_lower_io, shader, layout);
 803
 804    nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
 805
 806    ir3_finalize_nir(dev->compiler, nir);
 807
 808    shader->ir3_shader =
 809       ir3_shader_from_nir(dev->compiler, nir,
 810                           align(shader->push_consts.count, 4),
 811                           &so_info);
 812
 813    return shader;
 814 }
 815
 816 void
 817 tu_shader_destroy(struct tu_device *dev,
 818                   struct tu_shader *shader,
 819                   const VkAllocationCallbacks *alloc)
 820 {
 821    ir3_shader_destroy(shader->ir3_shader);
 822
 823    vk_free2(&dev->vk.alloc, alloc, shader);
 824 }
 825
 826 VkResult
 827 tu_CreateShaderModule(VkDevice _device,
 828                       const VkShaderModuleCreateInfo *pCreateInfo,
 829                       const VkAllocationCallbacks *pAllocator,
 830                       VkShaderModule *pShaderModule)
 831 {
 832    TU_FROM_HANDLE(tu_device, device, _device);
 833    struct tu_shader_module *module;
 834
 835    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
 836    assert(pCreateInfo->flags == 0);
 837    assert(pCreateInfo->codeSize % 4 == 0);
 838
 839    module = vk_object_alloc(&device->vk, pAllocator,
 840                             sizeof(*module) + pCreateInfo->codeSize,
 841                             VK_OBJECT_TYPE_SHADER_MODULE);
 842    if (module == NULL)
 843       return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
 844
 845    module->code_size = pCreateInfo->codeSize;
 846    memcpy(module->code, pCreateInfo->pCode, pCreateInfo->codeSize);
 847
 848    _mesa_sha1_compute(module->code, module->code_size, module->sha1);
 849
 850    *pShaderModule = tu_shader_module_to_handle(module);
 851
 852    return VK_SUCCESS;
 853 }
 854
 855 void
 856 tu_DestroyShaderModule(VkDevice _device,
 857                        VkShaderModule _module,
 858                        const VkAllocationCallbacks *pAllocator)
 859 {
 860    TU_FROM_HANDLE(tu_device, device, _device);
 861    TU_FROM_HANDLE(tu_shader_module, module, _module);
 862
 863    if (!module)
 864       return;
 865
 866    vk_object_free(&device->vk, pAllocator, module);
 867 }