b85febe641071841508df6e1b41abfb2d6e4fe1e
[mesa.git] / src / freedreno / vulkan / tu_shader.c
1 /*
2 * Copyright © 2019 Google LLC
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "tu_private.h"
25
26 #include "spirv/nir_spirv.h"
27 #include "util/mesa-sha1.h"
28 #include "nir/nir_xfb_info.h"
29 #include "nir/nir_vulkan.h"
30 #include "vk_util.h"
31
32 #include "ir3/ir3_nir.h"
33
34 static nir_shader *
35 tu_spirv_to_nir(struct ir3_compiler *compiler,
36 const uint32_t *words,
37 size_t word_count,
38 gl_shader_stage stage,
39 const char *entry_point_name,
40 const VkSpecializationInfo *spec_info)
41 {
42 /* TODO these are made-up */
43 const struct spirv_to_nir_options spirv_options = {
44 .frag_coord_is_sysval = true,
45 .lower_ubo_ssbo_access_to_offsets = false,
46
47 .ubo_addr_format = nir_address_format_vec2_index_32bit_offset,
48 .ssbo_addr_format = nir_address_format_vec2_index_32bit_offset,
49
50 /* Accessed via stg/ldg */
51 .phys_ssbo_addr_format = nir_address_format_64bit_global,
52
53 /* Accessed via the const register file */
54 .push_const_addr_format = nir_address_format_logical,
55
56 /* Accessed via ldl/stl */
57 .shared_addr_format = nir_address_format_32bit_offset,
58
59 /* Accessed via stg/ldg (not used with Vulkan?) */
60 .global_addr_format = nir_address_format_64bit_global,
61
62 /* ViewID is a sysval in geometry stages and an input in the FS */
63 .view_index_is_input = stage == MESA_SHADER_FRAGMENT,
64 .caps = {
65 .transform_feedback = true,
66 .tessellation = true,
67 .draw_parameters = true,
68 .variable_pointers = true,
69 .stencil_export = true,
70 },
71 };
72 const nir_shader_compiler_options *nir_options =
73 ir3_get_compiler_options(compiler);
74
75 /* convert VkSpecializationInfo */
76 struct nir_spirv_specialization *spec = NULL;
77 uint32_t num_spec = 0;
78 if (spec_info && spec_info->mapEntryCount) {
79 spec = calloc(spec_info->mapEntryCount, sizeof(*spec));
80 if (!spec)
81 return NULL;
82
83 for (uint32_t i = 0; i < spec_info->mapEntryCount; i++) {
84 const VkSpecializationMapEntry *entry = &spec_info->pMapEntries[i];
85 const void *data = spec_info->pData + entry->offset;
86 assert(data + entry->size <= spec_info->pData + spec_info->dataSize);
87 spec[i].id = entry->constantID;
88 switch (entry->size) {
89 case 8:
90 spec[i].value.u64 = *(const uint64_t *)data;
91 break;
92 case 4:
93 spec[i].value.u32 = *(const uint32_t *)data;
94 break;
95 case 2:
96 spec[i].value.u16 = *(const uint16_t *)data;
97 break;
98 case 1:
99 spec[i].value.u8 = *(const uint8_t *)data;
100 break;
101 default:
102 assert(!"Invalid spec constant size");
103 break;
104 }
105 spec[i].defined_on_module = false;
106 }
107
108 num_spec = spec_info->mapEntryCount;
109 }
110
111 nir_shader *nir =
112 spirv_to_nir(words, word_count, spec, num_spec, stage, entry_point_name,
113 &spirv_options, nir_options);
114
115 free(spec);
116
117 assert(nir->info.stage == stage);
118 nir_validate_shader(nir, "after spirv_to_nir");
119
120 return nir;
121 }
122
123 static void
124 lower_load_push_constant(nir_builder *b, nir_intrinsic_instr *instr,
125 struct tu_shader *shader)
126 {
127 nir_intrinsic_instr *load =
128 nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_uniform);
129 load->num_components = instr->num_components;
130 uint32_t base = nir_intrinsic_base(instr);
131 assert(base % 4 == 0);
132 assert(base >= shader->push_consts.lo * 16);
133 base -= shader->push_consts.lo * 16;
134 nir_intrinsic_set_base(load, base / 4);
135 load->src[0] =
136 nir_src_for_ssa(nir_ushr(b, instr->src[0].ssa, nir_imm_int(b, 2)));
137 nir_ssa_dest_init(&load->instr, &load->dest,
138 load->num_components, instr->dest.ssa.bit_size,
139 instr->dest.ssa.name);
140 nir_builder_instr_insert(b, &load->instr);
141 nir_ssa_def_rewrite_uses(&instr->dest.ssa, nir_src_for_ssa(&load->dest.ssa));
142
143 nir_instr_remove(&instr->instr);
144 }
145
146 static void
147 lower_vulkan_resource_index(nir_builder *b, nir_intrinsic_instr *instr,
148 struct tu_shader *shader,
149 const struct tu_pipeline_layout *layout)
150 {
151 nir_ssa_def *vulkan_idx = instr->src[0].ssa;
152
153 unsigned set = nir_intrinsic_desc_set(instr);
154 unsigned binding = nir_intrinsic_binding(instr);
155 struct tu_descriptor_set_layout *set_layout = layout->set[set].layout;
156 struct tu_descriptor_set_binding_layout *binding_layout =
157 &set_layout->binding[binding];
158 uint32_t base;
159
160 shader->active_desc_sets |= 1u << set;
161
162 switch (binding_layout->type) {
163 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
164 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
165 base = layout->set[set].dynamic_offset_start +
166 binding_layout->dynamic_offset_offset;
167 set = MAX_SETS;
168 break;
169 default:
170 base = binding_layout->offset / (4 * A6XX_TEX_CONST_DWORDS);
171 break;
172 }
173
174 nir_ssa_def *def = nir_vec3(b, nir_imm_int(b, set),
175 nir_iadd(b, nir_imm_int(b, base), vulkan_idx),
176 nir_imm_int(b, 0));
177
178 nir_ssa_def_rewrite_uses(&instr->dest.ssa, nir_src_for_ssa(def));
179 nir_instr_remove(&instr->instr);
180 }
181
182 static void
183 lower_load_vulkan_descriptor(nir_intrinsic_instr *intrin)
184 {
185 /* Loading the descriptor happens as part of the load/store instruction so
186 * this is a no-op.
187 */
188 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, intrin->src[0]);
189 nir_instr_remove(&intrin->instr);
190 }
191
192 static void
193 lower_ssbo_ubo_intrinsic(nir_builder *b, nir_intrinsic_instr *intrin)
194 {
195 const nir_intrinsic_info *info = &nir_intrinsic_infos[intrin->intrinsic];
196
197 /* The bindless base is part of the instruction, which means that part of
198 * the "pointer" has to be constant. We solve this in the same way the blob
199 * does, by generating a bunch of if-statements. In the usual case where
200 * the descriptor set is constant this will get optimized out.
201 */
202
203 unsigned buffer_src;
204 if (intrin->intrinsic == nir_intrinsic_store_ssbo) {
205 /* This has the value first */
206 buffer_src = 1;
207 } else {
208 buffer_src = 0;
209 }
210
211 nir_ssa_def *base_idx = nir_channel(b, intrin->src[buffer_src].ssa, 0);
212 nir_ssa_def *descriptor_idx = nir_channel(b, intrin->src[buffer_src].ssa, 1);
213
214 nir_ssa_def *results[MAX_SETS + 1] = { NULL };
215
216 for (unsigned i = 0; i < MAX_SETS + 1; i++) {
217 /* if (base_idx == i) { ... */
218 nir_if *nif = nir_push_if(b, nir_ieq(b, base_idx, nir_imm_int(b, i)));
219
220 nir_intrinsic_instr *bindless =
221 nir_intrinsic_instr_create(b->shader,
222 nir_intrinsic_bindless_resource_ir3);
223 bindless->num_components = 0;
224 nir_ssa_dest_init(&bindless->instr, &bindless->dest,
225 1, 32, NULL);
226 nir_intrinsic_set_desc_set(bindless, i);
227 bindless->src[0] = nir_src_for_ssa(descriptor_idx);
228 nir_builder_instr_insert(b, &bindless->instr);
229
230 nir_intrinsic_instr *copy =
231 nir_intrinsic_instr_create(b->shader, intrin->intrinsic);
232
233 copy->num_components = intrin->num_components;
234
235 for (unsigned src = 0; src < info->num_srcs; src++) {
236 if (src == buffer_src)
237 copy->src[src] = nir_src_for_ssa(&bindless->dest.ssa);
238 else
239 copy->src[src] = nir_src_for_ssa(intrin->src[src].ssa);
240 }
241
242 for (unsigned idx = 0; idx < info->num_indices; idx++) {
243 copy->const_index[idx] = intrin->const_index[idx];
244 }
245
246 if (info->has_dest) {
247 nir_ssa_dest_init(&copy->instr, &copy->dest,
248 intrin->dest.ssa.num_components,
249 intrin->dest.ssa.bit_size,
250 intrin->dest.ssa.name);
251 results[i] = &copy->dest.ssa;
252 }
253
254 nir_builder_instr_insert(b, &copy->instr);
255
256 /* } else { ... */
257 nir_push_else(b, nif);
258 }
259
260 nir_ssa_def *result =
261 nir_ssa_undef(b, intrin->dest.ssa.num_components, intrin->dest.ssa.bit_size);
262 for (int i = MAX_SETS; i >= 0; i--) {
263 nir_pop_if(b, NULL);
264 if (info->has_dest)
265 result = nir_if_phi(b, results[i], result);
266 }
267
268 if (info->has_dest)
269 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(result));
270 nir_instr_remove(&intrin->instr);
271 }
272
273 static nir_ssa_def *
274 build_bindless(nir_builder *b, nir_deref_instr *deref, bool is_sampler,
275 struct tu_shader *shader,
276 const struct tu_pipeline_layout *layout)
277 {
278 nir_variable *var = nir_deref_instr_get_variable(deref);
279
280 unsigned set = var->data.descriptor_set;
281 unsigned binding = var->data.binding;
282 const struct tu_descriptor_set_binding_layout *bind_layout =
283 &layout->set[set].layout->binding[binding];
284
285 /* input attachments use non bindless workaround */
286 if (bind_layout->type == VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT) {
287 const struct glsl_type *glsl_type = glsl_without_array(var->type);
288 uint32_t idx = var->data.index * 2;
289
290 b->shader->info.textures_used |=
291 ((1ull << (bind_layout->array_size * 2)) - 1) << (idx * 2);
292
293 /* D24S8 workaround: stencil of D24S8 will be sampled as uint */
294 if (glsl_get_sampler_result_type(glsl_type) == GLSL_TYPE_UINT)
295 idx += 1;
296
297 if (deref->deref_type == nir_deref_type_var)
298 return nir_imm_int(b, idx);
299
300 nir_ssa_def *arr_index = nir_ssa_for_src(b, deref->arr.index, 1);
301 return nir_iadd(b, nir_imm_int(b, idx),
302 nir_imul_imm(b, arr_index, 2));
303 }
304
305 shader->active_desc_sets |= 1u << set;
306
307 nir_ssa_def *desc_offset;
308 unsigned descriptor_stride;
309 unsigned offset = 0;
310 /* Samplers come second in combined image/sampler descriptors, see
311 * write_combined_image_sampler_descriptor().
312 */
313 if (is_sampler && bind_layout->type ==
314 VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER) {
315 offset = 1;
316 }
317 desc_offset =
318 nir_imm_int(b, (bind_layout->offset / (4 * A6XX_TEX_CONST_DWORDS)) +
319 offset);
320 descriptor_stride = bind_layout->size / (4 * A6XX_TEX_CONST_DWORDS);
321
322 if (deref->deref_type != nir_deref_type_var) {
323 assert(deref->deref_type == nir_deref_type_array);
324
325 nir_ssa_def *arr_index = nir_ssa_for_src(b, deref->arr.index, 1);
326 desc_offset = nir_iadd(b, desc_offset,
327 nir_imul_imm(b, arr_index, descriptor_stride));
328 }
329
330 nir_intrinsic_instr *bindless =
331 nir_intrinsic_instr_create(b->shader,
332 nir_intrinsic_bindless_resource_ir3);
333 bindless->num_components = 0;
334 nir_ssa_dest_init(&bindless->instr, &bindless->dest,
335 1, 32, NULL);
336 nir_intrinsic_set_desc_set(bindless, set);
337 bindless->src[0] = nir_src_for_ssa(desc_offset);
338 nir_builder_instr_insert(b, &bindless->instr);
339
340 return &bindless->dest.ssa;
341 }
342
343 static void
344 lower_image_deref(nir_builder *b,
345 nir_intrinsic_instr *instr, struct tu_shader *shader,
346 const struct tu_pipeline_layout *layout)
347 {
348 nir_deref_instr *deref = nir_src_as_deref(instr->src[0]);
349 nir_ssa_def *bindless = build_bindless(b, deref, false, shader, layout);
350 nir_rewrite_image_intrinsic(instr, bindless, true);
351 }
352
353 static bool
354 lower_intrinsic(nir_builder *b, nir_intrinsic_instr *instr,
355 struct tu_shader *shader,
356 const struct tu_pipeline_layout *layout)
357 {
358 switch (instr->intrinsic) {
359 case nir_intrinsic_load_push_constant:
360 lower_load_push_constant(b, instr, shader);
361 return true;
362
363 case nir_intrinsic_load_vulkan_descriptor:
364 lower_load_vulkan_descriptor(instr);
365 return true;
366
367 case nir_intrinsic_vulkan_resource_index:
368 lower_vulkan_resource_index(b, instr, shader, layout);
369 return true;
370
371 case nir_intrinsic_load_ubo:
372 case nir_intrinsic_load_ssbo:
373 case nir_intrinsic_store_ssbo:
374 case nir_intrinsic_ssbo_atomic_add:
375 case nir_intrinsic_ssbo_atomic_imin:
376 case nir_intrinsic_ssbo_atomic_umin:
377 case nir_intrinsic_ssbo_atomic_imax:
378 case nir_intrinsic_ssbo_atomic_umax:
379 case nir_intrinsic_ssbo_atomic_and:
380 case nir_intrinsic_ssbo_atomic_or:
381 case nir_intrinsic_ssbo_atomic_xor:
382 case nir_intrinsic_ssbo_atomic_exchange:
383 case nir_intrinsic_ssbo_atomic_comp_swap:
384 case nir_intrinsic_ssbo_atomic_fadd:
385 case nir_intrinsic_ssbo_atomic_fmin:
386 case nir_intrinsic_ssbo_atomic_fmax:
387 case nir_intrinsic_ssbo_atomic_fcomp_swap:
388 case nir_intrinsic_get_buffer_size:
389 lower_ssbo_ubo_intrinsic(b, instr);
390 return true;
391
392 case nir_intrinsic_image_deref_load:
393 case nir_intrinsic_image_deref_store:
394 case nir_intrinsic_image_deref_atomic_add:
395 case nir_intrinsic_image_deref_atomic_imin:
396 case nir_intrinsic_image_deref_atomic_umin:
397 case nir_intrinsic_image_deref_atomic_imax:
398 case nir_intrinsic_image_deref_atomic_umax:
399 case nir_intrinsic_image_deref_atomic_and:
400 case nir_intrinsic_image_deref_atomic_or:
401 case nir_intrinsic_image_deref_atomic_xor:
402 case nir_intrinsic_image_deref_atomic_exchange:
403 case nir_intrinsic_image_deref_atomic_comp_swap:
404 case nir_intrinsic_image_deref_size:
405 case nir_intrinsic_image_deref_samples:
406 lower_image_deref(b, instr, shader, layout);
407 return true;
408
409 default:
410 return false;
411 }
412 }
413
414 static void
415 lower_tex_ycbcr(const struct tu_pipeline_layout *layout,
416 nir_builder *builder,
417 nir_tex_instr *tex)
418 {
419 int deref_src_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_deref);
420 assert(deref_src_idx >= 0);
421 nir_deref_instr *deref = nir_src_as_deref(tex->src[deref_src_idx].src);
422
423 nir_variable *var = nir_deref_instr_get_variable(deref);
424 const struct tu_descriptor_set_layout *set_layout =
425 layout->set[var->data.descriptor_set].layout;
426 const struct tu_descriptor_set_binding_layout *binding =
427 &set_layout->binding[var->data.binding];
428 const struct tu_sampler_ycbcr_conversion *ycbcr_samplers =
429 tu_immutable_ycbcr_samplers(set_layout, binding);
430
431 if (!ycbcr_samplers)
432 return;
433
434 /* For the following instructions, we don't apply any change */
435 if (tex->op == nir_texop_txs ||
436 tex->op == nir_texop_query_levels ||
437 tex->op == nir_texop_lod)
438 return;
439
440 assert(tex->texture_index == 0);
441 unsigned array_index = 0;
442 if (deref->deref_type != nir_deref_type_var) {
443 assert(deref->deref_type == nir_deref_type_array);
444 if (!nir_src_is_const(deref->arr.index))
445 return;
446 array_index = nir_src_as_uint(deref->arr.index);
447 array_index = MIN2(array_index, binding->array_size - 1);
448 }
449 const struct tu_sampler_ycbcr_conversion *ycbcr_sampler = ycbcr_samplers + array_index;
450
451 if (ycbcr_sampler->ycbcr_model == VK_SAMPLER_YCBCR_MODEL_CONVERSION_RGB_IDENTITY)
452 return;
453
454 builder->cursor = nir_after_instr(&tex->instr);
455
456 uint8_t bits = vk_format_get_component_bits(ycbcr_sampler->format,
457 UTIL_FORMAT_COLORSPACE_RGB,
458 PIPE_SWIZZLE_X);
459 uint32_t bpcs[3] = {bits, bits, bits}; /* TODO: use right bpc for each channel ? */
460 nir_ssa_def *result = nir_convert_ycbcr_to_rgb(builder,
461 ycbcr_sampler->ycbcr_model,
462 ycbcr_sampler->ycbcr_range,
463 &tex->dest.ssa,
464 bpcs);
465 nir_ssa_def_rewrite_uses_after(&tex->dest.ssa, nir_src_for_ssa(result),
466 result->parent_instr);
467
468 builder->cursor = nir_before_instr(&tex->instr);
469 }
470
471 static bool
472 lower_tex(nir_builder *b, nir_tex_instr *tex,
473 struct tu_shader *shader, const struct tu_pipeline_layout *layout)
474 {
475 lower_tex_ycbcr(layout, b, tex);
476
477 int sampler_src_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_deref);
478 if (sampler_src_idx >= 0) {
479 nir_deref_instr *deref = nir_src_as_deref(tex->src[sampler_src_idx].src);
480 nir_ssa_def *bindless = build_bindless(b, deref, true, shader, layout);
481 nir_instr_rewrite_src(&tex->instr, &tex->src[sampler_src_idx].src,
482 nir_src_for_ssa(bindless));
483 tex->src[sampler_src_idx].src_type = nir_tex_src_sampler_handle;
484 }
485
486 int tex_src_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_deref);
487 if (tex_src_idx >= 0) {
488 nir_deref_instr *deref = nir_src_as_deref(tex->src[tex_src_idx].src);
489 nir_ssa_def *bindless = build_bindless(b, deref, false, shader, layout);
490 nir_instr_rewrite_src(&tex->instr, &tex->src[tex_src_idx].src,
491 nir_src_for_ssa(bindless));
492 tex->src[tex_src_idx].src_type = nir_tex_src_texture_handle;
493
494 /* for the input attachment case: */
495 if (bindless->parent_instr->type != nir_instr_type_intrinsic)
496 tex->src[tex_src_idx].src_type = nir_tex_src_texture_offset;
497 }
498
499 return true;
500 }
501
502 static bool
503 lower_impl(nir_function_impl *impl, struct tu_shader *shader,
504 const struct tu_pipeline_layout *layout)
505 {
506 nir_builder b;
507 nir_builder_init(&b, impl);
508 bool progress = false;
509
510 nir_foreach_block(block, impl) {
511 nir_foreach_instr_safe(instr, block) {
512 b.cursor = nir_before_instr(instr);
513 switch (instr->type) {
514 case nir_instr_type_tex:
515 progress |= lower_tex(&b, nir_instr_as_tex(instr), shader, layout);
516 break;
517 case nir_instr_type_intrinsic:
518 progress |= lower_intrinsic(&b, nir_instr_as_intrinsic(instr), shader, layout);
519 break;
520 default:
521 break;
522 }
523 }
524 }
525
526 if (progress)
527 nir_metadata_preserve(impl, nir_metadata_none);
528 else
529 nir_metadata_preserve(impl, nir_metadata_all);
530
531 return progress;
532 }
533
534
535 /* Figure out the range of push constants that we're actually going to push to
536 * the shader, and tell the backend to reserve this range when pushing UBO
537 * constants.
538 */
539
540 static void
541 gather_push_constants(nir_shader *shader, struct tu_shader *tu_shader)
542 {
543 uint32_t min = UINT32_MAX, max = 0;
544 nir_foreach_function(function, shader) {
545 if (!function->impl)
546 continue;
547
548 nir_foreach_block(block, function->impl) {
549 nir_foreach_instr_safe(instr, block) {
550 if (instr->type != nir_instr_type_intrinsic)
551 continue;
552
553 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
554 if (intrin->intrinsic != nir_intrinsic_load_push_constant)
555 continue;
556
557 uint32_t base = nir_intrinsic_base(intrin);
558 uint32_t range = nir_intrinsic_range(intrin);
559 min = MIN2(min, base);
560 max = MAX2(max, base + range);
561 break;
562 }
563 }
564 }
565
566 if (min >= max) {
567 tu_shader->push_consts.lo = 0;
568 tu_shader->push_consts.count = 0;
569 return;
570 }
571
572 /* CP_LOAD_STATE OFFSET and NUM_UNIT are in units of vec4 (4 dwords),
573 * however there's an alignment requirement of 4 on OFFSET. Expand the
574 * range and change units accordingly.
575 */
576 tu_shader->push_consts.lo = (min / 16) / 4 * 4;
577 tu_shader->push_consts.count =
578 align(max, 16) / 16 - tu_shader->push_consts.lo;
579 }
580
581 static bool
582 tu_lower_io(nir_shader *shader, struct tu_shader *tu_shader,
583 const struct tu_pipeline_layout *layout)
584 {
585 bool progress = false;
586
587 gather_push_constants(shader, tu_shader);
588
589 nir_foreach_function(function, shader) {
590 if (function->impl)
591 progress |= lower_impl(function->impl, tu_shader, layout);
592 }
593
594 /* Remove now-unused variables so that when we gather the shader info later
595 * they won't be counted.
596 */
597
598 if (progress)
599 nir_opt_dce(shader);
600
601 progress |=
602 nir_remove_dead_variables(shader,
603 nir_var_uniform | nir_var_mem_ubo | nir_var_mem_ssbo,
604 NULL);
605
606 return progress;
607 }
608
609 static void
610 shared_type_info(const struct glsl_type *type, unsigned *size, unsigned *align)
611 {
612 assert(glsl_type_is_vector_or_scalar(type));
613
614 unsigned comp_size =
615 glsl_type_is_boolean(type) ? 4 : glsl_get_bit_size(type) / 8;
616 unsigned length = glsl_get_vector_elements(type);
617 *size = comp_size * length;
618 *align = 4;
619 }
620
621 static void
622 tu_gather_xfb_info(nir_shader *nir, struct ir3_stream_output_info *info)
623 {
624 nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
625
626 if (!xfb)
627 return;
628
629 /* creating a map from VARYING_SLOT_* enums to consecutive index */
630 uint8_t num_outputs = 0;
631 uint64_t outputs_written = 0;
632 for (int i = 0; i < xfb->output_count; i++)
633 outputs_written |= BITFIELD64_BIT(xfb->outputs[i].location);
634
635 uint8_t output_map[VARYING_SLOT_TESS_MAX];
636 memset(output_map, 0, sizeof(output_map));
637
638 for (unsigned attr = 0; attr < VARYING_SLOT_MAX; attr++) {
639 if (outputs_written & BITFIELD64_BIT(attr))
640 output_map[attr] = num_outputs++;
641 }
642
643 assert(xfb->output_count < IR3_MAX_SO_OUTPUTS);
644 info->num_outputs = xfb->output_count;
645
646 for (int i = 0; i < IR3_MAX_SO_BUFFERS; i++)
647 info->stride[i] = xfb->buffers[i].stride / 4;
648
649 for (int i = 0; i < xfb->output_count; i++) {
650 info->output[i].register_index = output_map[xfb->outputs[i].location];
651 info->output[i].start_component = xfb->outputs[i].component_offset;
652 info->output[i].num_components =
653 util_bitcount(xfb->outputs[i].component_mask);
654 info->output[i].output_buffer = xfb->outputs[i].buffer;
655 info->output[i].dst_offset = xfb->outputs[i].offset / 4;
656 info->output[i].stream = xfb->buffer_to_stream[xfb->outputs[i].buffer];
657 }
658
659 ralloc_free(xfb);
660 }
661
662 struct tu_shader *
663 tu_shader_create(struct tu_device *dev,
664 gl_shader_stage stage,
665 const VkPipelineShaderStageCreateInfo *stage_info,
666 unsigned multiview_mask,
667 struct tu_pipeline_layout *layout,
668 const VkAllocationCallbacks *alloc)
669 {
670 struct tu_shader *shader;
671
672 shader = vk_zalloc2(
673 &dev->vk.alloc, alloc,
674 sizeof(*shader),
675 8, VK_SYSTEM_ALLOCATION_SCOPE_COMMAND);
676 if (!shader)
677 return NULL;
678
679 nir_shader *nir;
680 if (stage_info) {
681 /* translate SPIR-V to NIR */
682 const struct tu_shader_module *module =
683 tu_shader_module_from_handle(stage_info->module);
684 assert(module->code_size % 4 == 0);
685 nir = tu_spirv_to_nir(
686 dev->compiler, (const uint32_t *) module->code, module->code_size / 4,
687 stage, stage_info->pName, stage_info->pSpecializationInfo);
688 } else {
689 assert(stage == MESA_SHADER_FRAGMENT);
690 nir_builder fs_b;
691 const nir_shader_compiler_options *nir_options =
692 ir3_get_compiler_options(dev->compiler);
693 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, nir_options);
694 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
695 nir = fs_b.shader;
696 }
697
698 if (!nir) {
699 vk_free2(&dev->vk.alloc, alloc, shader);
700 return NULL;
701 }
702
703 if (unlikely(dev->physical_device->instance->debug_flags & TU_DEBUG_NIR)) {
704 fprintf(stderr, "translated nir:\n");
705 nir_print_shader(nir, stderr);
706 }
707
708 /* multi step inlining procedure */
709 NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_function_temp);
710 NIR_PASS_V(nir, nir_lower_returns);
711 NIR_PASS_V(nir, nir_inline_functions);
712 NIR_PASS_V(nir, nir_copy_prop);
713 NIR_PASS_V(nir, nir_opt_deref);
714 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
715 if (!func->is_entrypoint)
716 exec_node_remove(&func->node);
717 }
718 assert(exec_list_length(&nir->functions) == 1);
719 NIR_PASS_V(nir, nir_lower_variable_initializers, ~nir_var_function_temp);
720
721 /* Split member structs. We do this before lower_io_to_temporaries so that
722 * it doesn't lower system values to temporaries by accident.
723 */
724 NIR_PASS_V(nir, nir_split_var_copies);
725 NIR_PASS_V(nir, nir_split_per_member_structs);
726
727 NIR_PASS_V(nir, nir_remove_dead_variables,
728 nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared,
729 NULL);
730
731 /* Gather information for transform feedback.
732 * This should be called after nir_split_per_member_structs.
733 * Also needs to be called after nir_remove_dead_variables with varyings,
734 * so that we could align stream outputs correctly.
735 */
736 struct ir3_stream_output_info so_info = {};
737 if (nir->info.stage == MESA_SHADER_VERTEX ||
738 nir->info.stage == MESA_SHADER_TESS_EVAL ||
739 nir->info.stage == MESA_SHADER_GEOMETRY)
740 tu_gather_xfb_info(nir, &so_info);
741
742 NIR_PASS_V(nir, nir_propagate_invariant);
743
744 NIR_PASS_V(nir, nir_lower_io_to_temporaries, nir_shader_get_entrypoint(nir), true, true);
745
746 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
747 NIR_PASS_V(nir, nir_split_var_copies);
748 NIR_PASS_V(nir, nir_lower_var_copies);
749
750 NIR_PASS_V(nir, nir_opt_copy_prop_vars);
751 NIR_PASS_V(nir, nir_opt_combine_stores, nir_var_all);
752
753 /* ir3 doesn't support indirect input/output */
754 /* TODO: We shouldn't perform this lowering pass on gl_TessLevelInner
755 * and gl_TessLevelOuter. Since the tess levels are actually stored in
756 * a global BO, they can be directly accessed via stg and ldg.
757 * nir_lower_indirect_derefs will instead generate a big if-ladder which
758 * isn't *incorrect* but is much less efficient. */
759 NIR_PASS_V(nir, nir_lower_indirect_derefs, nir_var_shader_in | nir_var_shader_out);
760
761 NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects, false);
762
763 nir_assign_io_var_locations(nir, nir_var_shader_in, &nir->num_inputs, stage);
764 nir_assign_io_var_locations(nir, nir_var_shader_out, &nir->num_outputs, stage);
765
766 NIR_PASS_V(nir, nir_lower_system_values);
767 NIR_PASS_V(nir, nir_lower_frexp);
768
769 if (stage == MESA_SHADER_FRAGMENT) {
770 NIR_PASS_V(nir, nir_lower_input_attachments,
771 &(nir_input_attachment_options) {
772 .use_fragcoord_sysval = true,
773 .use_layer_id_sysval = false,
774 /* When using multiview rendering, we must use
775 * gl_ViewIndex as the layer id to pass to the texture
776 * sampling function. gl_Layer doesn't work when
777 * multiview is enabled.
778 */
779 .use_view_id_for_layer = multiview_mask != 0,
780 });
781 }
782
783 if (stage == MESA_SHADER_VERTEX && multiview_mask) {
784 NIR_PASS_V(nir, tu_nir_lower_multiview, multiview_mask, dev);
785 }
786
787 NIR_PASS_V(nir, nir_lower_explicit_io,
788 nir_var_mem_ubo | nir_var_mem_ssbo,
789 nir_address_format_vec2_index_32bit_offset);
790
791 if (nir->info.stage == MESA_SHADER_COMPUTE) {
792 NIR_PASS_V(nir, nir_lower_vars_to_explicit_types,
793 nir_var_mem_shared, shared_type_info);
794 NIR_PASS_V(nir, nir_lower_explicit_io,
795 nir_var_mem_shared,
796 nir_address_format_32bit_offset);
797 }
798
799 NIR_PASS_V(nir, tu_lower_io, shader, layout);
800
801 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
802
803 ir3_finalize_nir(dev->compiler, nir);
804
805 shader->ir3_shader =
806 ir3_shader_from_nir(dev->compiler, nir,
807 align(shader->push_consts.count, 4),
808 &so_info);
809
810 return shader;
811 }
812
813 void
814 tu_shader_destroy(struct tu_device *dev,
815 struct tu_shader *shader,
816 const VkAllocationCallbacks *alloc)
817 {
818 ir3_shader_destroy(shader->ir3_shader);
819
820 vk_free2(&dev->vk.alloc, alloc, shader);
821 }
822
823 VkResult
824 tu_CreateShaderModule(VkDevice _device,
825 const VkShaderModuleCreateInfo *pCreateInfo,
826 const VkAllocationCallbacks *pAllocator,
827 VkShaderModule *pShaderModule)
828 {
829 TU_FROM_HANDLE(tu_device, device, _device);
830 struct tu_shader_module *module;
831
832 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
833 assert(pCreateInfo->flags == 0);
834 assert(pCreateInfo->codeSize % 4 == 0);
835
836 module = vk_object_alloc(&device->vk, pAllocator,
837 sizeof(*module) + pCreateInfo->codeSize,
838 VK_OBJECT_TYPE_SHADER_MODULE);
839 if (module == NULL)
840 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
841
842 module->code_size = pCreateInfo->codeSize;
843 memcpy(module->code, pCreateInfo->pCode, pCreateInfo->codeSize);
844
845 _mesa_sha1_compute(module->code, module->code_size, module->sha1);
846
847 *pShaderModule = tu_shader_module_to_handle(module);
848
849 return VK_SUCCESS;
850 }
851
852 void
853 tu_DestroyShaderModule(VkDevice _device,
854 VkShaderModule _module,
855 const VkAllocationCallbacks *pAllocator)
856 {
857 TU_FROM_HANDLE(tu_device, device, _device);
858 TU_FROM_HANDLE(tu_shader_module, module, _module);
859
860 if (!module)
861 return;
862
863 vk_object_free(&device->vk, pAllocator, module);
864 }