src/freedreno/vulkan/tu_shader.c

   1 /*
   2  * Copyright © 2019 Google LLC
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "tu_private.h"
  25
  26 #include "spirv/nir_spirv.h"
  27 #include "util/mesa-sha1.h"
  28 #include "nir/nir_xfb_info.h"
  29 #include "nir/nir_vulkan.h"
  30 #include "vk_util.h"
  31
  32 #include "ir3/ir3_nir.h"
  33
  34 static nir_shader *
  35 tu_spirv_to_nir(struct ir3_compiler *compiler,
  36                 const uint32_t *words,
  37                 size_t word_count,
  38                 gl_shader_stage stage,
  39                 const char *entry_point_name,
  40                 const VkSpecializationInfo *spec_info)
  41 {
  42    /* TODO these are made-up */
  43    const struct spirv_to_nir_options spirv_options = {
  44       .frag_coord_is_sysval = true,
  45       .lower_ubo_ssbo_access_to_offsets = true,
  46       .caps = {
  47          .transform_feedback = compiler->gpu_id >= 600,
  48       },
  49    };
  50    const nir_shader_compiler_options *nir_options =
  51       ir3_get_compiler_options(compiler);
  52
  53    /* convert VkSpecializationInfo */
  54    struct nir_spirv_specialization *spec = NULL;
  55    uint32_t num_spec = 0;
  56    if (spec_info && spec_info->mapEntryCount) {
  57       spec = calloc(spec_info->mapEntryCount, sizeof(*spec));
  58       if (!spec)
  59          return NULL;
  60
  61       for (uint32_t i = 0; i < spec_info->mapEntryCount; i++) {
  62          const VkSpecializationMapEntry *entry = &spec_info->pMapEntries[i];
  63          const void *data = spec_info->pData + entry->offset;
  64          assert(data + entry->size <= spec_info->pData + spec_info->dataSize);
  65          spec[i].id = entry->constantID;
  66          switch (entry->size) {
  67          case 8:
  68             spec[i].value.u64 = *(const uint64_t *)data;
  69             break;
  70          case 4:
  71             spec[i].value.u32 = *(const uint32_t *)data;
  72             break;
  73          case 2:
  74             spec[i].value.u16 = *(const uint16_t *)data;
  75             break;
  76          case 1:
  77             spec[i].value.u8 = *(const uint8_t *)data;
  78             break;
  79          default:
  80             assert(!"Invalid spec constant size");
  81             break;
  82          }
  83          spec[i].defined_on_module = false;
  84       }
  85
  86       num_spec = spec_info->mapEntryCount;
  87    }
  88
  89    nir_shader *nir =
  90       spirv_to_nir(words, word_count, spec, num_spec, stage, entry_point_name,
  91                    &spirv_options, nir_options);
  92
  93    free(spec);
  94
  95    assert(nir->info.stage == stage);
  96    nir_validate_shader(nir, "after spirv_to_nir");
  97
  98    return nir;
  99 }
 100
 101 static void
 102 lower_load_push_constant(nir_builder *b, nir_intrinsic_instr *instr,
 103                          struct tu_shader *shader)
 104 {
 105    nir_intrinsic_instr *load =
 106       nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_uniform);
 107    load->num_components = instr->num_components;
 108    uint32_t base = nir_intrinsic_base(instr);
 109    assert(base % 4 == 0);
 110    assert(base >= shader->push_consts.lo * 16);
 111    base -= shader->push_consts.lo * 16;
 112    nir_intrinsic_set_base(load, base / 4);
 113    load->src[0] =
 114       nir_src_for_ssa(nir_ushr(b, instr->src[0].ssa, nir_imm_int(b, 2)));
 115    nir_ssa_dest_init(&load->instr, &load->dest,
 116                      load->num_components, instr->dest.ssa.bit_size,
 117                      instr->dest.ssa.name);
 118    nir_builder_instr_insert(b, &load->instr);
 119    nir_ssa_def_rewrite_uses(&instr->dest.ssa, nir_src_for_ssa(&load->dest.ssa));
 120
 121    nir_instr_remove(&instr->instr);
 122 }
 123
 124 static void
 125 lower_vulkan_resource_index(nir_builder *b, nir_intrinsic_instr *instr,
 126                             struct tu_shader *shader,
 127                             const struct tu_pipeline_layout *layout)
 128 {
 129    nir_ssa_def *vulkan_idx = instr->src[0].ssa;
 130
 131    unsigned set = nir_intrinsic_desc_set(instr);
 132    unsigned binding = nir_intrinsic_binding(instr);
 133    struct tu_descriptor_set_layout *set_layout = layout->set[set].layout;
 134    struct tu_descriptor_set_binding_layout *binding_layout =
 135       &set_layout->binding[binding];
 136    uint32_t base;
 137
 138    shader->active_desc_sets |= 1u << set;
 139
 140    switch (binding_layout->type) {
 141    case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
 142    case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
 143       base = layout->set[set].dynamic_offset_start +
 144          binding_layout->dynamic_offset_offset;
 145       set = MAX_SETS;
 146       break;
 147    default:
 148       base = binding_layout->offset / (4 * A6XX_TEX_CONST_DWORDS);
 149       break;
 150    }
 151
 152    nir_intrinsic_instr *bindless =
 153       nir_intrinsic_instr_create(b->shader,
 154                                  nir_intrinsic_bindless_resource_ir3);
 155    bindless->num_components = 0;
 156    nir_ssa_dest_init(&bindless->instr, &bindless->dest,
 157                      1, 32, NULL);
 158    nir_intrinsic_set_desc_set(bindless, set);
 159    bindless->src[0] = nir_src_for_ssa(nir_iadd(b, nir_imm_int(b, base), vulkan_idx));
 160    nir_builder_instr_insert(b, &bindless->instr);
 161
 162    nir_ssa_def_rewrite_uses(&instr->dest.ssa,
 163                             nir_src_for_ssa(&bindless->dest.ssa));
 164    nir_instr_remove(&instr->instr);
 165 }
 166
 167 static nir_ssa_def *
 168 build_bindless(nir_builder *b, nir_deref_instr *deref, bool is_sampler,
 169                struct tu_shader *shader,
 170                const struct tu_pipeline_layout *layout)
 171 {
 172    nir_variable *var = nir_deref_instr_get_variable(deref);
 173
 174    unsigned set = var->data.descriptor_set;
 175    unsigned binding = var->data.binding;
 176    const struct tu_descriptor_set_binding_layout *bind_layout =
 177       &layout->set[set].layout->binding[binding];
 178
 179    /* input attachments use non bindless workaround */
 180    if (bind_layout->type == VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT) {
 181       const struct glsl_type *glsl_type = glsl_without_array(var->type);
 182       uint32_t idx = var->data.index * 2;
 183
 184       b->shader->info.textures_used |=
 185          ((1ull << (bind_layout->array_size * 2)) - 1) << (idx * 2);
 186
 187       /* D24S8 workaround: stencil of D24S8 will be sampled as uint */
 188       if (glsl_get_sampler_result_type(glsl_type) == GLSL_TYPE_UINT)
 189          idx += 1;
 190
 191       if (deref->deref_type == nir_deref_type_var)
 192          return nir_imm_int(b, idx);
 193
 194       nir_ssa_def *arr_index = nir_ssa_for_src(b, deref->arr.index, 1);
 195       return nir_iadd(b, nir_imm_int(b, idx),
 196                       nir_imul_imm(b, arr_index, 2));
 197    }
 198
 199    shader->active_desc_sets |= 1u << set;
 200
 201    nir_ssa_def *desc_offset;
 202    unsigned descriptor_stride;
 203    unsigned offset = 0;
 204    /* Samplers come second in combined image/sampler descriptors, see
 205       * write_combined_image_sampler_descriptor().
 206       */
 207    if (is_sampler && bind_layout->type ==
 208          VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER) {
 209       offset = 1;
 210    }
 211    desc_offset =
 212       nir_imm_int(b, (bind_layout->offset / (4 * A6XX_TEX_CONST_DWORDS)) +
 213                   offset);
 214    descriptor_stride = bind_layout->size / (4 * A6XX_TEX_CONST_DWORDS);
 215
 216    if (deref->deref_type != nir_deref_type_var) {
 217       assert(deref->deref_type == nir_deref_type_array);
 218
 219       nir_ssa_def *arr_index = nir_ssa_for_src(b, deref->arr.index, 1);
 220       desc_offset = nir_iadd(b, desc_offset,
 221                              nir_imul_imm(b, arr_index, descriptor_stride));
 222    }
 223
 224    nir_intrinsic_instr *bindless =
 225       nir_intrinsic_instr_create(b->shader,
 226                                  nir_intrinsic_bindless_resource_ir3);
 227    bindless->num_components = 0;
 228    nir_ssa_dest_init(&bindless->instr, &bindless->dest,
 229                      1, 32, NULL);
 230    nir_intrinsic_set_desc_set(bindless, set);
 231    bindless->src[0] = nir_src_for_ssa(desc_offset);
 232    nir_builder_instr_insert(b, &bindless->instr);
 233
 234    return &bindless->dest.ssa;
 235 }
 236
 237 static void
 238 lower_image_deref(nir_builder *b,
 239                   nir_intrinsic_instr *instr, struct tu_shader *shader,
 240                   const struct tu_pipeline_layout *layout)
 241 {
 242    nir_deref_instr *deref = nir_src_as_deref(instr->src[0]);
 243    nir_ssa_def *bindless = build_bindless(b, deref, false, shader, layout);
 244    nir_rewrite_image_intrinsic(instr, bindless, true);
 245 }
 246
 247 static bool
 248 lower_intrinsic(nir_builder *b, nir_intrinsic_instr *instr,
 249                 struct tu_shader *shader,
 250                 const struct tu_pipeline_layout *layout)
 251 {
 252    switch (instr->intrinsic) {
 253    case nir_intrinsic_load_layer_id:
 254       /* TODO: remove this when layered rendering is implemented */
 255       nir_ssa_def_rewrite_uses(&instr->dest.ssa,
 256                                nir_src_for_ssa(nir_imm_int(b, 0)));
 257       nir_instr_remove(&instr->instr);
 258       return true;
 259
 260    case nir_intrinsic_load_push_constant:
 261       lower_load_push_constant(b, instr, shader);
 262       return true;
 263
 264    case nir_intrinsic_vulkan_resource_index:
 265       lower_vulkan_resource_index(b, instr, shader, layout);
 266       return true;
 267
 268    case nir_intrinsic_image_deref_load:
 269    case nir_intrinsic_image_deref_store:
 270    case nir_intrinsic_image_deref_atomic_add:
 271    case nir_intrinsic_image_deref_atomic_imin:
 272    case nir_intrinsic_image_deref_atomic_umin:
 273    case nir_intrinsic_image_deref_atomic_imax:
 274    case nir_intrinsic_image_deref_atomic_umax:
 275    case nir_intrinsic_image_deref_atomic_and:
 276    case nir_intrinsic_image_deref_atomic_or:
 277    case nir_intrinsic_image_deref_atomic_xor:
 278    case nir_intrinsic_image_deref_atomic_exchange:
 279    case nir_intrinsic_image_deref_atomic_comp_swap:
 280    case nir_intrinsic_image_deref_size:
 281    case nir_intrinsic_image_deref_samples:
 282       lower_image_deref(b, instr, shader, layout);
 283       return true;
 284
 285    default:
 286       return false;
 287    }
 288 }
 289
 290 static void
 291 lower_tex_ycbcr(const struct tu_pipeline_layout *layout,
 292                 nir_builder *builder,
 293                 nir_tex_instr *tex)
 294 {
 295    int deref_src_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_deref);
 296    assert(deref_src_idx >= 0);
 297    nir_deref_instr *deref = nir_src_as_deref(tex->src[deref_src_idx].src);
 298
 299    nir_variable *var = nir_deref_instr_get_variable(deref);
 300    const struct tu_descriptor_set_layout *set_layout =
 301       layout->set[var->data.descriptor_set].layout;
 302    const struct tu_descriptor_set_binding_layout *binding =
 303       &set_layout->binding[var->data.binding];
 304    const struct tu_sampler_ycbcr_conversion *ycbcr_samplers =
 305       tu_immutable_ycbcr_samplers(set_layout, binding);
 306
 307    if (!ycbcr_samplers)
 308       return;
 309
 310    /* For the following instructions, we don't apply any change */
 311    if (tex->op == nir_texop_txs ||
 312        tex->op == nir_texop_query_levels ||
 313        tex->op == nir_texop_lod)
 314       return;
 315
 316    assert(tex->texture_index == 0);
 317    unsigned array_index = 0;
 318    if (deref->deref_type != nir_deref_type_var) {
 319       assert(deref->deref_type == nir_deref_type_array);
 320       if (!nir_src_is_const(deref->arr.index))
 321          return;
 322       array_index = nir_src_as_uint(deref->arr.index);
 323       array_index = MIN2(array_index, binding->array_size - 1);
 324    }
 325    const struct tu_sampler_ycbcr_conversion *ycbcr_sampler = ycbcr_samplers + array_index;
 326
 327    if (ycbcr_sampler->ycbcr_model == VK_SAMPLER_YCBCR_MODEL_CONVERSION_RGB_IDENTITY)
 328       return;
 329
 330    builder->cursor = nir_after_instr(&tex->instr);
 331
 332    uint8_t bits = vk_format_get_component_bits(ycbcr_sampler->format,
 333                                                UTIL_FORMAT_COLORSPACE_RGB,
 334                                                PIPE_SWIZZLE_X);
 335    uint32_t bpcs[3] = {bits, bits, bits}; /* TODO: use right bpc for each channel ? */
 336    nir_ssa_def *result = nir_convert_ycbcr_to_rgb(builder,
 337                                                   ycbcr_sampler->ycbcr_model,
 338                                                   ycbcr_sampler->ycbcr_range,
 339                                                   &tex->dest.ssa,
 340                                                   bpcs);
 341    nir_ssa_def_rewrite_uses_after(&tex->dest.ssa, nir_src_for_ssa(result),
 342                                   result->parent_instr);
 343
 344    builder->cursor = nir_before_instr(&tex->instr);
 345 }
 346
 347 static bool
 348 lower_tex(nir_builder *b, nir_tex_instr *tex,
 349           struct tu_shader *shader, const struct tu_pipeline_layout *layout)
 350 {
 351    lower_tex_ycbcr(layout, b, tex);
 352
 353    int sampler_src_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_deref);
 354    if (sampler_src_idx >= 0) {
 355       nir_deref_instr *deref = nir_src_as_deref(tex->src[sampler_src_idx].src);
 356       nir_ssa_def *bindless = build_bindless(b, deref, true, shader, layout);
 357       nir_instr_rewrite_src(&tex->instr, &tex->src[sampler_src_idx].src,
 358                             nir_src_for_ssa(bindless));
 359       tex->src[sampler_src_idx].src_type = nir_tex_src_sampler_handle;
 360    }
 361
 362    int tex_src_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_deref);
 363    if (tex_src_idx >= 0) {
 364       nir_deref_instr *deref = nir_src_as_deref(tex->src[tex_src_idx].src);
 365       nir_ssa_def *bindless = build_bindless(b, deref, false, shader, layout);
 366       nir_instr_rewrite_src(&tex->instr, &tex->src[tex_src_idx].src,
 367                             nir_src_for_ssa(bindless));
 368       tex->src[tex_src_idx].src_type = nir_tex_src_texture_handle;
 369
 370       /* for the input attachment case: */
 371       if (bindless->parent_instr->type != nir_instr_type_intrinsic)
 372          tex->src[tex_src_idx].src_type = nir_tex_src_texture_offset;
 373    }
 374
 375    return true;
 376 }
 377
 378 static bool
 379 lower_impl(nir_function_impl *impl, struct tu_shader *shader,
 380             const struct tu_pipeline_layout *layout)
 381 {
 382    nir_builder b;
 383    nir_builder_init(&b, impl);
 384    bool progress = false;
 385
 386    nir_foreach_block(block, impl) {
 387       nir_foreach_instr_safe(instr, block) {
 388          b.cursor = nir_before_instr(instr);
 389          switch (instr->type) {
 390          case nir_instr_type_tex:
 391             progress |= lower_tex(&b, nir_instr_as_tex(instr), shader, layout);
 392             break;
 393          case nir_instr_type_intrinsic:
 394             progress |= lower_intrinsic(&b, nir_instr_as_intrinsic(instr), shader, layout);
 395             break;
 396          default:
 397             break;
 398          }
 399       }
 400    }
 401
 402    return progress;
 403 }
 404
 405
 406 /* Figure out the range of push constants that we're actually going to push to
 407  * the shader, and tell the backend to reserve this range when pushing UBO
 408  * constants.
 409  */
 410
 411 static void
 412 gather_push_constants(nir_shader *shader, struct tu_shader *tu_shader)
 413 {
 414    uint32_t min = UINT32_MAX, max = 0;
 415    nir_foreach_function(function, shader) {
 416       if (!function->impl)
 417          continue;
 418
 419       nir_foreach_block(block, function->impl) {
 420          nir_foreach_instr_safe(instr, block) {
 421             if (instr->type != nir_instr_type_intrinsic)
 422                continue;
 423
 424             nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
 425             if (intrin->intrinsic != nir_intrinsic_load_push_constant)
 426                continue;
 427
 428             uint32_t base = nir_intrinsic_base(intrin);
 429             uint32_t range = nir_intrinsic_range(intrin);
 430             min = MIN2(min, base);
 431             max = MAX2(max, base + range);
 432             break;
 433          }
 434       }
 435    }
 436
 437    if (min >= max) {
 438       tu_shader->push_consts.lo = 0;
 439       tu_shader->push_consts.count = 0;
 440       return;
 441    }
 442
 443    /* CP_LOAD_STATE OFFSET and NUM_UNIT are in units of vec4 (4 dwords),
 444     * however there's an alignment requirement of 4 on OFFSET. Expand the
 445     * range and change units accordingly.
 446     */
 447    tu_shader->push_consts.lo = (min / 16) / 4 * 4;
 448    tu_shader->push_consts.count =
 449       align(max, 16) / 16 - tu_shader->push_consts.lo;
 450 }
 451
 452 static bool
 453 tu_lower_io(nir_shader *shader, struct tu_shader *tu_shader,
 454             const struct tu_pipeline_layout *layout)
 455 {
 456    bool progress = false;
 457
 458    gather_push_constants(shader, tu_shader);
 459
 460    nir_foreach_function(function, shader) {
 461       if (function->impl)
 462          progress |= lower_impl(function->impl, tu_shader, layout);
 463    }
 464
 465    /* Remove now-unused variables so that when we gather the shader info later
 466     * they won't be counted.
 467     */
 468
 469    if (progress)
 470       nir_opt_dce(shader);
 471
 472    progress |=
 473       nir_remove_dead_variables(shader,
 474                                 nir_var_uniform | nir_var_mem_ubo | nir_var_mem_ssbo,
 475                                 NULL);
 476
 477    return progress;
 478 }
 479
 480 static void
 481 tu_gather_xfb_info(nir_shader *nir, struct ir3_stream_output_info *info)
 482 {
 483    nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
 484
 485    if (!xfb)
 486       return;
 487
 488    /* creating a map from VARYING_SLOT_* enums to consecutive index */
 489    uint8_t num_outputs = 0;
 490    uint64_t outputs_written = 0;
 491    for (int i = 0; i < xfb->output_count; i++)
 492       outputs_written |= BITFIELD64_BIT(xfb->outputs[i].location);
 493
 494    uint8_t output_map[VARYING_SLOT_TESS_MAX];
 495    memset(output_map, 0, sizeof(output_map));
 496
 497    for (unsigned attr = 0; attr < VARYING_SLOT_MAX; attr++) {
 498       if (outputs_written & BITFIELD64_BIT(attr))
 499          output_map[attr] = num_outputs++;
 500    }
 501
 502    assert(xfb->output_count < IR3_MAX_SO_OUTPUTS);
 503    info->num_outputs = xfb->output_count;
 504
 505    for (int i = 0; i < IR3_MAX_SO_BUFFERS; i++)
 506       info->stride[i] = xfb->buffers[i].stride / 4;
 507
 508    for (int i = 0; i < xfb->output_count; i++) {
 509       info->output[i].register_index = output_map[xfb->outputs[i].location];
 510       info->output[i].start_component = xfb->outputs[i].component_offset;
 511       info->output[i].num_components =
 512                            util_bitcount(xfb->outputs[i].component_mask);
 513       info->output[i].output_buffer  = xfb->outputs[i].buffer;
 514       info->output[i].dst_offset = xfb->outputs[i].offset / 4;
 515       info->output[i].stream = xfb->buffer_to_stream[xfb->outputs[i].buffer];
 516    }
 517
 518    ralloc_free(xfb);
 519 }
 520
 521 struct tu_shader *
 522 tu_shader_create(struct tu_device *dev,
 523                  gl_shader_stage stage,
 524                  const VkPipelineShaderStageCreateInfo *stage_info,
 525                  struct tu_pipeline_layout *layout,
 526                  const VkAllocationCallbacks *alloc)
 527 {
 528    struct tu_shader *shader;
 529
 530    shader = vk_zalloc2(
 531       &dev->alloc, alloc,
 532       sizeof(*shader),
 533       8, VK_SYSTEM_ALLOCATION_SCOPE_COMMAND);
 534    if (!shader)
 535       return NULL;
 536
 537    nir_shader *nir;
 538    if (stage_info) {
 539       /* translate SPIR-V to NIR */
 540       const struct tu_shader_module *module =
 541          tu_shader_module_from_handle(stage_info->module);
 542       assert(module->code_size % 4 == 0);
 543       nir = tu_spirv_to_nir(
 544          dev->compiler, (const uint32_t *) module->code, module->code_size / 4,
 545          stage, stage_info->pName, stage_info->pSpecializationInfo);
 546    } else {
 547       assert(stage == MESA_SHADER_FRAGMENT);
 548       nir_builder fs_b;
 549       const nir_shader_compiler_options *nir_options =
 550          ir3_get_compiler_options(dev->compiler);
 551       nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, nir_options);
 552       fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
 553       nir = fs_b.shader;
 554    }
 555
 556    if (!nir) {
 557       vk_free2(&dev->alloc, alloc, shader);
 558       return NULL;
 559    }
 560
 561    if (unlikely(dev->physical_device->instance->debug_flags & TU_DEBUG_NIR)) {
 562       fprintf(stderr, "translated nir:\n");
 563       nir_print_shader(nir, stderr);
 564    }
 565
 566    /* multi step inlining procedure */
 567    NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_function_temp);
 568    NIR_PASS_V(nir, nir_lower_returns);
 569    NIR_PASS_V(nir, nir_inline_functions);
 570    NIR_PASS_V(nir, nir_opt_deref);
 571    foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
 572       if (!func->is_entrypoint)
 573          exec_node_remove(&func->node);
 574    }
 575    assert(exec_list_length(&nir->functions) == 1);
 576    NIR_PASS_V(nir, nir_lower_variable_initializers, ~nir_var_function_temp);
 577
 578    /* Split member structs.  We do this before lower_io_to_temporaries so that
 579     * it doesn't lower system values to temporaries by accident.
 580     */
 581    NIR_PASS_V(nir, nir_split_var_copies);
 582    NIR_PASS_V(nir, nir_split_per_member_structs);
 583
 584    NIR_PASS_V(nir, nir_remove_dead_variables,
 585               nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared,
 586               NULL);
 587
 588    /* Gather information for transform feedback.
 589     * This should be called after nir_split_per_member_structs.
 590     * Also needs to be called after nir_remove_dead_variables with varyings,
 591     * so that we could align stream outputs correctly.
 592     */
 593    struct ir3_stream_output_info so_info = {};
 594    if (nir->info.stage == MESA_SHADER_VERTEX ||
 595          nir->info.stage == MESA_SHADER_TESS_EVAL ||
 596          nir->info.stage == MESA_SHADER_GEOMETRY)
 597       tu_gather_xfb_info(nir, &so_info);
 598
 599    NIR_PASS_V(nir, nir_propagate_invariant);
 600
 601    NIR_PASS_V(nir, nir_lower_io_to_temporaries, nir_shader_get_entrypoint(nir), true, true);
 602
 603    NIR_PASS_V(nir, nir_lower_global_vars_to_local);
 604    NIR_PASS_V(nir, nir_split_var_copies);
 605    NIR_PASS_V(nir, nir_lower_var_copies);
 606
 607    NIR_PASS_V(nir, nir_opt_copy_prop_vars);
 608    NIR_PASS_V(nir, nir_opt_combine_stores, nir_var_all);
 609
 610    /* ir3 doesn't support indirect input/output */
 611    NIR_PASS_V(nir, nir_lower_indirect_derefs, nir_var_shader_in | nir_var_shader_out);
 612
 613    NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects, false);
 614
 615    nir_assign_io_var_locations(&nir->inputs, &nir->num_inputs, stage);
 616    nir_assign_io_var_locations(&nir->outputs, &nir->num_outputs, stage);
 617
 618    NIR_PASS_V(nir, nir_lower_system_values);
 619    NIR_PASS_V(nir, nir_lower_frexp);
 620
 621    if (stage == MESA_SHADER_FRAGMENT)
 622       NIR_PASS_V(nir, nir_lower_input_attachments, true);
 623
 624    NIR_PASS_V(nir, tu_lower_io, shader, layout);
 625
 626    nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
 627
 628    shader->ir3_shader =
 629       ir3_shader_from_nir(dev->compiler, nir,
 630                           align(shader->push_consts.count, 4),
 631                           &so_info);
 632
 633    return shader;
 634 }
 635
 636 void
 637 tu_shader_destroy(struct tu_device *dev,
 638                   struct tu_shader *shader,
 639                   const VkAllocationCallbacks *alloc)
 640 {
 641    ir3_shader_destroy(shader->ir3_shader);
 642
 643    vk_free2(&dev->alloc, alloc, shader);
 644 }
 645
 646 VkResult
 647 tu_CreateShaderModule(VkDevice _device,
 648                       const VkShaderModuleCreateInfo *pCreateInfo,
 649                       const VkAllocationCallbacks *pAllocator,
 650                       VkShaderModule *pShaderModule)
 651 {
 652    TU_FROM_HANDLE(tu_device, device, _device);
 653    struct tu_shader_module *module;
 654
 655    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
 656    assert(pCreateInfo->flags == 0);
 657    assert(pCreateInfo->codeSize % 4 == 0);
 658
 659    module = vk_alloc2(&device->alloc, pAllocator,
 660                       sizeof(*module) + pCreateInfo->codeSize, 8,
 661                       VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 662    if (module == NULL)
 663       return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
 664
 665    module->code_size = pCreateInfo->codeSize;
 666    memcpy(module->code, pCreateInfo->pCode, pCreateInfo->codeSize);
 667
 668    _mesa_sha1_compute(module->code, module->code_size, module->sha1);
 669
 670    *pShaderModule = tu_shader_module_to_handle(module);
 671
 672    return VK_SUCCESS;
 673 }
 674
 675 void
 676 tu_DestroyShaderModule(VkDevice _device,
 677                        VkShaderModule _module,
 678                        const VkAllocationCallbacks *pAllocator)
 679 {
 680    TU_FROM_HANDLE(tu_device, device, _device);
 681    TU_FROM_HANDLE(tu_shader_module, module, _module);
 682
 683    if (!module)
 684       return;
 685
 686    vk_free2(&device->alloc, pAllocator, module);
 687 }