src/freedreno/vulkan/tu_shader.c

   1 /*
   2  * Copyright © 2019 Google LLC
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "tu_private.h"
  25
  26 #include "spirv/nir_spirv.h"
  27 #include "util/mesa-sha1.h"
  28 #include "nir/nir_xfb_info.h"
  29 #include "nir/nir_vulkan.h"
  30 #include "vk_util.h"
  31
  32 #include "ir3/ir3_nir.h"
  33
  34 static nir_shader *
  35 tu_spirv_to_nir(struct ir3_compiler *compiler,
  36                 const uint32_t *words,
  37                 size_t word_count,
  38                 gl_shader_stage stage,
  39                 const char *entry_point_name,
  40                 const VkSpecializationInfo *spec_info)
  41 {
  42    /* TODO these are made-up */
  43    const struct spirv_to_nir_options spirv_options = {
  44       .frag_coord_is_sysval = true,
  45       .lower_ubo_ssbo_access_to_offsets = false,
  46
  47       .ubo_addr_format = nir_address_format_vec2_index_32bit_offset,
  48       .ssbo_addr_format = nir_address_format_vec2_index_32bit_offset,
  49
  50       /* Accessed via stg/ldg */
  51       .phys_ssbo_addr_format = nir_address_format_64bit_global,
  52
  53       /* Accessed via the const register file */
  54       .push_const_addr_format = nir_address_format_logical,
  55
  56       /* Accessed via ldl/stl */
  57       .shared_addr_format = nir_address_format_32bit_offset,
  58
  59       /* Accessed via stg/ldg (not used with Vulkan?) */
  60       .global_addr_format = nir_address_format_64bit_global,
  61
  62       .caps = {
  63          .transform_feedback = true,
  64          .tessellation = true,
  65          .draw_parameters = true,
  66       },
  67    };
  68    const nir_shader_compiler_options *nir_options =
  69       ir3_get_compiler_options(compiler);
  70
  71    /* convert VkSpecializationInfo */
  72    struct nir_spirv_specialization *spec = NULL;
  73    uint32_t num_spec = 0;
  74    if (spec_info && spec_info->mapEntryCount) {
  75       spec = calloc(spec_info->mapEntryCount, sizeof(*spec));
  76       if (!spec)
  77          return NULL;
  78
  79       for (uint32_t i = 0; i < spec_info->mapEntryCount; i++) {
  80          const VkSpecializationMapEntry *entry = &spec_info->pMapEntries[i];
  81          const void *data = spec_info->pData + entry->offset;
  82          assert(data + entry->size <= spec_info->pData + spec_info->dataSize);
  83          spec[i].id = entry->constantID;
  84          switch (entry->size) {
  85          case 8:
  86             spec[i].value.u64 = *(const uint64_t *)data;
  87             break;
  88          case 4:
  89             spec[i].value.u32 = *(const uint32_t *)data;
  90             break;
  91          case 2:
  92             spec[i].value.u16 = *(const uint16_t *)data;
  93             break;
  94          case 1:
  95             spec[i].value.u8 = *(const uint8_t *)data;
  96             break;
  97          default:
  98             assert(!"Invalid spec constant size");
  99             break;
 100          }
 101          spec[i].defined_on_module = false;
 102       }
 103
 104       num_spec = spec_info->mapEntryCount;
 105    }
 106
 107    nir_shader *nir =
 108       spirv_to_nir(words, word_count, spec, num_spec, stage, entry_point_name,
 109                    &spirv_options, nir_options);
 110
 111    free(spec);
 112
 113    assert(nir->info.stage == stage);
 114    nir_validate_shader(nir, "after spirv_to_nir");
 115
 116    return nir;
 117 }
 118
 119 static void
 120 lower_load_push_constant(nir_builder *b, nir_intrinsic_instr *instr,
 121                          struct tu_shader *shader)
 122 {
 123    nir_intrinsic_instr *load =
 124       nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_uniform);
 125    load->num_components = instr->num_components;
 126    uint32_t base = nir_intrinsic_base(instr);
 127    assert(base % 4 == 0);
 128    assert(base >= shader->push_consts.lo * 16);
 129    base -= shader->push_consts.lo * 16;
 130    nir_intrinsic_set_base(load, base / 4);
 131    load->src[0] =
 132       nir_src_for_ssa(nir_ushr(b, instr->src[0].ssa, nir_imm_int(b, 2)));
 133    nir_ssa_dest_init(&load->instr, &load->dest,
 134                      load->num_components, instr->dest.ssa.bit_size,
 135                      instr->dest.ssa.name);
 136    nir_builder_instr_insert(b, &load->instr);
 137    nir_ssa_def_rewrite_uses(&instr->dest.ssa, nir_src_for_ssa(&load->dest.ssa));
 138
 139    nir_instr_remove(&instr->instr);
 140 }
 141
 142 static void
 143 lower_vulkan_resource_index(nir_builder *b, nir_intrinsic_instr *instr,
 144                             struct tu_shader *shader,
 145                             const struct tu_pipeline_layout *layout)
 146 {
 147    nir_ssa_def *vulkan_idx = instr->src[0].ssa;
 148
 149    unsigned set = nir_intrinsic_desc_set(instr);
 150    unsigned binding = nir_intrinsic_binding(instr);
 151    struct tu_descriptor_set_layout *set_layout = layout->set[set].layout;
 152    struct tu_descriptor_set_binding_layout *binding_layout =
 153       &set_layout->binding[binding];
 154    uint32_t base;
 155
 156    shader->active_desc_sets |= 1u << set;
 157
 158    switch (binding_layout->type) {
 159    case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
 160    case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
 161       base = layout->set[set].dynamic_offset_start +
 162          binding_layout->dynamic_offset_offset;
 163       set = MAX_SETS;
 164       break;
 165    default:
 166       base = binding_layout->offset / (4 * A6XX_TEX_CONST_DWORDS);
 167       break;
 168    }
 169
 170    nir_ssa_def *def = nir_vec3(b, nir_imm_int(b, set),
 171                                nir_iadd(b, nir_imm_int(b, base), vulkan_idx),
 172                                nir_imm_int(b, 0));
 173
 174    nir_ssa_def_rewrite_uses(&instr->dest.ssa, nir_src_for_ssa(def));
 175    nir_instr_remove(&instr->instr);
 176 }
 177
 178 static void
 179 lower_load_vulkan_descriptor(nir_intrinsic_instr *intrin)
 180 {
 181    /* Loading the descriptor happens as part of the load/store instruction so
 182     * this is a no-op.
 183     */
 184    nir_ssa_def_rewrite_uses(&intrin->dest.ssa, intrin->src[0]);
 185    nir_instr_remove(&intrin->instr);
 186 }
 187
 188 static void
 189 lower_ssbo_ubo_intrinsic(nir_builder *b, nir_intrinsic_instr *intrin)
 190 {
 191    const nir_intrinsic_info *info = &nir_intrinsic_infos[intrin->intrinsic];
 192
 193    /* The bindless base is part of the instruction, which means that part of
 194     * the "pointer" has to be constant. We solve this in the same way the blob
 195     * does, by generating a bunch of if-statements. In the usual case where
 196     * the descriptor set is constant this will get optimized out.
 197     */
 198
 199    unsigned buffer_src;
 200    if (intrin->intrinsic == nir_intrinsic_store_ssbo) {
 201       /* This has the value first */
 202       buffer_src = 1;
 203    } else {
 204       buffer_src = 0;
 205    }
 206
 207    nir_ssa_def *base_idx = nir_channel(b, intrin->src[buffer_src].ssa, 0);
 208    nir_ssa_def *descriptor_idx = nir_channel(b, intrin->src[buffer_src].ssa, 1);
 209
 210    nir_ssa_def *results[MAX_SETS + 1] = { NULL };
 211
 212    for (unsigned i = 0; i < MAX_SETS + 1; i++) {
 213       /* if (base_idx == i) { ... */
 214       nir_if *nif = nir_push_if(b, nir_ieq(b, base_idx, nir_imm_int(b, i)));
 215
 216       nir_intrinsic_instr *bindless =
 217          nir_intrinsic_instr_create(b->shader,
 218                                     nir_intrinsic_bindless_resource_ir3);
 219       bindless->num_components = 0;
 220       nir_ssa_dest_init(&bindless->instr, &bindless->dest,
 221                         1, 32, NULL);
 222       nir_intrinsic_set_desc_set(bindless, i);
 223       bindless->src[0] = nir_src_for_ssa(descriptor_idx);
 224       nir_builder_instr_insert(b, &bindless->instr);
 225
 226       nir_intrinsic_instr *copy =
 227          nir_intrinsic_instr_create(b->shader, intrin->intrinsic);
 228
 229       copy->num_components = intrin->num_components;
 230
 231       for (unsigned src = 0; src < info->num_srcs; src++) {
 232          if (src == buffer_src)
 233             copy->src[src] = nir_src_for_ssa(&bindless->dest.ssa);
 234          else
 235             copy->src[src] = nir_src_for_ssa(intrin->src[src].ssa);
 236       }
 237
 238       for (unsigned idx = 0; idx < info->num_indices; idx++) {
 239          copy->const_index[idx] = intrin->const_index[idx];
 240       }
 241
 242       if (info->has_dest) {
 243          nir_ssa_dest_init(&copy->instr, &copy->dest,
 244                            intrin->dest.ssa.num_components,
 245                            intrin->dest.ssa.bit_size,
 246                            intrin->dest.ssa.name);
 247          results[i] = &copy->dest.ssa;
 248       }
 249
 250       nir_builder_instr_insert(b, &copy->instr);
 251
 252       /* } else { ... */
 253       nir_push_else(b, nif);
 254    }
 255
 256    nir_ssa_def *result =
 257       nir_ssa_undef(b, intrin->dest.ssa.num_components, intrin->dest.ssa.bit_size);
 258    for (int i = MAX_SETS; i >= 0; i--) {
 259       nir_pop_if(b, NULL);
 260       if (info->has_dest)
 261          result = nir_if_phi(b, results[i], result);
 262    }
 263
 264    if (info->has_dest)
 265       nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(result));
 266    nir_instr_remove(&intrin->instr);
 267 }
 268
 269 static nir_ssa_def *
 270 build_bindless(nir_builder *b, nir_deref_instr *deref, bool is_sampler,
 271                struct tu_shader *shader,
 272                const struct tu_pipeline_layout *layout)
 273 {
 274    nir_variable *var = nir_deref_instr_get_variable(deref);
 275
 276    unsigned set = var->data.descriptor_set;
 277    unsigned binding = var->data.binding;
 278    const struct tu_descriptor_set_binding_layout *bind_layout =
 279       &layout->set[set].layout->binding[binding];
 280
 281    /* input attachments use non bindless workaround */
 282    if (bind_layout->type == VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT) {
 283       const struct glsl_type *glsl_type = glsl_without_array(var->type);
 284       uint32_t idx = var->data.index * 2;
 285
 286       b->shader->info.textures_used |=
 287          ((1ull << (bind_layout->array_size * 2)) - 1) << (idx * 2);
 288
 289       /* D24S8 workaround: stencil of D24S8 will be sampled as uint */
 290       if (glsl_get_sampler_result_type(glsl_type) == GLSL_TYPE_UINT)
 291          idx += 1;
 292
 293       if (deref->deref_type == nir_deref_type_var)
 294          return nir_imm_int(b, idx);
 295
 296       nir_ssa_def *arr_index = nir_ssa_for_src(b, deref->arr.index, 1);
 297       return nir_iadd(b, nir_imm_int(b, idx),
 298                       nir_imul_imm(b, arr_index, 2));
 299    }
 300
 301    shader->active_desc_sets |= 1u << set;
 302
 303    nir_ssa_def *desc_offset;
 304    unsigned descriptor_stride;
 305    unsigned offset = 0;
 306    /* Samplers come second in combined image/sampler descriptors, see
 307       * write_combined_image_sampler_descriptor().
 308       */
 309    if (is_sampler && bind_layout->type ==
 310          VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER) {
 311       offset = 1;
 312    }
 313    desc_offset =
 314       nir_imm_int(b, (bind_layout->offset / (4 * A6XX_TEX_CONST_DWORDS)) +
 315                   offset);
 316    descriptor_stride = bind_layout->size / (4 * A6XX_TEX_CONST_DWORDS);
 317
 318    if (deref->deref_type != nir_deref_type_var) {
 319       assert(deref->deref_type == nir_deref_type_array);
 320
 321       nir_ssa_def *arr_index = nir_ssa_for_src(b, deref->arr.index, 1);
 322       desc_offset = nir_iadd(b, desc_offset,
 323                              nir_imul_imm(b, arr_index, descriptor_stride));
 324    }
 325
 326    nir_intrinsic_instr *bindless =
 327       nir_intrinsic_instr_create(b->shader,
 328                                  nir_intrinsic_bindless_resource_ir3);
 329    bindless->num_components = 0;
 330    nir_ssa_dest_init(&bindless->instr, &bindless->dest,
 331                      1, 32, NULL);
 332    nir_intrinsic_set_desc_set(bindless, set);
 333    bindless->src[0] = nir_src_for_ssa(desc_offset);
 334    nir_builder_instr_insert(b, &bindless->instr);
 335
 336    return &bindless->dest.ssa;
 337 }
 338
 339 static void
 340 lower_image_deref(nir_builder *b,
 341                   nir_intrinsic_instr *instr, struct tu_shader *shader,
 342                   const struct tu_pipeline_layout *layout)
 343 {
 344    nir_deref_instr *deref = nir_src_as_deref(instr->src[0]);
 345    nir_ssa_def *bindless = build_bindless(b, deref, false, shader, layout);
 346    nir_rewrite_image_intrinsic(instr, bindless, true);
 347 }
 348
 349 static bool
 350 lower_intrinsic(nir_builder *b, nir_intrinsic_instr *instr,
 351                 struct tu_shader *shader,
 352                 const struct tu_pipeline_layout *layout)
 353 {
 354    switch (instr->intrinsic) {
 355    case nir_intrinsic_load_layer_id:
 356       /* TODO: remove this when layered rendering is implemented */
 357       nir_ssa_def_rewrite_uses(&instr->dest.ssa,
 358                                nir_src_for_ssa(nir_imm_int(b, 0)));
 359       nir_instr_remove(&instr->instr);
 360       return true;
 361
 362    case nir_intrinsic_load_push_constant:
 363       lower_load_push_constant(b, instr, shader);
 364       return true;
 365
 366    case nir_intrinsic_load_vulkan_descriptor:
 367       lower_load_vulkan_descriptor(instr);
 368       return true;
 369
 370    case nir_intrinsic_vulkan_resource_index:
 371       lower_vulkan_resource_index(b, instr, shader, layout);
 372       return true;
 373
 374    case nir_intrinsic_load_ubo:
 375    case nir_intrinsic_load_ssbo:
 376    case nir_intrinsic_store_ssbo:
 377    case nir_intrinsic_ssbo_atomic_add:
 378    case nir_intrinsic_ssbo_atomic_imin:
 379    case nir_intrinsic_ssbo_atomic_umin:
 380    case nir_intrinsic_ssbo_atomic_imax:
 381    case nir_intrinsic_ssbo_atomic_umax:
 382    case nir_intrinsic_ssbo_atomic_and:
 383    case nir_intrinsic_ssbo_atomic_or:
 384    case nir_intrinsic_ssbo_atomic_xor:
 385    case nir_intrinsic_ssbo_atomic_exchange:
 386    case nir_intrinsic_ssbo_atomic_comp_swap:
 387    case nir_intrinsic_ssbo_atomic_fadd:
 388    case nir_intrinsic_ssbo_atomic_fmin:
 389    case nir_intrinsic_ssbo_atomic_fmax:
 390    case nir_intrinsic_ssbo_atomic_fcomp_swap:
 391    case nir_intrinsic_get_buffer_size:
 392       lower_ssbo_ubo_intrinsic(b, instr);
 393       return true;
 394
 395    case nir_intrinsic_image_deref_load:
 396    case nir_intrinsic_image_deref_store:
 397    case nir_intrinsic_image_deref_atomic_add:
 398    case nir_intrinsic_image_deref_atomic_imin:
 399    case nir_intrinsic_image_deref_atomic_umin:
 400    case nir_intrinsic_image_deref_atomic_imax:
 401    case nir_intrinsic_image_deref_atomic_umax:
 402    case nir_intrinsic_image_deref_atomic_and:
 403    case nir_intrinsic_image_deref_atomic_or:
 404    case nir_intrinsic_image_deref_atomic_xor:
 405    case nir_intrinsic_image_deref_atomic_exchange:
 406    case nir_intrinsic_image_deref_atomic_comp_swap:
 407    case nir_intrinsic_image_deref_size:
 408    case nir_intrinsic_image_deref_samples:
 409       lower_image_deref(b, instr, shader, layout);
 410       return true;
 411
 412    default:
 413       return false;
 414    }
 415 }
 416
 417 static void
 418 lower_tex_ycbcr(const struct tu_pipeline_layout *layout,
 419                 nir_builder *builder,
 420                 nir_tex_instr *tex)
 421 {
 422    int deref_src_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_deref);
 423    assert(deref_src_idx >= 0);
 424    nir_deref_instr *deref = nir_src_as_deref(tex->src[deref_src_idx].src);
 425
 426    nir_variable *var = nir_deref_instr_get_variable(deref);
 427    const struct tu_descriptor_set_layout *set_layout =
 428       layout->set[var->data.descriptor_set].layout;
 429    const struct tu_descriptor_set_binding_layout *binding =
 430       &set_layout->binding[var->data.binding];
 431    const struct tu_sampler_ycbcr_conversion *ycbcr_samplers =
 432       tu_immutable_ycbcr_samplers(set_layout, binding);
 433
 434    if (!ycbcr_samplers)
 435       return;
 436
 437    /* For the following instructions, we don't apply any change */
 438    if (tex->op == nir_texop_txs ||
 439        tex->op == nir_texop_query_levels ||
 440        tex->op == nir_texop_lod)
 441       return;
 442
 443    assert(tex->texture_index == 0);
 444    unsigned array_index = 0;
 445    if (deref->deref_type != nir_deref_type_var) {
 446       assert(deref->deref_type == nir_deref_type_array);
 447       if (!nir_src_is_const(deref->arr.index))
 448          return;
 449       array_index = nir_src_as_uint(deref->arr.index);
 450       array_index = MIN2(array_index, binding->array_size - 1);
 451    }
 452    const struct tu_sampler_ycbcr_conversion *ycbcr_sampler = ycbcr_samplers + array_index;
 453
 454    if (ycbcr_sampler->ycbcr_model == VK_SAMPLER_YCBCR_MODEL_CONVERSION_RGB_IDENTITY)
 455       return;
 456
 457    builder->cursor = nir_after_instr(&tex->instr);
 458
 459    uint8_t bits = vk_format_get_component_bits(ycbcr_sampler->format,
 460                                                UTIL_FORMAT_COLORSPACE_RGB,
 461                                                PIPE_SWIZZLE_X);
 462    uint32_t bpcs[3] = {bits, bits, bits}; /* TODO: use right bpc for each channel ? */
 463    nir_ssa_def *result = nir_convert_ycbcr_to_rgb(builder,
 464                                                   ycbcr_sampler->ycbcr_model,
 465                                                   ycbcr_sampler->ycbcr_range,
 466                                                   &tex->dest.ssa,
 467                                                   bpcs);
 468    nir_ssa_def_rewrite_uses_after(&tex->dest.ssa, nir_src_for_ssa(result),
 469                                   result->parent_instr);
 470
 471    builder->cursor = nir_before_instr(&tex->instr);
 472 }
 473
 474 static bool
 475 lower_tex(nir_builder *b, nir_tex_instr *tex,
 476           struct tu_shader *shader, const struct tu_pipeline_layout *layout)
 477 {
 478    lower_tex_ycbcr(layout, b, tex);
 479
 480    int sampler_src_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_deref);
 481    if (sampler_src_idx >= 0) {
 482       nir_deref_instr *deref = nir_src_as_deref(tex->src[sampler_src_idx].src);
 483       nir_ssa_def *bindless = build_bindless(b, deref, true, shader, layout);
 484       nir_instr_rewrite_src(&tex->instr, &tex->src[sampler_src_idx].src,
 485                             nir_src_for_ssa(bindless));
 486       tex->src[sampler_src_idx].src_type = nir_tex_src_sampler_handle;
 487    }
 488
 489    int tex_src_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_deref);
 490    if (tex_src_idx >= 0) {
 491       nir_deref_instr *deref = nir_src_as_deref(tex->src[tex_src_idx].src);
 492       nir_ssa_def *bindless = build_bindless(b, deref, false, shader, layout);
 493       nir_instr_rewrite_src(&tex->instr, &tex->src[tex_src_idx].src,
 494                             nir_src_for_ssa(bindless));
 495       tex->src[tex_src_idx].src_type = nir_tex_src_texture_handle;
 496
 497       /* for the input attachment case: */
 498       if (bindless->parent_instr->type != nir_instr_type_intrinsic)
 499          tex->src[tex_src_idx].src_type = nir_tex_src_texture_offset;
 500    }
 501
 502    return true;
 503 }
 504
 505 static bool
 506 lower_impl(nir_function_impl *impl, struct tu_shader *shader,
 507             const struct tu_pipeline_layout *layout)
 508 {
 509    nir_builder b;
 510    nir_builder_init(&b, impl);
 511    bool progress = false;
 512
 513    nir_foreach_block(block, impl) {
 514       nir_foreach_instr_safe(instr, block) {
 515          b.cursor = nir_before_instr(instr);
 516          switch (instr->type) {
 517          case nir_instr_type_tex:
 518             progress |= lower_tex(&b, nir_instr_as_tex(instr), shader, layout);
 519             break;
 520          case nir_instr_type_intrinsic:
 521             progress |= lower_intrinsic(&b, nir_instr_as_intrinsic(instr), shader, layout);
 522             break;
 523          default:
 524             break;
 525          }
 526       }
 527    }
 528
 529    if (progress)
 530       nir_metadata_preserve(impl, nir_metadata_none);
 531    else
 532       nir_metadata_preserve(impl, nir_metadata_all);
 533
 534    return progress;
 535 }
 536
 537
 538 /* Figure out the range of push constants that we're actually going to push to
 539  * the shader, and tell the backend to reserve this range when pushing UBO
 540  * constants.
 541  */
 542
 543 static void
 544 gather_push_constants(nir_shader *shader, struct tu_shader *tu_shader)
 545 {
 546    uint32_t min = UINT32_MAX, max = 0;
 547    nir_foreach_function(function, shader) {
 548       if (!function->impl)
 549          continue;
 550
 551       nir_foreach_block(block, function->impl) {
 552          nir_foreach_instr_safe(instr, block) {
 553             if (instr->type != nir_instr_type_intrinsic)
 554                continue;
 555
 556             nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
 557             if (intrin->intrinsic != nir_intrinsic_load_push_constant)
 558                continue;
 559
 560             uint32_t base = nir_intrinsic_base(intrin);
 561             uint32_t range = nir_intrinsic_range(intrin);
 562             min = MIN2(min, base);
 563             max = MAX2(max, base + range);
 564             break;
 565          }
 566       }
 567    }
 568
 569    if (min >= max) {
 570       tu_shader->push_consts.lo = 0;
 571       tu_shader->push_consts.count = 0;
 572       return;
 573    }
 574
 575    /* CP_LOAD_STATE OFFSET and NUM_UNIT are in units of vec4 (4 dwords),
 576     * however there's an alignment requirement of 4 on OFFSET. Expand the
 577     * range and change units accordingly.
 578     */
 579    tu_shader->push_consts.lo = (min / 16) / 4 * 4;
 580    tu_shader->push_consts.count =
 581       align(max, 16) / 16 - tu_shader->push_consts.lo;
 582 }
 583
 584 static bool
 585 tu_lower_io(nir_shader *shader, struct tu_shader *tu_shader,
 586             const struct tu_pipeline_layout *layout)
 587 {
 588    bool progress = false;
 589
 590    gather_push_constants(shader, tu_shader);
 591
 592    nir_foreach_function(function, shader) {
 593       if (function->impl)
 594          progress |= lower_impl(function->impl, tu_shader, layout);
 595    }
 596
 597    /* Remove now-unused variables so that when we gather the shader info later
 598     * they won't be counted.
 599     */
 600
 601    if (progress)
 602       nir_opt_dce(shader);
 603
 604    progress |=
 605       nir_remove_dead_variables(shader,
 606                                 nir_var_uniform | nir_var_mem_ubo | nir_var_mem_ssbo,
 607                                 NULL);
 608
 609    return progress;
 610 }
 611
 612 static void
 613 shared_type_info(const struct glsl_type *type, unsigned *size, unsigned *align)
 614 {
 615    assert(glsl_type_is_vector_or_scalar(type));
 616
 617    unsigned comp_size =
 618       glsl_type_is_boolean(type) ? 4 : glsl_get_bit_size(type) / 8;
 619    unsigned length = glsl_get_vector_elements(type);
 620    *size = comp_size * length;
 621    *align = 4;
 622 }
 623
 624 static void
 625 tu_gather_xfb_info(nir_shader *nir, struct ir3_stream_output_info *info)
 626 {
 627    nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
 628
 629    if (!xfb)
 630       return;
 631
 632    /* creating a map from VARYING_SLOT_* enums to consecutive index */
 633    uint8_t num_outputs = 0;
 634    uint64_t outputs_written = 0;
 635    for (int i = 0; i < xfb->output_count; i++)
 636       outputs_written |= BITFIELD64_BIT(xfb->outputs[i].location);
 637
 638    uint8_t output_map[VARYING_SLOT_TESS_MAX];
 639    memset(output_map, 0, sizeof(output_map));
 640
 641    for (unsigned attr = 0; attr < VARYING_SLOT_MAX; attr++) {
 642       if (outputs_written & BITFIELD64_BIT(attr))
 643          output_map[attr] = num_outputs++;
 644    }
 645
 646    assert(xfb->output_count < IR3_MAX_SO_OUTPUTS);
 647    info->num_outputs = xfb->output_count;
 648
 649    for (int i = 0; i < IR3_MAX_SO_BUFFERS; i++)
 650       info->stride[i] = xfb->buffers[i].stride / 4;
 651
 652    for (int i = 0; i < xfb->output_count; i++) {
 653       info->output[i].register_index = output_map[xfb->outputs[i].location];
 654       info->output[i].start_component = xfb->outputs[i].component_offset;
 655       info->output[i].num_components =
 656                            util_bitcount(xfb->outputs[i].component_mask);
 657       info->output[i].output_buffer  = xfb->outputs[i].buffer;
 658       info->output[i].dst_offset = xfb->outputs[i].offset / 4;
 659       info->output[i].stream = xfb->buffer_to_stream[xfb->outputs[i].buffer];
 660    }
 661
 662    ralloc_free(xfb);
 663 }
 664
 665 struct tu_shader *
 666 tu_shader_create(struct tu_device *dev,
 667                  gl_shader_stage stage,
 668                  const VkPipelineShaderStageCreateInfo *stage_info,
 669                  struct tu_pipeline_layout *layout,
 670                  const VkAllocationCallbacks *alloc)
 671 {
 672    struct tu_shader *shader;
 673
 674    shader = vk_zalloc2(
 675       &dev->alloc, alloc,
 676       sizeof(*shader),
 677       8, VK_SYSTEM_ALLOCATION_SCOPE_COMMAND);
 678    if (!shader)
 679       return NULL;
 680
 681    nir_shader *nir;
 682    if (stage_info) {
 683       /* translate SPIR-V to NIR */
 684       const struct tu_shader_module *module =
 685          tu_shader_module_from_handle(stage_info->module);
 686       assert(module->code_size % 4 == 0);
 687       nir = tu_spirv_to_nir(
 688          dev->compiler, (const uint32_t *) module->code, module->code_size / 4,
 689          stage, stage_info->pName, stage_info->pSpecializationInfo);
 690    } else {
 691       assert(stage == MESA_SHADER_FRAGMENT);
 692       nir_builder fs_b;
 693       const nir_shader_compiler_options *nir_options =
 694          ir3_get_compiler_options(dev->compiler);
 695       nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, nir_options);
 696       fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
 697       nir = fs_b.shader;
 698    }
 699
 700    if (!nir) {
 701       vk_free2(&dev->alloc, alloc, shader);
 702       return NULL;
 703    }
 704
 705    if (unlikely(dev->physical_device->instance->debug_flags & TU_DEBUG_NIR)) {
 706       fprintf(stderr, "translated nir:\n");
 707       nir_print_shader(nir, stderr);
 708    }
 709
 710    /* multi step inlining procedure */
 711    NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_function_temp);
 712    NIR_PASS_V(nir, nir_lower_returns);
 713    NIR_PASS_V(nir, nir_inline_functions);
 714    NIR_PASS_V(nir, nir_opt_deref);
 715    foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
 716       if (!func->is_entrypoint)
 717          exec_node_remove(&func->node);
 718    }
 719    assert(exec_list_length(&nir->functions) == 1);
 720    NIR_PASS_V(nir, nir_lower_variable_initializers, ~nir_var_function_temp);
 721
 722    /* Split member structs.  We do this before lower_io_to_temporaries so that
 723     * it doesn't lower system values to temporaries by accident.
 724     */
 725    NIR_PASS_V(nir, nir_split_var_copies);
 726    NIR_PASS_V(nir, nir_split_per_member_structs);
 727
 728    NIR_PASS_V(nir, nir_remove_dead_variables,
 729               nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared,
 730               NULL);
 731
 732    /* Gather information for transform feedback.
 733     * This should be called after nir_split_per_member_structs.
 734     * Also needs to be called after nir_remove_dead_variables with varyings,
 735     * so that we could align stream outputs correctly.
 736     */
 737    struct ir3_stream_output_info so_info = {};
 738    if (nir->info.stage == MESA_SHADER_VERTEX ||
 739          nir->info.stage == MESA_SHADER_TESS_EVAL ||
 740          nir->info.stage == MESA_SHADER_GEOMETRY)
 741       tu_gather_xfb_info(nir, &so_info);
 742
 743    NIR_PASS_V(nir, nir_propagate_invariant);
 744
 745    NIR_PASS_V(nir, nir_lower_io_to_temporaries, nir_shader_get_entrypoint(nir), true, true);
 746
 747    NIR_PASS_V(nir, nir_lower_global_vars_to_local);
 748    NIR_PASS_V(nir, nir_split_var_copies);
 749    NIR_PASS_V(nir, nir_lower_var_copies);
 750
 751    NIR_PASS_V(nir, nir_opt_copy_prop_vars);
 752    NIR_PASS_V(nir, nir_opt_combine_stores, nir_var_all);
 753
 754    /* ir3 doesn't support indirect input/output */
 755    /* TODO: We shouldn't perform this lowering pass on gl_TessLevelInner
 756     * and gl_TessLevelOuter. Since the tess levels are actually stored in
 757     * a global BO, they can be directly accessed via stg and ldg.
 758     * nir_lower_indirect_derefs will instead generate a big if-ladder which
 759     * isn't *incorrect* but is much less efficient. */
 760    NIR_PASS_V(nir, nir_lower_indirect_derefs, nir_var_shader_in | nir_var_shader_out);
 761
 762    NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects, false);
 763
 764    nir_assign_io_var_locations(&nir->inputs, &nir->num_inputs, stage);
 765    nir_assign_io_var_locations(&nir->outputs, &nir->num_outputs, stage);
 766
 767    NIR_PASS_V(nir, nir_lower_system_values);
 768    NIR_PASS_V(nir, nir_lower_frexp);
 769
 770    if (stage == MESA_SHADER_FRAGMENT)
 771       NIR_PASS_V(nir, nir_lower_input_attachments, true);
 772
 773    NIR_PASS_V(nir, nir_lower_explicit_io,
 774               nir_var_mem_ubo | nir_var_mem_ssbo,
 775               nir_address_format_vec2_index_32bit_offset);
 776
 777    if (nir->info.stage == MESA_SHADER_COMPUTE) {
 778       NIR_PASS_V(nir, nir_lower_vars_to_explicit_types,
 779                  nir_var_mem_shared, shared_type_info);
 780       NIR_PASS_V(nir, nir_lower_explicit_io,
 781                  nir_var_mem_shared,
 782                  nir_address_format_32bit_offset);
 783    }
 784
 785    NIR_PASS_V(nir, tu_lower_io, shader, layout);
 786
 787    nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
 788
 789    ir3_finalize_nir(dev->compiler, nir);
 790
 791    shader->ir3_shader =
 792       ir3_shader_from_nir(dev->compiler, nir,
 793                           align(shader->push_consts.count, 4),
 794                           &so_info);
 795
 796    return shader;
 797 }
 798
 799 void
 800 tu_shader_destroy(struct tu_device *dev,
 801                   struct tu_shader *shader,
 802                   const VkAllocationCallbacks *alloc)
 803 {
 804    ir3_shader_destroy(shader->ir3_shader);
 805
 806    vk_free2(&dev->alloc, alloc, shader);
 807 }
 808
 809 VkResult
 810 tu_CreateShaderModule(VkDevice _device,
 811                       const VkShaderModuleCreateInfo *pCreateInfo,
 812                       const VkAllocationCallbacks *pAllocator,
 813                       VkShaderModule *pShaderModule)
 814 {
 815    TU_FROM_HANDLE(tu_device, device, _device);
 816    struct tu_shader_module *module;
 817
 818    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
 819    assert(pCreateInfo->flags == 0);
 820    assert(pCreateInfo->codeSize % 4 == 0);
 821
 822    module = vk_alloc2(&device->alloc, pAllocator,
 823                       sizeof(*module) + pCreateInfo->codeSize, 8,
 824                       VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 825    if (module == NULL)
 826       return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
 827
 828    module->code_size = pCreateInfo->codeSize;
 829    memcpy(module->code, pCreateInfo->pCode, pCreateInfo->codeSize);
 830
 831    _mesa_sha1_compute(module->code, module->code_size, module->sha1);
 832
 833    *pShaderModule = tu_shader_module_to_handle(module);
 834
 835    return VK_SUCCESS;
 836 }
 837
 838 void
 839 tu_DestroyShaderModule(VkDevice _device,
 840                        VkShaderModule _module,
 841                        const VkAllocationCallbacks *pAllocator)
 842 {
 843    TU_FROM_HANDLE(tu_device, device, _device);
 844    TU_FROM_HANDLE(tu_shader_module, module, _module);
 845
 846    if (!module)
 847       return;
 848
 849    vk_free2(&device->alloc, pAllocator, module);
 850 }