2 * Copyright © 2019 Google LLC
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include "tu_private.h"
26 #include "spirv/nir_spirv.h"
27 #include "util/mesa-sha1.h"
28 #include "nir/nir_xfb_info.h"
29 #include "nir/nir_vulkan.h"
32 #include "ir3/ir3_nir.h"
35 tu_spirv_to_nir(struct ir3_compiler
*compiler
,
36 const uint32_t *words
,
38 gl_shader_stage stage
,
39 const char *entry_point_name
,
40 const VkSpecializationInfo
*spec_info
)
42 /* TODO these are made-up */
43 const struct spirv_to_nir_options spirv_options
= {
44 .frag_coord_is_sysval
= true,
45 .lower_ubo_ssbo_access_to_offsets
= true,
46 .tess_levels_are_sysvals
= true,
47 .lower_tess_levels_to_vec
= true,
49 .transform_feedback
= true,
53 const nir_shader_compiler_options
*nir_options
=
54 ir3_get_compiler_options(compiler
);
56 /* convert VkSpecializationInfo */
57 struct nir_spirv_specialization
*spec
= NULL
;
58 uint32_t num_spec
= 0;
59 if (spec_info
&& spec_info
->mapEntryCount
) {
60 spec
= calloc(spec_info
->mapEntryCount
, sizeof(*spec
));
64 for (uint32_t i
= 0; i
< spec_info
->mapEntryCount
; i
++) {
65 const VkSpecializationMapEntry
*entry
= &spec_info
->pMapEntries
[i
];
66 const void *data
= spec_info
->pData
+ entry
->offset
;
67 assert(data
+ entry
->size
<= spec_info
->pData
+ spec_info
->dataSize
);
68 spec
[i
].id
= entry
->constantID
;
69 switch (entry
->size
) {
71 spec
[i
].value
.u64
= *(const uint64_t *)data
;
74 spec
[i
].value
.u32
= *(const uint32_t *)data
;
77 spec
[i
].value
.u16
= *(const uint16_t *)data
;
80 spec
[i
].value
.u8
= *(const uint8_t *)data
;
83 assert(!"Invalid spec constant size");
86 spec
[i
].defined_on_module
= false;
89 num_spec
= spec_info
->mapEntryCount
;
93 spirv_to_nir(words
, word_count
, spec
, num_spec
, stage
, entry_point_name
,
94 &spirv_options
, nir_options
);
98 assert(nir
->info
.stage
== stage
);
99 nir_validate_shader(nir
, "after spirv_to_nir");
105 lower_load_push_constant(nir_builder
*b
, nir_intrinsic_instr
*instr
,
106 struct tu_shader
*shader
)
108 nir_intrinsic_instr
*load
=
109 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_load_uniform
);
110 load
->num_components
= instr
->num_components
;
111 uint32_t base
= nir_intrinsic_base(instr
);
112 assert(base
% 4 == 0);
113 assert(base
>= shader
->push_consts
.lo
* 16);
114 base
-= shader
->push_consts
.lo
* 16;
115 nir_intrinsic_set_base(load
, base
/ 4);
117 nir_src_for_ssa(nir_ushr(b
, instr
->src
[0].ssa
, nir_imm_int(b
, 2)));
118 nir_ssa_dest_init(&load
->instr
, &load
->dest
,
119 load
->num_components
, instr
->dest
.ssa
.bit_size
,
120 instr
->dest
.ssa
.name
);
121 nir_builder_instr_insert(b
, &load
->instr
);
122 nir_ssa_def_rewrite_uses(&instr
->dest
.ssa
, nir_src_for_ssa(&load
->dest
.ssa
));
124 nir_instr_remove(&instr
->instr
);
128 lower_vulkan_resource_index(nir_builder
*b
, nir_intrinsic_instr
*instr
,
129 struct tu_shader
*shader
,
130 const struct tu_pipeline_layout
*layout
)
132 nir_ssa_def
*vulkan_idx
= instr
->src
[0].ssa
;
134 unsigned set
= nir_intrinsic_desc_set(instr
);
135 unsigned binding
= nir_intrinsic_binding(instr
);
136 struct tu_descriptor_set_layout
*set_layout
= layout
->set
[set
].layout
;
137 struct tu_descriptor_set_binding_layout
*binding_layout
=
138 &set_layout
->binding
[binding
];
141 shader
->active_desc_sets
|= 1u << set
;
143 switch (binding_layout
->type
) {
144 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
145 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
146 base
= layout
->set
[set
].dynamic_offset_start
+
147 binding_layout
->dynamic_offset_offset
;
151 base
= binding_layout
->offset
/ (4 * A6XX_TEX_CONST_DWORDS
);
155 nir_intrinsic_instr
*bindless
=
156 nir_intrinsic_instr_create(b
->shader
,
157 nir_intrinsic_bindless_resource_ir3
);
158 bindless
->num_components
= 0;
159 nir_ssa_dest_init(&bindless
->instr
, &bindless
->dest
,
161 nir_intrinsic_set_desc_set(bindless
, set
);
162 bindless
->src
[0] = nir_src_for_ssa(nir_iadd(b
, nir_imm_int(b
, base
), vulkan_idx
));
163 nir_builder_instr_insert(b
, &bindless
->instr
);
165 nir_ssa_def_rewrite_uses(&instr
->dest
.ssa
,
166 nir_src_for_ssa(&bindless
->dest
.ssa
));
167 nir_instr_remove(&instr
->instr
);
171 build_bindless(nir_builder
*b
, nir_deref_instr
*deref
, bool is_sampler
,
172 struct tu_shader
*shader
,
173 const struct tu_pipeline_layout
*layout
)
175 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
177 unsigned set
= var
->data
.descriptor_set
;
178 unsigned binding
= var
->data
.binding
;
179 const struct tu_descriptor_set_binding_layout
*bind_layout
=
180 &layout
->set
[set
].layout
->binding
[binding
];
182 /* input attachments use non bindless workaround */
183 if (bind_layout
->type
== VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
) {
184 const struct glsl_type
*glsl_type
= glsl_without_array(var
->type
);
185 uint32_t idx
= var
->data
.index
* 2;
187 b
->shader
->info
.textures_used
|=
188 ((1ull << (bind_layout
->array_size
* 2)) - 1) << (idx
* 2);
190 /* D24S8 workaround: stencil of D24S8 will be sampled as uint */
191 if (glsl_get_sampler_result_type(glsl_type
) == GLSL_TYPE_UINT
)
194 if (deref
->deref_type
== nir_deref_type_var
)
195 return nir_imm_int(b
, idx
);
197 nir_ssa_def
*arr_index
= nir_ssa_for_src(b
, deref
->arr
.index
, 1);
198 return nir_iadd(b
, nir_imm_int(b
, idx
),
199 nir_imul_imm(b
, arr_index
, 2));
202 shader
->active_desc_sets
|= 1u << set
;
204 nir_ssa_def
*desc_offset
;
205 unsigned descriptor_stride
;
207 /* Samplers come second in combined image/sampler descriptors, see
208 * write_combined_image_sampler_descriptor().
210 if (is_sampler
&& bind_layout
->type
==
211 VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
) {
215 nir_imm_int(b
, (bind_layout
->offset
/ (4 * A6XX_TEX_CONST_DWORDS
)) +
217 descriptor_stride
= bind_layout
->size
/ (4 * A6XX_TEX_CONST_DWORDS
);
219 if (deref
->deref_type
!= nir_deref_type_var
) {
220 assert(deref
->deref_type
== nir_deref_type_array
);
222 nir_ssa_def
*arr_index
= nir_ssa_for_src(b
, deref
->arr
.index
, 1);
223 desc_offset
= nir_iadd(b
, desc_offset
,
224 nir_imul_imm(b
, arr_index
, descriptor_stride
));
227 nir_intrinsic_instr
*bindless
=
228 nir_intrinsic_instr_create(b
->shader
,
229 nir_intrinsic_bindless_resource_ir3
);
230 bindless
->num_components
= 0;
231 nir_ssa_dest_init(&bindless
->instr
, &bindless
->dest
,
233 nir_intrinsic_set_desc_set(bindless
, set
);
234 bindless
->src
[0] = nir_src_for_ssa(desc_offset
);
235 nir_builder_instr_insert(b
, &bindless
->instr
);
237 return &bindless
->dest
.ssa
;
241 lower_image_deref(nir_builder
*b
,
242 nir_intrinsic_instr
*instr
, struct tu_shader
*shader
,
243 const struct tu_pipeline_layout
*layout
)
245 nir_deref_instr
*deref
= nir_src_as_deref(instr
->src
[0]);
246 nir_ssa_def
*bindless
= build_bindless(b
, deref
, false, shader
, layout
);
247 nir_rewrite_image_intrinsic(instr
, bindless
, true);
251 lower_intrinsic(nir_builder
*b
, nir_intrinsic_instr
*instr
,
252 struct tu_shader
*shader
,
253 const struct tu_pipeline_layout
*layout
)
255 switch (instr
->intrinsic
) {
256 case nir_intrinsic_load_layer_id
:
257 /* TODO: remove this when layered rendering is implemented */
258 nir_ssa_def_rewrite_uses(&instr
->dest
.ssa
,
259 nir_src_for_ssa(nir_imm_int(b
, 0)));
260 nir_instr_remove(&instr
->instr
);
263 case nir_intrinsic_load_push_constant
:
264 lower_load_push_constant(b
, instr
, shader
);
267 case nir_intrinsic_vulkan_resource_index
:
268 lower_vulkan_resource_index(b
, instr
, shader
, layout
);
271 case nir_intrinsic_image_deref_load
:
272 case nir_intrinsic_image_deref_store
:
273 case nir_intrinsic_image_deref_atomic_add
:
274 case nir_intrinsic_image_deref_atomic_imin
:
275 case nir_intrinsic_image_deref_atomic_umin
:
276 case nir_intrinsic_image_deref_atomic_imax
:
277 case nir_intrinsic_image_deref_atomic_umax
:
278 case nir_intrinsic_image_deref_atomic_and
:
279 case nir_intrinsic_image_deref_atomic_or
:
280 case nir_intrinsic_image_deref_atomic_xor
:
281 case nir_intrinsic_image_deref_atomic_exchange
:
282 case nir_intrinsic_image_deref_atomic_comp_swap
:
283 case nir_intrinsic_image_deref_size
:
284 case nir_intrinsic_image_deref_samples
:
285 lower_image_deref(b
, instr
, shader
, layout
);
294 lower_tex_ycbcr(const struct tu_pipeline_layout
*layout
,
295 nir_builder
*builder
,
298 int deref_src_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_texture_deref
);
299 assert(deref_src_idx
>= 0);
300 nir_deref_instr
*deref
= nir_src_as_deref(tex
->src
[deref_src_idx
].src
);
302 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
303 const struct tu_descriptor_set_layout
*set_layout
=
304 layout
->set
[var
->data
.descriptor_set
].layout
;
305 const struct tu_descriptor_set_binding_layout
*binding
=
306 &set_layout
->binding
[var
->data
.binding
];
307 const struct tu_sampler_ycbcr_conversion
*ycbcr_samplers
=
308 tu_immutable_ycbcr_samplers(set_layout
, binding
);
313 /* For the following instructions, we don't apply any change */
314 if (tex
->op
== nir_texop_txs
||
315 tex
->op
== nir_texop_query_levels
||
316 tex
->op
== nir_texop_lod
)
319 assert(tex
->texture_index
== 0);
320 unsigned array_index
= 0;
321 if (deref
->deref_type
!= nir_deref_type_var
) {
322 assert(deref
->deref_type
== nir_deref_type_array
);
323 if (!nir_src_is_const(deref
->arr
.index
))
325 array_index
= nir_src_as_uint(deref
->arr
.index
);
326 array_index
= MIN2(array_index
, binding
->array_size
- 1);
328 const struct tu_sampler_ycbcr_conversion
*ycbcr_sampler
= ycbcr_samplers
+ array_index
;
330 if (ycbcr_sampler
->ycbcr_model
== VK_SAMPLER_YCBCR_MODEL_CONVERSION_RGB_IDENTITY
)
333 builder
->cursor
= nir_after_instr(&tex
->instr
);
335 uint8_t bits
= vk_format_get_component_bits(ycbcr_sampler
->format
,
336 UTIL_FORMAT_COLORSPACE_RGB
,
338 uint32_t bpcs
[3] = {bits
, bits
, bits
}; /* TODO: use right bpc for each channel ? */
339 nir_ssa_def
*result
= nir_convert_ycbcr_to_rgb(builder
,
340 ycbcr_sampler
->ycbcr_model
,
341 ycbcr_sampler
->ycbcr_range
,
344 nir_ssa_def_rewrite_uses_after(&tex
->dest
.ssa
, nir_src_for_ssa(result
),
345 result
->parent_instr
);
347 builder
->cursor
= nir_before_instr(&tex
->instr
);
351 lower_tex(nir_builder
*b
, nir_tex_instr
*tex
,
352 struct tu_shader
*shader
, const struct tu_pipeline_layout
*layout
)
354 lower_tex_ycbcr(layout
, b
, tex
);
356 int sampler_src_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_sampler_deref
);
357 if (sampler_src_idx
>= 0) {
358 nir_deref_instr
*deref
= nir_src_as_deref(tex
->src
[sampler_src_idx
].src
);
359 nir_ssa_def
*bindless
= build_bindless(b
, deref
, true, shader
, layout
);
360 nir_instr_rewrite_src(&tex
->instr
, &tex
->src
[sampler_src_idx
].src
,
361 nir_src_for_ssa(bindless
));
362 tex
->src
[sampler_src_idx
].src_type
= nir_tex_src_sampler_handle
;
365 int tex_src_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_texture_deref
);
366 if (tex_src_idx
>= 0) {
367 nir_deref_instr
*deref
= nir_src_as_deref(tex
->src
[tex_src_idx
].src
);
368 nir_ssa_def
*bindless
= build_bindless(b
, deref
, false, shader
, layout
);
369 nir_instr_rewrite_src(&tex
->instr
, &tex
->src
[tex_src_idx
].src
,
370 nir_src_for_ssa(bindless
));
371 tex
->src
[tex_src_idx
].src_type
= nir_tex_src_texture_handle
;
373 /* for the input attachment case: */
374 if (bindless
->parent_instr
->type
!= nir_instr_type_intrinsic
)
375 tex
->src
[tex_src_idx
].src_type
= nir_tex_src_texture_offset
;
382 lower_impl(nir_function_impl
*impl
, struct tu_shader
*shader
,
383 const struct tu_pipeline_layout
*layout
)
386 nir_builder_init(&b
, impl
);
387 bool progress
= false;
389 nir_foreach_block(block
, impl
) {
390 nir_foreach_instr_safe(instr
, block
) {
391 b
.cursor
= nir_before_instr(instr
);
392 switch (instr
->type
) {
393 case nir_instr_type_tex
:
394 progress
|= lower_tex(&b
, nir_instr_as_tex(instr
), shader
, layout
);
396 case nir_instr_type_intrinsic
:
397 progress
|= lower_intrinsic(&b
, nir_instr_as_intrinsic(instr
), shader
, layout
);
409 /* Figure out the range of push constants that we're actually going to push to
410 * the shader, and tell the backend to reserve this range when pushing UBO
415 gather_push_constants(nir_shader
*shader
, struct tu_shader
*tu_shader
)
417 uint32_t min
= UINT32_MAX
, max
= 0;
418 nir_foreach_function(function
, shader
) {
422 nir_foreach_block(block
, function
->impl
) {
423 nir_foreach_instr_safe(instr
, block
) {
424 if (instr
->type
!= nir_instr_type_intrinsic
)
427 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
428 if (intrin
->intrinsic
!= nir_intrinsic_load_push_constant
)
431 uint32_t base
= nir_intrinsic_base(intrin
);
432 uint32_t range
= nir_intrinsic_range(intrin
);
433 min
= MIN2(min
, base
);
434 max
= MAX2(max
, base
+ range
);
441 tu_shader
->push_consts
.lo
= 0;
442 tu_shader
->push_consts
.count
= 0;
446 /* CP_LOAD_STATE OFFSET and NUM_UNIT are in units of vec4 (4 dwords),
447 * however there's an alignment requirement of 4 on OFFSET. Expand the
448 * range and change units accordingly.
450 tu_shader
->push_consts
.lo
= (min
/ 16) / 4 * 4;
451 tu_shader
->push_consts
.count
=
452 align(max
, 16) / 16 - tu_shader
->push_consts
.lo
;
456 tu_lower_io(nir_shader
*shader
, struct tu_shader
*tu_shader
,
457 const struct tu_pipeline_layout
*layout
)
459 bool progress
= false;
461 gather_push_constants(shader
, tu_shader
);
463 nir_foreach_function(function
, shader
) {
465 progress
|= lower_impl(function
->impl
, tu_shader
, layout
);
468 /* Remove now-unused variables so that when we gather the shader info later
469 * they won't be counted.
476 nir_remove_dead_variables(shader
,
477 nir_var_uniform
| nir_var_mem_ubo
| nir_var_mem_ssbo
,
484 tu_gather_xfb_info(nir_shader
*nir
, struct ir3_stream_output_info
*info
)
486 nir_xfb_info
*xfb
= nir_gather_xfb_info(nir
, NULL
);
491 /* creating a map from VARYING_SLOT_* enums to consecutive index */
492 uint8_t num_outputs
= 0;
493 uint64_t outputs_written
= 0;
494 for (int i
= 0; i
< xfb
->output_count
; i
++)
495 outputs_written
|= BITFIELD64_BIT(xfb
->outputs
[i
].location
);
497 uint8_t output_map
[VARYING_SLOT_TESS_MAX
];
498 memset(output_map
, 0, sizeof(output_map
));
500 for (unsigned attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
501 if (outputs_written
& BITFIELD64_BIT(attr
))
502 output_map
[attr
] = num_outputs
++;
505 assert(xfb
->output_count
< IR3_MAX_SO_OUTPUTS
);
506 info
->num_outputs
= xfb
->output_count
;
508 for (int i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++)
509 info
->stride
[i
] = xfb
->buffers
[i
].stride
/ 4;
511 for (int i
= 0; i
< xfb
->output_count
; i
++) {
512 info
->output
[i
].register_index
= output_map
[xfb
->outputs
[i
].location
];
513 info
->output
[i
].start_component
= xfb
->outputs
[i
].component_offset
;
514 info
->output
[i
].num_components
=
515 util_bitcount(xfb
->outputs
[i
].component_mask
);
516 info
->output
[i
].output_buffer
= xfb
->outputs
[i
].buffer
;
517 info
->output
[i
].dst_offset
= xfb
->outputs
[i
].offset
/ 4;
518 info
->output
[i
].stream
= xfb
->buffer_to_stream
[xfb
->outputs
[i
].buffer
];
525 tu_shader_create(struct tu_device
*dev
,
526 gl_shader_stage stage
,
527 const VkPipelineShaderStageCreateInfo
*stage_info
,
528 struct tu_pipeline_layout
*layout
,
529 const VkAllocationCallbacks
*alloc
)
531 struct tu_shader
*shader
;
536 8, VK_SYSTEM_ALLOCATION_SCOPE_COMMAND
);
542 /* translate SPIR-V to NIR */
543 const struct tu_shader_module
*module
=
544 tu_shader_module_from_handle(stage_info
->module
);
545 assert(module
->code_size
% 4 == 0);
546 nir
= tu_spirv_to_nir(
547 dev
->compiler
, (const uint32_t *) module
->code
, module
->code_size
/ 4,
548 stage
, stage_info
->pName
, stage_info
->pSpecializationInfo
);
550 assert(stage
== MESA_SHADER_FRAGMENT
);
552 const nir_shader_compiler_options
*nir_options
=
553 ir3_get_compiler_options(dev
->compiler
);
554 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, nir_options
);
555 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "noop_fs");
560 vk_free2(&dev
->alloc
, alloc
, shader
);
564 if (unlikely(dev
->physical_device
->instance
->debug_flags
& TU_DEBUG_NIR
)) {
565 fprintf(stderr
, "translated nir:\n");
566 nir_print_shader(nir
, stderr
);
569 /* multi step inlining procedure */
570 NIR_PASS_V(nir
, nir_lower_variable_initializers
, nir_var_function_temp
);
571 NIR_PASS_V(nir
, nir_lower_returns
);
572 NIR_PASS_V(nir
, nir_inline_functions
);
573 NIR_PASS_V(nir
, nir_opt_deref
);
574 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
575 if (!func
->is_entrypoint
)
576 exec_node_remove(&func
->node
);
578 assert(exec_list_length(&nir
->functions
) == 1);
579 NIR_PASS_V(nir
, nir_lower_variable_initializers
, ~nir_var_function_temp
);
581 /* Split member structs. We do this before lower_io_to_temporaries so that
582 * it doesn't lower system values to temporaries by accident.
584 NIR_PASS_V(nir
, nir_split_var_copies
);
585 NIR_PASS_V(nir
, nir_split_per_member_structs
);
587 NIR_PASS_V(nir
, nir_remove_dead_variables
,
588 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
| nir_var_mem_shared
,
591 /* Gather information for transform feedback.
592 * This should be called after nir_split_per_member_structs.
593 * Also needs to be called after nir_remove_dead_variables with varyings,
594 * so that we could align stream outputs correctly.
596 struct ir3_stream_output_info so_info
= {};
597 if (nir
->info
.stage
== MESA_SHADER_VERTEX
||
598 nir
->info
.stage
== MESA_SHADER_TESS_EVAL
||
599 nir
->info
.stage
== MESA_SHADER_GEOMETRY
)
600 tu_gather_xfb_info(nir
, &so_info
);
602 NIR_PASS_V(nir
, nir_propagate_invariant
);
604 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
, nir_shader_get_entrypoint(nir
), true, true);
606 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
607 NIR_PASS_V(nir
, nir_split_var_copies
);
608 NIR_PASS_V(nir
, nir_lower_var_copies
);
610 NIR_PASS_V(nir
, nir_opt_copy_prop_vars
);
611 NIR_PASS_V(nir
, nir_opt_combine_stores
, nir_var_all
);
613 /* ir3 doesn't support indirect input/output */
614 /* TODO: We shouldn't perform this lowering pass on gl_TessLevelInner
615 * and gl_TessLevelOuter. Since the tess levels are actually stored in
616 * a global BO, they can be directly accessed via stg and ldg.
617 * nir_lower_indirect_derefs will instead generate a big if-ladder which
618 * isn't *incorrect* but is much less efficient. */
619 NIR_PASS_V(nir
, nir_lower_indirect_derefs
, nir_var_shader_in
| nir_var_shader_out
);
621 NIR_PASS_V(nir
, nir_lower_io_arrays_to_elements_no_indirects
, false);
623 nir_assign_io_var_locations(&nir
->inputs
, &nir
->num_inputs
, stage
);
624 nir_assign_io_var_locations(&nir
->outputs
, &nir
->num_outputs
, stage
);
626 NIR_PASS_V(nir
, nir_lower_system_values
);
627 NIR_PASS_V(nir
, nir_lower_frexp
);
629 if (stage
== MESA_SHADER_FRAGMENT
)
630 NIR_PASS_V(nir
, nir_lower_input_attachments
, true);
632 NIR_PASS_V(nir
, tu_lower_io
, shader
, layout
);
634 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
637 ir3_shader_from_nir(dev
->compiler
, nir
,
638 align(shader
->push_consts
.count
, 4),
645 tu_shader_destroy(struct tu_device
*dev
,
646 struct tu_shader
*shader
,
647 const VkAllocationCallbacks
*alloc
)
649 ir3_shader_destroy(shader
->ir3_shader
);
651 vk_free2(&dev
->alloc
, alloc
, shader
);
655 tu_CreateShaderModule(VkDevice _device
,
656 const VkShaderModuleCreateInfo
*pCreateInfo
,
657 const VkAllocationCallbacks
*pAllocator
,
658 VkShaderModule
*pShaderModule
)
660 TU_FROM_HANDLE(tu_device
, device
, _device
);
661 struct tu_shader_module
*module
;
663 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
664 assert(pCreateInfo
->flags
== 0);
665 assert(pCreateInfo
->codeSize
% 4 == 0);
667 module
= vk_alloc2(&device
->alloc
, pAllocator
,
668 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
669 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
671 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
673 module
->code_size
= pCreateInfo
->codeSize
;
674 memcpy(module
->code
, pCreateInfo
->pCode
, pCreateInfo
->codeSize
);
676 _mesa_sha1_compute(module
->code
, module
->code_size
, module
->sha1
);
678 *pShaderModule
= tu_shader_module_to_handle(module
);
684 tu_DestroyShaderModule(VkDevice _device
,
685 VkShaderModule _module
,
686 const VkAllocationCallbacks
*pAllocator
)
688 TU_FROM_HANDLE(tu_device
, device
, _device
);
689 TU_FROM_HANDLE(tu_shader_module
, module
, _module
);
694 vk_free2(&device
->alloc
, pAllocator
, module
);