src/freedreno/vulkan/tu_shader.c

   1 /*
   2  * Copyright © 2019 Google LLC
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "tu_private.h"
  25
  26 #include "spirv/nir_spirv.h"
  27 #include "util/mesa-sha1.h"
  28
  29 #include "ir3/ir3_nir.h"
  30
  31 static nir_shader *
  32 tu_spirv_to_nir(struct ir3_compiler *compiler,
  33                 const uint32_t *words,
  34                 size_t word_count,
  35                 gl_shader_stage stage,
  36                 const char *entry_point_name,
  37                 const VkSpecializationInfo *spec_info)
  38 {
  39    /* TODO these are made-up */
  40    const struct spirv_to_nir_options spirv_options = {
  41       .lower_ubo_ssbo_access_to_offsets = true,
  42       .caps = { false },
  43    };
  44    const nir_shader_compiler_options *nir_options =
  45       ir3_get_compiler_options(compiler);
  46
  47    /* convert VkSpecializationInfo */
  48    struct nir_spirv_specialization *spec = NULL;
  49    uint32_t num_spec = 0;
  50    if (spec_info && spec_info->mapEntryCount) {
  51       spec = malloc(sizeof(*spec) * spec_info->mapEntryCount);
  52       if (!spec)
  53          return NULL;
  54
  55       for (uint32_t i = 0; i < spec_info->mapEntryCount; i++) {
  56          const VkSpecializationMapEntry *entry = &spec_info->pMapEntries[i];
  57          const void *data = spec_info->pData + entry->offset;
  58          assert(data + entry->size <= spec_info->pData + spec_info->dataSize);
  59          spec[i].id = entry->constantID;
  60          if (entry->size == 8)
  61             spec[i].data64 = *(const uint64_t *) data;
  62          else
  63             spec[i].data32 = *(const uint32_t *) data;
  64          spec[i].defined_on_module = false;
  65       }
  66
  67       num_spec = spec_info->mapEntryCount;
  68    }
  69
  70    nir_shader *nir =
  71       spirv_to_nir(words, word_count, spec, num_spec, stage, entry_point_name,
  72                    &spirv_options, nir_options);
  73
  74    free(spec);
  75
  76    assert(nir->info.stage == stage);
  77    nir_validate_shader(nir, "after spirv_to_nir");
  78
  79    return nir;
  80 }
  81
  82 static void
  83 tu_sort_variables_by_location(struct exec_list *variables)
  84 {
  85    struct exec_list sorted;
  86    exec_list_make_empty(&sorted);
  87
  88    nir_foreach_variable_safe(var, variables)
  89    {
  90       exec_node_remove(&var->node);
  91
  92       /* insert the variable into the sorted list */
  93       nir_variable *next = NULL;
  94       nir_foreach_variable(tmp, &sorted)
  95       {
  96          if (var->data.location < tmp->data.location) {
  97             next = tmp;
  98             break;
  99          }
 100       }
 101       if (next)
 102          exec_node_insert_node_before(&next->node, &var->node);
 103       else
 104          exec_list_push_tail(&sorted, &var->node);
 105    }
 106
 107    exec_list_move_nodes_to(&sorted, variables);
 108 }
 109
 110 static unsigned
 111 map_add(struct tu_descriptor_map *map, int set, int binding)
 112 {
 113    unsigned index;
 114    for (index = 0; index < map->num; index++) {
 115       if (set == map->set[index] && binding == map->binding[index])
 116          break;
 117    }
 118
 119    assert(index < ARRAY_SIZE(map->set));
 120
 121    map->set[index] = set;
 122    map->binding[index] = binding;
 123    map->num = MAX2(map->num, index + 1);
 124    return index;
 125 }
 126
 127 static void
 128 lower_tex_src_to_offset(nir_tex_instr *instr, unsigned src_idx,
 129                         struct tu_shader *shader, bool is_sampler)
 130 {
 131    nir_deref_instr *deref =
 132       nir_instr_as_deref(instr->src[src_idx].src.ssa->parent_instr);
 133
 134    if (deref->deref_type != nir_deref_type_var) {
 135       tu_finishme("sampler array");
 136       return;
 137    }
 138
 139    if (is_sampler) {
 140       instr->sampler_index = map_add(&shader->sampler_map,
 141                                      deref->var->data.descriptor_set,
 142                                      deref->var->data.binding);
 143    } else {
 144       instr->texture_index = map_add(&shader->texture_map,
 145                                      deref->var->data.descriptor_set,
 146                                      deref->var->data.binding);
 147       instr->texture_array_size = 1;
 148    }
 149
 150    nir_tex_instr_remove_src(instr, src_idx);
 151 }
 152
 153 static bool
 154 lower_sampler(nir_tex_instr *instr, struct tu_shader *shader)
 155 {
 156    int texture_idx =
 157       nir_tex_instr_src_index(instr, nir_tex_src_texture_deref);
 158
 159    if (texture_idx >= 0)
 160       lower_tex_src_to_offset(instr, texture_idx, shader, false);
 161
 162    int sampler_idx =
 163       nir_tex_instr_src_index(instr, nir_tex_src_sampler_deref);
 164
 165    if (sampler_idx >= 0)
 166       lower_tex_src_to_offset(instr, sampler_idx, shader, true);
 167
 168    if (texture_idx < 0 && sampler_idx < 0)
 169       return false;
 170
 171    return true;
 172 }
 173
 174 static bool
 175 lower_intrinsic(nir_builder *b, nir_intrinsic_instr *instr,
 176                 struct tu_shader *shader)
 177 {
 178    if (instr->intrinsic != nir_intrinsic_vulkan_resource_index)
 179       return false;
 180
 181    nir_const_value *const_val = nir_src_as_const_value(instr->src[0]);
 182    if (!const_val || const_val->u32 != 0) {
 183       tu_finishme("non-zero vulkan_resource_index array index");
 184       return false;
 185    }
 186
 187    if (nir_intrinsic_desc_type(instr) != VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER) {
 188       tu_finishme("non-ubo vulkan_resource_index");
 189       return false;
 190    }
 191
 192    unsigned index = map_add(&shader->ubo_map,
 193                             nir_intrinsic_desc_set(instr),
 194                             nir_intrinsic_binding(instr));
 195
 196    b->cursor = nir_before_instr(&instr->instr);
 197    /* skip index 0 because ir3 treats it differently */
 198    nir_ssa_def_rewrite_uses(&instr->dest.ssa,
 199                             nir_src_for_ssa(nir_imm_int(b, index + 1)));
 200    nir_instr_remove(&instr->instr);
 201
 202    return true;
 203 }
 204
 205 static bool
 206 lower_impl(nir_function_impl *impl, struct tu_shader *shader)
 207 {
 208    nir_builder b;
 209    nir_builder_init(&b, impl);
 210    bool progress = false;
 211
 212    nir_foreach_block(block, impl) {
 213       nir_foreach_instr_safe(instr, block) {
 214          switch (instr->type) {
 215          case nir_instr_type_tex:
 216             progress |= lower_sampler(nir_instr_as_tex(instr), shader);
 217             break;
 218          case nir_instr_type_intrinsic:
 219             progress |= lower_intrinsic(&b, nir_instr_as_intrinsic(instr), shader);
 220             break;
 221          default:
 222             break;
 223          }
 224       }
 225    }
 226
 227    return progress;
 228 }
 229
 230 static bool
 231 tu_lower_io(nir_shader *shader, struct tu_shader *tu_shader)
 232 {
 233    bool progress = false;
 234
 235    nir_foreach_function(function, shader) {
 236       if (function->impl)
 237          progress |= lower_impl(function->impl, tu_shader);
 238    }
 239
 240    return progress;
 241 }
 242
 243 struct tu_shader *
 244 tu_shader_create(struct tu_device *dev,
 245                  gl_shader_stage stage,
 246                  const VkPipelineShaderStageCreateInfo *stage_info,
 247                  const VkAllocationCallbacks *alloc)
 248 {
 249    const struct tu_shader_module *module =
 250       tu_shader_module_from_handle(stage_info->module);
 251    struct tu_shader *shader;
 252
 253    const uint32_t max_variant_count = (stage == MESA_SHADER_VERTEX) ? 2 : 1;
 254    shader = vk_zalloc2(
 255       &dev->alloc, alloc,
 256       sizeof(*shader) + sizeof(struct ir3_shader_variant) * max_variant_count,
 257       8, VK_SYSTEM_ALLOCATION_SCOPE_COMMAND);
 258    if (!shader)
 259       return NULL;
 260
 261    /* translate SPIR-V to NIR */
 262    assert(module->code_size % 4 == 0);
 263    nir_shader *nir = tu_spirv_to_nir(
 264       dev->compiler, (const uint32_t *) module->code, module->code_size / 4,
 265       stage, stage_info->pName, stage_info->pSpecializationInfo);
 266    if (!nir) {
 267       vk_free2(&dev->alloc, alloc, shader);
 268       return NULL;
 269    }
 270
 271    if (unlikely(dev->physical_device->instance->debug_flags & TU_DEBUG_NIR)) {
 272       fprintf(stderr, "translated nir:\n");
 273       nir_print_shader(nir, stderr);
 274    }
 275
 276    /* TODO what needs to happen? */
 277
 278    switch (stage) {
 279    case MESA_SHADER_VERTEX:
 280       tu_sort_variables_by_location(&nir->outputs);
 281       break;
 282    case MESA_SHADER_TESS_CTRL:
 283    case MESA_SHADER_TESS_EVAL:
 284    case MESA_SHADER_GEOMETRY:
 285       tu_sort_variables_by_location(&nir->inputs);
 286       tu_sort_variables_by_location(&nir->outputs);
 287       break;
 288    case MESA_SHADER_FRAGMENT:
 289       tu_sort_variables_by_location(&nir->inputs);
 290       break;
 291    case MESA_SHADER_COMPUTE:
 292       break;
 293    default:
 294       unreachable("invalid gl_shader_stage");
 295       break;
 296    }
 297
 298    nir_assign_var_locations(&nir->inputs, &nir->num_inputs,
 299                             ir3_glsl_type_size);
 300    nir_assign_var_locations(&nir->outputs, &nir->num_outputs,
 301                             ir3_glsl_type_size);
 302    nir_assign_var_locations(&nir->uniforms, &nir->num_uniforms,
 303                             ir3_glsl_type_size);
 304
 305    NIR_PASS_V(nir, nir_lower_system_values);
 306    NIR_PASS_V(nir, nir_lower_frexp);
 307
 308    NIR_PASS_V(nir, tu_lower_io, shader);
 309
 310    NIR_PASS_V(nir, nir_lower_io, nir_var_all, ir3_glsl_type_size, 0);
 311
 312    nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
 313
 314    shader->ir3_shader.compiler = dev->compiler;
 315    shader->ir3_shader.type = stage;
 316    shader->ir3_shader.nir = nir;
 317
 318    return shader;
 319 }
 320
 321 void
 322 tu_shader_destroy(struct tu_device *dev,
 323                   struct tu_shader *shader,
 324                   const VkAllocationCallbacks *alloc)
 325 {
 326    if (shader->ir3_shader.nir)
 327       ralloc_free(shader->ir3_shader.nir);
 328
 329    for (uint32_t i = 0; i < 1 + shader->has_binning_pass; i++) {
 330       if (shader->variants[i].ir)
 331          ir3_destroy(shader->variants[i].ir);
 332    }
 333
 334    if (shader->ir3_shader.const_state.immediates)
 335            free(shader->ir3_shader.const_state.immediates);
 336    if (shader->binary)
 337       free(shader->binary);
 338    if (shader->binning_binary)
 339       free(shader->binning_binary);
 340
 341    vk_free2(&dev->alloc, alloc, shader);
 342 }
 343
 344 void
 345 tu_shader_compile_options_init(
 346    struct tu_shader_compile_options *options,
 347    const VkGraphicsPipelineCreateInfo *pipeline_info)
 348 {
 349    *options = (struct tu_shader_compile_options) {
 350       /* TODO ir3_key */
 351
 352       .optimize = !(pipeline_info->flags &
 353                     VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT),
 354       .include_binning_pass = true,
 355    };
 356 }
 357
 358 static uint32_t *
 359 tu_compile_shader_variant(struct ir3_shader *shader,
 360                           const struct ir3_shader_key *key,
 361                           struct ir3_shader_variant *nonbinning,
 362                           struct ir3_shader_variant *variant)
 363 {
 364    variant->shader = shader;
 365    variant->type = shader->type;
 366    variant->key = *key;
 367    variant->binning_pass = !!nonbinning;
 368    variant->nonbinning = nonbinning;
 369
 370    int ret = ir3_compile_shader_nir(shader->compiler, variant);
 371    if (ret)
 372       return NULL;
 373
 374    /* when assemble fails, we rely on tu_shader_destroy to clean up the
 375     * variant
 376     */
 377    return ir3_shader_assemble(variant, shader->compiler->gpu_id);
 378 }
 379
 380 VkResult
 381 tu_shader_compile(struct tu_device *dev,
 382                   struct tu_shader *shader,
 383                   const struct tu_shader *next_stage,
 384                   const struct tu_shader_compile_options *options,
 385                   const VkAllocationCallbacks *alloc)
 386 {
 387    if (options->optimize) {
 388       /* ignore the key for the first pass of optimization */
 389       ir3_optimize_nir(&shader->ir3_shader, shader->ir3_shader.nir, NULL);
 390
 391       if (unlikely(dev->physical_device->instance->debug_flags &
 392                    TU_DEBUG_NIR)) {
 393          fprintf(stderr, "optimized nir:\n");
 394          nir_print_shader(shader->ir3_shader.nir, stderr);
 395       }
 396    }
 397
 398    shader->binary = tu_compile_shader_variant(
 399       &shader->ir3_shader, &options->key, NULL, &shader->variants[0]);
 400    if (!shader->binary)
 401       return VK_ERROR_OUT_OF_HOST_MEMORY;
 402
 403    /* compile another variant for the binning pass */
 404    if (options->include_binning_pass &&
 405        shader->ir3_shader.type == MESA_SHADER_VERTEX) {
 406       shader->binning_binary = tu_compile_shader_variant(
 407          &shader->ir3_shader, &options->key, &shader->variants[0],
 408          &shader->variants[1]);
 409       if (!shader->binning_binary)
 410          return VK_ERROR_OUT_OF_HOST_MEMORY;
 411
 412       shader->has_binning_pass = true;
 413    }
 414
 415    if (unlikely(dev->physical_device->instance->debug_flags & TU_DEBUG_IR3)) {
 416       fprintf(stderr, "disassembled ir3:\n");
 417       fprintf(stderr, "shader: %s\n",
 418               gl_shader_stage_name(shader->ir3_shader.type));
 419       ir3_shader_disasm(&shader->variants[0], shader->binary, stderr);
 420
 421       if (shader->has_binning_pass) {
 422          fprintf(stderr, "disassembled ir3:\n");
 423          fprintf(stderr, "shader: %s (binning)\n",
 424                  gl_shader_stage_name(shader->ir3_shader.type));
 425          ir3_shader_disasm(&shader->variants[1], shader->binning_binary,
 426                            stderr);
 427       }
 428    }
 429
 430    return VK_SUCCESS;
 431 }
 432
 433 VkResult
 434 tu_CreateShaderModule(VkDevice _device,
 435                       const VkShaderModuleCreateInfo *pCreateInfo,
 436                       const VkAllocationCallbacks *pAllocator,
 437                       VkShaderModule *pShaderModule)
 438 {
 439    TU_FROM_HANDLE(tu_device, device, _device);
 440    struct tu_shader_module *module;
 441
 442    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
 443    assert(pCreateInfo->flags == 0);
 444    assert(pCreateInfo->codeSize % 4 == 0);
 445
 446    module = vk_alloc2(&device->alloc, pAllocator,
 447                       sizeof(*module) + pCreateInfo->codeSize, 8,
 448                       VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 449    if (module == NULL)
 450       return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
 451
 452    module->code_size = pCreateInfo->codeSize;
 453    memcpy(module->code, pCreateInfo->pCode, pCreateInfo->codeSize);
 454
 455    _mesa_sha1_compute(module->code, module->code_size, module->sha1);
 456
 457    *pShaderModule = tu_shader_module_to_handle(module);
 458
 459    return VK_SUCCESS;
 460 }
 461
 462 void
 463 tu_DestroyShaderModule(VkDevice _device,
 464                        VkShaderModule _module,
 465                        const VkAllocationCallbacks *pAllocator)
 466 {
 467    TU_FROM_HANDLE(tu_device, device, _device);
 468    TU_FROM_HANDLE(tu_shader_module, module, _module);
 469
 470    if (!module)
 471       return;
 472
 473    vk_free2(&device->alloc, pAllocator, module);
 474 }