src/freedreno/vulkan/tu_shader.c

   1 /*
   2  * Copyright © 2019 Google LLC
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "tu_private.h"
  25
  26 #include "spirv/nir_spirv.h"
  27 #include "util/mesa-sha1.h"
  28 #include "nir/nir_xfb_info.h"
  29 #include "nir/nir_vulkan.h"
  30 #include "vk_util.h"
  31
  32 #include "ir3/ir3_nir.h"
  33
  34 static nir_shader *
  35 tu_spirv_to_nir(struct ir3_compiler *compiler,
  36                 const uint32_t *words,
  37                 size_t word_count,
  38                 gl_shader_stage stage,
  39                 const char *entry_point_name,
  40                 const VkSpecializationInfo *spec_info)
  41 {
  42    /* TODO these are made-up */
  43    const struct spirv_to_nir_options spirv_options = {
  44       .frag_coord_is_sysval = true,
  45       .lower_ubo_ssbo_access_to_offsets = true,
  46       .caps = {
  47          .transform_feedback = true,
  48          .tessellation = true,
  49          .draw_parameters = true,
  50       },
  51    };
  52    const nir_shader_compiler_options *nir_options =
  53       ir3_get_compiler_options(compiler);
  54
  55    /* convert VkSpecializationInfo */
  56    struct nir_spirv_specialization *spec = NULL;
  57    uint32_t num_spec = 0;
  58    if (spec_info && spec_info->mapEntryCount) {
  59       spec = calloc(spec_info->mapEntryCount, sizeof(*spec));
  60       if (!spec)
  61          return NULL;
  62
  63       for (uint32_t i = 0; i < spec_info->mapEntryCount; i++) {
  64          const VkSpecializationMapEntry *entry = &spec_info->pMapEntries[i];
  65          const void *data = spec_info->pData + entry->offset;
  66          assert(data + entry->size <= spec_info->pData + spec_info->dataSize);
  67          spec[i].id = entry->constantID;
  68          switch (entry->size) {
  69          case 8:
  70             spec[i].value.u64 = *(const uint64_t *)data;
  71             break;
  72          case 4:
  73             spec[i].value.u32 = *(const uint32_t *)data;
  74             break;
  75          case 2:
  76             spec[i].value.u16 = *(const uint16_t *)data;
  77             break;
  78          case 1:
  79             spec[i].value.u8 = *(const uint8_t *)data;
  80             break;
  81          default:
  82             assert(!"Invalid spec constant size");
  83             break;
  84          }
  85          spec[i].defined_on_module = false;
  86       }
  87
  88       num_spec = spec_info->mapEntryCount;
  89    }
  90
  91    nir_shader *nir =
  92       spirv_to_nir(words, word_count, spec, num_spec, stage, entry_point_name,
  93                    &spirv_options, nir_options);
  94
  95    free(spec);
  96
  97    assert(nir->info.stage == stage);
  98    nir_validate_shader(nir, "after spirv_to_nir");
  99
 100    return nir;
 101 }
 102
 103 static void
 104 lower_load_push_constant(nir_builder *b, nir_intrinsic_instr *instr,
 105                          struct tu_shader *shader)
 106 {
 107    nir_intrinsic_instr *load =
 108       nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_uniform);
 109    load->num_components = instr->num_components;
 110    uint32_t base = nir_intrinsic_base(instr);
 111    assert(base % 4 == 0);
 112    assert(base >= shader->push_consts.lo * 16);
 113    base -= shader->push_consts.lo * 16;
 114    nir_intrinsic_set_base(load, base / 4);
 115    load->src[0] =
 116       nir_src_for_ssa(nir_ushr(b, instr->src[0].ssa, nir_imm_int(b, 2)));
 117    nir_ssa_dest_init(&load->instr, &load->dest,
 118                      load->num_components, instr->dest.ssa.bit_size,
 119                      instr->dest.ssa.name);
 120    nir_builder_instr_insert(b, &load->instr);
 121    nir_ssa_def_rewrite_uses(&instr->dest.ssa, nir_src_for_ssa(&load->dest.ssa));
 122
 123    nir_instr_remove(&instr->instr);
 124 }
 125
 126 static void
 127 lower_vulkan_resource_index(nir_builder *b, nir_intrinsic_instr *instr,
 128                             struct tu_shader *shader,
 129                             const struct tu_pipeline_layout *layout)
 130 {
 131    nir_ssa_def *vulkan_idx = instr->src[0].ssa;
 132
 133    unsigned set = nir_intrinsic_desc_set(instr);
 134    unsigned binding = nir_intrinsic_binding(instr);
 135    struct tu_descriptor_set_layout *set_layout = layout->set[set].layout;
 136    struct tu_descriptor_set_binding_layout *binding_layout =
 137       &set_layout->binding[binding];
 138    uint32_t base;
 139
 140    shader->active_desc_sets |= 1u << set;
 141
 142    switch (binding_layout->type) {
 143    case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
 144    case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
 145       base = layout->set[set].dynamic_offset_start +
 146          binding_layout->dynamic_offset_offset;
 147       set = MAX_SETS;
 148       break;
 149    default:
 150       base = binding_layout->offset / (4 * A6XX_TEX_CONST_DWORDS);
 151       break;
 152    }
 153
 154    nir_intrinsic_instr *bindless =
 155       nir_intrinsic_instr_create(b->shader,
 156                                  nir_intrinsic_bindless_resource_ir3);
 157    bindless->num_components = 0;
 158    nir_ssa_dest_init(&bindless->instr, &bindless->dest,
 159                      1, 32, NULL);
 160    nir_intrinsic_set_desc_set(bindless, set);
 161    bindless->src[0] = nir_src_for_ssa(nir_iadd(b, nir_imm_int(b, base), vulkan_idx));
 162    nir_builder_instr_insert(b, &bindless->instr);
 163
 164    nir_ssa_def_rewrite_uses(&instr->dest.ssa,
 165                             nir_src_for_ssa(&bindless->dest.ssa));
 166    nir_instr_remove(&instr->instr);
 167 }
 168
 169 static nir_ssa_def *
 170 build_bindless(nir_builder *b, nir_deref_instr *deref, bool is_sampler,
 171                struct tu_shader *shader,
 172                const struct tu_pipeline_layout *layout)
 173 {
 174    nir_variable *var = nir_deref_instr_get_variable(deref);
 175
 176    unsigned set = var->data.descriptor_set;
 177    unsigned binding = var->data.binding;
 178    const struct tu_descriptor_set_binding_layout *bind_layout =
 179       &layout->set[set].layout->binding[binding];
 180
 181    /* input attachments use non bindless workaround */
 182    if (bind_layout->type == VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT) {
 183       const struct glsl_type *glsl_type = glsl_without_array(var->type);
 184       uint32_t idx = var->data.index * 2;
 185
 186       b->shader->info.textures_used |=
 187          ((1ull << (bind_layout->array_size * 2)) - 1) << (idx * 2);
 188
 189       /* D24S8 workaround: stencil of D24S8 will be sampled as uint */
 190       if (glsl_get_sampler_result_type(glsl_type) == GLSL_TYPE_UINT)
 191          idx += 1;
 192
 193       if (deref->deref_type == nir_deref_type_var)
 194          return nir_imm_int(b, idx);
 195
 196       nir_ssa_def *arr_index = nir_ssa_for_src(b, deref->arr.index, 1);
 197       return nir_iadd(b, nir_imm_int(b, idx),
 198                       nir_imul_imm(b, arr_index, 2));
 199    }
 200
 201    shader->active_desc_sets |= 1u << set;
 202
 203    nir_ssa_def *desc_offset;
 204    unsigned descriptor_stride;
 205    unsigned offset = 0;
 206    /* Samplers come second in combined image/sampler descriptors, see
 207       * write_combined_image_sampler_descriptor().
 208       */
 209    if (is_sampler && bind_layout->type ==
 210          VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER) {
 211       offset = 1;
 212    }
 213    desc_offset =
 214       nir_imm_int(b, (bind_layout->offset / (4 * A6XX_TEX_CONST_DWORDS)) +
 215                   offset);
 216    descriptor_stride = bind_layout->size / (4 * A6XX_TEX_CONST_DWORDS);
 217
 218    if (deref->deref_type != nir_deref_type_var) {
 219       assert(deref->deref_type == nir_deref_type_array);
 220
 221       nir_ssa_def *arr_index = nir_ssa_for_src(b, deref->arr.index, 1);
 222       desc_offset = nir_iadd(b, desc_offset,
 223                              nir_imul_imm(b, arr_index, descriptor_stride));
 224    }
 225
 226    nir_intrinsic_instr *bindless =
 227       nir_intrinsic_instr_create(b->shader,
 228                                  nir_intrinsic_bindless_resource_ir3);
 229    bindless->num_components = 0;
 230    nir_ssa_dest_init(&bindless->instr, &bindless->dest,
 231                      1, 32, NULL);
 232    nir_intrinsic_set_desc_set(bindless, set);
 233    bindless->src[0] = nir_src_for_ssa(desc_offset);
 234    nir_builder_instr_insert(b, &bindless->instr);
 235
 236    return &bindless->dest.ssa;
 237 }
 238
 239 static void
 240 lower_image_deref(nir_builder *b,
 241                   nir_intrinsic_instr *instr, struct tu_shader *shader,
 242                   const struct tu_pipeline_layout *layout)
 243 {
 244    nir_deref_instr *deref = nir_src_as_deref(instr->src[0]);
 245    nir_ssa_def *bindless = build_bindless(b, deref, false, shader, layout);
 246    nir_rewrite_image_intrinsic(instr, bindless, true);
 247 }
 248
 249 static bool
 250 lower_intrinsic(nir_builder *b, nir_intrinsic_instr *instr,
 251                 struct tu_shader *shader,
 252                 const struct tu_pipeline_layout *layout)
 253 {
 254    switch (instr->intrinsic) {
 255    case nir_intrinsic_load_layer_id:
 256       /* TODO: remove this when layered rendering is implemented */
 257       nir_ssa_def_rewrite_uses(&instr->dest.ssa,
 258                                nir_src_for_ssa(nir_imm_int(b, 0)));
 259       nir_instr_remove(&instr->instr);
 260       return true;
 261
 262    case nir_intrinsic_load_push_constant:
 263       lower_load_push_constant(b, instr, shader);
 264       return true;
 265
 266    case nir_intrinsic_vulkan_resource_index:
 267       lower_vulkan_resource_index(b, instr, shader, layout);
 268       return true;
 269
 270    case nir_intrinsic_image_deref_load:
 271    case nir_intrinsic_image_deref_store:
 272    case nir_intrinsic_image_deref_atomic_add:
 273    case nir_intrinsic_image_deref_atomic_imin:
 274    case nir_intrinsic_image_deref_atomic_umin:
 275    case nir_intrinsic_image_deref_atomic_imax:
 276    case nir_intrinsic_image_deref_atomic_umax:
 277    case nir_intrinsic_image_deref_atomic_and:
 278    case nir_intrinsic_image_deref_atomic_or:
 279    case nir_intrinsic_image_deref_atomic_xor:
 280    case nir_intrinsic_image_deref_atomic_exchange:
 281    case nir_intrinsic_image_deref_atomic_comp_swap:
 282    case nir_intrinsic_image_deref_size:
 283    case nir_intrinsic_image_deref_samples:
 284       lower_image_deref(b, instr, shader, layout);
 285       return true;
 286
 287    default:
 288       return false;
 289    }
 290 }
 291
 292 static void
 293 lower_tex_ycbcr(const struct tu_pipeline_layout *layout,
 294                 nir_builder *builder,
 295                 nir_tex_instr *tex)
 296 {
 297    int deref_src_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_deref);
 298    assert(deref_src_idx >= 0);
 299    nir_deref_instr *deref = nir_src_as_deref(tex->src[deref_src_idx].src);
 300
 301    nir_variable *var = nir_deref_instr_get_variable(deref);
 302    const struct tu_descriptor_set_layout *set_layout =
 303       layout->set[var->data.descriptor_set].layout;
 304    const struct tu_descriptor_set_binding_layout *binding =
 305       &set_layout->binding[var->data.binding];
 306    const struct tu_sampler_ycbcr_conversion *ycbcr_samplers =
 307       tu_immutable_ycbcr_samplers(set_layout, binding);
 308
 309    if (!ycbcr_samplers)
 310       return;
 311
 312    /* For the following instructions, we don't apply any change */
 313    if (tex->op == nir_texop_txs ||
 314        tex->op == nir_texop_query_levels ||
 315        tex->op == nir_texop_lod)
 316       return;
 317
 318    assert(tex->texture_index == 0);
 319    unsigned array_index = 0;
 320    if (deref->deref_type != nir_deref_type_var) {
 321       assert(deref->deref_type == nir_deref_type_array);
 322       if (!nir_src_is_const(deref->arr.index))
 323          return;
 324       array_index = nir_src_as_uint(deref->arr.index);
 325       array_index = MIN2(array_index, binding->array_size - 1);
 326    }
 327    const struct tu_sampler_ycbcr_conversion *ycbcr_sampler = ycbcr_samplers + array_index;
 328
 329    if (ycbcr_sampler->ycbcr_model == VK_SAMPLER_YCBCR_MODEL_CONVERSION_RGB_IDENTITY)
 330       return;
 331
 332    builder->cursor = nir_after_instr(&tex->instr);
 333
 334    uint8_t bits = vk_format_get_component_bits(ycbcr_sampler->format,
 335                                                UTIL_FORMAT_COLORSPACE_RGB,
 336                                                PIPE_SWIZZLE_X);
 337    uint32_t bpcs[3] = {bits, bits, bits}; /* TODO: use right bpc for each channel ? */
 338    nir_ssa_def *result = nir_convert_ycbcr_to_rgb(builder,
 339                                                   ycbcr_sampler->ycbcr_model,
 340                                                   ycbcr_sampler->ycbcr_range,
 341                                                   &tex->dest.ssa,
 342                                                   bpcs);
 343    nir_ssa_def_rewrite_uses_after(&tex->dest.ssa, nir_src_for_ssa(result),
 344                                   result->parent_instr);
 345
 346    builder->cursor = nir_before_instr(&tex->instr);
 347 }
 348
 349 static bool
 350 lower_tex(nir_builder *b, nir_tex_instr *tex,
 351           struct tu_shader *shader, const struct tu_pipeline_layout *layout)
 352 {
 353    lower_tex_ycbcr(layout, b, tex);
 354
 355    int sampler_src_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_deref);
 356    if (sampler_src_idx >= 0) {
 357       nir_deref_instr *deref = nir_src_as_deref(tex->src[sampler_src_idx].src);
 358       nir_ssa_def *bindless = build_bindless(b, deref, true, shader, layout);
 359       nir_instr_rewrite_src(&tex->instr, &tex->src[sampler_src_idx].src,
 360                             nir_src_for_ssa(bindless));
 361       tex->src[sampler_src_idx].src_type = nir_tex_src_sampler_handle;
 362    }
 363
 364    int tex_src_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_deref);
 365    if (tex_src_idx >= 0) {
 366       nir_deref_instr *deref = nir_src_as_deref(tex->src[tex_src_idx].src);
 367       nir_ssa_def *bindless = build_bindless(b, deref, false, shader, layout);
 368       nir_instr_rewrite_src(&tex->instr, &tex->src[tex_src_idx].src,
 369                             nir_src_for_ssa(bindless));
 370       tex->src[tex_src_idx].src_type = nir_tex_src_texture_handle;
 371
 372       /* for the input attachment case: */
 373       if (bindless->parent_instr->type != nir_instr_type_intrinsic)
 374          tex->src[tex_src_idx].src_type = nir_tex_src_texture_offset;
 375    }
 376
 377    return true;
 378 }
 379
 380 static bool
 381 lower_impl(nir_function_impl *impl, struct tu_shader *shader,
 382             const struct tu_pipeline_layout *layout)
 383 {
 384    nir_builder b;
 385    nir_builder_init(&b, impl);
 386    bool progress = false;
 387
 388    nir_foreach_block(block, impl) {
 389       nir_foreach_instr_safe(instr, block) {
 390          b.cursor = nir_before_instr(instr);
 391          switch (instr->type) {
 392          case nir_instr_type_tex:
 393             progress |= lower_tex(&b, nir_instr_as_tex(instr), shader, layout);
 394             break;
 395          case nir_instr_type_intrinsic:
 396             progress |= lower_intrinsic(&b, nir_instr_as_intrinsic(instr), shader, layout);
 397             break;
 398          default:
 399             break;
 400          }
 401       }
 402    }
 403
 404    return progress;
 405 }
 406
 407
 408 /* Figure out the range of push constants that we're actually going to push to
 409  * the shader, and tell the backend to reserve this range when pushing UBO
 410  * constants.
 411  */
 412
 413 static void
 414 gather_push_constants(nir_shader *shader, struct tu_shader *tu_shader)
 415 {
 416    uint32_t min = UINT32_MAX, max = 0;
 417    nir_foreach_function(function, shader) {
 418       if (!function->impl)
 419          continue;
 420
 421       nir_foreach_block(block, function->impl) {
 422          nir_foreach_instr_safe(instr, block) {
 423             if (instr->type != nir_instr_type_intrinsic)
 424                continue;
 425
 426             nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
 427             if (intrin->intrinsic != nir_intrinsic_load_push_constant)
 428                continue;
 429
 430             uint32_t base = nir_intrinsic_base(intrin);
 431             uint32_t range = nir_intrinsic_range(intrin);
 432             min = MIN2(min, base);
 433             max = MAX2(max, base + range);
 434             break;
 435          }
 436       }
 437    }
 438
 439    if (min >= max) {
 440       tu_shader->push_consts.lo = 0;
 441       tu_shader->push_consts.count = 0;
 442       return;
 443    }
 444
 445    /* CP_LOAD_STATE OFFSET and NUM_UNIT are in units of vec4 (4 dwords),
 446     * however there's an alignment requirement of 4 on OFFSET. Expand the
 447     * range and change units accordingly.
 448     */
 449    tu_shader->push_consts.lo = (min / 16) / 4 * 4;
 450    tu_shader->push_consts.count =
 451       align(max, 16) / 16 - tu_shader->push_consts.lo;
 452 }
 453
 454 static bool
 455 tu_lower_io(nir_shader *shader, struct tu_shader *tu_shader,
 456             const struct tu_pipeline_layout *layout)
 457 {
 458    bool progress = false;
 459
 460    gather_push_constants(shader, tu_shader);
 461
 462    nir_foreach_function(function, shader) {
 463       if (function->impl)
 464          progress |= lower_impl(function->impl, tu_shader, layout);
 465    }
 466
 467    /* Remove now-unused variables so that when we gather the shader info later
 468     * they won't be counted.
 469     */
 470
 471    if (progress)
 472       nir_opt_dce(shader);
 473
 474    progress |=
 475       nir_remove_dead_variables(shader,
 476                                 nir_var_uniform | nir_var_mem_ubo | nir_var_mem_ssbo,
 477                                 NULL);
 478
 479    return progress;
 480 }
 481
 482 static void
 483 tu_gather_xfb_info(nir_shader *nir, struct ir3_stream_output_info *info)
 484 {
 485    nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
 486
 487    if (!xfb)
 488       return;
 489
 490    /* creating a map from VARYING_SLOT_* enums to consecutive index */
 491    uint8_t num_outputs = 0;
 492    uint64_t outputs_written = 0;
 493    for (int i = 0; i < xfb->output_count; i++)
 494       outputs_written |= BITFIELD64_BIT(xfb->outputs[i].location);
 495
 496    uint8_t output_map[VARYING_SLOT_TESS_MAX];
 497    memset(output_map, 0, sizeof(output_map));
 498
 499    for (unsigned attr = 0; attr < VARYING_SLOT_MAX; attr++) {
 500       if (outputs_written & BITFIELD64_BIT(attr))
 501          output_map[attr] = num_outputs++;
 502    }
 503
 504    assert(xfb->output_count < IR3_MAX_SO_OUTPUTS);
 505    info->num_outputs = xfb->output_count;
 506
 507    for (int i = 0; i < IR3_MAX_SO_BUFFERS; i++)
 508       info->stride[i] = xfb->buffers[i].stride / 4;
 509
 510    for (int i = 0; i < xfb->output_count; i++) {
 511       info->output[i].register_index = output_map[xfb->outputs[i].location];
 512       info->output[i].start_component = xfb->outputs[i].component_offset;
 513       info->output[i].num_components =
 514                            util_bitcount(xfb->outputs[i].component_mask);
 515       info->output[i].output_buffer  = xfb->outputs[i].buffer;
 516       info->output[i].dst_offset = xfb->outputs[i].offset / 4;
 517       info->output[i].stream = xfb->buffer_to_stream[xfb->outputs[i].buffer];
 518    }
 519
 520    ralloc_free(xfb);
 521 }
 522
 523 struct tu_shader *
 524 tu_shader_create(struct tu_device *dev,
 525                  gl_shader_stage stage,
 526                  const VkPipelineShaderStageCreateInfo *stage_info,
 527                  struct tu_pipeline_layout *layout,
 528                  const VkAllocationCallbacks *alloc)
 529 {
 530    struct tu_shader *shader;
 531
 532    shader = vk_zalloc2(
 533       &dev->alloc, alloc,
 534       sizeof(*shader),
 535       8, VK_SYSTEM_ALLOCATION_SCOPE_COMMAND);
 536    if (!shader)
 537       return NULL;
 538
 539    nir_shader *nir;
 540    if (stage_info) {
 541       /* translate SPIR-V to NIR */
 542       const struct tu_shader_module *module =
 543          tu_shader_module_from_handle(stage_info->module);
 544       assert(module->code_size % 4 == 0);
 545       nir = tu_spirv_to_nir(
 546          dev->compiler, (const uint32_t *) module->code, module->code_size / 4,
 547          stage, stage_info->pName, stage_info->pSpecializationInfo);
 548    } else {
 549       assert(stage == MESA_SHADER_FRAGMENT);
 550       nir_builder fs_b;
 551       const nir_shader_compiler_options *nir_options =
 552          ir3_get_compiler_options(dev->compiler);
 553       nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, nir_options);
 554       fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
 555       nir = fs_b.shader;
 556    }
 557
 558    if (!nir) {
 559       vk_free2(&dev->alloc, alloc, shader);
 560       return NULL;
 561    }
 562
 563    if (unlikely(dev->physical_device->instance->debug_flags & TU_DEBUG_NIR)) {
 564       fprintf(stderr, "translated nir:\n");
 565       nir_print_shader(nir, stderr);
 566    }
 567
 568    /* multi step inlining procedure */
 569    NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_function_temp);
 570    NIR_PASS_V(nir, nir_lower_returns);
 571    NIR_PASS_V(nir, nir_inline_functions);
 572    NIR_PASS_V(nir, nir_opt_deref);
 573    foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
 574       if (!func->is_entrypoint)
 575          exec_node_remove(&func->node);
 576    }
 577    assert(exec_list_length(&nir->functions) == 1);
 578    NIR_PASS_V(nir, nir_lower_variable_initializers, ~nir_var_function_temp);
 579
 580    /* Split member structs.  We do this before lower_io_to_temporaries so that
 581     * it doesn't lower system values to temporaries by accident.
 582     */
 583    NIR_PASS_V(nir, nir_split_var_copies);
 584    NIR_PASS_V(nir, nir_split_per_member_structs);
 585
 586    NIR_PASS_V(nir, nir_remove_dead_variables,
 587               nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared,
 588               NULL);
 589
 590    /* Gather information for transform feedback.
 591     * This should be called after nir_split_per_member_structs.
 592     * Also needs to be called after nir_remove_dead_variables with varyings,
 593     * so that we could align stream outputs correctly.
 594     */
 595    struct ir3_stream_output_info so_info = {};
 596    if (nir->info.stage == MESA_SHADER_VERTEX ||
 597          nir->info.stage == MESA_SHADER_TESS_EVAL ||
 598          nir->info.stage == MESA_SHADER_GEOMETRY)
 599       tu_gather_xfb_info(nir, &so_info);
 600
 601    NIR_PASS_V(nir, nir_propagate_invariant);
 602
 603    NIR_PASS_V(nir, nir_lower_io_to_temporaries, nir_shader_get_entrypoint(nir), true, true);
 604
 605    NIR_PASS_V(nir, nir_lower_global_vars_to_local);
 606    NIR_PASS_V(nir, nir_split_var_copies);
 607    NIR_PASS_V(nir, nir_lower_var_copies);
 608
 609    NIR_PASS_V(nir, nir_opt_copy_prop_vars);
 610    NIR_PASS_V(nir, nir_opt_combine_stores, nir_var_all);
 611
 612    /* ir3 doesn't support indirect input/output */
 613    /* TODO: We shouldn't perform this lowering pass on gl_TessLevelInner
 614     * and gl_TessLevelOuter. Since the tess levels are actually stored in
 615     * a global BO, they can be directly accessed via stg and ldg.
 616     * nir_lower_indirect_derefs will instead generate a big if-ladder which
 617     * isn't *incorrect* but is much less efficient. */
 618    NIR_PASS_V(nir, nir_lower_indirect_derefs, nir_var_shader_in | nir_var_shader_out);
 619
 620    NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects, false);
 621
 622    nir_assign_io_var_locations(&nir->inputs, &nir->num_inputs, stage);
 623    nir_assign_io_var_locations(&nir->outputs, &nir->num_outputs, stage);
 624
 625    NIR_PASS_V(nir, nir_lower_system_values);
 626    NIR_PASS_V(nir, nir_lower_frexp);
 627
 628    if (stage == MESA_SHADER_FRAGMENT)
 629       NIR_PASS_V(nir, nir_lower_input_attachments, true);
 630
 631    NIR_PASS_V(nir, tu_lower_io, shader, layout);
 632
 633    nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
 634
 635    ir3_finalize_nir(dev->compiler, nir);
 636
 637    shader->ir3_shader =
 638       ir3_shader_from_nir(dev->compiler, nir,
 639                           align(shader->push_consts.count, 4),
 640                           &so_info);
 641
 642    return shader;
 643 }
 644
 645 void
 646 tu_shader_destroy(struct tu_device *dev,
 647                   struct tu_shader *shader,
 648                   const VkAllocationCallbacks *alloc)
 649 {
 650    ir3_shader_destroy(shader->ir3_shader);
 651
 652    vk_free2(&dev->alloc, alloc, shader);
 653 }
 654
 655 VkResult
 656 tu_CreateShaderModule(VkDevice _device,
 657                       const VkShaderModuleCreateInfo *pCreateInfo,
 658                       const VkAllocationCallbacks *pAllocator,
 659                       VkShaderModule *pShaderModule)
 660 {
 661    TU_FROM_HANDLE(tu_device, device, _device);
 662    struct tu_shader_module *module;
 663
 664    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
 665    assert(pCreateInfo->flags == 0);
 666    assert(pCreateInfo->codeSize % 4 == 0);
 667
 668    module = vk_alloc2(&device->alloc, pAllocator,
 669                       sizeof(*module) + pCreateInfo->codeSize, 8,
 670                       VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 671    if (module == NULL)
 672       return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
 673
 674    module->code_size = pCreateInfo->codeSize;
 675    memcpy(module->code, pCreateInfo->pCode, pCreateInfo->codeSize);
 676
 677    _mesa_sha1_compute(module->code, module->code_size, module->sha1);
 678
 679    *pShaderModule = tu_shader_module_to_handle(module);
 680
 681    return VK_SUCCESS;
 682 }
 683
 684 void
 685 tu_DestroyShaderModule(VkDevice _device,
 686                        VkShaderModule _module,
 687                        const VkAllocationCallbacks *pAllocator)
 688 {
 689    TU_FROM_HANDLE(tu_device, device, _device);
 690    TU_FROM_HANDLE(tu_shader_module, module, _module);
 691
 692    if (!module)
 693       return;
 694
 695    vk_free2(&device->alloc, pAllocator, module);
 696 }