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11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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21 * DEALINGS IN THE SOFTWARE.
24 #include "tu_private.h"
26 #include "spirv/nir_spirv.h"
27 #include "util/mesa-sha1.h"
29 #include "ir3/ir3_nir.h"
32 tu_spirv_to_nir(struct ir3_compiler
*compiler
,
33 const uint32_t *words
,
35 gl_shader_stage stage
,
36 const char *entry_point_name
,
37 const VkSpecializationInfo
*spec_info
)
39 /* TODO these are made-up */
40 const struct spirv_to_nir_options spirv_options
= {
41 .frag_coord_is_sysval
= true,
42 .lower_ubo_ssbo_access_to_offsets
= true,
45 const nir_shader_compiler_options
*nir_options
=
46 ir3_get_compiler_options(compiler
);
48 /* convert VkSpecializationInfo */
49 struct nir_spirv_specialization
*spec
= NULL
;
50 uint32_t num_spec
= 0;
51 if (spec_info
&& spec_info
->mapEntryCount
) {
52 spec
= malloc(sizeof(*spec
) * spec_info
->mapEntryCount
);
56 for (uint32_t i
= 0; i
< spec_info
->mapEntryCount
; i
++) {
57 const VkSpecializationMapEntry
*entry
= &spec_info
->pMapEntries
[i
];
58 const void *data
= spec_info
->pData
+ entry
->offset
;
59 assert(data
+ entry
->size
<= spec_info
->pData
+ spec_info
->dataSize
);
60 spec
[i
].id
= entry
->constantID
;
62 spec
[i
].data64
= *(const uint64_t *) data
;
64 spec
[i
].data32
= *(const uint32_t *) data
;
65 spec
[i
].defined_on_module
= false;
68 num_spec
= spec_info
->mapEntryCount
;
72 spirv_to_nir(words
, word_count
, spec
, num_spec
, stage
, entry_point_name
,
73 &spirv_options
, nir_options
);
77 assert(nir
->info
.stage
== stage
);
78 nir_validate_shader(nir
, "after spirv_to_nir");
84 tu_sort_variables_by_location(struct exec_list
*variables
)
86 struct exec_list sorted
;
87 exec_list_make_empty(&sorted
);
89 nir_foreach_variable_safe(var
, variables
)
91 exec_node_remove(&var
->node
);
93 /* insert the variable into the sorted list */
94 nir_variable
*next
= NULL
;
95 nir_foreach_variable(tmp
, &sorted
)
97 if (var
->data
.location
< tmp
->data
.location
) {
103 exec_node_insert_node_before(&next
->node
, &var
->node
);
105 exec_list_push_tail(&sorted
, &var
->node
);
108 exec_list_move_nodes_to(&sorted
, variables
);
112 map_add(struct tu_descriptor_map
*map
, int set
, int binding
)
115 for (index
= 0; index
< map
->num
; index
++) {
116 if (set
== map
->set
[index
] && binding
== map
->binding
[index
])
120 assert(index
< ARRAY_SIZE(map
->set
));
122 map
->set
[index
] = set
;
123 map
->binding
[index
] = binding
;
124 map
->num
= MAX2(map
->num
, index
+ 1);
129 lower_tex_src_to_offset(nir_builder
*b
, nir_tex_instr
*instr
, unsigned src_idx
,
130 struct tu_shader
*shader
)
132 nir_ssa_def
*index
= NULL
;
133 unsigned base_index
= 0;
134 unsigned array_elements
= 1;
135 nir_tex_src
*src
= &instr
->src
[src_idx
];
136 bool is_sampler
= src
->src_type
== nir_tex_src_sampler_deref
;
138 /* We compute first the offsets */
139 nir_deref_instr
*deref
= nir_instr_as_deref(src
->src
.ssa
->parent_instr
);
140 while (deref
->deref_type
!= nir_deref_type_var
) {
141 assert(deref
->parent
.is_ssa
);
142 nir_deref_instr
*parent
=
143 nir_instr_as_deref(deref
->parent
.ssa
->parent_instr
);
145 assert(deref
->deref_type
== nir_deref_type_array
);
147 if (nir_src_is_const(deref
->arr
.index
) && index
== NULL
) {
148 /* We're still building a direct index */
149 base_index
+= nir_src_as_uint(deref
->arr
.index
) * array_elements
;
152 /* We used to be direct but not anymore */
153 index
= nir_imm_int(b
, base_index
);
157 index
= nir_iadd(b
, index
,
158 nir_imul(b
, nir_imm_int(b
, array_elements
),
159 nir_ssa_for_src(b
, deref
->arr
.index
, 1)));
162 array_elements
*= glsl_get_length(parent
->type
);
168 index
= nir_umin(b
, index
, nir_imm_int(b
, array_elements
- 1));
170 /* We have the offsets, we apply them, rewriting the source or removing
174 nir_instr_rewrite_src(&instr
->instr
, &src
->src
,
175 nir_src_for_ssa(index
));
177 src
->src_type
= is_sampler
?
178 nir_tex_src_sampler_offset
:
179 nir_tex_src_texture_offset
;
181 instr
->texture_array_size
= array_elements
;
183 nir_tex_instr_remove_src(instr
, src_idx
);
186 if (array_elements
> 1)
187 tu_finishme("texture/sampler array");
190 instr
->sampler_index
= map_add(&shader
->sampler_map
,
191 deref
->var
->data
.descriptor_set
,
192 deref
->var
->data
.binding
);
193 instr
->sampler_index
+= base_index
;
195 instr
->texture_index
= map_add(&shader
->texture_map
,
196 deref
->var
->data
.descriptor_set
,
197 deref
->var
->data
.binding
);
198 instr
->texture_index
+= base_index
;
199 instr
->texture_array_size
= array_elements
;
204 lower_sampler(nir_builder
*b
, nir_tex_instr
*instr
, struct tu_shader
*shader
)
207 nir_tex_instr_src_index(instr
, nir_tex_src_texture_deref
);
209 if (texture_idx
>= 0)
210 lower_tex_src_to_offset(b
, instr
, texture_idx
, shader
);
213 nir_tex_instr_src_index(instr
, nir_tex_src_sampler_deref
);
215 if (sampler_idx
>= 0)
216 lower_tex_src_to_offset(b
, instr
, sampler_idx
, shader
);
218 if (texture_idx
< 0 && sampler_idx
< 0)
225 lower_intrinsic(nir_builder
*b
, nir_intrinsic_instr
*instr
,
226 struct tu_shader
*shader
)
228 if (instr
->intrinsic
!= nir_intrinsic_vulkan_resource_index
)
231 nir_const_value
*const_val
= nir_src_as_const_value(instr
->src
[0]);
232 if (!const_val
|| const_val
->u32
!= 0) {
233 tu_finishme("non-zero vulkan_resource_index array index");
237 if (nir_intrinsic_desc_type(instr
) != VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
238 tu_finishme("non-ubo vulkan_resource_index");
242 unsigned index
= map_add(&shader
->ubo_map
,
243 nir_intrinsic_desc_set(instr
),
244 nir_intrinsic_binding(instr
));
246 b
->cursor
= nir_before_instr(&instr
->instr
);
247 /* skip index 0 because ir3 treats it differently */
248 nir_ssa_def_rewrite_uses(&instr
->dest
.ssa
,
249 nir_src_for_ssa(nir_imm_int(b
, index
+ 1)));
250 nir_instr_remove(&instr
->instr
);
256 lower_impl(nir_function_impl
*impl
, struct tu_shader
*shader
)
259 nir_builder_init(&b
, impl
);
260 bool progress
= false;
262 nir_foreach_block(block
, impl
) {
263 nir_foreach_instr_safe(instr
, block
) {
264 switch (instr
->type
) {
265 case nir_instr_type_tex
:
266 progress
|= lower_sampler(&b
, nir_instr_as_tex(instr
), shader
);
268 case nir_instr_type_intrinsic
:
269 progress
|= lower_intrinsic(&b
, nir_instr_as_intrinsic(instr
), shader
);
281 tu_lower_io(nir_shader
*shader
, struct tu_shader
*tu_shader
)
283 bool progress
= false;
285 nir_foreach_function(function
, shader
) {
287 progress
|= lower_impl(function
->impl
, tu_shader
);
294 tu_shader_create(struct tu_device
*dev
,
295 gl_shader_stage stage
,
296 const VkPipelineShaderStageCreateInfo
*stage_info
,
297 const VkAllocationCallbacks
*alloc
)
299 const struct tu_shader_module
*module
=
300 tu_shader_module_from_handle(stage_info
->module
);
301 struct tu_shader
*shader
;
303 const uint32_t max_variant_count
= (stage
== MESA_SHADER_VERTEX
) ? 2 : 1;
306 sizeof(*shader
) + sizeof(struct ir3_shader_variant
) * max_variant_count
,
307 8, VK_SYSTEM_ALLOCATION_SCOPE_COMMAND
);
311 /* translate SPIR-V to NIR */
312 assert(module
->code_size
% 4 == 0);
313 nir_shader
*nir
= tu_spirv_to_nir(
314 dev
->compiler
, (const uint32_t *) module
->code
, module
->code_size
/ 4,
315 stage
, stage_info
->pName
, stage_info
->pSpecializationInfo
);
317 vk_free2(&dev
->alloc
, alloc
, shader
);
321 if (unlikely(dev
->physical_device
->instance
->debug_flags
& TU_DEBUG_NIR
)) {
322 fprintf(stderr
, "translated nir:\n");
323 nir_print_shader(nir
, stderr
);
326 /* TODO what needs to happen? */
329 case MESA_SHADER_VERTEX
:
330 tu_sort_variables_by_location(&nir
->outputs
);
332 case MESA_SHADER_TESS_CTRL
:
333 case MESA_SHADER_TESS_EVAL
:
334 case MESA_SHADER_GEOMETRY
:
335 tu_sort_variables_by_location(&nir
->inputs
);
336 tu_sort_variables_by_location(&nir
->outputs
);
338 case MESA_SHADER_FRAGMENT
:
339 tu_sort_variables_by_location(&nir
->inputs
);
341 case MESA_SHADER_COMPUTE
:
344 unreachable("invalid gl_shader_stage");
348 nir_assign_var_locations(&nir
->inputs
, &nir
->num_inputs
,
350 nir_assign_var_locations(&nir
->outputs
, &nir
->num_outputs
,
352 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
,
355 NIR_PASS_V(nir
, nir_opt_copy_prop_vars
);
357 NIR_PASS_V(nir
, nir_lower_system_values
);
358 NIR_PASS_V(nir
, nir_lower_frexp
);
360 NIR_PASS_V(nir
, tu_lower_io
, shader
);
362 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, ir3_glsl_type_size
, 0);
364 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
366 shader
->ir3_shader
.compiler
= dev
->compiler
;
367 shader
->ir3_shader
.type
= stage
;
368 shader
->ir3_shader
.nir
= nir
;
374 tu_shader_destroy(struct tu_device
*dev
,
375 struct tu_shader
*shader
,
376 const VkAllocationCallbacks
*alloc
)
378 if (shader
->ir3_shader
.nir
)
379 ralloc_free(shader
->ir3_shader
.nir
);
381 for (uint32_t i
= 0; i
< 1 + shader
->has_binning_pass
; i
++) {
382 if (shader
->variants
[i
].ir
)
383 ir3_destroy(shader
->variants
[i
].ir
);
386 if (shader
->ir3_shader
.const_state
.immediates
)
387 free(shader
->ir3_shader
.const_state
.immediates
);
389 free(shader
->binary
);
390 if (shader
->binning_binary
)
391 free(shader
->binning_binary
);
393 vk_free2(&dev
->alloc
, alloc
, shader
);
397 tu_shader_compile_options_init(
398 struct tu_shader_compile_options
*options
,
399 const VkGraphicsPipelineCreateInfo
*pipeline_info
)
401 *options
= (struct tu_shader_compile_options
) {
404 .optimize
= !(pipeline_info
->flags
&
405 VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
),
406 .include_binning_pass
= true,
411 tu_compile_shader_variant(struct ir3_shader
*shader
,
412 const struct ir3_shader_key
*key
,
413 struct ir3_shader_variant
*nonbinning
,
414 struct ir3_shader_variant
*variant
)
416 variant
->shader
= shader
;
417 variant
->type
= shader
->type
;
419 variant
->binning_pass
= !!nonbinning
;
420 variant
->nonbinning
= nonbinning
;
422 int ret
= ir3_compile_shader_nir(shader
->compiler
, variant
);
426 /* when assemble fails, we rely on tu_shader_destroy to clean up the
429 return ir3_shader_assemble(variant
, shader
->compiler
->gpu_id
);
433 tu_shader_compile(struct tu_device
*dev
,
434 struct tu_shader
*shader
,
435 const struct tu_shader
*next_stage
,
436 const struct tu_shader_compile_options
*options
,
437 const VkAllocationCallbacks
*alloc
)
439 if (options
->optimize
) {
440 /* ignore the key for the first pass of optimization */
441 ir3_optimize_nir(&shader
->ir3_shader
, shader
->ir3_shader
.nir
, NULL
);
443 if (unlikely(dev
->physical_device
->instance
->debug_flags
&
445 fprintf(stderr
, "optimized nir:\n");
446 nir_print_shader(shader
->ir3_shader
.nir
, stderr
);
450 shader
->binary
= tu_compile_shader_variant(
451 &shader
->ir3_shader
, &options
->key
, NULL
, &shader
->variants
[0]);
453 return VK_ERROR_OUT_OF_HOST_MEMORY
;
455 /* compile another variant for the binning pass */
456 if (options
->include_binning_pass
&&
457 shader
->ir3_shader
.type
== MESA_SHADER_VERTEX
) {
458 shader
->binning_binary
= tu_compile_shader_variant(
459 &shader
->ir3_shader
, &options
->key
, &shader
->variants
[0],
460 &shader
->variants
[1]);
461 if (!shader
->binning_binary
)
462 return VK_ERROR_OUT_OF_HOST_MEMORY
;
464 shader
->has_binning_pass
= true;
467 if (unlikely(dev
->physical_device
->instance
->debug_flags
& TU_DEBUG_IR3
)) {
468 fprintf(stderr
, "disassembled ir3:\n");
469 fprintf(stderr
, "shader: %s\n",
470 gl_shader_stage_name(shader
->ir3_shader
.type
));
471 ir3_shader_disasm(&shader
->variants
[0], shader
->binary
, stderr
);
473 if (shader
->has_binning_pass
) {
474 fprintf(stderr
, "disassembled ir3:\n");
475 fprintf(stderr
, "shader: %s (binning)\n",
476 gl_shader_stage_name(shader
->ir3_shader
.type
));
477 ir3_shader_disasm(&shader
->variants
[1], shader
->binning_binary
,
486 tu_CreateShaderModule(VkDevice _device
,
487 const VkShaderModuleCreateInfo
*pCreateInfo
,
488 const VkAllocationCallbacks
*pAllocator
,
489 VkShaderModule
*pShaderModule
)
491 TU_FROM_HANDLE(tu_device
, device
, _device
);
492 struct tu_shader_module
*module
;
494 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
495 assert(pCreateInfo
->flags
== 0);
496 assert(pCreateInfo
->codeSize
% 4 == 0);
498 module
= vk_alloc2(&device
->alloc
, pAllocator
,
499 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
500 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
502 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
504 module
->code_size
= pCreateInfo
->codeSize
;
505 memcpy(module
->code
, pCreateInfo
->pCode
, pCreateInfo
->codeSize
);
507 _mesa_sha1_compute(module
->code
, module
->code_size
, module
->sha1
);
509 *pShaderModule
= tu_shader_module_to_handle(module
);
515 tu_DestroyShaderModule(VkDevice _device
,
516 VkShaderModule _module
,
517 const VkAllocationCallbacks
*pAllocator
)
519 TU_FROM_HANDLE(tu_device
, device
, _device
);
520 TU_FROM_HANDLE(tu_shader_module
, module
, _module
);
525 vk_free2(&device
->alloc
, pAllocator
, module
);