src/freedreno/vulkan/tu_shader.c

   1 /*
   2  * Copyright © 2019 Google LLC
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "tu_private.h"
  25
  26 #include "spirv/nir_spirv.h"
  27 #include "util/mesa-sha1.h"
  28
  29 #include "ir3/ir3_nir.h"
  30
  31 static nir_shader *
  32 tu_spirv_to_nir(struct ir3_compiler *compiler,
  33                 const uint32_t *words,
  34                 size_t word_count,
  35                 gl_shader_stage stage,
  36                 const char *entry_point_name,
  37                 const VkSpecializationInfo *spec_info)
  38 {
  39    /* TODO these are made-up */
  40    const struct spirv_to_nir_options spirv_options = {
  41       .frag_coord_is_sysval = true,
  42       .lower_ubo_ssbo_access_to_offsets = true,
  43       .caps = { false },
  44    };
  45    const nir_shader_compiler_options *nir_options =
  46       ir3_get_compiler_options(compiler);
  47
  48    /* convert VkSpecializationInfo */
  49    struct nir_spirv_specialization *spec = NULL;
  50    uint32_t num_spec = 0;
  51    if (spec_info && spec_info->mapEntryCount) {
  52       spec = malloc(sizeof(*spec) * spec_info->mapEntryCount);
  53       if (!spec)
  54          return NULL;
  55
  56       for (uint32_t i = 0; i < spec_info->mapEntryCount; i++) {
  57          const VkSpecializationMapEntry *entry = &spec_info->pMapEntries[i];
  58          const void *data = spec_info->pData + entry->offset;
  59          assert(data + entry->size <= spec_info->pData + spec_info->dataSize);
  60          spec[i].id = entry->constantID;
  61          if (entry->size == 8)
  62             spec[i].data64 = *(const uint64_t *) data;
  63          else
  64             spec[i].data32 = *(const uint32_t *) data;
  65          spec[i].defined_on_module = false;
  66       }
  67
  68       num_spec = spec_info->mapEntryCount;
  69    }
  70
  71    nir_shader *nir =
  72       spirv_to_nir(words, word_count, spec, num_spec, stage, entry_point_name,
  73                    &spirv_options, nir_options);
  74
  75    free(spec);
  76
  77    assert(nir->info.stage == stage);
  78    nir_validate_shader(nir, "after spirv_to_nir");
  79
  80    return nir;
  81 }
  82
  83 static void
  84 tu_sort_variables_by_location(struct exec_list *variables)
  85 {
  86    struct exec_list sorted;
  87    exec_list_make_empty(&sorted);
  88
  89    nir_foreach_variable_safe(var, variables)
  90    {
  91       exec_node_remove(&var->node);
  92
  93       /* insert the variable into the sorted list */
  94       nir_variable *next = NULL;
  95       nir_foreach_variable(tmp, &sorted)
  96       {
  97          if (var->data.location < tmp->data.location) {
  98             next = tmp;
  99             break;
 100          }
 101       }
 102       if (next)
 103          exec_node_insert_node_before(&next->node, &var->node);
 104       else
 105          exec_list_push_tail(&sorted, &var->node);
 106    }
 107
 108    exec_list_move_nodes_to(&sorted, variables);
 109 }
 110
 111 static unsigned
 112 map_add(struct tu_descriptor_map *map, int set, int binding, int value,
 113         int array_size)
 114 {
 115    unsigned index = 0;
 116    for (unsigned i = 0; i < map->num; i++) {
 117       if (set == map->set[i] && binding == map->binding[i]) {
 118          assert(value == map->value[i]);
 119          assert(array_size == map->array_size[i]);
 120          return index;
 121       }
 122       index += map->array_size[i];
 123    }
 124
 125    assert(index == map->num_desc);
 126
 127    map->set[map->num] = set;
 128    map->binding[map->num] = binding;
 129    map->value[map->num] = value;
 130    map->array_size[map->num] = array_size;
 131    map->num++;
 132    map->num_desc += array_size;
 133
 134    return index;
 135 }
 136
 137 static void
 138 lower_tex_src_to_offset(nir_builder *b, nir_tex_instr *instr, unsigned src_idx,
 139                         struct tu_shader *shader,
 140                         const struct tu_pipeline_layout *layout)
 141 {
 142    nir_ssa_def *index = NULL;
 143    unsigned base_index = 0;
 144    unsigned array_elements = 1;
 145    nir_tex_src *src = &instr->src[src_idx];
 146    bool is_sampler = src->src_type == nir_tex_src_sampler_deref;
 147
 148    /* We compute first the offsets */
 149    nir_deref_instr *deref = nir_instr_as_deref(src->src.ssa->parent_instr);
 150    while (deref->deref_type != nir_deref_type_var) {
 151       assert(deref->parent.is_ssa);
 152       nir_deref_instr *parent =
 153          nir_instr_as_deref(deref->parent.ssa->parent_instr);
 154
 155       assert(deref->deref_type == nir_deref_type_array);
 156
 157       if (nir_src_is_const(deref->arr.index) && index == NULL) {
 158          /* We're still building a direct index */
 159          base_index += nir_src_as_uint(deref->arr.index) * array_elements;
 160       } else {
 161          if (index == NULL) {
 162             /* We used to be direct but not anymore */
 163             index = nir_imm_int(b, base_index);
 164             base_index = 0;
 165          }
 166
 167          index = nir_iadd(b, index,
 168                           nir_imul(b, nir_imm_int(b, array_elements),
 169                                    nir_ssa_for_src(b, deref->arr.index, 1)));
 170       }
 171
 172       array_elements *= glsl_get_length(parent->type);
 173
 174       deref = parent;
 175    }
 176
 177    if (index)
 178       index = nir_umin(b, index, nir_imm_int(b, array_elements - 1));
 179
 180    /* We have the offsets, we apply them, rewriting the source or removing
 181     * instr if needed
 182     */
 183    if (index) {
 184       nir_instr_rewrite_src(&instr->instr, &src->src,
 185                             nir_src_for_ssa(index));
 186
 187       src->src_type = is_sampler ?
 188          nir_tex_src_sampler_offset :
 189          nir_tex_src_texture_offset;
 190
 191       instr->texture_array_size = array_elements;
 192    } else {
 193       nir_tex_instr_remove_src(instr, src_idx);
 194    }
 195
 196    uint32_t set = deref->var->data.descriptor_set;
 197    uint32_t binding = deref->var->data.binding;
 198    struct tu_descriptor_set_layout *set_layout = layout->set[set].layout;
 199    struct tu_descriptor_set_binding_layout *binding_layout =
 200       &set_layout->binding[binding];
 201
 202    int desc_index = map_add(is_sampler ?
 203                             &shader->sampler_map : &shader->texture_map,
 204                             deref->var->data.descriptor_set,
 205                             deref->var->data.binding,
 206                             deref->var->data.index,
 207                             binding_layout->array_size) + base_index;
 208    if (is_sampler)
 209       instr->sampler_index = desc_index;
 210    else
 211       instr->texture_index = desc_index;
 212 }
 213
 214 static bool
 215 lower_sampler(nir_builder *b, nir_tex_instr *instr, struct tu_shader *shader,
 216                 const struct tu_pipeline_layout *layout)
 217 {
 218    int texture_idx =
 219       nir_tex_instr_src_index(instr, nir_tex_src_texture_deref);
 220
 221    if (texture_idx >= 0)
 222       lower_tex_src_to_offset(b, instr, texture_idx, shader, layout);
 223
 224    int sampler_idx =
 225       nir_tex_instr_src_index(instr, nir_tex_src_sampler_deref);
 226
 227    if (sampler_idx >= 0)
 228       lower_tex_src_to_offset(b, instr, sampler_idx, shader, layout);
 229
 230    if (texture_idx < 0 && sampler_idx < 0)
 231       return false;
 232
 233    return true;
 234 }
 235
 236 static void
 237 lower_load_push_constant(nir_builder *b, nir_intrinsic_instr *instr,
 238                          struct tu_shader *shader)
 239 {
 240    /* note: ir3 wants load_ubo, not load_uniform */
 241    assert(nir_intrinsic_base(instr) == 0);
 242
 243    nir_intrinsic_instr *load =
 244       nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_ubo);
 245    load->num_components = instr->num_components;
 246    load->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
 247    load->src[1] = instr->src[0];
 248    nir_ssa_dest_init(&load->instr, &load->dest,
 249                      load->num_components, instr->dest.ssa.bit_size,
 250                      instr->dest.ssa.name);
 251    nir_builder_instr_insert(b, &load->instr);
 252    nir_ssa_def_rewrite_uses(&instr->dest.ssa, nir_src_for_ssa(&load->dest.ssa));
 253
 254    nir_instr_remove(&instr->instr);
 255 }
 256
 257 static void
 258 lower_vulkan_resource_index(nir_builder *b, nir_intrinsic_instr *instr,
 259                             struct tu_shader *shader,
 260                             const struct tu_pipeline_layout *layout)
 261 {
 262    nir_const_value *const_val = nir_src_as_const_value(instr->src[0]);
 263
 264    unsigned set = nir_intrinsic_desc_set(instr);
 265    unsigned binding = nir_intrinsic_binding(instr);
 266    struct tu_descriptor_set_layout *set_layout = layout->set[set].layout;
 267    struct tu_descriptor_set_binding_layout *binding_layout =
 268       &set_layout->binding[binding];
 269    unsigned index = 0;
 270
 271    switch (nir_intrinsic_desc_type(instr)) {
 272    case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
 273    case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
 274       if (!const_val || const_val->u32 != 0)
 275          tu_finishme("non-zero vulkan_resource_index array index");
 276       /* skip index 0 which is used for push constants */
 277       index = map_add(&shader->ubo_map, set, binding, 0,
 278                       binding_layout->array_size) + 1;
 279       break;
 280    case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
 281    case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
 282       if (!const_val)
 283          tu_finishme("non-constant vulkan_resource_index array index");
 284       index = map_add(&shader->ssbo_map, set, binding, 0,
 285                       binding_layout->array_size);
 286       index += const_val->u32;
 287       break;
 288    default:
 289       tu_finishme("unsupported desc_type for vulkan_resource_index");
 290       break;
 291    }
 292
 293    nir_ssa_def_rewrite_uses(&instr->dest.ssa,
 294                             nir_src_for_ssa(nir_imm_int(b, index)));
 295    nir_instr_remove(&instr->instr);
 296 }
 297
 298 static void
 299 add_image_deref_mapping(nir_intrinsic_instr *instr, struct tu_shader *shader,
 300                 const struct tu_pipeline_layout *layout)
 301 {
 302    nir_deref_instr *deref = nir_src_as_deref(instr->src[0]);
 303    nir_variable *var = nir_deref_instr_get_variable(deref);
 304
 305    uint32_t set = var->data.descriptor_set;
 306    uint32_t binding = var->data.binding;
 307    struct tu_descriptor_set_layout *set_layout = layout->set[set].layout;
 308    struct tu_descriptor_set_binding_layout *binding_layout =
 309       &set_layout->binding[binding];
 310
 311    var->data.driver_location =
 312       map_add(&shader->image_map, set, binding, var->data.index,
 313               binding_layout->array_size);
 314 }
 315
 316 static bool
 317 lower_intrinsic(nir_builder *b, nir_intrinsic_instr *instr,
 318                 struct tu_shader *shader,
 319                 const struct tu_pipeline_layout *layout)
 320 {
 321    switch (instr->intrinsic) {
 322    case nir_intrinsic_load_layer_id:
 323       /* TODO: remove this when layered rendering is implemented */
 324       nir_ssa_def_rewrite_uses(&instr->dest.ssa,
 325                                nir_src_for_ssa(nir_imm_int(b, 0)));
 326       nir_instr_remove(&instr->instr);
 327       return true;
 328
 329    case nir_intrinsic_load_push_constant:
 330       lower_load_push_constant(b, instr, shader);
 331       return true;
 332
 333    case nir_intrinsic_vulkan_resource_index:
 334       lower_vulkan_resource_index(b, instr, shader, layout);
 335       return true;
 336
 337    case nir_intrinsic_image_deref_load:
 338    case nir_intrinsic_image_deref_store:
 339    case nir_intrinsic_image_deref_atomic_add:
 340    case nir_intrinsic_image_deref_atomic_imin:
 341    case nir_intrinsic_image_deref_atomic_umin:
 342    case nir_intrinsic_image_deref_atomic_imax:
 343    case nir_intrinsic_image_deref_atomic_umax:
 344    case nir_intrinsic_image_deref_atomic_and:
 345    case nir_intrinsic_image_deref_atomic_or:
 346    case nir_intrinsic_image_deref_atomic_xor:
 347    case nir_intrinsic_image_deref_atomic_exchange:
 348    case nir_intrinsic_image_deref_atomic_comp_swap:
 349    case nir_intrinsic_image_deref_size:
 350    case nir_intrinsic_image_deref_samples:
 351    case nir_intrinsic_image_deref_load_param_intel:
 352    case nir_intrinsic_image_deref_load_raw_intel:
 353    case nir_intrinsic_image_deref_store_raw_intel:
 354       add_image_deref_mapping(instr, shader, layout);
 355       return true;
 356
 357    default:
 358       return false;
 359    }
 360 }
 361
 362 static bool
 363 lower_impl(nir_function_impl *impl, struct tu_shader *shader,
 364             const struct tu_pipeline_layout *layout)
 365 {
 366    nir_builder b;
 367    nir_builder_init(&b, impl);
 368    bool progress = false;
 369
 370    nir_foreach_block(block, impl) {
 371       nir_foreach_instr_safe(instr, block) {
 372          b.cursor = nir_before_instr(instr);
 373          switch (instr->type) {
 374          case nir_instr_type_tex:
 375             progress |= lower_sampler(&b, nir_instr_as_tex(instr), shader, layout);
 376             break;
 377          case nir_instr_type_intrinsic:
 378             progress |= lower_intrinsic(&b, nir_instr_as_intrinsic(instr), shader, layout);
 379             break;
 380          default:
 381             break;
 382          }
 383       }
 384    }
 385
 386    return progress;
 387 }
 388
 389 static bool
 390 tu_lower_io(nir_shader *shader, struct tu_shader *tu_shader,
 391             const struct tu_pipeline_layout *layout)
 392 {
 393    bool progress = false;
 394
 395    nir_foreach_function(function, shader) {
 396       if (function->impl)
 397          progress |= lower_impl(function->impl, tu_shader, layout);
 398    }
 399
 400    /* spirv_to_nir produces num_ssbos equal to the number of SSBO-containing
 401     * variables, while ir3 wants the number of descriptors (like the gallium
 402     * path).
 403     */
 404    shader->info.num_ssbos = tu_shader->ssbo_map.num_desc;
 405
 406    return progress;
 407 }
 408
 409 struct tu_shader *
 410 tu_shader_create(struct tu_device *dev,
 411                  gl_shader_stage stage,
 412                  const VkPipelineShaderStageCreateInfo *stage_info,
 413                  struct tu_pipeline_layout *layout,
 414                  const VkAllocationCallbacks *alloc)
 415 {
 416    const struct tu_shader_module *module =
 417       tu_shader_module_from_handle(stage_info->module);
 418    struct tu_shader *shader;
 419
 420    const uint32_t max_variant_count = (stage == MESA_SHADER_VERTEX) ? 2 : 1;
 421    shader = vk_zalloc2(
 422       &dev->alloc, alloc,
 423       sizeof(*shader) + sizeof(struct ir3_shader_variant) * max_variant_count,
 424       8, VK_SYSTEM_ALLOCATION_SCOPE_COMMAND);
 425    if (!shader)
 426       return NULL;
 427
 428    /* translate SPIR-V to NIR */
 429    assert(module->code_size % 4 == 0);
 430    nir_shader *nir = tu_spirv_to_nir(
 431       dev->compiler, (const uint32_t *) module->code, module->code_size / 4,
 432       stage, stage_info->pName, stage_info->pSpecializationInfo);
 433    if (!nir) {
 434       vk_free2(&dev->alloc, alloc, shader);
 435       return NULL;
 436    }
 437
 438    if (unlikely(dev->physical_device->instance->debug_flags & TU_DEBUG_NIR)) {
 439       fprintf(stderr, "translated nir:\n");
 440       nir_print_shader(nir, stderr);
 441    }
 442
 443    /* multi step inlining procedure */
 444    NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_function_temp);
 445    NIR_PASS_V(nir, nir_lower_returns);
 446    NIR_PASS_V(nir, nir_inline_functions);
 447    NIR_PASS_V(nir, nir_opt_deref);
 448    foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
 449       if (!func->is_entrypoint)
 450          exec_node_remove(&func->node);
 451    }
 452    assert(exec_list_length(&nir->functions) == 1);
 453    NIR_PASS_V(nir, nir_lower_constant_initializers, ~nir_var_function_temp);
 454
 455    /* Split member structs.  We do this before lower_io_to_temporaries so that
 456     * it doesn't lower system values to temporaries by accident.
 457     */
 458    NIR_PASS_V(nir, nir_split_var_copies);
 459    NIR_PASS_V(nir, nir_split_per_member_structs);
 460
 461    NIR_PASS_V(nir, nir_remove_dead_variables,
 462               nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared);
 463
 464    NIR_PASS_V(nir, nir_propagate_invariant);
 465
 466    NIR_PASS_V(nir, nir_lower_io_to_temporaries, nir_shader_get_entrypoint(nir), true, true);
 467
 468    NIR_PASS_V(nir, nir_lower_global_vars_to_local);
 469    NIR_PASS_V(nir, nir_split_var_copies);
 470    NIR_PASS_V(nir, nir_lower_var_copies);
 471
 472    NIR_PASS_V(nir, nir_opt_copy_prop_vars);
 473    NIR_PASS_V(nir, nir_opt_combine_stores, nir_var_all);
 474
 475    /* ir3 doesn't support indirect input/output */
 476    NIR_PASS_V(nir, nir_lower_indirect_derefs, nir_var_shader_in | nir_var_shader_out);
 477
 478    switch (stage) {
 479    case MESA_SHADER_VERTEX:
 480       tu_sort_variables_by_location(&nir->outputs);
 481       break;
 482    case MESA_SHADER_TESS_CTRL:
 483    case MESA_SHADER_TESS_EVAL:
 484    case MESA_SHADER_GEOMETRY:
 485       tu_sort_variables_by_location(&nir->inputs);
 486       tu_sort_variables_by_location(&nir->outputs);
 487       break;
 488    case MESA_SHADER_FRAGMENT:
 489       tu_sort_variables_by_location(&nir->inputs);
 490       break;
 491    case MESA_SHADER_COMPUTE:
 492       break;
 493    default:
 494       unreachable("invalid gl_shader_stage");
 495       break;
 496    }
 497
 498    nir_assign_io_var_locations(&nir->inputs, &nir->num_inputs, stage);
 499    nir_assign_io_var_locations(&nir->outputs, &nir->num_outputs, stage);
 500
 501    NIR_PASS_V(nir, nir_lower_system_values);
 502    NIR_PASS_V(nir, nir_lower_frexp);
 503
 504    if (stage == MESA_SHADER_FRAGMENT)
 505       NIR_PASS_V(nir, nir_lower_input_attachments, true);
 506
 507    NIR_PASS_V(nir, tu_lower_io, shader, layout);
 508
 509    NIR_PASS_V(nir, nir_lower_io, nir_var_all, ir3_glsl_type_size, 0);
 510
 511    if (stage == MESA_SHADER_FRAGMENT) {
 512       /* NOTE: lower load_barycentric_at_sample first, since it
 513        * produces load_barycentric_at_offset:
 514        */
 515       NIR_PASS_V(nir, ir3_nir_lower_load_barycentric_at_sample);
 516       NIR_PASS_V(nir, ir3_nir_lower_load_barycentric_at_offset);
 517
 518       NIR_PASS_V(nir, ir3_nir_move_varying_inputs);
 519    }
 520
 521    NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects, false);
 522
 523    nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
 524
 525    /* num_uniforms only used by ir3 for size of ubo 0 (push constants) */
 526    nir->num_uniforms = MAX_PUSH_CONSTANTS_SIZE / 16;
 527
 528    shader->ir3_shader.compiler = dev->compiler;
 529    shader->ir3_shader.type = stage;
 530    shader->ir3_shader.nir = nir;
 531
 532    return shader;
 533 }
 534
 535 void
 536 tu_shader_destroy(struct tu_device *dev,
 537                   struct tu_shader *shader,
 538                   const VkAllocationCallbacks *alloc)
 539 {
 540    if (shader->ir3_shader.nir)
 541       ralloc_free(shader->ir3_shader.nir);
 542
 543    for (uint32_t i = 0; i < 1 + shader->has_binning_pass; i++) {
 544       if (shader->variants[i].ir)
 545          ir3_destroy(shader->variants[i].ir);
 546    }
 547
 548    if (shader->ir3_shader.const_state.immediates)
 549            free(shader->ir3_shader.const_state.immediates);
 550    if (shader->binary)
 551       free(shader->binary);
 552    if (shader->binning_binary)
 553       free(shader->binning_binary);
 554
 555    vk_free2(&dev->alloc, alloc, shader);
 556 }
 557
 558 void
 559 tu_shader_compile_options_init(
 560    struct tu_shader_compile_options *options,
 561    const VkGraphicsPipelineCreateInfo *pipeline_info)
 562 {
 563    *options = (struct tu_shader_compile_options) {
 564       /* TODO ir3_key */
 565
 566       /* TODO: VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
 567        * some optimizations need to happen otherwise shader might not compile
 568        */
 569       .optimize = true,
 570       .include_binning_pass = true,
 571    };
 572 }
 573
 574 static uint32_t *
 575 tu_compile_shader_variant(struct ir3_shader *shader,
 576                           const struct ir3_shader_key *key,
 577                           struct ir3_shader_variant *nonbinning,
 578                           struct ir3_shader_variant *variant)
 579 {
 580    variant->shader = shader;
 581    variant->type = shader->type;
 582    variant->key = *key;
 583    variant->binning_pass = !!nonbinning;
 584    variant->nonbinning = nonbinning;
 585
 586    int ret = ir3_compile_shader_nir(shader->compiler, variant);
 587    if (ret)
 588       return NULL;
 589
 590    /* when assemble fails, we rely on tu_shader_destroy to clean up the
 591     * variant
 592     */
 593    return ir3_shader_assemble(variant, shader->compiler->gpu_id);
 594 }
 595
 596 VkResult
 597 tu_shader_compile(struct tu_device *dev,
 598                   struct tu_shader *shader,
 599                   const struct tu_shader *next_stage,
 600                   const struct tu_shader_compile_options *options,
 601                   const VkAllocationCallbacks *alloc)
 602 {
 603    if (options->optimize) {
 604       /* ignore the key for the first pass of optimization */
 605       ir3_optimize_nir(&shader->ir3_shader, shader->ir3_shader.nir, NULL);
 606
 607       if (unlikely(dev->physical_device->instance->debug_flags &
 608                    TU_DEBUG_NIR)) {
 609          fprintf(stderr, "optimized nir:\n");
 610          nir_print_shader(shader->ir3_shader.nir, stderr);
 611       }
 612    }
 613
 614    shader->binary = tu_compile_shader_variant(
 615       &shader->ir3_shader, &options->key, NULL, &shader->variants[0]);
 616    if (!shader->binary)
 617       return VK_ERROR_OUT_OF_HOST_MEMORY;
 618
 619    /* compile another variant for the binning pass */
 620    if (options->include_binning_pass &&
 621        shader->ir3_shader.type == MESA_SHADER_VERTEX) {
 622       shader->binning_binary = tu_compile_shader_variant(
 623          &shader->ir3_shader, &options->key, &shader->variants[0],
 624          &shader->variants[1]);
 625       if (!shader->binning_binary)
 626          return VK_ERROR_OUT_OF_HOST_MEMORY;
 627
 628       shader->has_binning_pass = true;
 629    }
 630
 631    if (unlikely(dev->physical_device->instance->debug_flags & TU_DEBUG_IR3)) {
 632       fprintf(stderr, "disassembled ir3:\n");
 633       fprintf(stderr, "shader: %s\n",
 634               gl_shader_stage_name(shader->ir3_shader.type));
 635       ir3_shader_disasm(&shader->variants[0], shader->binary, stderr);
 636
 637       if (shader->has_binning_pass) {
 638          fprintf(stderr, "disassembled ir3:\n");
 639          fprintf(stderr, "shader: %s (binning)\n",
 640                  gl_shader_stage_name(shader->ir3_shader.type));
 641          ir3_shader_disasm(&shader->variants[1], shader->binning_binary,
 642                            stderr);
 643       }
 644    }
 645
 646    return VK_SUCCESS;
 647 }
 648
 649 VkResult
 650 tu_CreateShaderModule(VkDevice _device,
 651                       const VkShaderModuleCreateInfo *pCreateInfo,
 652                       const VkAllocationCallbacks *pAllocator,
 653                       VkShaderModule *pShaderModule)
 654 {
 655    TU_FROM_HANDLE(tu_device, device, _device);
 656    struct tu_shader_module *module;
 657
 658    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
 659    assert(pCreateInfo->flags == 0);
 660    assert(pCreateInfo->codeSize % 4 == 0);
 661
 662    module = vk_alloc2(&device->alloc, pAllocator,
 663                       sizeof(*module) + pCreateInfo->codeSize, 8,
 664                       VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 665    if (module == NULL)
 666       return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
 667
 668    module->code_size = pCreateInfo->codeSize;
 669    memcpy(module->code, pCreateInfo->pCode, pCreateInfo->codeSize);
 670
 671    _mesa_sha1_compute(module->code, module->code_size, module->sha1);
 672
 673    *pShaderModule = tu_shader_module_to_handle(module);
 674
 675    return VK_SUCCESS;
 676 }
 677
 678 void
 679 tu_DestroyShaderModule(VkDevice _device,
 680                        VkShaderModule _module,
 681                        const VkAllocationCallbacks *pAllocator)
 682 {
 683    TU_FROM_HANDLE(tu_device, device, _device);
 684    TU_FROM_HANDLE(tu_shader_module, module, _module);
 685
 686    if (!module)
 687       return;
 688
 689    vk_free2(&device->alloc, pAllocator, module);
 690 }