src/freedreno/vulkan/tu_shader.c

   1 /*
   2  * Copyright © 2019 Google LLC
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "tu_private.h"
  25
  26 #include "spirv/nir_spirv.h"
  27 #include "util/mesa-sha1.h"
  28 #include "nir/nir_xfb_info.h"
  29
  30 #include "ir3/ir3_nir.h"
  31
  32 static nir_shader *
  33 tu_spirv_to_nir(struct ir3_compiler *compiler,
  34                 const uint32_t *words,
  35                 size_t word_count,
  36                 gl_shader_stage stage,
  37                 const char *entry_point_name,
  38                 const VkSpecializationInfo *spec_info)
  39 {
  40    /* TODO these are made-up */
  41    const struct spirv_to_nir_options spirv_options = {
  42       .frag_coord_is_sysval = true,
  43       .lower_ubo_ssbo_access_to_offsets = true,
  44       .caps = {
  45          .transform_feedback = compiler->gpu_id >= 600,
  46       },
  47    };
  48    const nir_shader_compiler_options *nir_options =
  49       ir3_get_compiler_options(compiler);
  50
  51    /* convert VkSpecializationInfo */
  52    struct nir_spirv_specialization *spec = NULL;
  53    uint32_t num_spec = 0;
  54    if (spec_info && spec_info->mapEntryCount) {
  55       spec = malloc(sizeof(*spec) * spec_info->mapEntryCount);
  56       if (!spec)
  57          return NULL;
  58
  59       for (uint32_t i = 0; i < spec_info->mapEntryCount; i++) {
  60          const VkSpecializationMapEntry *entry = &spec_info->pMapEntries[i];
  61          const void *data = spec_info->pData + entry->offset;
  62          assert(data + entry->size <= spec_info->pData + spec_info->dataSize);
  63          spec[i].id = entry->constantID;
  64          if (entry->size == 8)
  65             spec[i].data64 = *(const uint64_t *) data;
  66          else
  67             spec[i].data32 = *(const uint32_t *) data;
  68          spec[i].defined_on_module = false;
  69       }
  70
  71       num_spec = spec_info->mapEntryCount;
  72    }
  73
  74    nir_shader *nir =
  75       spirv_to_nir(words, word_count, spec, num_spec, stage, entry_point_name,
  76                    &spirv_options, nir_options);
  77
  78    free(spec);
  79
  80    assert(nir->info.stage == stage);
  81    nir_validate_shader(nir, "after spirv_to_nir");
  82
  83    return nir;
  84 }
  85
  86 static unsigned
  87 map_add(struct tu_descriptor_map *map, int set, int binding, int value,
  88         int array_size)
  89 {
  90    unsigned index = 0;
  91    for (unsigned i = 0; i < map->num; i++) {
  92       if (set == map->set[i] && binding == map->binding[i]) {
  93          assert(value == map->value[i]);
  94          assert(array_size == map->array_size[i]);
  95          return index;
  96       }
  97       index += map->array_size[i];
  98    }
  99
 100    assert(index == map->num_desc);
 101
 102    map->set[map->num] = set;
 103    map->binding[map->num] = binding;
 104    map->value[map->num] = value;
 105    map->array_size[map->num] = array_size;
 106    map->num++;
 107    map->num_desc += array_size;
 108
 109    return index;
 110 }
 111
 112 static void
 113 lower_tex_src_to_offset(nir_builder *b, nir_tex_instr *instr, unsigned src_idx,
 114                         struct tu_shader *shader,
 115                         const struct tu_pipeline_layout *layout)
 116 {
 117    nir_ssa_def *index = NULL;
 118    unsigned base_index = 0;
 119    unsigned array_elements = 1;
 120    nir_tex_src *src = &instr->src[src_idx];
 121    bool is_sampler = src->src_type == nir_tex_src_sampler_deref;
 122
 123    /* We compute first the offsets */
 124    nir_deref_instr *deref = nir_instr_as_deref(src->src.ssa->parent_instr);
 125    while (deref->deref_type != nir_deref_type_var) {
 126       assert(deref->parent.is_ssa);
 127       nir_deref_instr *parent =
 128          nir_instr_as_deref(deref->parent.ssa->parent_instr);
 129
 130       assert(deref->deref_type == nir_deref_type_array);
 131
 132       if (nir_src_is_const(deref->arr.index) && index == NULL) {
 133          /* We're still building a direct index */
 134          base_index += nir_src_as_uint(deref->arr.index) * array_elements;
 135       } else {
 136          if (index == NULL) {
 137             /* We used to be direct but not anymore */
 138             index = nir_imm_int(b, base_index);
 139             base_index = 0;
 140          }
 141
 142          index = nir_iadd(b, index,
 143                           nir_imul(b, nir_imm_int(b, array_elements),
 144                                    nir_ssa_for_src(b, deref->arr.index, 1)));
 145       }
 146
 147       array_elements *= glsl_get_length(parent->type);
 148
 149       deref = parent;
 150    }
 151
 152    if (index)
 153       index = nir_umin(b, index, nir_imm_int(b, array_elements - 1));
 154
 155    /* We have the offsets, we apply them, rewriting the source or removing
 156     * instr if needed
 157     */
 158    if (index) {
 159       nir_instr_rewrite_src(&instr->instr, &src->src,
 160                             nir_src_for_ssa(index));
 161
 162       src->src_type = is_sampler ?
 163          nir_tex_src_sampler_offset :
 164          nir_tex_src_texture_offset;
 165    } else {
 166       nir_tex_instr_remove_src(instr, src_idx);
 167    }
 168
 169    uint32_t set = deref->var->data.descriptor_set;
 170    uint32_t binding = deref->var->data.binding;
 171    struct tu_descriptor_set_layout *set_layout = layout->set[set].layout;
 172    struct tu_descriptor_set_binding_layout *binding_layout =
 173       &set_layout->binding[binding];
 174
 175    int desc_index = map_add(is_sampler ?
 176                             &shader->sampler_map : &shader->texture_map,
 177                             deref->var->data.descriptor_set,
 178                             deref->var->data.binding,
 179                             deref->var->data.index,
 180                             binding_layout->array_size) + base_index;
 181    if (is_sampler)
 182       instr->sampler_index = desc_index;
 183    else
 184       instr->texture_index = desc_index;
 185 }
 186
 187 static bool
 188 lower_sampler(nir_builder *b, nir_tex_instr *instr, struct tu_shader *shader,
 189                 const struct tu_pipeline_layout *layout)
 190 {
 191    int texture_idx =
 192       nir_tex_instr_src_index(instr, nir_tex_src_texture_deref);
 193
 194    if (texture_idx >= 0)
 195       lower_tex_src_to_offset(b, instr, texture_idx, shader, layout);
 196
 197    int sampler_idx =
 198       nir_tex_instr_src_index(instr, nir_tex_src_sampler_deref);
 199
 200    if (sampler_idx >= 0)
 201       lower_tex_src_to_offset(b, instr, sampler_idx, shader, layout);
 202
 203    if (texture_idx < 0 && sampler_idx < 0)
 204       return false;
 205
 206    return true;
 207 }
 208
 209 static void
 210 lower_load_push_constant(nir_builder *b, nir_intrinsic_instr *instr,
 211                          struct tu_shader *shader)
 212 {
 213    /* note: ir3 wants load_ubo, not load_uniform */
 214    assert(nir_intrinsic_base(instr) == 0);
 215
 216    nir_intrinsic_instr *load =
 217       nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_ubo);
 218
 219    nir_intrinsic_set_align(load, 4, 0);
 220
 221    load->num_components = instr->num_components;
 222    load->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
 223    load->src[1] = instr->src[0];
 224    nir_ssa_dest_init(&load->instr, &load->dest,
 225                      load->num_components, instr->dest.ssa.bit_size,
 226                      instr->dest.ssa.name);
 227    nir_builder_instr_insert(b, &load->instr);
 228    nir_ssa_def_rewrite_uses(&instr->dest.ssa, nir_src_for_ssa(&load->dest.ssa));
 229
 230    nir_instr_remove(&instr->instr);
 231 }
 232
 233 static void
 234 lower_vulkan_resource_index(nir_builder *b, nir_intrinsic_instr *instr,
 235                             struct tu_shader *shader,
 236                             const struct tu_pipeline_layout *layout)
 237 {
 238    nir_const_value *const_val = nir_src_as_const_value(instr->src[0]);
 239
 240    unsigned set = nir_intrinsic_desc_set(instr);
 241    unsigned binding = nir_intrinsic_binding(instr);
 242    struct tu_descriptor_set_layout *set_layout = layout->set[set].layout;
 243    struct tu_descriptor_set_binding_layout *binding_layout =
 244       &set_layout->binding[binding];
 245    unsigned index = 0;
 246
 247    switch (nir_intrinsic_desc_type(instr)) {
 248    case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
 249    case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
 250       if (!const_val)
 251          tu_finishme("non-constant vulkan_resource_index array index");
 252       /* skip index 0 which is used for push constants */
 253       index = map_add(&shader->ubo_map, set, binding, 0,
 254                       binding_layout->array_size) + 1;
 255       index += const_val->u32;
 256       break;
 257    case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
 258    case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
 259       if (!const_val)
 260          tu_finishme("non-constant vulkan_resource_index array index");
 261       index = map_add(&shader->ssbo_map, set, binding, 0,
 262                       binding_layout->array_size);
 263       index += const_val->u32;
 264       break;
 265    default:
 266       tu_finishme("unsupported desc_type for vulkan_resource_index");
 267       break;
 268    }
 269
 270    nir_ssa_def_rewrite_uses(&instr->dest.ssa,
 271                             nir_src_for_ssa(nir_imm_int(b, index)));
 272    nir_instr_remove(&instr->instr);
 273 }
 274
 275 static void
 276 lower_image_deref(nir_builder *b,
 277                   nir_intrinsic_instr *instr, struct tu_shader *shader,
 278                   const struct tu_pipeline_layout *layout)
 279 {
 280    nir_deref_instr *deref = nir_src_as_deref(instr->src[0]);
 281    nir_variable *var = nir_deref_instr_get_variable(deref);
 282
 283    uint32_t set = var->data.descriptor_set;
 284    uint32_t binding = var->data.binding;
 285    struct tu_descriptor_set_layout *set_layout = layout->set[set].layout;
 286    struct tu_descriptor_set_binding_layout *binding_layout =
 287       &set_layout->binding[binding];
 288
 289    nir_ssa_def *index = nir_imm_int(b,
 290                                     map_add(&shader->image_map,
 291                                             set, binding, var->data.index,
 292                                             binding_layout->array_size));
 293    if (deref->deref_type != nir_deref_type_var) {
 294       assert(deref->deref_type == nir_deref_type_array);
 295       index = nir_iadd(b, index, nir_ssa_for_src(b, deref->arr.index, 1));
 296    }
 297    nir_rewrite_image_intrinsic(instr, index, false);
 298 }
 299
 300 static bool
 301 lower_intrinsic(nir_builder *b, nir_intrinsic_instr *instr,
 302                 struct tu_shader *shader,
 303                 const struct tu_pipeline_layout *layout)
 304 {
 305    switch (instr->intrinsic) {
 306    case nir_intrinsic_load_layer_id:
 307       /* TODO: remove this when layered rendering is implemented */
 308       nir_ssa_def_rewrite_uses(&instr->dest.ssa,
 309                                nir_src_for_ssa(nir_imm_int(b, 0)));
 310       nir_instr_remove(&instr->instr);
 311       return true;
 312
 313    case nir_intrinsic_load_push_constant:
 314       lower_load_push_constant(b, instr, shader);
 315       return true;
 316
 317    case nir_intrinsic_vulkan_resource_index:
 318       lower_vulkan_resource_index(b, instr, shader, layout);
 319       return true;
 320
 321    case nir_intrinsic_image_deref_load:
 322    case nir_intrinsic_image_deref_store:
 323    case nir_intrinsic_image_deref_atomic_add:
 324    case nir_intrinsic_image_deref_atomic_imin:
 325    case nir_intrinsic_image_deref_atomic_umin:
 326    case nir_intrinsic_image_deref_atomic_imax:
 327    case nir_intrinsic_image_deref_atomic_umax:
 328    case nir_intrinsic_image_deref_atomic_and:
 329    case nir_intrinsic_image_deref_atomic_or:
 330    case nir_intrinsic_image_deref_atomic_xor:
 331    case nir_intrinsic_image_deref_atomic_exchange:
 332    case nir_intrinsic_image_deref_atomic_comp_swap:
 333    case nir_intrinsic_image_deref_size:
 334    case nir_intrinsic_image_deref_samples:
 335    case nir_intrinsic_image_deref_load_param_intel:
 336    case nir_intrinsic_image_deref_load_raw_intel:
 337    case nir_intrinsic_image_deref_store_raw_intel:
 338       lower_image_deref(b, instr, shader, layout);
 339       return true;
 340
 341    default:
 342       return false;
 343    }
 344 }
 345
 346 static bool
 347 lower_impl(nir_function_impl *impl, struct tu_shader *shader,
 348             const struct tu_pipeline_layout *layout)
 349 {
 350    nir_builder b;
 351    nir_builder_init(&b, impl);
 352    bool progress = false;
 353
 354    nir_foreach_block(block, impl) {
 355       nir_foreach_instr_safe(instr, block) {
 356          b.cursor = nir_before_instr(instr);
 357          switch (instr->type) {
 358          case nir_instr_type_tex:
 359             progress |= lower_sampler(&b, nir_instr_as_tex(instr), shader, layout);
 360             break;
 361          case nir_instr_type_intrinsic:
 362             progress |= lower_intrinsic(&b, nir_instr_as_intrinsic(instr), shader, layout);
 363             break;
 364          default:
 365             break;
 366          }
 367       }
 368    }
 369
 370    return progress;
 371 }
 372
 373 static bool
 374 tu_lower_io(nir_shader *shader, struct tu_shader *tu_shader,
 375             const struct tu_pipeline_layout *layout)
 376 {
 377    bool progress = false;
 378
 379    nir_foreach_function(function, shader) {
 380       if (function->impl)
 381          progress |= lower_impl(function->impl, tu_shader, layout);
 382    }
 383
 384    /* spirv_to_nir produces num_ssbos equal to the number of SSBO-containing
 385     * variables, while ir3 wants the number of descriptors (like the gallium
 386     * path).
 387     */
 388    shader->info.num_ssbos = tu_shader->ssbo_map.num_desc;
 389
 390    return progress;
 391 }
 392
 393 static void
 394 tu_gather_xfb_info(nir_shader *nir, struct tu_shader *shader)
 395 {
 396    struct ir3_stream_output_info *info = &shader->ir3_shader.stream_output;
 397    nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
 398
 399    if (!xfb)
 400       return;
 401
 402    /* creating a map from VARYING_SLOT_* enums to consecutive index */
 403    uint8_t num_outputs = 0;
 404    uint64_t outputs_written = 0;
 405    for (int i = 0; i < xfb->output_count; i++)
 406       outputs_written |= BITFIELD64_BIT(xfb->outputs[i].location);
 407
 408    uint8_t output_map[VARYING_SLOT_TESS_MAX];
 409    memset(output_map, 0, sizeof(output_map));
 410
 411    for (unsigned attr = 0; attr < VARYING_SLOT_MAX; attr++) {
 412       if (outputs_written & BITFIELD64_BIT(attr))
 413          output_map[attr] = num_outputs++;
 414    }
 415
 416    assert(xfb->output_count < IR3_MAX_SO_OUTPUTS);
 417    info->num_outputs = xfb->output_count;
 418
 419    for (int i = 0; i < IR3_MAX_SO_BUFFERS; i++)
 420       info->stride[i] = xfb->buffers[i].stride / 4;
 421
 422    for (int i = 0; i < xfb->output_count; i++) {
 423       info->output[i].register_index = output_map[xfb->outputs[i].location];
 424       info->output[i].start_component = xfb->outputs[i].component_offset;
 425       info->output[i].num_components =
 426                            util_bitcount(xfb->outputs[i].component_mask);
 427       info->output[i].output_buffer  = xfb->outputs[i].buffer;
 428       info->output[i].dst_offset = xfb->outputs[i].offset / 4;
 429       info->output[i].stream = xfb->buffer_to_stream[xfb->outputs[i].buffer];
 430    }
 431
 432    ralloc_free(xfb);
 433 }
 434
 435 struct tu_shader *
 436 tu_shader_create(struct tu_device *dev,
 437                  gl_shader_stage stage,
 438                  const VkPipelineShaderStageCreateInfo *stage_info,
 439                  struct tu_pipeline_layout *layout,
 440                  const VkAllocationCallbacks *alloc)
 441 {
 442    const struct tu_shader_module *module =
 443       tu_shader_module_from_handle(stage_info->module);
 444    struct tu_shader *shader;
 445
 446    const uint32_t max_variant_count = (stage == MESA_SHADER_VERTEX) ? 2 : 1;
 447    shader = vk_zalloc2(
 448       &dev->alloc, alloc,
 449       sizeof(*shader) + sizeof(struct ir3_shader_variant) * max_variant_count,
 450       8, VK_SYSTEM_ALLOCATION_SCOPE_COMMAND);
 451    if (!shader)
 452       return NULL;
 453
 454    /* translate SPIR-V to NIR */
 455    assert(module->code_size % 4 == 0);
 456    nir_shader *nir = tu_spirv_to_nir(
 457       dev->compiler, (const uint32_t *) module->code, module->code_size / 4,
 458       stage, stage_info->pName, stage_info->pSpecializationInfo);
 459    if (!nir) {
 460       vk_free2(&dev->alloc, alloc, shader);
 461       return NULL;
 462    }
 463
 464    if (unlikely(dev->physical_device->instance->debug_flags & TU_DEBUG_NIR)) {
 465       fprintf(stderr, "translated nir:\n");
 466       nir_print_shader(nir, stderr);
 467    }
 468
 469    /* multi step inlining procedure */
 470    NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_function_temp);
 471    NIR_PASS_V(nir, nir_lower_returns);
 472    NIR_PASS_V(nir, nir_inline_functions);
 473    NIR_PASS_V(nir, nir_opt_deref);
 474    foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
 475       if (!func->is_entrypoint)
 476          exec_node_remove(&func->node);
 477    }
 478    assert(exec_list_length(&nir->functions) == 1);
 479    NIR_PASS_V(nir, nir_lower_variable_initializers, ~nir_var_function_temp);
 480
 481    /* Split member structs.  We do this before lower_io_to_temporaries so that
 482     * it doesn't lower system values to temporaries by accident.
 483     */
 484    NIR_PASS_V(nir, nir_split_var_copies);
 485    NIR_PASS_V(nir, nir_split_per_member_structs);
 486
 487    NIR_PASS_V(nir, nir_remove_dead_variables,
 488               nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared);
 489
 490    /* Gather information for transform feedback.
 491     * This should be called after nir_split_per_member_structs.
 492     * Also needs to be called after nir_remove_dead_variables with varyings,
 493     * so that we could align stream outputs correctly.
 494     */
 495    if (nir->info.stage == MESA_SHADER_VERTEX ||
 496          nir->info.stage == MESA_SHADER_TESS_EVAL ||
 497          nir->info.stage == MESA_SHADER_GEOMETRY)
 498       tu_gather_xfb_info(nir, shader);
 499
 500    NIR_PASS_V(nir, nir_propagate_invariant);
 501
 502    NIR_PASS_V(nir, nir_lower_io_to_temporaries, nir_shader_get_entrypoint(nir), true, true);
 503
 504    NIR_PASS_V(nir, nir_lower_global_vars_to_local);
 505    NIR_PASS_V(nir, nir_split_var_copies);
 506    NIR_PASS_V(nir, nir_lower_var_copies);
 507
 508    NIR_PASS_V(nir, nir_opt_copy_prop_vars);
 509    NIR_PASS_V(nir, nir_opt_combine_stores, nir_var_all);
 510
 511    /* ir3 doesn't support indirect input/output */
 512    NIR_PASS_V(nir, nir_lower_indirect_derefs, nir_var_shader_in | nir_var_shader_out);
 513
 514    NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects, false);
 515
 516    nir_assign_io_var_locations(&nir->inputs, &nir->num_inputs, stage);
 517    nir_assign_io_var_locations(&nir->outputs, &nir->num_outputs, stage);
 518
 519    NIR_PASS_V(nir, nir_lower_system_values);
 520    NIR_PASS_V(nir, nir_lower_frexp);
 521
 522    if (stage == MESA_SHADER_FRAGMENT)
 523       NIR_PASS_V(nir, nir_lower_input_attachments, true);
 524
 525    NIR_PASS_V(nir, tu_lower_io, shader, layout);
 526
 527    NIR_PASS_V(nir, nir_lower_io, nir_var_all, ir3_glsl_type_size, 0);
 528
 529    if (stage == MESA_SHADER_FRAGMENT) {
 530       /* NOTE: lower load_barycentric_at_sample first, since it
 531        * produces load_barycentric_at_offset:
 532        */
 533       NIR_PASS_V(nir, ir3_nir_lower_load_barycentric_at_sample);
 534       NIR_PASS_V(nir, ir3_nir_lower_load_barycentric_at_offset);
 535
 536       NIR_PASS_V(nir, ir3_nir_move_varying_inputs);
 537    }
 538
 539    nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
 540
 541    /* num_uniforms only used by ir3 for size of ubo 0 (push constants) */
 542    nir->num_uniforms = MAX_PUSH_CONSTANTS_SIZE / 16;
 543
 544    shader->ir3_shader.compiler = dev->compiler;
 545    shader->ir3_shader.type = stage;
 546    shader->ir3_shader.nir = nir;
 547
 548    return shader;
 549 }
 550
 551 void
 552 tu_shader_destroy(struct tu_device *dev,
 553                   struct tu_shader *shader,
 554                   const VkAllocationCallbacks *alloc)
 555 {
 556    if (shader->ir3_shader.nir)
 557       ralloc_free(shader->ir3_shader.nir);
 558
 559    for (uint32_t i = 0; i < 1 + shader->has_binning_pass; i++) {
 560       if (shader->variants[i].ir)
 561          ir3_destroy(shader->variants[i].ir);
 562    }
 563
 564    if (shader->ir3_shader.const_state.immediates)
 565            free(shader->ir3_shader.const_state.immediates);
 566    if (shader->binary)
 567       free(shader->binary);
 568    if (shader->binning_binary)
 569       free(shader->binning_binary);
 570
 571    vk_free2(&dev->alloc, alloc, shader);
 572 }
 573
 574 void
 575 tu_shader_compile_options_init(
 576    struct tu_shader_compile_options *options,
 577    const VkGraphicsPipelineCreateInfo *pipeline_info)
 578 {
 579    bool has_gs = false;
 580    if (pipeline_info) {
 581       for (uint32_t i = 0; i < pipeline_info->stageCount; i++) {
 582          if (pipeline_info->pStages[i].stage == VK_SHADER_STAGE_GEOMETRY_BIT) {
 583             has_gs = true;
 584             break;
 585          }
 586       }
 587    }
 588
 589    *options = (struct tu_shader_compile_options) {
 590       /* TODO: Populate the remaining fields of ir3_shader_key. */
 591       .key = {
 592          .has_gs = has_gs,
 593       },
 594       /* TODO: VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
 595        * some optimizations need to happen otherwise shader might not compile
 596        */
 597       .optimize = true,
 598       .include_binning_pass = true,
 599    };
 600 }
 601
 602 static uint32_t *
 603 tu_compile_shader_variant(struct ir3_shader *shader,
 604                           const struct ir3_shader_key *key,
 605                           struct ir3_shader_variant *nonbinning,
 606                           struct ir3_shader_variant *variant)
 607 {
 608    variant->shader = shader;
 609    variant->type = shader->type;
 610    variant->key = *key;
 611    variant->binning_pass = !!nonbinning;
 612    variant->nonbinning = nonbinning;
 613
 614    int ret = ir3_compile_shader_nir(shader->compiler, variant);
 615    if (ret)
 616       return NULL;
 617
 618    /* when assemble fails, we rely on tu_shader_destroy to clean up the
 619     * variant
 620     */
 621    return ir3_shader_assemble(variant, shader->compiler->gpu_id);
 622 }
 623
 624 VkResult
 625 tu_shader_compile(struct tu_device *dev,
 626                   struct tu_shader *shader,
 627                   const struct tu_shader *next_stage,
 628                   const struct tu_shader_compile_options *options,
 629                   const VkAllocationCallbacks *alloc)
 630 {
 631    if (options->optimize) {
 632       /* ignore the key for the first pass of optimization */
 633       ir3_optimize_nir(&shader->ir3_shader, shader->ir3_shader.nir, NULL);
 634
 635       if (unlikely(dev->physical_device->instance->debug_flags &
 636                    TU_DEBUG_NIR)) {
 637          fprintf(stderr, "optimized nir:\n");
 638          nir_print_shader(shader->ir3_shader.nir, stderr);
 639       }
 640    }
 641
 642    shader->binary = tu_compile_shader_variant(
 643       &shader->ir3_shader, &options->key, NULL, &shader->variants[0]);
 644    if (!shader->binary)
 645       return VK_ERROR_OUT_OF_HOST_MEMORY;
 646
 647    /* compile another variant for the binning pass */
 648    if (options->include_binning_pass &&
 649        shader->ir3_shader.type == MESA_SHADER_VERTEX) {
 650       shader->binning_binary = tu_compile_shader_variant(
 651          &shader->ir3_shader, &options->key, &shader->variants[0],
 652          &shader->variants[1]);
 653       if (!shader->binning_binary)
 654          return VK_ERROR_OUT_OF_HOST_MEMORY;
 655
 656       shader->has_binning_pass = true;
 657    }
 658
 659    if (unlikely(dev->physical_device->instance->debug_flags & TU_DEBUG_IR3)) {
 660       fprintf(stderr, "disassembled ir3:\n");
 661       fprintf(stderr, "shader: %s\n",
 662               gl_shader_stage_name(shader->ir3_shader.type));
 663       ir3_shader_disasm(&shader->variants[0], shader->binary, stderr);
 664
 665       if (shader->has_binning_pass) {
 666          fprintf(stderr, "disassembled ir3:\n");
 667          fprintf(stderr, "shader: %s (binning)\n",
 668                  gl_shader_stage_name(shader->ir3_shader.type));
 669          ir3_shader_disasm(&shader->variants[1], shader->binning_binary,
 670                            stderr);
 671       }
 672    }
 673
 674    return VK_SUCCESS;
 675 }
 676
 677 VkResult
 678 tu_CreateShaderModule(VkDevice _device,
 679                       const VkShaderModuleCreateInfo *pCreateInfo,
 680                       const VkAllocationCallbacks *pAllocator,
 681                       VkShaderModule *pShaderModule)
 682 {
 683    TU_FROM_HANDLE(tu_device, device, _device);
 684    struct tu_shader_module *module;
 685
 686    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
 687    assert(pCreateInfo->flags == 0);
 688    assert(pCreateInfo->codeSize % 4 == 0);
 689
 690    module = vk_alloc2(&device->alloc, pAllocator,
 691                       sizeof(*module) + pCreateInfo->codeSize, 8,
 692                       VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 693    if (module == NULL)
 694       return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
 695
 696    module->code_size = pCreateInfo->codeSize;
 697    memcpy(module->code, pCreateInfo->pCode, pCreateInfo->codeSize);
 698
 699    _mesa_sha1_compute(module->code, module->code_size, module->sha1);
 700
 701    *pShaderModule = tu_shader_module_to_handle(module);
 702
 703    return VK_SUCCESS;
 704 }
 705
 706 void
 707 tu_DestroyShaderModule(VkDevice _device,
 708                        VkShaderModule _module,
 709                        const VkAllocationCallbacks *pAllocator)
 710 {
 711    TU_FROM_HANDLE(tu_device, device, _device);
 712    TU_FROM_HANDLE(tu_shader_module, module, _module);
 713
 714    if (!module)
 715       return;
 716
 717    vk_free2(&device->alloc, pAllocator, module);
 718 }