2 * Copyright 2017 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 * This is ported mostly out of radeonsi, if we can drop TGSI, we can likely
27 * make a lot this go away.
30 #include "nir_to_tgsi_info.h"
31 #include "util/u_math.h"
33 #include "nir_deref.h"
34 #include "tgsi/tgsi_scan.h"
35 #include "tgsi/tgsi_from_mesa.h"
37 static nir_variable
* tex_get_texture_var(nir_tex_instr
*instr
)
39 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
40 switch (instr
->src
[i
].src_type
) {
41 case nir_tex_src_texture_deref
:
42 return nir_deref_instr_get_variable(nir_src_as_deref(instr
->src
[i
].src
));
51 static nir_variable
* intrinsic_get_var(nir_intrinsic_instr
*instr
)
53 return nir_deref_instr_get_variable(nir_src_as_deref(instr
->src
[0]));
57 static void gather_usage_helper(const nir_deref_instr
**deref_ptr
,
62 for (; *deref_ptr
; deref_ptr
++) {
63 const nir_deref_instr
*deref
= *deref_ptr
;
64 switch (deref
->deref_type
) {
65 case nir_deref_type_array
: {
66 bool is_compact
= nir_deref_instr_get_variable(deref
)->data
.compact
;
67 unsigned elem_size
= is_compact
? DIV_ROUND_UP(glsl_get_length(deref
->type
), 4) :
68 glsl_count_attribute_slots(deref
->type
, false);
69 if (nir_src_is_const(deref
->arr
.index
)) {
71 location
+= nir_src_as_uint(deref
->arr
.index
) / 4;
72 mask
<<= nir_src_as_uint(deref
->arr
.index
) % 4;
74 location
+= elem_size
* nir_src_as_uint(deref
->arr
.index
);
76 unsigned array_elems
=
77 glsl_get_length(deref_ptr
[-1]->type
);
78 for (unsigned i
= 0; i
< array_elems
; i
++) {
79 gather_usage_helper(deref_ptr
+ 1,
80 location
+ elem_size
* i
,
87 case nir_deref_type_struct
: {
88 const struct glsl_type
*parent_type
=
90 unsigned index
= deref
->strct
.index
;
91 for (unsigned i
= 0; i
< index
; i
++) {
92 const struct glsl_type
*ft
= glsl_get_struct_field(parent_type
, i
);
93 location
+= glsl_count_attribute_slots(ft
, false);
98 unreachable("Unhandled deref type in gather_components_used_helper");
102 usage_mask
[location
] |= mask
& 0xf;
104 usage_mask
[location
+ 1] |= (mask
>> 4) & 0xf;
107 static void gather_usage(const nir_deref_instr
*deref
,
112 nir_deref_path_init(&path
, (nir_deref_instr
*)deref
, NULL
);
114 unsigned location_frac
= path
.path
[0]->var
->data
.location_frac
;
115 if (glsl_type_is_64bit(deref
->type
)) {
116 uint8_t new_mask
= 0;
117 for (unsigned i
= 0; i
< 4; i
++) {
119 new_mask
|= 0x3 << (2 * i
);
121 mask
= new_mask
<< location_frac
;
123 mask
<<= location_frac
;
127 gather_usage_helper((const nir_deref_instr
**)&path
.path
[1],
128 path
.path
[0]->var
->data
.driver_location
,
131 nir_deref_path_finish(&path
);
134 static void gather_intrinsic_load_deref_info(const nir_shader
*nir
,
135 const nir_intrinsic_instr
*instr
,
136 const nir_deref_instr
*deref
,
139 struct tgsi_shader_info
*info
)
141 assert(var
&& var
->data
.mode
== nir_var_shader_in
);
143 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
)
144 gather_usage(deref
, nir_ssa_def_components_read(&instr
->dest
.ssa
),
145 info
->input_usage_mask
);
147 switch (nir
->info
.stage
) {
148 case MESA_SHADER_VERTEX
: {
153 unsigned semantic_name
, semantic_index
;
154 tgsi_get_gl_varying_semantic(var
->data
.location
, need_texcoord
,
155 &semantic_name
, &semantic_index
);
157 if (semantic_name
== TGSI_SEMANTIC_COLOR
) {
158 uint8_t mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
159 info
->colors_read
|= mask
<< (semantic_index
* 4);
161 if (semantic_name
== TGSI_SEMANTIC_FACE
) {
162 info
->uses_frontface
= true;
169 static void scan_instruction(const struct nir_shader
*nir
,
171 struct tgsi_shader_info
*info
,
174 if (instr
->type
== nir_instr_type_alu
) {
175 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
180 case nir_op_fddx_fine
:
181 case nir_op_fddy_fine
:
182 case nir_op_fddx_coarse
:
183 case nir_op_fddy_coarse
:
184 info
->uses_derivatives
= true;
189 } else if (instr
->type
== nir_instr_type_tex
) {
190 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
191 nir_variable
*texture
= tex_get_texture_var(tex
);
194 info
->samplers_declared
|=
195 u_bit_consecutive(tex
->sampler_index
, 1);
197 if (texture
->data
.bindless
)
198 info
->uses_bindless_samplers
= true;
205 info
->uses_derivatives
= true;
210 } else if (instr
->type
== nir_instr_type_intrinsic
) {
211 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
213 switch (intr
->intrinsic
) {
214 case nir_intrinsic_load_front_face
:
215 info
->uses_frontface
= 1;
217 case nir_intrinsic_load_instance_id
:
218 info
->uses_instanceid
= 1;
220 case nir_intrinsic_load_invocation_id
:
221 info
->uses_invocationid
= true;
223 case nir_intrinsic_load_num_work_groups
:
224 info
->uses_grid_size
= true;
226 case nir_intrinsic_load_local_group_size
:
227 /* The block size is translated to IMM with a fixed block size. */
228 if (info
->properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] == 0)
229 info
->uses_block_size
= true;
231 case nir_intrinsic_load_local_invocation_id
:
232 case nir_intrinsic_load_work_group_id
: {
233 unsigned mask
= nir_ssa_def_components_read(&intr
->dest
.ssa
);
235 unsigned i
= u_bit_scan(&mask
);
237 if (intr
->intrinsic
== nir_intrinsic_load_work_group_id
)
238 info
->uses_block_id
[i
] = true;
240 info
->uses_thread_id
[i
] = true;
244 case nir_intrinsic_load_vertex_id
:
245 info
->uses_vertexid
= 1;
247 case nir_intrinsic_load_vertex_id_zero_base
:
248 info
->uses_vertexid_nobase
= 1;
250 case nir_intrinsic_load_base_vertex
:
251 info
->uses_basevertex
= 1;
253 case nir_intrinsic_load_draw_id
:
254 info
->uses_drawid
= 1;
256 case nir_intrinsic_load_primitive_id
:
257 info
->uses_primid
= 1;
259 case nir_intrinsic_load_sample_mask_in
:
260 info
->reads_samplemask
= true;
262 case nir_intrinsic_load_tess_level_inner
:
263 case nir_intrinsic_load_tess_level_outer
:
264 info
->reads_tess_factors
= true;
266 case nir_intrinsic_bindless_image_load
:
267 info
->uses_bindless_images
= true;
269 if (nir_intrinsic_image_dim(intr
) == GLSL_SAMPLER_DIM_BUF
)
270 info
->uses_bindless_buffer_load
= true;
272 info
->uses_bindless_image_load
= true;
274 case nir_intrinsic_bindless_image_size
:
275 case nir_intrinsic_bindless_image_samples
:
276 info
->uses_bindless_images
= true;
278 case nir_intrinsic_bindless_image_store
:
279 info
->uses_bindless_images
= true;
281 if (nir_intrinsic_image_dim(intr
) == GLSL_SAMPLER_DIM_BUF
)
282 info
->uses_bindless_buffer_store
= true;
284 info
->uses_bindless_image_store
= true;
286 info
->writes_memory
= true;
288 case nir_intrinsic_image_deref_store
:
289 info
->writes_memory
= true;
291 case nir_intrinsic_bindless_image_atomic_add
:
292 case nir_intrinsic_bindless_image_atomic_imin
:
293 case nir_intrinsic_bindless_image_atomic_imax
:
294 case nir_intrinsic_bindless_image_atomic_umin
:
295 case nir_intrinsic_bindless_image_atomic_umax
:
296 case nir_intrinsic_bindless_image_atomic_and
:
297 case nir_intrinsic_bindless_image_atomic_or
:
298 case nir_intrinsic_bindless_image_atomic_xor
:
299 case nir_intrinsic_bindless_image_atomic_exchange
:
300 case nir_intrinsic_bindless_image_atomic_comp_swap
:
301 info
->uses_bindless_images
= true;
303 if (nir_intrinsic_image_dim(intr
) == GLSL_SAMPLER_DIM_BUF
)
304 info
->uses_bindless_buffer_atomic
= true;
306 info
->uses_bindless_image_atomic
= true;
308 info
->writes_memory
= true;
310 case nir_intrinsic_image_deref_atomic_add
:
311 case nir_intrinsic_image_deref_atomic_imin
:
312 case nir_intrinsic_image_deref_atomic_imax
:
313 case nir_intrinsic_image_deref_atomic_umin
:
314 case nir_intrinsic_image_deref_atomic_umax
:
315 case nir_intrinsic_image_deref_atomic_and
:
316 case nir_intrinsic_image_deref_atomic_or
:
317 case nir_intrinsic_image_deref_atomic_xor
:
318 case nir_intrinsic_image_deref_atomic_exchange
:
319 case nir_intrinsic_image_deref_atomic_comp_swap
:
320 info
->writes_memory
= true;
322 case nir_intrinsic_store_ssbo
:
323 case nir_intrinsic_ssbo_atomic_add
:
324 case nir_intrinsic_ssbo_atomic_imin
:
325 case nir_intrinsic_ssbo_atomic_umin
:
326 case nir_intrinsic_ssbo_atomic_imax
:
327 case nir_intrinsic_ssbo_atomic_umax
:
328 case nir_intrinsic_ssbo_atomic_and
:
329 case nir_intrinsic_ssbo_atomic_or
:
330 case nir_intrinsic_ssbo_atomic_xor
:
331 case nir_intrinsic_ssbo_atomic_exchange
:
332 case nir_intrinsic_ssbo_atomic_comp_swap
:
333 info
->writes_memory
= true;
335 case nir_intrinsic_load_deref
: {
336 nir_variable
*var
= intrinsic_get_var(intr
);
337 nir_variable_mode mode
= var
->data
.mode
;
338 nir_deref_instr
*const deref
= nir_src_as_deref(intr
->src
[0]);
339 enum glsl_base_type base_type
=
340 glsl_get_base_type(glsl_without_array(var
->type
));
342 if (nir_deref_instr_has_indirect(deref
)) {
343 if (mode
== nir_var_shader_in
)
344 info
->indirect_files
|= (1 << TGSI_FILE_INPUT
);
346 if (mode
== nir_var_shader_in
) {
347 gather_intrinsic_load_deref_info(nir
, intr
, deref
, need_texcoord
, var
, info
);
349 switch (var
->data
.interpolation
) {
350 case INTERP_MODE_NONE
:
351 if (glsl_base_type_is_integer(base_type
))
355 case INTERP_MODE_SMOOTH
:
356 if (var
->data
.sample
)
357 info
->uses_persp_sample
= true;
358 else if (var
->data
.centroid
)
359 info
->uses_persp_centroid
= true;
361 info
->uses_persp_center
= true;
364 case INTERP_MODE_NOPERSPECTIVE
:
365 if (var
->data
.sample
)
366 info
->uses_linear_sample
= true;
367 else if (var
->data
.centroid
)
368 info
->uses_linear_centroid
= true;
370 info
->uses_linear_center
= true;
376 case nir_intrinsic_interp_deref_at_centroid
:
377 case nir_intrinsic_interp_deref_at_sample
:
378 case nir_intrinsic_interp_deref_at_offset
: {
379 enum glsl_interp_mode interp
= intrinsic_get_var(intr
)->data
.interpolation
;
381 case INTERP_MODE_SMOOTH
:
382 case INTERP_MODE_NONE
:
383 if (intr
->intrinsic
== nir_intrinsic_interp_deref_at_centroid
)
384 info
->uses_persp_opcode_interp_centroid
= true;
385 else if (intr
->intrinsic
== nir_intrinsic_interp_deref_at_sample
)
386 info
->uses_persp_opcode_interp_sample
= true;
388 info
->uses_persp_opcode_interp_offset
= true;
390 case INTERP_MODE_NOPERSPECTIVE
:
391 if (intr
->intrinsic
== nir_intrinsic_interp_deref_at_centroid
)
392 info
->uses_linear_opcode_interp_centroid
= true;
393 else if (intr
->intrinsic
== nir_intrinsic_interp_deref_at_sample
)
394 info
->uses_linear_opcode_interp_sample
= true;
396 info
->uses_linear_opcode_interp_offset
= true;
398 case INTERP_MODE_FLAT
:
401 unreachable("Unsupported interpoation type");
411 void nir_tgsi_scan_shader(const struct nir_shader
*nir
,
412 struct tgsi_shader_info
*info
,
418 info
->processor
= pipe_shader_type_from_mesa(nir
->info
.stage
);
419 info
->num_tokens
= 2; /* indicate that the shader is non-empty */
420 info
->num_instructions
= 2;
422 info
->properties
[TGSI_PROPERTY_NEXT_SHADER
] =
423 pipe_shader_type_from_mesa(nir
->info
.next_stage
);
425 if (nir
->info
.stage
== MESA_SHADER_VERTEX
) {
426 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] =
427 nir
->info
.vs
.window_space_position
;
430 if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
431 info
->properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
] =
432 nir
->info
.tess
.tcs_vertices_out
;
435 if (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
436 if (nir
->info
.tess
.primitive_mode
== GL_ISOLINES
)
437 info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
] = PIPE_PRIM_LINES
;
439 info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
] = nir
->info
.tess
.primitive_mode
;
441 STATIC_ASSERT((TESS_SPACING_EQUAL
+ 1) % 3 == PIPE_TESS_SPACING_EQUAL
);
442 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD
+ 1) % 3 ==
443 PIPE_TESS_SPACING_FRACTIONAL_ODD
);
444 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN
+ 1) % 3 ==
445 PIPE_TESS_SPACING_FRACTIONAL_EVEN
);
447 info
->properties
[TGSI_PROPERTY_TES_SPACING
] = (nir
->info
.tess
.spacing
+ 1) % 3;
448 info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
] = !nir
->info
.tess
.ccw
;
449 info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
] = nir
->info
.tess
.point_mode
;
452 if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
453 info
->properties
[TGSI_PROPERTY_GS_INPUT_PRIM
] = nir
->info
.gs
.input_primitive
;
454 info
->properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
] = nir
->info
.gs
.output_primitive
;
455 info
->properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
] = nir
->info
.gs
.vertices_out
;
456 info
->properties
[TGSI_PROPERTY_GS_INVOCATIONS
] = nir
->info
.gs
.invocations
;
459 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
460 info
->properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] =
461 nir
->info
.fs
.early_fragment_tests
| nir
->info
.fs
.post_depth_coverage
;
462 info
->properties
[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE
] = nir
->info
.fs
.post_depth_coverage
;
464 if (nir
->info
.fs
.pixel_center_integer
) {
465 info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] =
466 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
;
469 if (nir
->info
.fs
.depth_layout
!= FRAG_DEPTH_LAYOUT_NONE
) {
470 switch (nir
->info
.fs
.depth_layout
) {
471 case FRAG_DEPTH_LAYOUT_ANY
:
472 info
->properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
] = TGSI_FS_DEPTH_LAYOUT_ANY
;
474 case FRAG_DEPTH_LAYOUT_GREATER
:
475 info
->properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
] = TGSI_FS_DEPTH_LAYOUT_GREATER
;
477 case FRAG_DEPTH_LAYOUT_LESS
:
478 info
->properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
] = TGSI_FS_DEPTH_LAYOUT_LESS
;
480 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
481 info
->properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
] = TGSI_FS_DEPTH_LAYOUT_UNCHANGED
;
484 unreachable("Unknow depth layout");
489 if (gl_shader_stage_is_compute(nir
->info
.stage
)) {
490 info
->properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] = nir
->info
.cs
.local_size
[0];
491 info
->properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
] = nir
->info
.cs
.local_size
[1];
492 info
->properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
] = nir
->info
.cs
.local_size
[2];
496 uint64_t processed_inputs
= 0;
497 nir_foreach_shader_in_variable(variable
, nir
) {
498 unsigned semantic_name
, semantic_index
;
500 const struct glsl_type
*type
= variable
->type
;
501 if (nir_is_per_vertex_io(variable
, nir
->info
.stage
)) {
502 assert(glsl_type_is_array(type
));
503 type
= glsl_get_array_element(type
);
506 unsigned attrib_count
= variable
->data
.compact
? DIV_ROUND_UP(glsl_get_length(type
), 4) :
507 glsl_count_attribute_slots(type
, nir
->info
.stage
== MESA_SHADER_VERTEX
);
509 i
= variable
->data
.driver_location
;
511 /* Vertex shader inputs don't have semantics. The state
512 * tracker has already mapped them to attributes via
513 * variable->data.driver_location.
515 if (nir
->info
.stage
== MESA_SHADER_VERTEX
) {
519 for (unsigned j
= 0; j
< attrib_count
; j
++, i
++) {
521 if (processed_inputs
& ((uint64_t)1 << i
))
524 processed_inputs
|= ((uint64_t)1 << i
);
526 tgsi_get_gl_varying_semantic(variable
->data
.location
+ j
, need_texcoord
,
527 &semantic_name
, &semantic_index
);
529 info
->input_semantic_name
[i
] = semantic_name
;
530 info
->input_semantic_index
[i
] = semantic_index
;
532 if (semantic_name
== TGSI_SEMANTIC_PRIMID
)
533 info
->uses_primid
= true;
535 enum glsl_base_type base_type
=
536 glsl_get_base_type(glsl_without_array(variable
->type
));
538 if (variable
->data
.centroid
)
539 info
->input_interpolate_loc
[i
] = TGSI_INTERPOLATE_LOC_CENTROID
;
540 if (variable
->data
.sample
)
541 info
->input_interpolate_loc
[i
] = TGSI_INTERPOLATE_LOC_SAMPLE
;
543 switch (variable
->data
.interpolation
) {
544 case INTERP_MODE_NONE
:
545 if (glsl_base_type_is_integer(base_type
)) {
546 info
->input_interpolate
[i
] = TGSI_INTERPOLATE_CONSTANT
;
550 if (semantic_name
== TGSI_SEMANTIC_COLOR
) {
551 info
->input_interpolate
[i
] = TGSI_INTERPOLATE_COLOR
;
556 case INTERP_MODE_SMOOTH
:
557 assert(!glsl_base_type_is_integer(base_type
));
559 info
->input_interpolate
[i
] = TGSI_INTERPOLATE_PERSPECTIVE
;
562 case INTERP_MODE_NOPERSPECTIVE
:
563 assert(!glsl_base_type_is_integer(base_type
));
565 info
->input_interpolate
[i
] = TGSI_INTERPOLATE_LINEAR
;
568 case INTERP_MODE_FLAT
:
569 info
->input_interpolate
[i
] = TGSI_INTERPOLATE_CONSTANT
;
575 info
->num_inputs
= nir
->num_inputs
;
576 info
->file_max
[TGSI_FILE_INPUT
] = nir
->num_inputs
- 1;
579 uint64_t processed_outputs
= 0;
580 unsigned num_outputs
= 0;
581 nir_foreach_shader_out_variable(variable
, nir
) {
582 unsigned semantic_name
, semantic_index
;
584 i
= variable
->data
.driver_location
;
586 const struct glsl_type
*type
= variable
->type
;
587 if (nir_is_per_vertex_io(variable
, nir
->info
.stage
)) {
588 assert(glsl_type_is_array(type
));
589 type
= glsl_get_array_element(type
);
592 unsigned attrib_count
= variable
->data
.compact
? DIV_ROUND_UP(glsl_get_length(type
), 4) :
593 glsl_count_attribute_slots(type
, false);
594 for (unsigned k
= 0; k
< attrib_count
; k
++, i
++) {
596 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
597 tgsi_get_gl_frag_result_semantic(variable
->data
.location
+ k
,
598 &semantic_name
, &semantic_index
);
600 /* Adjust for dual source blending */
601 if (variable
->data
.index
> 0) {
605 tgsi_get_gl_varying_semantic(variable
->data
.location
+ k
, need_texcoord
,
606 &semantic_name
, &semantic_index
);
609 unsigned num_components
= 4;
610 unsigned vector_elements
= glsl_get_vector_elements(glsl_without_array(variable
->type
));
612 num_components
= vector_elements
;
614 unsigned component
= variable
->data
.location_frac
;
615 if (glsl_type_is_64bit(glsl_without_array(variable
->type
))) {
616 if (glsl_type_is_dual_slot(glsl_without_array(variable
->type
)) && k
% 2) {
617 num_components
= (num_components
* 2) - 4;
620 num_components
= MIN2(num_components
* 2, 4);
625 for (unsigned j
= component
; j
< num_components
+ component
; j
++) {
628 usagemask
|= TGSI_WRITEMASK_X
;
631 usagemask
|= TGSI_WRITEMASK_Y
;
634 usagemask
|= TGSI_WRITEMASK_Z
;
637 usagemask
|= TGSI_WRITEMASK_W
;
640 unreachable("error calculating component index");
644 unsigned gs_out_streams
;
645 if (variable
->data
.stream
& NIR_STREAM_PACKED
) {
646 gs_out_streams
= variable
->data
.stream
& ~NIR_STREAM_PACKED
;
648 assert(variable
->data
.stream
< 4);
650 for (unsigned j
= 0; j
< num_components
; ++j
)
651 gs_out_streams
|= variable
->data
.stream
<< (2 * (component
+ j
));
654 unsigned streamx
= gs_out_streams
& 3;
655 unsigned streamy
= (gs_out_streams
>> 2) & 3;
656 unsigned streamz
= (gs_out_streams
>> 4) & 3;
657 unsigned streamw
= (gs_out_streams
>> 6) & 3;
659 if (usagemask
& TGSI_WRITEMASK_X
) {
660 info
->output_usagemask
[i
] |= TGSI_WRITEMASK_X
;
661 info
->output_streams
[i
] |= streamx
;
662 info
->num_stream_output_components
[streamx
]++;
664 if (usagemask
& TGSI_WRITEMASK_Y
) {
665 info
->output_usagemask
[i
] |= TGSI_WRITEMASK_Y
;
666 info
->output_streams
[i
] |= streamy
<< 2;
667 info
->num_stream_output_components
[streamy
]++;
669 if (usagemask
& TGSI_WRITEMASK_Z
) {
670 info
->output_usagemask
[i
] |= TGSI_WRITEMASK_Z
;
671 info
->output_streams
[i
] |= streamz
<< 4;
672 info
->num_stream_output_components
[streamz
]++;
674 if (usagemask
& TGSI_WRITEMASK_W
) {
675 info
->output_usagemask
[i
] |= TGSI_WRITEMASK_W
;
676 info
->output_streams
[i
] |= streamw
<< 6;
677 info
->num_stream_output_components
[streamw
]++;
680 /* make sure we only count this location once against
681 * the num_outputs counter.
683 if (processed_outputs
& ((uint64_t)1 << i
))
686 processed_outputs
|= ((uint64_t)1 << i
);
689 info
->output_semantic_name
[i
] = semantic_name
;
690 info
->output_semantic_index
[i
] = semantic_index
;
692 switch (semantic_name
) {
693 case TGSI_SEMANTIC_PRIMID
:
694 info
->writes_primid
= true;
696 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
697 info
->writes_viewport_index
= true;
699 case TGSI_SEMANTIC_LAYER
:
700 info
->writes_layer
= true;
702 case TGSI_SEMANTIC_PSIZE
:
703 info
->writes_psize
= true;
705 case TGSI_SEMANTIC_CLIPVERTEX
:
706 info
->writes_clipvertex
= true;
708 case TGSI_SEMANTIC_COLOR
:
709 info
->colors_written
|= 1 << semantic_index
;
711 case TGSI_SEMANTIC_STENCIL
:
712 info
->writes_stencil
= true;
714 case TGSI_SEMANTIC_SAMPLEMASK
:
715 info
->writes_samplemask
= true;
717 case TGSI_SEMANTIC_EDGEFLAG
:
718 info
->writes_edgeflag
= true;
720 case TGSI_SEMANTIC_POSITION
:
721 if (info
->processor
== PIPE_SHADER_FRAGMENT
)
722 info
->writes_z
= true;
724 info
->writes_position
= true;
728 if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
729 switch (semantic_name
) {
730 case TGSI_SEMANTIC_PATCH
:
731 info
->reads_perpatch_outputs
= true;
733 case TGSI_SEMANTIC_TESSINNER
:
734 case TGSI_SEMANTIC_TESSOUTER
:
735 info
->reads_tessfactor_outputs
= true;
738 info
->reads_pervertex_outputs
= true;
743 unsigned loc
= variable
->data
.location
;
744 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
&&
745 loc
== FRAG_RESULT_COLOR
&&
746 nir
->info
.outputs_written
& (1ull << loc
)) {
747 assert(attrib_count
== 1);
748 info
->properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] = true;
752 uint32_t sampler_mask
= 0, image_mask
= 0;
753 nir_foreach_uniform_variable(var
, nir
) {
754 uint32_t sampler_count
= glsl_type_get_sampler_count(var
->type
);
755 uint32_t image_count
= glsl_type_get_image_count(var
->type
);
756 sampler_mask
|= ((1ull << sampler_count
) - 1) << var
->data
.binding
;
757 image_mask
|= ((1ull << image_count
) - 1) << var
->data
.binding
;
759 info
->num_outputs
= num_outputs
;
761 info
->const_file_max
[0] = nir
->num_uniforms
- 1;
762 info
->const_buffers_declared
= u_bit_consecutive(1, nir
->info
.num_ubos
);
763 if (nir
->num_uniforms
> 0)
764 info
->const_buffers_declared
|= 1;
765 info
->images_declared
= image_mask
;
766 info
->samplers_declared
= sampler_mask
;
768 info
->file_max
[TGSI_FILE_SAMPLER
] = util_last_bit(info
->samplers_declared
) - 1;
769 info
->file_max
[TGSI_FILE_SAMPLER_VIEW
] = util_last_bit(nir
->info
.textures_used
) - 1;
770 info
->file_mask
[TGSI_FILE_SAMPLER
] = info
->samplers_declared
;
771 info
->file_mask
[TGSI_FILE_SAMPLER_VIEW
] = nir
->info
.textures_used
;
772 info
->file_max
[TGSI_FILE_IMAGE
] = util_last_bit(info
->images_declared
) - 1;
773 info
->file_mask
[TGSI_FILE_IMAGE
] = info
->images_declared
;
775 info
->num_written_clipdistance
= nir
->info
.clip_distance_array_size
;
776 info
->num_written_culldistance
= nir
->info
.cull_distance_array_size
;
777 info
->clipdist_writemask
= u_bit_consecutive(0, info
->num_written_clipdistance
);
778 info
->culldist_writemask
= u_bit_consecutive(0, info
->num_written_culldistance
);
780 if (info
->processor
== PIPE_SHADER_FRAGMENT
)
781 info
->uses_kill
= nir
->info
.fs
.uses_discard
;
783 func
= (struct nir_function
*)exec_list_get_head_const(&nir
->functions
);
784 nir_foreach_block(block
, func
->impl
) {
785 nir_foreach_instr(instr
, block
)
786 scan_instruction(nir
, need_texcoord
, info
, instr
);