2 * Copyright © 2014-2015 Broadcom
3 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "util/blob.h"
26 #include "util/disk_cache.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "pipe/p_screen.h"
31 #include "compiler/nir/nir.h"
32 #include "compiler/nir/nir_control_flow.h"
33 #include "compiler/nir/nir_builder.h"
34 #include "compiler/nir/nir_serialize.h"
35 #include "compiler/shader_enums.h"
37 #include "tgsi_to_nir.h"
38 #include "tgsi/tgsi_parse.h"
39 #include "tgsi/tgsi_dump.h"
40 #include "tgsi/tgsi_info.h"
41 #include "tgsi/tgsi_scan.h"
42 #include "tgsi/tgsi_from_mesa.h"
44 #define SWIZ(X, Y, Z, W) (unsigned[4]){ \
52 /** nir register containing this TGSI index. */
55 /** Offset (in vec4s) from the start of var for this TGSI index. */
60 union tgsi_full_token
*token
;
62 struct tgsi_shader_info
*scan
;
64 struct ttn_reg_info
*output_regs
;
65 struct ttn_reg_info
*temp_regs
;
66 nir_ssa_def
**imm_defs
;
68 unsigned num_samp_types
;
69 nir_alu_type
*samp_types
;
71 nir_register
*addr_reg
;
73 nir_variable
**inputs
;
74 nir_variable
**outputs
;
75 nir_variable
*samplers
[PIPE_MAX_SAMPLERS
];
76 nir_variable
*images
[PIPE_MAX_SHADER_IMAGES
];
77 nir_variable
*ssbo
[PIPE_MAX_SHADER_BUFFERS
];
79 unsigned num_samplers
;
81 unsigned num_msaa_images
;
83 nir_variable
*input_var_face
;
84 nir_variable
*input_var_position
;
85 nir_variable
*input_var_point
;
88 * Stack of nir_cursors where instructions should be pushed as we pop
89 * back out of the control flow stack.
91 * For each IF/ELSE/ENDIF block, if_stack[if_stack_pos] has where the else
92 * instructions should be placed, and if_stack[if_stack_pos - 1] has where
93 * the next instructions outside of the if/then/else block go.
96 unsigned if_stack_pos
;
99 * Stack of nir_cursors where instructions should be pushed as we pop
100 * back out of the control flow stack.
102 * loop_stack[loop_stack_pos - 1] contains the cf_node_list for the outside
105 nir_cursor
*loop_stack
;
106 unsigned loop_stack_pos
;
108 /* How many TGSI_FILE_IMMEDIATE vec4s have been parsed so far. */
111 bool cap_face_is_sysval
;
112 bool cap_position_is_sysval
;
113 bool cap_point_is_sysval
;
114 bool cap_packed_uniforms
;
115 bool cap_samplers_as_deref
;
118 #define ttn_swizzle(b, src, x, y, z, w) \
119 nir_swizzle(b, src, SWIZ(x, y, z, w), 4)
120 #define ttn_channel(b, src, swiz) \
121 nir_channel(b, src, TGSI_SWIZZLE_##swiz)
123 static gl_varying_slot
124 tgsi_varying_semantic_to_slot(unsigned semantic
, unsigned index
)
127 case TGSI_SEMANTIC_POSITION
:
128 return VARYING_SLOT_POS
;
129 case TGSI_SEMANTIC_COLOR
:
131 return VARYING_SLOT_COL0
;
133 return VARYING_SLOT_COL1
;
134 case TGSI_SEMANTIC_BCOLOR
:
136 return VARYING_SLOT_BFC0
;
138 return VARYING_SLOT_BFC1
;
139 case TGSI_SEMANTIC_FOG
:
140 return VARYING_SLOT_FOGC
;
141 case TGSI_SEMANTIC_PSIZE
:
142 return VARYING_SLOT_PSIZ
;
143 case TGSI_SEMANTIC_GENERIC
:
145 return VARYING_SLOT_VAR0
+ index
;
146 case TGSI_SEMANTIC_FACE
:
147 return VARYING_SLOT_FACE
;
148 case TGSI_SEMANTIC_EDGEFLAG
:
149 return VARYING_SLOT_EDGE
;
150 case TGSI_SEMANTIC_PRIMID
:
151 return VARYING_SLOT_PRIMITIVE_ID
;
152 case TGSI_SEMANTIC_CLIPDIST
:
154 return VARYING_SLOT_CLIP_DIST0
;
156 return VARYING_SLOT_CLIP_DIST1
;
157 case TGSI_SEMANTIC_CLIPVERTEX
:
158 return VARYING_SLOT_CLIP_VERTEX
;
159 case TGSI_SEMANTIC_TEXCOORD
:
161 return VARYING_SLOT_TEX0
+ index
;
162 case TGSI_SEMANTIC_PCOORD
:
163 return VARYING_SLOT_PNTC
;
164 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
165 return VARYING_SLOT_VIEWPORT
;
166 case TGSI_SEMANTIC_LAYER
:
167 return VARYING_SLOT_LAYER
;
168 case TGSI_SEMANTIC_TESSINNER
:
169 return VARYING_SLOT_TESS_LEVEL_INNER
;
170 case TGSI_SEMANTIC_TESSOUTER
:
171 return VARYING_SLOT_TESS_LEVEL_OUTER
;
173 fprintf(stderr
, "Bad TGSI semantic: %d/%d\n", semantic
, index
);
178 static enum gl_frag_depth_layout
179 ttn_get_depth_layout(unsigned tgsi_fs_depth_layout
)
181 switch (tgsi_fs_depth_layout
) {
182 case TGSI_FS_DEPTH_LAYOUT_NONE
:
183 return FRAG_DEPTH_LAYOUT_NONE
;
184 case TGSI_FS_DEPTH_LAYOUT_ANY
:
185 return FRAG_DEPTH_LAYOUT_ANY
;
186 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
187 return FRAG_DEPTH_LAYOUT_GREATER
;
188 case TGSI_FS_DEPTH_LAYOUT_LESS
:
189 return FRAG_DEPTH_LAYOUT_LESS
;
190 case TGSI_FS_DEPTH_LAYOUT_UNCHANGED
:
191 return FRAG_DEPTH_LAYOUT_UNCHANGED
;
193 unreachable("bad TGSI FS depth layout");
198 ttn_src_for_dest(nir_builder
*b
, nir_alu_dest
*dest
)
201 memset(&src
, 0, sizeof(src
));
203 if (dest
->dest
.is_ssa
)
204 src
.src
= nir_src_for_ssa(&dest
->dest
.ssa
);
206 assert(!dest
->dest
.reg
.indirect
);
207 src
.src
= nir_src_for_reg(dest
->dest
.reg
.reg
);
208 src
.src
.reg
.base_offset
= dest
->dest
.reg
.base_offset
;
211 for (int i
= 0; i
< 4; i
++)
214 return nir_mov_alu(b
, src
, 4);
217 static enum glsl_interp_mode
218 ttn_translate_interp_mode(unsigned tgsi_interp
)
220 switch (tgsi_interp
) {
221 case TGSI_INTERPOLATE_CONSTANT
:
222 return INTERP_MODE_FLAT
;
223 case TGSI_INTERPOLATE_LINEAR
:
224 return INTERP_MODE_NOPERSPECTIVE
;
225 case TGSI_INTERPOLATE_PERSPECTIVE
:
226 return INTERP_MODE_SMOOTH
;
227 case TGSI_INTERPOLATE_COLOR
:
228 return INTERP_MODE_NONE
;
230 unreachable("bad TGSI interpolation mode");
235 ttn_emit_declaration(struct ttn_compile
*c
)
237 nir_builder
*b
= &c
->build
;
238 struct tgsi_full_declaration
*decl
= &c
->token
->FullDeclaration
;
239 unsigned array_size
= decl
->Range
.Last
- decl
->Range
.First
+ 1;
240 unsigned file
= decl
->Declaration
.File
;
243 if (file
== TGSI_FILE_TEMPORARY
) {
244 if (decl
->Declaration
.Array
) {
245 /* for arrays, we create variables instead of registers: */
247 nir_variable_create(b
->shader
, nir_var_shader_temp
,
248 glsl_array_type(glsl_vec4_type(), array_size
, 0),
249 ralloc_asprintf(b
->shader
, "arr_%d",
250 decl
->Array
.ArrayID
));
252 for (i
= 0; i
< array_size
; i
++) {
253 /* point all the matching slots to the same var,
254 * with appropriate offset set, mostly just so
255 * we know what to do when tgsi does a non-indirect
258 c
->temp_regs
[decl
->Range
.First
+ i
].reg
= NULL
;
259 c
->temp_regs
[decl
->Range
.First
+ i
].var
= var
;
260 c
->temp_regs
[decl
->Range
.First
+ i
].offset
= i
;
263 for (i
= 0; i
< array_size
; i
++) {
264 nir_register
*reg
= nir_local_reg_create(b
->impl
);
265 reg
->num_components
= 4;
266 c
->temp_regs
[decl
->Range
.First
+ i
].reg
= reg
;
267 c
->temp_regs
[decl
->Range
.First
+ i
].var
= NULL
;
268 c
->temp_regs
[decl
->Range
.First
+ i
].offset
= 0;
271 } else if (file
== TGSI_FILE_ADDRESS
) {
272 c
->addr_reg
= nir_local_reg_create(b
->impl
);
273 c
->addr_reg
->num_components
= 4;
274 } else if (file
== TGSI_FILE_SYSTEM_VALUE
) {
275 /* Nothing to record for system values. */
276 } else if (file
== TGSI_FILE_BUFFER
) {
277 /* Nothing to record for buffers. */
278 } else if (file
== TGSI_FILE_IMAGE
) {
279 /* Nothing to record for images. */
280 } else if (file
== TGSI_FILE_SAMPLER
) {
281 /* Nothing to record for samplers. */
282 } else if (file
== TGSI_FILE_SAMPLER_VIEW
) {
283 struct tgsi_declaration_sampler_view
*sview
= &decl
->SamplerView
;
286 assert((sview
->ReturnTypeX
== sview
->ReturnTypeY
) &&
287 (sview
->ReturnTypeX
== sview
->ReturnTypeZ
) &&
288 (sview
->ReturnTypeX
== sview
->ReturnTypeW
));
290 switch (sview
->ReturnTypeX
) {
291 case TGSI_RETURN_TYPE_SINT
:
294 case TGSI_RETURN_TYPE_UINT
:
295 type
= nir_type_uint
;
297 case TGSI_RETURN_TYPE_FLOAT
:
299 type
= nir_type_float
;
303 for (i
= 0; i
< array_size
; i
++) {
304 c
->samp_types
[decl
->Range
.First
+ i
] = type
;
307 bool is_array
= (array_size
> 1);
309 assert(file
== TGSI_FILE_INPUT
||
310 file
== TGSI_FILE_OUTPUT
||
311 file
== TGSI_FILE_CONSTANT
);
313 /* nothing to do for UBOs: */
314 if ((file
== TGSI_FILE_CONSTANT
) && decl
->Declaration
.Dimension
&&
315 decl
->Dim
.Index2D
!= 0) {
316 b
->shader
->info
.num_ubos
=
317 MAX2(b
->shader
->info
.num_ubos
, decl
->Dim
.Index2D
);
321 if ((file
== TGSI_FILE_INPUT
) || (file
== TGSI_FILE_OUTPUT
)) {
322 is_array
= (is_array
&& decl
->Declaration
.Array
&&
323 (decl
->Array
.ArrayID
!= 0));
326 for (i
= 0; i
< array_size
; i
++) {
327 unsigned idx
= decl
->Range
.First
+ i
;
328 nir_variable
*var
= rzalloc(b
->shader
, nir_variable
);
330 var
->data
.driver_location
= idx
;
332 var
->type
= glsl_vec4_type();
334 var
->type
= glsl_array_type(var
->type
, array_size
, 0);
337 case TGSI_FILE_INPUT
:
338 var
->data
.read_only
= true;
339 var
->data
.mode
= nir_var_shader_in
;
340 var
->name
= ralloc_asprintf(var
, "in_%d", idx
);
342 if (c
->scan
->processor
== PIPE_SHADER_FRAGMENT
) {
343 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_FACE
) {
344 var
->type
= glsl_bool_type();
345 if (c
->cap_face_is_sysval
) {
346 var
->data
.mode
= nir_var_system_value
;
347 var
->data
.location
= SYSTEM_VALUE_FRONT_FACE
;
349 var
->data
.location
= VARYING_SLOT_FACE
;
351 c
->input_var_face
= var
;
352 } else if (decl
->Semantic
.Name
== TGSI_SEMANTIC_POSITION
) {
353 if (c
->cap_position_is_sysval
) {
354 var
->data
.mode
= nir_var_system_value
;
355 var
->data
.location
= SYSTEM_VALUE_FRAG_COORD
;
357 var
->data
.location
= VARYING_SLOT_POS
;
359 c
->input_var_position
= var
;
360 } else if (decl
->Semantic
.Name
== TGSI_SEMANTIC_PCOORD
) {
361 if (c
->cap_point_is_sysval
) {
362 var
->data
.mode
= nir_var_system_value
;
363 var
->data
.location
= SYSTEM_VALUE_POINT_COORD
;
365 var
->data
.location
= VARYING_SLOT_PNTC
;
367 c
->input_var_point
= var
;
370 tgsi_varying_semantic_to_slot(decl
->Semantic
.Name
,
371 decl
->Semantic
.Index
);
374 assert(!decl
->Declaration
.Semantic
);
375 var
->data
.location
= VERT_ATTRIB_GENERIC0
+ idx
;
378 var
->data
.interpolation
=
379 ttn_translate_interp_mode(decl
->Interp
.Interpolate
);
381 c
->inputs
[idx
] = var
;
383 for (int i
= 0; i
< array_size
; i
++)
384 b
->shader
->info
.inputs_read
|= 1 << (var
->data
.location
+ i
);
387 case TGSI_FILE_OUTPUT
: {
388 int semantic_name
= decl
->Semantic
.Name
;
389 int semantic_index
= decl
->Semantic
.Index
;
390 /* Since we can't load from outputs in the IR, we make temporaries
391 * for the outputs and emit stores to the real outputs at the end of
394 nir_register
*reg
= nir_local_reg_create(b
->impl
);
395 reg
->num_components
= 4;
397 reg
->num_array_elems
= array_size
;
399 var
->data
.mode
= nir_var_shader_out
;
400 var
->name
= ralloc_asprintf(var
, "out_%d", idx
);
402 var
->data
.interpolation
=
403 ttn_translate_interp_mode(decl
->Interp
.Interpolate
);
404 var
->data
.patch
= semantic_name
== TGSI_SEMANTIC_TESSINNER
||
405 semantic_name
== TGSI_SEMANTIC_TESSOUTER
||
406 semantic_name
== TGSI_SEMANTIC_PATCH
;
408 if (c
->scan
->processor
== PIPE_SHADER_FRAGMENT
) {
409 switch (semantic_name
) {
410 case TGSI_SEMANTIC_COLOR
: {
411 /* TODO tgsi loses some information, so we cannot
412 * actually differentiate here between DSB and MRT
413 * at this point. But so far no drivers using tgsi-
414 * to-nir support dual source blend:
416 bool dual_src_blend
= false;
417 if (dual_src_blend
&& (semantic_index
== 1)) {
418 var
->data
.location
= FRAG_RESULT_DATA0
;
421 if (c
->scan
->properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
])
422 var
->data
.location
= FRAG_RESULT_COLOR
;
424 var
->data
.location
= FRAG_RESULT_DATA0
+ semantic_index
;
428 case TGSI_SEMANTIC_POSITION
:
429 var
->data
.location
= FRAG_RESULT_DEPTH
;
430 var
->type
= glsl_float_type();
432 case TGSI_SEMANTIC_STENCIL
:
433 var
->data
.location
= FRAG_RESULT_STENCIL
;
434 var
->type
= glsl_int_type();
437 fprintf(stderr
, "Bad TGSI semantic: %d/%d\n",
438 decl
->Semantic
.Name
, decl
->Semantic
.Index
);
443 tgsi_varying_semantic_to_slot(semantic_name
, semantic_index
);
444 if (var
->data
.location
== VARYING_SLOT_FOGC
||
445 var
->data
.location
== VARYING_SLOT_PSIZ
) {
446 var
->type
= glsl_float_type();
452 for (j
= 0; j
< array_size
; j
++) {
453 c
->output_regs
[idx
+ j
].offset
= i
+ j
;
454 c
->output_regs
[idx
+ j
].reg
= reg
;
457 c
->output_regs
[idx
].offset
= i
;
458 c
->output_regs
[idx
].reg
= reg
;
461 c
->outputs
[idx
] = var
;
463 for (int i
= 0; i
< array_size
; i
++)
464 b
->shader
->info
.outputs_written
|= 1ull << (var
->data
.location
+ i
);
467 case TGSI_FILE_CONSTANT
:
468 var
->data
.mode
= nir_var_uniform
;
469 var
->name
= ralloc_asprintf(var
, "uniform_%d", idx
);
470 var
->data
.location
= idx
;
473 unreachable("bad declaration file");
477 nir_shader_add_variable(b
->shader
, var
);
487 ttn_emit_immediate(struct ttn_compile
*c
)
489 nir_builder
*b
= &c
->build
;
490 struct tgsi_full_immediate
*tgsi_imm
= &c
->token
->FullImmediate
;
491 nir_load_const_instr
*load_const
;
494 load_const
= nir_load_const_instr_create(b
->shader
, 4, 32);
495 c
->imm_defs
[c
->next_imm
] = &load_const
->def
;
498 for (i
= 0; i
< load_const
->def
.num_components
; i
++)
499 load_const
->value
[i
].u32
= tgsi_imm
->u
[i
].Uint
;
501 nir_builder_instr_insert(b
, &load_const
->instr
);
505 ttn_src_for_indirect(struct ttn_compile
*c
, struct tgsi_ind_register
*indirect
);
507 /* generate either a constant or indirect deref chain for accessing an
510 static nir_deref_instr
*
511 ttn_array_deref(struct ttn_compile
*c
, nir_variable
*var
, unsigned offset
,
512 struct tgsi_ind_register
*indirect
)
514 nir_deref_instr
*deref
= nir_build_deref_var(&c
->build
, var
);
515 nir_ssa_def
*index
= nir_imm_int(&c
->build
, offset
);
517 index
= nir_iadd(&c
->build
, index
, ttn_src_for_indirect(c
, indirect
));
518 return nir_build_deref_array(&c
->build
, deref
, index
);
521 /* Special case: Turn the frontface varying into a load of the
522 * frontface variable, and create the vector as required by TGSI.
525 ttn_emulate_tgsi_front_face(struct ttn_compile
*c
)
527 nir_ssa_def
*tgsi_frontface
[4];
529 if (c
->cap_face_is_sysval
) {
530 /* When it's a system value, it should be an integer vector: (F, 0, 0, 1)
531 * F is 0xffffffff if front-facing, 0 if not.
534 nir_ssa_def
*frontface
= nir_load_front_face(&c
->build
, 1);
536 tgsi_frontface
[0] = nir_bcsel(&c
->build
,
538 nir_imm_int(&c
->build
, 0xffffffff),
539 nir_imm_int(&c
->build
, 0));
540 tgsi_frontface
[1] = nir_imm_int(&c
->build
, 0);
541 tgsi_frontface
[2] = nir_imm_int(&c
->build
, 0);
542 tgsi_frontface
[3] = nir_imm_int(&c
->build
, 1);
544 /* When it's an input, it should be a float vector: (F, 0.0, 0.0, 1.0)
545 * F is positive if front-facing, negative if not.
548 assert(c
->input_var_face
);
549 nir_ssa_def
*frontface
= nir_load_var(&c
->build
, c
->input_var_face
);
551 tgsi_frontface
[0] = nir_bcsel(&c
->build
,
553 nir_imm_float(&c
->build
, 1.0),
554 nir_imm_float(&c
->build
, -1.0));
555 tgsi_frontface
[1] = nir_imm_float(&c
->build
, 0.0);
556 tgsi_frontface
[2] = nir_imm_float(&c
->build
, 0.0);
557 tgsi_frontface
[3] = nir_imm_float(&c
->build
, 1.0);
560 return nir_vec(&c
->build
, tgsi_frontface
, 4);
564 ttn_src_for_file_and_index(struct ttn_compile
*c
, unsigned file
, unsigned index
,
565 struct tgsi_ind_register
*indirect
,
566 struct tgsi_dimension
*dim
,
567 struct tgsi_ind_register
*dimind
,
570 nir_builder
*b
= &c
->build
;
573 memset(&src
, 0, sizeof(src
));
576 case TGSI_FILE_TEMPORARY
:
577 if (c
->temp_regs
[index
].var
) {
578 unsigned offset
= c
->temp_regs
[index
].offset
;
579 nir_variable
*var
= c
->temp_regs
[index
].var
;
580 nir_ssa_def
*load
= nir_load_deref(&c
->build
,
581 ttn_array_deref(c
, var
, offset
, indirect
));
583 src
= nir_src_for_ssa(load
);
586 src
.reg
.reg
= c
->temp_regs
[index
].reg
;
591 case TGSI_FILE_ADDRESS
:
592 src
.reg
.reg
= c
->addr_reg
;
596 case TGSI_FILE_IMMEDIATE
:
597 src
= nir_src_for_ssa(c
->imm_defs
[index
]);
602 case TGSI_FILE_SYSTEM_VALUE
: {
609 switch (c
->scan
->system_value_semantic_name
[index
]) {
610 case TGSI_SEMANTIC_VERTEXID_NOBASE
:
611 op
= nir_intrinsic_load_vertex_id_zero_base
;
612 load
= nir_load_vertex_id_zero_base(b
);
614 case TGSI_SEMANTIC_VERTEXID
:
615 op
= nir_intrinsic_load_vertex_id
;
616 load
= nir_load_vertex_id(b
);
618 case TGSI_SEMANTIC_BASEVERTEX
:
619 op
= nir_intrinsic_load_base_vertex
;
620 load
= nir_load_base_vertex(b
);
622 case TGSI_SEMANTIC_INSTANCEID
:
623 op
= nir_intrinsic_load_instance_id
;
624 load
= nir_load_instance_id(b
);
626 case TGSI_SEMANTIC_FACE
:
627 assert(c
->cap_face_is_sysval
);
628 op
= nir_intrinsic_load_front_face
;
629 load
= ttn_emulate_tgsi_front_face(c
);
631 case TGSI_SEMANTIC_POSITION
:
632 assert(c
->cap_position_is_sysval
);
633 op
= nir_intrinsic_load_frag_coord
;
634 load
= nir_load_frag_coord(b
);
636 case TGSI_SEMANTIC_PCOORD
:
637 assert(c
->cap_point_is_sysval
);
638 op
= nir_intrinsic_load_point_coord
;
639 load
= nir_load_point_coord(b
);
641 case TGSI_SEMANTIC_THREAD_ID
:
642 op
= nir_intrinsic_load_local_invocation_id
;
643 load
= nir_load_local_invocation_id(b
);
645 case TGSI_SEMANTIC_BLOCK_ID
:
646 op
= nir_intrinsic_load_work_group_id
;
647 load
= nir_load_work_group_id(b
, 32);
649 case TGSI_SEMANTIC_BLOCK_SIZE
:
650 op
= nir_intrinsic_load_local_group_size
;
651 load
= nir_load_local_group_size(b
);
653 case TGSI_SEMANTIC_CS_USER_DATA_AMD
:
654 op
= nir_intrinsic_load_user_data_amd
;
655 load
= nir_load_user_data_amd(b
);
657 case TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL
:
658 op
= nir_intrinsic_load_tess_level_inner_default
;
659 load
= nir_load_tess_level_inner_default(b
);
661 case TGSI_SEMANTIC_TESS_DEFAULT_OUTER_LEVEL
:
662 op
= nir_intrinsic_load_tess_level_outer_default
;
663 load
= nir_load_tess_level_outer_default(b
);
666 unreachable("bad system value");
669 if (load
->num_components
== 2)
670 load
= nir_swizzle(b
, load
, SWIZ(X
, Y
, Y
, Y
), 4);
671 else if (load
->num_components
== 3)
672 load
= nir_swizzle(b
, load
, SWIZ(X
, Y
, Z
, Z
), 4);
674 src
= nir_src_for_ssa(load
);
675 b
->shader
->info
.system_values_read
|=
676 (1ull << nir_system_value_from_intrinsic(op
));
681 case TGSI_FILE_INPUT
:
682 if (c
->scan
->processor
== PIPE_SHADER_FRAGMENT
&&
683 c
->scan
->input_semantic_name
[index
] == TGSI_SEMANTIC_FACE
) {
684 assert(!c
->cap_face_is_sysval
&& c
->input_var_face
);
685 return nir_src_for_ssa(ttn_emulate_tgsi_front_face(c
));
686 } else if (c
->scan
->processor
== PIPE_SHADER_FRAGMENT
&&
687 c
->scan
->input_semantic_name
[index
] == TGSI_SEMANTIC_POSITION
) {
688 assert(!c
->cap_position_is_sysval
&& c
->input_var_position
);
689 return nir_src_for_ssa(nir_load_var(&c
->build
, c
->input_var_position
));
690 } else if (c
->scan
->processor
== PIPE_SHADER_FRAGMENT
&&
691 c
->scan
->input_semantic_name
[index
] == TGSI_SEMANTIC_PCOORD
) {
692 assert(!c
->cap_point_is_sysval
&& c
->input_var_point
);
693 return nir_src_for_ssa(nir_load_var(&c
->build
, c
->input_var_point
));
695 /* Indirection on input arrays isn't supported by TTN. */
697 nir_deref_instr
*deref
= nir_build_deref_var(&c
->build
,
699 return nir_src_for_ssa(nir_load_deref(&c
->build
, deref
));
703 case TGSI_FILE_CONSTANT
: {
704 nir_intrinsic_instr
*load
;
708 if (dim
&& (dim
->Index
> 0 || dim
->Indirect
)) {
709 op
= nir_intrinsic_load_ubo
;
711 op
= nir_intrinsic_load_uniform
;
714 load
= nir_intrinsic_instr_create(b
->shader
, op
);
715 if (op
== nir_intrinsic_load_uniform
) {
716 nir_intrinsic_set_type(load
, src_is_float
? nir_type_float
:
720 load
->num_components
= 4;
721 if (dim
&& (dim
->Index
> 0 || dim
->Indirect
)) {
724 ttn_src_for_file_and_index(c
, dimind
->File
, dimind
->Index
,
725 NULL
, NULL
, NULL
, false);
727 /* UBOs start at index 1 in TGSI: */
729 nir_src_for_ssa(nir_imm_int(b
, dim
->Index
- 1));
735 if (op
== nir_intrinsic_load_ubo
) {
736 /* UBO loads don't have a base offset. */
737 offset
= nir_imm_int(b
, index
);
739 offset
= nir_iadd(b
, offset
, ttn_src_for_indirect(c
, indirect
));
741 /* UBO offsets are in bytes, but TGSI gives them to us in vec4's */
742 offset
= nir_ishl(b
, offset
, nir_imm_int(b
, 4));
743 nir_intrinsic_set_align(load
, 16, 0);
745 nir_intrinsic_set_base(load
, index
);
747 offset
= ttn_src_for_indirect(c
, indirect
);
749 offset
= nir_imm_int(b
, 0);
752 load
->src
[srcn
++] = nir_src_for_ssa(offset
);
754 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 4, 32, NULL
);
755 nir_builder_instr_insert(b
, &load
->instr
);
757 src
= nir_src_for_ssa(&load
->dest
.ssa
);
762 unreachable("bad src file");
770 ttn_src_for_indirect(struct ttn_compile
*c
, struct tgsi_ind_register
*indirect
)
772 nir_builder
*b
= &c
->build
;
774 memset(&src
, 0, sizeof(src
));
775 for (int i
= 0; i
< 4; i
++)
776 src
.swizzle
[i
] = indirect
->Swizzle
;
777 src
.src
= ttn_src_for_file_and_index(c
,
782 return nir_mov_alu(b
, src
, 1);
786 ttn_get_dest(struct ttn_compile
*c
, struct tgsi_full_dst_register
*tgsi_fdst
)
788 struct tgsi_dst_register
*tgsi_dst
= &tgsi_fdst
->Register
;
790 unsigned index
= tgsi_dst
->Index
;
792 memset(&dest
, 0, sizeof(dest
));
794 if (tgsi_dst
->File
== TGSI_FILE_TEMPORARY
) {
795 if (c
->temp_regs
[index
].var
) {
798 /* this works, because TGSI will give us a base offset
799 * (in case of indirect index) that points back into
800 * the array. Access can be direct or indirect, we
801 * don't really care. Just create a one-shot dst reg
802 * that will get store_var'd back into the array var
803 * at the end of ttn_emit_instruction()
805 reg
= nir_local_reg_create(c
->build
.impl
);
806 reg
->num_components
= 4;
807 dest
.dest
.reg
.reg
= reg
;
808 dest
.dest
.reg
.base_offset
= 0;
810 assert(!tgsi_dst
->Indirect
);
811 dest
.dest
.reg
.reg
= c
->temp_regs
[index
].reg
;
812 dest
.dest
.reg
.base_offset
= c
->temp_regs
[index
].offset
;
814 } else if (tgsi_dst
->File
== TGSI_FILE_OUTPUT
) {
815 dest
.dest
.reg
.reg
= c
->output_regs
[index
].reg
;
816 dest
.dest
.reg
.base_offset
= c
->output_regs
[index
].offset
;
817 } else if (tgsi_dst
->File
== TGSI_FILE_ADDRESS
) {
819 dest
.dest
.reg
.reg
= c
->addr_reg
;
822 dest
.write_mask
= tgsi_dst
->WriteMask
;
823 dest
.saturate
= false;
825 if (tgsi_dst
->Indirect
&& (tgsi_dst
->File
!= TGSI_FILE_TEMPORARY
)) {
826 nir_src
*indirect
= ralloc(c
->build
.shader
, nir_src
);
827 *indirect
= nir_src_for_ssa(ttn_src_for_indirect(c
, &tgsi_fdst
->Indirect
));
828 dest
.dest
.reg
.indirect
= indirect
;
834 static nir_variable
*
835 ttn_get_var(struct ttn_compile
*c
, struct tgsi_full_dst_register
*tgsi_fdst
)
837 struct tgsi_dst_register
*tgsi_dst
= &tgsi_fdst
->Register
;
838 unsigned index
= tgsi_dst
->Index
;
840 if (tgsi_dst
->File
== TGSI_FILE_TEMPORARY
) {
841 /* we should not have an indirect when there is no var! */
842 if (!c
->temp_regs
[index
].var
)
843 assert(!tgsi_dst
->Indirect
);
844 return c
->temp_regs
[index
].var
;
851 ttn_get_src(struct ttn_compile
*c
, struct tgsi_full_src_register
*tgsi_fsrc
,
854 nir_builder
*b
= &c
->build
;
855 struct tgsi_src_register
*tgsi_src
= &tgsi_fsrc
->Register
;
856 enum tgsi_opcode opcode
= c
->token
->FullInstruction
.Instruction
.Opcode
;
857 unsigned tgsi_src_type
= tgsi_opcode_infer_src_type(opcode
, src_idx
);
858 bool src_is_float
= (tgsi_src_type
== TGSI_TYPE_FLOAT
||
859 tgsi_src_type
== TGSI_TYPE_DOUBLE
||
860 tgsi_src_type
== TGSI_TYPE_UNTYPED
);
863 memset(&src
, 0, sizeof(src
));
865 if (tgsi_src
->File
== TGSI_FILE_NULL
) {
866 return nir_imm_float(b
, 0.0);
867 } else if (tgsi_src
->File
== TGSI_FILE_SAMPLER
||
868 tgsi_src
->File
== TGSI_FILE_IMAGE
||
869 tgsi_src
->File
== TGSI_FILE_BUFFER
) {
870 /* Only the index of the resource gets used in texturing, and it will
871 * handle looking that up on its own instead of using the nir_alu_src.
873 assert(!tgsi_src
->Indirect
);
876 struct tgsi_ind_register
*ind
= NULL
;
877 struct tgsi_dimension
*dim
= NULL
;
878 struct tgsi_ind_register
*dimind
= NULL
;
879 if (tgsi_src
->Indirect
)
880 ind
= &tgsi_fsrc
->Indirect
;
881 if (tgsi_src
->Dimension
) {
882 dim
= &tgsi_fsrc
->Dimension
;
884 dimind
= &tgsi_fsrc
->DimIndirect
;
886 src
.src
= ttn_src_for_file_and_index(c
,
893 src
.swizzle
[0] = tgsi_src
->SwizzleX
;
894 src
.swizzle
[1] = tgsi_src
->SwizzleY
;
895 src
.swizzle
[2] = tgsi_src
->SwizzleZ
;
896 src
.swizzle
[3] = tgsi_src
->SwizzleW
;
898 nir_ssa_def
*def
= nir_mov_alu(b
, src
, 4);
900 if (tgsi_type_is_64bit(tgsi_src_type
))
901 def
= nir_bitcast_vector(b
, def
, 64);
903 if (tgsi_src
->Absolute
) {
905 def
= nir_fabs(b
, def
);
907 def
= nir_iabs(b
, def
);
910 if (tgsi_src
->Negate
) {
912 def
= nir_fneg(b
, def
);
914 def
= nir_ineg(b
, def
);
921 ttn_move_dest_masked(nir_builder
*b
, nir_alu_dest dest
,
922 nir_ssa_def
*def
, unsigned write_mask
)
924 if (!(dest
.write_mask
& write_mask
))
927 nir_alu_instr
*mov
= nir_alu_instr_create(b
->shader
, nir_op_mov
);
929 mov
->dest
.write_mask
&= write_mask
;
930 mov
->src
[0].src
= nir_src_for_ssa(def
);
931 for (unsigned i
= def
->num_components
; i
< 4; i
++)
932 mov
->src
[0].swizzle
[i
] = def
->num_components
- 1;
933 nir_builder_instr_insert(b
, &mov
->instr
);
937 ttn_move_dest(nir_builder
*b
, nir_alu_dest dest
, nir_ssa_def
*def
)
939 ttn_move_dest_masked(b
, dest
, def
, TGSI_WRITEMASK_XYZW
);
943 ttn_alu(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, unsigned dest_bitsize
,
946 nir_ssa_def
*def
= nir_build_alu_src_arr(b
, op
, src
);
947 if (def
->bit_size
== 1)
948 def
= nir_ineg(b
, nir_b2i(b
, def
, dest_bitsize
));
949 assert(def
->bit_size
== dest_bitsize
);
950 if (dest_bitsize
== 64) {
951 if (def
->num_components
> 2) {
952 /* 32 -> 64 bit conversion ops are supposed to only convert the first
953 * two components, and we need to truncate here to avoid creating a
954 * vec8 after bitcasting the destination.
956 def
= nir_channels(b
, def
, 0x3);
958 def
= nir_bitcast_vector(b
, def
, 32);
960 ttn_move_dest(b
, dest
, def
);
964 ttn_arl(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
966 ttn_move_dest(b
, dest
, nir_f2i32(b
, nir_ffloor(b
, src
[0])));
969 /* EXP - Approximate Exponential Base 2
970 * dst.x = 2^{\lfloor src.x\rfloor}
971 * dst.y = src.x - \lfloor src.x\rfloor
976 ttn_exp(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
978 nir_ssa_def
*srcx
= ttn_channel(b
, src
[0], X
);
980 ttn_move_dest_masked(b
, dest
, nir_fexp2(b
, nir_ffloor(b
, srcx
)),
982 ttn_move_dest_masked(b
, dest
, nir_fsub(b
, srcx
, nir_ffloor(b
, srcx
)),
984 ttn_move_dest_masked(b
, dest
, nir_fexp2(b
, srcx
), TGSI_WRITEMASK_Z
);
985 ttn_move_dest_masked(b
, dest
, nir_imm_float(b
, 1.0), TGSI_WRITEMASK_W
);
988 /* LOG - Approximate Logarithm Base 2
989 * dst.x = \lfloor\log_2{|src.x|}\rfloor
990 * dst.y = \frac{|src.x|}{2^{\lfloor\log_2{|src.x|}\rfloor}}
991 * dst.z = \log_2{|src.x|}
995 ttn_log(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
997 nir_ssa_def
*abs_srcx
= nir_fabs(b
, ttn_channel(b
, src
[0], X
));
998 nir_ssa_def
*log2
= nir_flog2(b
, abs_srcx
);
1000 ttn_move_dest_masked(b
, dest
, nir_ffloor(b
, log2
), TGSI_WRITEMASK_X
);
1001 ttn_move_dest_masked(b
, dest
,
1002 nir_fdiv(b
, abs_srcx
, nir_fexp2(b
, nir_ffloor(b
, log2
))),
1004 ttn_move_dest_masked(b
, dest
, nir_flog2(b
, abs_srcx
), TGSI_WRITEMASK_Z
);
1005 ttn_move_dest_masked(b
, dest
, nir_imm_float(b
, 1.0), TGSI_WRITEMASK_W
);
1008 /* DST - Distance Vector
1010 * dst.y = src0.y \times src1.y
1015 ttn_dst(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
1017 ttn_move_dest_masked(b
, dest
, nir_imm_float(b
, 1.0), TGSI_WRITEMASK_X
);
1018 ttn_move_dest_masked(b
, dest
, nir_fmul(b
, src
[0], src
[1]), TGSI_WRITEMASK_Y
);
1019 ttn_move_dest_masked(b
, dest
, nir_mov(b
, src
[0]), TGSI_WRITEMASK_Z
);
1020 ttn_move_dest_masked(b
, dest
, nir_mov(b
, src
[1]), TGSI_WRITEMASK_W
);
1023 /* LIT - Light Coefficients
1025 * dst.y = max(src.x, 0.0)
1026 * dst.z = (src.x > 0.0) ? max(src.y, 0.0)^{clamp(src.w, -128.0, 128.0))} : 0
1030 ttn_lit(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
1032 ttn_move_dest_masked(b
, dest
, nir_imm_float(b
, 1.0), TGSI_WRITEMASK_XW
);
1034 ttn_move_dest_masked(b
, dest
, nir_fmax(b
, ttn_channel(b
, src
[0], X
),
1035 nir_imm_float(b
, 0.0)), TGSI_WRITEMASK_Y
);
1037 if (dest
.write_mask
& TGSI_WRITEMASK_Z
) {
1038 nir_ssa_def
*src0_y
= ttn_channel(b
, src
[0], Y
);
1039 nir_ssa_def
*wclamp
= nir_fmax(b
, nir_fmin(b
, ttn_channel(b
, src
[0], W
),
1040 nir_imm_float(b
, 128.0)),
1041 nir_imm_float(b
, -128.0));
1042 nir_ssa_def
*pow
= nir_fpow(b
, nir_fmax(b
, src0_y
, nir_imm_float(b
, 0.0)),
1045 ttn_move_dest_masked(b
, dest
,
1048 ttn_channel(b
, src
[0], X
),
1049 nir_imm_float(b
, 0.0)),
1050 nir_imm_float(b
, 0.0),
1057 ttn_sle(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
1059 ttn_move_dest(b
, dest
, nir_sge(b
, src
[1], src
[0]));
1063 ttn_sgt(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
1065 ttn_move_dest(b
, dest
, nir_slt(b
, src
[1], src
[0]));
1069 ttn_dp2(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
1071 ttn_move_dest(b
, dest
, nir_fdot2(b
, src
[0], src
[1]));
1075 ttn_dp3(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
1077 ttn_move_dest(b
, dest
, nir_fdot3(b
, src
[0], src
[1]));
1081 ttn_dp4(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
1083 ttn_move_dest(b
, dest
, nir_fdot4(b
, src
[0], src
[1]));
1087 ttn_umad(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
1089 ttn_move_dest(b
, dest
, nir_iadd(b
, nir_imul(b
, src
[0], src
[1]), src
[2]));
1093 ttn_arr(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
1095 ttn_move_dest(b
, dest
, nir_f2i32(b
, nir_fround_even(b
, src
[0])));
1099 ttn_cmp(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
1101 ttn_move_dest(b
, dest
, nir_bcsel(b
,
1102 nir_flt(b
, src
[0], nir_imm_float(b
, 0.0)),
1107 ttn_ucmp(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
1109 ttn_move_dest(b
, dest
, nir_bcsel(b
,
1110 nir_ine(b
, src
[0], nir_imm_int(b
, 0)),
1115 ttn_barrier(nir_builder
*b
)
1117 nir_intrinsic_instr
*barrier
=
1118 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_control_barrier
);
1119 nir_builder_instr_insert(b
, &barrier
->instr
);
1123 ttn_kill(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
1125 nir_intrinsic_instr
*discard
=
1126 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_discard
);
1127 nir_builder_instr_insert(b
, &discard
->instr
);
1128 b
->shader
->info
.fs
.uses_discard
= true;
1132 ttn_kill_if(nir_builder
*b
, nir_op op
, nir_alu_dest dest
, nir_ssa_def
**src
)
1134 /* flt must be exact, because NaN shouldn't discard. (apps rely on this) */
1136 nir_ssa_def
*cmp
= nir_bany(b
, nir_flt(b
, src
[0], nir_imm_float(b
, 0.0)));
1139 nir_intrinsic_instr
*discard
=
1140 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_discard_if
);
1141 discard
->src
[0] = nir_src_for_ssa(cmp
);
1142 nir_builder_instr_insert(b
, &discard
->instr
);
1143 b
->shader
->info
.fs
.uses_discard
= true;
1147 ttn_if(struct ttn_compile
*c
, nir_ssa_def
*src
, bool is_uint
)
1149 nir_builder
*b
= &c
->build
;
1150 nir_ssa_def
*src_x
= ttn_channel(b
, src
, X
);
1152 nir_if
*if_stmt
= nir_if_create(b
->shader
);
1154 /* equivalent to TGSI UIF, src is interpreted as integer */
1155 if_stmt
->condition
= nir_src_for_ssa(nir_ine(b
, src_x
, nir_imm_int(b
, 0)));
1157 /* equivalent to TGSI IF, src is interpreted as float */
1158 if_stmt
->condition
= nir_src_for_ssa(nir_fneu(b
, src_x
, nir_imm_float(b
, 0.0)));
1160 nir_builder_cf_insert(b
, &if_stmt
->cf_node
);
1162 c
->if_stack
[c
->if_stack_pos
] = nir_after_cf_node(&if_stmt
->cf_node
);
1165 b
->cursor
= nir_after_cf_list(&if_stmt
->then_list
);
1167 c
->if_stack
[c
->if_stack_pos
] = nir_after_cf_list(&if_stmt
->else_list
);
1172 ttn_else(struct ttn_compile
*c
)
1174 nir_builder
*b
= &c
->build
;
1176 b
->cursor
= c
->if_stack
[c
->if_stack_pos
- 1];
1180 ttn_endif(struct ttn_compile
*c
)
1182 nir_builder
*b
= &c
->build
;
1184 c
->if_stack_pos
-= 2;
1185 b
->cursor
= c
->if_stack
[c
->if_stack_pos
];
1189 ttn_bgnloop(struct ttn_compile
*c
)
1191 nir_builder
*b
= &c
->build
;
1193 nir_loop
*loop
= nir_loop_create(b
->shader
);
1194 nir_builder_cf_insert(b
, &loop
->cf_node
);
1196 c
->loop_stack
[c
->loop_stack_pos
] = nir_after_cf_node(&loop
->cf_node
);
1197 c
->loop_stack_pos
++;
1199 b
->cursor
= nir_after_cf_list(&loop
->body
);
1203 ttn_cont(nir_builder
*b
)
1205 nir_jump_instr
*instr
= nir_jump_instr_create(b
->shader
, nir_jump_continue
);
1206 nir_builder_instr_insert(b
, &instr
->instr
);
1210 ttn_brk(nir_builder
*b
)
1212 nir_jump_instr
*instr
= nir_jump_instr_create(b
->shader
, nir_jump_break
);
1213 nir_builder_instr_insert(b
, &instr
->instr
);
1217 ttn_endloop(struct ttn_compile
*c
)
1219 nir_builder
*b
= &c
->build
;
1221 c
->loop_stack_pos
--;
1222 b
->cursor
= c
->loop_stack
[c
->loop_stack_pos
];
1226 get_texture_info(unsigned texture
,
1227 enum glsl_sampler_dim
*dim
,
1238 case TGSI_TEXTURE_BUFFER
:
1239 *dim
= GLSL_SAMPLER_DIM_BUF
;
1241 case TGSI_TEXTURE_1D
:
1242 *dim
= GLSL_SAMPLER_DIM_1D
;
1244 case TGSI_TEXTURE_1D_ARRAY
:
1245 *dim
= GLSL_SAMPLER_DIM_1D
;
1248 case TGSI_TEXTURE_SHADOW1D
:
1249 *dim
= GLSL_SAMPLER_DIM_1D
;
1252 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
1253 *dim
= GLSL_SAMPLER_DIM_1D
;
1257 case TGSI_TEXTURE_2D
:
1258 *dim
= GLSL_SAMPLER_DIM_2D
;
1260 case TGSI_TEXTURE_2D_ARRAY
:
1261 *dim
= GLSL_SAMPLER_DIM_2D
;
1264 case TGSI_TEXTURE_2D_MSAA
:
1265 *dim
= GLSL_SAMPLER_DIM_MS
;
1267 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
1268 *dim
= GLSL_SAMPLER_DIM_MS
;
1271 case TGSI_TEXTURE_SHADOW2D
:
1272 *dim
= GLSL_SAMPLER_DIM_2D
;
1275 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
1276 *dim
= GLSL_SAMPLER_DIM_2D
;
1280 case TGSI_TEXTURE_3D
:
1281 *dim
= GLSL_SAMPLER_DIM_3D
;
1283 case TGSI_TEXTURE_CUBE
:
1284 *dim
= GLSL_SAMPLER_DIM_CUBE
;
1286 case TGSI_TEXTURE_CUBE_ARRAY
:
1287 *dim
= GLSL_SAMPLER_DIM_CUBE
;
1290 case TGSI_TEXTURE_SHADOWCUBE
:
1291 *dim
= GLSL_SAMPLER_DIM_CUBE
;
1294 case TGSI_TEXTURE_SHADOWCUBE_ARRAY
:
1295 *dim
= GLSL_SAMPLER_DIM_CUBE
;
1299 case TGSI_TEXTURE_RECT
:
1300 *dim
= GLSL_SAMPLER_DIM_RECT
;
1302 case TGSI_TEXTURE_SHADOWRECT
:
1303 *dim
= GLSL_SAMPLER_DIM_RECT
;
1307 fprintf(stderr
, "Unknown TGSI texture target %d\n", texture
);
1312 static enum glsl_base_type
1313 base_type_for_alu_type(nir_alu_type type
)
1315 type
= nir_alu_type_get_base_type(type
);
1318 case nir_type_float
:
1319 return GLSL_TYPE_FLOAT
;
1321 return GLSL_TYPE_INT
;
1323 return GLSL_TYPE_UINT
;
1325 unreachable("invalid type");
1329 static nir_variable
*
1330 get_sampler_var(struct ttn_compile
*c
, int binding
,
1331 enum glsl_sampler_dim dim
,
1334 enum glsl_base_type base_type
,
1337 nir_variable
*var
= c
->samplers
[binding
];
1339 const struct glsl_type
*type
=
1340 glsl_sampler_type(dim
, is_shadow
, is_array
, base_type
);
1341 var
= nir_variable_create(c
->build
.shader
, nir_var_uniform
, type
,
1343 var
->data
.binding
= binding
;
1344 var
->data
.explicit_binding
= true;
1346 c
->samplers
[binding
] = var
;
1347 c
->num_samplers
= MAX2(c
->num_samplers
, binding
+ 1);
1349 /* Record textures used */
1350 unsigned mask
= 1 << binding
;
1351 c
->build
.shader
->info
.textures_used
|= mask
;
1352 if (op
== nir_texop_txf
||
1353 op
== nir_texop_txf_ms
||
1354 op
== nir_texop_txf_ms_mcs
)
1355 c
->build
.shader
->info
.textures_used_by_txf
|= mask
;
1361 static nir_variable
*
1362 get_image_var(struct ttn_compile
*c
, int binding
,
1363 enum glsl_sampler_dim dim
,
1365 enum glsl_base_type base_type
,
1366 enum gl_access_qualifier access
,
1367 enum pipe_format format
)
1369 nir_variable
*var
= c
->images
[binding
];
1372 const struct glsl_type
*type
= glsl_image_type(dim
, is_array
, base_type
);
1374 var
= nir_variable_create(c
->build
.shader
, nir_var_uniform
, type
, "image");
1375 var
->data
.binding
= binding
;
1376 var
->data
.explicit_binding
= true;
1377 var
->data
.access
= access
;
1378 var
->data
.image
.format
= format
;
1380 c
->images
[binding
] = var
;
1381 c
->num_images
= MAX2(c
->num_images
, binding
+ 1);
1382 if (dim
== GLSL_SAMPLER_DIM_MS
)
1383 c
->num_msaa_images
= c
->num_images
;
1390 add_ssbo_var(struct ttn_compile
*c
, int binding
)
1392 nir_variable
*var
= c
->ssbo
[binding
];
1395 /* A length of 0 is used to denote unsized arrays */
1396 const struct glsl_type
*type
= glsl_array_type(glsl_uint_type(), 0, 0);
1398 struct glsl_struct_field field
= {
1404 var
= nir_variable_create(c
->build
.shader
, nir_var_mem_ssbo
, type
, "ssbo");
1405 var
->data
.binding
= binding
;
1406 var
->interface_type
=
1407 glsl_interface_type(&field
, 1, GLSL_INTERFACE_PACKING_STD430
,
1409 c
->ssbo
[binding
] = var
;
1414 ttn_tex(struct ttn_compile
*c
, nir_alu_dest dest
, nir_ssa_def
**src
)
1416 nir_builder
*b
= &c
->build
;
1417 struct tgsi_full_instruction
*tgsi_inst
= &c
->token
->FullInstruction
;
1418 nir_tex_instr
*instr
;
1420 unsigned num_srcs
, samp
= 1, sview
, i
;
1422 switch (tgsi_inst
->Instruction
.Opcode
) {
1423 case TGSI_OPCODE_TEX
:
1427 case TGSI_OPCODE_TEX2
:
1432 case TGSI_OPCODE_TXP
:
1436 case TGSI_OPCODE_TXB
:
1440 case TGSI_OPCODE_TXB2
:
1445 case TGSI_OPCODE_TXL
:
1446 case TGSI_OPCODE_TEX_LZ
:
1450 case TGSI_OPCODE_TXL2
:
1455 case TGSI_OPCODE_TXF
:
1456 case TGSI_OPCODE_TXF_LZ
:
1457 if (tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_2D_MSAA
||
1458 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_2D_ARRAY_MSAA
) {
1459 op
= nir_texop_txf_ms
;
1465 case TGSI_OPCODE_TXD
:
1470 case TGSI_OPCODE_LODQ
:
1476 fprintf(stderr
, "unknown TGSI tex op %d\n", tgsi_inst
->Instruction
.Opcode
);
1480 if (tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D
||
1481 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D_ARRAY
||
1482 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D
||
1483 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D_ARRAY
||
1484 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWRECT
||
1485 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
1486 tgsi_inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
1493 num_srcs
+= tgsi_inst
->Texture
.NumOffsets
;
1495 instr
= nir_tex_instr_create(b
->shader
, num_srcs
);
1498 get_texture_info(tgsi_inst
->Texture
.Texture
,
1499 &instr
->sampler_dim
, &instr
->is_shadow
, &instr
->is_array
);
1501 instr
->coord_components
=
1502 glsl_get_sampler_dim_coordinate_components(instr
->sampler_dim
);
1504 if (instr
->is_array
)
1505 instr
->coord_components
++;
1507 assert(tgsi_inst
->Src
[samp
].Register
.File
== TGSI_FILE_SAMPLER
);
1509 /* TODO if we supported any opc's which take an explicit SVIEW
1510 * src, we would use that here instead. But for the "legacy"
1511 * texture opc's the SVIEW index is same as SAMP index:
1513 sview
= tgsi_inst
->Src
[samp
].Register
.Index
;
1515 if (op
== nir_texop_lod
) {
1516 instr
->dest_type
= nir_type_float
;
1517 } else if (sview
< c
->num_samp_types
) {
1518 instr
->dest_type
= c
->samp_types
[sview
];
1520 instr
->dest_type
= nir_type_float
;
1524 get_sampler_var(c
, sview
, instr
->sampler_dim
,
1527 base_type_for_alu_type(instr
->dest_type
),
1530 nir_deref_instr
*deref
= nir_build_deref_var(b
, var
);
1532 unsigned src_number
= 0;
1534 instr
->src
[src_number
].src
= nir_src_for_ssa(&deref
->dest
.ssa
);
1535 instr
->src
[src_number
].src_type
= nir_tex_src_texture_deref
;
1537 instr
->src
[src_number
].src
= nir_src_for_ssa(&deref
->dest
.ssa
);
1538 instr
->src
[src_number
].src_type
= nir_tex_src_sampler_deref
;
1541 instr
->src
[src_number
].src
=
1542 nir_src_for_ssa(nir_swizzle(b
, src
[0], SWIZ(X
, Y
, Z
, W
),
1543 instr
->coord_components
));
1544 instr
->src
[src_number
].src_type
= nir_tex_src_coord
;
1547 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXP
) {
1548 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[0], W
));
1549 instr
->src
[src_number
].src_type
= nir_tex_src_projector
;
1553 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB
) {
1554 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[0], W
));
1555 instr
->src
[src_number
].src_type
= nir_tex_src_bias
;
1559 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB2
) {
1560 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[1], X
));
1561 instr
->src
[src_number
].src_type
= nir_tex_src_bias
;
1565 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL
||
1566 tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TEX_LZ
) {
1567 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TEX_LZ
)
1568 instr
->src
[src_number
].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
1570 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[0], W
));
1571 instr
->src
[src_number
].src_type
= nir_tex_src_lod
;
1575 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL2
) {
1576 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[1], X
));
1577 instr
->src
[src_number
].src_type
= nir_tex_src_lod
;
1581 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXF
||
1582 tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXF_LZ
) {
1583 if (op
== nir_texop_txf_ms
) {
1584 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[0], W
));
1585 instr
->src
[src_number
].src_type
= nir_tex_src_ms_index
;
1587 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXF_LZ
)
1588 instr
->src
[src_number
].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
1590 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[0], W
));
1591 instr
->src
[src_number
].src_type
= nir_tex_src_lod
;
1596 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_TXD
) {
1597 instr
->src
[src_number
].src_type
= nir_tex_src_ddx
;
1598 instr
->src
[src_number
].src
=
1599 nir_src_for_ssa(nir_swizzle(b
, src
[1], SWIZ(X
, Y
, Z
, W
),
1600 nir_tex_instr_src_size(instr
, src_number
)));
1602 instr
->src
[src_number
].src_type
= nir_tex_src_ddy
;
1603 instr
->src
[src_number
].src
=
1604 nir_src_for_ssa(nir_swizzle(b
, src
[2], SWIZ(X
, Y
, Z
, W
),
1605 nir_tex_instr_src_size(instr
, src_number
)));
1609 if (instr
->is_shadow
) {
1610 if (instr
->coord_components
== 4)
1611 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[1], X
));
1612 else if (instr
->coord_components
== 3)
1613 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[0], W
));
1615 instr
->src
[src_number
].src
= nir_src_for_ssa(ttn_channel(b
, src
[0], Z
));
1617 instr
->src
[src_number
].src_type
= nir_tex_src_comparator
;
1621 for (i
= 0; i
< tgsi_inst
->Texture
.NumOffsets
; i
++) {
1622 struct tgsi_texture_offset
*tex_offset
= &tgsi_inst
->TexOffsets
[i
];
1623 /* since TexOffset ins't using tgsi_full_src_register we get to
1624 * do some extra gymnastics:
1628 memset(&src
, 0, sizeof(src
));
1630 src
.src
= ttn_src_for_file_and_index(c
,
1636 src
.swizzle
[0] = tex_offset
->SwizzleX
;
1637 src
.swizzle
[1] = tex_offset
->SwizzleY
;
1638 src
.swizzle
[2] = tex_offset
->SwizzleZ
;
1639 src
.swizzle
[3] = TGSI_SWIZZLE_W
;
1641 instr
->src
[src_number
].src_type
= nir_tex_src_offset
;
1642 instr
->src
[src_number
].src
= nir_src_for_ssa(
1643 nir_mov_alu(b
, src
, nir_tex_instr_src_size(instr
, src_number
)));
1647 assert(src_number
== num_srcs
);
1648 assert(src_number
== instr
->num_srcs
);
1650 nir_ssa_dest_init(&instr
->instr
, &instr
->dest
,
1651 nir_tex_instr_dest_size(instr
),
1653 nir_builder_instr_insert(b
, &instr
->instr
);
1655 /* Resolve the writemask on the texture op. */
1656 ttn_move_dest(b
, dest
, &instr
->dest
.ssa
);
1659 /* TGSI_OPCODE_TXQ is actually two distinct operations:
1661 * dst.x = texture\_width(unit, lod)
1662 * dst.y = texture\_height(unit, lod)
1663 * dst.z = texture\_depth(unit, lod)
1664 * dst.w = texture\_levels(unit)
1666 * dst.xyz map to NIR txs opcode, and dst.w maps to query_levels
1669 ttn_txq(struct ttn_compile
*c
, nir_alu_dest dest
, nir_ssa_def
**src
)
1671 nir_builder
*b
= &c
->build
;
1672 struct tgsi_full_instruction
*tgsi_inst
= &c
->token
->FullInstruction
;
1673 nir_tex_instr
*txs
, *qlv
;
1675 txs
= nir_tex_instr_create(b
->shader
, 2);
1676 txs
->op
= nir_texop_txs
;
1677 get_texture_info(tgsi_inst
->Texture
.Texture
,
1678 &txs
->sampler_dim
, &txs
->is_shadow
, &txs
->is_array
);
1680 qlv
= nir_tex_instr_create(b
->shader
, 1);
1681 qlv
->op
= nir_texop_query_levels
;
1682 get_texture_info(tgsi_inst
->Texture
.Texture
,
1683 &qlv
->sampler_dim
, &qlv
->is_shadow
, &qlv
->is_array
);
1685 assert(tgsi_inst
->Src
[1].Register
.File
== TGSI_FILE_SAMPLER
);
1686 int tex_index
= tgsi_inst
->Src
[1].Register
.Index
;
1689 get_sampler_var(c
, tex_index
, txs
->sampler_dim
,
1692 base_type_for_alu_type(txs
->dest_type
),
1695 nir_deref_instr
*deref
= nir_build_deref_var(b
, var
);
1697 txs
->src
[0].src
= nir_src_for_ssa(&deref
->dest
.ssa
);
1698 txs
->src
[0].src_type
= nir_tex_src_texture_deref
;
1700 qlv
->src
[0].src
= nir_src_for_ssa(&deref
->dest
.ssa
);
1701 qlv
->src
[0].src_type
= nir_tex_src_texture_deref
;
1704 txs
->src
[1].src
= nir_src_for_ssa(ttn_channel(b
, src
[0], X
));
1705 txs
->src
[1].src_type
= nir_tex_src_lod
;
1707 nir_ssa_dest_init(&txs
->instr
, &txs
->dest
,
1708 nir_tex_instr_dest_size(txs
), 32, NULL
);
1709 nir_builder_instr_insert(b
, &txs
->instr
);
1711 nir_ssa_dest_init(&qlv
->instr
, &qlv
->dest
, 1, 32, NULL
);
1712 nir_builder_instr_insert(b
, &qlv
->instr
);
1714 ttn_move_dest_masked(b
, dest
, &txs
->dest
.ssa
, TGSI_WRITEMASK_XYZ
);
1715 ttn_move_dest_masked(b
, dest
, &qlv
->dest
.ssa
, TGSI_WRITEMASK_W
);
1718 static enum glsl_base_type
1719 get_image_base_type(struct tgsi_full_instruction
*tgsi_inst
)
1721 const struct util_format_description
*desc
=
1722 util_format_description(tgsi_inst
->Memory
.Format
);
1724 if (desc
->channel
[0].pure_integer
) {
1725 if (desc
->channel
[0].type
== UTIL_FORMAT_TYPE_SIGNED
)
1726 return GLSL_TYPE_INT
;
1728 return GLSL_TYPE_UINT
;
1730 return GLSL_TYPE_FLOAT
;
1733 static enum gl_access_qualifier
1734 get_mem_qualifier(struct tgsi_full_instruction
*tgsi_inst
)
1736 enum gl_access_qualifier access
= 0;
1738 if (tgsi_inst
->Memory
.Qualifier
& TGSI_MEMORY_COHERENT
)
1739 access
|= ACCESS_COHERENT
;
1740 if (tgsi_inst
->Memory
.Qualifier
& TGSI_MEMORY_RESTRICT
)
1741 access
|= ACCESS_RESTRICT
;
1742 if (tgsi_inst
->Memory
.Qualifier
& TGSI_MEMORY_VOLATILE
)
1743 access
|= ACCESS_VOLATILE
;
1744 if (tgsi_inst
->Memory
.Qualifier
& TGSI_MEMORY_STREAM_CACHE_POLICY
)
1745 access
|= ACCESS_STREAM_CACHE_POLICY
;
1751 ttn_mem(struct ttn_compile
*c
, nir_alu_dest dest
, nir_ssa_def
**src
)
1753 nir_builder
*b
= &c
->build
;
1754 struct tgsi_full_instruction
*tgsi_inst
= &c
->token
->FullInstruction
;
1755 nir_intrinsic_instr
*instr
= NULL
;
1756 unsigned resource_index
, addr_src_index
, file
;
1758 switch (tgsi_inst
->Instruction
.Opcode
) {
1759 case TGSI_OPCODE_LOAD
:
1760 assert(!tgsi_inst
->Src
[0].Register
.Indirect
);
1761 resource_index
= tgsi_inst
->Src
[0].Register
.Index
;
1762 file
= tgsi_inst
->Src
[0].Register
.File
;
1765 case TGSI_OPCODE_STORE
:
1766 assert(!tgsi_inst
->Dst
[0].Register
.Indirect
);
1767 resource_index
= tgsi_inst
->Dst
[0].Register
.Index
;
1768 file
= tgsi_inst
->Dst
[0].Register
.File
;
1772 unreachable("unexpected memory opcode");
1775 if (file
== TGSI_FILE_BUFFER
) {
1776 nir_intrinsic_op op
;
1778 switch (tgsi_inst
->Instruction
.Opcode
) {
1779 case TGSI_OPCODE_LOAD
:
1780 op
= nir_intrinsic_load_ssbo
;
1782 case TGSI_OPCODE_STORE
:
1783 op
= nir_intrinsic_store_ssbo
;
1787 add_ssbo_var(c
, resource_index
);
1789 instr
= nir_intrinsic_instr_create(b
->shader
, op
);
1790 instr
->num_components
= util_last_bit(tgsi_inst
->Dst
[0].Register
.WriteMask
);
1791 nir_intrinsic_set_access(instr
, get_mem_qualifier(tgsi_inst
));
1792 nir_intrinsic_set_align(instr
, 4, 0);
1795 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_STORE
)
1796 instr
->src
[i
++] = nir_src_for_ssa(nir_swizzle(b
, src
[1], SWIZ(X
, Y
, Z
, W
),
1797 instr
->num_components
));
1798 instr
->src
[i
++] = nir_src_for_ssa(nir_imm_int(b
, resource_index
));
1799 instr
->src
[i
++] = nir_src_for_ssa(ttn_channel(b
, src
[addr_src_index
], X
));
1801 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_STORE
)
1802 nir_intrinsic_set_write_mask(instr
, tgsi_inst
->Dst
[0].Register
.WriteMask
);
1804 } else if (file
== TGSI_FILE_IMAGE
) {
1805 nir_intrinsic_op op
;
1807 switch (tgsi_inst
->Instruction
.Opcode
) {
1808 case TGSI_OPCODE_LOAD
:
1809 op
= nir_intrinsic_image_deref_load
;
1811 case TGSI_OPCODE_STORE
:
1812 op
= nir_intrinsic_image_deref_store
;
1816 instr
= nir_intrinsic_instr_create(b
->shader
, op
);
1818 /* Set the image variable dereference. */
1819 enum glsl_sampler_dim dim
;
1821 get_texture_info(tgsi_inst
->Memory
.Texture
, &dim
, NULL
, &is_array
);
1823 enum glsl_base_type base_type
= get_image_base_type(tgsi_inst
);
1824 enum gl_access_qualifier access
= get_mem_qualifier(tgsi_inst
);
1826 nir_variable
*image
=
1827 get_image_var(c
, resource_index
,
1828 dim
, is_array
, base_type
, access
,
1829 tgsi_inst
->Memory
.Format
);
1830 nir_deref_instr
*image_deref
= nir_build_deref_var(b
, image
);
1831 const struct glsl_type
*type
= image_deref
->type
;
1833 nir_intrinsic_set_access(instr
, image_deref
->var
->data
.access
);
1835 instr
->src
[0] = nir_src_for_ssa(&image_deref
->dest
.ssa
);
1836 instr
->src
[1] = nir_src_for_ssa(src
[addr_src_index
]);
1838 /* Set the sample argument, which is undefined for single-sample images. */
1839 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_MS
) {
1840 instr
->src
[2] = nir_src_for_ssa(ttn_channel(b
, src
[addr_src_index
], W
));
1842 instr
->src
[2] = nir_src_for_ssa(nir_ssa_undef(b
, 1, 32));
1845 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_LOAD
) {
1846 instr
->src
[3] = nir_src_for_ssa(nir_imm_int(b
, 0)); /* LOD */
1849 unsigned num_components
= util_last_bit(tgsi_inst
->Dst
[0].Register
.WriteMask
);
1851 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_STORE
) {
1852 instr
->src
[3] = nir_src_for_ssa(nir_swizzle(b
, src
[1], SWIZ(X
, Y
, Z
, W
),
1854 instr
->src
[4] = nir_src_for_ssa(nir_imm_int(b
, 0)); /* LOD */
1857 instr
->num_components
= num_components
;
1859 unreachable("unexpected file");
1863 if (tgsi_inst
->Instruction
.Opcode
== TGSI_OPCODE_LOAD
) {
1864 nir_ssa_dest_init(&instr
->instr
, &instr
->dest
, instr
->num_components
,
1866 nir_builder_instr_insert(b
, &instr
->instr
);
1867 ttn_move_dest(b
, dest
, &instr
->dest
.ssa
);
1869 nir_builder_instr_insert(b
, &instr
->instr
);
1873 static const nir_op op_trans
[TGSI_OPCODE_LAST
] = {
1874 [TGSI_OPCODE_ARL
] = 0,
1875 [TGSI_OPCODE_MOV
] = nir_op_mov
,
1876 [TGSI_OPCODE_LIT
] = 0,
1877 [TGSI_OPCODE_RCP
] = nir_op_frcp
,
1878 [TGSI_OPCODE_RSQ
] = nir_op_frsq
,
1879 [TGSI_OPCODE_EXP
] = 0,
1880 [TGSI_OPCODE_LOG
] = 0,
1881 [TGSI_OPCODE_MUL
] = nir_op_fmul
,
1882 [TGSI_OPCODE_ADD
] = nir_op_fadd
,
1883 [TGSI_OPCODE_DP3
] = 0,
1884 [TGSI_OPCODE_DP4
] = 0,
1885 [TGSI_OPCODE_DST
] = 0,
1886 [TGSI_OPCODE_MIN
] = nir_op_fmin
,
1887 [TGSI_OPCODE_MAX
] = nir_op_fmax
,
1888 [TGSI_OPCODE_SLT
] = nir_op_slt
,
1889 [TGSI_OPCODE_SGE
] = nir_op_sge
,
1890 [TGSI_OPCODE_MAD
] = nir_op_ffma
,
1891 [TGSI_OPCODE_TEX_LZ
] = 0,
1892 [TGSI_OPCODE_LRP
] = 0,
1893 [TGSI_OPCODE_SQRT
] = nir_op_fsqrt
,
1894 [TGSI_OPCODE_FRC
] = nir_op_ffract
,
1895 [TGSI_OPCODE_TXF_LZ
] = 0,
1896 [TGSI_OPCODE_FLR
] = nir_op_ffloor
,
1897 [TGSI_OPCODE_ROUND
] = nir_op_fround_even
,
1898 [TGSI_OPCODE_EX2
] = nir_op_fexp2
,
1899 [TGSI_OPCODE_LG2
] = nir_op_flog2
,
1900 [TGSI_OPCODE_POW
] = nir_op_fpow
,
1901 [TGSI_OPCODE_COS
] = nir_op_fcos
,
1902 [TGSI_OPCODE_DDX
] = nir_op_fddx
,
1903 [TGSI_OPCODE_DDY
] = nir_op_fddy
,
1904 [TGSI_OPCODE_KILL
] = 0,
1905 [TGSI_OPCODE_PK2H
] = 0, /* XXX */
1906 [TGSI_OPCODE_PK2US
] = 0, /* XXX */
1907 [TGSI_OPCODE_PK4B
] = 0, /* XXX */
1908 [TGSI_OPCODE_PK4UB
] = 0, /* XXX */
1909 [TGSI_OPCODE_SEQ
] = nir_op_seq
,
1910 [TGSI_OPCODE_SGT
] = 0,
1911 [TGSI_OPCODE_SIN
] = nir_op_fsin
,
1912 [TGSI_OPCODE_SNE
] = nir_op_sne
,
1913 [TGSI_OPCODE_SLE
] = 0,
1914 [TGSI_OPCODE_TEX
] = 0,
1915 [TGSI_OPCODE_TXD
] = 0,
1916 [TGSI_OPCODE_TXP
] = 0,
1917 [TGSI_OPCODE_UP2H
] = 0, /* XXX */
1918 [TGSI_OPCODE_UP2US
] = 0, /* XXX */
1919 [TGSI_OPCODE_UP4B
] = 0, /* XXX */
1920 [TGSI_OPCODE_UP4UB
] = 0, /* XXX */
1921 [TGSI_OPCODE_ARR
] = 0,
1923 /* No function calls, yet. */
1924 [TGSI_OPCODE_CAL
] = 0, /* XXX */
1925 [TGSI_OPCODE_RET
] = 0, /* XXX */
1927 [TGSI_OPCODE_SSG
] = nir_op_fsign
,
1928 [TGSI_OPCODE_CMP
] = 0,
1929 [TGSI_OPCODE_TXB
] = 0,
1930 [TGSI_OPCODE_DIV
] = nir_op_fdiv
,
1931 [TGSI_OPCODE_DP2
] = 0,
1932 [TGSI_OPCODE_TXL
] = 0,
1934 [TGSI_OPCODE_BRK
] = 0,
1935 [TGSI_OPCODE_IF
] = 0,
1936 [TGSI_OPCODE_UIF
] = 0,
1937 [TGSI_OPCODE_ELSE
] = 0,
1938 [TGSI_OPCODE_ENDIF
] = 0,
1940 [TGSI_OPCODE_DDX_FINE
] = nir_op_fddx_fine
,
1941 [TGSI_OPCODE_DDY_FINE
] = nir_op_fddy_fine
,
1943 [TGSI_OPCODE_CEIL
] = nir_op_fceil
,
1944 [TGSI_OPCODE_I2F
] = nir_op_i2f32
,
1945 [TGSI_OPCODE_NOT
] = nir_op_inot
,
1946 [TGSI_OPCODE_TRUNC
] = nir_op_ftrunc
,
1947 [TGSI_OPCODE_SHL
] = nir_op_ishl
,
1948 [TGSI_OPCODE_AND
] = nir_op_iand
,
1949 [TGSI_OPCODE_OR
] = nir_op_ior
,
1950 [TGSI_OPCODE_MOD
] = nir_op_umod
,
1951 [TGSI_OPCODE_XOR
] = nir_op_ixor
,
1952 [TGSI_OPCODE_TXF
] = 0,
1953 [TGSI_OPCODE_TXQ
] = 0,
1955 [TGSI_OPCODE_CONT
] = 0,
1957 [TGSI_OPCODE_EMIT
] = 0, /* XXX */
1958 [TGSI_OPCODE_ENDPRIM
] = 0, /* XXX */
1960 [TGSI_OPCODE_BGNLOOP
] = 0,
1961 [TGSI_OPCODE_BGNSUB
] = 0, /* XXX: no function calls */
1962 [TGSI_OPCODE_ENDLOOP
] = 0,
1963 [TGSI_OPCODE_ENDSUB
] = 0, /* XXX: no function calls */
1965 [TGSI_OPCODE_NOP
] = 0,
1966 [TGSI_OPCODE_FSEQ
] = nir_op_feq
,
1967 [TGSI_OPCODE_FSGE
] = nir_op_fge
,
1968 [TGSI_OPCODE_FSLT
] = nir_op_flt
,
1969 [TGSI_OPCODE_FSNE
] = nir_op_fneu
,
1971 [TGSI_OPCODE_KILL_IF
] = 0,
1973 [TGSI_OPCODE_END
] = 0,
1975 [TGSI_OPCODE_F2I
] = nir_op_f2i32
,
1976 [TGSI_OPCODE_IDIV
] = nir_op_idiv
,
1977 [TGSI_OPCODE_IMAX
] = nir_op_imax
,
1978 [TGSI_OPCODE_IMIN
] = nir_op_imin
,
1979 [TGSI_OPCODE_INEG
] = nir_op_ineg
,
1980 [TGSI_OPCODE_ISGE
] = nir_op_ige
,
1981 [TGSI_OPCODE_ISHR
] = nir_op_ishr
,
1982 [TGSI_OPCODE_ISLT
] = nir_op_ilt
,
1983 [TGSI_OPCODE_F2U
] = nir_op_f2u32
,
1984 [TGSI_OPCODE_U2F
] = nir_op_u2f32
,
1985 [TGSI_OPCODE_UADD
] = nir_op_iadd
,
1986 [TGSI_OPCODE_UDIV
] = nir_op_udiv
,
1987 [TGSI_OPCODE_UMAD
] = 0,
1988 [TGSI_OPCODE_UMAX
] = nir_op_umax
,
1989 [TGSI_OPCODE_UMIN
] = nir_op_umin
,
1990 [TGSI_OPCODE_UMOD
] = nir_op_umod
,
1991 [TGSI_OPCODE_UMUL
] = nir_op_imul
,
1992 [TGSI_OPCODE_USEQ
] = nir_op_ieq
,
1993 [TGSI_OPCODE_USGE
] = nir_op_uge
,
1994 [TGSI_OPCODE_USHR
] = nir_op_ushr
,
1995 [TGSI_OPCODE_USLT
] = nir_op_ult
,
1996 [TGSI_OPCODE_USNE
] = nir_op_ine
,
1998 [TGSI_OPCODE_SWITCH
] = 0, /* not emitted by glsl_to_tgsi.cpp */
1999 [TGSI_OPCODE_CASE
] = 0, /* not emitted by glsl_to_tgsi.cpp */
2000 [TGSI_OPCODE_DEFAULT
] = 0, /* not emitted by glsl_to_tgsi.cpp */
2001 [TGSI_OPCODE_ENDSWITCH
] = 0, /* not emitted by glsl_to_tgsi.cpp */
2003 /* XXX: SAMPLE opcodes */
2005 [TGSI_OPCODE_UARL
] = nir_op_mov
,
2006 [TGSI_OPCODE_UCMP
] = 0,
2007 [TGSI_OPCODE_IABS
] = nir_op_iabs
,
2008 [TGSI_OPCODE_ISSG
] = nir_op_isign
,
2010 [TGSI_OPCODE_LOAD
] = 0,
2011 [TGSI_OPCODE_STORE
] = 0,
2015 [TGSI_OPCODE_TEX2
] = 0,
2016 [TGSI_OPCODE_TXB2
] = 0,
2017 [TGSI_OPCODE_TXL2
] = 0,
2019 [TGSI_OPCODE_IMUL_HI
] = nir_op_imul_high
,
2020 [TGSI_OPCODE_UMUL_HI
] = nir_op_umul_high
,
2022 [TGSI_OPCODE_TG4
] = 0,
2023 [TGSI_OPCODE_LODQ
] = 0,
2025 [TGSI_OPCODE_IBFE
] = nir_op_ibitfield_extract
,
2026 [TGSI_OPCODE_UBFE
] = nir_op_ubitfield_extract
,
2027 [TGSI_OPCODE_BFI
] = nir_op_bitfield_insert
,
2028 [TGSI_OPCODE_BREV
] = nir_op_bitfield_reverse
,
2029 [TGSI_OPCODE_POPC
] = nir_op_bit_count
,
2030 [TGSI_OPCODE_LSB
] = nir_op_find_lsb
,
2031 [TGSI_OPCODE_IMSB
] = nir_op_ifind_msb
,
2032 [TGSI_OPCODE_UMSB
] = nir_op_ufind_msb
,
2034 [TGSI_OPCODE_INTERP_CENTROID
] = 0, /* XXX */
2035 [TGSI_OPCODE_INTERP_SAMPLE
] = 0, /* XXX */
2036 [TGSI_OPCODE_INTERP_OFFSET
] = 0, /* XXX */
2038 [TGSI_OPCODE_F2D
] = nir_op_f2f64
,
2039 [TGSI_OPCODE_D2F
] = nir_op_f2f32
,
2040 [TGSI_OPCODE_DMUL
] = nir_op_fmul
,
2041 [TGSI_OPCODE_D2U
] = nir_op_f2u32
,
2042 [TGSI_OPCODE_U2D
] = nir_op_u2f64
,
2044 [TGSI_OPCODE_U64ADD
] = nir_op_iadd
,
2045 [TGSI_OPCODE_U64MUL
] = nir_op_imul
,
2046 [TGSI_OPCODE_U64DIV
] = nir_op_udiv
,
2047 [TGSI_OPCODE_U64SNE
] = nir_op_ine
,
2051 ttn_emit_instruction(struct ttn_compile
*c
)
2053 nir_builder
*b
= &c
->build
;
2054 struct tgsi_full_instruction
*tgsi_inst
= &c
->token
->FullInstruction
;
2056 unsigned tgsi_op
= tgsi_inst
->Instruction
.Opcode
;
2057 struct tgsi_full_dst_register
*tgsi_dst
= &tgsi_inst
->Dst
[0];
2059 if (tgsi_op
== TGSI_OPCODE_END
)
2062 nir_ssa_def
*src
[TGSI_FULL_MAX_SRC_REGISTERS
];
2063 for (i
= 0; i
< tgsi_inst
->Instruction
.NumSrcRegs
; i
++) {
2064 src
[i
] = ttn_get_src(c
, &tgsi_inst
->Src
[i
], i
);
2066 nir_alu_dest dest
= ttn_get_dest(c
, tgsi_dst
);
2068 unsigned tgsi_dst_type
= tgsi_opcode_infer_dst_type(tgsi_op
, 0);
2070 /* The destination bitsize of the NIR opcode (not TGSI, where it's always
2071 * 32 bits). This needs to be passed into ttn_alu() because it can't be
2072 * inferred for comparison opcodes.
2074 unsigned dst_bitsize
= tgsi_type_is_64bit(tgsi_dst_type
) ? 64 : 32;
2077 case TGSI_OPCODE_RSQ
:
2078 ttn_move_dest(b
, dest
, nir_frsq(b
, ttn_channel(b
, src
[0], X
)));
2081 case TGSI_OPCODE_SQRT
:
2082 ttn_move_dest(b
, dest
, nir_fsqrt(b
, ttn_channel(b
, src
[0], X
)));
2085 case TGSI_OPCODE_RCP
:
2086 ttn_move_dest(b
, dest
, nir_frcp(b
, ttn_channel(b
, src
[0], X
)));
2089 case TGSI_OPCODE_EX2
:
2090 ttn_move_dest(b
, dest
, nir_fexp2(b
, ttn_channel(b
, src
[0], X
)));
2093 case TGSI_OPCODE_LG2
:
2094 ttn_move_dest(b
, dest
, nir_flog2(b
, ttn_channel(b
, src
[0], X
)));
2097 case TGSI_OPCODE_POW
:
2098 ttn_move_dest(b
, dest
, nir_fpow(b
,
2099 ttn_channel(b
, src
[0], X
),
2100 ttn_channel(b
, src
[1], X
)));
2103 case TGSI_OPCODE_COS
:
2104 ttn_move_dest(b
, dest
, nir_fcos(b
, ttn_channel(b
, src
[0], X
)));
2107 case TGSI_OPCODE_SIN
:
2108 ttn_move_dest(b
, dest
, nir_fsin(b
, ttn_channel(b
, src
[0], X
)));
2111 case TGSI_OPCODE_ARL
:
2112 ttn_arl(b
, op_trans
[tgsi_op
], dest
, src
);
2115 case TGSI_OPCODE_EXP
:
2116 ttn_exp(b
, op_trans
[tgsi_op
], dest
, src
);
2119 case TGSI_OPCODE_LOG
:
2120 ttn_log(b
, op_trans
[tgsi_op
], dest
, src
);
2123 case TGSI_OPCODE_DST
:
2124 ttn_dst(b
, op_trans
[tgsi_op
], dest
, src
);
2127 case TGSI_OPCODE_LIT
:
2128 ttn_lit(b
, op_trans
[tgsi_op
], dest
, src
);
2131 case TGSI_OPCODE_DP2
:
2132 ttn_dp2(b
, op_trans
[tgsi_op
], dest
, src
);
2135 case TGSI_OPCODE_DP3
:
2136 ttn_dp3(b
, op_trans
[tgsi_op
], dest
, src
);
2139 case TGSI_OPCODE_DP4
:
2140 ttn_dp4(b
, op_trans
[tgsi_op
], dest
, src
);
2143 case TGSI_OPCODE_UMAD
:
2144 ttn_umad(b
, op_trans
[tgsi_op
], dest
, src
);
2147 case TGSI_OPCODE_LRP
:
2148 ttn_move_dest(b
, dest
, nir_flrp(b
, src
[2], src
[1], src
[0]));
2151 case TGSI_OPCODE_KILL
:
2152 ttn_kill(b
, op_trans
[tgsi_op
], dest
, src
);
2155 case TGSI_OPCODE_ARR
:
2156 ttn_arr(b
, op_trans
[tgsi_op
], dest
, src
);
2159 case TGSI_OPCODE_CMP
:
2160 ttn_cmp(b
, op_trans
[tgsi_op
], dest
, src
);
2163 case TGSI_OPCODE_UCMP
:
2164 ttn_ucmp(b
, op_trans
[tgsi_op
], dest
, src
);
2167 case TGSI_OPCODE_SGT
:
2168 ttn_sgt(b
, op_trans
[tgsi_op
], dest
, src
);
2171 case TGSI_OPCODE_SLE
:
2172 ttn_sle(b
, op_trans
[tgsi_op
], dest
, src
);
2175 case TGSI_OPCODE_KILL_IF
:
2176 ttn_kill_if(b
, op_trans
[tgsi_op
], dest
, src
);
2179 case TGSI_OPCODE_TEX
:
2180 case TGSI_OPCODE_TEX_LZ
:
2181 case TGSI_OPCODE_TXP
:
2182 case TGSI_OPCODE_TXL
:
2183 case TGSI_OPCODE_TXB
:
2184 case TGSI_OPCODE_TXD
:
2185 case TGSI_OPCODE_TEX2
:
2186 case TGSI_OPCODE_TXL2
:
2187 case TGSI_OPCODE_TXB2
:
2188 case TGSI_OPCODE_TXF
:
2189 case TGSI_OPCODE_TXF_LZ
:
2190 case TGSI_OPCODE_TG4
:
2191 case TGSI_OPCODE_LODQ
:
2192 ttn_tex(c
, dest
, src
);
2195 case TGSI_OPCODE_TXQ
:
2196 ttn_txq(c
, dest
, src
);
2199 case TGSI_OPCODE_LOAD
:
2200 case TGSI_OPCODE_STORE
:
2201 ttn_mem(c
, dest
, src
);
2204 case TGSI_OPCODE_NOP
:
2207 case TGSI_OPCODE_IF
:
2208 ttn_if(c
, src
[0], false);
2211 case TGSI_OPCODE_UIF
:
2212 ttn_if(c
, src
[0], true);
2215 case TGSI_OPCODE_ELSE
:
2219 case TGSI_OPCODE_ENDIF
:
2223 case TGSI_OPCODE_BGNLOOP
:
2227 case TGSI_OPCODE_BRK
:
2231 case TGSI_OPCODE_CONT
:
2235 case TGSI_OPCODE_ENDLOOP
:
2239 case TGSI_OPCODE_BARRIER
:
2244 if (op_trans
[tgsi_op
] != 0 || tgsi_op
== TGSI_OPCODE_MOV
) {
2245 ttn_alu(b
, op_trans
[tgsi_op
], dest
, dst_bitsize
, src
);
2247 fprintf(stderr
, "unknown TGSI opcode: %s\n",
2248 tgsi_get_opcode_name(tgsi_op
));
2254 if (tgsi_inst
->Instruction
.Saturate
) {
2255 assert(!dest
.dest
.is_ssa
);
2256 ttn_move_dest(b
, dest
, nir_fsat(b
, ttn_src_for_dest(b
, &dest
)));
2259 /* if the dst has a matching var, append store_var to move
2260 * output from reg to var
2262 nir_variable
*var
= ttn_get_var(c
, tgsi_dst
);
2264 unsigned index
= tgsi_dst
->Register
.Index
;
2265 unsigned offset
= c
->temp_regs
[index
].offset
;
2266 struct tgsi_ind_register
*indirect
= tgsi_dst
->Register
.Indirect
?
2267 &tgsi_dst
->Indirect
: NULL
;
2268 nir_src val
= nir_src_for_reg(dest
.dest
.reg
.reg
);
2269 nir_store_deref(b
, ttn_array_deref(c
, var
, offset
, indirect
),
2270 nir_ssa_for_src(b
, val
, 4), dest
.write_mask
);
2275 * Puts a NIR intrinsic to store of each TGSI_FILE_OUTPUT value to the output
2276 * variables at the end of the shader.
2278 * We don't generate these incrementally as the TGSI_FILE_OUTPUT values are
2279 * written, because there's no output load intrinsic, which means we couldn't
2280 * handle writemasks.
2283 ttn_add_output_stores(struct ttn_compile
*c
)
2285 nir_builder
*b
= &c
->build
;
2287 for (int i
= 0; i
< c
->build
.shader
->num_outputs
; i
++) {
2288 nir_variable
*var
= c
->outputs
[i
];
2292 nir_src src
= nir_src_for_reg(c
->output_regs
[i
].reg
);
2293 src
.reg
.base_offset
= c
->output_regs
[i
].offset
;
2295 nir_ssa_def
*store_value
= nir_ssa_for_src(b
, src
, 4);
2296 if (c
->build
.shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
2297 /* TGSI uses TGSI_SEMANTIC_POSITION.z for the depth output
2298 * and TGSI_SEMANTIC_STENCIL.y for the stencil output,
2299 * while NIR uses a single-component output.
2301 if (var
->data
.location
== FRAG_RESULT_DEPTH
)
2302 store_value
= nir_channel(b
, store_value
, 2);
2303 else if (var
->data
.location
== FRAG_RESULT_STENCIL
)
2304 store_value
= nir_channel(b
, store_value
, 1);
2306 /* FOGC and PSIZ are scalar values */
2307 if (var
->data
.location
== VARYING_SLOT_FOGC
||
2308 var
->data
.location
== VARYING_SLOT_PSIZ
) {
2309 store_value
= nir_channel(b
, store_value
, 0);
2313 nir_store_deref(b
, nir_build_deref_var(b
, var
), store_value
,
2314 (1 << store_value
->num_components
) - 1);
2319 * Parses the given TGSI tokens.
2322 ttn_parse_tgsi(struct ttn_compile
*c
, const void *tgsi_tokens
)
2324 struct tgsi_parse_context parser
;
2327 ret
= tgsi_parse_init(&parser
, tgsi_tokens
);
2328 assert(ret
== TGSI_PARSE_OK
);
2330 while (!tgsi_parse_end_of_tokens(&parser
)) {
2331 tgsi_parse_token(&parser
);
2332 c
->token
= &parser
.FullToken
;
2334 switch (parser
.FullToken
.Token
.Type
) {
2335 case TGSI_TOKEN_TYPE_DECLARATION
:
2336 ttn_emit_declaration(c
);
2339 case TGSI_TOKEN_TYPE_INSTRUCTION
:
2340 ttn_emit_instruction(c
);
2343 case TGSI_TOKEN_TYPE_IMMEDIATE
:
2344 ttn_emit_immediate(c
);
2349 tgsi_parse_free(&parser
);
2353 ttn_read_pipe_caps(struct ttn_compile
*c
,
2354 struct pipe_screen
*screen
)
2356 c
->cap_packed_uniforms
= screen
->get_param(screen
, PIPE_CAP_PACKED_UNIFORMS
);
2357 c
->cap_samplers_as_deref
= screen
->get_param(screen
, PIPE_CAP_NIR_SAMPLERS_AS_DEREF
);
2358 c
->cap_face_is_sysval
= screen
->get_param(screen
, PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
);
2359 c
->cap_position_is_sysval
= screen
->get_param(screen
, PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
);
2360 c
->cap_point_is_sysval
= screen
->get_param(screen
, PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL
);
2364 * Initializes a TGSI-to-NIR compiler.
2366 static struct ttn_compile
*
2367 ttn_compile_init(const void *tgsi_tokens
,
2368 const nir_shader_compiler_options
*options
,
2369 struct pipe_screen
*screen
)
2371 struct ttn_compile
*c
;
2372 struct nir_shader
*s
;
2373 struct tgsi_shader_info scan
;
2375 assert(options
|| screen
);
2376 c
= rzalloc(NULL
, struct ttn_compile
);
2378 tgsi_scan_shader(tgsi_tokens
, &scan
);
2383 screen
->get_compiler_options(screen
, PIPE_SHADER_IR_NIR
, scan
.processor
);
2386 nir_builder_init_simple_shader(&c
->build
, NULL
,
2387 tgsi_processor_to_shader_stage(scan
.processor
),
2390 s
= c
->build
.shader
;
2393 ttn_read_pipe_caps(c
, screen
);
2395 /* TTN used to be hard coded to always make FACE a sysval,
2396 * so it makes sense to preserve that behavior so users don't break. */
2397 c
->cap_face_is_sysval
= true;
2400 if (s
->info
.stage
== MESA_SHADER_FRAGMENT
)
2401 s
->info
.fs
.untyped_color_outputs
= true;
2403 s
->num_inputs
= scan
.file_max
[TGSI_FILE_INPUT
] + 1;
2404 s
->num_uniforms
= scan
.const_file_max
[0] + 1;
2405 s
->num_outputs
= scan
.file_max
[TGSI_FILE_OUTPUT
] + 1;
2406 s
->info
.num_ssbos
= util_last_bit(scan
.shader_buffers_declared
);
2407 s
->info
.num_ubos
= util_last_bit(scan
.const_buffers_declared
>> 1);
2408 s
->info
.num_images
= util_last_bit(scan
.images_declared
);
2409 s
->info
.num_textures
= util_last_bit(scan
.samplers_declared
);
2411 for (unsigned i
= 0; i
< TGSI_PROPERTY_COUNT
; i
++) {
2412 unsigned value
= scan
.properties
[i
];
2415 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
:
2416 break; /* handled in ttn_emit_declaration */
2417 case TGSI_PROPERTY_FS_COORD_ORIGIN
:
2418 if (s
->info
.stage
== MESA_SHADER_FRAGMENT
)
2419 s
->info
.fs
.origin_upper_left
= value
== TGSI_FS_COORD_ORIGIN_UPPER_LEFT
;
2421 case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
:
2422 if (s
->info
.stage
== MESA_SHADER_FRAGMENT
)
2423 s
->info
.fs
.pixel_center_integer
= value
== TGSI_FS_COORD_PIXEL_CENTER_INTEGER
;
2425 case TGSI_PROPERTY_FS_DEPTH_LAYOUT
:
2426 if (s
->info
.stage
== MESA_SHADER_FRAGMENT
)
2427 s
->info
.fs
.depth_layout
= ttn_get_depth_layout(value
);
2429 case TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
:
2430 if (s
->info
.stage
== MESA_SHADER_VERTEX
)
2431 s
->info
.vs
.window_space_position
= value
;
2433 case TGSI_PROPERTY_NEXT_SHADER
:
2434 s
->info
.next_stage
= tgsi_processor_to_shader_stage(value
);
2436 case TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
:
2437 if (s
->info
.stage
== MESA_SHADER_VERTEX
)
2438 s
->info
.vs
.blit_sgprs_amd
= value
;
2440 case TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
:
2441 if (s
->info
.stage
== MESA_SHADER_COMPUTE
)
2442 s
->info
.cs
.local_size
[0] = value
;
2444 case TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
:
2445 if (s
->info
.stage
== MESA_SHADER_COMPUTE
)
2446 s
->info
.cs
.local_size
[1] = value
;
2448 case TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
:
2449 if (s
->info
.stage
== MESA_SHADER_COMPUTE
)
2450 s
->info
.cs
.local_size
[2] = value
;
2452 case TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD
:
2453 if (s
->info
.stage
== MESA_SHADER_COMPUTE
)
2454 s
->info
.cs
.user_data_components_amd
= value
;
2458 fprintf(stderr
, "tgsi_to_nir: unhandled TGSI property %u = %u\n",
2460 unreachable("unhandled TGSI property");
2465 if (s
->info
.stage
== MESA_SHADER_COMPUTE
&&
2466 (!s
->info
.cs
.local_size
[0] ||
2467 !s
->info
.cs
.local_size
[1] ||
2468 !s
->info
.cs
.local_size
[2]))
2469 s
->info
.cs
.local_size_variable
= true;
2471 c
->inputs
= rzalloc_array(c
, struct nir_variable
*, s
->num_inputs
);
2472 c
->outputs
= rzalloc_array(c
, struct nir_variable
*, s
->num_outputs
);
2474 c
->output_regs
= rzalloc_array(c
, struct ttn_reg_info
,
2475 scan
.file_max
[TGSI_FILE_OUTPUT
] + 1);
2476 c
->temp_regs
= rzalloc_array(c
, struct ttn_reg_info
,
2477 scan
.file_max
[TGSI_FILE_TEMPORARY
] + 1);
2478 c
->imm_defs
= rzalloc_array(c
, nir_ssa_def
*,
2479 scan
.file_max
[TGSI_FILE_IMMEDIATE
] + 1);
2481 c
->num_samp_types
= scan
.file_max
[TGSI_FILE_SAMPLER_VIEW
] + 1;
2482 c
->samp_types
= rzalloc_array(c
, nir_alu_type
, c
->num_samp_types
);
2484 c
->if_stack
= rzalloc_array(c
, nir_cursor
,
2485 (scan
.opcode_count
[TGSI_OPCODE_IF
] +
2486 scan
.opcode_count
[TGSI_OPCODE_UIF
]) * 2);
2487 c
->loop_stack
= rzalloc_array(c
, nir_cursor
,
2488 scan
.opcode_count
[TGSI_OPCODE_BGNLOOP
]);
2491 ttn_parse_tgsi(c
, tgsi_tokens
);
2492 ttn_add_output_stores(c
);
2494 nir_validate_shader(c
->build
.shader
, "TTN: after parsing TGSI and creating the NIR shader");
2500 ttn_optimize_nir(nir_shader
*nir
)
2506 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2508 if (nir
->options
->lower_to_scalar
) {
2509 NIR_PASS_V(nir
, nir_lower_alu_to_scalar
, NULL
, NULL
);
2510 NIR_PASS_V(nir
, nir_lower_phis_to_scalar
);
2513 NIR_PASS_V(nir
, nir_lower_alu
);
2514 NIR_PASS_V(nir
, nir_lower_pack
);
2515 NIR_PASS(progress
, nir
, nir_copy_prop
);
2516 NIR_PASS(progress
, nir
, nir_opt_remove_phis
);
2517 NIR_PASS(progress
, nir
, nir_opt_dce
);
2519 if (nir_opt_trivial_continues(nir
)) {
2521 NIR_PASS(progress
, nir
, nir_copy_prop
);
2522 NIR_PASS(progress
, nir
, nir_opt_dce
);
2525 NIR_PASS(progress
, nir
, nir_opt_if
, false);
2526 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
2527 NIR_PASS(progress
, nir
, nir_opt_cse
);
2528 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 8, true, true);
2530 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
2531 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
2533 NIR_PASS(progress
, nir
, nir_opt_undef
);
2534 NIR_PASS(progress
, nir
, nir_opt_conditional_discard
);
2536 if (nir
->options
->max_unroll_iterations
) {
2537 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
, (nir_variable_mode
)0);
2545 * Finalizes the NIR in a similar way as st_glsl_to_nir does.
2547 * Drivers expect that these passes are already performed,
2548 * so we have to do it here too.
2551 ttn_finalize_nir(struct ttn_compile
*c
, struct pipe_screen
*screen
)
2553 struct nir_shader
*nir
= c
->build
.shader
;
2555 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2556 NIR_PASS_V(nir
, nir_lower_regs_to_ssa
);
2558 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
2559 NIR_PASS_V(nir
, nir_split_var_copies
);
2560 NIR_PASS_V(nir
, nir_lower_var_copies
);
2561 NIR_PASS_V(nir
, nir_lower_system_values
);
2562 NIR_PASS_V(nir
, nir_lower_compute_system_values
);
2564 if (c
->cap_packed_uniforms
)
2565 NIR_PASS_V(nir
, nir_lower_uniforms_to_ubo
, 16);
2567 if (!c
->cap_samplers_as_deref
)
2568 NIR_PASS_V(nir
, nir_lower_samplers
);
2570 if (screen
->finalize_nir
) {
2571 screen
->finalize_nir(screen
, nir
, true);
2573 ttn_optimize_nir(nir
);
2574 nir_shader_gather_info(nir
, c
->build
.impl
);
2577 nir
->info
.num_images
= c
->num_images
;
2578 nir
->info
.num_textures
= c
->num_samplers
;
2580 nir_validate_shader(nir
, "TTN: after all optimizations");
2583 static void save_nir_to_disk_cache(struct disk_cache
*cache
,
2584 uint8_t key
[CACHE_KEY_SIZE
],
2585 const nir_shader
*s
)
2587 struct blob blob
= {0};
2590 /* Because we cannot fully trust disk_cache_put
2591 * (EGL_ANDROID_blob_cache) we add the shader size,
2592 * which we'll check after disk_cache_get().
2594 if (blob_reserve_uint32(&blob
) != 0) {
2599 nir_serialize(&blob
, s
, true);
2600 *(uint32_t *)blob
.data
= blob
.size
;
2602 disk_cache_put(cache
, key
, blob
.data
, blob
.size
, NULL
);
2607 load_nir_from_disk_cache(struct disk_cache
*cache
,
2608 struct pipe_screen
*screen
,
2609 uint8_t key
[CACHE_KEY_SIZE
],
2612 const nir_shader_compiler_options
*options
=
2613 screen
->get_compiler_options(screen
, PIPE_SHADER_IR_NIR
, processor
);
2614 struct blob_reader blob_reader
;
2618 uint32_t *buffer
= (uint32_t *)disk_cache_get(cache
, key
, &size
);
2622 /* Match found. No need to check crc32 or other things.
2623 * disk_cache_get is supposed to do that for us.
2624 * However we do still check if the first element is indeed the size,
2625 * as we cannot fully trust disk_cache_get (EGL_ANDROID_blob_cache) */
2626 if (buffer
[0] != size
) {
2631 blob_reader_init(&blob_reader
, buffer
+ 1, size
);
2632 s
= nir_deserialize(NULL
, options
, &blob_reader
);
2633 free(buffer
); /* buffer was malloc-ed */
2638 tgsi_to_nir(const void *tgsi_tokens
,
2639 struct pipe_screen
*screen
,
2640 bool allow_disk_cache
)
2642 struct disk_cache
*cache
= NULL
;
2643 struct ttn_compile
*c
;
2644 struct nir_shader
*s
= NULL
;
2645 uint8_t key
[CACHE_KEY_SIZE
];
2648 if (allow_disk_cache
)
2649 cache
= screen
->get_disk_shader_cache(screen
);
2651 /* Look first in the cache */
2653 disk_cache_compute_key(cache
,
2655 tgsi_num_tokens(tgsi_tokens
) * sizeof(struct tgsi_token
),
2657 processor
= tgsi_get_processor_type(tgsi_tokens
);
2658 s
= load_nir_from_disk_cache(cache
, screen
, key
, processor
);
2664 /* Not in the cache */
2666 c
= ttn_compile_init(tgsi_tokens
, NULL
, screen
);
2667 s
= c
->build
.shader
;
2668 ttn_finalize_nir(c
, screen
);
2672 save_nir_to_disk_cache(cache
, key
, s
);
2678 tgsi_to_nir_noscreen(const void *tgsi_tokens
,
2679 const nir_shader_compiler_options
*options
)
2681 struct ttn_compile
*c
;
2682 struct nir_shader
*s
;
2684 c
= ttn_compile_init(tgsi_tokens
, options
, NULL
);
2685 s
= c
->build
.shader
;