1 /**************************************************************************
3 * Copyright 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 **************************************************************************/
30 * TGSI interpreter/executor.
32 * Flow control information:
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_memory.h"
62 #include "util/u_math.h"
67 #define TILE_TOP_LEFT 0
68 #define TILE_TOP_RIGHT 1
69 #define TILE_BOTTOM_LEFT 2
70 #define TILE_BOTTOM_RIGHT 3
73 micro_abs(union tgsi_exec_channel
*dst
,
74 const union tgsi_exec_channel
*src
)
76 dst
->f
[0] = fabsf(src
->f
[0]);
77 dst
->f
[1] = fabsf(src
->f
[1]);
78 dst
->f
[2] = fabsf(src
->f
[2]);
79 dst
->f
[3] = fabsf(src
->f
[3]);
83 micro_arl(union tgsi_exec_channel
*dst
,
84 const union tgsi_exec_channel
*src
)
86 dst
->i
[0] = (int)floorf(src
->f
[0]);
87 dst
->i
[1] = (int)floorf(src
->f
[1]);
88 dst
->i
[2] = (int)floorf(src
->f
[2]);
89 dst
->i
[3] = (int)floorf(src
->f
[3]);
93 micro_arr(union tgsi_exec_channel
*dst
,
94 const union tgsi_exec_channel
*src
)
96 dst
->i
[0] = (int)floorf(src
->f
[0] + 0.5f
);
97 dst
->i
[1] = (int)floorf(src
->f
[1] + 0.5f
);
98 dst
->i
[2] = (int)floorf(src
->f
[2] + 0.5f
);
99 dst
->i
[3] = (int)floorf(src
->f
[3] + 0.5f
);
103 micro_ceil(union tgsi_exec_channel
*dst
,
104 const union tgsi_exec_channel
*src
)
106 dst
->f
[0] = ceilf(src
->f
[0]);
107 dst
->f
[1] = ceilf(src
->f
[1]);
108 dst
->f
[2] = ceilf(src
->f
[2]);
109 dst
->f
[3] = ceilf(src
->f
[3]);
113 micro_clamp(union tgsi_exec_channel
*dst
,
114 const union tgsi_exec_channel
*src0
,
115 const union tgsi_exec_channel
*src1
,
116 const union tgsi_exec_channel
*src2
)
118 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src1
->f
[0] : src0
->f
[0] > src2
->f
[0] ? src2
->f
[0] : src0
->f
[0];
119 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src1
->f
[1] : src0
->f
[1] > src2
->f
[1] ? src2
->f
[1] : src0
->f
[1];
120 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src1
->f
[2] : src0
->f
[2] > src2
->f
[2] ? src2
->f
[2] : src0
->f
[2];
121 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src1
->f
[3] : src0
->f
[3] > src2
->f
[3] ? src2
->f
[3] : src0
->f
[3];
125 micro_cmp(union tgsi_exec_channel
*dst
,
126 const union tgsi_exec_channel
*src0
,
127 const union tgsi_exec_channel
*src1
,
128 const union tgsi_exec_channel
*src2
)
130 dst
->f
[0] = src0
->f
[0] < 0.0f
? src1
->f
[0] : src2
->f
[0];
131 dst
->f
[1] = src0
->f
[1] < 0.0f
? src1
->f
[1] : src2
->f
[1];
132 dst
->f
[2] = src0
->f
[2] < 0.0f
? src1
->f
[2] : src2
->f
[2];
133 dst
->f
[3] = src0
->f
[3] < 0.0f
? src1
->f
[3] : src2
->f
[3];
137 micro_cnd(union tgsi_exec_channel
*dst
,
138 const union tgsi_exec_channel
*src0
,
139 const union tgsi_exec_channel
*src1
,
140 const union tgsi_exec_channel
*src2
)
142 dst
->f
[0] = src2
->f
[0] > 0.5f
? src0
->f
[0] : src1
->f
[0];
143 dst
->f
[1] = src2
->f
[1] > 0.5f
? src0
->f
[1] : src1
->f
[1];
144 dst
->f
[2] = src2
->f
[2] > 0.5f
? src0
->f
[2] : src1
->f
[2];
145 dst
->f
[3] = src2
->f
[3] > 0.5f
? src0
->f
[3] : src1
->f
[3];
149 micro_cos(union tgsi_exec_channel
*dst
,
150 const union tgsi_exec_channel
*src
)
152 dst
->f
[0] = cosf(src
->f
[0]);
153 dst
->f
[1] = cosf(src
->f
[1]);
154 dst
->f
[2] = cosf(src
->f
[2]);
155 dst
->f
[3] = cosf(src
->f
[3]);
159 micro_ddx(union tgsi_exec_channel
*dst
,
160 const union tgsi_exec_channel
*src
)
165 dst
->f
[3] = src
->f
[TILE_BOTTOM_RIGHT
] - src
->f
[TILE_BOTTOM_LEFT
];
169 micro_ddy(union tgsi_exec_channel
*dst
,
170 const union tgsi_exec_channel
*src
)
175 dst
->f
[3] = src
->f
[TILE_BOTTOM_LEFT
] - src
->f
[TILE_TOP_LEFT
];
179 micro_exp2(union tgsi_exec_channel
*dst
,
180 const union tgsi_exec_channel
*src
)
183 dst
->f
[0] = util_fast_exp2(src
->f
[0]);
184 dst
->f
[1] = util_fast_exp2(src
->f
[1]);
185 dst
->f
[2] = util_fast_exp2(src
->f
[2]);
186 dst
->f
[3] = util_fast_exp2(src
->f
[3]);
189 /* Inf is okay for this instruction, so clamp it to silence assertions. */
191 union tgsi_exec_channel clamped
;
193 for (i
= 0; i
< 4; i
++) {
194 if (src
->f
[i
] > 127.99999f
) {
195 clamped
.f
[i
] = 127.99999f
;
196 } else if (src
->f
[i
] < -126.99999f
) {
197 clamped
.f
[i
] = -126.99999f
;
199 clamped
.f
[i
] = src
->f
[i
];
205 dst
->f
[0] = powf(2.0f
, src
->f
[0]);
206 dst
->f
[1] = powf(2.0f
, src
->f
[1]);
207 dst
->f
[2] = powf(2.0f
, src
->f
[2]);
208 dst
->f
[3] = powf(2.0f
, src
->f
[3]);
209 #endif /* FAST_MATH */
213 micro_flr(union tgsi_exec_channel
*dst
,
214 const union tgsi_exec_channel
*src
)
216 dst
->f
[0] = floorf(src
->f
[0]);
217 dst
->f
[1] = floorf(src
->f
[1]);
218 dst
->f
[2] = floorf(src
->f
[2]);
219 dst
->f
[3] = floorf(src
->f
[3]);
223 micro_frc(union tgsi_exec_channel
*dst
,
224 const union tgsi_exec_channel
*src
)
226 dst
->f
[0] = src
->f
[0] - floorf(src
->f
[0]);
227 dst
->f
[1] = src
->f
[1] - floorf(src
->f
[1]);
228 dst
->f
[2] = src
->f
[2] - floorf(src
->f
[2]);
229 dst
->f
[3] = src
->f
[3] - floorf(src
->f
[3]);
233 micro_iabs(union tgsi_exec_channel
*dst
,
234 const union tgsi_exec_channel
*src
)
236 dst
->i
[0] = src
->i
[0] >= 0 ? src
->i
[0] : -src
->i
[0];
237 dst
->i
[1] = src
->i
[1] >= 0 ? src
->i
[1] : -src
->i
[1];
238 dst
->i
[2] = src
->i
[2] >= 0 ? src
->i
[2] : -src
->i
[2];
239 dst
->i
[3] = src
->i
[3] >= 0 ? src
->i
[3] : -src
->i
[3];
243 micro_ineg(union tgsi_exec_channel
*dst
,
244 const union tgsi_exec_channel
*src
)
246 dst
->i
[0] = -src
->i
[0];
247 dst
->i
[1] = -src
->i
[1];
248 dst
->i
[2] = -src
->i
[2];
249 dst
->i
[3] = -src
->i
[3];
253 micro_lg2(union tgsi_exec_channel
*dst
,
254 const union tgsi_exec_channel
*src
)
257 dst
->f
[0] = util_fast_log2(src
->f
[0]);
258 dst
->f
[1] = util_fast_log2(src
->f
[1]);
259 dst
->f
[2] = util_fast_log2(src
->f
[2]);
260 dst
->f
[3] = util_fast_log2(src
->f
[3]);
262 dst
->f
[0] = logf(src
->f
[0]) * 1.442695f
;
263 dst
->f
[1] = logf(src
->f
[1]) * 1.442695f
;
264 dst
->f
[2] = logf(src
->f
[2]) * 1.442695f
;
265 dst
->f
[3] = logf(src
->f
[3]) * 1.442695f
;
270 micro_lrp(union tgsi_exec_channel
*dst
,
271 const union tgsi_exec_channel
*src0
,
272 const union tgsi_exec_channel
*src1
,
273 const union tgsi_exec_channel
*src2
)
275 dst
->f
[0] = src0
->f
[0] * (src1
->f
[0] - src2
->f
[0]) + src2
->f
[0];
276 dst
->f
[1] = src0
->f
[1] * (src1
->f
[1] - src2
->f
[1]) + src2
->f
[1];
277 dst
->f
[2] = src0
->f
[2] * (src1
->f
[2] - src2
->f
[2]) + src2
->f
[2];
278 dst
->f
[3] = src0
->f
[3] * (src1
->f
[3] - src2
->f
[3]) + src2
->f
[3];
282 micro_mad(union tgsi_exec_channel
*dst
,
283 const union tgsi_exec_channel
*src0
,
284 const union tgsi_exec_channel
*src1
,
285 const union tgsi_exec_channel
*src2
)
287 dst
->f
[0] = src0
->f
[0] * src1
->f
[0] + src2
->f
[0];
288 dst
->f
[1] = src0
->f
[1] * src1
->f
[1] + src2
->f
[1];
289 dst
->f
[2] = src0
->f
[2] * src1
->f
[2] + src2
->f
[2];
290 dst
->f
[3] = src0
->f
[3] * src1
->f
[3] + src2
->f
[3];
294 micro_mov(union tgsi_exec_channel
*dst
,
295 const union tgsi_exec_channel
*src
)
297 dst
->u
[0] = src
->u
[0];
298 dst
->u
[1] = src
->u
[1];
299 dst
->u
[2] = src
->u
[2];
300 dst
->u
[3] = src
->u
[3];
304 micro_rcp(union tgsi_exec_channel
*dst
,
305 const union tgsi_exec_channel
*src
)
307 #if 0 /* for debugging */
308 assert(src
->f
[0] != 0.0f
);
309 assert(src
->f
[1] != 0.0f
);
310 assert(src
->f
[2] != 0.0f
);
311 assert(src
->f
[3] != 0.0f
);
313 dst
->f
[0] = 1.0f
/ src
->f
[0];
314 dst
->f
[1] = 1.0f
/ src
->f
[1];
315 dst
->f
[2] = 1.0f
/ src
->f
[2];
316 dst
->f
[3] = 1.0f
/ src
->f
[3];
320 micro_rnd(union tgsi_exec_channel
*dst
,
321 const union tgsi_exec_channel
*src
)
323 dst
->f
[0] = floorf(src
->f
[0] + 0.5f
);
324 dst
->f
[1] = floorf(src
->f
[1] + 0.5f
);
325 dst
->f
[2] = floorf(src
->f
[2] + 0.5f
);
326 dst
->f
[3] = floorf(src
->f
[3] + 0.5f
);
330 micro_rsq(union tgsi_exec_channel
*dst
,
331 const union tgsi_exec_channel
*src
)
333 #if 0 /* for debugging */
334 assert(src
->f
[0] != 0.0f
);
335 assert(src
->f
[1] != 0.0f
);
336 assert(src
->f
[2] != 0.0f
);
337 assert(src
->f
[3] != 0.0f
);
339 dst
->f
[0] = 1.0f
/ sqrtf(fabsf(src
->f
[0]));
340 dst
->f
[1] = 1.0f
/ sqrtf(fabsf(src
->f
[1]));
341 dst
->f
[2] = 1.0f
/ sqrtf(fabsf(src
->f
[2]));
342 dst
->f
[3] = 1.0f
/ sqrtf(fabsf(src
->f
[3]));
346 micro_seq(union tgsi_exec_channel
*dst
,
347 const union tgsi_exec_channel
*src0
,
348 const union tgsi_exec_channel
*src1
)
350 dst
->f
[0] = src0
->f
[0] == src1
->f
[0] ? 1.0f
: 0.0f
;
351 dst
->f
[1] = src0
->f
[1] == src1
->f
[1] ? 1.0f
: 0.0f
;
352 dst
->f
[2] = src0
->f
[2] == src1
->f
[2] ? 1.0f
: 0.0f
;
353 dst
->f
[3] = src0
->f
[3] == src1
->f
[3] ? 1.0f
: 0.0f
;
357 micro_sge(union tgsi_exec_channel
*dst
,
358 const union tgsi_exec_channel
*src0
,
359 const union tgsi_exec_channel
*src1
)
361 dst
->f
[0] = src0
->f
[0] >= src1
->f
[0] ? 1.0f
: 0.0f
;
362 dst
->f
[1] = src0
->f
[1] >= src1
->f
[1] ? 1.0f
: 0.0f
;
363 dst
->f
[2] = src0
->f
[2] >= src1
->f
[2] ? 1.0f
: 0.0f
;
364 dst
->f
[3] = src0
->f
[3] >= src1
->f
[3] ? 1.0f
: 0.0f
;
368 micro_sgn(union tgsi_exec_channel
*dst
,
369 const union tgsi_exec_channel
*src
)
371 dst
->f
[0] = src
->f
[0] < 0.0f
? -1.0f
: src
->f
[0] > 0.0f
? 1.0f
: 0.0f
;
372 dst
->f
[1] = src
->f
[1] < 0.0f
? -1.0f
: src
->f
[1] > 0.0f
? 1.0f
: 0.0f
;
373 dst
->f
[2] = src
->f
[2] < 0.0f
? -1.0f
: src
->f
[2] > 0.0f
? 1.0f
: 0.0f
;
374 dst
->f
[3] = src
->f
[3] < 0.0f
? -1.0f
: src
->f
[3] > 0.0f
? 1.0f
: 0.0f
;
378 micro_sgt(union tgsi_exec_channel
*dst
,
379 const union tgsi_exec_channel
*src0
,
380 const union tgsi_exec_channel
*src1
)
382 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? 1.0f
: 0.0f
;
383 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? 1.0f
: 0.0f
;
384 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? 1.0f
: 0.0f
;
385 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? 1.0f
: 0.0f
;
389 micro_sin(union tgsi_exec_channel
*dst
,
390 const union tgsi_exec_channel
*src
)
392 dst
->f
[0] = sinf(src
->f
[0]);
393 dst
->f
[1] = sinf(src
->f
[1]);
394 dst
->f
[2] = sinf(src
->f
[2]);
395 dst
->f
[3] = sinf(src
->f
[3]);
399 micro_sle(union tgsi_exec_channel
*dst
,
400 const union tgsi_exec_channel
*src0
,
401 const union tgsi_exec_channel
*src1
)
403 dst
->f
[0] = src0
->f
[0] <= src1
->f
[0] ? 1.0f
: 0.0f
;
404 dst
->f
[1] = src0
->f
[1] <= src1
->f
[1] ? 1.0f
: 0.0f
;
405 dst
->f
[2] = src0
->f
[2] <= src1
->f
[2] ? 1.0f
: 0.0f
;
406 dst
->f
[3] = src0
->f
[3] <= src1
->f
[3] ? 1.0f
: 0.0f
;
410 micro_slt(union tgsi_exec_channel
*dst
,
411 const union tgsi_exec_channel
*src0
,
412 const union tgsi_exec_channel
*src1
)
414 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? 1.0f
: 0.0f
;
415 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? 1.0f
: 0.0f
;
416 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? 1.0f
: 0.0f
;
417 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? 1.0f
: 0.0f
;
421 micro_sne(union tgsi_exec_channel
*dst
,
422 const union tgsi_exec_channel
*src0
,
423 const union tgsi_exec_channel
*src1
)
425 dst
->f
[0] = src0
->f
[0] != src1
->f
[0] ? 1.0f
: 0.0f
;
426 dst
->f
[1] = src0
->f
[1] != src1
->f
[1] ? 1.0f
: 0.0f
;
427 dst
->f
[2] = src0
->f
[2] != src1
->f
[2] ? 1.0f
: 0.0f
;
428 dst
->f
[3] = src0
->f
[3] != src1
->f
[3] ? 1.0f
: 0.0f
;
432 micro_sfl(union tgsi_exec_channel
*dst
)
441 micro_str(union tgsi_exec_channel
*dst
)
450 micro_trunc(union tgsi_exec_channel
*dst
,
451 const union tgsi_exec_channel
*src
)
453 dst
->f
[0] = (float)(int)src
->f
[0];
454 dst
->f
[1] = (float)(int)src
->f
[1];
455 dst
->f
[2] = (float)(int)src
->f
[2];
456 dst
->f
[3] = (float)(int)src
->f
[3];
465 enum tgsi_exec_datatype
{
466 TGSI_EXEC_DATA_FLOAT
,
472 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
474 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
475 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
476 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
477 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
478 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
479 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
482 /** The execution mask depends on the conditional mask and the loop mask */
483 #define UPDATE_EXEC_MASK(MACH) \
484 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
487 static const union tgsi_exec_channel ZeroVec
=
488 { { 0.0, 0.0, 0.0, 0.0 } };
490 static const union tgsi_exec_channel OneVec
= {
491 {1.0f
, 1.0f
, 1.0f
, 1.0f
}
494 static const union tgsi_exec_channel P128Vec
= {
495 {128.0f
, 128.0f
, 128.0f
, 128.0f
}
498 static const union tgsi_exec_channel M128Vec
= {
499 {-128.0f
, -128.0f
, -128.0f
, -128.0f
}
504 * Assert that none of the float values in 'chan' are infinite or NaN.
505 * NaN and Inf may occur normally during program execution and should
506 * not lead to crashes, etc. But when debugging, it's helpful to catch
510 check_inf_or_nan(const union tgsi_exec_channel
*chan
)
512 assert(!util_is_inf_or_nan((chan
)->f
[0]));
513 assert(!util_is_inf_or_nan((chan
)->f
[1]));
514 assert(!util_is_inf_or_nan((chan
)->f
[2]));
515 assert(!util_is_inf_or_nan((chan
)->f
[3]));
521 print_chan(const char *msg
, const union tgsi_exec_channel
*chan
)
523 debug_printf("%s = {%f, %f, %f, %f}\n",
524 msg
, chan
->f
[0], chan
->f
[1], chan
->f
[2], chan
->f
[3]);
531 print_temp(const struct tgsi_exec_machine
*mach
, uint index
)
533 const struct tgsi_exec_vector
*tmp
= &mach
->Temps
[index
];
535 debug_printf("Temp[%u] =\n", index
);
536 for (i
= 0; i
< 4; i
++) {
537 debug_printf(" %c: { %f, %f, %f, %f }\n",
549 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine
*mach
,
552 const unsigned *buf_sizes
)
556 for (i
= 0; i
< num_bufs
; i
++) {
557 mach
->Consts
[i
] = bufs
[i
];
558 mach
->ConstsSize
[i
] = buf_sizes
[i
];
564 * Check if there's a potential src/dst register data dependency when
565 * using SOA execution.
568 * This would expand into:
573 * The second instruction will have the wrong value for t0 if executed as-is.
576 tgsi_check_soa_dependencies(const struct tgsi_full_instruction
*inst
)
580 uint writemask
= inst
->Dst
[0].Register
.WriteMask
;
581 if (writemask
== TGSI_WRITEMASK_X
||
582 writemask
== TGSI_WRITEMASK_Y
||
583 writemask
== TGSI_WRITEMASK_Z
||
584 writemask
== TGSI_WRITEMASK_W
||
585 writemask
== TGSI_WRITEMASK_NONE
) {
586 /* no chance of data dependency */
590 /* loop over src regs */
591 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
592 if ((inst
->Src
[i
].Register
.File
==
593 inst
->Dst
[0].Register
.File
) &&
594 ((inst
->Src
[i
].Register
.Index
==
595 inst
->Dst
[0].Register
.Index
) ||
596 inst
->Src
[i
].Register
.Indirect
||
597 inst
->Dst
[0].Register
.Indirect
)) {
598 /* loop over dest channels */
599 uint channelsWritten
= 0x0;
600 for (chan
= 0; chan
< NUM_CHANNELS
; chan
++) {
601 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
602 /* check if we're reading a channel that's been written */
603 uint swizzle
= tgsi_util_get_full_src_register_swizzle(&inst
->Src
[i
], chan
);
604 if (channelsWritten
& (1 << swizzle
)) {
608 channelsWritten
|= (1 << chan
);
618 * Initialize machine state by expanding tokens to full instructions,
619 * allocating temporary storage, setting up constants, etc.
620 * After this, we can call tgsi_exec_machine_run() many times.
623 tgsi_exec_machine_bind_shader(
624 struct tgsi_exec_machine
*mach
,
625 const struct tgsi_token
*tokens
,
627 struct tgsi_sampler
**samplers
)
630 struct tgsi_parse_context parse
;
631 struct tgsi_full_instruction
*instructions
;
632 struct tgsi_full_declaration
*declarations
;
633 uint maxInstructions
= 10, numInstructions
= 0;
634 uint maxDeclarations
= 10, numDeclarations
= 0;
637 tgsi_dump(tokens
, 0);
646 mach
->Tokens
= tokens
;
647 mach
->Samplers
= samplers
;
650 /* unbind and free all */
651 if (mach
->Declarations
) {
652 FREE( mach
->Declarations
);
654 mach
->Declarations
= NULL
;
655 mach
->NumDeclarations
= 0;
657 if (mach
->Instructions
) {
658 FREE( mach
->Instructions
);
660 mach
->Instructions
= NULL
;
661 mach
->NumInstructions
= 0;
666 k
= tgsi_parse_init (&parse
, mach
->Tokens
);
667 if (k
!= TGSI_PARSE_OK
) {
668 debug_printf( "Problem parsing!\n" );
672 mach
->Processor
= parse
.FullHeader
.Processor
.Processor
;
675 declarations
= (struct tgsi_full_declaration
*)
676 MALLOC( maxDeclarations
* sizeof(struct tgsi_full_declaration
) );
682 instructions
= (struct tgsi_full_instruction
*)
683 MALLOC( maxInstructions
* sizeof(struct tgsi_full_instruction
) );
686 FREE( declarations
);
690 while( !tgsi_parse_end_of_tokens( &parse
) ) {
693 tgsi_parse_token( &parse
);
694 switch( parse
.FullToken
.Token
.Type
) {
695 case TGSI_TOKEN_TYPE_DECLARATION
:
696 /* save expanded declaration */
697 if (numDeclarations
== maxDeclarations
) {
698 declarations
= REALLOC(declarations
,
700 * sizeof(struct tgsi_full_declaration
),
701 (maxDeclarations
+ 10)
702 * sizeof(struct tgsi_full_declaration
));
703 maxDeclarations
+= 10;
705 if (parse
.FullToken
.FullDeclaration
.Declaration
.File
== TGSI_FILE_OUTPUT
) {
707 for (reg
= parse
.FullToken
.FullDeclaration
.Range
.First
;
708 reg
<= parse
.FullToken
.FullDeclaration
.Range
.Last
;
713 if (parse
.FullToken
.FullDeclaration
.Declaration
.File
==
714 TGSI_FILE_IMMEDIATE_ARRAY
) {
716 struct tgsi_full_declaration
*decl
=
717 &parse
.FullToken
.FullDeclaration
;
718 debug_assert(decl
->Range
.Last
< TGSI_EXEC_NUM_IMMEDIATES
);
719 for (reg
= decl
->Range
.First
; reg
<= decl
->Range
.Last
; ++reg
) {
720 for( i
= 0; i
< 4; i
++ ) {
721 int idx
= reg
* 4 + i
;
722 mach
->ImmArray
[reg
][i
] = decl
->ImmediateData
.u
[idx
].Float
;
726 memcpy(declarations
+ numDeclarations
,
727 &parse
.FullToken
.FullDeclaration
,
728 sizeof(declarations
[0]));
732 case TGSI_TOKEN_TYPE_IMMEDIATE
:
734 uint size
= parse
.FullToken
.FullImmediate
.Immediate
.NrTokens
- 1;
736 assert( mach
->ImmLimit
+ 1 <= TGSI_EXEC_NUM_IMMEDIATES
);
738 for( i
= 0; i
< size
; i
++ ) {
739 mach
->Imms
[mach
->ImmLimit
][i
] =
740 parse
.FullToken
.FullImmediate
.u
[i
].Float
;
746 case TGSI_TOKEN_TYPE_INSTRUCTION
:
748 /* save expanded instruction */
749 if (numInstructions
== maxInstructions
) {
750 instructions
= REALLOC(instructions
,
752 * sizeof(struct tgsi_full_instruction
),
753 (maxInstructions
+ 10)
754 * sizeof(struct tgsi_full_instruction
));
755 maxInstructions
+= 10;
758 memcpy(instructions
+ numInstructions
,
759 &parse
.FullToken
.FullInstruction
,
760 sizeof(instructions
[0]));
765 case TGSI_TOKEN_TYPE_PROPERTY
:
772 tgsi_parse_free (&parse
);
774 if (mach
->Declarations
) {
775 FREE( mach
->Declarations
);
777 mach
->Declarations
= declarations
;
778 mach
->NumDeclarations
= numDeclarations
;
780 if (mach
->Instructions
) {
781 FREE( mach
->Instructions
);
783 mach
->Instructions
= instructions
;
784 mach
->NumInstructions
= numInstructions
;
788 struct tgsi_exec_machine
*
789 tgsi_exec_machine_create( void )
791 struct tgsi_exec_machine
*mach
;
794 mach
= align_malloc( sizeof *mach
, 16 );
798 memset(mach
, 0, sizeof(*mach
));
800 mach
->Addrs
= &mach
->Temps
[TGSI_EXEC_TEMP_ADDR
];
801 mach
->MaxGeometryShaderOutputs
= TGSI_MAX_TOTAL_VERTICES
;
802 mach
->Predicates
= &mach
->Temps
[TGSI_EXEC_TEMP_P0
];
804 /* Setup constants needed by the SSE2 executor. */
805 for( i
= 0; i
< 4; i
++ ) {
806 mach
->Temps
[TGSI_EXEC_TEMP_00000000_I
].xyzw
[TGSI_EXEC_TEMP_00000000_C
].u
[i
] = 0x00000000;
807 mach
->Temps
[TGSI_EXEC_TEMP_7FFFFFFF_I
].xyzw
[TGSI_EXEC_TEMP_7FFFFFFF_C
].u
[i
] = 0x7FFFFFFF;
808 mach
->Temps
[TGSI_EXEC_TEMP_80000000_I
].xyzw
[TGSI_EXEC_TEMP_80000000_C
].u
[i
] = 0x80000000;
809 mach
->Temps
[TGSI_EXEC_TEMP_FFFFFFFF_I
].xyzw
[TGSI_EXEC_TEMP_FFFFFFFF_C
].u
[i
] = 0xFFFFFFFF; /* not used */
810 mach
->Temps
[TGSI_EXEC_TEMP_ONE_I
].xyzw
[TGSI_EXEC_TEMP_ONE_C
].f
[i
] = 1.0f
;
811 mach
->Temps
[TGSI_EXEC_TEMP_TWO_I
].xyzw
[TGSI_EXEC_TEMP_TWO_C
].f
[i
] = 2.0f
; /* not used */
812 mach
->Temps
[TGSI_EXEC_TEMP_128_I
].xyzw
[TGSI_EXEC_TEMP_128_C
].f
[i
] = 128.0f
;
813 mach
->Temps
[TGSI_EXEC_TEMP_MINUS_128_I
].xyzw
[TGSI_EXEC_TEMP_MINUS_128_C
].f
[i
] = -128.0f
;
814 mach
->Temps
[TGSI_EXEC_TEMP_THREE_I
].xyzw
[TGSI_EXEC_TEMP_THREE_C
].f
[i
] = 3.0f
;
815 mach
->Temps
[TGSI_EXEC_TEMP_HALF_I
].xyzw
[TGSI_EXEC_TEMP_HALF_C
].f
[i
] = 0.5f
;
819 /* silence warnings */
833 tgsi_exec_machine_destroy(struct tgsi_exec_machine
*mach
)
836 if (mach
->Instructions
)
837 FREE(mach
->Instructions
);
838 if (mach
->Declarations
)
839 FREE(mach
->Declarations
);
846 micro_add(union tgsi_exec_channel
*dst
,
847 const union tgsi_exec_channel
*src0
,
848 const union tgsi_exec_channel
*src1
)
850 dst
->f
[0] = src0
->f
[0] + src1
->f
[0];
851 dst
->f
[1] = src0
->f
[1] + src1
->f
[1];
852 dst
->f
[2] = src0
->f
[2] + src1
->f
[2];
853 dst
->f
[3] = src0
->f
[3] + src1
->f
[3];
858 union tgsi_exec_channel
*dst
,
859 const union tgsi_exec_channel
*src0
,
860 const union tgsi_exec_channel
*src1
)
862 if (src1
->f
[0] != 0) {
863 dst
->f
[0] = src0
->f
[0] / src1
->f
[0];
865 if (src1
->f
[1] != 0) {
866 dst
->f
[1] = src0
->f
[1] / src1
->f
[1];
868 if (src1
->f
[2] != 0) {
869 dst
->f
[2] = src0
->f
[2] / src1
->f
[2];
871 if (src1
->f
[3] != 0) {
872 dst
->f
[3] = src0
->f
[3] / src1
->f
[3];
877 micro_rcc(union tgsi_exec_channel
*dst
,
878 const union tgsi_exec_channel
*src
)
882 for (i
= 0; i
< 4; i
++) {
883 float recip
= 1.0f
/ src
->f
[i
];
886 if (recip
> 1.884467e+019f
) {
887 dst
->f
[i
] = 1.884467e+019f
;
889 else if (recip
< 5.42101e-020f
) {
890 dst
->f
[i
] = 5.42101e-020f
;
897 if (recip
< -1.884467e+019f
) {
898 dst
->f
[i
] = -1.884467e+019f
;
900 else if (recip
> -5.42101e-020f
) {
901 dst
->f
[i
] = -5.42101e-020f
;
912 union tgsi_exec_channel
*dst
,
913 const union tgsi_exec_channel
*src0
,
914 const union tgsi_exec_channel
*src1
,
915 const union tgsi_exec_channel
*src2
,
916 const union tgsi_exec_channel
*src3
)
918 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src2
->f
[0] : src3
->f
[0];
919 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src2
->f
[1] : src3
->f
[1];
920 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src2
->f
[2] : src3
->f
[2];
921 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src2
->f
[3] : src3
->f
[3];
925 micro_max(union tgsi_exec_channel
*dst
,
926 const union tgsi_exec_channel
*src0
,
927 const union tgsi_exec_channel
*src1
)
929 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
930 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
931 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
932 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
936 micro_min(union tgsi_exec_channel
*dst
,
937 const union tgsi_exec_channel
*src0
,
938 const union tgsi_exec_channel
*src1
)
940 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
941 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
942 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
943 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
947 micro_mul(union tgsi_exec_channel
*dst
,
948 const union tgsi_exec_channel
*src0
,
949 const union tgsi_exec_channel
*src1
)
951 dst
->f
[0] = src0
->f
[0] * src1
->f
[0];
952 dst
->f
[1] = src0
->f
[1] * src1
->f
[1];
953 dst
->f
[2] = src0
->f
[2] * src1
->f
[2];
954 dst
->f
[3] = src0
->f
[3] * src1
->f
[3];
959 union tgsi_exec_channel
*dst
,
960 const union tgsi_exec_channel
*src
)
962 dst
->f
[0] = -src
->f
[0];
963 dst
->f
[1] = -src
->f
[1];
964 dst
->f
[2] = -src
->f
[2];
965 dst
->f
[3] = -src
->f
[3];
970 union tgsi_exec_channel
*dst
,
971 const union tgsi_exec_channel
*src0
,
972 const union tgsi_exec_channel
*src1
)
975 dst
->f
[0] = util_fast_pow( src0
->f
[0], src1
->f
[0] );
976 dst
->f
[1] = util_fast_pow( src0
->f
[1], src1
->f
[1] );
977 dst
->f
[2] = util_fast_pow( src0
->f
[2], src1
->f
[2] );
978 dst
->f
[3] = util_fast_pow( src0
->f
[3], src1
->f
[3] );
980 dst
->f
[0] = powf( src0
->f
[0], src1
->f
[0] );
981 dst
->f
[1] = powf( src0
->f
[1], src1
->f
[1] );
982 dst
->f
[2] = powf( src0
->f
[2], src1
->f
[2] );
983 dst
->f
[3] = powf( src0
->f
[3], src1
->f
[3] );
988 micro_sub(union tgsi_exec_channel
*dst
,
989 const union tgsi_exec_channel
*src0
,
990 const union tgsi_exec_channel
*src1
)
992 dst
->f
[0] = src0
->f
[0] - src1
->f
[0];
993 dst
->f
[1] = src0
->f
[1] - src1
->f
[1];
994 dst
->f
[2] = src0
->f
[2] - src1
->f
[2];
995 dst
->f
[3] = src0
->f
[3] - src1
->f
[3];
999 fetch_src_file_channel(const struct tgsi_exec_machine
*mach
,
1002 const union tgsi_exec_channel
*index
,
1003 const union tgsi_exec_channel
*index2D
,
1004 union tgsi_exec_channel
*chan
)
1008 assert(swizzle
< 4);
1011 case TGSI_FILE_CONSTANT
:
1012 for (i
= 0; i
< QUAD_SIZE
; i
++) {
1013 assert(index2D
->i
[i
] >= 0 && index2D
->i
[i
] < PIPE_MAX_CONSTANT_BUFFERS
);
1014 assert(mach
->Consts
[index2D
->i
[i
]]);
1016 if (index
->i
[i
] < 0) {
1019 /* NOTE: copying the const value as a uint instead of float */
1020 const uint constbuf
= index2D
->i
[i
];
1021 const uint
*buf
= (const uint
*)mach
->Consts
[constbuf
];
1022 const int pos
= index
->i
[i
] * 4 + swizzle
;
1023 /* const buffer bounds check */
1024 if (pos
< 0 || pos
>= mach
->ConstsSize
[constbuf
]) {
1026 /* Debug: print warning */
1027 static int count
= 0;
1029 debug_printf("TGSI Exec: const buffer index %d"
1030 " out of bounds\n", pos
);
1035 chan
->u
[i
] = buf
[pos
];
1040 case TGSI_FILE_INPUT
:
1041 case TGSI_FILE_SYSTEM_VALUE
:
1042 for (i
= 0; i
< QUAD_SIZE
; i
++) {
1044 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1045 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1046 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1047 index2D->i[i], index->i[i]);
1049 int pos
= index2D
->i
[i
] * TGSI_EXEC_MAX_INPUT_ATTRIBS
+ index
->i
[i
];
1051 assert(pos
< Elements(mach
->Inputs
));
1052 chan
->u
[i
] = mach
->Inputs
[pos
].xyzw
[swizzle
].u
[i
];
1056 case TGSI_FILE_TEMPORARY
:
1057 for (i
= 0; i
< QUAD_SIZE
; i
++) {
1058 assert(index
->i
[i
] < TGSI_EXEC_NUM_TEMPS
);
1059 assert(index2D
->i
[i
] == 0);
1061 chan
->u
[i
] = mach
->Temps
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1065 case TGSI_FILE_TEMPORARY_ARRAY
:
1066 for (i
= 0; i
< QUAD_SIZE
; i
++) {
1067 assert(index
->i
[i
] < TGSI_EXEC_NUM_TEMPS
);
1068 assert(index2D
->i
[i
] < TGSI_EXEC_NUM_TEMP_ARRAYS
);
1071 mach
->TempArray
[index2D
->i
[i
]][index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1075 case TGSI_FILE_IMMEDIATE
:
1076 for (i
= 0; i
< QUAD_SIZE
; i
++) {
1077 assert(index
->i
[i
] >= 0 && index
->i
[i
] < (int)mach
->ImmLimit
);
1078 assert(index2D
->i
[i
] == 0);
1080 chan
->f
[i
] = mach
->Imms
[index
->i
[i
]][swizzle
];
1084 case TGSI_FILE_IMMEDIATE_ARRAY
:
1085 for (i
= 0; i
< QUAD_SIZE
; i
++) {
1086 assert(index2D
->i
[i
] == 0);
1088 chan
->f
[i
] = mach
->ImmArray
[index
->i
[i
]][swizzle
];
1092 case TGSI_FILE_ADDRESS
:
1093 for (i
= 0; i
< QUAD_SIZE
; i
++) {
1094 assert(index
->i
[i
] >= 0);
1095 assert(index2D
->i
[i
] == 0);
1097 chan
->u
[i
] = mach
->Addrs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1101 case TGSI_FILE_PREDICATE
:
1102 for (i
= 0; i
< QUAD_SIZE
; i
++) {
1103 assert(index
->i
[i
] >= 0 && index
->i
[i
] < TGSI_EXEC_NUM_PREDS
);
1104 assert(index2D
->i
[i
] == 0);
1106 chan
->u
[i
] = mach
->Predicates
[0].xyzw
[swizzle
].u
[i
];
1110 case TGSI_FILE_OUTPUT
:
1111 /* vertex/fragment output vars can be read too */
1112 for (i
= 0; i
< QUAD_SIZE
; i
++) {
1113 assert(index
->i
[i
] >= 0);
1114 assert(index2D
->i
[i
] == 0);
1116 chan
->u
[i
] = mach
->Outputs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1122 for (i
= 0; i
< QUAD_SIZE
; i
++) {
1129 fetch_source(const struct tgsi_exec_machine
*mach
,
1130 union tgsi_exec_channel
*chan
,
1131 const struct tgsi_full_src_register
*reg
,
1132 const uint chan_index
,
1133 enum tgsi_exec_datatype src_datatype
)
1135 union tgsi_exec_channel index
;
1136 union tgsi_exec_channel index2D
;
1139 /* We start with a direct index into a register file.
1143 * file = Register.File
1144 * [1] = Register.Index
1149 index
.i
[3] = reg
->Register
.Index
;
1151 /* There is an extra source register that indirectly subscripts
1152 * a register file. The direct index now becomes an offset
1153 * that is being added to the indirect register.
1157 * ind = Indirect.File
1158 * [2] = Indirect.Index
1159 * .x = Indirect.SwizzleX
1161 if (reg
->Register
.Indirect
) {
1162 union tgsi_exec_channel index2
;
1163 union tgsi_exec_channel indir_index
;
1164 const uint execmask
= mach
->ExecMask
;
1167 /* which address register (always zero now) */
1171 index2
.i
[3] = reg
->Indirect
.Index
;
1172 assert(reg
->Indirect
.File
== TGSI_FILE_ADDRESS
);
1173 /* get current value of address register[swizzle] */
1174 swizzle
= tgsi_util_get_src_register_swizzle( ®
->Indirect
, CHAN_X
);
1175 fetch_src_file_channel(mach
,
1182 /* add value of address register to the offset */
1183 index
.i
[0] += indir_index
.i
[0];
1184 index
.i
[1] += indir_index
.i
[1];
1185 index
.i
[2] += indir_index
.i
[2];
1186 index
.i
[3] += indir_index
.i
[3];
1188 /* for disabled execution channels, zero-out the index to
1189 * avoid using a potential garbage value.
1191 for (i
= 0; i
< QUAD_SIZE
; i
++) {
1192 if ((execmask
& (1 << i
)) == 0)
1197 /* There is an extra source register that is a second
1198 * subscript to a register file. Effectively it means that
1199 * the register file is actually a 2D array of registers.
1203 * [3] = Dimension.Index
1205 if (reg
->Register
.Dimension
) {
1209 index2D
.i
[3] = reg
->Dimension
.Index
;
1211 /* Again, the second subscript index can be addressed indirectly
1212 * identically to the first one.
1213 * Nothing stops us from indirectly addressing the indirect register,
1214 * but there is no need for that, so we won't exercise it.
1216 * file[ind[4].y+3][1],
1218 * ind = DimIndirect.File
1219 * [4] = DimIndirect.Index
1220 * .y = DimIndirect.SwizzleX
1222 if (reg
->Dimension
.Indirect
) {
1223 union tgsi_exec_channel index2
;
1224 union tgsi_exec_channel indir_index
;
1225 const uint execmask
= mach
->ExecMask
;
1231 index2
.i
[3] = reg
->DimIndirect
.Index
;
1233 swizzle
= tgsi_util_get_src_register_swizzle( ®
->DimIndirect
, CHAN_X
);
1234 fetch_src_file_channel(mach
,
1235 reg
->DimIndirect
.File
,
1241 index2D
.i
[0] += indir_index
.i
[0];
1242 index2D
.i
[1] += indir_index
.i
[1];
1243 index2D
.i
[2] += indir_index
.i
[2];
1244 index2D
.i
[3] += indir_index
.i
[3];
1246 /* for disabled execution channels, zero-out the index to
1247 * avoid using a potential garbage value.
1249 for (i
= 0; i
< QUAD_SIZE
; i
++) {
1250 if ((execmask
& (1 << i
)) == 0) {
1256 /* If by any chance there was a need for a 3D array of register
1257 * files, we would have to check whether Dimension is followed
1258 * by a dimension register and continue the saga.
1267 swizzle
= tgsi_util_get_full_src_register_swizzle( reg
, chan_index
);
1268 fetch_src_file_channel(mach
,
1275 if (reg
->Register
.Absolute
) {
1276 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1277 micro_abs(chan
, chan
);
1279 micro_iabs(chan
, chan
);
1283 if (reg
->Register
.Negate
) {
1284 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1285 micro_neg(chan
, chan
);
1287 micro_ineg(chan
, chan
);
1293 store_dest(struct tgsi_exec_machine
*mach
,
1294 const union tgsi_exec_channel
*chan
,
1295 const struct tgsi_full_dst_register
*reg
,
1296 const struct tgsi_full_instruction
*inst
,
1298 enum tgsi_exec_datatype dst_datatype
)
1301 union tgsi_exec_channel null
;
1302 union tgsi_exec_channel
*dst
;
1303 union tgsi_exec_channel index2D
;
1304 uint execmask
= mach
->ExecMask
;
1305 int offset
= 0; /* indirection offset */
1309 if (0 && dst_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1310 check_inf_or_nan(chan
);
1313 /* There is an extra source register that indirectly subscripts
1314 * a register file. The direct index now becomes an offset
1315 * that is being added to the indirect register.
1319 * ind = Indirect.File
1320 * [2] = Indirect.Index
1321 * .x = Indirect.SwizzleX
1323 if (reg
->Register
.Indirect
) {
1324 union tgsi_exec_channel index
;
1325 union tgsi_exec_channel indir_index
;
1328 /* which address register (always zero for now) */
1332 index
.i
[3] = reg
->Indirect
.Index
;
1334 /* get current value of address register[swizzle] */
1335 swizzle
= tgsi_util_get_src_register_swizzle( ®
->Indirect
, CHAN_X
);
1337 /* fetch values from the address/indirection register */
1338 fetch_src_file_channel(mach
,
1345 /* save indirection offset */
1346 offset
= indir_index
.i
[0];
1349 /* There is an extra source register that is a second
1350 * subscript to a register file. Effectively it means that
1351 * the register file is actually a 2D array of registers.
1355 * [3] = Dimension.Index
1357 if (reg
->Register
.Dimension
) {
1361 index2D
.i
[3] = reg
->Dimension
.Index
;
1363 /* Again, the second subscript index can be addressed indirectly
1364 * identically to the first one.
1365 * Nothing stops us from indirectly addressing the indirect register,
1366 * but there is no need for that, so we won't exercise it.
1368 * file[ind[4].y+3][1],
1370 * ind = DimIndirect.File
1371 * [4] = DimIndirect.Index
1372 * .y = DimIndirect.SwizzleX
1374 if (reg
->Dimension
.Indirect
) {
1375 union tgsi_exec_channel index2
;
1376 union tgsi_exec_channel indir_index
;
1377 const uint execmask
= mach
->ExecMask
;
1384 index2
.i
[3] = reg
->DimIndirect
.Index
;
1386 swizzle
= tgsi_util_get_src_register_swizzle( ®
->DimIndirect
, CHAN_X
);
1387 fetch_src_file_channel(mach
,
1388 reg
->DimIndirect
.File
,
1394 index2D
.i
[0] += indir_index
.i
[0];
1395 index2D
.i
[1] += indir_index
.i
[1];
1396 index2D
.i
[2] += indir_index
.i
[2];
1397 index2D
.i
[3] += indir_index
.i
[3];
1399 /* for disabled execution channels, zero-out the index to
1400 * avoid using a potential garbage value.
1402 for (i
= 0; i
< QUAD_SIZE
; i
++) {
1403 if ((execmask
& (1 << i
)) == 0) {
1409 /* If by any chance there was a need for a 3D array of register
1410 * files, we would have to check whether Dimension is followed
1411 * by a dimension register and continue the saga.
1420 switch (reg
->Register
.File
) {
1421 case TGSI_FILE_NULL
:
1425 case TGSI_FILE_OUTPUT
:
1426 index
= mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0]
1427 + reg
->Register
.Index
;
1428 dst
= &mach
->Outputs
[offset
+ index
].xyzw
[chan_index
];
1430 if (TGSI_PROCESSOR_GEOMETRY
== mach
->Processor
) {
1431 fprintf(stderr
, "STORING OUT[%d] mask(%d), = (", offset
+ index
, execmask
);
1432 for (i
= 0; i
< QUAD_SIZE
; i
++)
1433 if (execmask
& (1 << i
))
1434 fprintf(stderr
, "%f, ", chan
->f
[i
]);
1435 fprintf(stderr
, ")\n");
1440 case TGSI_FILE_TEMPORARY
:
1441 index
= reg
->Register
.Index
;
1442 assert( index
< TGSI_EXEC_NUM_TEMPS
);
1443 dst
= &mach
->Temps
[offset
+ index
].xyzw
[chan_index
];
1446 case TGSI_FILE_TEMPORARY_ARRAY
:
1447 index
= reg
->Register
.Index
;
1448 assert( index
< TGSI_EXEC_NUM_TEMPS
);
1449 assert( index2D
.i
[0] < TGSI_EXEC_NUM_TEMP_ARRAYS
);
1450 /* XXX we use index2D.i[0] here but somehow we might
1451 * end up with someone trying to store indirectly in
1452 * different buffers */
1453 dst
= &mach
->TempArray
[index2D
.i
[0]][offset
+ index
].xyzw
[chan_index
];
1456 case TGSI_FILE_ADDRESS
:
1457 index
= reg
->Register
.Index
;
1458 dst
= &mach
->Addrs
[index
].xyzw
[chan_index
];
1461 case TGSI_FILE_PREDICATE
:
1462 index
= reg
->Register
.Index
;
1463 assert(index
< TGSI_EXEC_NUM_PREDS
);
1464 dst
= &mach
->Predicates
[index
].xyzw
[chan_index
];
1472 if (inst
->Instruction
.Predicate
) {
1474 union tgsi_exec_channel
*pred
;
1476 switch (chan_index
) {
1478 swizzle
= inst
->Predicate
.SwizzleX
;
1481 swizzle
= inst
->Predicate
.SwizzleY
;
1484 swizzle
= inst
->Predicate
.SwizzleZ
;
1487 swizzle
= inst
->Predicate
.SwizzleW
;
1494 assert(inst
->Predicate
.Index
== 0);
1496 pred
= &mach
->Predicates
[inst
->Predicate
.Index
].xyzw
[swizzle
];
1498 if (inst
->Predicate
.Negate
) {
1499 for (i
= 0; i
< QUAD_SIZE
; i
++) {
1501 execmask
&= ~(1 << i
);
1505 for (i
= 0; i
< QUAD_SIZE
; i
++) {
1507 execmask
&= ~(1 << i
);
1513 switch (inst
->Instruction
.Saturate
) {
1515 for (i
= 0; i
< QUAD_SIZE
; i
++)
1516 if (execmask
& (1 << i
))
1517 dst
->i
[i
] = chan
->i
[i
];
1520 case TGSI_SAT_ZERO_ONE
:
1521 for (i
= 0; i
< QUAD_SIZE
; i
++)
1522 if (execmask
& (1 << i
)) {
1523 if (chan
->f
[i
] < 0.0f
)
1525 else if (chan
->f
[i
] > 1.0f
)
1528 dst
->i
[i
] = chan
->i
[i
];
1532 case TGSI_SAT_MINUS_PLUS_ONE
:
1533 for (i
= 0; i
< QUAD_SIZE
; i
++)
1534 if (execmask
& (1 << i
)) {
1535 if (chan
->f
[i
] < -1.0f
)
1537 else if (chan
->f
[i
] > 1.0f
)
1540 dst
->i
[i
] = chan
->i
[i
];
1549 #define FETCH(VAL,INDEX,CHAN)\
1550 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1554 * Execute ARB-style KIL which is predicated by a src register.
1555 * Kill fragment if any of the four values is less than zero.
1558 exec_kil(struct tgsi_exec_machine
*mach
,
1559 const struct tgsi_full_instruction
*inst
)
1563 uint kilmask
= 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1564 union tgsi_exec_channel r
[1];
1566 /* This mask stores component bits that were already tested. */
1569 for (chan_index
= 0; chan_index
< 4; chan_index
++)
1574 /* unswizzle channel */
1575 swizzle
= tgsi_util_get_full_src_register_swizzle (
1579 /* check if the component has not been already tested */
1580 if (uniquemask
& (1 << swizzle
))
1582 uniquemask
|= 1 << swizzle
;
1584 FETCH(&r
[0], 0, chan_index
);
1585 for (i
= 0; i
< 4; i
++)
1586 if (r
[0].f
[i
] < 0.0f
)
1590 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
1594 * Execute NVIDIA-style KIL which is predicated by a condition code.
1595 * Kill fragment if the condition code is TRUE.
1598 exec_kilp(struct tgsi_exec_machine
*mach
,
1599 const struct tgsi_full_instruction
*inst
)
1601 uint kilmask
; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1603 /* "unconditional" kil */
1604 kilmask
= mach
->ExecMask
;
1605 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
1609 emit_vertex(struct tgsi_exec_machine
*mach
)
1611 /* FIXME: check for exec mask correctly
1613 for (i = 0; i < QUAD_SIZE; ++i) {
1614 if ((mach->ExecMask & (1 << i)))
1616 if (mach
->ExecMask
) {
1617 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] += mach
->NumOutputs
;
1618 mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]]++;
1623 emit_primitive(struct tgsi_exec_machine
*mach
)
1625 unsigned *prim_count
= &mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0];
1626 /* FIXME: check for exec mask correctly
1628 for (i = 0; i < QUAD_SIZE; ++i) {
1629 if ((mach->ExecMask & (1 << i)))
1631 if (mach
->ExecMask
) {
1633 debug_assert((*prim_count
* mach
->NumOutputs
) < mach
->MaxGeometryShaderOutputs
);
1634 mach
->Primitives
[*prim_count
] = 0;
1639 conditional_emit_primitive(struct tgsi_exec_machine
*mach
)
1641 if (TGSI_PROCESSOR_GEOMETRY
== mach
->Processor
) {
1643 mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]];
1644 if (emitted_verts
) {
1645 emit_primitive(mach
);
1652 * Fetch four texture samples using STR texture coordinates.
1655 fetch_texel( struct tgsi_sampler
*sampler
,
1656 const union tgsi_exec_channel
*s
,
1657 const union tgsi_exec_channel
*t
,
1658 const union tgsi_exec_channel
*p
,
1659 const union tgsi_exec_channel
*c0
,
1660 enum tgsi_sampler_control control
,
1661 union tgsi_exec_channel
*r
,
1662 union tgsi_exec_channel
*g
,
1663 union tgsi_exec_channel
*b
,
1664 union tgsi_exec_channel
*a
)
1667 float rgba
[NUM_CHANNELS
][QUAD_SIZE
];
1669 sampler
->get_samples(sampler
, s
->f
, t
->f
, p
->f
, c0
->f
, control
, rgba
);
1671 for (j
= 0; j
< 4; j
++) {
1672 r
->f
[j
] = rgba
[0][j
];
1673 g
->f
[j
] = rgba
[1][j
];
1674 b
->f
[j
] = rgba
[2][j
];
1675 a
->f
[j
] = rgba
[3][j
];
1680 #define TEX_MODIFIER_NONE 0
1681 #define TEX_MODIFIER_PROJECTED 1
1682 #define TEX_MODIFIER_LOD_BIAS 2
1683 #define TEX_MODIFIER_EXPLICIT_LOD 3
1687 exec_tex(struct tgsi_exec_machine
*mach
,
1688 const struct tgsi_full_instruction
*inst
,
1691 const uint unit
= inst
->Src
[1].Register
.Index
;
1692 union tgsi_exec_channel r
[4];
1693 const union tgsi_exec_channel
*lod
= &ZeroVec
;
1694 enum tgsi_sampler_control control
;
1697 if (modifier
!= TEX_MODIFIER_NONE
) {
1698 FETCH(&r
[3], 0, CHAN_W
);
1699 if (modifier
!= TEX_MODIFIER_PROJECTED
) {
1704 if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
) {
1705 control
= tgsi_sampler_lod_explicit
;
1707 control
= tgsi_sampler_lod_bias
;
1710 switch (inst
->Texture
.Texture
) {
1711 case TGSI_TEXTURE_1D
:
1712 case TGSI_TEXTURE_SHADOW1D
:
1713 FETCH(&r
[0], 0, CHAN_X
);
1715 if (modifier
== TEX_MODIFIER_PROJECTED
) {
1716 micro_div(&r
[0], &r
[0], &r
[3]);
1719 fetch_texel(mach
->Samplers
[unit
],
1720 &r
[0], &ZeroVec
, &ZeroVec
, lod
, /* S, T, P, LOD */
1722 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
1725 case TGSI_TEXTURE_2D
:
1726 case TGSI_TEXTURE_RECT
:
1727 case TGSI_TEXTURE_SHADOW2D
:
1728 case TGSI_TEXTURE_SHADOWRECT
:
1729 FETCH(&r
[0], 0, CHAN_X
);
1730 FETCH(&r
[1], 0, CHAN_Y
);
1731 FETCH(&r
[2], 0, CHAN_Z
);
1733 if (modifier
== TEX_MODIFIER_PROJECTED
) {
1734 micro_div(&r
[0], &r
[0], &r
[3]);
1735 micro_div(&r
[1], &r
[1], &r
[3]);
1736 micro_div(&r
[2], &r
[2], &r
[3]);
1739 fetch_texel(mach
->Samplers
[unit
],
1740 &r
[0], &r
[1], &r
[2], lod
, /* S, T, P, LOD */
1742 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
1745 case TGSI_TEXTURE_3D
:
1746 case TGSI_TEXTURE_CUBE
:
1747 FETCH(&r
[0], 0, CHAN_X
);
1748 FETCH(&r
[1], 0, CHAN_Y
);
1749 FETCH(&r
[2], 0, CHAN_Z
);
1751 if (modifier
== TEX_MODIFIER_PROJECTED
) {
1752 micro_div(&r
[0], &r
[0], &r
[3]);
1753 micro_div(&r
[1], &r
[1], &r
[3]);
1754 micro_div(&r
[2], &r
[2], &r
[3]);
1757 fetch_texel(mach
->Samplers
[unit
],
1758 &r
[0], &r
[1], &r
[2], lod
,
1760 &r
[0], &r
[1], &r
[2], &r
[3]);
1767 for (chan
= 0; chan
< NUM_CHANNELS
; chan
++) {
1768 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
1769 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
1775 exec_txd(struct tgsi_exec_machine
*mach
,
1776 const struct tgsi_full_instruction
*inst
)
1778 const uint unit
= inst
->Src
[3].Register
.Index
;
1779 union tgsi_exec_channel r
[4];
1783 * XXX: This is fake TXD -- the derivatives are not taken into account, yet.
1786 switch (inst
->Texture
.Texture
) {
1787 case TGSI_TEXTURE_1D
:
1788 case TGSI_TEXTURE_SHADOW1D
:
1790 FETCH(&r
[0], 0, CHAN_X
);
1792 fetch_texel(mach
->Samplers
[unit
],
1793 &r
[0], &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, BIAS */
1794 tgsi_sampler_lod_bias
,
1795 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
1798 case TGSI_TEXTURE_2D
:
1799 case TGSI_TEXTURE_RECT
:
1800 case TGSI_TEXTURE_SHADOW2D
:
1801 case TGSI_TEXTURE_SHADOWRECT
:
1803 FETCH(&r
[0], 0, CHAN_X
);
1804 FETCH(&r
[1], 0, CHAN_Y
);
1805 FETCH(&r
[2], 0, CHAN_Z
);
1807 fetch_texel(mach
->Samplers
[unit
],
1808 &r
[0], &r
[1], &r
[2], &ZeroVec
, /* inputs */
1809 tgsi_sampler_lod_bias
,
1810 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
1813 case TGSI_TEXTURE_3D
:
1814 case TGSI_TEXTURE_CUBE
:
1816 FETCH(&r
[0], 0, CHAN_X
);
1817 FETCH(&r
[1], 0, CHAN_Y
);
1818 FETCH(&r
[2], 0, CHAN_Z
);
1820 fetch_texel(mach
->Samplers
[unit
],
1821 &r
[0], &r
[1], &r
[2], &ZeroVec
,
1822 tgsi_sampler_lod_bias
,
1823 &r
[0], &r
[1], &r
[2], &r
[3]);
1830 for (chan
= 0; chan
< NUM_CHANNELS
; chan
++) {
1831 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
1832 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
1839 * Evaluate a constant-valued coefficient at the position of the
1844 struct tgsi_exec_machine
*mach
,
1850 for( i
= 0; i
< QUAD_SIZE
; i
++ ) {
1851 mach
->Inputs
[attrib
].xyzw
[chan
].f
[i
] = mach
->InterpCoefs
[attrib
].a0
[chan
];
1856 * Evaluate a linear-valued coefficient at the position of the
1861 struct tgsi_exec_machine
*mach
,
1865 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
1866 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
1867 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
1868 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
1869 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
1870 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
;
1871 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = a0
+ dadx
;
1872 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = a0
+ dady
;
1873 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = a0
+ dadx
+ dady
;
1877 * Evaluate a perspective-valued coefficient at the position of the
1881 eval_perspective_coef(
1882 struct tgsi_exec_machine
*mach
,
1886 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
1887 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
1888 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
1889 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
1890 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
1891 const float *w
= mach
->QuadPos
.xyzw
[3].f
;
1892 /* divide by W here */
1893 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
/ w
[0];
1894 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = (a0
+ dadx
) / w
[1];
1895 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = (a0
+ dady
) / w
[2];
1896 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = (a0
+ dadx
+ dady
) / w
[3];
1900 typedef void (* eval_coef_func
)(
1901 struct tgsi_exec_machine
*mach
,
1906 exec_declaration(struct tgsi_exec_machine
*mach
,
1907 const struct tgsi_full_declaration
*decl
)
1909 if (mach
->Processor
== TGSI_PROCESSOR_FRAGMENT
) {
1910 if (decl
->Declaration
.File
== TGSI_FILE_INPUT
||
1911 decl
->Declaration
.File
== TGSI_FILE_SYSTEM_VALUE
) {
1912 uint first
, last
, mask
;
1914 first
= decl
->Range
.First
;
1915 last
= decl
->Range
.Last
;
1916 mask
= decl
->Declaration
.UsageMask
;
1918 /* XXX we could remove this special-case code since
1919 * mach->InterpCoefs[first].a0 should already have the
1920 * front/back-face value. But we should first update the
1921 * ureg code to emit the right UsageMask value (WRITEMASK_X).
1922 * Then, we could remove the tgsi_exec_machine::Face field.
1924 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_FACE
) {
1927 assert(decl
->Semantic
.Index
== 0);
1928 assert(first
== last
);
1930 for (i
= 0; i
< QUAD_SIZE
; i
++) {
1931 mach
->Inputs
[first
].xyzw
[0].f
[i
] = mach
->Face
;
1934 eval_coef_func eval
;
1937 switch (decl
->Declaration
.Interpolate
) {
1938 case TGSI_INTERPOLATE_CONSTANT
:
1939 eval
= eval_constant_coef
;
1942 case TGSI_INTERPOLATE_LINEAR
:
1943 eval
= eval_linear_coef
;
1946 case TGSI_INTERPOLATE_PERSPECTIVE
:
1947 eval
= eval_perspective_coef
;
1955 for (j
= 0; j
< NUM_CHANNELS
; j
++) {
1956 if (mask
& (1 << j
)) {
1957 for (i
= first
; i
<= last
; i
++) {
1967 typedef void (* micro_op
)(union tgsi_exec_channel
*dst
);
1970 exec_vector(struct tgsi_exec_machine
*mach
,
1971 const struct tgsi_full_instruction
*inst
,
1973 enum tgsi_exec_datatype dst_datatype
)
1977 for (chan
= 0; chan
< NUM_CHANNELS
; chan
++) {
1978 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
1979 union tgsi_exec_channel dst
;
1982 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
1987 typedef void (* micro_unary_op
)(union tgsi_exec_channel
*dst
,
1988 const union tgsi_exec_channel
*src
);
1991 exec_scalar_unary(struct tgsi_exec_machine
*mach
,
1992 const struct tgsi_full_instruction
*inst
,
1994 enum tgsi_exec_datatype dst_datatype
,
1995 enum tgsi_exec_datatype src_datatype
)
1998 union tgsi_exec_channel src
;
1999 union tgsi_exec_channel dst
;
2001 fetch_source(mach
, &src
, &inst
->Src
[0], CHAN_X
, src_datatype
);
2003 for (chan
= 0; chan
< NUM_CHANNELS
; chan
++) {
2004 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2005 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2011 exec_vector_unary(struct tgsi_exec_machine
*mach
,
2012 const struct tgsi_full_instruction
*inst
,
2014 enum tgsi_exec_datatype dst_datatype
,
2015 enum tgsi_exec_datatype src_datatype
)
2018 struct tgsi_exec_vector dst
;
2020 for (chan
= 0; chan
< NUM_CHANNELS
; chan
++) {
2021 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2022 union tgsi_exec_channel src
;
2024 fetch_source(mach
, &src
, &inst
->Src
[0], chan
, src_datatype
);
2025 op(&dst
.xyzw
[chan
], &src
);
2028 for (chan
= 0; chan
< NUM_CHANNELS
; chan
++) {
2029 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2030 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2035 typedef void (* micro_binary_op
)(union tgsi_exec_channel
*dst
,
2036 const union tgsi_exec_channel
*src0
,
2037 const union tgsi_exec_channel
*src1
);
2040 exec_scalar_binary(struct tgsi_exec_machine
*mach
,
2041 const struct tgsi_full_instruction
*inst
,
2043 enum tgsi_exec_datatype dst_datatype
,
2044 enum tgsi_exec_datatype src_datatype
)
2047 union tgsi_exec_channel src
[2];
2048 union tgsi_exec_channel dst
;
2050 fetch_source(mach
, &src
[0], &inst
->Src
[0], CHAN_X
, src_datatype
);
2051 fetch_source(mach
, &src
[1], &inst
->Src
[1], CHAN_Y
, src_datatype
);
2052 op(&dst
, &src
[0], &src
[1]);
2053 for (chan
= 0; chan
< NUM_CHANNELS
; chan
++) {
2054 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2055 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2061 exec_vector_binary(struct tgsi_exec_machine
*mach
,
2062 const struct tgsi_full_instruction
*inst
,
2064 enum tgsi_exec_datatype dst_datatype
,
2065 enum tgsi_exec_datatype src_datatype
)
2068 struct tgsi_exec_vector dst
;
2070 for (chan
= 0; chan
< NUM_CHANNELS
; chan
++) {
2071 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2072 union tgsi_exec_channel src
[2];
2074 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
2075 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
2076 op(&dst
.xyzw
[chan
], &src
[0], &src
[1]);
2079 for (chan
= 0; chan
< NUM_CHANNELS
; chan
++) {
2080 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2081 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2086 typedef void (* micro_trinary_op
)(union tgsi_exec_channel
*dst
,
2087 const union tgsi_exec_channel
*src0
,
2088 const union tgsi_exec_channel
*src1
,
2089 const union tgsi_exec_channel
*src2
);
2092 exec_vector_trinary(struct tgsi_exec_machine
*mach
,
2093 const struct tgsi_full_instruction
*inst
,
2094 micro_trinary_op op
,
2095 enum tgsi_exec_datatype dst_datatype
,
2096 enum tgsi_exec_datatype src_datatype
)
2099 struct tgsi_exec_vector dst
;
2101 for (chan
= 0; chan
< NUM_CHANNELS
; chan
++) {
2102 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2103 union tgsi_exec_channel src
[3];
2105 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
2106 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
2107 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
, src_datatype
);
2108 op(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2]);
2111 for (chan
= 0; chan
< NUM_CHANNELS
; chan
++) {
2112 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2113 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
2119 exec_dp3(struct tgsi_exec_machine
*mach
,
2120 const struct tgsi_full_instruction
*inst
)
2123 union tgsi_exec_channel arg
[3];
2125 fetch_source(mach
, &arg
[0], &inst
->Src
[0], CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2126 fetch_source(mach
, &arg
[1], &inst
->Src
[1], CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2127 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
2129 for (chan
= CHAN_Y
; chan
<= CHAN_Z
; chan
++) {
2130 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
2131 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
2132 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
2135 for (chan
= 0; chan
< NUM_CHANNELS
; chan
++) {
2136 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2137 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2143 exec_dp4(struct tgsi_exec_machine
*mach
,
2144 const struct tgsi_full_instruction
*inst
)
2147 union tgsi_exec_channel arg
[3];
2149 fetch_source(mach
, &arg
[0], &inst
->Src
[0], CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2150 fetch_source(mach
, &arg
[1], &inst
->Src
[1], CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2151 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
2153 for (chan
= CHAN_Y
; chan
<= CHAN_W
; chan
++) {
2154 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
2155 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
2156 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
2159 for (chan
= 0; chan
< NUM_CHANNELS
; chan
++) {
2160 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2161 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2167 exec_dp2a(struct tgsi_exec_machine
*mach
,
2168 const struct tgsi_full_instruction
*inst
)
2171 union tgsi_exec_channel arg
[3];
2173 fetch_source(mach
, &arg
[0], &inst
->Src
[0], CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2174 fetch_source(mach
, &arg
[1], &inst
->Src
[1], CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2175 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
2177 fetch_source(mach
, &arg
[0], &inst
->Src
[0], CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2178 fetch_source(mach
, &arg
[1], &inst
->Src
[1], CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2179 micro_mad(&arg
[0], &arg
[0], &arg
[1], &arg
[2]);
2181 fetch_source(mach
, &arg
[1], &inst
->Src
[2], CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2182 micro_add(&arg
[0], &arg
[0], &arg
[1]);
2184 for (chan
= 0; chan
< NUM_CHANNELS
; chan
++) {
2185 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2186 store_dest(mach
, &arg
[0], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2192 exec_dph(struct tgsi_exec_machine
*mach
,
2193 const struct tgsi_full_instruction
*inst
)
2196 union tgsi_exec_channel arg
[3];
2198 fetch_source(mach
, &arg
[0], &inst
->Src
[0], CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2199 fetch_source(mach
, &arg
[1], &inst
->Src
[1], CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2200 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
2202 fetch_source(mach
, &arg
[0], &inst
->Src
[0], CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2203 fetch_source(mach
, &arg
[1], &inst
->Src
[1], CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2204 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
2206 fetch_source(mach
, &arg
[0], &inst
->Src
[0], CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2207 fetch_source(mach
, &arg
[1], &inst
->Src
[1], CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2208 micro_mad(&arg
[0], &arg
[0], &arg
[1], &arg
[2]);
2210 fetch_source(mach
, &arg
[1], &inst
->Src
[1], CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2211 micro_add(&arg
[0], &arg
[0], &arg
[1]);
2213 for (chan
= 0; chan
< NUM_CHANNELS
; chan
++) {
2214 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2215 store_dest(mach
, &arg
[0], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2221 exec_dp2(struct tgsi_exec_machine
*mach
,
2222 const struct tgsi_full_instruction
*inst
)
2225 union tgsi_exec_channel arg
[3];
2227 fetch_source(mach
, &arg
[0], &inst
->Src
[0], CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2228 fetch_source(mach
, &arg
[1], &inst
->Src
[1], CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2229 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
2231 fetch_source(mach
, &arg
[0], &inst
->Src
[0], CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2232 fetch_source(mach
, &arg
[1], &inst
->Src
[1], CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2233 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
2235 for (chan
= 0; chan
< NUM_CHANNELS
; chan
++) {
2236 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2237 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2243 exec_nrm4(struct tgsi_exec_machine
*mach
,
2244 const struct tgsi_full_instruction
*inst
)
2247 union tgsi_exec_channel arg
[4];
2248 union tgsi_exec_channel scale
;
2250 fetch_source(mach
, &arg
[0], &inst
->Src
[0], CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2251 micro_mul(&scale
, &arg
[0], &arg
[0]);
2253 for (chan
= CHAN_Y
; chan
<= CHAN_W
; chan
++) {
2254 union tgsi_exec_channel product
;
2256 fetch_source(mach
, &arg
[chan
], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
2257 micro_mul(&product
, &arg
[chan
], &arg
[chan
]);
2258 micro_add(&scale
, &scale
, &product
);
2261 micro_rsq(&scale
, &scale
);
2263 for (chan
= CHAN_X
; chan
<= CHAN_W
; chan
++) {
2264 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2265 micro_mul(&arg
[chan
], &arg
[chan
], &scale
);
2266 store_dest(mach
, &arg
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2272 exec_nrm3(struct tgsi_exec_machine
*mach
,
2273 const struct tgsi_full_instruction
*inst
)
2275 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XYZ
) {
2277 union tgsi_exec_channel arg
[3];
2278 union tgsi_exec_channel scale
;
2280 fetch_source(mach
, &arg
[0], &inst
->Src
[0], CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2281 micro_mul(&scale
, &arg
[0], &arg
[0]);
2283 for (chan
= CHAN_Y
; chan
<= CHAN_Z
; chan
++) {
2284 union tgsi_exec_channel product
;
2286 fetch_source(mach
, &arg
[chan
], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
2287 micro_mul(&product
, &arg
[chan
], &arg
[chan
]);
2288 micro_add(&scale
, &scale
, &product
);
2291 micro_rsq(&scale
, &scale
);
2293 for (chan
= CHAN_X
; chan
<= CHAN_Z
; chan
++) {
2294 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2295 micro_mul(&arg
[chan
], &arg
[chan
], &scale
);
2296 store_dest(mach
, &arg
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2301 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2302 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2307 exec_scs(struct tgsi_exec_machine
*mach
,
2308 const struct tgsi_full_instruction
*inst
)
2310 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) {
2311 union tgsi_exec_channel arg
;
2312 union tgsi_exec_channel result
;
2314 fetch_source(mach
, &arg
, &inst
->Src
[0], CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2316 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2317 micro_cos(&result
, &arg
);
2318 store_dest(mach
, &result
, &inst
->Dst
[0], inst
, CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2320 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2321 micro_sin(&result
, &arg
);
2322 store_dest(mach
, &result
, &inst
->Dst
[0], inst
, CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2325 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
2326 store_dest(mach
, &ZeroVec
, &inst
->Dst
[0], inst
, CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2328 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2329 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2334 exec_x2d(struct tgsi_exec_machine
*mach
,
2335 const struct tgsi_full_instruction
*inst
)
2337 union tgsi_exec_channel r
[4];
2338 union tgsi_exec_channel d
[2];
2340 fetch_source(mach
, &r
[0], &inst
->Src
[1], CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2341 fetch_source(mach
, &r
[1], &inst
->Src
[1], CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2342 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XZ
) {
2343 fetch_source(mach
, &r
[2], &inst
->Src
[2], CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2344 micro_mul(&r
[2], &r
[2], &r
[0]);
2345 fetch_source(mach
, &r
[3], &inst
->Src
[2], CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2346 micro_mul(&r
[3], &r
[3], &r
[1]);
2347 micro_add(&r
[2], &r
[2], &r
[3]);
2348 fetch_source(mach
, &r
[3], &inst
->Src
[0], CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2349 micro_add(&d
[0], &r
[2], &r
[3]);
2351 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_YW
) {
2352 fetch_source(mach
, &r
[2], &inst
->Src
[2], CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2353 micro_mul(&r
[2], &r
[2], &r
[0]);
2354 fetch_source(mach
, &r
[3], &inst
->Src
[2], CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2355 micro_mul(&r
[3], &r
[3], &r
[1]);
2356 micro_add(&r
[2], &r
[2], &r
[3]);
2357 fetch_source(mach
, &r
[3], &inst
->Src
[0], CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2358 micro_add(&d
[1], &r
[2], &r
[3]);
2360 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2361 store_dest(mach
, &d
[0], &inst
->Dst
[0], inst
, CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2363 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2364 store_dest(mach
, &d
[1], &inst
->Dst
[0], inst
, CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2366 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
2367 store_dest(mach
, &d
[0], &inst
->Dst
[0], inst
, CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2369 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2370 store_dest(mach
, &d
[1], &inst
->Dst
[0], inst
, CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2375 exec_rfl(struct tgsi_exec_machine
*mach
,
2376 const struct tgsi_full_instruction
*inst
)
2378 union tgsi_exec_channel r
[9];
2380 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XYZ
) {
2381 /* r0 = dp3(src0, src0) */
2382 fetch_source(mach
, &r
[2], &inst
->Src
[0], CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2383 micro_mul(&r
[0], &r
[2], &r
[2]);
2384 fetch_source(mach
, &r
[4], &inst
->Src
[0], CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2385 micro_mul(&r
[8], &r
[4], &r
[4]);
2386 micro_add(&r
[0], &r
[0], &r
[8]);
2387 fetch_source(mach
, &r
[6], &inst
->Src
[0], CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2388 micro_mul(&r
[8], &r
[6], &r
[6]);
2389 micro_add(&r
[0], &r
[0], &r
[8]);
2391 /* r1 = dp3(src0, src1) */
2392 fetch_source(mach
, &r
[3], &inst
->Src
[1], CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2393 micro_mul(&r
[1], &r
[2], &r
[3]);
2394 fetch_source(mach
, &r
[5], &inst
->Src
[1], CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2395 micro_mul(&r
[8], &r
[4], &r
[5]);
2396 micro_add(&r
[1], &r
[1], &r
[8]);
2397 fetch_source(mach
, &r
[7], &inst
->Src
[1], CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2398 micro_mul(&r
[8], &r
[6], &r
[7]);
2399 micro_add(&r
[1], &r
[1], &r
[8]);
2401 /* r1 = 2 * r1 / r0 */
2402 micro_add(&r
[1], &r
[1], &r
[1]);
2403 micro_div(&r
[1], &r
[1], &r
[0]);
2405 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2406 micro_mul(&r
[2], &r
[2], &r
[1]);
2407 micro_sub(&r
[2], &r
[2], &r
[3]);
2408 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2410 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2411 micro_mul(&r
[4], &r
[4], &r
[1]);
2412 micro_sub(&r
[4], &r
[4], &r
[5]);
2413 store_dest(mach
, &r
[4], &inst
->Dst
[0], inst
, CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2415 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
2416 micro_mul(&r
[6], &r
[6], &r
[1]);
2417 micro_sub(&r
[6], &r
[6], &r
[7]);
2418 store_dest(mach
, &r
[6], &inst
->Dst
[0], inst
, CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2421 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2422 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2427 exec_xpd(struct tgsi_exec_machine
*mach
,
2428 const struct tgsi_full_instruction
*inst
)
2430 union tgsi_exec_channel r
[6];
2431 union tgsi_exec_channel d
[3];
2433 fetch_source(mach
, &r
[0], &inst
->Src
[0], CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2434 fetch_source(mach
, &r
[1], &inst
->Src
[1], CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2436 micro_mul(&r
[2], &r
[0], &r
[1]);
2438 fetch_source(mach
, &r
[3], &inst
->Src
[0], CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2439 fetch_source(mach
, &r
[4], &inst
->Src
[1], CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2441 micro_mul(&r
[5], &r
[3], &r
[4] );
2442 micro_sub(&d
[CHAN_X
], &r
[2], &r
[5]);
2444 fetch_source(mach
, &r
[2], &inst
->Src
[1], CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2446 micro_mul(&r
[3], &r
[3], &r
[2]);
2448 fetch_source(mach
, &r
[5], &inst
->Src
[0], CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2450 micro_mul(&r
[1], &r
[1], &r
[5]);
2451 micro_sub(&d
[CHAN_Y
], &r
[3], &r
[1]);
2453 micro_mul(&r
[5], &r
[5], &r
[4]);
2454 micro_mul(&r
[0], &r
[0], &r
[2]);
2455 micro_sub(&d
[CHAN_Z
], &r
[5], &r
[0]);
2457 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2458 store_dest(mach
, &d
[CHAN_X
], &inst
->Dst
[0], inst
, CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2460 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2461 store_dest(mach
, &d
[CHAN_Y
], &inst
->Dst
[0], inst
, CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2463 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
2464 store_dest(mach
, &d
[CHAN_Z
], &inst
->Dst
[0], inst
, CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2466 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2467 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2472 exec_dst(struct tgsi_exec_machine
*mach
,
2473 const struct tgsi_full_instruction
*inst
)
2475 union tgsi_exec_channel r
[2];
2476 union tgsi_exec_channel d
[4];
2478 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2479 fetch_source(mach
, &r
[0], &inst
->Src
[0], CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2480 fetch_source(mach
, &r
[1], &inst
->Src
[1], CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2481 micro_mul(&d
[CHAN_Y
], &r
[0], &r
[1]);
2483 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
2484 fetch_source(mach
, &d
[CHAN_Z
], &inst
->Src
[0], CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2486 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2487 fetch_source(mach
, &d
[CHAN_W
], &inst
->Src
[1], CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2490 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2491 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2493 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2494 store_dest(mach
, &d
[CHAN_Y
], &inst
->Dst
[0], inst
, CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2496 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
2497 store_dest(mach
, &d
[CHAN_Z
], &inst
->Dst
[0], inst
, CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2499 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2500 store_dest(mach
, &d
[CHAN_W
], &inst
->Dst
[0], inst
, CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2505 exec_log(struct tgsi_exec_machine
*mach
,
2506 const struct tgsi_full_instruction
*inst
)
2508 union tgsi_exec_channel r
[3];
2510 fetch_source(mach
, &r
[0], &inst
->Src
[0], CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2511 micro_abs(&r
[2], &r
[0]); /* r2 = abs(r0) */
2512 micro_lg2(&r
[1], &r
[2]); /* r1 = lg2(r2) */
2513 micro_flr(&r
[0], &r
[1]); /* r0 = floor(r1) */
2514 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2515 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2517 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2518 micro_exp2(&r
[0], &r
[0]); /* r0 = 2 ^ r0 */
2519 micro_div(&r
[0], &r
[2], &r
[0]); /* r0 = r2 / r0 */
2520 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2522 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
2523 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2525 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2526 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2531 exec_exp(struct tgsi_exec_machine
*mach
,
2532 const struct tgsi_full_instruction
*inst
)
2534 union tgsi_exec_channel r
[3];
2536 fetch_source(mach
, &r
[0], &inst
->Src
[0], CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2537 micro_flr(&r
[1], &r
[0]); /* r1 = floor(r0) */
2538 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2539 micro_exp2(&r
[2], &r
[1]); /* r2 = 2 ^ r1 */
2540 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2542 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2543 micro_sub(&r
[2], &r
[0], &r
[1]); /* r2 = r0 - r1 */
2544 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2546 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
2547 micro_exp2(&r
[2], &r
[0]); /* r2 = 2 ^ r0 */
2548 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2550 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2551 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2556 exec_lit(struct tgsi_exec_machine
*mach
,
2557 const struct tgsi_full_instruction
*inst
)
2559 union tgsi_exec_channel r
[3];
2560 union tgsi_exec_channel d
[3];
2562 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2563 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2565 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_YZ
) {
2566 fetch_source(mach
, &r
[0], &inst
->Src
[0], CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
2567 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2568 micro_max(&d
[CHAN_Y
], &r
[0], &ZeroVec
);
2569 store_dest(mach
, &d
[CHAN_Y
], &inst
->Dst
[0], inst
, CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2572 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
2573 fetch_source(mach
, &r
[1], &inst
->Src
[0], CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
2574 micro_max(&r
[1], &r
[1], &ZeroVec
);
2576 fetch_source(mach
, &r
[2], &inst
->Src
[0], CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2577 micro_min(&r
[2], &r
[2], &P128Vec
);
2578 micro_max(&r
[2], &r
[2], &M128Vec
);
2579 micro_pow(&r
[1], &r
[1], &r
[2]);
2580 micro_lt(&d
[CHAN_Z
], &ZeroVec
, &r
[0], &r
[1], &ZeroVec
);
2581 store_dest(mach
, &d
[CHAN_Z
], &inst
->Dst
[0], inst
, CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
2584 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2585 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
2590 exec_break(struct tgsi_exec_machine
*mach
)
2592 if (mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_LOOP
) {
2593 /* turn off loop channels for each enabled exec channel */
2594 mach
->LoopMask
&= ~mach
->ExecMask
;
2595 /* Todo: if mach->LoopMask == 0, jump to end of loop */
2596 UPDATE_EXEC_MASK(mach
);
2598 assert(mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_SWITCH
);
2600 mach
->Switch
.mask
= 0x0;
2602 UPDATE_EXEC_MASK(mach
);
2607 exec_switch(struct tgsi_exec_machine
*mach
,
2608 const struct tgsi_full_instruction
*inst
)
2610 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
2611 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
2613 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
2614 fetch_source(mach
, &mach
->Switch
.selector
, &inst
->Src
[0], CHAN_X
, TGSI_EXEC_DATA_UINT
);
2615 mach
->Switch
.mask
= 0x0;
2616 mach
->Switch
.defaultMask
= 0x0;
2618 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
2619 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_SWITCH
;
2621 UPDATE_EXEC_MASK(mach
);
2625 exec_case(struct tgsi_exec_machine
*mach
,
2626 const struct tgsi_full_instruction
*inst
)
2628 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
2629 union tgsi_exec_channel src
;
2632 fetch_source(mach
, &src
, &inst
->Src
[0], CHAN_X
, TGSI_EXEC_DATA_UINT
);
2634 if (mach
->Switch
.selector
.u
[0] == src
.u
[0]) {
2637 if (mach
->Switch
.selector
.u
[1] == src
.u
[1]) {
2640 if (mach
->Switch
.selector
.u
[2] == src
.u
[2]) {
2643 if (mach
->Switch
.selector
.u
[3] == src
.u
[3]) {
2647 mach
->Switch
.defaultMask
|= mask
;
2649 mach
->Switch
.mask
|= mask
& prevMask
;
2651 UPDATE_EXEC_MASK(mach
);
2655 exec_default(struct tgsi_exec_machine
*mach
)
2657 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
2659 mach
->Switch
.mask
|= ~mach
->Switch
.defaultMask
& prevMask
;
2661 UPDATE_EXEC_MASK(mach
);
2665 exec_endswitch(struct tgsi_exec_machine
*mach
)
2667 mach
->Switch
= mach
->SwitchStack
[--mach
->SwitchStackTop
];
2668 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
2670 UPDATE_EXEC_MASK(mach
);
2674 micro_i2f(union tgsi_exec_channel
*dst
,
2675 const union tgsi_exec_channel
*src
)
2677 dst
->f
[0] = (float)src
->i
[0];
2678 dst
->f
[1] = (float)src
->i
[1];
2679 dst
->f
[2] = (float)src
->i
[2];
2680 dst
->f
[3] = (float)src
->i
[3];
2684 micro_not(union tgsi_exec_channel
*dst
,
2685 const union tgsi_exec_channel
*src
)
2687 dst
->u
[0] = ~src
->u
[0];
2688 dst
->u
[1] = ~src
->u
[1];
2689 dst
->u
[2] = ~src
->u
[2];
2690 dst
->u
[3] = ~src
->u
[3];
2694 micro_shl(union tgsi_exec_channel
*dst
,
2695 const union tgsi_exec_channel
*src0
,
2696 const union tgsi_exec_channel
*src1
)
2698 dst
->u
[0] = src0
->u
[0] << src1
->u
[0];
2699 dst
->u
[1] = src0
->u
[1] << src1
->u
[1];
2700 dst
->u
[2] = src0
->u
[2] << src1
->u
[2];
2701 dst
->u
[3] = src0
->u
[3] << src1
->u
[3];
2705 micro_and(union tgsi_exec_channel
*dst
,
2706 const union tgsi_exec_channel
*src0
,
2707 const union tgsi_exec_channel
*src1
)
2709 dst
->u
[0] = src0
->u
[0] & src1
->u
[0];
2710 dst
->u
[1] = src0
->u
[1] & src1
->u
[1];
2711 dst
->u
[2] = src0
->u
[2] & src1
->u
[2];
2712 dst
->u
[3] = src0
->u
[3] & src1
->u
[3];
2716 micro_or(union tgsi_exec_channel
*dst
,
2717 const union tgsi_exec_channel
*src0
,
2718 const union tgsi_exec_channel
*src1
)
2720 dst
->u
[0] = src0
->u
[0] | src1
->u
[0];
2721 dst
->u
[1] = src0
->u
[1] | src1
->u
[1];
2722 dst
->u
[2] = src0
->u
[2] | src1
->u
[2];
2723 dst
->u
[3] = src0
->u
[3] | src1
->u
[3];
2727 micro_xor(union tgsi_exec_channel
*dst
,
2728 const union tgsi_exec_channel
*src0
,
2729 const union tgsi_exec_channel
*src1
)
2731 dst
->u
[0] = src0
->u
[0] ^ src1
->u
[0];
2732 dst
->u
[1] = src0
->u
[1] ^ src1
->u
[1];
2733 dst
->u
[2] = src0
->u
[2] ^ src1
->u
[2];
2734 dst
->u
[3] = src0
->u
[3] ^ src1
->u
[3];
2738 micro_f2i(union tgsi_exec_channel
*dst
,
2739 const union tgsi_exec_channel
*src
)
2741 dst
->i
[0] = (int)src
->f
[0];
2742 dst
->i
[1] = (int)src
->f
[1];
2743 dst
->i
[2] = (int)src
->f
[2];
2744 dst
->i
[3] = (int)src
->f
[3];
2748 micro_idiv(union tgsi_exec_channel
*dst
,
2749 const union tgsi_exec_channel
*src0
,
2750 const union tgsi_exec_channel
*src1
)
2752 dst
->i
[0] = src0
->i
[0] / src1
->i
[0];
2753 dst
->i
[1] = src0
->i
[1] / src1
->i
[1];
2754 dst
->i
[2] = src0
->i
[2] / src1
->i
[2];
2755 dst
->i
[3] = src0
->i
[3] / src1
->i
[3];
2759 micro_imax(union tgsi_exec_channel
*dst
,
2760 const union tgsi_exec_channel
*src0
,
2761 const union tgsi_exec_channel
*src1
)
2763 dst
->i
[0] = src0
->i
[0] > src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
2764 dst
->i
[1] = src0
->i
[1] > src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
2765 dst
->i
[2] = src0
->i
[2] > src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
2766 dst
->i
[3] = src0
->i
[3] > src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
2770 micro_imin(union tgsi_exec_channel
*dst
,
2771 const union tgsi_exec_channel
*src0
,
2772 const union tgsi_exec_channel
*src1
)
2774 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
2775 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
2776 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
2777 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
2781 micro_isge(union tgsi_exec_channel
*dst
,
2782 const union tgsi_exec_channel
*src0
,
2783 const union tgsi_exec_channel
*src1
)
2785 dst
->i
[0] = src0
->i
[0] >= src1
->i
[0] ? -1 : 0;
2786 dst
->i
[1] = src0
->i
[1] >= src1
->i
[1] ? -1 : 0;
2787 dst
->i
[2] = src0
->i
[2] >= src1
->i
[2] ? -1 : 0;
2788 dst
->i
[3] = src0
->i
[3] >= src1
->i
[3] ? -1 : 0;
2792 micro_ishr(union tgsi_exec_channel
*dst
,
2793 const union tgsi_exec_channel
*src0
,
2794 const union tgsi_exec_channel
*src1
)
2796 dst
->i
[0] = src0
->i
[0] >> src1
->i
[0];
2797 dst
->i
[1] = src0
->i
[1] >> src1
->i
[1];
2798 dst
->i
[2] = src0
->i
[2] >> src1
->i
[2];
2799 dst
->i
[3] = src0
->i
[3] >> src1
->i
[3];
2803 micro_islt(union tgsi_exec_channel
*dst
,
2804 const union tgsi_exec_channel
*src0
,
2805 const union tgsi_exec_channel
*src1
)
2807 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? -1 : 0;
2808 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? -1 : 0;
2809 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? -1 : 0;
2810 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? -1 : 0;
2814 micro_f2u(union tgsi_exec_channel
*dst
,
2815 const union tgsi_exec_channel
*src
)
2817 dst
->u
[0] = (uint
)src
->f
[0];
2818 dst
->u
[1] = (uint
)src
->f
[1];
2819 dst
->u
[2] = (uint
)src
->f
[2];
2820 dst
->u
[3] = (uint
)src
->f
[3];
2824 micro_u2f(union tgsi_exec_channel
*dst
,
2825 const union tgsi_exec_channel
*src
)
2827 dst
->f
[0] = (float)src
->u
[0];
2828 dst
->f
[1] = (float)src
->u
[1];
2829 dst
->f
[2] = (float)src
->u
[2];
2830 dst
->f
[3] = (float)src
->u
[3];
2834 micro_uadd(union tgsi_exec_channel
*dst
,
2835 const union tgsi_exec_channel
*src0
,
2836 const union tgsi_exec_channel
*src1
)
2838 dst
->u
[0] = src0
->u
[0] + src1
->u
[0];
2839 dst
->u
[1] = src0
->u
[1] + src1
->u
[1];
2840 dst
->u
[2] = src0
->u
[2] + src1
->u
[2];
2841 dst
->u
[3] = src0
->u
[3] + src1
->u
[3];
2845 micro_udiv(union tgsi_exec_channel
*dst
,
2846 const union tgsi_exec_channel
*src0
,
2847 const union tgsi_exec_channel
*src1
)
2849 dst
->u
[0] = src0
->u
[0] / src1
->u
[0];
2850 dst
->u
[1] = src0
->u
[1] / src1
->u
[1];
2851 dst
->u
[2] = src0
->u
[2] / src1
->u
[2];
2852 dst
->u
[3] = src0
->u
[3] / src1
->u
[3];
2856 micro_umad(union tgsi_exec_channel
*dst
,
2857 const union tgsi_exec_channel
*src0
,
2858 const union tgsi_exec_channel
*src1
,
2859 const union tgsi_exec_channel
*src2
)
2861 dst
->u
[0] = src0
->u
[0] * src1
->u
[0] + src2
->u
[0];
2862 dst
->u
[1] = src0
->u
[1] * src1
->u
[1] + src2
->u
[1];
2863 dst
->u
[2] = src0
->u
[2] * src1
->u
[2] + src2
->u
[2];
2864 dst
->u
[3] = src0
->u
[3] * src1
->u
[3] + src2
->u
[3];
2868 micro_umax(union tgsi_exec_channel
*dst
,
2869 const union tgsi_exec_channel
*src0
,
2870 const union tgsi_exec_channel
*src1
)
2872 dst
->u
[0] = src0
->u
[0] > src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
2873 dst
->u
[1] = src0
->u
[1] > src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
2874 dst
->u
[2] = src0
->u
[2] > src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
2875 dst
->u
[3] = src0
->u
[3] > src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
2879 micro_umin(union tgsi_exec_channel
*dst
,
2880 const union tgsi_exec_channel
*src0
,
2881 const union tgsi_exec_channel
*src1
)
2883 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
2884 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
2885 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
2886 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
2890 micro_umod(union tgsi_exec_channel
*dst
,
2891 const union tgsi_exec_channel
*src0
,
2892 const union tgsi_exec_channel
*src1
)
2894 dst
->u
[0] = src0
->u
[0] % src1
->u
[0];
2895 dst
->u
[1] = src0
->u
[1] % src1
->u
[1];
2896 dst
->u
[2] = src0
->u
[2] % src1
->u
[2];
2897 dst
->u
[3] = src0
->u
[3] % src1
->u
[3];
2901 micro_umul(union tgsi_exec_channel
*dst
,
2902 const union tgsi_exec_channel
*src0
,
2903 const union tgsi_exec_channel
*src1
)
2905 dst
->u
[0] = src0
->u
[0] * src1
->u
[0];
2906 dst
->u
[1] = src0
->u
[1] * src1
->u
[1];
2907 dst
->u
[2] = src0
->u
[2] * src1
->u
[2];
2908 dst
->u
[3] = src0
->u
[3] * src1
->u
[3];
2912 micro_useq(union tgsi_exec_channel
*dst
,
2913 const union tgsi_exec_channel
*src0
,
2914 const union tgsi_exec_channel
*src1
)
2916 dst
->u
[0] = src0
->u
[0] == src1
->u
[0] ? ~0 : 0;
2917 dst
->u
[1] = src0
->u
[1] == src1
->u
[1] ? ~0 : 0;
2918 dst
->u
[2] = src0
->u
[2] == src1
->u
[2] ? ~0 : 0;
2919 dst
->u
[3] = src0
->u
[3] == src1
->u
[3] ? ~0 : 0;
2923 micro_usge(union tgsi_exec_channel
*dst
,
2924 const union tgsi_exec_channel
*src0
,
2925 const union tgsi_exec_channel
*src1
)
2927 dst
->u
[0] = src0
->u
[0] >= src1
->u
[0] ? ~0 : 0;
2928 dst
->u
[1] = src0
->u
[1] >= src1
->u
[1] ? ~0 : 0;
2929 dst
->u
[2] = src0
->u
[2] >= src1
->u
[2] ? ~0 : 0;
2930 dst
->u
[3] = src0
->u
[3] >= src1
->u
[3] ? ~0 : 0;
2934 micro_ushr(union tgsi_exec_channel
*dst
,
2935 const union tgsi_exec_channel
*src0
,
2936 const union tgsi_exec_channel
*src1
)
2938 dst
->u
[0] = src0
->u
[0] >> src1
->u
[0];
2939 dst
->u
[1] = src0
->u
[1] >> src1
->u
[1];
2940 dst
->u
[2] = src0
->u
[2] >> src1
->u
[2];
2941 dst
->u
[3] = src0
->u
[3] >> src1
->u
[3];
2945 micro_uslt(union tgsi_exec_channel
*dst
,
2946 const union tgsi_exec_channel
*src0
,
2947 const union tgsi_exec_channel
*src1
)
2949 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? ~0 : 0;
2950 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? ~0 : 0;
2951 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? ~0 : 0;
2952 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? ~0 : 0;
2956 micro_usne(union tgsi_exec_channel
*dst
,
2957 const union tgsi_exec_channel
*src0
,
2958 const union tgsi_exec_channel
*src1
)
2960 dst
->u
[0] = src0
->u
[0] != src1
->u
[0] ? ~0 : 0;
2961 dst
->u
[1] = src0
->u
[1] != src1
->u
[1] ? ~0 : 0;
2962 dst
->u
[2] = src0
->u
[2] != src1
->u
[2] ? ~0 : 0;
2963 dst
->u
[3] = src0
->u
[3] != src1
->u
[3] ? ~0 : 0;
2968 struct tgsi_exec_machine
*mach
,
2969 const struct tgsi_full_instruction
*inst
,
2972 union tgsi_exec_channel r
[10];
2976 switch (inst
->Instruction
.Opcode
) {
2977 case TGSI_OPCODE_ARL
:
2978 exec_vector_unary(mach
, inst
, micro_arl
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
2981 case TGSI_OPCODE_MOV
:
2982 exec_vector_unary(mach
, inst
, micro_mov
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
2985 case TGSI_OPCODE_LIT
:
2986 exec_lit(mach
, inst
);
2989 case TGSI_OPCODE_RCP
:
2990 exec_scalar_unary(mach
, inst
, micro_rcp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
2993 case TGSI_OPCODE_RSQ
:
2994 exec_scalar_unary(mach
, inst
, micro_rsq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
2997 case TGSI_OPCODE_EXP
:
2998 exec_exp(mach
, inst
);
3001 case TGSI_OPCODE_LOG
:
3002 exec_log(mach
, inst
);
3005 case TGSI_OPCODE_MUL
:
3006 exec_vector_binary(mach
, inst
, micro_mul
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3009 case TGSI_OPCODE_ADD
:
3010 exec_vector_binary(mach
, inst
, micro_add
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3013 case TGSI_OPCODE_DP3
:
3014 exec_dp3(mach
, inst
);
3017 case TGSI_OPCODE_DP4
:
3018 exec_dp4(mach
, inst
);
3021 case TGSI_OPCODE_DST
:
3022 exec_dst(mach
, inst
);
3025 case TGSI_OPCODE_MIN
:
3026 exec_vector_binary(mach
, inst
, micro_min
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3029 case TGSI_OPCODE_MAX
:
3030 exec_vector_binary(mach
, inst
, micro_max
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3033 case TGSI_OPCODE_SLT
:
3034 exec_vector_binary(mach
, inst
, micro_slt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3037 case TGSI_OPCODE_SGE
:
3038 exec_vector_binary(mach
, inst
, micro_sge
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3041 case TGSI_OPCODE_MAD
:
3042 exec_vector_trinary(mach
, inst
, micro_mad
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3045 case TGSI_OPCODE_SUB
:
3046 exec_vector_binary(mach
, inst
, micro_sub
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3049 case TGSI_OPCODE_LRP
:
3050 exec_vector_trinary(mach
, inst
, micro_lrp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3053 case TGSI_OPCODE_CND
:
3054 exec_vector_trinary(mach
, inst
, micro_cnd
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3057 case TGSI_OPCODE_DP2A
:
3058 exec_dp2a(mach
, inst
);
3061 case TGSI_OPCODE_FRC
:
3062 exec_vector_unary(mach
, inst
, micro_frc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3065 case TGSI_OPCODE_CLAMP
:
3066 exec_vector_trinary(mach
, inst
, micro_clamp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3069 case TGSI_OPCODE_FLR
:
3070 exec_vector_unary(mach
, inst
, micro_flr
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3073 case TGSI_OPCODE_ROUND
:
3074 exec_vector_unary(mach
, inst
, micro_rnd
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3077 case TGSI_OPCODE_EX2
:
3078 exec_scalar_unary(mach
, inst
, micro_exp2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3081 case TGSI_OPCODE_LG2
:
3082 exec_scalar_unary(mach
, inst
, micro_lg2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3085 case TGSI_OPCODE_POW
:
3086 exec_scalar_binary(mach
, inst
, micro_pow
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3089 case TGSI_OPCODE_XPD
:
3090 exec_xpd(mach
, inst
);
3093 case TGSI_OPCODE_ABS
:
3094 exec_vector_unary(mach
, inst
, micro_abs
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3097 case TGSI_OPCODE_RCC
:
3098 exec_scalar_unary(mach
, inst
, micro_rcc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3101 case TGSI_OPCODE_DPH
:
3102 exec_dph(mach
, inst
);
3105 case TGSI_OPCODE_COS
:
3106 exec_scalar_unary(mach
, inst
, micro_cos
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3109 case TGSI_OPCODE_DDX
:
3110 exec_vector_unary(mach
, inst
, micro_ddx
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3113 case TGSI_OPCODE_DDY
:
3114 exec_vector_unary(mach
, inst
, micro_ddy
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3117 case TGSI_OPCODE_KILP
:
3118 exec_kilp (mach
, inst
);
3121 case TGSI_OPCODE_KIL
:
3122 exec_kil (mach
, inst
);
3125 case TGSI_OPCODE_PK2H
:
3129 case TGSI_OPCODE_PK2US
:
3133 case TGSI_OPCODE_PK4B
:
3137 case TGSI_OPCODE_PK4UB
:
3141 case TGSI_OPCODE_RFL
:
3142 exec_rfl(mach
, inst
);
3145 case TGSI_OPCODE_SEQ
:
3146 exec_vector_binary(mach
, inst
, micro_seq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3149 case TGSI_OPCODE_SFL
:
3150 exec_vector(mach
, inst
, micro_sfl
, TGSI_EXEC_DATA_FLOAT
);
3153 case TGSI_OPCODE_SGT
:
3154 exec_vector_binary(mach
, inst
, micro_sgt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3157 case TGSI_OPCODE_SIN
:
3158 exec_scalar_unary(mach
, inst
, micro_sin
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3161 case TGSI_OPCODE_SLE
:
3162 exec_vector_binary(mach
, inst
, micro_sle
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3165 case TGSI_OPCODE_SNE
:
3166 exec_vector_binary(mach
, inst
, micro_sne
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3169 case TGSI_OPCODE_STR
:
3170 exec_vector(mach
, inst
, micro_str
, TGSI_EXEC_DATA_FLOAT
);
3173 case TGSI_OPCODE_TEX
:
3174 /* simple texture lookup */
3175 /* src[0] = texcoord */
3176 /* src[1] = sampler unit */
3177 exec_tex(mach
, inst
, TEX_MODIFIER_NONE
);
3180 case TGSI_OPCODE_TXB
:
3181 /* Texture lookup with lod bias */
3182 /* src[0] = texcoord (src[0].w = LOD bias) */
3183 /* src[1] = sampler unit */
3184 exec_tex(mach
, inst
, TEX_MODIFIER_LOD_BIAS
);
3187 case TGSI_OPCODE_TXD
:
3188 /* Texture lookup with explict partial derivatives */
3189 /* src[0] = texcoord */
3190 /* src[1] = d[strq]/dx */
3191 /* src[2] = d[strq]/dy */
3192 /* src[3] = sampler unit */
3193 exec_txd(mach
, inst
);
3196 case TGSI_OPCODE_TXL
:
3197 /* Texture lookup with explit LOD */
3198 /* src[0] = texcoord (src[0].w = LOD) */
3199 /* src[1] = sampler unit */
3200 exec_tex(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
);
3203 case TGSI_OPCODE_TXP
:
3204 /* Texture lookup with projection */
3205 /* src[0] = texcoord (src[0].w = projection) */
3206 /* src[1] = sampler unit */
3207 exec_tex(mach
, inst
, TEX_MODIFIER_PROJECTED
);
3210 case TGSI_OPCODE_UP2H
:
3214 case TGSI_OPCODE_UP2US
:
3218 case TGSI_OPCODE_UP4B
:
3222 case TGSI_OPCODE_UP4UB
:
3226 case TGSI_OPCODE_X2D
:
3227 exec_x2d(mach
, inst
);
3230 case TGSI_OPCODE_ARA
:
3234 case TGSI_OPCODE_ARR
:
3235 exec_vector_unary(mach
, inst
, micro_arr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
3238 case TGSI_OPCODE_BRA
:
3242 case TGSI_OPCODE_CAL
:
3243 /* skip the call if no execution channels are enabled */
3244 if (mach
->ExecMask
) {
3247 /* First, record the depths of the execution stacks.
3248 * This is important for deeply nested/looped return statements.
3249 * We have to unwind the stacks by the correct amount. For a
3250 * real code generator, we could determine the number of entries
3251 * to pop off each stack with simple static analysis and avoid
3252 * implementing this data structure at run time.
3254 mach
->CallStack
[mach
->CallStackTop
].CondStackTop
= mach
->CondStackTop
;
3255 mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
= mach
->LoopStackTop
;
3256 mach
->CallStack
[mach
->CallStackTop
].ContStackTop
= mach
->ContStackTop
;
3257 mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
= mach
->SwitchStackTop
;
3258 mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
= mach
->BreakStackTop
;
3259 /* note that PC was already incremented above */
3260 mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
= *pc
;
3262 mach
->CallStackTop
++;
3264 /* Second, push the Cond, Loop, Cont, Func stacks */
3265 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
3266 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
3267 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
3268 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
3269 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
3270 assert(mach
->FuncStackTop
< TGSI_EXEC_MAX_CALL_NESTING
);
3272 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
3273 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
3274 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
3275 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
3276 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
3277 mach
->FuncStack
[mach
->FuncStackTop
++] = mach
->FuncMask
;
3279 /* Finally, jump to the subroutine */
3280 *pc
= inst
->Label
.Label
;
3284 case TGSI_OPCODE_RET
:
3285 mach
->FuncMask
&= ~mach
->ExecMask
;
3286 UPDATE_EXEC_MASK(mach
);
3288 if (mach
->FuncMask
== 0x0) {
3289 /* really return now (otherwise, keep executing */
3291 if (mach
->CallStackTop
== 0) {
3292 /* returning from main() */
3293 mach
->CondStackTop
= 0;
3294 mach
->LoopStackTop
= 0;
3299 assert(mach
->CallStackTop
> 0);
3300 mach
->CallStackTop
--;
3302 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
3303 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
3305 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
3306 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
3308 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
3309 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
3311 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
3312 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
3314 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
3315 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
3317 assert(mach
->FuncStackTop
> 0);
3318 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
3320 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
3322 UPDATE_EXEC_MASK(mach
);
3326 case TGSI_OPCODE_SSG
:
3327 exec_vector_unary(mach
, inst
, micro_sgn
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3330 case TGSI_OPCODE_CMP
:
3331 exec_vector_trinary(mach
, inst
, micro_cmp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3334 case TGSI_OPCODE_SCS
:
3335 exec_scs(mach
, inst
);
3338 case TGSI_OPCODE_NRM
:
3339 exec_nrm3(mach
, inst
);
3342 case TGSI_OPCODE_NRM4
:
3343 exec_nrm4(mach
, inst
);
3346 case TGSI_OPCODE_DIV
:
3347 exec_vector_binary(mach
, inst
, micro_div
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3350 case TGSI_OPCODE_DP2
:
3351 exec_dp2(mach
, inst
);
3354 case TGSI_OPCODE_IF
:
3356 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
3357 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
3358 FETCH( &r
[0], 0, CHAN_X
);
3359 /* update CondMask */
3361 mach
->CondMask
&= ~0x1;
3364 mach
->CondMask
&= ~0x2;
3367 mach
->CondMask
&= ~0x4;
3370 mach
->CondMask
&= ~0x8;
3372 UPDATE_EXEC_MASK(mach
);
3373 /* Todo: If CondMask==0, jump to ELSE */
3376 case TGSI_OPCODE_ELSE
:
3377 /* invert CondMask wrt previous mask */
3380 assert(mach
->CondStackTop
> 0);
3381 prevMask
= mach
->CondStack
[mach
->CondStackTop
- 1];
3382 mach
->CondMask
= ~mach
->CondMask
& prevMask
;
3383 UPDATE_EXEC_MASK(mach
);
3384 /* Todo: If CondMask==0, jump to ENDIF */
3388 case TGSI_OPCODE_ENDIF
:
3390 assert(mach
->CondStackTop
> 0);
3391 mach
->CondMask
= mach
->CondStack
[--mach
->CondStackTop
];
3392 UPDATE_EXEC_MASK(mach
);
3395 case TGSI_OPCODE_END
:
3396 /* make sure we end primitives which haven't
3397 * been explicitly emitted */
3398 conditional_emit_primitive(mach
);
3399 /* halt execution */
3403 case TGSI_OPCODE_PUSHA
:
3407 case TGSI_OPCODE_POPA
:
3411 case TGSI_OPCODE_CEIL
:
3412 exec_vector_unary(mach
, inst
, micro_ceil
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3415 case TGSI_OPCODE_I2F
:
3416 exec_vector_unary(mach
, inst
, micro_i2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_INT
);
3419 case TGSI_OPCODE_NOT
:
3420 exec_vector_unary(mach
, inst
, micro_not
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
3423 case TGSI_OPCODE_TRUNC
:
3424 exec_vector_unary(mach
, inst
, micro_trunc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
3427 case TGSI_OPCODE_SHL
:
3428 exec_vector_binary(mach
, inst
, micro_shl
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
3431 case TGSI_OPCODE_AND
:
3432 exec_vector_binary(mach
, inst
, micro_and
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
3435 case TGSI_OPCODE_OR
:
3436 exec_vector_binary(mach
, inst
, micro_or
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
3439 case TGSI_OPCODE_MOD
:
3443 case TGSI_OPCODE_XOR
:
3444 exec_vector_binary(mach
, inst
, micro_xor
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
3447 case TGSI_OPCODE_SAD
:
3451 case TGSI_OPCODE_TXF
:
3455 case TGSI_OPCODE_TXQ
:
3459 case TGSI_OPCODE_EMIT
:
3463 case TGSI_OPCODE_ENDPRIM
:
3464 emit_primitive(mach
);
3467 case TGSI_OPCODE_BGNLOOP
:
3468 /* push LoopMask and ContMasks */
3469 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
3470 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
3471 assert(mach
->LoopLabelStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
3472 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
3474 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
3475 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
3476 mach
->LoopLabelStack
[mach
->LoopLabelStackTop
++] = *pc
- 1;
3477 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
3478 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_LOOP
;
3481 case TGSI_OPCODE_ENDLOOP
:
3482 /* Restore ContMask, but don't pop */
3483 assert(mach
->ContStackTop
> 0);
3484 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
- 1];
3485 UPDATE_EXEC_MASK(mach
);
3486 if (mach
->ExecMask
) {
3487 /* repeat loop: jump to instruction just past BGNLOOP */
3488 assert(mach
->LoopLabelStackTop
> 0);
3489 *pc
= mach
->LoopLabelStack
[mach
->LoopLabelStackTop
- 1] + 1;
3492 /* exit loop: pop LoopMask */
3493 assert(mach
->LoopStackTop
> 0);
3494 mach
->LoopMask
= mach
->LoopStack
[--mach
->LoopStackTop
];
3496 assert(mach
->ContStackTop
> 0);
3497 mach
->ContMask
= mach
->ContStack
[--mach
->ContStackTop
];
3498 assert(mach
->LoopLabelStackTop
> 0);
3499 --mach
->LoopLabelStackTop
;
3501 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
3503 UPDATE_EXEC_MASK(mach
);
3506 case TGSI_OPCODE_BRK
:
3510 case TGSI_OPCODE_CONT
:
3511 /* turn off cont channels for each enabled exec channel */
3512 mach
->ContMask
&= ~mach
->ExecMask
;
3513 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3514 UPDATE_EXEC_MASK(mach
);
3517 case TGSI_OPCODE_BGNSUB
:
3521 case TGSI_OPCODE_ENDSUB
:
3523 * XXX: This really should be a no-op. We should never reach this opcode.
3526 assert(mach
->CallStackTop
> 0);
3527 mach
->CallStackTop
--;
3529 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
3530 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
3532 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
3533 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
3535 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
3536 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
3538 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
3539 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
3541 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
3542 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
3544 assert(mach
->FuncStackTop
> 0);
3545 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
3547 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
3549 UPDATE_EXEC_MASK(mach
);
3552 case TGSI_OPCODE_NOP
:
3555 case TGSI_OPCODE_BREAKC
:
3556 FETCH(&r
[0], 0, CHAN_X
);
3557 /* update CondMask */
3558 if (r
[0].u
[0] && (mach
->ExecMask
& 0x1)) {
3559 mach
->LoopMask
&= ~0x1;
3561 if (r
[0].u
[1] && (mach
->ExecMask
& 0x2)) {
3562 mach
->LoopMask
&= ~0x2;
3564 if (r
[0].u
[2] && (mach
->ExecMask
& 0x4)) {
3565 mach
->LoopMask
&= ~0x4;
3567 if (r
[0].u
[3] && (mach
->ExecMask
& 0x8)) {
3568 mach
->LoopMask
&= ~0x8;
3570 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3571 UPDATE_EXEC_MASK(mach
);
3574 case TGSI_OPCODE_F2I
:
3575 exec_vector_unary(mach
, inst
, micro_f2i
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
3578 case TGSI_OPCODE_IDIV
:
3579 exec_vector_binary(mach
, inst
, micro_idiv
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
3582 case TGSI_OPCODE_IMAX
:
3583 exec_vector_binary(mach
, inst
, micro_imax
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
3586 case TGSI_OPCODE_IMIN
:
3587 exec_vector_binary(mach
, inst
, micro_imin
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
3590 case TGSI_OPCODE_INEG
:
3591 exec_vector_unary(mach
, inst
, micro_ineg
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
3594 case TGSI_OPCODE_ISGE
:
3595 exec_vector_binary(mach
, inst
, micro_isge
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
3598 case TGSI_OPCODE_ISHR
:
3599 exec_vector_binary(mach
, inst
, micro_ishr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
3602 case TGSI_OPCODE_ISLT
:
3603 exec_vector_binary(mach
, inst
, micro_islt
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
3606 case TGSI_OPCODE_F2U
:
3607 exec_vector_unary(mach
, inst
, micro_f2u
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
3610 case TGSI_OPCODE_U2F
:
3611 exec_vector_unary(mach
, inst
, micro_u2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_UINT
);
3614 case TGSI_OPCODE_UADD
:
3615 exec_vector_binary(mach
, inst
, micro_uadd
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
3618 case TGSI_OPCODE_UDIV
:
3619 exec_vector_binary(mach
, inst
, micro_udiv
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
3622 case TGSI_OPCODE_UMAD
:
3623 exec_vector_trinary(mach
, inst
, micro_umad
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
3626 case TGSI_OPCODE_UMAX
:
3627 exec_vector_binary(mach
, inst
, micro_umax
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
3630 case TGSI_OPCODE_UMIN
:
3631 exec_vector_binary(mach
, inst
, micro_umin
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
3634 case TGSI_OPCODE_UMOD
:
3635 exec_vector_binary(mach
, inst
, micro_umod
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
3638 case TGSI_OPCODE_UMUL
:
3639 exec_vector_binary(mach
, inst
, micro_umul
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
3642 case TGSI_OPCODE_USEQ
:
3643 exec_vector_binary(mach
, inst
, micro_useq
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
3646 case TGSI_OPCODE_USGE
:
3647 exec_vector_binary(mach
, inst
, micro_usge
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
3650 case TGSI_OPCODE_USHR
:
3651 exec_vector_binary(mach
, inst
, micro_ushr
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
3654 case TGSI_OPCODE_USLT
:
3655 exec_vector_binary(mach
, inst
, micro_uslt
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
3658 case TGSI_OPCODE_USNE
:
3659 exec_vector_binary(mach
, inst
, micro_usne
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
3662 case TGSI_OPCODE_SWITCH
:
3663 exec_switch(mach
, inst
);
3666 case TGSI_OPCODE_CASE
:
3667 exec_case(mach
, inst
);
3670 case TGSI_OPCODE_DEFAULT
:
3674 case TGSI_OPCODE_ENDSWITCH
:
3675 exec_endswitch(mach
);
3684 #define DEBUG_EXECUTION 0
3688 * Run TGSI interpreter.
3689 * \return bitmask of "alive" quad components
3692 tgsi_exec_machine_run( struct tgsi_exec_machine
*mach
)
3697 mach
->CondMask
= 0xf;
3698 mach
->LoopMask
= 0xf;
3699 mach
->ContMask
= 0xf;
3700 mach
->FuncMask
= 0xf;
3701 mach
->ExecMask
= 0xf;
3703 mach
->Switch
.mask
= 0xf;
3705 assert(mach
->CondStackTop
== 0);
3706 assert(mach
->LoopStackTop
== 0);
3707 assert(mach
->ContStackTop
== 0);
3708 assert(mach
->SwitchStackTop
== 0);
3709 assert(mach
->BreakStackTop
== 0);
3710 assert(mach
->CallStackTop
== 0);
3712 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] = 0;
3713 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] = 0;
3715 if( mach
->Processor
== TGSI_PROCESSOR_GEOMETRY
) {
3716 mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0] = 0;
3717 mach
->Primitives
[0] = 0;
3720 /* execute declarations (interpolants) */
3721 for (i
= 0; i
< mach
->NumDeclarations
; i
++) {
3722 exec_declaration( mach
, mach
->Declarations
+i
);
3727 struct tgsi_exec_vector temps
[TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
];
3728 struct tgsi_exec_vector outputs
[PIPE_MAX_ATTRIBS
];
3731 memcpy(temps
, mach
->Temps
, sizeof(temps
));
3732 memcpy(outputs
, mach
->Outputs
, sizeof(outputs
));
3735 /* execute instructions, until pc is set to -1 */
3741 tgsi_dump_instruction(&mach
->Instructions
[pc
], inst
++);
3744 assert(pc
< (int) mach
->NumInstructions
);
3745 exec_instruction(mach
, mach
->Instructions
+ pc
, &pc
);
3748 for (i
= 0; i
< TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
; i
++) {
3749 if (memcmp(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]))) {
3752 memcpy(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]));
3753 debug_printf("TEMP[%2u] = ", i
);
3754 for (j
= 0; j
< 4; j
++) {
3758 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
3759 temps
[i
].xyzw
[0].f
[j
], temps
[i
].xyzw
[0].u
[j
],
3760 temps
[i
].xyzw
[1].f
[j
], temps
[i
].xyzw
[1].u
[j
],
3761 temps
[i
].xyzw
[2].f
[j
], temps
[i
].xyzw
[2].u
[j
],
3762 temps
[i
].xyzw
[3].f
[j
], temps
[i
].xyzw
[3].u
[j
]);
3766 for (i
= 0; i
< PIPE_MAX_ATTRIBS
; i
++) {
3767 if (memcmp(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]))) {
3770 memcpy(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]));
3771 debug_printf("OUT[%2u] = ", i
);
3772 for (j
= 0; j
< 4; j
++) {
3776 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
3777 outputs
[i
].xyzw
[0].f
[j
], outputs
[i
].xyzw
[0].u
[j
],
3778 outputs
[i
].xyzw
[1].f
[j
], outputs
[i
].xyzw
[1].u
[j
],
3779 outputs
[i
].xyzw
[2].f
[j
], outputs
[i
].xyzw
[2].u
[j
],
3780 outputs
[i
].xyzw
[3].f
[j
], outputs
[i
].xyzw
[3].u
[j
]);
3789 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
3790 if (mach
->Processor
== TGSI_PROCESSOR_FRAGMENT
) {
3792 * Scale back depth component.
3794 for (i
= 0; i
< 4; i
++)
3795 mach
->Outputs
[0].xyzw
[2].f
[i
] *= ctx
->DrawBuffer
->_DepthMaxF
;
3799 /* Strictly speaking, these assertions aren't really needed but they
3800 * can potentially catch some bugs in the control flow code.
3802 assert(mach
->CondStackTop
== 0);
3803 assert(mach
->LoopStackTop
== 0);
3804 assert(mach
->ContStackTop
== 0);
3805 assert(mach
->SwitchStackTop
== 0);
3806 assert(mach
->BreakStackTop
== 0);
3807 assert(mach
->CallStackTop
== 0);
3809 return ~mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];