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gallium: Drop unused BRA opcode.
[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 VMware, Inc.
4 * All Rights Reserved.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 /**
30 * TGSI interpreter/executor.
31 *
32 * Flow control information:
33 *
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
38 *
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
42 * See store_dest().
43 *
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
47 *
48 *
49 * Authors:
50 * Michal Krol
51 * Brian Paul
52 */
53
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_memory.h"
62 #include "util/u_math.h"
63
64
65 #define DEBUG_EXECUTION 0
66
67
68 #define FAST_MATH 0
69
70 #define TILE_TOP_LEFT 0
71 #define TILE_TOP_RIGHT 1
72 #define TILE_BOTTOM_LEFT 2
73 #define TILE_BOTTOM_RIGHT 3
74
75 static void
76 micro_abs(union tgsi_exec_channel *dst,
77 const union tgsi_exec_channel *src)
78 {
79 dst->f[0] = fabsf(src->f[0]);
80 dst->f[1] = fabsf(src->f[1]);
81 dst->f[2] = fabsf(src->f[2]);
82 dst->f[3] = fabsf(src->f[3]);
83 }
84
85 static void
86 micro_arl(union tgsi_exec_channel *dst,
87 const union tgsi_exec_channel *src)
88 {
89 dst->i[0] = (int)floorf(src->f[0]);
90 dst->i[1] = (int)floorf(src->f[1]);
91 dst->i[2] = (int)floorf(src->f[2]);
92 dst->i[3] = (int)floorf(src->f[3]);
93 }
94
95 static void
96 micro_arr(union tgsi_exec_channel *dst,
97 const union tgsi_exec_channel *src)
98 {
99 dst->i[0] = (int)floorf(src->f[0] + 0.5f);
100 dst->i[1] = (int)floorf(src->f[1] + 0.5f);
101 dst->i[2] = (int)floorf(src->f[2] + 0.5f);
102 dst->i[3] = (int)floorf(src->f[3] + 0.5f);
103 }
104
105 static void
106 micro_ceil(union tgsi_exec_channel *dst,
107 const union tgsi_exec_channel *src)
108 {
109 dst->f[0] = ceilf(src->f[0]);
110 dst->f[1] = ceilf(src->f[1]);
111 dst->f[2] = ceilf(src->f[2]);
112 dst->f[3] = ceilf(src->f[3]);
113 }
114
115 static void
116 micro_clamp(union tgsi_exec_channel *dst,
117 const union tgsi_exec_channel *src0,
118 const union tgsi_exec_channel *src1,
119 const union tgsi_exec_channel *src2)
120 {
121 dst->f[0] = src0->f[0] < src1->f[0] ? src1->f[0] : src0->f[0] > src2->f[0] ? src2->f[0] : src0->f[0];
122 dst->f[1] = src0->f[1] < src1->f[1] ? src1->f[1] : src0->f[1] > src2->f[1] ? src2->f[1] : src0->f[1];
123 dst->f[2] = src0->f[2] < src1->f[2] ? src1->f[2] : src0->f[2] > src2->f[2] ? src2->f[2] : src0->f[2];
124 dst->f[3] = src0->f[3] < src1->f[3] ? src1->f[3] : src0->f[3] > src2->f[3] ? src2->f[3] : src0->f[3];
125 }
126
127 static void
128 micro_cmp(union tgsi_exec_channel *dst,
129 const union tgsi_exec_channel *src0,
130 const union tgsi_exec_channel *src1,
131 const union tgsi_exec_channel *src2)
132 {
133 dst->f[0] = src0->f[0] < 0.0f ? src1->f[0] : src2->f[0];
134 dst->f[1] = src0->f[1] < 0.0f ? src1->f[1] : src2->f[1];
135 dst->f[2] = src0->f[2] < 0.0f ? src1->f[2] : src2->f[2];
136 dst->f[3] = src0->f[3] < 0.0f ? src1->f[3] : src2->f[3];
137 }
138
139 static void
140 micro_cnd(union tgsi_exec_channel *dst,
141 const union tgsi_exec_channel *src0,
142 const union tgsi_exec_channel *src1,
143 const union tgsi_exec_channel *src2)
144 {
145 dst->f[0] = src2->f[0] > 0.5f ? src0->f[0] : src1->f[0];
146 dst->f[1] = src2->f[1] > 0.5f ? src0->f[1] : src1->f[1];
147 dst->f[2] = src2->f[2] > 0.5f ? src0->f[2] : src1->f[2];
148 dst->f[3] = src2->f[3] > 0.5f ? src0->f[3] : src1->f[3];
149 }
150
151 static void
152 micro_cos(union tgsi_exec_channel *dst,
153 const union tgsi_exec_channel *src)
154 {
155 dst->f[0] = cosf(src->f[0]);
156 dst->f[1] = cosf(src->f[1]);
157 dst->f[2] = cosf(src->f[2]);
158 dst->f[3] = cosf(src->f[3]);
159 }
160
161 static void
162 micro_ddx(union tgsi_exec_channel *dst,
163 const union tgsi_exec_channel *src)
164 {
165 dst->f[0] =
166 dst->f[1] =
167 dst->f[2] =
168 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
169 }
170
171 static void
172 micro_ddy(union tgsi_exec_channel *dst,
173 const union tgsi_exec_channel *src)
174 {
175 dst->f[0] =
176 dst->f[1] =
177 dst->f[2] =
178 dst->f[3] = src->f[TILE_BOTTOM_LEFT] - src->f[TILE_TOP_LEFT];
179 }
180
181 static void
182 micro_exp2(union tgsi_exec_channel *dst,
183 const union tgsi_exec_channel *src)
184 {
185 #if FAST_MATH
186 dst->f[0] = util_fast_exp2(src->f[0]);
187 dst->f[1] = util_fast_exp2(src->f[1]);
188 dst->f[2] = util_fast_exp2(src->f[2]);
189 dst->f[3] = util_fast_exp2(src->f[3]);
190 #else
191 #if DEBUG
192 /* Inf is okay for this instruction, so clamp it to silence assertions. */
193 uint i;
194 union tgsi_exec_channel clamped;
195
196 for (i = 0; i < 4; i++) {
197 if (src->f[i] > 127.99999f) {
198 clamped.f[i] = 127.99999f;
199 } else if (src->f[i] < -126.99999f) {
200 clamped.f[i] = -126.99999f;
201 } else {
202 clamped.f[i] = src->f[i];
203 }
204 }
205 src = &clamped;
206 #endif /* DEBUG */
207
208 dst->f[0] = powf(2.0f, src->f[0]);
209 dst->f[1] = powf(2.0f, src->f[1]);
210 dst->f[2] = powf(2.0f, src->f[2]);
211 dst->f[3] = powf(2.0f, src->f[3]);
212 #endif /* FAST_MATH */
213 }
214
215 static void
216 micro_flr(union tgsi_exec_channel *dst,
217 const union tgsi_exec_channel *src)
218 {
219 dst->f[0] = floorf(src->f[0]);
220 dst->f[1] = floorf(src->f[1]);
221 dst->f[2] = floorf(src->f[2]);
222 dst->f[3] = floorf(src->f[3]);
223 }
224
225 static void
226 micro_frc(union tgsi_exec_channel *dst,
227 const union tgsi_exec_channel *src)
228 {
229 dst->f[0] = src->f[0] - floorf(src->f[0]);
230 dst->f[1] = src->f[1] - floorf(src->f[1]);
231 dst->f[2] = src->f[2] - floorf(src->f[2]);
232 dst->f[3] = src->f[3] - floorf(src->f[3]);
233 }
234
235 static void
236 micro_iabs(union tgsi_exec_channel *dst,
237 const union tgsi_exec_channel *src)
238 {
239 dst->i[0] = src->i[0] >= 0 ? src->i[0] : -src->i[0];
240 dst->i[1] = src->i[1] >= 0 ? src->i[1] : -src->i[1];
241 dst->i[2] = src->i[2] >= 0 ? src->i[2] : -src->i[2];
242 dst->i[3] = src->i[3] >= 0 ? src->i[3] : -src->i[3];
243 }
244
245 static void
246 micro_ineg(union tgsi_exec_channel *dst,
247 const union tgsi_exec_channel *src)
248 {
249 dst->i[0] = -src->i[0];
250 dst->i[1] = -src->i[1];
251 dst->i[2] = -src->i[2];
252 dst->i[3] = -src->i[3];
253 }
254
255 static void
256 micro_lg2(union tgsi_exec_channel *dst,
257 const union tgsi_exec_channel *src)
258 {
259 #if FAST_MATH
260 dst->f[0] = util_fast_log2(src->f[0]);
261 dst->f[1] = util_fast_log2(src->f[1]);
262 dst->f[2] = util_fast_log2(src->f[2]);
263 dst->f[3] = util_fast_log2(src->f[3]);
264 #else
265 dst->f[0] = logf(src->f[0]) * 1.442695f;
266 dst->f[1] = logf(src->f[1]) * 1.442695f;
267 dst->f[2] = logf(src->f[2]) * 1.442695f;
268 dst->f[3] = logf(src->f[3]) * 1.442695f;
269 #endif
270 }
271
272 static void
273 micro_lrp(union tgsi_exec_channel *dst,
274 const union tgsi_exec_channel *src0,
275 const union tgsi_exec_channel *src1,
276 const union tgsi_exec_channel *src2)
277 {
278 dst->f[0] = src0->f[0] * (src1->f[0] - src2->f[0]) + src2->f[0];
279 dst->f[1] = src0->f[1] * (src1->f[1] - src2->f[1]) + src2->f[1];
280 dst->f[2] = src0->f[2] * (src1->f[2] - src2->f[2]) + src2->f[2];
281 dst->f[3] = src0->f[3] * (src1->f[3] - src2->f[3]) + src2->f[3];
282 }
283
284 static void
285 micro_mad(union tgsi_exec_channel *dst,
286 const union tgsi_exec_channel *src0,
287 const union tgsi_exec_channel *src1,
288 const union tgsi_exec_channel *src2)
289 {
290 dst->f[0] = src0->f[0] * src1->f[0] + src2->f[0];
291 dst->f[1] = src0->f[1] * src1->f[1] + src2->f[1];
292 dst->f[2] = src0->f[2] * src1->f[2] + src2->f[2];
293 dst->f[3] = src0->f[3] * src1->f[3] + src2->f[3];
294 }
295
296 static void
297 micro_mov(union tgsi_exec_channel *dst,
298 const union tgsi_exec_channel *src)
299 {
300 dst->u[0] = src->u[0];
301 dst->u[1] = src->u[1];
302 dst->u[2] = src->u[2];
303 dst->u[3] = src->u[3];
304 }
305
306 static void
307 micro_rcp(union tgsi_exec_channel *dst,
308 const union tgsi_exec_channel *src)
309 {
310 #if 0 /* for debugging */
311 assert(src->f[0] != 0.0f);
312 assert(src->f[1] != 0.0f);
313 assert(src->f[2] != 0.0f);
314 assert(src->f[3] != 0.0f);
315 #endif
316 dst->f[0] = 1.0f / src->f[0];
317 dst->f[1] = 1.0f / src->f[1];
318 dst->f[2] = 1.0f / src->f[2];
319 dst->f[3] = 1.0f / src->f[3];
320 }
321
322 static void
323 micro_rnd(union tgsi_exec_channel *dst,
324 const union tgsi_exec_channel *src)
325 {
326 dst->f[0] = floorf(src->f[0] + 0.5f);
327 dst->f[1] = floorf(src->f[1] + 0.5f);
328 dst->f[2] = floorf(src->f[2] + 0.5f);
329 dst->f[3] = floorf(src->f[3] + 0.5f);
330 }
331
332 static void
333 micro_rsq(union tgsi_exec_channel *dst,
334 const union tgsi_exec_channel *src)
335 {
336 #if 0 /* for debugging */
337 assert(src->f[0] != 0.0f);
338 assert(src->f[1] != 0.0f);
339 assert(src->f[2] != 0.0f);
340 assert(src->f[3] != 0.0f);
341 #endif
342 dst->f[0] = 1.0f / sqrtf(src->f[0]);
343 dst->f[1] = 1.0f / sqrtf(src->f[1]);
344 dst->f[2] = 1.0f / sqrtf(src->f[2]);
345 dst->f[3] = 1.0f / sqrtf(src->f[3]);
346 }
347
348 static void
349 micro_sqrt(union tgsi_exec_channel *dst,
350 const union tgsi_exec_channel *src)
351 {
352 dst->f[0] = sqrtf(src->f[0]);
353 dst->f[1] = sqrtf(src->f[1]);
354 dst->f[2] = sqrtf(src->f[2]);
355 dst->f[3] = sqrtf(src->f[3]);
356 }
357
358 static void
359 micro_seq(union tgsi_exec_channel *dst,
360 const union tgsi_exec_channel *src0,
361 const union tgsi_exec_channel *src1)
362 {
363 dst->f[0] = src0->f[0] == src1->f[0] ? 1.0f : 0.0f;
364 dst->f[1] = src0->f[1] == src1->f[1] ? 1.0f : 0.0f;
365 dst->f[2] = src0->f[2] == src1->f[2] ? 1.0f : 0.0f;
366 dst->f[3] = src0->f[3] == src1->f[3] ? 1.0f : 0.0f;
367 }
368
369 static void
370 micro_sge(union tgsi_exec_channel *dst,
371 const union tgsi_exec_channel *src0,
372 const union tgsi_exec_channel *src1)
373 {
374 dst->f[0] = src0->f[0] >= src1->f[0] ? 1.0f : 0.0f;
375 dst->f[1] = src0->f[1] >= src1->f[1] ? 1.0f : 0.0f;
376 dst->f[2] = src0->f[2] >= src1->f[2] ? 1.0f : 0.0f;
377 dst->f[3] = src0->f[3] >= src1->f[3] ? 1.0f : 0.0f;
378 }
379
380 static void
381 micro_sgn(union tgsi_exec_channel *dst,
382 const union tgsi_exec_channel *src)
383 {
384 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
385 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
386 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
387 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
388 }
389
390 static void
391 micro_isgn(union tgsi_exec_channel *dst,
392 const union tgsi_exec_channel *src)
393 {
394 dst->i[0] = src->i[0] < 0 ? -1 : src->i[0] > 0 ? 1 : 0;
395 dst->i[1] = src->i[1] < 0 ? -1 : src->i[1] > 0 ? 1 : 0;
396 dst->i[2] = src->i[2] < 0 ? -1 : src->i[2] > 0 ? 1 : 0;
397 dst->i[3] = src->i[3] < 0 ? -1 : src->i[3] > 0 ? 1 : 0;
398 }
399
400 static void
401 micro_sgt(union tgsi_exec_channel *dst,
402 const union tgsi_exec_channel *src0,
403 const union tgsi_exec_channel *src1)
404 {
405 dst->f[0] = src0->f[0] > src1->f[0] ? 1.0f : 0.0f;
406 dst->f[1] = src0->f[1] > src1->f[1] ? 1.0f : 0.0f;
407 dst->f[2] = src0->f[2] > src1->f[2] ? 1.0f : 0.0f;
408 dst->f[3] = src0->f[3] > src1->f[3] ? 1.0f : 0.0f;
409 }
410
411 static void
412 micro_sin(union tgsi_exec_channel *dst,
413 const union tgsi_exec_channel *src)
414 {
415 dst->f[0] = sinf(src->f[0]);
416 dst->f[1] = sinf(src->f[1]);
417 dst->f[2] = sinf(src->f[2]);
418 dst->f[3] = sinf(src->f[3]);
419 }
420
421 static void
422 micro_sle(union tgsi_exec_channel *dst,
423 const union tgsi_exec_channel *src0,
424 const union tgsi_exec_channel *src1)
425 {
426 dst->f[0] = src0->f[0] <= src1->f[0] ? 1.0f : 0.0f;
427 dst->f[1] = src0->f[1] <= src1->f[1] ? 1.0f : 0.0f;
428 dst->f[2] = src0->f[2] <= src1->f[2] ? 1.0f : 0.0f;
429 dst->f[3] = src0->f[3] <= src1->f[3] ? 1.0f : 0.0f;
430 }
431
432 static void
433 micro_slt(union tgsi_exec_channel *dst,
434 const union tgsi_exec_channel *src0,
435 const union tgsi_exec_channel *src1)
436 {
437 dst->f[0] = src0->f[0] < src1->f[0] ? 1.0f : 0.0f;
438 dst->f[1] = src0->f[1] < src1->f[1] ? 1.0f : 0.0f;
439 dst->f[2] = src0->f[2] < src1->f[2] ? 1.0f : 0.0f;
440 dst->f[3] = src0->f[3] < src1->f[3] ? 1.0f : 0.0f;
441 }
442
443 static void
444 micro_sne(union tgsi_exec_channel *dst,
445 const union tgsi_exec_channel *src0,
446 const union tgsi_exec_channel *src1)
447 {
448 dst->f[0] = src0->f[0] != src1->f[0] ? 1.0f : 0.0f;
449 dst->f[1] = src0->f[1] != src1->f[1] ? 1.0f : 0.0f;
450 dst->f[2] = src0->f[2] != src1->f[2] ? 1.0f : 0.0f;
451 dst->f[3] = src0->f[3] != src1->f[3] ? 1.0f : 0.0f;
452 }
453
454 static void
455 micro_trunc(union tgsi_exec_channel *dst,
456 const union tgsi_exec_channel *src)
457 {
458 dst->f[0] = (float)(int)src->f[0];
459 dst->f[1] = (float)(int)src->f[1];
460 dst->f[2] = (float)(int)src->f[2];
461 dst->f[3] = (float)(int)src->f[3];
462 }
463
464
465 enum tgsi_exec_datatype {
466 TGSI_EXEC_DATA_FLOAT,
467 TGSI_EXEC_DATA_INT,
468 TGSI_EXEC_DATA_UINT
469 };
470
471 /*
472 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
473 */
474 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
475 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
476 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
477 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
478 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
479 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
480
481
482 /** The execution mask depends on the conditional mask and the loop mask */
483 #define UPDATE_EXEC_MASK(MACH) \
484 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
485
486
487 static const union tgsi_exec_channel ZeroVec =
488 { { 0.0, 0.0, 0.0, 0.0 } };
489
490 static const union tgsi_exec_channel OneVec = {
491 {1.0f, 1.0f, 1.0f, 1.0f}
492 };
493
494 static const union tgsi_exec_channel P128Vec = {
495 {128.0f, 128.0f, 128.0f, 128.0f}
496 };
497
498 static const union tgsi_exec_channel M128Vec = {
499 {-128.0f, -128.0f, -128.0f, -128.0f}
500 };
501
502
503 /**
504 * Assert that none of the float values in 'chan' are infinite or NaN.
505 * NaN and Inf may occur normally during program execution and should
506 * not lead to crashes, etc. But when debugging, it's helpful to catch
507 * them.
508 */
509 static INLINE void
510 check_inf_or_nan(const union tgsi_exec_channel *chan)
511 {
512 assert(!util_is_inf_or_nan((chan)->f[0]));
513 assert(!util_is_inf_or_nan((chan)->f[1]));
514 assert(!util_is_inf_or_nan((chan)->f[2]));
515 assert(!util_is_inf_or_nan((chan)->f[3]));
516 }
517
518
519 #ifdef DEBUG
520 static void
521 print_chan(const char *msg, const union tgsi_exec_channel *chan)
522 {
523 debug_printf("%s = {%f, %f, %f, %f}\n",
524 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
525 }
526 #endif
527
528
529 #ifdef DEBUG
530 static void
531 print_temp(const struct tgsi_exec_machine *mach, uint index)
532 {
533 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
534 int i;
535 debug_printf("Temp[%u] =\n", index);
536 for (i = 0; i < 4; i++) {
537 debug_printf(" %c: { %f, %f, %f, %f }\n",
538 "XYZW"[i],
539 tmp->xyzw[i].f[0],
540 tmp->xyzw[i].f[1],
541 tmp->xyzw[i].f[2],
542 tmp->xyzw[i].f[3]);
543 }
544 }
545 #endif
546
547
548 void
549 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine *mach,
550 unsigned num_bufs,
551 const void **bufs,
552 const unsigned *buf_sizes)
553 {
554 unsigned i;
555
556 for (i = 0; i < num_bufs; i++) {
557 mach->Consts[i] = bufs[i];
558 mach->ConstsSize[i] = buf_sizes[i];
559 }
560 }
561
562
563 /**
564 * Check if there's a potential src/dst register data dependency when
565 * using SOA execution.
566 * Example:
567 * MOV T, T.yxwz;
568 * This would expand into:
569 * MOV t0, t1;
570 * MOV t1, t0;
571 * MOV t2, t3;
572 * MOV t3, t2;
573 * The second instruction will have the wrong value for t0 if executed as-is.
574 */
575 boolean
576 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
577 {
578 uint i, chan;
579
580 uint writemask = inst->Dst[0].Register.WriteMask;
581 if (writemask == TGSI_WRITEMASK_X ||
582 writemask == TGSI_WRITEMASK_Y ||
583 writemask == TGSI_WRITEMASK_Z ||
584 writemask == TGSI_WRITEMASK_W ||
585 writemask == TGSI_WRITEMASK_NONE) {
586 /* no chance of data dependency */
587 return FALSE;
588 }
589
590 /* loop over src regs */
591 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
592 if ((inst->Src[i].Register.File ==
593 inst->Dst[0].Register.File) &&
594 ((inst->Src[i].Register.Index ==
595 inst->Dst[0].Register.Index) ||
596 inst->Src[i].Register.Indirect ||
597 inst->Dst[0].Register.Indirect)) {
598 /* loop over dest channels */
599 uint channelsWritten = 0x0;
600 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
601 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
602 /* check if we're reading a channel that's been written */
603 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
604 if (channelsWritten & (1 << swizzle)) {
605 return TRUE;
606 }
607
608 channelsWritten |= (1 << chan);
609 }
610 }
611 }
612 }
613 return FALSE;
614 }
615
616
617 /**
618 * Initialize machine state by expanding tokens to full instructions,
619 * allocating temporary storage, setting up constants, etc.
620 * After this, we can call tgsi_exec_machine_run() many times.
621 */
622 void
623 tgsi_exec_machine_bind_shader(
624 struct tgsi_exec_machine *mach,
625 const struct tgsi_token *tokens,
626 struct tgsi_sampler *sampler)
627 {
628 uint k;
629 struct tgsi_parse_context parse;
630 struct tgsi_full_instruction *instructions;
631 struct tgsi_full_declaration *declarations;
632 uint maxInstructions = 10, numInstructions = 0;
633 uint maxDeclarations = 10, numDeclarations = 0;
634
635 #if 0
636 tgsi_dump(tokens, 0);
637 #endif
638
639 util_init_math();
640
641
642 mach->Tokens = tokens;
643 mach->Sampler = sampler;
644
645 if (!tokens) {
646 /* unbind and free all */
647 FREE(mach->Declarations);
648 mach->Declarations = NULL;
649 mach->NumDeclarations = 0;
650
651 FREE(mach->Instructions);
652 mach->Instructions = NULL;
653 mach->NumInstructions = 0;
654
655 return;
656 }
657
658 k = tgsi_parse_init (&parse, mach->Tokens);
659 if (k != TGSI_PARSE_OK) {
660 debug_printf( "Problem parsing!\n" );
661 return;
662 }
663
664 mach->Processor = parse.FullHeader.Processor.Processor;
665 mach->ImmLimit = 0;
666 mach->NumOutputs = 0;
667
668 if (mach->Processor == TGSI_PROCESSOR_GEOMETRY &&
669 !mach->UsedGeometryShader) {
670 struct tgsi_exec_vector *inputs;
671 struct tgsi_exec_vector *outputs;
672
673 inputs = align_malloc(sizeof(struct tgsi_exec_vector) *
674 TGSI_MAX_PRIM_VERTICES * PIPE_MAX_SHADER_INPUTS,
675 16);
676
677 if (!inputs)
678 return;
679
680 outputs = align_malloc(sizeof(struct tgsi_exec_vector) *
681 TGSI_MAX_TOTAL_VERTICES, 16);
682
683 if (!outputs) {
684 align_free(inputs);
685 return;
686 }
687
688 align_free(mach->Inputs);
689 align_free(mach->Outputs);
690
691 mach->Inputs = inputs;
692 mach->Outputs = outputs;
693 mach->UsedGeometryShader = TRUE;
694 }
695
696 declarations = (struct tgsi_full_declaration *)
697 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
698
699 if (!declarations) {
700 return;
701 }
702
703 instructions = (struct tgsi_full_instruction *)
704 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
705
706 if (!instructions) {
707 FREE( declarations );
708 return;
709 }
710
711 while( !tgsi_parse_end_of_tokens( &parse ) ) {
712 uint i;
713
714 tgsi_parse_token( &parse );
715 switch( parse.FullToken.Token.Type ) {
716 case TGSI_TOKEN_TYPE_DECLARATION:
717 /* save expanded declaration */
718 if (numDeclarations == maxDeclarations) {
719 declarations = REALLOC(declarations,
720 maxDeclarations
721 * sizeof(struct tgsi_full_declaration),
722 (maxDeclarations + 10)
723 * sizeof(struct tgsi_full_declaration));
724 maxDeclarations += 10;
725 }
726 if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_OUTPUT) {
727 unsigned reg;
728 for (reg = parse.FullToken.FullDeclaration.Range.First;
729 reg <= parse.FullToken.FullDeclaration.Range.Last;
730 ++reg) {
731 ++mach->NumOutputs;
732 }
733 }
734 memcpy(declarations + numDeclarations,
735 &parse.FullToken.FullDeclaration,
736 sizeof(declarations[0]));
737 numDeclarations++;
738 break;
739
740 case TGSI_TOKEN_TYPE_IMMEDIATE:
741 {
742 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
743 assert( size <= 4 );
744 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
745
746 for( i = 0; i < size; i++ ) {
747 mach->Imms[mach->ImmLimit][i] =
748 parse.FullToken.FullImmediate.u[i].Float;
749 }
750 mach->ImmLimit += 1;
751 }
752 break;
753
754 case TGSI_TOKEN_TYPE_INSTRUCTION:
755
756 /* save expanded instruction */
757 if (numInstructions == maxInstructions) {
758 instructions = REALLOC(instructions,
759 maxInstructions
760 * sizeof(struct tgsi_full_instruction),
761 (maxInstructions + 10)
762 * sizeof(struct tgsi_full_instruction));
763 maxInstructions += 10;
764 }
765
766 memcpy(instructions + numInstructions,
767 &parse.FullToken.FullInstruction,
768 sizeof(instructions[0]));
769
770 numInstructions++;
771 break;
772
773 case TGSI_TOKEN_TYPE_PROPERTY:
774 if (mach->Processor == TGSI_PROCESSOR_GEOMETRY) {
775 if (parse.FullToken.FullProperty.Property.PropertyName == TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES) {
776 mach->MaxOutputVertices = parse.FullToken.FullProperty.u[0].Data;
777 }
778 }
779 break;
780
781 default:
782 assert( 0 );
783 }
784 }
785 tgsi_parse_free (&parse);
786
787 FREE(mach->Declarations);
788 mach->Declarations = declarations;
789 mach->NumDeclarations = numDeclarations;
790
791 FREE(mach->Instructions);
792 mach->Instructions = instructions;
793 mach->NumInstructions = numInstructions;
794 }
795
796
797 struct tgsi_exec_machine *
798 tgsi_exec_machine_create( void )
799 {
800 struct tgsi_exec_machine *mach;
801 uint i;
802
803 mach = align_malloc( sizeof *mach, 16 );
804 if (!mach)
805 goto fail;
806
807 memset(mach, 0, sizeof(*mach));
808
809 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
810 mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
811 mach->Predicates = &mach->Temps[TGSI_EXEC_TEMP_P0];
812
813 mach->Inputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_INPUTS, 16);
814 mach->Outputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_OUTPUTS, 16);
815 if (!mach->Inputs || !mach->Outputs)
816 goto fail;
817
818 /* Setup constants needed by the SSE2 executor. */
819 for( i = 0; i < 4; i++ ) {
820 mach->Temps[TGSI_EXEC_TEMP_00000000_I].xyzw[TGSI_EXEC_TEMP_00000000_C].u[i] = 0x00000000;
821 mach->Temps[TGSI_EXEC_TEMP_7FFFFFFF_I].xyzw[TGSI_EXEC_TEMP_7FFFFFFF_C].u[i] = 0x7FFFFFFF;
822 mach->Temps[TGSI_EXEC_TEMP_80000000_I].xyzw[TGSI_EXEC_TEMP_80000000_C].u[i] = 0x80000000;
823 mach->Temps[TGSI_EXEC_TEMP_FFFFFFFF_I].xyzw[TGSI_EXEC_TEMP_FFFFFFFF_C].u[i] = 0xFFFFFFFF; /* not used */
824 mach->Temps[TGSI_EXEC_TEMP_ONE_I].xyzw[TGSI_EXEC_TEMP_ONE_C].f[i] = 1.0f;
825 mach->Temps[TGSI_EXEC_TEMP_TWO_I].xyzw[TGSI_EXEC_TEMP_TWO_C].f[i] = 2.0f; /* not used */
826 mach->Temps[TGSI_EXEC_TEMP_128_I].xyzw[TGSI_EXEC_TEMP_128_C].f[i] = 128.0f;
827 mach->Temps[TGSI_EXEC_TEMP_MINUS_128_I].xyzw[TGSI_EXEC_TEMP_MINUS_128_C].f[i] = -128.0f;
828 mach->Temps[TGSI_EXEC_TEMP_THREE_I].xyzw[TGSI_EXEC_TEMP_THREE_C].f[i] = 3.0f;
829 mach->Temps[TGSI_EXEC_TEMP_HALF_I].xyzw[TGSI_EXEC_TEMP_HALF_C].f[i] = 0.5f;
830 }
831
832 #ifdef DEBUG
833 /* silence warnings */
834 (void) print_chan;
835 (void) print_temp;
836 #endif
837
838 return mach;
839
840 fail:
841 if (mach) {
842 align_free(mach->Inputs);
843 align_free(mach->Outputs);
844 align_free(mach);
845 }
846 return NULL;
847 }
848
849
850 void
851 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
852 {
853 if (mach) {
854 FREE(mach->Instructions);
855 FREE(mach->Declarations);
856
857 align_free(mach->Inputs);
858 align_free(mach->Outputs);
859
860 align_free(mach);
861 }
862 }
863
864 static void
865 micro_add(union tgsi_exec_channel *dst,
866 const union tgsi_exec_channel *src0,
867 const union tgsi_exec_channel *src1)
868 {
869 dst->f[0] = src0->f[0] + src1->f[0];
870 dst->f[1] = src0->f[1] + src1->f[1];
871 dst->f[2] = src0->f[2] + src1->f[2];
872 dst->f[3] = src0->f[3] + src1->f[3];
873 }
874
875 static void
876 micro_div(
877 union tgsi_exec_channel *dst,
878 const union tgsi_exec_channel *src0,
879 const union tgsi_exec_channel *src1 )
880 {
881 if (src1->f[0] != 0) {
882 dst->f[0] = src0->f[0] / src1->f[0];
883 }
884 if (src1->f[1] != 0) {
885 dst->f[1] = src0->f[1] / src1->f[1];
886 }
887 if (src1->f[2] != 0) {
888 dst->f[2] = src0->f[2] / src1->f[2];
889 }
890 if (src1->f[3] != 0) {
891 dst->f[3] = src0->f[3] / src1->f[3];
892 }
893 }
894
895 static void
896 micro_lt(
897 union tgsi_exec_channel *dst,
898 const union tgsi_exec_channel *src0,
899 const union tgsi_exec_channel *src1,
900 const union tgsi_exec_channel *src2,
901 const union tgsi_exec_channel *src3 )
902 {
903 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
904 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
905 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
906 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
907 }
908
909 static void
910 micro_max(union tgsi_exec_channel *dst,
911 const union tgsi_exec_channel *src0,
912 const union tgsi_exec_channel *src1)
913 {
914 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
915 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
916 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
917 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
918 }
919
920 static void
921 micro_min(union tgsi_exec_channel *dst,
922 const union tgsi_exec_channel *src0,
923 const union tgsi_exec_channel *src1)
924 {
925 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
926 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
927 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
928 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
929 }
930
931 static void
932 micro_mul(union tgsi_exec_channel *dst,
933 const union tgsi_exec_channel *src0,
934 const union tgsi_exec_channel *src1)
935 {
936 dst->f[0] = src0->f[0] * src1->f[0];
937 dst->f[1] = src0->f[1] * src1->f[1];
938 dst->f[2] = src0->f[2] * src1->f[2];
939 dst->f[3] = src0->f[3] * src1->f[3];
940 }
941
942 static void
943 micro_neg(
944 union tgsi_exec_channel *dst,
945 const union tgsi_exec_channel *src )
946 {
947 dst->f[0] = -src->f[0];
948 dst->f[1] = -src->f[1];
949 dst->f[2] = -src->f[2];
950 dst->f[3] = -src->f[3];
951 }
952
953 static void
954 micro_pow(
955 union tgsi_exec_channel *dst,
956 const union tgsi_exec_channel *src0,
957 const union tgsi_exec_channel *src1 )
958 {
959 #if FAST_MATH
960 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
961 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
962 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
963 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
964 #else
965 dst->f[0] = powf( src0->f[0], src1->f[0] );
966 dst->f[1] = powf( src0->f[1], src1->f[1] );
967 dst->f[2] = powf( src0->f[2], src1->f[2] );
968 dst->f[3] = powf( src0->f[3], src1->f[3] );
969 #endif
970 }
971
972 static void
973 micro_sub(union tgsi_exec_channel *dst,
974 const union tgsi_exec_channel *src0,
975 const union tgsi_exec_channel *src1)
976 {
977 dst->f[0] = src0->f[0] - src1->f[0];
978 dst->f[1] = src0->f[1] - src1->f[1];
979 dst->f[2] = src0->f[2] - src1->f[2];
980 dst->f[3] = src0->f[3] - src1->f[3];
981 }
982
983 static void
984 fetch_src_file_channel(const struct tgsi_exec_machine *mach,
985 const uint chan_index,
986 const uint file,
987 const uint swizzle,
988 const union tgsi_exec_channel *index,
989 const union tgsi_exec_channel *index2D,
990 union tgsi_exec_channel *chan)
991 {
992 uint i;
993
994 assert(swizzle < 4);
995
996 switch (file) {
997 case TGSI_FILE_CONSTANT:
998 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
999 assert(index2D->i[i] >= 0 && index2D->i[i] < PIPE_MAX_CONSTANT_BUFFERS);
1000 assert(mach->Consts[index2D->i[i]]);
1001
1002 if (index->i[i] < 0) {
1003 chan->u[i] = 0;
1004 } else {
1005 /* NOTE: copying the const value as a uint instead of float */
1006 const uint constbuf = index2D->i[i];
1007 const uint *buf = (const uint *)mach->Consts[constbuf];
1008 const int pos = index->i[i] * 4 + swizzle;
1009 /* const buffer bounds check */
1010 if (pos < 0 || pos >= (int) mach->ConstsSize[constbuf]) {
1011 if (0) {
1012 /* Debug: print warning */
1013 static int count = 0;
1014 if (count++ < 100)
1015 debug_printf("TGSI Exec: const buffer index %d"
1016 " out of bounds\n", pos);
1017 }
1018 chan->u[i] = 0;
1019 }
1020 else
1021 chan->u[i] = buf[pos];
1022 }
1023 }
1024 break;
1025
1026 case TGSI_FILE_INPUT:
1027 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1028 /*
1029 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1030 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1031 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1032 index2D->i[i], index->i[i]);
1033 }*/
1034 int pos = index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i];
1035 assert(pos >= 0);
1036 assert(pos < TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS);
1037 chan->u[i] = mach->Inputs[pos].xyzw[swizzle].u[i];
1038 }
1039 break;
1040
1041 case TGSI_FILE_SYSTEM_VALUE:
1042 /* XXX no swizzling at this point. Will be needed if we put
1043 * gl_FragCoord, for example, in a sys value register.
1044 */
1045 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1046 chan->u[i] = mach->SystemValue[index->i[i]].u[i];
1047 }
1048 break;
1049
1050 case TGSI_FILE_TEMPORARY:
1051 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1052 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1053 assert(index2D->i[i] == 0);
1054
1055 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1056 }
1057 break;
1058
1059 case TGSI_FILE_IMMEDIATE:
1060 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1061 assert(index->i[i] >= 0 && index->i[i] < (int)mach->ImmLimit);
1062 assert(index2D->i[i] == 0);
1063
1064 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1065 }
1066 break;
1067
1068 case TGSI_FILE_ADDRESS:
1069 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1070 assert(index->i[i] >= 0);
1071 assert(index2D->i[i] == 0);
1072
1073 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1074 }
1075 break;
1076
1077 case TGSI_FILE_PREDICATE:
1078 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1079 assert(index->i[i] >= 0 && index->i[i] < TGSI_EXEC_NUM_PREDS);
1080 assert(index2D->i[i] == 0);
1081
1082 chan->u[i] = mach->Predicates[0].xyzw[swizzle].u[i];
1083 }
1084 break;
1085
1086 case TGSI_FILE_OUTPUT:
1087 /* vertex/fragment output vars can be read too */
1088 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1089 assert(index->i[i] >= 0);
1090 assert(index2D->i[i] == 0);
1091
1092 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1093 }
1094 break;
1095
1096 default:
1097 assert(0);
1098 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1099 chan->u[i] = 0;
1100 }
1101 }
1102 }
1103
1104 static void
1105 fetch_source(const struct tgsi_exec_machine *mach,
1106 union tgsi_exec_channel *chan,
1107 const struct tgsi_full_src_register *reg,
1108 const uint chan_index,
1109 enum tgsi_exec_datatype src_datatype)
1110 {
1111 union tgsi_exec_channel index;
1112 union tgsi_exec_channel index2D;
1113 uint swizzle;
1114
1115 /* We start with a direct index into a register file.
1116 *
1117 * file[1],
1118 * where:
1119 * file = Register.File
1120 * [1] = Register.Index
1121 */
1122 index.i[0] =
1123 index.i[1] =
1124 index.i[2] =
1125 index.i[3] = reg->Register.Index;
1126
1127 /* There is an extra source register that indirectly subscripts
1128 * a register file. The direct index now becomes an offset
1129 * that is being added to the indirect register.
1130 *
1131 * file[ind[2].x+1],
1132 * where:
1133 * ind = Indirect.File
1134 * [2] = Indirect.Index
1135 * .x = Indirect.SwizzleX
1136 */
1137 if (reg->Register.Indirect) {
1138 union tgsi_exec_channel index2;
1139 union tgsi_exec_channel indir_index;
1140 const uint execmask = mach->ExecMask;
1141 uint i;
1142
1143 /* which address register (always zero now) */
1144 index2.i[0] =
1145 index2.i[1] =
1146 index2.i[2] =
1147 index2.i[3] = reg->Indirect.Index;
1148 /* get current value of address register[swizzle] */
1149 swizzle = reg->Indirect.Swizzle;
1150 fetch_src_file_channel(mach,
1151 chan_index,
1152 reg->Indirect.File,
1153 swizzle,
1154 &index2,
1155 &ZeroVec,
1156 &indir_index);
1157
1158 /* add value of address register to the offset */
1159 index.i[0] += indir_index.i[0];
1160 index.i[1] += indir_index.i[1];
1161 index.i[2] += indir_index.i[2];
1162 index.i[3] += indir_index.i[3];
1163
1164 /* for disabled execution channels, zero-out the index to
1165 * avoid using a potential garbage value.
1166 */
1167 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1168 if ((execmask & (1 << i)) == 0)
1169 index.i[i] = 0;
1170 }
1171 }
1172
1173 /* There is an extra source register that is a second
1174 * subscript to a register file. Effectively it means that
1175 * the register file is actually a 2D array of registers.
1176 *
1177 * file[3][1],
1178 * where:
1179 * [3] = Dimension.Index
1180 */
1181 if (reg->Register.Dimension) {
1182 index2D.i[0] =
1183 index2D.i[1] =
1184 index2D.i[2] =
1185 index2D.i[3] = reg->Dimension.Index;
1186
1187 /* Again, the second subscript index can be addressed indirectly
1188 * identically to the first one.
1189 * Nothing stops us from indirectly addressing the indirect register,
1190 * but there is no need for that, so we won't exercise it.
1191 *
1192 * file[ind[4].y+3][1],
1193 * where:
1194 * ind = DimIndirect.File
1195 * [4] = DimIndirect.Index
1196 * .y = DimIndirect.SwizzleX
1197 */
1198 if (reg->Dimension.Indirect) {
1199 union tgsi_exec_channel index2;
1200 union tgsi_exec_channel indir_index;
1201 const uint execmask = mach->ExecMask;
1202 uint i;
1203
1204 index2.i[0] =
1205 index2.i[1] =
1206 index2.i[2] =
1207 index2.i[3] = reg->DimIndirect.Index;
1208
1209 swizzle = reg->DimIndirect.Swizzle;
1210 fetch_src_file_channel(mach,
1211 chan_index,
1212 reg->DimIndirect.File,
1213 swizzle,
1214 &index2,
1215 &ZeroVec,
1216 &indir_index);
1217
1218 index2D.i[0] += indir_index.i[0];
1219 index2D.i[1] += indir_index.i[1];
1220 index2D.i[2] += indir_index.i[2];
1221 index2D.i[3] += indir_index.i[3];
1222
1223 /* for disabled execution channels, zero-out the index to
1224 * avoid using a potential garbage value.
1225 */
1226 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1227 if ((execmask & (1 << i)) == 0) {
1228 index2D.i[i] = 0;
1229 }
1230 }
1231 }
1232
1233 /* If by any chance there was a need for a 3D array of register
1234 * files, we would have to check whether Dimension is followed
1235 * by a dimension register and continue the saga.
1236 */
1237 } else {
1238 index2D.i[0] =
1239 index2D.i[1] =
1240 index2D.i[2] =
1241 index2D.i[3] = 0;
1242 }
1243
1244 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1245 fetch_src_file_channel(mach,
1246 chan_index,
1247 reg->Register.File,
1248 swizzle,
1249 &index,
1250 &index2D,
1251 chan);
1252
1253 if (reg->Register.Absolute) {
1254 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1255 micro_abs(chan, chan);
1256 } else {
1257 micro_iabs(chan, chan);
1258 }
1259 }
1260
1261 if (reg->Register.Negate) {
1262 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1263 micro_neg(chan, chan);
1264 } else {
1265 micro_ineg(chan, chan);
1266 }
1267 }
1268 }
1269
1270 static void
1271 store_dest(struct tgsi_exec_machine *mach,
1272 const union tgsi_exec_channel *chan,
1273 const struct tgsi_full_dst_register *reg,
1274 const struct tgsi_full_instruction *inst,
1275 uint chan_index,
1276 enum tgsi_exec_datatype dst_datatype)
1277 {
1278 uint i;
1279 union tgsi_exec_channel null;
1280 union tgsi_exec_channel *dst;
1281 union tgsi_exec_channel index2D;
1282 uint execmask = mach->ExecMask;
1283 int offset = 0; /* indirection offset */
1284 int index;
1285
1286 /* for debugging */
1287 if (0 && dst_datatype == TGSI_EXEC_DATA_FLOAT) {
1288 check_inf_or_nan(chan);
1289 }
1290
1291 /* There is an extra source register that indirectly subscripts
1292 * a register file. The direct index now becomes an offset
1293 * that is being added to the indirect register.
1294 *
1295 * file[ind[2].x+1],
1296 * where:
1297 * ind = Indirect.File
1298 * [2] = Indirect.Index
1299 * .x = Indirect.SwizzleX
1300 */
1301 if (reg->Register.Indirect) {
1302 union tgsi_exec_channel index;
1303 union tgsi_exec_channel indir_index;
1304 uint swizzle;
1305
1306 /* which address register (always zero for now) */
1307 index.i[0] =
1308 index.i[1] =
1309 index.i[2] =
1310 index.i[3] = reg->Indirect.Index;
1311
1312 /* get current value of address register[swizzle] */
1313 swizzle = reg->Indirect.Swizzle;
1314
1315 /* fetch values from the address/indirection register */
1316 fetch_src_file_channel(mach,
1317 chan_index,
1318 reg->Indirect.File,
1319 swizzle,
1320 &index,
1321 &ZeroVec,
1322 &indir_index);
1323
1324 /* save indirection offset */
1325 offset = indir_index.i[0];
1326 }
1327
1328 /* There is an extra source register that is a second
1329 * subscript to a register file. Effectively it means that
1330 * the register file is actually a 2D array of registers.
1331 *
1332 * file[3][1],
1333 * where:
1334 * [3] = Dimension.Index
1335 */
1336 if (reg->Register.Dimension) {
1337 index2D.i[0] =
1338 index2D.i[1] =
1339 index2D.i[2] =
1340 index2D.i[3] = reg->Dimension.Index;
1341
1342 /* Again, the second subscript index can be addressed indirectly
1343 * identically to the first one.
1344 * Nothing stops us from indirectly addressing the indirect register,
1345 * but there is no need for that, so we won't exercise it.
1346 *
1347 * file[ind[4].y+3][1],
1348 * where:
1349 * ind = DimIndirect.File
1350 * [4] = DimIndirect.Index
1351 * .y = DimIndirect.SwizzleX
1352 */
1353 if (reg->Dimension.Indirect) {
1354 union tgsi_exec_channel index2;
1355 union tgsi_exec_channel indir_index;
1356 const uint execmask = mach->ExecMask;
1357 unsigned swizzle;
1358 uint i;
1359
1360 index2.i[0] =
1361 index2.i[1] =
1362 index2.i[2] =
1363 index2.i[3] = reg->DimIndirect.Index;
1364
1365 swizzle = reg->DimIndirect.Swizzle;
1366 fetch_src_file_channel(mach,
1367 chan_index,
1368 reg->DimIndirect.File,
1369 swizzle,
1370 &index2,
1371 &ZeroVec,
1372 &indir_index);
1373
1374 index2D.i[0] += indir_index.i[0];
1375 index2D.i[1] += indir_index.i[1];
1376 index2D.i[2] += indir_index.i[2];
1377 index2D.i[3] += indir_index.i[3];
1378
1379 /* for disabled execution channels, zero-out the index to
1380 * avoid using a potential garbage value.
1381 */
1382 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1383 if ((execmask & (1 << i)) == 0) {
1384 index2D.i[i] = 0;
1385 }
1386 }
1387 }
1388
1389 /* If by any chance there was a need for a 3D array of register
1390 * files, we would have to check whether Dimension is followed
1391 * by a dimension register and continue the saga.
1392 */
1393 } else {
1394 index2D.i[0] =
1395 index2D.i[1] =
1396 index2D.i[2] =
1397 index2D.i[3] = 0;
1398 }
1399
1400 switch (reg->Register.File) {
1401 case TGSI_FILE_NULL:
1402 dst = &null;
1403 break;
1404
1405 case TGSI_FILE_OUTPUT:
1406 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1407 + reg->Register.Index;
1408 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1409 #if 0
1410 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1411 mach->NumOutputs, mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0],
1412 reg->Register.Index);
1413 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1414 debug_printf("STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1415 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1416 if (execmask & (1 << i))
1417 debug_printf("%f, ", chan->f[i]);
1418 debug_printf(")\n");
1419 }
1420 #endif
1421 break;
1422
1423 case TGSI_FILE_TEMPORARY:
1424 index = reg->Register.Index;
1425 assert( index < TGSI_EXEC_NUM_TEMPS );
1426 dst = &mach->Temps[offset + index].xyzw[chan_index];
1427 break;
1428
1429 case TGSI_FILE_ADDRESS:
1430 index = reg->Register.Index;
1431 dst = &mach->Addrs[index].xyzw[chan_index];
1432 break;
1433
1434 case TGSI_FILE_PREDICATE:
1435 index = reg->Register.Index;
1436 assert(index < TGSI_EXEC_NUM_PREDS);
1437 dst = &mach->Predicates[index].xyzw[chan_index];
1438 break;
1439
1440 default:
1441 assert( 0 );
1442 return;
1443 }
1444
1445 if (inst->Instruction.Predicate) {
1446 uint swizzle;
1447 union tgsi_exec_channel *pred;
1448
1449 switch (chan_index) {
1450 case TGSI_CHAN_X:
1451 swizzle = inst->Predicate.SwizzleX;
1452 break;
1453 case TGSI_CHAN_Y:
1454 swizzle = inst->Predicate.SwizzleY;
1455 break;
1456 case TGSI_CHAN_Z:
1457 swizzle = inst->Predicate.SwizzleZ;
1458 break;
1459 case TGSI_CHAN_W:
1460 swizzle = inst->Predicate.SwizzleW;
1461 break;
1462 default:
1463 assert(0);
1464 return;
1465 }
1466
1467 assert(inst->Predicate.Index == 0);
1468
1469 pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
1470
1471 if (inst->Predicate.Negate) {
1472 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1473 if (pred->u[i]) {
1474 execmask &= ~(1 << i);
1475 }
1476 }
1477 } else {
1478 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1479 if (!pred->u[i]) {
1480 execmask &= ~(1 << i);
1481 }
1482 }
1483 }
1484 }
1485
1486 switch (inst->Instruction.Saturate) {
1487 case TGSI_SAT_NONE:
1488 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1489 if (execmask & (1 << i))
1490 dst->i[i] = chan->i[i];
1491 break;
1492
1493 case TGSI_SAT_ZERO_ONE:
1494 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1495 if (execmask & (1 << i)) {
1496 if (chan->f[i] < 0.0f)
1497 dst->f[i] = 0.0f;
1498 else if (chan->f[i] > 1.0f)
1499 dst->f[i] = 1.0f;
1500 else
1501 dst->i[i] = chan->i[i];
1502 }
1503 break;
1504
1505 case TGSI_SAT_MINUS_PLUS_ONE:
1506 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1507 if (execmask & (1 << i)) {
1508 if (chan->f[i] < -1.0f)
1509 dst->f[i] = -1.0f;
1510 else if (chan->f[i] > 1.0f)
1511 dst->f[i] = 1.0f;
1512 else
1513 dst->i[i] = chan->i[i];
1514 }
1515 break;
1516
1517 default:
1518 assert( 0 );
1519 }
1520 }
1521
1522 #define FETCH(VAL,INDEX,CHAN)\
1523 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1524
1525 #define IFETCH(VAL,INDEX,CHAN)\
1526 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1527
1528
1529 /**
1530 * Execute ARB-style KIL which is predicated by a src register.
1531 * Kill fragment if any of the four values is less than zero.
1532 */
1533 static void
1534 exec_kill_if(struct tgsi_exec_machine *mach,
1535 const struct tgsi_full_instruction *inst)
1536 {
1537 uint uniquemask;
1538 uint chan_index;
1539 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1540 union tgsi_exec_channel r[1];
1541
1542 /* This mask stores component bits that were already tested. */
1543 uniquemask = 0;
1544
1545 for (chan_index = 0; chan_index < 4; chan_index++)
1546 {
1547 uint swizzle;
1548 uint i;
1549
1550 /* unswizzle channel */
1551 swizzle = tgsi_util_get_full_src_register_swizzle (
1552 &inst->Src[0],
1553 chan_index);
1554
1555 /* check if the component has not been already tested */
1556 if (uniquemask & (1 << swizzle))
1557 continue;
1558 uniquemask |= 1 << swizzle;
1559
1560 FETCH(&r[0], 0, chan_index);
1561 for (i = 0; i < 4; i++)
1562 if (r[0].f[i] < 0.0f)
1563 kilmask |= 1 << i;
1564 }
1565
1566 /* restrict to fragments currently executing */
1567 kilmask &= mach->ExecMask;
1568
1569 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1570 }
1571
1572 /**
1573 * Unconditional fragment kill/discard.
1574 */
1575 static void
1576 exec_kill(struct tgsi_exec_machine *mach,
1577 const struct tgsi_full_instruction *inst)
1578 {
1579 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1580
1581 /* kill fragment for all fragments currently executing */
1582 kilmask = mach->ExecMask;
1583 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1584 }
1585
1586 static void
1587 emit_vertex(struct tgsi_exec_machine *mach)
1588 {
1589 /* FIXME: check for exec mask correctly
1590 unsigned i;
1591 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1592 if ((mach->ExecMask & (1 << i)))
1593 */
1594 if (mach->ExecMask) {
1595 if (mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]] >= mach->MaxOutputVertices)
1596 return;
1597
1598 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += mach->NumOutputs;
1599 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
1600 }
1601 }
1602
1603 static void
1604 emit_primitive(struct tgsi_exec_machine *mach)
1605 {
1606 unsigned *prim_count = &mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0];
1607 /* FIXME: check for exec mask correctly
1608 unsigned i;
1609 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1610 if ((mach->ExecMask & (1 << i)))
1611 */
1612 if (mach->ExecMask) {
1613 ++(*prim_count);
1614 debug_assert((*prim_count * mach->NumOutputs) < mach->MaxGeometryShaderOutputs);
1615 mach->Primitives[*prim_count] = 0;
1616 }
1617 }
1618
1619 static void
1620 conditional_emit_primitive(struct tgsi_exec_machine *mach)
1621 {
1622 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1623 int emitted_verts =
1624 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]];
1625 if (emitted_verts) {
1626 emit_primitive(mach);
1627 }
1628 }
1629 }
1630
1631
1632 /*
1633 * Fetch four texture samples using STR texture coordinates.
1634 */
1635 static void
1636 fetch_texel( struct tgsi_sampler *sampler,
1637 const unsigned sview_idx,
1638 const unsigned sampler_idx,
1639 const union tgsi_exec_channel *s,
1640 const union tgsi_exec_channel *t,
1641 const union tgsi_exec_channel *p,
1642 const union tgsi_exec_channel *c0,
1643 const union tgsi_exec_channel *c1,
1644 float derivs[3][2][TGSI_QUAD_SIZE],
1645 const int8_t offset[3],
1646 enum tgsi_sampler_control control,
1647 union tgsi_exec_channel *r,
1648 union tgsi_exec_channel *g,
1649 union tgsi_exec_channel *b,
1650 union tgsi_exec_channel *a )
1651 {
1652 uint j;
1653 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
1654
1655 /* FIXME: handle explicit derivs, offsets */
1656 sampler->get_samples(sampler, sview_idx, sampler_idx,
1657 s->f, t->f, p->f, c0->f, c1->f, derivs, offset, control, rgba);
1658
1659 for (j = 0; j < 4; j++) {
1660 r->f[j] = rgba[0][j];
1661 g->f[j] = rgba[1][j];
1662 b->f[j] = rgba[2][j];
1663 a->f[j] = rgba[3][j];
1664 }
1665 }
1666
1667
1668 #define TEX_MODIFIER_NONE 0
1669 #define TEX_MODIFIER_PROJECTED 1
1670 #define TEX_MODIFIER_LOD_BIAS 2
1671 #define TEX_MODIFIER_EXPLICIT_LOD 3
1672 #define TEX_MODIFIER_LEVEL_ZERO 4
1673
1674
1675 /*
1676 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
1677 */
1678 static void
1679 fetch_texel_offsets(struct tgsi_exec_machine *mach,
1680 const struct tgsi_full_instruction *inst,
1681 int8_t offsets[3])
1682 {
1683 if (inst->Texture.NumOffsets == 1) {
1684 union tgsi_exec_channel index;
1685 union tgsi_exec_channel offset[3];
1686 index.i[0] = index.i[1] = index.i[2] = index.i[3] = inst->TexOffsets[0].Index;
1687 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1688 inst->TexOffsets[0].SwizzleX, &index, &ZeroVec, &offset[0]);
1689 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1690 inst->TexOffsets[0].SwizzleY, &index, &ZeroVec, &offset[1]);
1691 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1692 inst->TexOffsets[0].SwizzleZ, &index, &ZeroVec, &offset[2]);
1693 offsets[0] = offset[0].i[0];
1694 offsets[1] = offset[1].i[0];
1695 offsets[2] = offset[2].i[0];
1696 } else {
1697 assert(inst->Texture.NumOffsets == 0);
1698 offsets[0] = offsets[1] = offsets[2] = 0;
1699 }
1700 }
1701
1702
1703 /*
1704 * Fetch dx and dy values for one channel (s, t or r).
1705 * Put dx values into one float array, dy values into another.
1706 */
1707 static void
1708 fetch_assign_deriv_channel(struct tgsi_exec_machine *mach,
1709 const struct tgsi_full_instruction *inst,
1710 unsigned regdsrcx,
1711 unsigned chan,
1712 float derivs[2][TGSI_QUAD_SIZE])
1713 {
1714 union tgsi_exec_channel d;
1715 FETCH(&d, regdsrcx, chan);
1716 derivs[0][0] = d.f[0];
1717 derivs[0][1] = d.f[1];
1718 derivs[0][2] = d.f[2];
1719 derivs[0][3] = d.f[3];
1720 FETCH(&d, regdsrcx + 1, chan);
1721 derivs[1][0] = d.f[0];
1722 derivs[1][1] = d.f[1];
1723 derivs[1][2] = d.f[2];
1724 derivs[1][3] = d.f[3];
1725 }
1726
1727
1728 /*
1729 * execute a texture instruction.
1730 *
1731 * modifier is used to control the channel routing for the\
1732 * instruction variants like proj, lod, and texture with lod bias.
1733 * sampler indicates which src register the sampler is contained in.
1734 */
1735 static void
1736 exec_tex(struct tgsi_exec_machine *mach,
1737 const struct tgsi_full_instruction *inst,
1738 uint modifier, uint sampler)
1739 {
1740 const uint unit = inst->Src[sampler].Register.Index;
1741 const union tgsi_exec_channel *args[5], *proj = NULL;
1742 union tgsi_exec_channel r[5];
1743 enum tgsi_sampler_control control = tgsi_sampler_lod_none;
1744 uint chan;
1745 int8_t offsets[3];
1746 int dim, shadow_ref, i;
1747
1748 /* always fetch all 3 offsets, overkill but keeps code simple */
1749 fetch_texel_offsets(mach, inst, offsets);
1750
1751 assert(modifier != TEX_MODIFIER_LEVEL_ZERO);
1752 assert(inst->Texture.Texture != TGSI_TEXTURE_BUFFER);
1753
1754 dim = tgsi_util_get_texture_coord_dim(inst->Texture.Texture, &shadow_ref);
1755
1756 assert(dim <= 4);
1757 if (shadow_ref >= 0)
1758 assert(shadow_ref >= dim && shadow_ref < Elements(args));
1759
1760 /* fetch modifier to the last argument */
1761 if (modifier != TEX_MODIFIER_NONE) {
1762 const int last = Elements(args) - 1;
1763
1764 /* fetch modifier from src0.w or src1.x */
1765 if (sampler == 1) {
1766 assert(dim <= TGSI_CHAN_W && shadow_ref != TGSI_CHAN_W);
1767 FETCH(&r[last], 0, TGSI_CHAN_W);
1768 }
1769 else {
1770 assert(shadow_ref != 4);
1771 FETCH(&r[last], 1, TGSI_CHAN_X);
1772 }
1773
1774 if (modifier != TEX_MODIFIER_PROJECTED) {
1775 args[last] = &r[last];
1776 }
1777 else {
1778 proj = &r[last];
1779 args[last] = &ZeroVec;
1780 }
1781
1782 /* point unused arguments to zero vector */
1783 for (i = dim; i < last; i++)
1784 args[i] = &ZeroVec;
1785
1786 if (modifier == TEX_MODIFIER_EXPLICIT_LOD)
1787 control = tgsi_sampler_lod_explicit;
1788 else if (modifier == TEX_MODIFIER_LOD_BIAS)
1789 control = tgsi_sampler_lod_bias;
1790 }
1791 else {
1792 for (i = dim; i < Elements(args); i++)
1793 args[i] = &ZeroVec;
1794 }
1795
1796 /* fetch coordinates */
1797 for (i = 0; i < dim; i++) {
1798 FETCH(&r[i], 0, TGSI_CHAN_X + i);
1799
1800 if (proj)
1801 micro_div(&r[i], &r[i], proj);
1802
1803 args[i] = &r[i];
1804 }
1805
1806 /* fetch reference value */
1807 if (shadow_ref >= 0) {
1808 FETCH(&r[shadow_ref], shadow_ref / 4, TGSI_CHAN_X + (shadow_ref % 4));
1809
1810 if (proj)
1811 micro_div(&r[shadow_ref], &r[shadow_ref], proj);
1812
1813 args[shadow_ref] = &r[shadow_ref];
1814 }
1815
1816 fetch_texel(mach->Sampler, unit, unit,
1817 args[0], args[1], args[2], args[3], args[4],
1818 NULL, offsets, control,
1819 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1820
1821 #if 0
1822 debug_printf("fetch r: %g %g %g %g\n",
1823 r[0].f[0], r[0].f[1], r[0].f[2], r[0].f[3]);
1824 debug_printf("fetch g: %g %g %g %g\n",
1825 r[1].f[0], r[1].f[1], r[1].f[2], r[1].f[3]);
1826 debug_printf("fetch b: %g %g %g %g\n",
1827 r[2].f[0], r[2].f[1], r[2].f[2], r[2].f[3]);
1828 debug_printf("fetch a: %g %g %g %g\n",
1829 r[3].f[0], r[3].f[1], r[3].f[2], r[3].f[3]);
1830 #endif
1831
1832 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1833 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1834 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1835 }
1836 }
1837 }
1838
1839
1840 static void
1841 exec_txd(struct tgsi_exec_machine *mach,
1842 const struct tgsi_full_instruction *inst)
1843 {
1844 const uint unit = inst->Src[3].Register.Index;
1845 union tgsi_exec_channel r[4];
1846 float derivs[3][2][TGSI_QUAD_SIZE];
1847 uint chan;
1848 int8_t offsets[3];
1849
1850 /* always fetch all 3 offsets, overkill but keeps code simple */
1851 fetch_texel_offsets(mach, inst, offsets);
1852
1853 switch (inst->Texture.Texture) {
1854 case TGSI_TEXTURE_1D:
1855 FETCH(&r[0], 0, TGSI_CHAN_X);
1856
1857 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1858
1859 fetch_texel(mach->Sampler, unit, unit,
1860 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
1861 derivs, offsets, tgsi_sampler_derivs_explicit,
1862 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1863 break;
1864
1865 case TGSI_TEXTURE_SHADOW1D:
1866 case TGSI_TEXTURE_1D_ARRAY:
1867 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1868 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
1869 FETCH(&r[0], 0, TGSI_CHAN_X);
1870 FETCH(&r[1], 0, TGSI_CHAN_Y);
1871 FETCH(&r[2], 0, TGSI_CHAN_Z);
1872
1873 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1874
1875 fetch_texel(mach->Sampler, unit, unit,
1876 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
1877 derivs, offsets, tgsi_sampler_derivs_explicit,
1878 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1879 break;
1880
1881 case TGSI_TEXTURE_2D:
1882 case TGSI_TEXTURE_RECT:
1883 FETCH(&r[0], 0, TGSI_CHAN_X);
1884 FETCH(&r[1], 0, TGSI_CHAN_Y);
1885
1886 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1887 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
1888
1889 fetch_texel(mach->Sampler, unit, unit,
1890 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
1891 derivs, offsets, tgsi_sampler_derivs_explicit,
1892 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1893 break;
1894
1895
1896 case TGSI_TEXTURE_SHADOW2D:
1897 case TGSI_TEXTURE_SHADOWRECT:
1898 case TGSI_TEXTURE_2D_ARRAY:
1899 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1900 /* only SHADOW2D_ARRAY actually needs W */
1901 FETCH(&r[0], 0, TGSI_CHAN_X);
1902 FETCH(&r[1], 0, TGSI_CHAN_Y);
1903 FETCH(&r[2], 0, TGSI_CHAN_Z);
1904 FETCH(&r[3], 0, TGSI_CHAN_W);
1905
1906 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1907 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
1908
1909 fetch_texel(mach->Sampler, unit, unit,
1910 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
1911 derivs, offsets, tgsi_sampler_derivs_explicit,
1912 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1913 break;
1914
1915 case TGSI_TEXTURE_3D:
1916 case TGSI_TEXTURE_CUBE:
1917 case TGSI_TEXTURE_CUBE_ARRAY:
1918 case TGSI_TEXTURE_SHADOWCUBE:
1919 /* only TEXTURE_CUBE_ARRAY and TEXTURE_SHADOWCUBE actually need W */
1920 FETCH(&r[0], 0, TGSI_CHAN_X);
1921 FETCH(&r[1], 0, TGSI_CHAN_Y);
1922 FETCH(&r[2], 0, TGSI_CHAN_Z);
1923 FETCH(&r[3], 0, TGSI_CHAN_W);
1924
1925 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1926 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
1927 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Z, derivs[2]);
1928
1929 fetch_texel(mach->Sampler, unit, unit,
1930 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
1931 derivs, offsets, tgsi_sampler_derivs_explicit,
1932 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1933 break;
1934
1935 default:
1936 assert(0);
1937 }
1938
1939 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1940 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1941 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1942 }
1943 }
1944 }
1945
1946
1947 static void
1948 exec_txf(struct tgsi_exec_machine *mach,
1949 const struct tgsi_full_instruction *inst)
1950 {
1951 const uint unit = inst->Src[1].Register.Index;
1952 union tgsi_exec_channel r[4];
1953 uint chan;
1954 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
1955 int j;
1956 int8_t offsets[3];
1957 unsigned target;
1958
1959 /* always fetch all 3 offsets, overkill but keeps code simple */
1960 fetch_texel_offsets(mach, inst, offsets);
1961
1962 IFETCH(&r[3], 0, TGSI_CHAN_W);
1963
1964 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I) {
1965 target = mach->SamplerViews[unit].Resource;
1966 }
1967 else {
1968 target = inst->Texture.Texture;
1969 }
1970 switch(target) {
1971 case TGSI_TEXTURE_3D:
1972 case TGSI_TEXTURE_2D_ARRAY:
1973 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1974 case TGSI_TEXTURE_2D_ARRAY_MSAA:
1975 IFETCH(&r[2], 0, TGSI_CHAN_Z);
1976 /* fallthrough */
1977 case TGSI_TEXTURE_2D:
1978 case TGSI_TEXTURE_RECT:
1979 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1980 case TGSI_TEXTURE_SHADOW2D:
1981 case TGSI_TEXTURE_SHADOWRECT:
1982 case TGSI_TEXTURE_1D_ARRAY:
1983 case TGSI_TEXTURE_2D_MSAA:
1984 IFETCH(&r[1], 0, TGSI_CHAN_Y);
1985 /* fallthrough */
1986 case TGSI_TEXTURE_BUFFER:
1987 case TGSI_TEXTURE_1D:
1988 case TGSI_TEXTURE_SHADOW1D:
1989 IFETCH(&r[0], 0, TGSI_CHAN_X);
1990 break;
1991 default:
1992 assert(0);
1993 break;
1994 }
1995
1996 mach->Sampler->get_texel(mach->Sampler, unit, r[0].i, r[1].i, r[2].i, r[3].i,
1997 offsets, rgba);
1998
1999 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
2000 r[0].f[j] = rgba[0][j];
2001 r[1].f[j] = rgba[1][j];
2002 r[2].f[j] = rgba[2][j];
2003 r[3].f[j] = rgba[3][j];
2004 }
2005
2006 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I) {
2007 unsigned char swizzles[4];
2008 swizzles[0] = inst->Src[1].Register.SwizzleX;
2009 swizzles[1] = inst->Src[1].Register.SwizzleY;
2010 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2011 swizzles[3] = inst->Src[1].Register.SwizzleW;
2012
2013 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2014 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2015 store_dest(mach, &r[swizzles[chan]],
2016 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2017 }
2018 }
2019 }
2020 else {
2021 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2022 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2023 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2024 }
2025 }
2026 }
2027 }
2028
2029 static void
2030 exec_txq(struct tgsi_exec_machine *mach,
2031 const struct tgsi_full_instruction *inst)
2032 {
2033 const uint unit = inst->Src[1].Register.Index;
2034 int result[4];
2035 union tgsi_exec_channel r[4], src;
2036 uint chan;
2037 int i,j;
2038
2039 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
2040
2041 /* XXX: This interface can't return per-pixel values */
2042 mach->Sampler->get_dims(mach->Sampler, unit, src.i[0], result);
2043
2044 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2045 for (j = 0; j < 4; j++) {
2046 r[j].i[i] = result[j];
2047 }
2048 }
2049
2050 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2051 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2052 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
2053 TGSI_EXEC_DATA_INT);
2054 }
2055 }
2056 }
2057
2058 static void
2059 exec_sample(struct tgsi_exec_machine *mach,
2060 const struct tgsi_full_instruction *inst,
2061 uint modifier, boolean compare)
2062 {
2063 const uint resource_unit = inst->Src[1].Register.Index;
2064 const uint sampler_unit = inst->Src[2].Register.Index;
2065 union tgsi_exec_channel r[4], c1;
2066 const union tgsi_exec_channel *lod = &ZeroVec;
2067 enum tgsi_sampler_control control = tgsi_sampler_lod_none;
2068 uint chan;
2069 unsigned char swizzles[4];
2070 int8_t offsets[3];
2071
2072 /* always fetch all 3 offsets, overkill but keeps code simple */
2073 fetch_texel_offsets(mach, inst, offsets);
2074
2075 assert(modifier != TEX_MODIFIER_PROJECTED);
2076
2077 if (modifier != TEX_MODIFIER_NONE) {
2078 if (modifier == TEX_MODIFIER_LOD_BIAS) {
2079 FETCH(&c1, 3, TGSI_CHAN_X);
2080 lod = &c1;
2081 control = tgsi_sampler_lod_bias;
2082 }
2083 else if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
2084 FETCH(&c1, 3, TGSI_CHAN_X);
2085 lod = &c1;
2086 control = tgsi_sampler_lod_explicit;
2087 }
2088 else {
2089 assert(modifier == TEX_MODIFIER_LEVEL_ZERO);
2090 control = tgsi_sampler_lod_zero;
2091 }
2092 }
2093
2094 FETCH(&r[0], 0, TGSI_CHAN_X);
2095
2096 switch (mach->SamplerViews[resource_unit].Resource) {
2097 case TGSI_TEXTURE_1D:
2098 if (compare) {
2099 FETCH(&r[2], 3, TGSI_CHAN_X);
2100 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2101 &r[0], &ZeroVec, &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2102 NULL, offsets, control,
2103 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2104 }
2105 else {
2106 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2107 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2108 NULL, offsets, control,
2109 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2110 }
2111 break;
2112
2113 case TGSI_TEXTURE_1D_ARRAY:
2114 case TGSI_TEXTURE_2D:
2115 case TGSI_TEXTURE_RECT:
2116 FETCH(&r[1], 0, TGSI_CHAN_Y);
2117 if (compare) {
2118 FETCH(&r[2], 3, TGSI_CHAN_X);
2119 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2120 &r[0], &r[1], &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2121 NULL, offsets, control,
2122 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2123 }
2124 else {
2125 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2126 &r[0], &r[1], &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2127 NULL, offsets, control,
2128 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2129 }
2130 break;
2131
2132 case TGSI_TEXTURE_2D_ARRAY:
2133 case TGSI_TEXTURE_3D:
2134 case TGSI_TEXTURE_CUBE:
2135 FETCH(&r[1], 0, TGSI_CHAN_Y);
2136 FETCH(&r[2], 0, TGSI_CHAN_Z);
2137 if(compare) {
2138 FETCH(&r[3], 3, TGSI_CHAN_X);
2139 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2140 &r[0], &r[1], &r[2], &r[3], lod,
2141 NULL, offsets, control,
2142 &r[0], &r[1], &r[2], &r[3]);
2143 }
2144 else {
2145 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2146 &r[0], &r[1], &r[2], &ZeroVec, lod,
2147 NULL, offsets, control,
2148 &r[0], &r[1], &r[2], &r[3]);
2149 }
2150 break;
2151
2152 case TGSI_TEXTURE_CUBE_ARRAY:
2153 FETCH(&r[1], 0, TGSI_CHAN_Y);
2154 FETCH(&r[2], 0, TGSI_CHAN_Z);
2155 FETCH(&r[3], 0, TGSI_CHAN_W);
2156 if(compare) {
2157 FETCH(&r[4], 3, TGSI_CHAN_X);
2158 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2159 &r[0], &r[1], &r[2], &r[3], &r[4],
2160 NULL, offsets, control,
2161 &r[0], &r[1], &r[2], &r[3]);
2162 }
2163 else {
2164 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2165 &r[0], &r[1], &r[2], &r[3], lod,
2166 NULL, offsets, control,
2167 &r[0], &r[1], &r[2], &r[3]);
2168 }
2169 break;
2170
2171
2172 default:
2173 assert(0);
2174 }
2175
2176 swizzles[0] = inst->Src[1].Register.SwizzleX;
2177 swizzles[1] = inst->Src[1].Register.SwizzleY;
2178 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2179 swizzles[3] = inst->Src[1].Register.SwizzleW;
2180
2181 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2182 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2183 store_dest(mach, &r[swizzles[chan]],
2184 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2185 }
2186 }
2187 }
2188
2189 static void
2190 exec_sample_d(struct tgsi_exec_machine *mach,
2191 const struct tgsi_full_instruction *inst)
2192 {
2193 const uint resource_unit = inst->Src[1].Register.Index;
2194 const uint sampler_unit = inst->Src[2].Register.Index;
2195 union tgsi_exec_channel r[4];
2196 float derivs[3][2][TGSI_QUAD_SIZE];
2197 uint chan;
2198 unsigned char swizzles[4];
2199 int8_t offsets[3];
2200
2201 /* always fetch all 3 offsets, overkill but keeps code simple */
2202 fetch_texel_offsets(mach, inst, offsets);
2203
2204 FETCH(&r[0], 0, TGSI_CHAN_X);
2205
2206 switch (mach->SamplerViews[resource_unit].Resource) {
2207 case TGSI_TEXTURE_1D:
2208 case TGSI_TEXTURE_1D_ARRAY:
2209 /* only 1D array actually needs Y */
2210 FETCH(&r[1], 0, TGSI_CHAN_Y);
2211
2212 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2213
2214 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2215 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2216 derivs, offsets, tgsi_sampler_derivs_explicit,
2217 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2218 break;
2219
2220 case TGSI_TEXTURE_2D:
2221 case TGSI_TEXTURE_RECT:
2222 case TGSI_TEXTURE_2D_ARRAY:
2223 /* only 2D array actually needs Z */
2224 FETCH(&r[1], 0, TGSI_CHAN_Y);
2225 FETCH(&r[2], 0, TGSI_CHAN_Z);
2226
2227 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2228 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2229
2230 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2231 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* inputs */
2232 derivs, offsets, tgsi_sampler_derivs_explicit,
2233 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2234 break;
2235
2236 case TGSI_TEXTURE_3D:
2237 case TGSI_TEXTURE_CUBE:
2238 case TGSI_TEXTURE_CUBE_ARRAY:
2239 /* only cube array actually needs W */
2240 FETCH(&r[1], 0, TGSI_CHAN_Y);
2241 FETCH(&r[2], 0, TGSI_CHAN_Z);
2242 FETCH(&r[3], 0, TGSI_CHAN_W);
2243
2244 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2245 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2246 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Z, derivs[2]);
2247
2248 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2249 &r[0], &r[1], &r[2], &r[3], &ZeroVec,
2250 derivs, offsets, tgsi_sampler_derivs_explicit,
2251 &r[0], &r[1], &r[2], &r[3]);
2252 break;
2253
2254 default:
2255 assert(0);
2256 }
2257
2258 swizzles[0] = inst->Src[1].Register.SwizzleX;
2259 swizzles[1] = inst->Src[1].Register.SwizzleY;
2260 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2261 swizzles[3] = inst->Src[1].Register.SwizzleW;
2262
2263 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2264 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2265 store_dest(mach, &r[swizzles[chan]],
2266 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2267 }
2268 }
2269 }
2270
2271
2272 /**
2273 * Evaluate a constant-valued coefficient at the position of the
2274 * current quad.
2275 */
2276 static void
2277 eval_constant_coef(
2278 struct tgsi_exec_machine *mach,
2279 unsigned attrib,
2280 unsigned chan )
2281 {
2282 unsigned i;
2283
2284 for( i = 0; i < TGSI_QUAD_SIZE; i++ ) {
2285 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
2286 }
2287 }
2288
2289 /**
2290 * Evaluate a linear-valued coefficient at the position of the
2291 * current quad.
2292 */
2293 static void
2294 eval_linear_coef(
2295 struct tgsi_exec_machine *mach,
2296 unsigned attrib,
2297 unsigned chan )
2298 {
2299 const float x = mach->QuadPos.xyzw[0].f[0];
2300 const float y = mach->QuadPos.xyzw[1].f[0];
2301 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2302 const float dady = mach->InterpCoefs[attrib].dady[chan];
2303 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2304 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
2305 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
2306 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
2307 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
2308 }
2309
2310 /**
2311 * Evaluate a perspective-valued coefficient at the position of the
2312 * current quad.
2313 */
2314 static void
2315 eval_perspective_coef(
2316 struct tgsi_exec_machine *mach,
2317 unsigned attrib,
2318 unsigned chan )
2319 {
2320 const float x = mach->QuadPos.xyzw[0].f[0];
2321 const float y = mach->QuadPos.xyzw[1].f[0];
2322 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2323 const float dady = mach->InterpCoefs[attrib].dady[chan];
2324 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2325 const float *w = mach->QuadPos.xyzw[3].f;
2326 /* divide by W here */
2327 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
2328 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
2329 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
2330 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
2331 }
2332
2333
2334 typedef void (* eval_coef_func)(
2335 struct tgsi_exec_machine *mach,
2336 unsigned attrib,
2337 unsigned chan );
2338
2339 static void
2340 exec_declaration(struct tgsi_exec_machine *mach,
2341 const struct tgsi_full_declaration *decl)
2342 {
2343 if (decl->Declaration.File == TGSI_FILE_SAMPLER_VIEW) {
2344 mach->SamplerViews[decl->Range.First] = decl->SamplerView;
2345 return;
2346 }
2347
2348 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
2349 if (decl->Declaration.File == TGSI_FILE_INPUT) {
2350 uint first, last, mask;
2351
2352 first = decl->Range.First;
2353 last = decl->Range.Last;
2354 mask = decl->Declaration.UsageMask;
2355
2356 /* XXX we could remove this special-case code since
2357 * mach->InterpCoefs[first].a0 should already have the
2358 * front/back-face value. But we should first update the
2359 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2360 * Then, we could remove the tgsi_exec_machine::Face field.
2361 */
2362 /* XXX make FACE a system value */
2363 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
2364 uint i;
2365
2366 assert(decl->Semantic.Index == 0);
2367 assert(first == last);
2368
2369 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2370 mach->Inputs[first].xyzw[0].f[i] = mach->Face;
2371 }
2372 } else {
2373 eval_coef_func eval;
2374 uint i, j;
2375
2376 switch (decl->Interp.Interpolate) {
2377 case TGSI_INTERPOLATE_CONSTANT:
2378 eval = eval_constant_coef;
2379 break;
2380
2381 case TGSI_INTERPOLATE_LINEAR:
2382 eval = eval_linear_coef;
2383 break;
2384
2385 case TGSI_INTERPOLATE_PERSPECTIVE:
2386 eval = eval_perspective_coef;
2387 break;
2388
2389 case TGSI_INTERPOLATE_COLOR:
2390 eval = mach->flatshade_color ? eval_constant_coef : eval_perspective_coef;
2391 break;
2392
2393 default:
2394 assert(0);
2395 return;
2396 }
2397
2398 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2399 if (mask & (1 << j)) {
2400 for (i = first; i <= last; i++) {
2401 eval(mach, i, j);
2402 }
2403 }
2404 }
2405 }
2406
2407 if (DEBUG_EXECUTION) {
2408 uint i, j;
2409 for (i = first; i <= last; ++i) {
2410 debug_printf("IN[%2u] = ", i);
2411 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2412 if (j > 0) {
2413 debug_printf(" ");
2414 }
2415 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
2416 mach->Inputs[i].xyzw[0].f[j], mach->Inputs[i].xyzw[0].u[j],
2417 mach->Inputs[i].xyzw[1].f[j], mach->Inputs[i].xyzw[1].u[j],
2418 mach->Inputs[i].xyzw[2].f[j], mach->Inputs[i].xyzw[2].u[j],
2419 mach->Inputs[i].xyzw[3].f[j], mach->Inputs[i].xyzw[3].u[j]);
2420 }
2421 }
2422 }
2423 }
2424 }
2425
2426 if (decl->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
2427 mach->SysSemanticToIndex[decl->Declaration.Semantic] = decl->Range.First;
2428 }
2429 }
2430
2431 typedef void (* micro_unary_op)(union tgsi_exec_channel *dst,
2432 const union tgsi_exec_channel *src);
2433
2434 static void
2435 exec_scalar_unary(struct tgsi_exec_machine *mach,
2436 const struct tgsi_full_instruction *inst,
2437 micro_unary_op op,
2438 enum tgsi_exec_datatype dst_datatype,
2439 enum tgsi_exec_datatype src_datatype)
2440 {
2441 unsigned int chan;
2442 union tgsi_exec_channel src;
2443 union tgsi_exec_channel dst;
2444
2445 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, src_datatype);
2446 op(&dst, &src);
2447 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2448 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2449 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2450 }
2451 }
2452 }
2453
2454 static void
2455 exec_vector_unary(struct tgsi_exec_machine *mach,
2456 const struct tgsi_full_instruction *inst,
2457 micro_unary_op op,
2458 enum tgsi_exec_datatype dst_datatype,
2459 enum tgsi_exec_datatype src_datatype)
2460 {
2461 unsigned int chan;
2462 struct tgsi_exec_vector dst;
2463
2464 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2465 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2466 union tgsi_exec_channel src;
2467
2468 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
2469 op(&dst.xyzw[chan], &src);
2470 }
2471 }
2472 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2473 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2474 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2475 }
2476 }
2477 }
2478
2479 typedef void (* micro_binary_op)(union tgsi_exec_channel *dst,
2480 const union tgsi_exec_channel *src0,
2481 const union tgsi_exec_channel *src1);
2482
2483 static void
2484 exec_scalar_binary(struct tgsi_exec_machine *mach,
2485 const struct tgsi_full_instruction *inst,
2486 micro_binary_op op,
2487 enum tgsi_exec_datatype dst_datatype,
2488 enum tgsi_exec_datatype src_datatype)
2489 {
2490 unsigned int chan;
2491 union tgsi_exec_channel src[2];
2492 union tgsi_exec_channel dst;
2493
2494 fetch_source(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, src_datatype);
2495 fetch_source(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, src_datatype);
2496 op(&dst, &src[0], &src[1]);
2497 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2498 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2499 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2500 }
2501 }
2502 }
2503
2504 static void
2505 exec_vector_binary(struct tgsi_exec_machine *mach,
2506 const struct tgsi_full_instruction *inst,
2507 micro_binary_op op,
2508 enum tgsi_exec_datatype dst_datatype,
2509 enum tgsi_exec_datatype src_datatype)
2510 {
2511 unsigned int chan;
2512 struct tgsi_exec_vector dst;
2513
2514 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2515 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2516 union tgsi_exec_channel src[2];
2517
2518 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2519 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2520 op(&dst.xyzw[chan], &src[0], &src[1]);
2521 }
2522 }
2523 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2524 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2525 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2526 }
2527 }
2528 }
2529
2530 typedef void (* micro_trinary_op)(union tgsi_exec_channel *dst,
2531 const union tgsi_exec_channel *src0,
2532 const union tgsi_exec_channel *src1,
2533 const union tgsi_exec_channel *src2);
2534
2535 static void
2536 exec_vector_trinary(struct tgsi_exec_machine *mach,
2537 const struct tgsi_full_instruction *inst,
2538 micro_trinary_op op,
2539 enum tgsi_exec_datatype dst_datatype,
2540 enum tgsi_exec_datatype src_datatype)
2541 {
2542 unsigned int chan;
2543 struct tgsi_exec_vector dst;
2544
2545 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2546 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2547 union tgsi_exec_channel src[3];
2548
2549 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2550 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2551 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2552 op(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
2553 }
2554 }
2555 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2556 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2557 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2558 }
2559 }
2560 }
2561
2562 typedef void (* micro_quaternary_op)(union tgsi_exec_channel *dst,
2563 const union tgsi_exec_channel *src0,
2564 const union tgsi_exec_channel *src1,
2565 const union tgsi_exec_channel *src2,
2566 const union tgsi_exec_channel *src3);
2567
2568 static void
2569 exec_vector_quaternary(struct tgsi_exec_machine *mach,
2570 const struct tgsi_full_instruction *inst,
2571 micro_quaternary_op op,
2572 enum tgsi_exec_datatype dst_datatype,
2573 enum tgsi_exec_datatype src_datatype)
2574 {
2575 unsigned int chan;
2576 struct tgsi_exec_vector dst;
2577
2578 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2579 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2580 union tgsi_exec_channel src[4];
2581
2582 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2583 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2584 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2585 fetch_source(mach, &src[3], &inst->Src[3], chan, src_datatype);
2586 op(&dst.xyzw[chan], &src[0], &src[1], &src[2], &src[3]);
2587 }
2588 }
2589 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2590 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2591 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2592 }
2593 }
2594 }
2595
2596 static void
2597 exec_dp3(struct tgsi_exec_machine *mach,
2598 const struct tgsi_full_instruction *inst)
2599 {
2600 unsigned int chan;
2601 union tgsi_exec_channel arg[3];
2602
2603 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2604 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2605 micro_mul(&arg[2], &arg[0], &arg[1]);
2606
2607 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_Z; chan++) {
2608 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2609 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2610 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2611 }
2612
2613 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2614 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2615 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2616 }
2617 }
2618 }
2619
2620 static void
2621 exec_dp4(struct tgsi_exec_machine *mach,
2622 const struct tgsi_full_instruction *inst)
2623 {
2624 unsigned int chan;
2625 union tgsi_exec_channel arg[3];
2626
2627 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2628 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2629 micro_mul(&arg[2], &arg[0], &arg[1]);
2630
2631 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_W; chan++) {
2632 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2633 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2634 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2635 }
2636
2637 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2638 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2639 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2640 }
2641 }
2642 }
2643
2644 static void
2645 exec_dp2a(struct tgsi_exec_machine *mach,
2646 const struct tgsi_full_instruction *inst)
2647 {
2648 unsigned int chan;
2649 union tgsi_exec_channel arg[3];
2650
2651 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2652 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2653 micro_mul(&arg[2], &arg[0], &arg[1]);
2654
2655 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2656 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2657 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2658
2659 fetch_source(mach, &arg[1], &inst->Src[2], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2660 micro_add(&arg[0], &arg[0], &arg[1]);
2661
2662 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2663 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2664 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2665 }
2666 }
2667 }
2668
2669 static void
2670 exec_dph(struct tgsi_exec_machine *mach,
2671 const struct tgsi_full_instruction *inst)
2672 {
2673 unsigned int chan;
2674 union tgsi_exec_channel arg[3];
2675
2676 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2677 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2678 micro_mul(&arg[2], &arg[0], &arg[1]);
2679
2680 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2681 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2682 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2683
2684 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2685 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2686 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2687
2688 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2689 micro_add(&arg[0], &arg[0], &arg[1]);
2690
2691 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2692 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2693 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2694 }
2695 }
2696 }
2697
2698 static void
2699 exec_dp2(struct tgsi_exec_machine *mach,
2700 const struct tgsi_full_instruction *inst)
2701 {
2702 unsigned int chan;
2703 union tgsi_exec_channel arg[3];
2704
2705 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2706 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2707 micro_mul(&arg[2], &arg[0], &arg[1]);
2708
2709 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2710 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2711 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2712
2713 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2714 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2715 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2716 }
2717 }
2718 }
2719
2720 static void
2721 exec_scs(struct tgsi_exec_machine *mach,
2722 const struct tgsi_full_instruction *inst)
2723 {
2724 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) {
2725 union tgsi_exec_channel arg;
2726 union tgsi_exec_channel result;
2727
2728 fetch_source(mach, &arg, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2729
2730 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2731 micro_cos(&result, &arg);
2732 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2733 }
2734 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2735 micro_sin(&result, &arg);
2736 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2737 }
2738 }
2739 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2740 store_dest(mach, &ZeroVec, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2741 }
2742 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2743 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2744 }
2745 }
2746
2747 static void
2748 exec_xpd(struct tgsi_exec_machine *mach,
2749 const struct tgsi_full_instruction *inst)
2750 {
2751 union tgsi_exec_channel r[6];
2752 union tgsi_exec_channel d[3];
2753
2754 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2755 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2756
2757 micro_mul(&r[2], &r[0], &r[1]);
2758
2759 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2760 fetch_source(mach, &r[4], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2761
2762 micro_mul(&r[5], &r[3], &r[4] );
2763 micro_sub(&d[TGSI_CHAN_X], &r[2], &r[5]);
2764
2765 fetch_source(mach, &r[2], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2766
2767 micro_mul(&r[3], &r[3], &r[2]);
2768
2769 fetch_source(mach, &r[5], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2770
2771 micro_mul(&r[1], &r[1], &r[5]);
2772 micro_sub(&d[TGSI_CHAN_Y], &r[3], &r[1]);
2773
2774 micro_mul(&r[5], &r[5], &r[4]);
2775 micro_mul(&r[0], &r[0], &r[2]);
2776 micro_sub(&d[TGSI_CHAN_Z], &r[5], &r[0]);
2777
2778 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2779 store_dest(mach, &d[TGSI_CHAN_X], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2780 }
2781 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2782 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2783 }
2784 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2785 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2786 }
2787 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2788 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2789 }
2790 }
2791
2792 static void
2793 exec_dst(struct tgsi_exec_machine *mach,
2794 const struct tgsi_full_instruction *inst)
2795 {
2796 union tgsi_exec_channel r[2];
2797 union tgsi_exec_channel d[4];
2798
2799 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2800 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2801 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2802 micro_mul(&d[TGSI_CHAN_Y], &r[0], &r[1]);
2803 }
2804 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2805 fetch_source(mach, &d[TGSI_CHAN_Z], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2806 }
2807 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2808 fetch_source(mach, &d[TGSI_CHAN_W], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2809 }
2810
2811 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2812 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2813 }
2814 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2815 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2816 }
2817 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2818 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2819 }
2820 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2821 store_dest(mach, &d[TGSI_CHAN_W], &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2822 }
2823 }
2824
2825 static void
2826 exec_log(struct tgsi_exec_machine *mach,
2827 const struct tgsi_full_instruction *inst)
2828 {
2829 union tgsi_exec_channel r[3];
2830
2831 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2832 micro_abs(&r[2], &r[0]); /* r2 = abs(r0) */
2833 micro_lg2(&r[1], &r[2]); /* r1 = lg2(r2) */
2834 micro_flr(&r[0], &r[1]); /* r0 = floor(r1) */
2835 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2836 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2837 }
2838 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2839 micro_exp2(&r[0], &r[0]); /* r0 = 2 ^ r0 */
2840 micro_div(&r[0], &r[2], &r[0]); /* r0 = r2 / r0 */
2841 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2842 }
2843 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2844 store_dest(mach, &r[1], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2845 }
2846 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2847 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2848 }
2849 }
2850
2851 static void
2852 exec_exp(struct tgsi_exec_machine *mach,
2853 const struct tgsi_full_instruction *inst)
2854 {
2855 union tgsi_exec_channel r[3];
2856
2857 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2858 micro_flr(&r[1], &r[0]); /* r1 = floor(r0) */
2859 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2860 micro_exp2(&r[2], &r[1]); /* r2 = 2 ^ r1 */
2861 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2862 }
2863 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2864 micro_sub(&r[2], &r[0], &r[1]); /* r2 = r0 - r1 */
2865 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2866 }
2867 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2868 micro_exp2(&r[2], &r[0]); /* r2 = 2 ^ r0 */
2869 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2870 }
2871 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2872 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2873 }
2874 }
2875
2876 static void
2877 exec_lit(struct tgsi_exec_machine *mach,
2878 const struct tgsi_full_instruction *inst)
2879 {
2880 union tgsi_exec_channel r[3];
2881 union tgsi_exec_channel d[3];
2882
2883 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YZ) {
2884 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2885 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2886 fetch_source(mach, &r[1], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2887 micro_max(&r[1], &r[1], &ZeroVec);
2888
2889 fetch_source(mach, &r[2], &inst->Src[0], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2890 micro_min(&r[2], &r[2], &P128Vec);
2891 micro_max(&r[2], &r[2], &M128Vec);
2892 micro_pow(&r[1], &r[1], &r[2]);
2893 micro_lt(&d[TGSI_CHAN_Z], &ZeroVec, &r[0], &r[1], &ZeroVec);
2894 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2895 }
2896 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2897 micro_max(&d[TGSI_CHAN_Y], &r[0], &ZeroVec);
2898 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2899 }
2900 }
2901 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2902 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2903 }
2904
2905 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2906 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2907 }
2908 }
2909
2910 static void
2911 exec_break(struct tgsi_exec_machine *mach)
2912 {
2913 if (mach->BreakType == TGSI_EXEC_BREAK_INSIDE_LOOP) {
2914 /* turn off loop channels for each enabled exec channel */
2915 mach->LoopMask &= ~mach->ExecMask;
2916 /* Todo: if mach->LoopMask == 0, jump to end of loop */
2917 UPDATE_EXEC_MASK(mach);
2918 } else {
2919 assert(mach->BreakType == TGSI_EXEC_BREAK_INSIDE_SWITCH);
2920
2921 mach->Switch.mask = 0x0;
2922
2923 UPDATE_EXEC_MASK(mach);
2924 }
2925 }
2926
2927 static void
2928 exec_switch(struct tgsi_exec_machine *mach,
2929 const struct tgsi_full_instruction *inst)
2930 {
2931 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
2932 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
2933
2934 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
2935 fetch_source(mach, &mach->Switch.selector, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
2936 mach->Switch.mask = 0x0;
2937 mach->Switch.defaultMask = 0x0;
2938
2939 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
2940 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_SWITCH;
2941
2942 UPDATE_EXEC_MASK(mach);
2943 }
2944
2945 static void
2946 exec_case(struct tgsi_exec_machine *mach,
2947 const struct tgsi_full_instruction *inst)
2948 {
2949 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
2950 union tgsi_exec_channel src;
2951 uint mask = 0;
2952
2953 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
2954
2955 if (mach->Switch.selector.u[0] == src.u[0]) {
2956 mask |= 0x1;
2957 }
2958 if (mach->Switch.selector.u[1] == src.u[1]) {
2959 mask |= 0x2;
2960 }
2961 if (mach->Switch.selector.u[2] == src.u[2]) {
2962 mask |= 0x4;
2963 }
2964 if (mach->Switch.selector.u[3] == src.u[3]) {
2965 mask |= 0x8;
2966 }
2967
2968 mach->Switch.defaultMask |= mask;
2969
2970 mach->Switch.mask |= mask & prevMask;
2971
2972 UPDATE_EXEC_MASK(mach);
2973 }
2974
2975 /* FIXME: this will only work if default is last */
2976 static void
2977 exec_default(struct tgsi_exec_machine *mach)
2978 {
2979 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
2980
2981 mach->Switch.mask |= ~mach->Switch.defaultMask & prevMask;
2982
2983 UPDATE_EXEC_MASK(mach);
2984 }
2985
2986 static void
2987 exec_endswitch(struct tgsi_exec_machine *mach)
2988 {
2989 mach->Switch = mach->SwitchStack[--mach->SwitchStackTop];
2990 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
2991
2992 UPDATE_EXEC_MASK(mach);
2993 }
2994
2995 static void
2996 micro_i2f(union tgsi_exec_channel *dst,
2997 const union tgsi_exec_channel *src)
2998 {
2999 dst->f[0] = (float)src->i[0];
3000 dst->f[1] = (float)src->i[1];
3001 dst->f[2] = (float)src->i[2];
3002 dst->f[3] = (float)src->i[3];
3003 }
3004
3005 static void
3006 micro_not(union tgsi_exec_channel *dst,
3007 const union tgsi_exec_channel *src)
3008 {
3009 dst->u[0] = ~src->u[0];
3010 dst->u[1] = ~src->u[1];
3011 dst->u[2] = ~src->u[2];
3012 dst->u[3] = ~src->u[3];
3013 }
3014
3015 static void
3016 micro_shl(union tgsi_exec_channel *dst,
3017 const union tgsi_exec_channel *src0,
3018 const union tgsi_exec_channel *src1)
3019 {
3020 unsigned masked_count;
3021 masked_count = src1->u[0] & 0x1f;
3022 dst->u[0] = src0->u[0] << masked_count;
3023 masked_count = src1->u[1] & 0x1f;
3024 dst->u[1] = src0->u[1] << masked_count;
3025 masked_count = src1->u[2] & 0x1f;
3026 dst->u[2] = src0->u[2] << masked_count;
3027 masked_count = src1->u[3] & 0x1f;
3028 dst->u[3] = src0->u[3] << masked_count;
3029 }
3030
3031 static void
3032 micro_and(union tgsi_exec_channel *dst,
3033 const union tgsi_exec_channel *src0,
3034 const union tgsi_exec_channel *src1)
3035 {
3036 dst->u[0] = src0->u[0] & src1->u[0];
3037 dst->u[1] = src0->u[1] & src1->u[1];
3038 dst->u[2] = src0->u[2] & src1->u[2];
3039 dst->u[3] = src0->u[3] & src1->u[3];
3040 }
3041
3042 static void
3043 micro_or(union tgsi_exec_channel *dst,
3044 const union tgsi_exec_channel *src0,
3045 const union tgsi_exec_channel *src1)
3046 {
3047 dst->u[0] = src0->u[0] | src1->u[0];
3048 dst->u[1] = src0->u[1] | src1->u[1];
3049 dst->u[2] = src0->u[2] | src1->u[2];
3050 dst->u[3] = src0->u[3] | src1->u[3];
3051 }
3052
3053 static void
3054 micro_xor(union tgsi_exec_channel *dst,
3055 const union tgsi_exec_channel *src0,
3056 const union tgsi_exec_channel *src1)
3057 {
3058 dst->u[0] = src0->u[0] ^ src1->u[0];
3059 dst->u[1] = src0->u[1] ^ src1->u[1];
3060 dst->u[2] = src0->u[2] ^ src1->u[2];
3061 dst->u[3] = src0->u[3] ^ src1->u[3];
3062 }
3063
3064 static void
3065 micro_mod(union tgsi_exec_channel *dst,
3066 const union tgsi_exec_channel *src0,
3067 const union tgsi_exec_channel *src1)
3068 {
3069 dst->i[0] = src0->i[0] % src1->i[0];
3070 dst->i[1] = src0->i[1] % src1->i[1];
3071 dst->i[2] = src0->i[2] % src1->i[2];
3072 dst->i[3] = src0->i[3] % src1->i[3];
3073 }
3074
3075 static void
3076 micro_f2i(union tgsi_exec_channel *dst,
3077 const union tgsi_exec_channel *src)
3078 {
3079 dst->i[0] = (int)src->f[0];
3080 dst->i[1] = (int)src->f[1];
3081 dst->i[2] = (int)src->f[2];
3082 dst->i[3] = (int)src->f[3];
3083 }
3084
3085 static void
3086 micro_fseq(union tgsi_exec_channel *dst,
3087 const union tgsi_exec_channel *src0,
3088 const union tgsi_exec_channel *src1)
3089 {
3090 dst->u[0] = src0->f[0] == src1->f[0] ? ~0 : 0;
3091 dst->u[1] = src0->f[1] == src1->f[1] ? ~0 : 0;
3092 dst->u[2] = src0->f[2] == src1->f[2] ? ~0 : 0;
3093 dst->u[3] = src0->f[3] == src1->f[3] ? ~0 : 0;
3094 }
3095
3096 static void
3097 micro_fsge(union tgsi_exec_channel *dst,
3098 const union tgsi_exec_channel *src0,
3099 const union tgsi_exec_channel *src1)
3100 {
3101 dst->u[0] = src0->f[0] >= src1->f[0] ? ~0 : 0;
3102 dst->u[1] = src0->f[1] >= src1->f[1] ? ~0 : 0;
3103 dst->u[2] = src0->f[2] >= src1->f[2] ? ~0 : 0;
3104 dst->u[3] = src0->f[3] >= src1->f[3] ? ~0 : 0;
3105 }
3106
3107 static void
3108 micro_fslt(union tgsi_exec_channel *dst,
3109 const union tgsi_exec_channel *src0,
3110 const union tgsi_exec_channel *src1)
3111 {
3112 dst->u[0] = src0->f[0] < src1->f[0] ? ~0 : 0;
3113 dst->u[1] = src0->f[1] < src1->f[1] ? ~0 : 0;
3114 dst->u[2] = src0->f[2] < src1->f[2] ? ~0 : 0;
3115 dst->u[3] = src0->f[3] < src1->f[3] ? ~0 : 0;
3116 }
3117
3118 static void
3119 micro_fsne(union tgsi_exec_channel *dst,
3120 const union tgsi_exec_channel *src0,
3121 const union tgsi_exec_channel *src1)
3122 {
3123 dst->u[0] = src0->f[0] != src1->f[0] ? ~0 : 0;
3124 dst->u[1] = src0->f[1] != src1->f[1] ? ~0 : 0;
3125 dst->u[2] = src0->f[2] != src1->f[2] ? ~0 : 0;
3126 dst->u[3] = src0->f[3] != src1->f[3] ? ~0 : 0;
3127 }
3128
3129 static void
3130 micro_idiv(union tgsi_exec_channel *dst,
3131 const union tgsi_exec_channel *src0,
3132 const union tgsi_exec_channel *src1)
3133 {
3134 dst->i[0] = src1->i[0] ? src0->i[0] / src1->i[0] : 0;
3135 dst->i[1] = src1->i[1] ? src0->i[1] / src1->i[1] : 0;
3136 dst->i[2] = src1->i[2] ? src0->i[2] / src1->i[2] : 0;
3137 dst->i[3] = src1->i[3] ? src0->i[3] / src1->i[3] : 0;
3138 }
3139
3140 static void
3141 micro_imax(union tgsi_exec_channel *dst,
3142 const union tgsi_exec_channel *src0,
3143 const union tgsi_exec_channel *src1)
3144 {
3145 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
3146 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
3147 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
3148 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
3149 }
3150
3151 static void
3152 micro_imin(union tgsi_exec_channel *dst,
3153 const union tgsi_exec_channel *src0,
3154 const union tgsi_exec_channel *src1)
3155 {
3156 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
3157 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
3158 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
3159 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
3160 }
3161
3162 static void
3163 micro_isge(union tgsi_exec_channel *dst,
3164 const union tgsi_exec_channel *src0,
3165 const union tgsi_exec_channel *src1)
3166 {
3167 dst->i[0] = src0->i[0] >= src1->i[0] ? -1 : 0;
3168 dst->i[1] = src0->i[1] >= src1->i[1] ? -1 : 0;
3169 dst->i[2] = src0->i[2] >= src1->i[2] ? -1 : 0;
3170 dst->i[3] = src0->i[3] >= src1->i[3] ? -1 : 0;
3171 }
3172
3173 static void
3174 micro_ishr(union tgsi_exec_channel *dst,
3175 const union tgsi_exec_channel *src0,
3176 const union tgsi_exec_channel *src1)
3177 {
3178 unsigned masked_count;
3179 masked_count = src1->i[0] & 0x1f;
3180 dst->i[0] = src0->i[0] >> masked_count;
3181 masked_count = src1->i[1] & 0x1f;
3182 dst->i[1] = src0->i[1] >> masked_count;
3183 masked_count = src1->i[2] & 0x1f;
3184 dst->i[2] = src0->i[2] >> masked_count;
3185 masked_count = src1->i[3] & 0x1f;
3186 dst->i[3] = src0->i[3] >> masked_count;
3187 }
3188
3189 static void
3190 micro_islt(union tgsi_exec_channel *dst,
3191 const union tgsi_exec_channel *src0,
3192 const union tgsi_exec_channel *src1)
3193 {
3194 dst->i[0] = src0->i[0] < src1->i[0] ? -1 : 0;
3195 dst->i[1] = src0->i[1] < src1->i[1] ? -1 : 0;
3196 dst->i[2] = src0->i[2] < src1->i[2] ? -1 : 0;
3197 dst->i[3] = src0->i[3] < src1->i[3] ? -1 : 0;
3198 }
3199
3200 static void
3201 micro_f2u(union tgsi_exec_channel *dst,
3202 const union tgsi_exec_channel *src)
3203 {
3204 dst->u[0] = (uint)src->f[0];
3205 dst->u[1] = (uint)src->f[1];
3206 dst->u[2] = (uint)src->f[2];
3207 dst->u[3] = (uint)src->f[3];
3208 }
3209
3210 static void
3211 micro_u2f(union tgsi_exec_channel *dst,
3212 const union tgsi_exec_channel *src)
3213 {
3214 dst->f[0] = (float)src->u[0];
3215 dst->f[1] = (float)src->u[1];
3216 dst->f[2] = (float)src->u[2];
3217 dst->f[3] = (float)src->u[3];
3218 }
3219
3220 static void
3221 micro_uadd(union tgsi_exec_channel *dst,
3222 const union tgsi_exec_channel *src0,
3223 const union tgsi_exec_channel *src1)
3224 {
3225 dst->u[0] = src0->u[0] + src1->u[0];
3226 dst->u[1] = src0->u[1] + src1->u[1];
3227 dst->u[2] = src0->u[2] + src1->u[2];
3228 dst->u[3] = src0->u[3] + src1->u[3];
3229 }
3230
3231 static void
3232 micro_udiv(union tgsi_exec_channel *dst,
3233 const union tgsi_exec_channel *src0,
3234 const union tgsi_exec_channel *src1)
3235 {
3236 dst->u[0] = src1->u[0] ? src0->u[0] / src1->u[0] : ~0u;
3237 dst->u[1] = src1->u[1] ? src0->u[1] / src1->u[1] : ~0u;
3238 dst->u[2] = src1->u[2] ? src0->u[2] / src1->u[2] : ~0u;
3239 dst->u[3] = src1->u[3] ? src0->u[3] / src1->u[3] : ~0u;
3240 }
3241
3242 static void
3243 micro_umad(union tgsi_exec_channel *dst,
3244 const union tgsi_exec_channel *src0,
3245 const union tgsi_exec_channel *src1,
3246 const union tgsi_exec_channel *src2)
3247 {
3248 dst->u[0] = src0->u[0] * src1->u[0] + src2->u[0];
3249 dst->u[1] = src0->u[1] * src1->u[1] + src2->u[1];
3250 dst->u[2] = src0->u[2] * src1->u[2] + src2->u[2];
3251 dst->u[3] = src0->u[3] * src1->u[3] + src2->u[3];
3252 }
3253
3254 static void
3255 micro_umax(union tgsi_exec_channel *dst,
3256 const union tgsi_exec_channel *src0,
3257 const union tgsi_exec_channel *src1)
3258 {
3259 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
3260 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
3261 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
3262 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
3263 }
3264
3265 static void
3266 micro_umin(union tgsi_exec_channel *dst,
3267 const union tgsi_exec_channel *src0,
3268 const union tgsi_exec_channel *src1)
3269 {
3270 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
3271 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
3272 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
3273 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
3274 }
3275
3276 static void
3277 micro_umod(union tgsi_exec_channel *dst,
3278 const union tgsi_exec_channel *src0,
3279 const union tgsi_exec_channel *src1)
3280 {
3281 dst->u[0] = src1->u[0] ? src0->u[0] % src1->u[0] : ~0u;
3282 dst->u[1] = src1->u[1] ? src0->u[1] % src1->u[1] : ~0u;
3283 dst->u[2] = src1->u[2] ? src0->u[2] % src1->u[2] : ~0u;
3284 dst->u[3] = src1->u[3] ? src0->u[3] % src1->u[3] : ~0u;
3285 }
3286
3287 static void
3288 micro_umul(union tgsi_exec_channel *dst,
3289 const union tgsi_exec_channel *src0,
3290 const union tgsi_exec_channel *src1)
3291 {
3292 dst->u[0] = src0->u[0] * src1->u[0];
3293 dst->u[1] = src0->u[1] * src1->u[1];
3294 dst->u[2] = src0->u[2] * src1->u[2];
3295 dst->u[3] = src0->u[3] * src1->u[3];
3296 }
3297
3298 static void
3299 micro_imul_hi(union tgsi_exec_channel *dst,
3300 const union tgsi_exec_channel *src0,
3301 const union tgsi_exec_channel *src1)
3302 {
3303 #define I64M(x, y) ((((int64_t)x) * ((int64_t)y)) >> 32)
3304 dst->i[0] = I64M(src0->i[0], src1->i[0]);
3305 dst->i[1] = I64M(src0->i[1], src1->i[1]);
3306 dst->i[2] = I64M(src0->i[2], src1->i[2]);
3307 dst->i[3] = I64M(src0->i[3], src1->i[3]);
3308 #undef I64M
3309 }
3310
3311 static void
3312 micro_umul_hi(union tgsi_exec_channel *dst,
3313 const union tgsi_exec_channel *src0,
3314 const union tgsi_exec_channel *src1)
3315 {
3316 #define U64M(x, y) ((((uint64_t)x) * ((uint64_t)y)) >> 32)
3317 dst->u[0] = U64M(src0->u[0], src1->u[0]);
3318 dst->u[1] = U64M(src0->u[1], src1->u[1]);
3319 dst->u[2] = U64M(src0->u[2], src1->u[2]);
3320 dst->u[3] = U64M(src0->u[3], src1->u[3]);
3321 #undef U64M
3322 }
3323
3324 static void
3325 micro_useq(union tgsi_exec_channel *dst,
3326 const union tgsi_exec_channel *src0,
3327 const union tgsi_exec_channel *src1)
3328 {
3329 dst->u[0] = src0->u[0] == src1->u[0] ? ~0 : 0;
3330 dst->u[1] = src0->u[1] == src1->u[1] ? ~0 : 0;
3331 dst->u[2] = src0->u[2] == src1->u[2] ? ~0 : 0;
3332 dst->u[3] = src0->u[3] == src1->u[3] ? ~0 : 0;
3333 }
3334
3335 static void
3336 micro_usge(union tgsi_exec_channel *dst,
3337 const union tgsi_exec_channel *src0,
3338 const union tgsi_exec_channel *src1)
3339 {
3340 dst->u[0] = src0->u[0] >= src1->u[0] ? ~0 : 0;
3341 dst->u[1] = src0->u[1] >= src1->u[1] ? ~0 : 0;
3342 dst->u[2] = src0->u[2] >= src1->u[2] ? ~0 : 0;
3343 dst->u[3] = src0->u[3] >= src1->u[3] ? ~0 : 0;
3344 }
3345
3346 static void
3347 micro_ushr(union tgsi_exec_channel *dst,
3348 const union tgsi_exec_channel *src0,
3349 const union tgsi_exec_channel *src1)
3350 {
3351 unsigned masked_count;
3352 masked_count = src1->u[0] & 0x1f;
3353 dst->u[0] = src0->u[0] >> masked_count;
3354 masked_count = src1->u[1] & 0x1f;
3355 dst->u[1] = src0->u[1] >> masked_count;
3356 masked_count = src1->u[2] & 0x1f;
3357 dst->u[2] = src0->u[2] >> masked_count;
3358 masked_count = src1->u[3] & 0x1f;
3359 dst->u[3] = src0->u[3] >> masked_count;
3360 }
3361
3362 static void
3363 micro_uslt(union tgsi_exec_channel *dst,
3364 const union tgsi_exec_channel *src0,
3365 const union tgsi_exec_channel *src1)
3366 {
3367 dst->u[0] = src0->u[0] < src1->u[0] ? ~0 : 0;
3368 dst->u[1] = src0->u[1] < src1->u[1] ? ~0 : 0;
3369 dst->u[2] = src0->u[2] < src1->u[2] ? ~0 : 0;
3370 dst->u[3] = src0->u[3] < src1->u[3] ? ~0 : 0;
3371 }
3372
3373 static void
3374 micro_usne(union tgsi_exec_channel *dst,
3375 const union tgsi_exec_channel *src0,
3376 const union tgsi_exec_channel *src1)
3377 {
3378 dst->u[0] = src0->u[0] != src1->u[0] ? ~0 : 0;
3379 dst->u[1] = src0->u[1] != src1->u[1] ? ~0 : 0;
3380 dst->u[2] = src0->u[2] != src1->u[2] ? ~0 : 0;
3381 dst->u[3] = src0->u[3] != src1->u[3] ? ~0 : 0;
3382 }
3383
3384 static void
3385 micro_uarl(union tgsi_exec_channel *dst,
3386 const union tgsi_exec_channel *src)
3387 {
3388 dst->i[0] = src->u[0];
3389 dst->i[1] = src->u[1];
3390 dst->i[2] = src->u[2];
3391 dst->i[3] = src->u[3];
3392 }
3393
3394 static void
3395 micro_ucmp(union tgsi_exec_channel *dst,
3396 const union tgsi_exec_channel *src0,
3397 const union tgsi_exec_channel *src1,
3398 const union tgsi_exec_channel *src2)
3399 {
3400 dst->u[0] = src0->u[0] ? src1->u[0] : src2->u[0];
3401 dst->u[1] = src0->u[1] ? src1->u[1] : src2->u[1];
3402 dst->u[2] = src0->u[2] ? src1->u[2] : src2->u[2];
3403 dst->u[3] = src0->u[3] ? src1->u[3] : src2->u[3];
3404 }
3405
3406 /**
3407 * Signed bitfield extract (i.e. sign-extend the extracted bits)
3408 */
3409 static void
3410 micro_ibfe(union tgsi_exec_channel *dst,
3411 const union tgsi_exec_channel *src0,
3412 const union tgsi_exec_channel *src1,
3413 const union tgsi_exec_channel *src2)
3414 {
3415 int i;
3416 for (i = 0; i < 4; i++) {
3417 int width = src2->i[i] & 0x1f;
3418 int offset = src1->i[i] & 0x1f;
3419 if (width == 0)
3420 dst->i[i] = 0;
3421 else if (width + offset < 32)
3422 dst->i[i] = (src0->i[i] << (32 - width - offset)) >> (32 - width);
3423 else
3424 dst->i[i] = src0->i[i] >> offset;
3425 }
3426 }
3427
3428 /**
3429 * Unsigned bitfield extract
3430 */
3431 static void
3432 micro_ubfe(union tgsi_exec_channel *dst,
3433 const union tgsi_exec_channel *src0,
3434 const union tgsi_exec_channel *src1,
3435 const union tgsi_exec_channel *src2)
3436 {
3437 int i;
3438 for (i = 0; i < 4; i++) {
3439 int width = src2->u[i] & 0x1f;
3440 int offset = src1->u[i] & 0x1f;
3441 if (width == 0)
3442 dst->u[i] = 0;
3443 else if (width + offset < 32)
3444 dst->u[i] = (src0->u[i] << (32 - width - offset)) >> (32 - width);
3445 else
3446 dst->u[i] = src0->u[i] >> offset;
3447 }
3448 }
3449
3450 /**
3451 * Bitfield insert: copy low bits from src1 into a region of src0.
3452 */
3453 static void
3454 micro_bfi(union tgsi_exec_channel *dst,
3455 const union tgsi_exec_channel *src0,
3456 const union tgsi_exec_channel *src1,
3457 const union tgsi_exec_channel *src2,
3458 const union tgsi_exec_channel *src3)
3459 {
3460 int i;
3461 for (i = 0; i < 4; i++) {
3462 int width = src3->u[i] & 0x1f;
3463 int offset = src2->u[i] & 0x1f;
3464 int bitmask = ((1 << width) - 1) << offset;
3465 dst->u[i] = ((src1->u[i] << offset) & bitmask) | (src0->u[i] & ~bitmask);
3466 }
3467 }
3468
3469 static void
3470 micro_brev(union tgsi_exec_channel *dst,
3471 const union tgsi_exec_channel *src)
3472 {
3473 dst->u[0] = util_bitreverse(src->u[0]);
3474 dst->u[1] = util_bitreverse(src->u[1]);
3475 dst->u[2] = util_bitreverse(src->u[2]);
3476 dst->u[3] = util_bitreverse(src->u[3]);
3477 }
3478
3479 static void
3480 micro_popc(union tgsi_exec_channel *dst,
3481 const union tgsi_exec_channel *src)
3482 {
3483 dst->u[0] = util_bitcount(src->u[0]);
3484 dst->u[1] = util_bitcount(src->u[1]);
3485 dst->u[2] = util_bitcount(src->u[2]);
3486 dst->u[3] = util_bitcount(src->u[3]);
3487 }
3488
3489 static void
3490 micro_lsb(union tgsi_exec_channel *dst,
3491 const union tgsi_exec_channel *src)
3492 {
3493 dst->i[0] = ffs(src->u[0]) - 1;
3494 dst->i[1] = ffs(src->u[1]) - 1;
3495 dst->i[2] = ffs(src->u[2]) - 1;
3496 dst->i[3] = ffs(src->u[3]) - 1;
3497 }
3498
3499 static void
3500 micro_imsb(union tgsi_exec_channel *dst,
3501 const union tgsi_exec_channel *src)
3502 {
3503 dst->i[0] = util_last_bit_signed(src->i[0]) - 1;
3504 dst->i[1] = util_last_bit_signed(src->i[1]) - 1;
3505 dst->i[2] = util_last_bit_signed(src->i[2]) - 1;
3506 dst->i[3] = util_last_bit_signed(src->i[3]) - 1;
3507 }
3508
3509 static void
3510 micro_umsb(union tgsi_exec_channel *dst,
3511 const union tgsi_exec_channel *src)
3512 {
3513 dst->i[0] = util_last_bit(src->u[0]) - 1;
3514 dst->i[1] = util_last_bit(src->u[1]) - 1;
3515 dst->i[2] = util_last_bit(src->u[2]) - 1;
3516 dst->i[3] = util_last_bit(src->u[3]) - 1;
3517 }
3518
3519 static void
3520 exec_instruction(
3521 struct tgsi_exec_machine *mach,
3522 const struct tgsi_full_instruction *inst,
3523 int *pc )
3524 {
3525 union tgsi_exec_channel r[10];
3526
3527 (*pc)++;
3528
3529 switch (inst->Instruction.Opcode) {
3530 case TGSI_OPCODE_ARL:
3531 exec_vector_unary(mach, inst, micro_arl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3532 break;
3533
3534 case TGSI_OPCODE_MOV:
3535 exec_vector_unary(mach, inst, micro_mov, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
3536 break;
3537
3538 case TGSI_OPCODE_LIT:
3539 exec_lit(mach, inst);
3540 break;
3541
3542 case TGSI_OPCODE_RCP:
3543 exec_scalar_unary(mach, inst, micro_rcp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3544 break;
3545
3546 case TGSI_OPCODE_RSQ:
3547 exec_scalar_unary(mach, inst, micro_rsq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3548 break;
3549
3550 case TGSI_OPCODE_EXP:
3551 exec_exp(mach, inst);
3552 break;
3553
3554 case TGSI_OPCODE_LOG:
3555 exec_log(mach, inst);
3556 break;
3557
3558 case TGSI_OPCODE_MUL:
3559 exec_vector_binary(mach, inst, micro_mul, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3560 break;
3561
3562 case TGSI_OPCODE_ADD:
3563 exec_vector_binary(mach, inst, micro_add, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3564 break;
3565
3566 case TGSI_OPCODE_DP3:
3567 exec_dp3(mach, inst);
3568 break;
3569
3570 case TGSI_OPCODE_DP4:
3571 exec_dp4(mach, inst);
3572 break;
3573
3574 case TGSI_OPCODE_DST:
3575 exec_dst(mach, inst);
3576 break;
3577
3578 case TGSI_OPCODE_MIN:
3579 exec_vector_binary(mach, inst, micro_min, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3580 break;
3581
3582 case TGSI_OPCODE_MAX:
3583 exec_vector_binary(mach, inst, micro_max, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3584 break;
3585
3586 case TGSI_OPCODE_SLT:
3587 exec_vector_binary(mach, inst, micro_slt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3588 break;
3589
3590 case TGSI_OPCODE_SGE:
3591 exec_vector_binary(mach, inst, micro_sge, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3592 break;
3593
3594 case TGSI_OPCODE_MAD:
3595 exec_vector_trinary(mach, inst, micro_mad, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3596 break;
3597
3598 case TGSI_OPCODE_SUB:
3599 exec_vector_binary(mach, inst, micro_sub, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3600 break;
3601
3602 case TGSI_OPCODE_LRP:
3603 exec_vector_trinary(mach, inst, micro_lrp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3604 break;
3605
3606 case TGSI_OPCODE_CND:
3607 exec_vector_trinary(mach, inst, micro_cnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3608 break;
3609
3610 case TGSI_OPCODE_SQRT:
3611 exec_scalar_unary(mach, inst, micro_sqrt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3612 break;
3613
3614 case TGSI_OPCODE_DP2A:
3615 exec_dp2a(mach, inst);
3616 break;
3617
3618 case TGSI_OPCODE_FRC:
3619 exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3620 break;
3621
3622 case TGSI_OPCODE_CLAMP:
3623 exec_vector_trinary(mach, inst, micro_clamp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3624 break;
3625
3626 case TGSI_OPCODE_FLR:
3627 exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3628 break;
3629
3630 case TGSI_OPCODE_ROUND:
3631 exec_vector_unary(mach, inst, micro_rnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3632 break;
3633
3634 case TGSI_OPCODE_EX2:
3635 exec_scalar_unary(mach, inst, micro_exp2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3636 break;
3637
3638 case TGSI_OPCODE_LG2:
3639 exec_scalar_unary(mach, inst, micro_lg2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3640 break;
3641
3642 case TGSI_OPCODE_POW:
3643 exec_scalar_binary(mach, inst, micro_pow, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3644 break;
3645
3646 case TGSI_OPCODE_XPD:
3647 exec_xpd(mach, inst);
3648 break;
3649
3650 case TGSI_OPCODE_ABS:
3651 exec_vector_unary(mach, inst, micro_abs, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3652 break;
3653
3654 case TGSI_OPCODE_DPH:
3655 exec_dph(mach, inst);
3656 break;
3657
3658 case TGSI_OPCODE_COS:
3659 exec_scalar_unary(mach, inst, micro_cos, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3660 break;
3661
3662 case TGSI_OPCODE_DDX:
3663 exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3664 break;
3665
3666 case TGSI_OPCODE_DDY:
3667 exec_vector_unary(mach, inst, micro_ddy, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3668 break;
3669
3670 case TGSI_OPCODE_KILL:
3671 exec_kill (mach, inst);
3672 break;
3673
3674 case TGSI_OPCODE_KILL_IF:
3675 exec_kill_if (mach, inst);
3676 break;
3677
3678 case TGSI_OPCODE_PK2H:
3679 assert (0);
3680 break;
3681
3682 case TGSI_OPCODE_PK2US:
3683 assert (0);
3684 break;
3685
3686 case TGSI_OPCODE_PK4B:
3687 assert (0);
3688 break;
3689
3690 case TGSI_OPCODE_PK4UB:
3691 assert (0);
3692 break;
3693
3694 case TGSI_OPCODE_SEQ:
3695 exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3696 break;
3697
3698 case TGSI_OPCODE_SGT:
3699 exec_vector_binary(mach, inst, micro_sgt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3700 break;
3701
3702 case TGSI_OPCODE_SIN:
3703 exec_scalar_unary(mach, inst, micro_sin, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3704 break;
3705
3706 case TGSI_OPCODE_SLE:
3707 exec_vector_binary(mach, inst, micro_sle, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3708 break;
3709
3710 case TGSI_OPCODE_SNE:
3711 exec_vector_binary(mach, inst, micro_sne, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3712 break;
3713
3714 case TGSI_OPCODE_TEX:
3715 /* simple texture lookup */
3716 /* src[0] = texcoord */
3717 /* src[1] = sampler unit */
3718 exec_tex(mach, inst, TEX_MODIFIER_NONE, 1);
3719 break;
3720
3721 case TGSI_OPCODE_TXB:
3722 /* Texture lookup with lod bias */
3723 /* src[0] = texcoord (src[0].w = LOD bias) */
3724 /* src[1] = sampler unit */
3725 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 1);
3726 break;
3727
3728 case TGSI_OPCODE_TXD:
3729 /* Texture lookup with explict partial derivatives */
3730 /* src[0] = texcoord */
3731 /* src[1] = d[strq]/dx */
3732 /* src[2] = d[strq]/dy */
3733 /* src[3] = sampler unit */
3734 exec_txd(mach, inst);
3735 break;
3736
3737 case TGSI_OPCODE_TXL:
3738 /* Texture lookup with explit LOD */
3739 /* src[0] = texcoord (src[0].w = LOD) */
3740 /* src[1] = sampler unit */
3741 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 1);
3742 break;
3743
3744 case TGSI_OPCODE_TXP:
3745 /* Texture lookup with projection */
3746 /* src[0] = texcoord (src[0].w = projection) */
3747 /* src[1] = sampler unit */
3748 exec_tex(mach, inst, TEX_MODIFIER_PROJECTED, 1);
3749 break;
3750
3751 case TGSI_OPCODE_UP2H:
3752 assert (0);
3753 break;
3754
3755 case TGSI_OPCODE_UP2US:
3756 assert (0);
3757 break;
3758
3759 case TGSI_OPCODE_UP4B:
3760 assert (0);
3761 break;
3762
3763 case TGSI_OPCODE_UP4UB:
3764 assert (0);
3765 break;
3766
3767 case TGSI_OPCODE_ARR:
3768 exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3769 break;
3770
3771 case TGSI_OPCODE_CAL:
3772 /* skip the call if no execution channels are enabled */
3773 if (mach->ExecMask) {
3774 /* do the call */
3775
3776 /* First, record the depths of the execution stacks.
3777 * This is important for deeply nested/looped return statements.
3778 * We have to unwind the stacks by the correct amount. For a
3779 * real code generator, we could determine the number of entries
3780 * to pop off each stack with simple static analysis and avoid
3781 * implementing this data structure at run time.
3782 */
3783 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
3784 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
3785 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
3786 mach->CallStack[mach->CallStackTop].SwitchStackTop = mach->SwitchStackTop;
3787 mach->CallStack[mach->CallStackTop].BreakStackTop = mach->BreakStackTop;
3788 /* note that PC was already incremented above */
3789 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
3790
3791 mach->CallStackTop++;
3792
3793 /* Second, push the Cond, Loop, Cont, Func stacks */
3794 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3795 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3796 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3797 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3798 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3799 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
3800
3801 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3802 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
3803 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
3804 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3805 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3806 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
3807
3808 /* Finally, jump to the subroutine */
3809 *pc = inst->Label.Label;
3810 }
3811 break;
3812
3813 case TGSI_OPCODE_RET:
3814 mach->FuncMask &= ~mach->ExecMask;
3815 UPDATE_EXEC_MASK(mach);
3816
3817 if (mach->FuncMask == 0x0) {
3818 /* really return now (otherwise, keep executing */
3819
3820 if (mach->CallStackTop == 0) {
3821 /* returning from main() */
3822 mach->CondStackTop = 0;
3823 mach->LoopStackTop = 0;
3824 *pc = -1;
3825 return;
3826 }
3827
3828 assert(mach->CallStackTop > 0);
3829 mach->CallStackTop--;
3830
3831 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
3832 mach->CondMask = mach->CondStack[mach->CondStackTop];
3833
3834 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
3835 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
3836
3837 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
3838 mach->ContMask = mach->ContStack[mach->ContStackTop];
3839
3840 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
3841 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
3842
3843 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
3844 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
3845
3846 assert(mach->FuncStackTop > 0);
3847 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
3848
3849 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
3850
3851 UPDATE_EXEC_MASK(mach);
3852 }
3853 break;
3854
3855 case TGSI_OPCODE_SSG:
3856 exec_vector_unary(mach, inst, micro_sgn, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3857 break;
3858
3859 case TGSI_OPCODE_CMP:
3860 exec_vector_trinary(mach, inst, micro_cmp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3861 break;
3862
3863 case TGSI_OPCODE_SCS:
3864 exec_scs(mach, inst);
3865 break;
3866
3867 case TGSI_OPCODE_DIV:
3868 exec_vector_binary(mach, inst, micro_div, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3869 break;
3870
3871 case TGSI_OPCODE_DP2:
3872 exec_dp2(mach, inst);
3873 break;
3874
3875 case TGSI_OPCODE_IF:
3876 /* push CondMask */
3877 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3878 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3879 FETCH( &r[0], 0, TGSI_CHAN_X );
3880 /* update CondMask */
3881 if( ! r[0].f[0] ) {
3882 mach->CondMask &= ~0x1;
3883 }
3884 if( ! r[0].f[1] ) {
3885 mach->CondMask &= ~0x2;
3886 }
3887 if( ! r[0].f[2] ) {
3888 mach->CondMask &= ~0x4;
3889 }
3890 if( ! r[0].f[3] ) {
3891 mach->CondMask &= ~0x8;
3892 }
3893 UPDATE_EXEC_MASK(mach);
3894 /* Todo: If CondMask==0, jump to ELSE */
3895 break;
3896
3897 case TGSI_OPCODE_UIF:
3898 /* push CondMask */
3899 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3900 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3901 IFETCH( &r[0], 0, TGSI_CHAN_X );
3902 /* update CondMask */
3903 if( ! r[0].u[0] ) {
3904 mach->CondMask &= ~0x1;
3905 }
3906 if( ! r[0].u[1] ) {
3907 mach->CondMask &= ~0x2;
3908 }
3909 if( ! r[0].u[2] ) {
3910 mach->CondMask &= ~0x4;
3911 }
3912 if( ! r[0].u[3] ) {
3913 mach->CondMask &= ~0x8;
3914 }
3915 UPDATE_EXEC_MASK(mach);
3916 /* Todo: If CondMask==0, jump to ELSE */
3917 break;
3918
3919 case TGSI_OPCODE_ELSE:
3920 /* invert CondMask wrt previous mask */
3921 {
3922 uint prevMask;
3923 assert(mach->CondStackTop > 0);
3924 prevMask = mach->CondStack[mach->CondStackTop - 1];
3925 mach->CondMask = ~mach->CondMask & prevMask;
3926 UPDATE_EXEC_MASK(mach);
3927 /* Todo: If CondMask==0, jump to ENDIF */
3928 }
3929 break;
3930
3931 case TGSI_OPCODE_ENDIF:
3932 /* pop CondMask */
3933 assert(mach->CondStackTop > 0);
3934 mach->CondMask = mach->CondStack[--mach->CondStackTop];
3935 UPDATE_EXEC_MASK(mach);
3936 break;
3937
3938 case TGSI_OPCODE_END:
3939 /* make sure we end primitives which haven't
3940 * been explicitly emitted */
3941 conditional_emit_primitive(mach);
3942 /* halt execution */
3943 *pc = -1;
3944 break;
3945
3946 case TGSI_OPCODE_PUSHA:
3947 assert (0);
3948 break;
3949
3950 case TGSI_OPCODE_POPA:
3951 assert (0);
3952 break;
3953
3954 case TGSI_OPCODE_CEIL:
3955 exec_vector_unary(mach, inst, micro_ceil, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3956 break;
3957
3958 case TGSI_OPCODE_I2F:
3959 exec_vector_unary(mach, inst, micro_i2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
3960 break;
3961
3962 case TGSI_OPCODE_NOT:
3963 exec_vector_unary(mach, inst, micro_not, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3964 break;
3965
3966 case TGSI_OPCODE_TRUNC:
3967 exec_vector_unary(mach, inst, micro_trunc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3968 break;
3969
3970 case TGSI_OPCODE_SHL:
3971 exec_vector_binary(mach, inst, micro_shl, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3972 break;
3973
3974 case TGSI_OPCODE_AND:
3975 exec_vector_binary(mach, inst, micro_and, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3976 break;
3977
3978 case TGSI_OPCODE_OR:
3979 exec_vector_binary(mach, inst, micro_or, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3980 break;
3981
3982 case TGSI_OPCODE_MOD:
3983 exec_vector_binary(mach, inst, micro_mod, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
3984 break;
3985
3986 case TGSI_OPCODE_XOR:
3987 exec_vector_binary(mach, inst, micro_xor, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
3988 break;
3989
3990 case TGSI_OPCODE_SAD:
3991 assert (0);
3992 break;
3993
3994 case TGSI_OPCODE_TXF:
3995 exec_txf(mach, inst);
3996 break;
3997
3998 case TGSI_OPCODE_TXQ:
3999 exec_txq(mach, inst);
4000 break;
4001
4002 case TGSI_OPCODE_EMIT:
4003 emit_vertex(mach);
4004 break;
4005
4006 case TGSI_OPCODE_ENDPRIM:
4007 emit_primitive(mach);
4008 break;
4009
4010 case TGSI_OPCODE_BGNLOOP:
4011 /* push LoopMask and ContMasks */
4012 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4013 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4014 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4015 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
4016
4017 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
4018 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
4019 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
4020 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
4021 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_LOOP;
4022 break;
4023
4024 case TGSI_OPCODE_ENDLOOP:
4025 /* Restore ContMask, but don't pop */
4026 assert(mach->ContStackTop > 0);
4027 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
4028 UPDATE_EXEC_MASK(mach);
4029 if (mach->ExecMask) {
4030 /* repeat loop: jump to instruction just past BGNLOOP */
4031 assert(mach->LoopLabelStackTop > 0);
4032 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
4033 }
4034 else {
4035 /* exit loop: pop LoopMask */
4036 assert(mach->LoopStackTop > 0);
4037 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
4038 /* pop ContMask */
4039 assert(mach->ContStackTop > 0);
4040 mach->ContMask = mach->ContStack[--mach->ContStackTop];
4041 assert(mach->LoopLabelStackTop > 0);
4042 --mach->LoopLabelStackTop;
4043
4044 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
4045 }
4046 UPDATE_EXEC_MASK(mach);
4047 break;
4048
4049 case TGSI_OPCODE_BRK:
4050 exec_break(mach);
4051 break;
4052
4053 case TGSI_OPCODE_CONT:
4054 /* turn off cont channels for each enabled exec channel */
4055 mach->ContMask &= ~mach->ExecMask;
4056 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4057 UPDATE_EXEC_MASK(mach);
4058 break;
4059
4060 case TGSI_OPCODE_BGNSUB:
4061 /* no-op */
4062 break;
4063
4064 case TGSI_OPCODE_ENDSUB:
4065 /*
4066 * XXX: This really should be a no-op. We should never reach this opcode.
4067 */
4068
4069 assert(mach->CallStackTop > 0);
4070 mach->CallStackTop--;
4071
4072 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
4073 mach->CondMask = mach->CondStack[mach->CondStackTop];
4074
4075 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
4076 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
4077
4078 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
4079 mach->ContMask = mach->ContStack[mach->ContStackTop];
4080
4081 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
4082 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
4083
4084 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
4085 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
4086
4087 assert(mach->FuncStackTop > 0);
4088 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
4089
4090 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
4091
4092 UPDATE_EXEC_MASK(mach);
4093 break;
4094
4095 case TGSI_OPCODE_NOP:
4096 break;
4097
4098 case TGSI_OPCODE_BREAKC:
4099 IFETCH(&r[0], 0, TGSI_CHAN_X);
4100 /* update CondMask */
4101 if (r[0].u[0] && (mach->ExecMask & 0x1)) {
4102 mach->LoopMask &= ~0x1;
4103 }
4104 if (r[0].u[1] && (mach->ExecMask & 0x2)) {
4105 mach->LoopMask &= ~0x2;
4106 }
4107 if (r[0].u[2] && (mach->ExecMask & 0x4)) {
4108 mach->LoopMask &= ~0x4;
4109 }
4110 if (r[0].u[3] && (mach->ExecMask & 0x8)) {
4111 mach->LoopMask &= ~0x8;
4112 }
4113 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4114 UPDATE_EXEC_MASK(mach);
4115 break;
4116
4117 case TGSI_OPCODE_F2I:
4118 exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4119 break;
4120
4121 case TGSI_OPCODE_FSEQ:
4122 exec_vector_binary(mach, inst, micro_fseq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4123 break;
4124
4125 case TGSI_OPCODE_FSGE:
4126 exec_vector_binary(mach, inst, micro_fsge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4127 break;
4128
4129 case TGSI_OPCODE_FSLT:
4130 exec_vector_binary(mach, inst, micro_fslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4131 break;
4132
4133 case TGSI_OPCODE_FSNE:
4134 exec_vector_binary(mach, inst, micro_fsne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4135 break;
4136
4137 case TGSI_OPCODE_IDIV:
4138 exec_vector_binary(mach, inst, micro_idiv, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4139 break;
4140
4141 case TGSI_OPCODE_IMAX:
4142 exec_vector_binary(mach, inst, micro_imax, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4143 break;
4144
4145 case TGSI_OPCODE_IMIN:
4146 exec_vector_binary(mach, inst, micro_imin, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4147 break;
4148
4149 case TGSI_OPCODE_INEG:
4150 exec_vector_unary(mach, inst, micro_ineg, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4151 break;
4152
4153 case TGSI_OPCODE_ISGE:
4154 exec_vector_binary(mach, inst, micro_isge, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4155 break;
4156
4157 case TGSI_OPCODE_ISHR:
4158 exec_vector_binary(mach, inst, micro_ishr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4159 break;
4160
4161 case TGSI_OPCODE_ISLT:
4162 exec_vector_binary(mach, inst, micro_islt, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4163 break;
4164
4165 case TGSI_OPCODE_F2U:
4166 exec_vector_unary(mach, inst, micro_f2u, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4167 break;
4168
4169 case TGSI_OPCODE_U2F:
4170 exec_vector_unary(mach, inst, micro_u2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_UINT);
4171 break;
4172
4173 case TGSI_OPCODE_UADD:
4174 exec_vector_binary(mach, inst, micro_uadd, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4175 break;
4176
4177 case TGSI_OPCODE_UDIV:
4178 exec_vector_binary(mach, inst, micro_udiv, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4179 break;
4180
4181 case TGSI_OPCODE_UMAD:
4182 exec_vector_trinary(mach, inst, micro_umad, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4183 break;
4184
4185 case TGSI_OPCODE_UMAX:
4186 exec_vector_binary(mach, inst, micro_umax, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4187 break;
4188
4189 case TGSI_OPCODE_UMIN:
4190 exec_vector_binary(mach, inst, micro_umin, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4191 break;
4192
4193 case TGSI_OPCODE_UMOD:
4194 exec_vector_binary(mach, inst, micro_umod, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4195 break;
4196
4197 case TGSI_OPCODE_UMUL:
4198 exec_vector_binary(mach, inst, micro_umul, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4199 break;
4200
4201 case TGSI_OPCODE_IMUL_HI:
4202 exec_vector_binary(mach, inst, micro_imul_hi, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4203 break;
4204
4205 case TGSI_OPCODE_UMUL_HI:
4206 exec_vector_binary(mach, inst, micro_umul_hi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4207 break;
4208
4209 case TGSI_OPCODE_USEQ:
4210 exec_vector_binary(mach, inst, micro_useq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4211 break;
4212
4213 case TGSI_OPCODE_USGE:
4214 exec_vector_binary(mach, inst, micro_usge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4215 break;
4216
4217 case TGSI_OPCODE_USHR:
4218 exec_vector_binary(mach, inst, micro_ushr, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4219 break;
4220
4221 case TGSI_OPCODE_USLT:
4222 exec_vector_binary(mach, inst, micro_uslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4223 break;
4224
4225 case TGSI_OPCODE_USNE:
4226 exec_vector_binary(mach, inst, micro_usne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4227 break;
4228
4229 case TGSI_OPCODE_SWITCH:
4230 exec_switch(mach, inst);
4231 break;
4232
4233 case TGSI_OPCODE_CASE:
4234 exec_case(mach, inst);
4235 break;
4236
4237 case TGSI_OPCODE_DEFAULT:
4238 exec_default(mach);
4239 break;
4240
4241 case TGSI_OPCODE_ENDSWITCH:
4242 exec_endswitch(mach);
4243 break;
4244
4245 case TGSI_OPCODE_SAMPLE_I:
4246 exec_txf(mach, inst);
4247 break;
4248
4249 case TGSI_OPCODE_SAMPLE_I_MS:
4250 assert(0);
4251 break;
4252
4253 case TGSI_OPCODE_SAMPLE:
4254 exec_sample(mach, inst, TEX_MODIFIER_NONE, FALSE);
4255 break;
4256
4257 case TGSI_OPCODE_SAMPLE_B:
4258 exec_sample(mach, inst, TEX_MODIFIER_LOD_BIAS, FALSE);
4259 break;
4260
4261 case TGSI_OPCODE_SAMPLE_C:
4262 exec_sample(mach, inst, TEX_MODIFIER_NONE, TRUE);
4263 break;
4264
4265 case TGSI_OPCODE_SAMPLE_C_LZ:
4266 exec_sample(mach, inst, TEX_MODIFIER_LEVEL_ZERO, TRUE);
4267 break;
4268
4269 case TGSI_OPCODE_SAMPLE_D:
4270 exec_sample_d(mach, inst);
4271 break;
4272
4273 case TGSI_OPCODE_SAMPLE_L:
4274 exec_sample(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, FALSE);
4275 break;
4276
4277 case TGSI_OPCODE_GATHER4:
4278 assert(0);
4279 break;
4280
4281 case TGSI_OPCODE_SVIEWINFO:
4282 exec_txq(mach, inst);
4283 break;
4284
4285 case TGSI_OPCODE_SAMPLE_POS:
4286 assert(0);
4287 break;
4288
4289 case TGSI_OPCODE_SAMPLE_INFO:
4290 assert(0);
4291 break;
4292
4293 case TGSI_OPCODE_UARL:
4294 exec_vector_unary(mach, inst, micro_uarl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
4295 break;
4296
4297 case TGSI_OPCODE_UCMP:
4298 exec_vector_trinary(mach, inst, micro_ucmp, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4299 break;
4300
4301 case TGSI_OPCODE_IABS:
4302 exec_vector_unary(mach, inst, micro_iabs, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4303 break;
4304
4305 case TGSI_OPCODE_ISSG:
4306 exec_vector_unary(mach, inst, micro_isgn, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4307 break;
4308
4309 case TGSI_OPCODE_TEX2:
4310 /* simple texture lookup */
4311 /* src[0] = texcoord */
4312 /* src[1] = compare */
4313 /* src[2] = sampler unit */
4314 exec_tex(mach, inst, TEX_MODIFIER_NONE, 2);
4315 break;
4316 case TGSI_OPCODE_TXB2:
4317 /* simple texture lookup */
4318 /* src[0] = texcoord */
4319 /* src[1] = bias */
4320 /* src[2] = sampler unit */
4321 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 2);
4322 break;
4323 case TGSI_OPCODE_TXL2:
4324 /* simple texture lookup */
4325 /* src[0] = texcoord */
4326 /* src[1] = lod */
4327 /* src[2] = sampler unit */
4328 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 2);
4329 break;
4330
4331 case TGSI_OPCODE_IBFE:
4332 exec_vector_trinary(mach, inst, micro_ibfe, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4333 break;
4334 case TGSI_OPCODE_UBFE:
4335 exec_vector_trinary(mach, inst, micro_ubfe, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4336 break;
4337 case TGSI_OPCODE_BFI:
4338 exec_vector_quaternary(mach, inst, micro_bfi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4339 break;
4340 case TGSI_OPCODE_BREV:
4341 exec_vector_unary(mach, inst, micro_brev, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4342 break;
4343 case TGSI_OPCODE_POPC:
4344 exec_vector_unary(mach, inst, micro_popc, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4345 break;
4346 case TGSI_OPCODE_LSB:
4347 exec_vector_unary(mach, inst, micro_lsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
4348 break;
4349 case TGSI_OPCODE_IMSB:
4350 exec_vector_unary(mach, inst, micro_imsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4351 break;
4352 case TGSI_OPCODE_UMSB:
4353 exec_vector_unary(mach, inst, micro_umsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
4354 break;
4355 default:
4356 assert( 0 );
4357 }
4358 }
4359
4360
4361 /**
4362 * Run TGSI interpreter.
4363 * \return bitmask of "alive" quad components
4364 */
4365 uint
4366 tgsi_exec_machine_run( struct tgsi_exec_machine *mach )
4367 {
4368 uint i;
4369 int pc = 0;
4370 uint default_mask = 0xf;
4371
4372 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
4373 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
4374
4375 if( mach->Processor == TGSI_PROCESSOR_GEOMETRY ) {
4376 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
4377 mach->Primitives[0] = 0;
4378 /* GS runs on a single primitive for now */
4379 default_mask = 0x1;
4380 }
4381
4382 mach->CondMask = default_mask;
4383 mach->LoopMask = default_mask;
4384 mach->ContMask = default_mask;
4385 mach->FuncMask = default_mask;
4386 mach->ExecMask = default_mask;
4387
4388 mach->Switch.mask = default_mask;
4389
4390 assert(mach->CondStackTop == 0);
4391 assert(mach->LoopStackTop == 0);
4392 assert(mach->ContStackTop == 0);
4393 assert(mach->SwitchStackTop == 0);
4394 assert(mach->BreakStackTop == 0);
4395 assert(mach->CallStackTop == 0);
4396
4397
4398 /* execute declarations (interpolants) */
4399 for (i = 0; i < mach->NumDeclarations; i++) {
4400 exec_declaration( mach, mach->Declarations+i );
4401 }
4402
4403 {
4404 #if DEBUG_EXECUTION
4405 struct tgsi_exec_vector temps[TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS];
4406 struct tgsi_exec_vector outputs[PIPE_MAX_ATTRIBS];
4407 uint inst = 1;
4408
4409 memset(mach->Temps, 0, sizeof(temps));
4410 memset(mach->Outputs, 0, sizeof(outputs));
4411 memset(temps, 0, sizeof(temps));
4412 memset(outputs, 0, sizeof(outputs));
4413 #endif
4414
4415 /* execute instructions, until pc is set to -1 */
4416 while (pc != -1) {
4417
4418 #if DEBUG_EXECUTION
4419 uint i;
4420
4421 tgsi_dump_instruction(&mach->Instructions[pc], inst++);
4422 #endif
4423
4424 assert(pc < (int) mach->NumInstructions);
4425 exec_instruction(mach, mach->Instructions + pc, &pc);
4426
4427 #if DEBUG_EXECUTION
4428 for (i = 0; i < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS; i++) {
4429 if (memcmp(&temps[i], &mach->Temps[i], sizeof(temps[i]))) {
4430 uint j;
4431
4432 memcpy(&temps[i], &mach->Temps[i], sizeof(temps[i]));
4433 debug_printf("TEMP[%2u] = ", i);
4434 for (j = 0; j < 4; j++) {
4435 if (j > 0) {
4436 debug_printf(" ");
4437 }
4438 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4439 temps[i].xyzw[0].f[j], temps[i].xyzw[0].u[j],
4440 temps[i].xyzw[1].f[j], temps[i].xyzw[1].u[j],
4441 temps[i].xyzw[2].f[j], temps[i].xyzw[2].u[j],
4442 temps[i].xyzw[3].f[j], temps[i].xyzw[3].u[j]);
4443 }
4444 }
4445 }
4446 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
4447 if (memcmp(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]))) {
4448 uint j;
4449
4450 memcpy(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]));
4451 debug_printf("OUT[%2u] = ", i);
4452 for (j = 0; j < 4; j++) {
4453 if (j > 0) {
4454 debug_printf(" ");
4455 }
4456 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4457 outputs[i].xyzw[0].f[j], outputs[i].xyzw[0].u[j],
4458 outputs[i].xyzw[1].f[j], outputs[i].xyzw[1].u[j],
4459 outputs[i].xyzw[2].f[j], outputs[i].xyzw[2].u[j],
4460 outputs[i].xyzw[3].f[j], outputs[i].xyzw[3].u[j]);
4461 }
4462 }
4463 }
4464 #endif
4465 }
4466 }
4467
4468 #if 0
4469 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
4470 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
4471 /*
4472 * Scale back depth component.
4473 */
4474 for (i = 0; i < 4; i++)
4475 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
4476 }
4477 #endif
4478
4479 /* Strictly speaking, these assertions aren't really needed but they
4480 * can potentially catch some bugs in the control flow code.
4481 */
4482 assert(mach->CondStackTop == 0);
4483 assert(mach->LoopStackTop == 0);
4484 assert(mach->ContStackTop == 0);
4485 assert(mach->SwitchStackTop == 0);
4486 assert(mach->BreakStackTop == 0);
4487 assert(mach->CallStackTop == 0);
4488
4489 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4490 }