projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
tgsi: new comments, assertion for executing TGSI_OPCODE_CAL
[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 VMware, Inc.
4 * All Rights Reserved.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 /**
30 * TGSI interpreter/executor.
31 *
32 * Flow control information:
33 *
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
38 *
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
42 * See store_dest().
43 *
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
47 *
48 *
49 * Authors:
50 * Michal Krol
51 * Brian Paul
52 */
53
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_memory.h"
62 #include "util/u_math.h"
63
64
65 #define DEBUG_EXECUTION 0
66
67
68 #define FAST_MATH 0
69
70 #define TILE_TOP_LEFT 0
71 #define TILE_TOP_RIGHT 1
72 #define TILE_BOTTOM_LEFT 2
73 #define TILE_BOTTOM_RIGHT 3
74
75 union tgsi_double_channel {
76 double d[TGSI_QUAD_SIZE];
77 unsigned u[TGSI_QUAD_SIZE][2];
78 };
79
80 struct tgsi_double_vector {
81 union tgsi_double_channel xy;
82 union tgsi_double_channel zw;
83 };
84
85 static void
86 micro_abs(union tgsi_exec_channel *dst,
87 const union tgsi_exec_channel *src)
88 {
89 dst->f[0] = fabsf(src->f[0]);
90 dst->f[1] = fabsf(src->f[1]);
91 dst->f[2] = fabsf(src->f[2]);
92 dst->f[3] = fabsf(src->f[3]);
93 }
94
95 static void
96 micro_arl(union tgsi_exec_channel *dst,
97 const union tgsi_exec_channel *src)
98 {
99 dst->i[0] = (int)floorf(src->f[0]);
100 dst->i[1] = (int)floorf(src->f[1]);
101 dst->i[2] = (int)floorf(src->f[2]);
102 dst->i[3] = (int)floorf(src->f[3]);
103 }
104
105 static void
106 micro_arr(union tgsi_exec_channel *dst,
107 const union tgsi_exec_channel *src)
108 {
109 dst->i[0] = (int)floorf(src->f[0] + 0.5f);
110 dst->i[1] = (int)floorf(src->f[1] + 0.5f);
111 dst->i[2] = (int)floorf(src->f[2] + 0.5f);
112 dst->i[3] = (int)floorf(src->f[3] + 0.5f);
113 }
114
115 static void
116 micro_ceil(union tgsi_exec_channel *dst,
117 const union tgsi_exec_channel *src)
118 {
119 dst->f[0] = ceilf(src->f[0]);
120 dst->f[1] = ceilf(src->f[1]);
121 dst->f[2] = ceilf(src->f[2]);
122 dst->f[3] = ceilf(src->f[3]);
123 }
124
125 static void
126 micro_clamp(union tgsi_exec_channel *dst,
127 const union tgsi_exec_channel *src0,
128 const union tgsi_exec_channel *src1,
129 const union tgsi_exec_channel *src2)
130 {
131 dst->f[0] = src0->f[0] < src1->f[0] ? src1->f[0] : src0->f[0] > src2->f[0] ? src2->f[0] : src0->f[0];
132 dst->f[1] = src0->f[1] < src1->f[1] ? src1->f[1] : src0->f[1] > src2->f[1] ? src2->f[1] : src0->f[1];
133 dst->f[2] = src0->f[2] < src1->f[2] ? src1->f[2] : src0->f[2] > src2->f[2] ? src2->f[2] : src0->f[2];
134 dst->f[3] = src0->f[3] < src1->f[3] ? src1->f[3] : src0->f[3] > src2->f[3] ? src2->f[3] : src0->f[3];
135 }
136
137 static void
138 micro_cmp(union tgsi_exec_channel *dst,
139 const union tgsi_exec_channel *src0,
140 const union tgsi_exec_channel *src1,
141 const union tgsi_exec_channel *src2)
142 {
143 dst->f[0] = src0->f[0] < 0.0f ? src1->f[0] : src2->f[0];
144 dst->f[1] = src0->f[1] < 0.0f ? src1->f[1] : src2->f[1];
145 dst->f[2] = src0->f[2] < 0.0f ? src1->f[2] : src2->f[2];
146 dst->f[3] = src0->f[3] < 0.0f ? src1->f[3] : src2->f[3];
147 }
148
149 static void
150 micro_cos(union tgsi_exec_channel *dst,
151 const union tgsi_exec_channel *src)
152 {
153 dst->f[0] = cosf(src->f[0]);
154 dst->f[1] = cosf(src->f[1]);
155 dst->f[2] = cosf(src->f[2]);
156 dst->f[3] = cosf(src->f[3]);
157 }
158
159 static void
160 micro_d2f(union tgsi_exec_channel *dst,
161 const union tgsi_double_channel *src)
162 {
163 dst->f[0] = (float)src->d[0];
164 dst->f[1] = (float)src->d[1];
165 dst->f[2] = (float)src->d[2];
166 dst->f[3] = (float)src->d[3];
167 }
168
169 static void
170 micro_d2i(union tgsi_exec_channel *dst,
171 const union tgsi_double_channel *src)
172 {
173 dst->i[0] = (int)src->d[0];
174 dst->i[1] = (int)src->d[1];
175 dst->i[2] = (int)src->d[2];
176 dst->i[3] = (int)src->d[3];
177 }
178
179 static void
180 micro_d2u(union tgsi_exec_channel *dst,
181 const union tgsi_double_channel *src)
182 {
183 dst->u[0] = (unsigned)src->d[0];
184 dst->u[1] = (unsigned)src->d[1];
185 dst->u[2] = (unsigned)src->d[2];
186 dst->u[3] = (unsigned)src->d[3];
187 }
188 static void
189 micro_dabs(union tgsi_double_channel *dst,
190 const union tgsi_double_channel *src)
191 {
192 dst->d[0] = src->d[0] >= 0.0 ? src->d[0] : -src->d[0];
193 dst->d[1] = src->d[1] >= 0.0 ? src->d[1] : -src->d[1];
194 dst->d[2] = src->d[2] >= 0.0 ? src->d[2] : -src->d[2];
195 dst->d[3] = src->d[3] >= 0.0 ? src->d[3] : -src->d[3];
196 }
197
198 static void
199 micro_dadd(union tgsi_double_channel *dst,
200 const union tgsi_double_channel *src)
201 {
202 dst->d[0] = src[0].d[0] + src[1].d[0];
203 dst->d[1] = src[0].d[1] + src[1].d[1];
204 dst->d[2] = src[0].d[2] + src[1].d[2];
205 dst->d[3] = src[0].d[3] + src[1].d[3];
206 }
207
208 static void
209 micro_ddx(union tgsi_exec_channel *dst,
210 const union tgsi_exec_channel *src)
211 {
212 dst->f[0] =
213 dst->f[1] =
214 dst->f[2] =
215 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
216 }
217
218 static void
219 micro_ddy(union tgsi_exec_channel *dst,
220 const union tgsi_exec_channel *src)
221 {
222 dst->f[0] =
223 dst->f[1] =
224 dst->f[2] =
225 dst->f[3] = src->f[TILE_BOTTOM_LEFT] - src->f[TILE_TOP_LEFT];
226 }
227
228 static void
229 micro_dmul(union tgsi_double_channel *dst,
230 const union tgsi_double_channel *src)
231 {
232 dst->d[0] = src[0].d[0] * src[1].d[0];
233 dst->d[1] = src[0].d[1] * src[1].d[1];
234 dst->d[2] = src[0].d[2] * src[1].d[2];
235 dst->d[3] = src[0].d[3] * src[1].d[3];
236 }
237
238 static void
239 micro_dmax(union tgsi_double_channel *dst,
240 const union tgsi_double_channel *src)
241 {
242 dst->d[0] = src[0].d[0] > src[1].d[0] ? src[0].d[0] : src[1].d[0];
243 dst->d[1] = src[0].d[1] > src[1].d[1] ? src[0].d[1] : src[1].d[1];
244 dst->d[2] = src[0].d[2] > src[1].d[2] ? src[0].d[2] : src[1].d[2];
245 dst->d[3] = src[0].d[3] > src[1].d[3] ? src[0].d[3] : src[1].d[3];
246 }
247
248 static void
249 micro_dmin(union tgsi_double_channel *dst,
250 const union tgsi_double_channel *src)
251 {
252 dst->d[0] = src[0].d[0] < src[1].d[0] ? src[0].d[0] : src[1].d[0];
253 dst->d[1] = src[0].d[1] < src[1].d[1] ? src[0].d[1] : src[1].d[1];
254 dst->d[2] = src[0].d[2] < src[1].d[2] ? src[0].d[2] : src[1].d[2];
255 dst->d[3] = src[0].d[3] < src[1].d[3] ? src[0].d[3] : src[1].d[3];
256 }
257
258 static void
259 micro_dneg(union tgsi_double_channel *dst,
260 const union tgsi_double_channel *src)
261 {
262 dst->d[0] = -src->d[0];
263 dst->d[1] = -src->d[1];
264 dst->d[2] = -src->d[2];
265 dst->d[3] = -src->d[3];
266 }
267
268 static void
269 micro_dslt(union tgsi_double_channel *dst,
270 const union tgsi_double_channel *src)
271 {
272 dst->u[0][0] = src[0].d[0] < src[1].d[0] ? ~0U : 0U;
273 dst->u[1][0] = src[0].d[1] < src[1].d[1] ? ~0U : 0U;
274 dst->u[2][0] = src[0].d[2] < src[1].d[2] ? ~0U : 0U;
275 dst->u[3][0] = src[0].d[3] < src[1].d[3] ? ~0U : 0U;
276 }
277
278 static void
279 micro_dsne(union tgsi_double_channel *dst,
280 const union tgsi_double_channel *src)
281 {
282 dst->u[0][0] = src[0].d[0] != src[1].d[0] ? ~0U : 0U;
283 dst->u[1][0] = src[0].d[1] != src[1].d[1] ? ~0U : 0U;
284 dst->u[2][0] = src[0].d[2] != src[1].d[2] ? ~0U : 0U;
285 dst->u[3][0] = src[0].d[3] != src[1].d[3] ? ~0U : 0U;
286 }
287
288 static void
289 micro_dsge(union tgsi_double_channel *dst,
290 const union tgsi_double_channel *src)
291 {
292 dst->u[0][0] = src[0].d[0] >= src[1].d[0] ? ~0U : 0U;
293 dst->u[1][0] = src[0].d[1] >= src[1].d[1] ? ~0U : 0U;
294 dst->u[2][0] = src[0].d[2] >= src[1].d[2] ? ~0U : 0U;
295 dst->u[3][0] = src[0].d[3] >= src[1].d[3] ? ~0U : 0U;
296 }
297
298 static void
299 micro_dseq(union tgsi_double_channel *dst,
300 const union tgsi_double_channel *src)
301 {
302 dst->u[0][0] = src[0].d[0] == src[1].d[0] ? ~0U : 0U;
303 dst->u[1][0] = src[0].d[1] == src[1].d[1] ? ~0U : 0U;
304 dst->u[2][0] = src[0].d[2] == src[1].d[2] ? ~0U : 0U;
305 dst->u[3][0] = src[0].d[3] == src[1].d[3] ? ~0U : 0U;
306 }
307
308 static void
309 micro_drcp(union tgsi_double_channel *dst,
310 const union tgsi_double_channel *src)
311 {
312 dst->d[0] = 1.0 / src->d[0];
313 dst->d[1] = 1.0 / src->d[1];
314 dst->d[2] = 1.0 / src->d[2];
315 dst->d[3] = 1.0 / src->d[3];
316 }
317
318 static void
319 micro_dsqrt(union tgsi_double_channel *dst,
320 const union tgsi_double_channel *src)
321 {
322 dst->d[0] = sqrt(src->d[0]);
323 dst->d[1] = sqrt(src->d[1]);
324 dst->d[2] = sqrt(src->d[2]);
325 dst->d[3] = sqrt(src->d[3]);
326 }
327
328 static void
329 micro_drsq(union tgsi_double_channel *dst,
330 const union tgsi_double_channel *src)
331 {
332 dst->d[0] = 1.0 / sqrt(src->d[0]);
333 dst->d[1] = 1.0 / sqrt(src->d[1]);
334 dst->d[2] = 1.0 / sqrt(src->d[2]);
335 dst->d[3] = 1.0 / sqrt(src->d[3]);
336 }
337
338 static void
339 micro_dmad(union tgsi_double_channel *dst,
340 const union tgsi_double_channel *src)
341 {
342 dst->d[0] = src[0].d[0] * src[1].d[0] + src[2].d[0];
343 dst->d[1] = src[0].d[1] * src[1].d[1] + src[2].d[1];
344 dst->d[2] = src[0].d[2] * src[1].d[2] + src[2].d[2];
345 dst->d[3] = src[0].d[3] * src[1].d[3] + src[2].d[3];
346 }
347
348 static void
349 micro_dfrac(union tgsi_double_channel *dst,
350 const union tgsi_double_channel *src)
351 {
352 dst->d[0] = src->d[0] - floor(src->d[0]);
353 dst->d[1] = src->d[1] - floor(src->d[1]);
354 dst->d[2] = src->d[2] - floor(src->d[2]);
355 dst->d[3] = src->d[3] - floor(src->d[3]);
356 }
357
358 static void
359 micro_dldexp(union tgsi_double_channel *dst,
360 const union tgsi_double_channel *src0,
361 union tgsi_exec_channel *src1)
362 {
363 dst->d[0] = ldexp(src0->d[0], src1->i[0]);
364 dst->d[1] = ldexp(src0->d[1], src1->i[1]);
365 dst->d[2] = ldexp(src0->d[2], src1->i[2]);
366 dst->d[3] = ldexp(src0->d[3], src1->i[3]);
367 }
368
369 static void
370 micro_dfracexp(union tgsi_double_channel *dst,
371 union tgsi_exec_channel *dst_exp,
372 const union tgsi_double_channel *src)
373 {
374 dst->d[0] = frexp(src->d[0], &dst_exp->i[0]);
375 dst->d[1] = frexp(src->d[1], &dst_exp->i[1]);
376 dst->d[2] = frexp(src->d[2], &dst_exp->i[2]);
377 dst->d[3] = frexp(src->d[3], &dst_exp->i[3]);
378 }
379
380 static void
381 micro_exp2(union tgsi_exec_channel *dst,
382 const union tgsi_exec_channel *src)
383 {
384 #if FAST_MATH
385 dst->f[0] = util_fast_exp2(src->f[0]);
386 dst->f[1] = util_fast_exp2(src->f[1]);
387 dst->f[2] = util_fast_exp2(src->f[2]);
388 dst->f[3] = util_fast_exp2(src->f[3]);
389 #else
390 #if DEBUG
391 /* Inf is okay for this instruction, so clamp it to silence assertions. */
392 uint i;
393 union tgsi_exec_channel clamped;
394
395 for (i = 0; i < 4; i++) {
396 if (src->f[i] > 127.99999f) {
397 clamped.f[i] = 127.99999f;
398 } else if (src->f[i] < -126.99999f) {
399 clamped.f[i] = -126.99999f;
400 } else {
401 clamped.f[i] = src->f[i];
402 }
403 }
404 src = &clamped;
405 #endif /* DEBUG */
406
407 dst->f[0] = powf(2.0f, src->f[0]);
408 dst->f[1] = powf(2.0f, src->f[1]);
409 dst->f[2] = powf(2.0f, src->f[2]);
410 dst->f[3] = powf(2.0f, src->f[3]);
411 #endif /* FAST_MATH */
412 }
413
414 static void
415 micro_f2d(union tgsi_double_channel *dst,
416 const union tgsi_exec_channel *src)
417 {
418 dst->d[0] = (double)src->f[0];
419 dst->d[1] = (double)src->f[1];
420 dst->d[2] = (double)src->f[2];
421 dst->d[3] = (double)src->f[3];
422 }
423
424 static void
425 micro_flr(union tgsi_exec_channel *dst,
426 const union tgsi_exec_channel *src)
427 {
428 dst->f[0] = floorf(src->f[0]);
429 dst->f[1] = floorf(src->f[1]);
430 dst->f[2] = floorf(src->f[2]);
431 dst->f[3] = floorf(src->f[3]);
432 }
433
434 static void
435 micro_frc(union tgsi_exec_channel *dst,
436 const union tgsi_exec_channel *src)
437 {
438 dst->f[0] = src->f[0] - floorf(src->f[0]);
439 dst->f[1] = src->f[1] - floorf(src->f[1]);
440 dst->f[2] = src->f[2] - floorf(src->f[2]);
441 dst->f[3] = src->f[3] - floorf(src->f[3]);
442 }
443
444 static void
445 micro_i2d(union tgsi_double_channel *dst,
446 const union tgsi_exec_channel *src)
447 {
448 dst->d[0] = (double)src->i[0];
449 dst->d[1] = (double)src->i[1];
450 dst->d[2] = (double)src->i[2];
451 dst->d[3] = (double)src->i[3];
452 }
453
454 static void
455 micro_iabs(union tgsi_exec_channel *dst,
456 const union tgsi_exec_channel *src)
457 {
458 dst->i[0] = src->i[0] >= 0 ? src->i[0] : -src->i[0];
459 dst->i[1] = src->i[1] >= 0 ? src->i[1] : -src->i[1];
460 dst->i[2] = src->i[2] >= 0 ? src->i[2] : -src->i[2];
461 dst->i[3] = src->i[3] >= 0 ? src->i[3] : -src->i[3];
462 }
463
464 static void
465 micro_ineg(union tgsi_exec_channel *dst,
466 const union tgsi_exec_channel *src)
467 {
468 dst->i[0] = -src->i[0];
469 dst->i[1] = -src->i[1];
470 dst->i[2] = -src->i[2];
471 dst->i[3] = -src->i[3];
472 }
473
474 static void
475 micro_lg2(union tgsi_exec_channel *dst,
476 const union tgsi_exec_channel *src)
477 {
478 #if FAST_MATH
479 dst->f[0] = util_fast_log2(src->f[0]);
480 dst->f[1] = util_fast_log2(src->f[1]);
481 dst->f[2] = util_fast_log2(src->f[2]);
482 dst->f[3] = util_fast_log2(src->f[3]);
483 #else
484 dst->f[0] = logf(src->f[0]) * 1.442695f;
485 dst->f[1] = logf(src->f[1]) * 1.442695f;
486 dst->f[2] = logf(src->f[2]) * 1.442695f;
487 dst->f[3] = logf(src->f[3]) * 1.442695f;
488 #endif
489 }
490
491 static void
492 micro_lrp(union tgsi_exec_channel *dst,
493 const union tgsi_exec_channel *src0,
494 const union tgsi_exec_channel *src1,
495 const union tgsi_exec_channel *src2)
496 {
497 dst->f[0] = src0->f[0] * (src1->f[0] - src2->f[0]) + src2->f[0];
498 dst->f[1] = src0->f[1] * (src1->f[1] - src2->f[1]) + src2->f[1];
499 dst->f[2] = src0->f[2] * (src1->f[2] - src2->f[2]) + src2->f[2];
500 dst->f[3] = src0->f[3] * (src1->f[3] - src2->f[3]) + src2->f[3];
501 }
502
503 static void
504 micro_mad(union tgsi_exec_channel *dst,
505 const union tgsi_exec_channel *src0,
506 const union tgsi_exec_channel *src1,
507 const union tgsi_exec_channel *src2)
508 {
509 dst->f[0] = src0->f[0] * src1->f[0] + src2->f[0];
510 dst->f[1] = src0->f[1] * src1->f[1] + src2->f[1];
511 dst->f[2] = src0->f[2] * src1->f[2] + src2->f[2];
512 dst->f[3] = src0->f[3] * src1->f[3] + src2->f[3];
513 }
514
515 static void
516 micro_mov(union tgsi_exec_channel *dst,
517 const union tgsi_exec_channel *src)
518 {
519 dst->u[0] = src->u[0];
520 dst->u[1] = src->u[1];
521 dst->u[2] = src->u[2];
522 dst->u[3] = src->u[3];
523 }
524
525 static void
526 micro_rcp(union tgsi_exec_channel *dst,
527 const union tgsi_exec_channel *src)
528 {
529 #if 0 /* for debugging */
530 assert(src->f[0] != 0.0f);
531 assert(src->f[1] != 0.0f);
532 assert(src->f[2] != 0.0f);
533 assert(src->f[3] != 0.0f);
534 #endif
535 dst->f[0] = 1.0f / src->f[0];
536 dst->f[1] = 1.0f / src->f[1];
537 dst->f[2] = 1.0f / src->f[2];
538 dst->f[3] = 1.0f / src->f[3];
539 }
540
541 static void
542 micro_rnd(union tgsi_exec_channel *dst,
543 const union tgsi_exec_channel *src)
544 {
545 dst->f[0] = floorf(src->f[0] + 0.5f);
546 dst->f[1] = floorf(src->f[1] + 0.5f);
547 dst->f[2] = floorf(src->f[2] + 0.5f);
548 dst->f[3] = floorf(src->f[3] + 0.5f);
549 }
550
551 static void
552 micro_rsq(union tgsi_exec_channel *dst,
553 const union tgsi_exec_channel *src)
554 {
555 #if 0 /* for debugging */
556 assert(src->f[0] != 0.0f);
557 assert(src->f[1] != 0.0f);
558 assert(src->f[2] != 0.0f);
559 assert(src->f[3] != 0.0f);
560 #endif
561 dst->f[0] = 1.0f / sqrtf(src->f[0]);
562 dst->f[1] = 1.0f / sqrtf(src->f[1]);
563 dst->f[2] = 1.0f / sqrtf(src->f[2]);
564 dst->f[3] = 1.0f / sqrtf(src->f[3]);
565 }
566
567 static void
568 micro_sqrt(union tgsi_exec_channel *dst,
569 const union tgsi_exec_channel *src)
570 {
571 dst->f[0] = sqrtf(src->f[0]);
572 dst->f[1] = sqrtf(src->f[1]);
573 dst->f[2] = sqrtf(src->f[2]);
574 dst->f[3] = sqrtf(src->f[3]);
575 }
576
577 static void
578 micro_seq(union tgsi_exec_channel *dst,
579 const union tgsi_exec_channel *src0,
580 const union tgsi_exec_channel *src1)
581 {
582 dst->f[0] = src0->f[0] == src1->f[0] ? 1.0f : 0.0f;
583 dst->f[1] = src0->f[1] == src1->f[1] ? 1.0f : 0.0f;
584 dst->f[2] = src0->f[2] == src1->f[2] ? 1.0f : 0.0f;
585 dst->f[3] = src0->f[3] == src1->f[3] ? 1.0f : 0.0f;
586 }
587
588 static void
589 micro_sge(union tgsi_exec_channel *dst,
590 const union tgsi_exec_channel *src0,
591 const union tgsi_exec_channel *src1)
592 {
593 dst->f[0] = src0->f[0] >= src1->f[0] ? 1.0f : 0.0f;
594 dst->f[1] = src0->f[1] >= src1->f[1] ? 1.0f : 0.0f;
595 dst->f[2] = src0->f[2] >= src1->f[2] ? 1.0f : 0.0f;
596 dst->f[3] = src0->f[3] >= src1->f[3] ? 1.0f : 0.0f;
597 }
598
599 static void
600 micro_sgn(union tgsi_exec_channel *dst,
601 const union tgsi_exec_channel *src)
602 {
603 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
604 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
605 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
606 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
607 }
608
609 static void
610 micro_isgn(union tgsi_exec_channel *dst,
611 const union tgsi_exec_channel *src)
612 {
613 dst->i[0] = src->i[0] < 0 ? -1 : src->i[0] > 0 ? 1 : 0;
614 dst->i[1] = src->i[1] < 0 ? -1 : src->i[1] > 0 ? 1 : 0;
615 dst->i[2] = src->i[2] < 0 ? -1 : src->i[2] > 0 ? 1 : 0;
616 dst->i[3] = src->i[3] < 0 ? -1 : src->i[3] > 0 ? 1 : 0;
617 }
618
619 static void
620 micro_sgt(union tgsi_exec_channel *dst,
621 const union tgsi_exec_channel *src0,
622 const union tgsi_exec_channel *src1)
623 {
624 dst->f[0] = src0->f[0] > src1->f[0] ? 1.0f : 0.0f;
625 dst->f[1] = src0->f[1] > src1->f[1] ? 1.0f : 0.0f;
626 dst->f[2] = src0->f[2] > src1->f[2] ? 1.0f : 0.0f;
627 dst->f[3] = src0->f[3] > src1->f[3] ? 1.0f : 0.0f;
628 }
629
630 static void
631 micro_sin(union tgsi_exec_channel *dst,
632 const union tgsi_exec_channel *src)
633 {
634 dst->f[0] = sinf(src->f[0]);
635 dst->f[1] = sinf(src->f[1]);
636 dst->f[2] = sinf(src->f[2]);
637 dst->f[3] = sinf(src->f[3]);
638 }
639
640 static void
641 micro_sle(union tgsi_exec_channel *dst,
642 const union tgsi_exec_channel *src0,
643 const union tgsi_exec_channel *src1)
644 {
645 dst->f[0] = src0->f[0] <= src1->f[0] ? 1.0f : 0.0f;
646 dst->f[1] = src0->f[1] <= src1->f[1] ? 1.0f : 0.0f;
647 dst->f[2] = src0->f[2] <= src1->f[2] ? 1.0f : 0.0f;
648 dst->f[3] = src0->f[3] <= src1->f[3] ? 1.0f : 0.0f;
649 }
650
651 static void
652 micro_slt(union tgsi_exec_channel *dst,
653 const union tgsi_exec_channel *src0,
654 const union tgsi_exec_channel *src1)
655 {
656 dst->f[0] = src0->f[0] < src1->f[0] ? 1.0f : 0.0f;
657 dst->f[1] = src0->f[1] < src1->f[1] ? 1.0f : 0.0f;
658 dst->f[2] = src0->f[2] < src1->f[2] ? 1.0f : 0.0f;
659 dst->f[3] = src0->f[3] < src1->f[3] ? 1.0f : 0.0f;
660 }
661
662 static void
663 micro_sne(union tgsi_exec_channel *dst,
664 const union tgsi_exec_channel *src0,
665 const union tgsi_exec_channel *src1)
666 {
667 dst->f[0] = src0->f[0] != src1->f[0] ? 1.0f : 0.0f;
668 dst->f[1] = src0->f[1] != src1->f[1] ? 1.0f : 0.0f;
669 dst->f[2] = src0->f[2] != src1->f[2] ? 1.0f : 0.0f;
670 dst->f[3] = src0->f[3] != src1->f[3] ? 1.0f : 0.0f;
671 }
672
673 static void
674 micro_trunc(union tgsi_exec_channel *dst,
675 const union tgsi_exec_channel *src)
676 {
677 dst->f[0] = (float)(int)src->f[0];
678 dst->f[1] = (float)(int)src->f[1];
679 dst->f[2] = (float)(int)src->f[2];
680 dst->f[3] = (float)(int)src->f[3];
681 }
682
683 static void
684 micro_u2d(union tgsi_double_channel *dst,
685 const union tgsi_exec_channel *src)
686 {
687 dst->d[0] = (double)src->u[0];
688 dst->d[1] = (double)src->u[1];
689 dst->d[2] = (double)src->u[2];
690 dst->d[3] = (double)src->u[3];
691 }
692
693 enum tgsi_exec_datatype {
694 TGSI_EXEC_DATA_FLOAT,
695 TGSI_EXEC_DATA_INT,
696 TGSI_EXEC_DATA_UINT,
697 TGSI_EXEC_DATA_DOUBLE
698 };
699
700 /*
701 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
702 */
703 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
704 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
705 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
706 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
707 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
708 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
709
710
711 /** The execution mask depends on the conditional mask and the loop mask */
712 #define UPDATE_EXEC_MASK(MACH) \
713 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
714
715
716 static const union tgsi_exec_channel ZeroVec =
717 { { 0.0, 0.0, 0.0, 0.0 } };
718
719 static const union tgsi_exec_channel OneVec = {
720 {1.0f, 1.0f, 1.0f, 1.0f}
721 };
722
723 static const union tgsi_exec_channel P128Vec = {
724 {128.0f, 128.0f, 128.0f, 128.0f}
725 };
726
727 static const union tgsi_exec_channel M128Vec = {
728 {-128.0f, -128.0f, -128.0f, -128.0f}
729 };
730
731
732 /**
733 * Assert that none of the float values in 'chan' are infinite or NaN.
734 * NaN and Inf may occur normally during program execution and should
735 * not lead to crashes, etc. But when debugging, it's helpful to catch
736 * them.
737 */
738 static INLINE void
739 check_inf_or_nan(const union tgsi_exec_channel *chan)
740 {
741 assert(!util_is_inf_or_nan((chan)->f[0]));
742 assert(!util_is_inf_or_nan((chan)->f[1]));
743 assert(!util_is_inf_or_nan((chan)->f[2]));
744 assert(!util_is_inf_or_nan((chan)->f[3]));
745 }
746
747
748 #ifdef DEBUG
749 static void
750 print_chan(const char *msg, const union tgsi_exec_channel *chan)
751 {
752 debug_printf("%s = {%f, %f, %f, %f}\n",
753 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
754 }
755 #endif
756
757
758 #ifdef DEBUG
759 static void
760 print_temp(const struct tgsi_exec_machine *mach, uint index)
761 {
762 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
763 int i;
764 debug_printf("Temp[%u] =\n", index);
765 for (i = 0; i < 4; i++) {
766 debug_printf(" %c: { %f, %f, %f, %f }\n",
767 "XYZW"[i],
768 tmp->xyzw[i].f[0],
769 tmp->xyzw[i].f[1],
770 tmp->xyzw[i].f[2],
771 tmp->xyzw[i].f[3]);
772 }
773 }
774 #endif
775
776
777 void
778 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine *mach,
779 unsigned num_bufs,
780 const void **bufs,
781 const unsigned *buf_sizes)
782 {
783 unsigned i;
784
785 for (i = 0; i < num_bufs; i++) {
786 mach->Consts[i] = bufs[i];
787 mach->ConstsSize[i] = buf_sizes[i];
788 }
789 }
790
791
792 /**
793 * Check if there's a potential src/dst register data dependency when
794 * using SOA execution.
795 * Example:
796 * MOV T, T.yxwz;
797 * This would expand into:
798 * MOV t0, t1;
799 * MOV t1, t0;
800 * MOV t2, t3;
801 * MOV t3, t2;
802 * The second instruction will have the wrong value for t0 if executed as-is.
803 */
804 boolean
805 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
806 {
807 uint i, chan;
808
809 uint writemask = inst->Dst[0].Register.WriteMask;
810 if (writemask == TGSI_WRITEMASK_X ||
811 writemask == TGSI_WRITEMASK_Y ||
812 writemask == TGSI_WRITEMASK_Z ||
813 writemask == TGSI_WRITEMASK_W ||
814 writemask == TGSI_WRITEMASK_NONE) {
815 /* no chance of data dependency */
816 return FALSE;
817 }
818
819 /* loop over src regs */
820 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
821 if ((inst->Src[i].Register.File ==
822 inst->Dst[0].Register.File) &&
823 ((inst->Src[i].Register.Index ==
824 inst->Dst[0].Register.Index) ||
825 inst->Src[i].Register.Indirect ||
826 inst->Dst[0].Register.Indirect)) {
827 /* loop over dest channels */
828 uint channelsWritten = 0x0;
829 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
830 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
831 /* check if we're reading a channel that's been written */
832 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
833 if (channelsWritten & (1 << swizzle)) {
834 return TRUE;
835 }
836
837 channelsWritten |= (1 << chan);
838 }
839 }
840 }
841 }
842 return FALSE;
843 }
844
845
846 /**
847 * Initialize machine state by expanding tokens to full instructions,
848 * allocating temporary storage, setting up constants, etc.
849 * After this, we can call tgsi_exec_machine_run() many times.
850 */
851 void
852 tgsi_exec_machine_bind_shader(
853 struct tgsi_exec_machine *mach,
854 const struct tgsi_token *tokens,
855 struct tgsi_sampler *sampler)
856 {
857 uint k;
858 struct tgsi_parse_context parse;
859 struct tgsi_full_instruction *instructions;
860 struct tgsi_full_declaration *declarations;
861 uint maxInstructions = 10, numInstructions = 0;
862 uint maxDeclarations = 10, numDeclarations = 0;
863
864 #if 0
865 tgsi_dump(tokens, 0);
866 #endif
867
868 util_init_math();
869
870
871 mach->Tokens = tokens;
872 mach->Sampler = sampler;
873
874 if (!tokens) {
875 /* unbind and free all */
876 FREE(mach->Declarations);
877 mach->Declarations = NULL;
878 mach->NumDeclarations = 0;
879
880 FREE(mach->Instructions);
881 mach->Instructions = NULL;
882 mach->NumInstructions = 0;
883
884 return;
885 }
886
887 k = tgsi_parse_init (&parse, mach->Tokens);
888 if (k != TGSI_PARSE_OK) {
889 debug_printf( "Problem parsing!\n" );
890 return;
891 }
892
893 mach->Processor = parse.FullHeader.Processor.Processor;
894 mach->ImmLimit = 0;
895 mach->NumOutputs = 0;
896
897 if (mach->Processor == TGSI_PROCESSOR_GEOMETRY &&
898 !mach->UsedGeometryShader) {
899 struct tgsi_exec_vector *inputs;
900 struct tgsi_exec_vector *outputs;
901
902 inputs = align_malloc(sizeof(struct tgsi_exec_vector) *
903 TGSI_MAX_PRIM_VERTICES * PIPE_MAX_SHADER_INPUTS,
904 16);
905
906 if (!inputs)
907 return;
908
909 outputs = align_malloc(sizeof(struct tgsi_exec_vector) *
910 TGSI_MAX_TOTAL_VERTICES, 16);
911
912 if (!outputs) {
913 align_free(inputs);
914 return;
915 }
916
917 align_free(mach->Inputs);
918 align_free(mach->Outputs);
919
920 mach->Inputs = inputs;
921 mach->Outputs = outputs;
922 mach->UsedGeometryShader = TRUE;
923 }
924
925 declarations = (struct tgsi_full_declaration *)
926 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
927
928 if (!declarations) {
929 return;
930 }
931
932 instructions = (struct tgsi_full_instruction *)
933 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
934
935 if (!instructions) {
936 FREE( declarations );
937 return;
938 }
939
940 while( !tgsi_parse_end_of_tokens( &parse ) ) {
941 uint i;
942
943 tgsi_parse_token( &parse );
944 switch( parse.FullToken.Token.Type ) {
945 case TGSI_TOKEN_TYPE_DECLARATION:
946 /* save expanded declaration */
947 if (numDeclarations == maxDeclarations) {
948 declarations = REALLOC(declarations,
949 maxDeclarations
950 * sizeof(struct tgsi_full_declaration),
951 (maxDeclarations + 10)
952 * sizeof(struct tgsi_full_declaration));
953 maxDeclarations += 10;
954 }
955 if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_OUTPUT) {
956 unsigned reg;
957 for (reg = parse.FullToken.FullDeclaration.Range.First;
958 reg <= parse.FullToken.FullDeclaration.Range.Last;
959 ++reg) {
960 ++mach->NumOutputs;
961 }
962 }
963 memcpy(declarations + numDeclarations,
964 &parse.FullToken.FullDeclaration,
965 sizeof(declarations[0]));
966 numDeclarations++;
967 break;
968
969 case TGSI_TOKEN_TYPE_IMMEDIATE:
970 {
971 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
972 assert( size <= 4 );
973 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
974
975 for( i = 0; i < size; i++ ) {
976 mach->Imms[mach->ImmLimit][i] =
977 parse.FullToken.FullImmediate.u[i].Float;
978 }
979 mach->ImmLimit += 1;
980 }
981 break;
982
983 case TGSI_TOKEN_TYPE_INSTRUCTION:
984
985 /* save expanded instruction */
986 if (numInstructions == maxInstructions) {
987 instructions = REALLOC(instructions,
988 maxInstructions
989 * sizeof(struct tgsi_full_instruction),
990 (maxInstructions + 10)
991 * sizeof(struct tgsi_full_instruction));
992 maxInstructions += 10;
993 }
994
995 memcpy(instructions + numInstructions,
996 &parse.FullToken.FullInstruction,
997 sizeof(instructions[0]));
998
999 numInstructions++;
1000 break;
1001
1002 case TGSI_TOKEN_TYPE_PROPERTY:
1003 if (mach->Processor == TGSI_PROCESSOR_GEOMETRY) {
1004 if (parse.FullToken.FullProperty.Property.PropertyName == TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES) {
1005 mach->MaxOutputVertices = parse.FullToken.FullProperty.u[0].Data;
1006 }
1007 }
1008 break;
1009
1010 default:
1011 assert( 0 );
1012 }
1013 }
1014 tgsi_parse_free (&parse);
1015
1016 FREE(mach->Declarations);
1017 mach->Declarations = declarations;
1018 mach->NumDeclarations = numDeclarations;
1019
1020 FREE(mach->Instructions);
1021 mach->Instructions = instructions;
1022 mach->NumInstructions = numInstructions;
1023 }
1024
1025
1026 struct tgsi_exec_machine *
1027 tgsi_exec_machine_create( void )
1028 {
1029 struct tgsi_exec_machine *mach;
1030 uint i;
1031
1032 mach = align_malloc( sizeof *mach, 16 );
1033 if (!mach)
1034 goto fail;
1035
1036 memset(mach, 0, sizeof(*mach));
1037
1038 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
1039 mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
1040 mach->Predicates = &mach->Temps[TGSI_EXEC_TEMP_P0];
1041
1042 mach->Inputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_INPUTS, 16);
1043 mach->Outputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_OUTPUTS, 16);
1044 if (!mach->Inputs || !mach->Outputs)
1045 goto fail;
1046
1047 /* Setup constants needed by the SSE2 executor. */
1048 for( i = 0; i < 4; i++ ) {
1049 mach->Temps[TGSI_EXEC_TEMP_00000000_I].xyzw[TGSI_EXEC_TEMP_00000000_C].u[i] = 0x00000000;
1050 mach->Temps[TGSI_EXEC_TEMP_7FFFFFFF_I].xyzw[TGSI_EXEC_TEMP_7FFFFFFF_C].u[i] = 0x7FFFFFFF;
1051 mach->Temps[TGSI_EXEC_TEMP_80000000_I].xyzw[TGSI_EXEC_TEMP_80000000_C].u[i] = 0x80000000;
1052 mach->Temps[TGSI_EXEC_TEMP_FFFFFFFF_I].xyzw[TGSI_EXEC_TEMP_FFFFFFFF_C].u[i] = 0xFFFFFFFF; /* not used */
1053 mach->Temps[TGSI_EXEC_TEMP_ONE_I].xyzw[TGSI_EXEC_TEMP_ONE_C].f[i] = 1.0f;
1054 mach->Temps[TGSI_EXEC_TEMP_TWO_I].xyzw[TGSI_EXEC_TEMP_TWO_C].f[i] = 2.0f; /* not used */
1055 mach->Temps[TGSI_EXEC_TEMP_128_I].xyzw[TGSI_EXEC_TEMP_128_C].f[i] = 128.0f;
1056 mach->Temps[TGSI_EXEC_TEMP_MINUS_128_I].xyzw[TGSI_EXEC_TEMP_MINUS_128_C].f[i] = -128.0f;
1057 mach->Temps[TGSI_EXEC_TEMP_THREE_I].xyzw[TGSI_EXEC_TEMP_THREE_C].f[i] = 3.0f;
1058 mach->Temps[TGSI_EXEC_TEMP_HALF_I].xyzw[TGSI_EXEC_TEMP_HALF_C].f[i] = 0.5f;
1059 }
1060
1061 #ifdef DEBUG
1062 /* silence warnings */
1063 (void) print_chan;
1064 (void) print_temp;
1065 #endif
1066
1067 return mach;
1068
1069 fail:
1070 if (mach) {
1071 align_free(mach->Inputs);
1072 align_free(mach->Outputs);
1073 align_free(mach);
1074 }
1075 return NULL;
1076 }
1077
1078
1079 void
1080 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
1081 {
1082 if (mach) {
1083 FREE(mach->Instructions);
1084 FREE(mach->Declarations);
1085
1086 align_free(mach->Inputs);
1087 align_free(mach->Outputs);
1088
1089 align_free(mach);
1090 }
1091 }
1092
1093 static void
1094 micro_add(union tgsi_exec_channel *dst,
1095 const union tgsi_exec_channel *src0,
1096 const union tgsi_exec_channel *src1)
1097 {
1098 dst->f[0] = src0->f[0] + src1->f[0];
1099 dst->f[1] = src0->f[1] + src1->f[1];
1100 dst->f[2] = src0->f[2] + src1->f[2];
1101 dst->f[3] = src0->f[3] + src1->f[3];
1102 }
1103
1104 static void
1105 micro_div(
1106 union tgsi_exec_channel *dst,
1107 const union tgsi_exec_channel *src0,
1108 const union tgsi_exec_channel *src1 )
1109 {
1110 if (src1->f[0] != 0) {
1111 dst->f[0] = src0->f[0] / src1->f[0];
1112 }
1113 if (src1->f[1] != 0) {
1114 dst->f[1] = src0->f[1] / src1->f[1];
1115 }
1116 if (src1->f[2] != 0) {
1117 dst->f[2] = src0->f[2] / src1->f[2];
1118 }
1119 if (src1->f[3] != 0) {
1120 dst->f[3] = src0->f[3] / src1->f[3];
1121 }
1122 }
1123
1124 static void
1125 micro_lt(
1126 union tgsi_exec_channel *dst,
1127 const union tgsi_exec_channel *src0,
1128 const union tgsi_exec_channel *src1,
1129 const union tgsi_exec_channel *src2,
1130 const union tgsi_exec_channel *src3 )
1131 {
1132 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
1133 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
1134 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
1135 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
1136 }
1137
1138 static void
1139 micro_max(union tgsi_exec_channel *dst,
1140 const union tgsi_exec_channel *src0,
1141 const union tgsi_exec_channel *src1)
1142 {
1143 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
1144 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
1145 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
1146 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
1147 }
1148
1149 static void
1150 micro_min(union tgsi_exec_channel *dst,
1151 const union tgsi_exec_channel *src0,
1152 const union tgsi_exec_channel *src1)
1153 {
1154 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
1155 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
1156 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
1157 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
1158 }
1159
1160 static void
1161 micro_mul(union tgsi_exec_channel *dst,
1162 const union tgsi_exec_channel *src0,
1163 const union tgsi_exec_channel *src1)
1164 {
1165 dst->f[0] = src0->f[0] * src1->f[0];
1166 dst->f[1] = src0->f[1] * src1->f[1];
1167 dst->f[2] = src0->f[2] * src1->f[2];
1168 dst->f[3] = src0->f[3] * src1->f[3];
1169 }
1170
1171 static void
1172 micro_neg(
1173 union tgsi_exec_channel *dst,
1174 const union tgsi_exec_channel *src )
1175 {
1176 dst->f[0] = -src->f[0];
1177 dst->f[1] = -src->f[1];
1178 dst->f[2] = -src->f[2];
1179 dst->f[3] = -src->f[3];
1180 }
1181
1182 static void
1183 micro_pow(
1184 union tgsi_exec_channel *dst,
1185 const union tgsi_exec_channel *src0,
1186 const union tgsi_exec_channel *src1 )
1187 {
1188 #if FAST_MATH
1189 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
1190 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
1191 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
1192 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
1193 #else
1194 dst->f[0] = powf( src0->f[0], src1->f[0] );
1195 dst->f[1] = powf( src0->f[1], src1->f[1] );
1196 dst->f[2] = powf( src0->f[2], src1->f[2] );
1197 dst->f[3] = powf( src0->f[3], src1->f[3] );
1198 #endif
1199 }
1200
1201 static void
1202 micro_sub(union tgsi_exec_channel *dst,
1203 const union tgsi_exec_channel *src0,
1204 const union tgsi_exec_channel *src1)
1205 {
1206 dst->f[0] = src0->f[0] - src1->f[0];
1207 dst->f[1] = src0->f[1] - src1->f[1];
1208 dst->f[2] = src0->f[2] - src1->f[2];
1209 dst->f[3] = src0->f[3] - src1->f[3];
1210 }
1211
1212 static void
1213 fetch_src_file_channel(const struct tgsi_exec_machine *mach,
1214 const uint chan_index,
1215 const uint file,
1216 const uint swizzle,
1217 const union tgsi_exec_channel *index,
1218 const union tgsi_exec_channel *index2D,
1219 union tgsi_exec_channel *chan)
1220 {
1221 uint i;
1222
1223 assert(swizzle < 4);
1224
1225 switch (file) {
1226 case TGSI_FILE_CONSTANT:
1227 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1228 assert(index2D->i[i] >= 0 && index2D->i[i] < PIPE_MAX_CONSTANT_BUFFERS);
1229 assert(mach->Consts[index2D->i[i]]);
1230
1231 if (index->i[i] < 0) {
1232 chan->u[i] = 0;
1233 } else {
1234 /* NOTE: copying the const value as a uint instead of float */
1235 const uint constbuf = index2D->i[i];
1236 const uint *buf = (const uint *)mach->Consts[constbuf];
1237 const int pos = index->i[i] * 4 + swizzle;
1238 /* const buffer bounds check */
1239 if (pos < 0 || pos >= (int) mach->ConstsSize[constbuf]) {
1240 if (0) {
1241 /* Debug: print warning */
1242 static int count = 0;
1243 if (count++ < 100)
1244 debug_printf("TGSI Exec: const buffer index %d"
1245 " out of bounds\n", pos);
1246 }
1247 chan->u[i] = 0;
1248 }
1249 else
1250 chan->u[i] = buf[pos];
1251 }
1252 }
1253 break;
1254
1255 case TGSI_FILE_INPUT:
1256 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1257 /*
1258 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1259 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1260 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1261 index2D->i[i], index->i[i]);
1262 }*/
1263 int pos = index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i];
1264 assert(pos >= 0);
1265 assert(pos < TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS);
1266 chan->u[i] = mach->Inputs[pos].xyzw[swizzle].u[i];
1267 }
1268 break;
1269
1270 case TGSI_FILE_SYSTEM_VALUE:
1271 /* XXX no swizzling at this point. Will be needed if we put
1272 * gl_FragCoord, for example, in a sys value register.
1273 */
1274 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1275 chan->u[i] = mach->SystemValue[index->i[i]].u[i];
1276 }
1277 break;
1278
1279 case TGSI_FILE_TEMPORARY:
1280 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1281 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1282 assert(index2D->i[i] == 0);
1283
1284 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1285 }
1286 break;
1287
1288 case TGSI_FILE_IMMEDIATE:
1289 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1290 assert(index->i[i] >= 0 && index->i[i] < (int)mach->ImmLimit);
1291 assert(index2D->i[i] == 0);
1292
1293 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1294 }
1295 break;
1296
1297 case TGSI_FILE_ADDRESS:
1298 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1299 assert(index->i[i] >= 0);
1300 assert(index2D->i[i] == 0);
1301
1302 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1303 }
1304 break;
1305
1306 case TGSI_FILE_PREDICATE:
1307 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1308 assert(index->i[i] >= 0 && index->i[i] < TGSI_EXEC_NUM_PREDS);
1309 assert(index2D->i[i] == 0);
1310
1311 chan->u[i] = mach->Predicates[0].xyzw[swizzle].u[i];
1312 }
1313 break;
1314
1315 case TGSI_FILE_OUTPUT:
1316 /* vertex/fragment output vars can be read too */
1317 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1318 assert(index->i[i] >= 0);
1319 assert(index2D->i[i] == 0);
1320
1321 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1322 }
1323 break;
1324
1325 default:
1326 assert(0);
1327 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1328 chan->u[i] = 0;
1329 }
1330 }
1331 }
1332
1333 static void
1334 fetch_source_d(const struct tgsi_exec_machine *mach,
1335 union tgsi_exec_channel *chan,
1336 const struct tgsi_full_src_register *reg,
1337 const uint chan_index,
1338 enum tgsi_exec_datatype src_datatype)
1339 {
1340 union tgsi_exec_channel index;
1341 union tgsi_exec_channel index2D;
1342 uint swizzle;
1343
1344 /* We start with a direct index into a register file.
1345 *
1346 * file[1],
1347 * where:
1348 * file = Register.File
1349 * [1] = Register.Index
1350 */
1351 index.i[0] =
1352 index.i[1] =
1353 index.i[2] =
1354 index.i[3] = reg->Register.Index;
1355
1356 /* There is an extra source register that indirectly subscripts
1357 * a register file. The direct index now becomes an offset
1358 * that is being added to the indirect register.
1359 *
1360 * file[ind[2].x+1],
1361 * where:
1362 * ind = Indirect.File
1363 * [2] = Indirect.Index
1364 * .x = Indirect.SwizzleX
1365 */
1366 if (reg->Register.Indirect) {
1367 union tgsi_exec_channel index2;
1368 union tgsi_exec_channel indir_index;
1369 const uint execmask = mach->ExecMask;
1370 uint i;
1371
1372 /* which address register (always zero now) */
1373 index2.i[0] =
1374 index2.i[1] =
1375 index2.i[2] =
1376 index2.i[3] = reg->Indirect.Index;
1377 /* get current value of address register[swizzle] */
1378 swizzle = reg->Indirect.Swizzle;
1379 fetch_src_file_channel(mach,
1380 chan_index,
1381 reg->Indirect.File,
1382 swizzle,
1383 &index2,
1384 &ZeroVec,
1385 &indir_index);
1386
1387 /* add value of address register to the offset */
1388 index.i[0] += indir_index.i[0];
1389 index.i[1] += indir_index.i[1];
1390 index.i[2] += indir_index.i[2];
1391 index.i[3] += indir_index.i[3];
1392
1393 /* for disabled execution channels, zero-out the index to
1394 * avoid using a potential garbage value.
1395 */
1396 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1397 if ((execmask & (1 << i)) == 0)
1398 index.i[i] = 0;
1399 }
1400 }
1401
1402 /* There is an extra source register that is a second
1403 * subscript to a register file. Effectively it means that
1404 * the register file is actually a 2D array of registers.
1405 *
1406 * file[3][1],
1407 * where:
1408 * [3] = Dimension.Index
1409 */
1410 if (reg->Register.Dimension) {
1411 index2D.i[0] =
1412 index2D.i[1] =
1413 index2D.i[2] =
1414 index2D.i[3] = reg->Dimension.Index;
1415
1416 /* Again, the second subscript index can be addressed indirectly
1417 * identically to the first one.
1418 * Nothing stops us from indirectly addressing the indirect register,
1419 * but there is no need for that, so we won't exercise it.
1420 *
1421 * file[ind[4].y+3][1],
1422 * where:
1423 * ind = DimIndirect.File
1424 * [4] = DimIndirect.Index
1425 * .y = DimIndirect.SwizzleX
1426 */
1427 if (reg->Dimension.Indirect) {
1428 union tgsi_exec_channel index2;
1429 union tgsi_exec_channel indir_index;
1430 const uint execmask = mach->ExecMask;
1431 uint i;
1432
1433 index2.i[0] =
1434 index2.i[1] =
1435 index2.i[2] =
1436 index2.i[3] = reg->DimIndirect.Index;
1437
1438 swizzle = reg->DimIndirect.Swizzle;
1439 fetch_src_file_channel(mach,
1440 chan_index,
1441 reg->DimIndirect.File,
1442 swizzle,
1443 &index2,
1444 &ZeroVec,
1445 &indir_index);
1446
1447 index2D.i[0] += indir_index.i[0];
1448 index2D.i[1] += indir_index.i[1];
1449 index2D.i[2] += indir_index.i[2];
1450 index2D.i[3] += indir_index.i[3];
1451
1452 /* for disabled execution channels, zero-out the index to
1453 * avoid using a potential garbage value.
1454 */
1455 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1456 if ((execmask & (1 << i)) == 0) {
1457 index2D.i[i] = 0;
1458 }
1459 }
1460 }
1461
1462 /* If by any chance there was a need for a 3D array of register
1463 * files, we would have to check whether Dimension is followed
1464 * by a dimension register and continue the saga.
1465 */
1466 } else {
1467 index2D.i[0] =
1468 index2D.i[1] =
1469 index2D.i[2] =
1470 index2D.i[3] = 0;
1471 }
1472
1473 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1474 fetch_src_file_channel(mach,
1475 chan_index,
1476 reg->Register.File,
1477 swizzle,
1478 &index,
1479 &index2D,
1480 chan);
1481 }
1482
1483 static void
1484 fetch_source(const struct tgsi_exec_machine *mach,
1485 union tgsi_exec_channel *chan,
1486 const struct tgsi_full_src_register *reg,
1487 const uint chan_index,
1488 enum tgsi_exec_datatype src_datatype)
1489 {
1490 fetch_source_d(mach, chan, reg, chan_index, src_datatype);
1491
1492 if (reg->Register.Absolute) {
1493 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1494 micro_abs(chan, chan);
1495 } else {
1496 micro_iabs(chan, chan);
1497 }
1498 }
1499
1500 if (reg->Register.Negate) {
1501 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1502 micro_neg(chan, chan);
1503 } else {
1504 micro_ineg(chan, chan);
1505 }
1506 }
1507 }
1508
1509 static union tgsi_exec_channel *
1510 store_dest_dstret(struct tgsi_exec_machine *mach,
1511 const union tgsi_exec_channel *chan,
1512 const struct tgsi_full_dst_register *reg,
1513 const struct tgsi_full_instruction *inst,
1514 uint chan_index,
1515 enum tgsi_exec_datatype dst_datatype)
1516 {
1517 uint i;
1518 static union tgsi_exec_channel null;
1519 union tgsi_exec_channel *dst;
1520 union tgsi_exec_channel index2D;
1521 uint execmask = mach->ExecMask;
1522 int offset = 0; /* indirection offset */
1523 int index;
1524
1525 /* for debugging */
1526 if (0 && dst_datatype == TGSI_EXEC_DATA_FLOAT) {
1527 check_inf_or_nan(chan);
1528 }
1529
1530 /* There is an extra source register that indirectly subscripts
1531 * a register file. The direct index now becomes an offset
1532 * that is being added to the indirect register.
1533 *
1534 * file[ind[2].x+1],
1535 * where:
1536 * ind = Indirect.File
1537 * [2] = Indirect.Index
1538 * .x = Indirect.SwizzleX
1539 */
1540 if (reg->Register.Indirect) {
1541 union tgsi_exec_channel index;
1542 union tgsi_exec_channel indir_index;
1543 uint swizzle;
1544
1545 /* which address register (always zero for now) */
1546 index.i[0] =
1547 index.i[1] =
1548 index.i[2] =
1549 index.i[3] = reg->Indirect.Index;
1550
1551 /* get current value of address register[swizzle] */
1552 swizzle = reg->Indirect.Swizzle;
1553
1554 /* fetch values from the address/indirection register */
1555 fetch_src_file_channel(mach,
1556 chan_index,
1557 reg->Indirect.File,
1558 swizzle,
1559 &index,
1560 &ZeroVec,
1561 &indir_index);
1562
1563 /* save indirection offset */
1564 offset = indir_index.i[0];
1565 }
1566
1567 /* There is an extra source register that is a second
1568 * subscript to a register file. Effectively it means that
1569 * the register file is actually a 2D array of registers.
1570 *
1571 * file[3][1],
1572 * where:
1573 * [3] = Dimension.Index
1574 */
1575 if (reg->Register.Dimension) {
1576 index2D.i[0] =
1577 index2D.i[1] =
1578 index2D.i[2] =
1579 index2D.i[3] = reg->Dimension.Index;
1580
1581 /* Again, the second subscript index can be addressed indirectly
1582 * identically to the first one.
1583 * Nothing stops us from indirectly addressing the indirect register,
1584 * but there is no need for that, so we won't exercise it.
1585 *
1586 * file[ind[4].y+3][1],
1587 * where:
1588 * ind = DimIndirect.File
1589 * [4] = DimIndirect.Index
1590 * .y = DimIndirect.SwizzleX
1591 */
1592 if (reg->Dimension.Indirect) {
1593 union tgsi_exec_channel index2;
1594 union tgsi_exec_channel indir_index;
1595 const uint execmask = mach->ExecMask;
1596 unsigned swizzle;
1597 uint i;
1598
1599 index2.i[0] =
1600 index2.i[1] =
1601 index2.i[2] =
1602 index2.i[3] = reg->DimIndirect.Index;
1603
1604 swizzle = reg->DimIndirect.Swizzle;
1605 fetch_src_file_channel(mach,
1606 chan_index,
1607 reg->DimIndirect.File,
1608 swizzle,
1609 &index2,
1610 &ZeroVec,
1611 &indir_index);
1612
1613 index2D.i[0] += indir_index.i[0];
1614 index2D.i[1] += indir_index.i[1];
1615 index2D.i[2] += indir_index.i[2];
1616 index2D.i[3] += indir_index.i[3];
1617
1618 /* for disabled execution channels, zero-out the index to
1619 * avoid using a potential garbage value.
1620 */
1621 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1622 if ((execmask & (1 << i)) == 0) {
1623 index2D.i[i] = 0;
1624 }
1625 }
1626 }
1627
1628 /* If by any chance there was a need for a 3D array of register
1629 * files, we would have to check whether Dimension is followed
1630 * by a dimension register and continue the saga.
1631 */
1632 } else {
1633 index2D.i[0] =
1634 index2D.i[1] =
1635 index2D.i[2] =
1636 index2D.i[3] = 0;
1637 }
1638
1639 switch (reg->Register.File) {
1640 case TGSI_FILE_NULL:
1641 dst = &null;
1642 break;
1643
1644 case TGSI_FILE_OUTPUT:
1645 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1646 + reg->Register.Index;
1647 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1648 #if 0
1649 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1650 mach->NumOutputs, mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0],
1651 reg->Register.Index);
1652 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1653 debug_printf("STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1654 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1655 if (execmask & (1 << i))
1656 debug_printf("%f, ", chan->f[i]);
1657 debug_printf(")\n");
1658 }
1659 #endif
1660 break;
1661
1662 case TGSI_FILE_TEMPORARY:
1663 index = reg->Register.Index;
1664 assert( index < TGSI_EXEC_NUM_TEMPS );
1665 dst = &mach->Temps[offset + index].xyzw[chan_index];
1666 break;
1667
1668 case TGSI_FILE_ADDRESS:
1669 index = reg->Register.Index;
1670 dst = &mach->Addrs[index].xyzw[chan_index];
1671 break;
1672
1673 case TGSI_FILE_PREDICATE:
1674 index = reg->Register.Index;
1675 assert(index < TGSI_EXEC_NUM_PREDS);
1676 dst = &mach->Predicates[index].xyzw[chan_index];
1677 break;
1678
1679 default:
1680 assert( 0 );
1681 return NULL;
1682 }
1683
1684 if (inst->Instruction.Predicate) {
1685 uint swizzle;
1686 union tgsi_exec_channel *pred;
1687
1688 switch (chan_index) {
1689 case TGSI_CHAN_X:
1690 swizzle = inst->Predicate.SwizzleX;
1691 break;
1692 case TGSI_CHAN_Y:
1693 swizzle = inst->Predicate.SwizzleY;
1694 break;
1695 case TGSI_CHAN_Z:
1696 swizzle = inst->Predicate.SwizzleZ;
1697 break;
1698 case TGSI_CHAN_W:
1699 swizzle = inst->Predicate.SwizzleW;
1700 break;
1701 default:
1702 assert(0);
1703 return NULL;
1704 }
1705
1706 assert(inst->Predicate.Index == 0);
1707
1708 pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
1709
1710 if (inst->Predicate.Negate) {
1711 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1712 if (pred->u[i]) {
1713 execmask &= ~(1 << i);
1714 }
1715 }
1716 } else {
1717 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1718 if (!pred->u[i]) {
1719 execmask &= ~(1 << i);
1720 }
1721 }
1722 }
1723 }
1724
1725 return dst;
1726 }
1727
1728 static void
1729 store_dest_double(struct tgsi_exec_machine *mach,
1730 const union tgsi_exec_channel *chan,
1731 const struct tgsi_full_dst_register *reg,
1732 const struct tgsi_full_instruction *inst,
1733 uint chan_index,
1734 enum tgsi_exec_datatype dst_datatype)
1735 {
1736 union tgsi_exec_channel *dst;
1737 const uint execmask = mach->ExecMask;
1738 int i;
1739
1740 dst = store_dest_dstret(mach, chan, reg, inst, chan_index,
1741 dst_datatype);
1742 if (!dst)
1743 return;
1744
1745 /* doubles path */
1746 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1747 if (execmask & (1 << i))
1748 dst->i[i] = chan->i[i];
1749 }
1750
1751 static void
1752 store_dest(struct tgsi_exec_machine *mach,
1753 const union tgsi_exec_channel *chan,
1754 const struct tgsi_full_dst_register *reg,
1755 const struct tgsi_full_instruction *inst,
1756 uint chan_index,
1757 enum tgsi_exec_datatype dst_datatype)
1758 {
1759 union tgsi_exec_channel *dst;
1760 const uint execmask = mach->ExecMask;
1761 int i;
1762
1763 dst = store_dest_dstret(mach, chan, reg, inst, chan_index,
1764 dst_datatype);
1765 if (!dst)
1766 return;
1767
1768 if (!inst->Instruction.Saturate) {
1769 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1770 if (execmask & (1 << i))
1771 dst->i[i] = chan->i[i];
1772 }
1773 else {
1774 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1775 if (execmask & (1 << i)) {
1776 if (chan->f[i] < 0.0f)
1777 dst->f[i] = 0.0f;
1778 else if (chan->f[i] > 1.0f)
1779 dst->f[i] = 1.0f;
1780 else
1781 dst->i[i] = chan->i[i];
1782 }
1783 }
1784 }
1785
1786 #define FETCH(VAL,INDEX,CHAN)\
1787 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1788
1789 #define IFETCH(VAL,INDEX,CHAN)\
1790 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1791
1792
1793 /**
1794 * Execute ARB-style KIL which is predicated by a src register.
1795 * Kill fragment if any of the four values is less than zero.
1796 */
1797 static void
1798 exec_kill_if(struct tgsi_exec_machine *mach,
1799 const struct tgsi_full_instruction *inst)
1800 {
1801 uint uniquemask;
1802 uint chan_index;
1803 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1804 union tgsi_exec_channel r[1];
1805
1806 /* This mask stores component bits that were already tested. */
1807 uniquemask = 0;
1808
1809 for (chan_index = 0; chan_index < 4; chan_index++)
1810 {
1811 uint swizzle;
1812 uint i;
1813
1814 /* unswizzle channel */
1815 swizzle = tgsi_util_get_full_src_register_swizzle (
1816 &inst->Src[0],
1817 chan_index);
1818
1819 /* check if the component has not been already tested */
1820 if (uniquemask & (1 << swizzle))
1821 continue;
1822 uniquemask |= 1 << swizzle;
1823
1824 FETCH(&r[0], 0, chan_index);
1825 for (i = 0; i < 4; i++)
1826 if (r[0].f[i] < 0.0f)
1827 kilmask |= 1 << i;
1828 }
1829
1830 /* restrict to fragments currently executing */
1831 kilmask &= mach->ExecMask;
1832
1833 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1834 }
1835
1836 /**
1837 * Unconditional fragment kill/discard.
1838 */
1839 static void
1840 exec_kill(struct tgsi_exec_machine *mach,
1841 const struct tgsi_full_instruction *inst)
1842 {
1843 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1844
1845 /* kill fragment for all fragments currently executing */
1846 kilmask = mach->ExecMask;
1847 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1848 }
1849
1850 static void
1851 emit_vertex(struct tgsi_exec_machine *mach)
1852 {
1853 /* FIXME: check for exec mask correctly
1854 unsigned i;
1855 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1856 if ((mach->ExecMask & (1 << i)))
1857 */
1858 if (mach->ExecMask) {
1859 if (mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]] >= mach->MaxOutputVertices)
1860 return;
1861
1862 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += mach->NumOutputs;
1863 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
1864 }
1865 }
1866
1867 static void
1868 emit_primitive(struct tgsi_exec_machine *mach)
1869 {
1870 unsigned *prim_count = &mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0];
1871 /* FIXME: check for exec mask correctly
1872 unsigned i;
1873 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1874 if ((mach->ExecMask & (1 << i)))
1875 */
1876 if (mach->ExecMask) {
1877 ++(*prim_count);
1878 debug_assert((*prim_count * mach->NumOutputs) < mach->MaxGeometryShaderOutputs);
1879 mach->Primitives[*prim_count] = 0;
1880 }
1881 }
1882
1883 static void
1884 conditional_emit_primitive(struct tgsi_exec_machine *mach)
1885 {
1886 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1887 int emitted_verts =
1888 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]];
1889 if (emitted_verts) {
1890 emit_primitive(mach);
1891 }
1892 }
1893 }
1894
1895
1896 /*
1897 * Fetch four texture samples using STR texture coordinates.
1898 */
1899 static void
1900 fetch_texel( struct tgsi_sampler *sampler,
1901 const unsigned sview_idx,
1902 const unsigned sampler_idx,
1903 const union tgsi_exec_channel *s,
1904 const union tgsi_exec_channel *t,
1905 const union tgsi_exec_channel *p,
1906 const union tgsi_exec_channel *c0,
1907 const union tgsi_exec_channel *c1,
1908 float derivs[3][2][TGSI_QUAD_SIZE],
1909 const int8_t offset[3],
1910 enum tgsi_sampler_control control,
1911 union tgsi_exec_channel *r,
1912 union tgsi_exec_channel *g,
1913 union tgsi_exec_channel *b,
1914 union tgsi_exec_channel *a )
1915 {
1916 uint j;
1917 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
1918
1919 /* FIXME: handle explicit derivs, offsets */
1920 sampler->get_samples(sampler, sview_idx, sampler_idx,
1921 s->f, t->f, p->f, c0->f, c1->f, derivs, offset, control, rgba);
1922
1923 for (j = 0; j < 4; j++) {
1924 r->f[j] = rgba[0][j];
1925 g->f[j] = rgba[1][j];
1926 b->f[j] = rgba[2][j];
1927 a->f[j] = rgba[3][j];
1928 }
1929 }
1930
1931
1932 #define TEX_MODIFIER_NONE 0
1933 #define TEX_MODIFIER_PROJECTED 1
1934 #define TEX_MODIFIER_LOD_BIAS 2
1935 #define TEX_MODIFIER_EXPLICIT_LOD 3
1936 #define TEX_MODIFIER_LEVEL_ZERO 4
1937 #define TEX_MODIFIER_GATHER 5
1938
1939 /*
1940 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
1941 */
1942 static void
1943 fetch_texel_offsets(struct tgsi_exec_machine *mach,
1944 const struct tgsi_full_instruction *inst,
1945 int8_t offsets[3])
1946 {
1947 if (inst->Texture.NumOffsets == 1) {
1948 union tgsi_exec_channel index;
1949 union tgsi_exec_channel offset[3];
1950 index.i[0] = index.i[1] = index.i[2] = index.i[3] = inst->TexOffsets[0].Index;
1951 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1952 inst->TexOffsets[0].SwizzleX, &index, &ZeroVec, &offset[0]);
1953 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1954 inst->TexOffsets[0].SwizzleY, &index, &ZeroVec, &offset[1]);
1955 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1956 inst->TexOffsets[0].SwizzleZ, &index, &ZeroVec, &offset[2]);
1957 offsets[0] = offset[0].i[0];
1958 offsets[1] = offset[1].i[0];
1959 offsets[2] = offset[2].i[0];
1960 } else {
1961 assert(inst->Texture.NumOffsets == 0);
1962 offsets[0] = offsets[1] = offsets[2] = 0;
1963 }
1964 }
1965
1966
1967 /*
1968 * Fetch dx and dy values for one channel (s, t or r).
1969 * Put dx values into one float array, dy values into another.
1970 */
1971 static void
1972 fetch_assign_deriv_channel(struct tgsi_exec_machine *mach,
1973 const struct tgsi_full_instruction *inst,
1974 unsigned regdsrcx,
1975 unsigned chan,
1976 float derivs[2][TGSI_QUAD_SIZE])
1977 {
1978 union tgsi_exec_channel d;
1979 FETCH(&d, regdsrcx, chan);
1980 derivs[0][0] = d.f[0];
1981 derivs[0][1] = d.f[1];
1982 derivs[0][2] = d.f[2];
1983 derivs[0][3] = d.f[3];
1984 FETCH(&d, regdsrcx + 1, chan);
1985 derivs[1][0] = d.f[0];
1986 derivs[1][1] = d.f[1];
1987 derivs[1][2] = d.f[2];
1988 derivs[1][3] = d.f[3];
1989 }
1990
1991
1992 /*
1993 * execute a texture instruction.
1994 *
1995 * modifier is used to control the channel routing for the\
1996 * instruction variants like proj, lod, and texture with lod bias.
1997 * sampler indicates which src register the sampler is contained in.
1998 */
1999 static void
2000 exec_tex(struct tgsi_exec_machine *mach,
2001 const struct tgsi_full_instruction *inst,
2002 uint modifier, uint sampler)
2003 {
2004 const uint unit = inst->Src[sampler].Register.Index;
2005 const union tgsi_exec_channel *args[5], *proj = NULL;
2006 union tgsi_exec_channel r[5];
2007 enum tgsi_sampler_control control = tgsi_sampler_lod_none;
2008 uint chan;
2009 int8_t offsets[3];
2010 int dim, shadow_ref, i;
2011
2012 /* always fetch all 3 offsets, overkill but keeps code simple */
2013 fetch_texel_offsets(mach, inst, offsets);
2014
2015 assert(modifier != TEX_MODIFIER_LEVEL_ZERO);
2016 assert(inst->Texture.Texture != TGSI_TEXTURE_BUFFER);
2017
2018 dim = tgsi_util_get_texture_coord_dim(inst->Texture.Texture, &shadow_ref);
2019
2020 assert(dim <= 4);
2021 if (shadow_ref >= 0)
2022 assert(shadow_ref >= dim && shadow_ref < Elements(args));
2023
2024 /* fetch modifier to the last argument */
2025 if (modifier != TEX_MODIFIER_NONE) {
2026 const int last = Elements(args) - 1;
2027
2028 /* fetch modifier from src0.w or src1.x */
2029 if (sampler == 1) {
2030 assert(dim <= TGSI_CHAN_W && shadow_ref != TGSI_CHAN_W);
2031 FETCH(&r[last], 0, TGSI_CHAN_W);
2032 }
2033 else {
2034 assert(shadow_ref != 4);
2035 FETCH(&r[last], 1, TGSI_CHAN_X);
2036 }
2037
2038 if (modifier != TEX_MODIFIER_PROJECTED) {
2039 args[last] = &r[last];
2040 }
2041 else {
2042 proj = &r[last];
2043 args[last] = &ZeroVec;
2044 }
2045
2046 /* point unused arguments to zero vector */
2047 for (i = dim; i < last; i++)
2048 args[i] = &ZeroVec;
2049
2050 if (modifier == TEX_MODIFIER_EXPLICIT_LOD)
2051 control = tgsi_sampler_lod_explicit;
2052 else if (modifier == TEX_MODIFIER_LOD_BIAS)
2053 control = tgsi_sampler_lod_bias;
2054 else if (modifier == TEX_MODIFIER_GATHER)
2055 control = tgsi_sampler_gather;
2056 }
2057 else {
2058 for (i = dim; i < Elements(args); i++)
2059 args[i] = &ZeroVec;
2060 }
2061
2062 /* fetch coordinates */
2063 for (i = 0; i < dim; i++) {
2064 FETCH(&r[i], 0, TGSI_CHAN_X + i);
2065
2066 if (proj)
2067 micro_div(&r[i], &r[i], proj);
2068
2069 args[i] = &r[i];
2070 }
2071
2072 /* fetch reference value */
2073 if (shadow_ref >= 0) {
2074 FETCH(&r[shadow_ref], shadow_ref / 4, TGSI_CHAN_X + (shadow_ref % 4));
2075
2076 if (proj)
2077 micro_div(&r[shadow_ref], &r[shadow_ref], proj);
2078
2079 args[shadow_ref] = &r[shadow_ref];
2080 }
2081
2082 fetch_texel(mach->Sampler, unit, unit,
2083 args[0], args[1], args[2], args[3], args[4],
2084 NULL, offsets, control,
2085 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2086
2087 #if 0
2088 debug_printf("fetch r: %g %g %g %g\n",
2089 r[0].f[0], r[0].f[1], r[0].f[2], r[0].f[3]);
2090 debug_printf("fetch g: %g %g %g %g\n",
2091 r[1].f[0], r[1].f[1], r[1].f[2], r[1].f[3]);
2092 debug_printf("fetch b: %g %g %g %g\n",
2093 r[2].f[0], r[2].f[1], r[2].f[2], r[2].f[3]);
2094 debug_printf("fetch a: %g %g %g %g\n",
2095 r[3].f[0], r[3].f[1], r[3].f[2], r[3].f[3]);
2096 #endif
2097
2098 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2099 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2100 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2101 }
2102 }
2103 }
2104
2105
2106 static void
2107 exec_txd(struct tgsi_exec_machine *mach,
2108 const struct tgsi_full_instruction *inst)
2109 {
2110 const uint unit = inst->Src[3].Register.Index;
2111 union tgsi_exec_channel r[4];
2112 float derivs[3][2][TGSI_QUAD_SIZE];
2113 uint chan;
2114 int8_t offsets[3];
2115
2116 /* always fetch all 3 offsets, overkill but keeps code simple */
2117 fetch_texel_offsets(mach, inst, offsets);
2118
2119 switch (inst->Texture.Texture) {
2120 case TGSI_TEXTURE_1D:
2121 FETCH(&r[0], 0, TGSI_CHAN_X);
2122
2123 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2124
2125 fetch_texel(mach->Sampler, unit, unit,
2126 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2127 derivs, offsets, tgsi_sampler_derivs_explicit,
2128 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2129 break;
2130
2131 case TGSI_TEXTURE_SHADOW1D:
2132 case TGSI_TEXTURE_1D_ARRAY:
2133 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2134 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
2135 FETCH(&r[0], 0, TGSI_CHAN_X);
2136 FETCH(&r[1], 0, TGSI_CHAN_Y);
2137 FETCH(&r[2], 0, TGSI_CHAN_Z);
2138
2139 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2140
2141 fetch_texel(mach->Sampler, unit, unit,
2142 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2143 derivs, offsets, tgsi_sampler_derivs_explicit,
2144 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2145 break;
2146
2147 case TGSI_TEXTURE_2D:
2148 case TGSI_TEXTURE_RECT:
2149 FETCH(&r[0], 0, TGSI_CHAN_X);
2150 FETCH(&r[1], 0, TGSI_CHAN_Y);
2151
2152 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2153 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2154
2155 fetch_texel(mach->Sampler, unit, unit,
2156 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2157 derivs, offsets, tgsi_sampler_derivs_explicit,
2158 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2159 break;
2160
2161
2162 case TGSI_TEXTURE_SHADOW2D:
2163 case TGSI_TEXTURE_SHADOWRECT:
2164 case TGSI_TEXTURE_2D_ARRAY:
2165 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2166 /* only SHADOW2D_ARRAY actually needs W */
2167 FETCH(&r[0], 0, TGSI_CHAN_X);
2168 FETCH(&r[1], 0, TGSI_CHAN_Y);
2169 FETCH(&r[2], 0, TGSI_CHAN_Z);
2170 FETCH(&r[3], 0, TGSI_CHAN_W);
2171
2172 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2173 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2174
2175 fetch_texel(mach->Sampler, unit, unit,
2176 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
2177 derivs, offsets, tgsi_sampler_derivs_explicit,
2178 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2179 break;
2180
2181 case TGSI_TEXTURE_3D:
2182 case TGSI_TEXTURE_CUBE:
2183 case TGSI_TEXTURE_CUBE_ARRAY:
2184 case TGSI_TEXTURE_SHADOWCUBE:
2185 /* only TEXTURE_CUBE_ARRAY and TEXTURE_SHADOWCUBE actually need W */
2186 FETCH(&r[0], 0, TGSI_CHAN_X);
2187 FETCH(&r[1], 0, TGSI_CHAN_Y);
2188 FETCH(&r[2], 0, TGSI_CHAN_Z);
2189 FETCH(&r[3], 0, TGSI_CHAN_W);
2190
2191 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2192 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2193 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Z, derivs[2]);
2194
2195 fetch_texel(mach->Sampler, unit, unit,
2196 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
2197 derivs, offsets, tgsi_sampler_derivs_explicit,
2198 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2199 break;
2200
2201 default:
2202 assert(0);
2203 }
2204
2205 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2206 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2207 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2208 }
2209 }
2210 }
2211
2212
2213 static void
2214 exec_txf(struct tgsi_exec_machine *mach,
2215 const struct tgsi_full_instruction *inst)
2216 {
2217 const uint unit = inst->Src[1].Register.Index;
2218 union tgsi_exec_channel r[4];
2219 uint chan;
2220 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
2221 int j;
2222 int8_t offsets[3];
2223 unsigned target;
2224
2225 /* always fetch all 3 offsets, overkill but keeps code simple */
2226 fetch_texel_offsets(mach, inst, offsets);
2227
2228 IFETCH(&r[3], 0, TGSI_CHAN_W);
2229
2230 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I) {
2231 target = mach->SamplerViews[unit].Resource;
2232 }
2233 else {
2234 target = inst->Texture.Texture;
2235 }
2236 switch(target) {
2237 case TGSI_TEXTURE_3D:
2238 case TGSI_TEXTURE_2D_ARRAY:
2239 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2240 case TGSI_TEXTURE_2D_ARRAY_MSAA:
2241 IFETCH(&r[2], 0, TGSI_CHAN_Z);
2242 /* fallthrough */
2243 case TGSI_TEXTURE_2D:
2244 case TGSI_TEXTURE_RECT:
2245 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2246 case TGSI_TEXTURE_SHADOW2D:
2247 case TGSI_TEXTURE_SHADOWRECT:
2248 case TGSI_TEXTURE_1D_ARRAY:
2249 case TGSI_TEXTURE_2D_MSAA:
2250 IFETCH(&r[1], 0, TGSI_CHAN_Y);
2251 /* fallthrough */
2252 case TGSI_TEXTURE_BUFFER:
2253 case TGSI_TEXTURE_1D:
2254 case TGSI_TEXTURE_SHADOW1D:
2255 IFETCH(&r[0], 0, TGSI_CHAN_X);
2256 break;
2257 default:
2258 assert(0);
2259 break;
2260 }
2261
2262 mach->Sampler->get_texel(mach->Sampler, unit, r[0].i, r[1].i, r[2].i, r[3].i,
2263 offsets, rgba);
2264
2265 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
2266 r[0].f[j] = rgba[0][j];
2267 r[1].f[j] = rgba[1][j];
2268 r[2].f[j] = rgba[2][j];
2269 r[3].f[j] = rgba[3][j];
2270 }
2271
2272 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I) {
2273 unsigned char swizzles[4];
2274 swizzles[0] = inst->Src[1].Register.SwizzleX;
2275 swizzles[1] = inst->Src[1].Register.SwizzleY;
2276 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2277 swizzles[3] = inst->Src[1].Register.SwizzleW;
2278
2279 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2280 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2281 store_dest(mach, &r[swizzles[chan]],
2282 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2283 }
2284 }
2285 }
2286 else {
2287 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2288 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2289 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2290 }
2291 }
2292 }
2293 }
2294
2295 static void
2296 exec_txq(struct tgsi_exec_machine *mach,
2297 const struct tgsi_full_instruction *inst)
2298 {
2299 const uint unit = inst->Src[1].Register.Index;
2300 int result[4];
2301 union tgsi_exec_channel r[4], src;
2302 uint chan;
2303 int i,j;
2304
2305 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
2306
2307 /* XXX: This interface can't return per-pixel values */
2308 mach->Sampler->get_dims(mach->Sampler, unit, src.i[0], result);
2309
2310 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2311 for (j = 0; j < 4; j++) {
2312 r[j].i[i] = result[j];
2313 }
2314 }
2315
2316 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2317 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2318 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
2319 TGSI_EXEC_DATA_INT);
2320 }
2321 }
2322 }
2323
2324 static void
2325 exec_sample(struct tgsi_exec_machine *mach,
2326 const struct tgsi_full_instruction *inst,
2327 uint modifier, boolean compare)
2328 {
2329 const uint resource_unit = inst->Src[1].Register.Index;
2330 const uint sampler_unit = inst->Src[2].Register.Index;
2331 union tgsi_exec_channel r[5], c1;
2332 const union tgsi_exec_channel *lod = &ZeroVec;
2333 enum tgsi_sampler_control control = tgsi_sampler_lod_none;
2334 uint chan;
2335 unsigned char swizzles[4];
2336 int8_t offsets[3];
2337
2338 /* always fetch all 3 offsets, overkill but keeps code simple */
2339 fetch_texel_offsets(mach, inst, offsets);
2340
2341 assert(modifier != TEX_MODIFIER_PROJECTED);
2342
2343 if (modifier != TEX_MODIFIER_NONE) {
2344 if (modifier == TEX_MODIFIER_LOD_BIAS) {
2345 FETCH(&c1, 3, TGSI_CHAN_X);
2346 lod = &c1;
2347 control = tgsi_sampler_lod_bias;
2348 }
2349 else if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
2350 FETCH(&c1, 3, TGSI_CHAN_X);
2351 lod = &c1;
2352 control = tgsi_sampler_lod_explicit;
2353 }
2354 else {
2355 assert(modifier == TEX_MODIFIER_LEVEL_ZERO);
2356 control = tgsi_sampler_lod_zero;
2357 }
2358 }
2359
2360 FETCH(&r[0], 0, TGSI_CHAN_X);
2361
2362 switch (mach->SamplerViews[resource_unit].Resource) {
2363 case TGSI_TEXTURE_1D:
2364 if (compare) {
2365 FETCH(&r[2], 3, TGSI_CHAN_X);
2366 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2367 &r[0], &ZeroVec, &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2368 NULL, offsets, control,
2369 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2370 }
2371 else {
2372 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2373 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2374 NULL, offsets, control,
2375 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2376 }
2377 break;
2378
2379 case TGSI_TEXTURE_1D_ARRAY:
2380 case TGSI_TEXTURE_2D:
2381 case TGSI_TEXTURE_RECT:
2382 FETCH(&r[1], 0, TGSI_CHAN_Y);
2383 if (compare) {
2384 FETCH(&r[2], 3, TGSI_CHAN_X);
2385 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2386 &r[0], &r[1], &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2387 NULL, offsets, control,
2388 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2389 }
2390 else {
2391 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2392 &r[0], &r[1], &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2393 NULL, offsets, control,
2394 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2395 }
2396 break;
2397
2398 case TGSI_TEXTURE_2D_ARRAY:
2399 case TGSI_TEXTURE_3D:
2400 case TGSI_TEXTURE_CUBE:
2401 FETCH(&r[1], 0, TGSI_CHAN_Y);
2402 FETCH(&r[2], 0, TGSI_CHAN_Z);
2403 if(compare) {
2404 FETCH(&r[3], 3, TGSI_CHAN_X);
2405 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2406 &r[0], &r[1], &r[2], &r[3], lod,
2407 NULL, offsets, control,
2408 &r[0], &r[1], &r[2], &r[3]);
2409 }
2410 else {
2411 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2412 &r[0], &r[1], &r[2], &ZeroVec, lod,
2413 NULL, offsets, control,
2414 &r[0], &r[1], &r[2], &r[3]);
2415 }
2416 break;
2417
2418 case TGSI_TEXTURE_CUBE_ARRAY:
2419 FETCH(&r[1], 0, TGSI_CHAN_Y);
2420 FETCH(&r[2], 0, TGSI_CHAN_Z);
2421 FETCH(&r[3], 0, TGSI_CHAN_W);
2422 if(compare) {
2423 FETCH(&r[4], 3, TGSI_CHAN_X);
2424 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2425 &r[0], &r[1], &r[2], &r[3], &r[4],
2426 NULL, offsets, control,
2427 &r[0], &r[1], &r[2], &r[3]);
2428 }
2429 else {
2430 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2431 &r[0], &r[1], &r[2], &r[3], lod,
2432 NULL, offsets, control,
2433 &r[0], &r[1], &r[2], &r[3]);
2434 }
2435 break;
2436
2437
2438 default:
2439 assert(0);
2440 }
2441
2442 swizzles[0] = inst->Src[1].Register.SwizzleX;
2443 swizzles[1] = inst->Src[1].Register.SwizzleY;
2444 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2445 swizzles[3] = inst->Src[1].Register.SwizzleW;
2446
2447 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2448 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2449 store_dest(mach, &r[swizzles[chan]],
2450 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2451 }
2452 }
2453 }
2454
2455 static void
2456 exec_sample_d(struct tgsi_exec_machine *mach,
2457 const struct tgsi_full_instruction *inst)
2458 {
2459 const uint resource_unit = inst->Src[1].Register.Index;
2460 const uint sampler_unit = inst->Src[2].Register.Index;
2461 union tgsi_exec_channel r[4];
2462 float derivs[3][2][TGSI_QUAD_SIZE];
2463 uint chan;
2464 unsigned char swizzles[4];
2465 int8_t offsets[3];
2466
2467 /* always fetch all 3 offsets, overkill but keeps code simple */
2468 fetch_texel_offsets(mach, inst, offsets);
2469
2470 FETCH(&r[0], 0, TGSI_CHAN_X);
2471
2472 switch (mach->SamplerViews[resource_unit].Resource) {
2473 case TGSI_TEXTURE_1D:
2474 case TGSI_TEXTURE_1D_ARRAY:
2475 /* only 1D array actually needs Y */
2476 FETCH(&r[1], 0, TGSI_CHAN_Y);
2477
2478 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2479
2480 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2481 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2482 derivs, offsets, tgsi_sampler_derivs_explicit,
2483 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2484 break;
2485
2486 case TGSI_TEXTURE_2D:
2487 case TGSI_TEXTURE_RECT:
2488 case TGSI_TEXTURE_2D_ARRAY:
2489 /* only 2D array actually needs Z */
2490 FETCH(&r[1], 0, TGSI_CHAN_Y);
2491 FETCH(&r[2], 0, TGSI_CHAN_Z);
2492
2493 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2494 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2495
2496 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2497 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* inputs */
2498 derivs, offsets, tgsi_sampler_derivs_explicit,
2499 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2500 break;
2501
2502 case TGSI_TEXTURE_3D:
2503 case TGSI_TEXTURE_CUBE:
2504 case TGSI_TEXTURE_CUBE_ARRAY:
2505 /* only cube array actually needs W */
2506 FETCH(&r[1], 0, TGSI_CHAN_Y);
2507 FETCH(&r[2], 0, TGSI_CHAN_Z);
2508 FETCH(&r[3], 0, TGSI_CHAN_W);
2509
2510 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2511 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2512 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Z, derivs[2]);
2513
2514 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2515 &r[0], &r[1], &r[2], &r[3], &ZeroVec,
2516 derivs, offsets, tgsi_sampler_derivs_explicit,
2517 &r[0], &r[1], &r[2], &r[3]);
2518 break;
2519
2520 default:
2521 assert(0);
2522 }
2523
2524 swizzles[0] = inst->Src[1].Register.SwizzleX;
2525 swizzles[1] = inst->Src[1].Register.SwizzleY;
2526 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2527 swizzles[3] = inst->Src[1].Register.SwizzleW;
2528
2529 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2530 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2531 store_dest(mach, &r[swizzles[chan]],
2532 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2533 }
2534 }
2535 }
2536
2537
2538 /**
2539 * Evaluate a constant-valued coefficient at the position of the
2540 * current quad.
2541 */
2542 static void
2543 eval_constant_coef(
2544 struct tgsi_exec_machine *mach,
2545 unsigned attrib,
2546 unsigned chan )
2547 {
2548 unsigned i;
2549
2550 for( i = 0; i < TGSI_QUAD_SIZE; i++ ) {
2551 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
2552 }
2553 }
2554
2555 /**
2556 * Evaluate a linear-valued coefficient at the position of the
2557 * current quad.
2558 */
2559 static void
2560 eval_linear_coef(
2561 struct tgsi_exec_machine *mach,
2562 unsigned attrib,
2563 unsigned chan )
2564 {
2565 const float x = mach->QuadPos.xyzw[0].f[0];
2566 const float y = mach->QuadPos.xyzw[1].f[0];
2567 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2568 const float dady = mach->InterpCoefs[attrib].dady[chan];
2569 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2570 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
2571 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
2572 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
2573 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
2574 }
2575
2576 /**
2577 * Evaluate a perspective-valued coefficient at the position of the
2578 * current quad.
2579 */
2580 static void
2581 eval_perspective_coef(
2582 struct tgsi_exec_machine *mach,
2583 unsigned attrib,
2584 unsigned chan )
2585 {
2586 const float x = mach->QuadPos.xyzw[0].f[0];
2587 const float y = mach->QuadPos.xyzw[1].f[0];
2588 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2589 const float dady = mach->InterpCoefs[attrib].dady[chan];
2590 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2591 const float *w = mach->QuadPos.xyzw[3].f;
2592 /* divide by W here */
2593 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
2594 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
2595 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
2596 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
2597 }
2598
2599
2600 typedef void (* eval_coef_func)(
2601 struct tgsi_exec_machine *mach,
2602 unsigned attrib,
2603 unsigned chan );
2604
2605 static void
2606 exec_declaration(struct tgsi_exec_machine *mach,
2607 const struct tgsi_full_declaration *decl)
2608 {
2609 if (decl->Declaration.File == TGSI_FILE_SAMPLER_VIEW) {
2610 mach->SamplerViews[decl->Range.First] = decl->SamplerView;
2611 return;
2612 }
2613
2614 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
2615 if (decl->Declaration.File == TGSI_FILE_INPUT) {
2616 uint first, last, mask;
2617
2618 first = decl->Range.First;
2619 last = decl->Range.Last;
2620 mask = decl->Declaration.UsageMask;
2621
2622 /* XXX we could remove this special-case code since
2623 * mach->InterpCoefs[first].a0 should already have the
2624 * front/back-face value. But we should first update the
2625 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2626 * Then, we could remove the tgsi_exec_machine::Face field.
2627 */
2628 /* XXX make FACE a system value */
2629 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
2630 uint i;
2631
2632 assert(decl->Semantic.Index == 0);
2633 assert(first == last);
2634
2635 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2636 mach->Inputs[first].xyzw[0].f[i] = mach->Face;
2637 }
2638 } else {
2639 eval_coef_func eval;
2640 uint i, j;
2641
2642 switch (decl->Interp.Interpolate) {
2643 case TGSI_INTERPOLATE_CONSTANT:
2644 eval = eval_constant_coef;
2645 break;
2646
2647 case TGSI_INTERPOLATE_LINEAR:
2648 eval = eval_linear_coef;
2649 break;
2650
2651 case TGSI_INTERPOLATE_PERSPECTIVE:
2652 eval = eval_perspective_coef;
2653 break;
2654
2655 case TGSI_INTERPOLATE_COLOR:
2656 eval = mach->flatshade_color ? eval_constant_coef : eval_perspective_coef;
2657 break;
2658
2659 default:
2660 assert(0);
2661 return;
2662 }
2663
2664 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2665 if (mask & (1 << j)) {
2666 for (i = first; i <= last; i++) {
2667 eval(mach, i, j);
2668 }
2669 }
2670 }
2671 }
2672
2673 if (DEBUG_EXECUTION) {
2674 uint i, j;
2675 for (i = first; i <= last; ++i) {
2676 debug_printf("IN[%2u] = ", i);
2677 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2678 if (j > 0) {
2679 debug_printf(" ");
2680 }
2681 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
2682 mach->Inputs[i].xyzw[0].f[j], mach->Inputs[i].xyzw[0].u[j],
2683 mach->Inputs[i].xyzw[1].f[j], mach->Inputs[i].xyzw[1].u[j],
2684 mach->Inputs[i].xyzw[2].f[j], mach->Inputs[i].xyzw[2].u[j],
2685 mach->Inputs[i].xyzw[3].f[j], mach->Inputs[i].xyzw[3].u[j]);
2686 }
2687 }
2688 }
2689 }
2690 }
2691
2692 if (decl->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
2693 mach->SysSemanticToIndex[decl->Declaration.Semantic] = decl->Range.First;
2694 }
2695 }
2696
2697 typedef void (* micro_unary_op)(union tgsi_exec_channel *dst,
2698 const union tgsi_exec_channel *src);
2699
2700 static void
2701 exec_scalar_unary(struct tgsi_exec_machine *mach,
2702 const struct tgsi_full_instruction *inst,
2703 micro_unary_op op,
2704 enum tgsi_exec_datatype dst_datatype,
2705 enum tgsi_exec_datatype src_datatype)
2706 {
2707 unsigned int chan;
2708 union tgsi_exec_channel src;
2709 union tgsi_exec_channel dst;
2710
2711 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, src_datatype);
2712 op(&dst, &src);
2713 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2714 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2715 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2716 }
2717 }
2718 }
2719
2720 static void
2721 exec_vector_unary(struct tgsi_exec_machine *mach,
2722 const struct tgsi_full_instruction *inst,
2723 micro_unary_op op,
2724 enum tgsi_exec_datatype dst_datatype,
2725 enum tgsi_exec_datatype src_datatype)
2726 {
2727 unsigned int chan;
2728 struct tgsi_exec_vector dst;
2729
2730 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2731 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2732 union tgsi_exec_channel src;
2733
2734 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
2735 op(&dst.xyzw[chan], &src);
2736 }
2737 }
2738 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2739 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2740 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2741 }
2742 }
2743 }
2744
2745 typedef void (* micro_binary_op)(union tgsi_exec_channel *dst,
2746 const union tgsi_exec_channel *src0,
2747 const union tgsi_exec_channel *src1);
2748
2749 static void
2750 exec_scalar_binary(struct tgsi_exec_machine *mach,
2751 const struct tgsi_full_instruction *inst,
2752 micro_binary_op op,
2753 enum tgsi_exec_datatype dst_datatype,
2754 enum tgsi_exec_datatype src_datatype)
2755 {
2756 unsigned int chan;
2757 union tgsi_exec_channel src[2];
2758 union tgsi_exec_channel dst;
2759
2760 fetch_source(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, src_datatype);
2761 fetch_source(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, src_datatype);
2762 op(&dst, &src[0], &src[1]);
2763 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2764 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2765 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2766 }
2767 }
2768 }
2769
2770 static void
2771 exec_vector_binary(struct tgsi_exec_machine *mach,
2772 const struct tgsi_full_instruction *inst,
2773 micro_binary_op op,
2774 enum tgsi_exec_datatype dst_datatype,
2775 enum tgsi_exec_datatype src_datatype)
2776 {
2777 unsigned int chan;
2778 struct tgsi_exec_vector dst;
2779
2780 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2781 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2782 union tgsi_exec_channel src[2];
2783
2784 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2785 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2786 op(&dst.xyzw[chan], &src[0], &src[1]);
2787 }
2788 }
2789 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2790 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2791 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2792 }
2793 }
2794 }
2795
2796 typedef void (* micro_trinary_op)(union tgsi_exec_channel *dst,
2797 const union tgsi_exec_channel *src0,
2798 const union tgsi_exec_channel *src1,
2799 const union tgsi_exec_channel *src2);
2800
2801 static void
2802 exec_vector_trinary(struct tgsi_exec_machine *mach,
2803 const struct tgsi_full_instruction *inst,
2804 micro_trinary_op op,
2805 enum tgsi_exec_datatype dst_datatype,
2806 enum tgsi_exec_datatype src_datatype)
2807 {
2808 unsigned int chan;
2809 struct tgsi_exec_vector dst;
2810
2811 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2812 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2813 union tgsi_exec_channel src[3];
2814
2815 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2816 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2817 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2818 op(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
2819 }
2820 }
2821 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2822 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2823 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2824 }
2825 }
2826 }
2827
2828 typedef void (* micro_quaternary_op)(union tgsi_exec_channel *dst,
2829 const union tgsi_exec_channel *src0,
2830 const union tgsi_exec_channel *src1,
2831 const union tgsi_exec_channel *src2,
2832 const union tgsi_exec_channel *src3);
2833
2834 static void
2835 exec_vector_quaternary(struct tgsi_exec_machine *mach,
2836 const struct tgsi_full_instruction *inst,
2837 micro_quaternary_op op,
2838 enum tgsi_exec_datatype dst_datatype,
2839 enum tgsi_exec_datatype src_datatype)
2840 {
2841 unsigned int chan;
2842 struct tgsi_exec_vector dst;
2843
2844 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2845 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2846 union tgsi_exec_channel src[4];
2847
2848 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2849 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2850 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2851 fetch_source(mach, &src[3], &inst->Src[3], chan, src_datatype);
2852 op(&dst.xyzw[chan], &src[0], &src[1], &src[2], &src[3]);
2853 }
2854 }
2855 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2856 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2857 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2858 }
2859 }
2860 }
2861
2862 static void
2863 exec_dp3(struct tgsi_exec_machine *mach,
2864 const struct tgsi_full_instruction *inst)
2865 {
2866 unsigned int chan;
2867 union tgsi_exec_channel arg[3];
2868
2869 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2870 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2871 micro_mul(&arg[2], &arg[0], &arg[1]);
2872
2873 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_Z; chan++) {
2874 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2875 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2876 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2877 }
2878
2879 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2880 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2881 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2882 }
2883 }
2884 }
2885
2886 static void
2887 exec_dp4(struct tgsi_exec_machine *mach,
2888 const struct tgsi_full_instruction *inst)
2889 {
2890 unsigned int chan;
2891 union tgsi_exec_channel arg[3];
2892
2893 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2894 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2895 micro_mul(&arg[2], &arg[0], &arg[1]);
2896
2897 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_W; chan++) {
2898 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2899 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2900 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2901 }
2902
2903 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2904 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2905 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2906 }
2907 }
2908 }
2909
2910 static void
2911 exec_dp2a(struct tgsi_exec_machine *mach,
2912 const struct tgsi_full_instruction *inst)
2913 {
2914 unsigned int chan;
2915 union tgsi_exec_channel arg[3];
2916
2917 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2918 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2919 micro_mul(&arg[2], &arg[0], &arg[1]);
2920
2921 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2922 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2923 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2924
2925 fetch_source(mach, &arg[1], &inst->Src[2], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2926 micro_add(&arg[0], &arg[0], &arg[1]);
2927
2928 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2929 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2930 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2931 }
2932 }
2933 }
2934
2935 static void
2936 exec_dph(struct tgsi_exec_machine *mach,
2937 const struct tgsi_full_instruction *inst)
2938 {
2939 unsigned int chan;
2940 union tgsi_exec_channel arg[3];
2941
2942 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2943 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2944 micro_mul(&arg[2], &arg[0], &arg[1]);
2945
2946 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2947 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2948 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2949
2950 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2951 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2952 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2953
2954 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2955 micro_add(&arg[0], &arg[0], &arg[1]);
2956
2957 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2958 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2959 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2960 }
2961 }
2962 }
2963
2964 static void
2965 exec_dp2(struct tgsi_exec_machine *mach,
2966 const struct tgsi_full_instruction *inst)
2967 {
2968 unsigned int chan;
2969 union tgsi_exec_channel arg[3];
2970
2971 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2972 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2973 micro_mul(&arg[2], &arg[0], &arg[1]);
2974
2975 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2976 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2977 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2978
2979 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2980 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2981 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2982 }
2983 }
2984 }
2985
2986 static void
2987 exec_scs(struct tgsi_exec_machine *mach,
2988 const struct tgsi_full_instruction *inst)
2989 {
2990 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) {
2991 union tgsi_exec_channel arg;
2992 union tgsi_exec_channel result;
2993
2994 fetch_source(mach, &arg, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2995
2996 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2997 micro_cos(&result, &arg);
2998 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2999 }
3000 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3001 micro_sin(&result, &arg);
3002 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3003 }
3004 }
3005 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3006 store_dest(mach, &ZeroVec, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3007 }
3008 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3009 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3010 }
3011 }
3012
3013 static void
3014 exec_xpd(struct tgsi_exec_machine *mach,
3015 const struct tgsi_full_instruction *inst)
3016 {
3017 union tgsi_exec_channel r[6];
3018 union tgsi_exec_channel d[3];
3019
3020 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3021 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3022
3023 micro_mul(&r[2], &r[0], &r[1]);
3024
3025 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3026 fetch_source(mach, &r[4], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3027
3028 micro_mul(&r[5], &r[3], &r[4] );
3029 micro_sub(&d[TGSI_CHAN_X], &r[2], &r[5]);
3030
3031 fetch_source(mach, &r[2], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3032
3033 micro_mul(&r[3], &r[3], &r[2]);
3034
3035 fetch_source(mach, &r[5], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3036
3037 micro_mul(&r[1], &r[1], &r[5]);
3038 micro_sub(&d[TGSI_CHAN_Y], &r[3], &r[1]);
3039
3040 micro_mul(&r[5], &r[5], &r[4]);
3041 micro_mul(&r[0], &r[0], &r[2]);
3042 micro_sub(&d[TGSI_CHAN_Z], &r[5], &r[0]);
3043
3044 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3045 store_dest(mach, &d[TGSI_CHAN_X], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3046 }
3047 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3048 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3049 }
3050 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3051 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3052 }
3053 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3054 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3055 }
3056 }
3057
3058 static void
3059 exec_dst(struct tgsi_exec_machine *mach,
3060 const struct tgsi_full_instruction *inst)
3061 {
3062 union tgsi_exec_channel r[2];
3063 union tgsi_exec_channel d[4];
3064
3065 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3066 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3067 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3068 micro_mul(&d[TGSI_CHAN_Y], &r[0], &r[1]);
3069 }
3070 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3071 fetch_source(mach, &d[TGSI_CHAN_Z], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3072 }
3073 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3074 fetch_source(mach, &d[TGSI_CHAN_W], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3075 }
3076
3077 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3078 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3079 }
3080 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3081 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3082 }
3083 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3084 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3085 }
3086 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3087 store_dest(mach, &d[TGSI_CHAN_W], &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3088 }
3089 }
3090
3091 static void
3092 exec_log(struct tgsi_exec_machine *mach,
3093 const struct tgsi_full_instruction *inst)
3094 {
3095 union tgsi_exec_channel r[3];
3096
3097 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3098 micro_abs(&r[2], &r[0]); /* r2 = abs(r0) */
3099 micro_lg2(&r[1], &r[2]); /* r1 = lg2(r2) */
3100 micro_flr(&r[0], &r[1]); /* r0 = floor(r1) */
3101 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3102 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3103 }
3104 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3105 micro_exp2(&r[0], &r[0]); /* r0 = 2 ^ r0 */
3106 micro_div(&r[0], &r[2], &r[0]); /* r0 = r2 / r0 */
3107 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3108 }
3109 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3110 store_dest(mach, &r[1], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3111 }
3112 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3113 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3114 }
3115 }
3116
3117 static void
3118 exec_exp(struct tgsi_exec_machine *mach,
3119 const struct tgsi_full_instruction *inst)
3120 {
3121 union tgsi_exec_channel r[3];
3122
3123 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3124 micro_flr(&r[1], &r[0]); /* r1 = floor(r0) */
3125 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3126 micro_exp2(&r[2], &r[1]); /* r2 = 2 ^ r1 */
3127 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3128 }
3129 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3130 micro_sub(&r[2], &r[0], &r[1]); /* r2 = r0 - r1 */
3131 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3132 }
3133 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3134 micro_exp2(&r[2], &r[0]); /* r2 = 2 ^ r0 */
3135 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3136 }
3137 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3138 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3139 }
3140 }
3141
3142 static void
3143 exec_lit(struct tgsi_exec_machine *mach,
3144 const struct tgsi_full_instruction *inst)
3145 {
3146 union tgsi_exec_channel r[3];
3147 union tgsi_exec_channel d[3];
3148
3149 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YZ) {
3150 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3151 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3152 fetch_source(mach, &r[1], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3153 micro_max(&r[1], &r[1], &ZeroVec);
3154
3155 fetch_source(mach, &r[2], &inst->Src[0], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3156 micro_min(&r[2], &r[2], &P128Vec);
3157 micro_max(&r[2], &r[2], &M128Vec);
3158 micro_pow(&r[1], &r[1], &r[2]);
3159 micro_lt(&d[TGSI_CHAN_Z], &ZeroVec, &r[0], &r[1], &ZeroVec);
3160 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3161 }
3162 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3163 micro_max(&d[TGSI_CHAN_Y], &r[0], &ZeroVec);
3164 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3165 }
3166 }
3167 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3168 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3169 }
3170
3171 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3172 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3173 }
3174 }
3175
3176 static void
3177 exec_break(struct tgsi_exec_machine *mach)
3178 {
3179 if (mach->BreakType == TGSI_EXEC_BREAK_INSIDE_LOOP) {
3180 /* turn off loop channels for each enabled exec channel */
3181 mach->LoopMask &= ~mach->ExecMask;
3182 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3183 UPDATE_EXEC_MASK(mach);
3184 } else {
3185 assert(mach->BreakType == TGSI_EXEC_BREAK_INSIDE_SWITCH);
3186
3187 mach->Switch.mask = 0x0;
3188
3189 UPDATE_EXEC_MASK(mach);
3190 }
3191 }
3192
3193 static void
3194 exec_switch(struct tgsi_exec_machine *mach,
3195 const struct tgsi_full_instruction *inst)
3196 {
3197 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3198 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3199
3200 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3201 fetch_source(mach, &mach->Switch.selector, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3202 mach->Switch.mask = 0x0;
3203 mach->Switch.defaultMask = 0x0;
3204
3205 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3206 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_SWITCH;
3207
3208 UPDATE_EXEC_MASK(mach);
3209 }
3210
3211 static void
3212 exec_case(struct tgsi_exec_machine *mach,
3213 const struct tgsi_full_instruction *inst)
3214 {
3215 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3216 union tgsi_exec_channel src;
3217 uint mask = 0;
3218
3219 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3220
3221 if (mach->Switch.selector.u[0] == src.u[0]) {
3222 mask |= 0x1;
3223 }
3224 if (mach->Switch.selector.u[1] == src.u[1]) {
3225 mask |= 0x2;
3226 }
3227 if (mach->Switch.selector.u[2] == src.u[2]) {
3228 mask |= 0x4;
3229 }
3230 if (mach->Switch.selector.u[3] == src.u[3]) {
3231 mask |= 0x8;
3232 }
3233
3234 mach->Switch.defaultMask |= mask;
3235
3236 mach->Switch.mask |= mask & prevMask;
3237
3238 UPDATE_EXEC_MASK(mach);
3239 }
3240
3241 /* FIXME: this will only work if default is last */
3242 static void
3243 exec_default(struct tgsi_exec_machine *mach)
3244 {
3245 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3246
3247 mach->Switch.mask |= ~mach->Switch.defaultMask & prevMask;
3248
3249 UPDATE_EXEC_MASK(mach);
3250 }
3251
3252 static void
3253 exec_endswitch(struct tgsi_exec_machine *mach)
3254 {
3255 mach->Switch = mach->SwitchStack[--mach->SwitchStackTop];
3256 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3257
3258 UPDATE_EXEC_MASK(mach);
3259 }
3260
3261 typedef void (* micro_dop)(union tgsi_double_channel *dst,
3262 const union tgsi_double_channel *src);
3263
3264 static void
3265 fetch_double_channel(struct tgsi_exec_machine *mach,
3266 union tgsi_double_channel *chan,
3267 const struct tgsi_full_src_register *reg,
3268 uint chan_0,
3269 uint chan_1)
3270 {
3271 union tgsi_exec_channel src[2];
3272 uint i;
3273
3274 fetch_source_d(mach, &src[0], reg, chan_0, TGSI_EXEC_DATA_UINT);
3275 fetch_source_d(mach, &src[1], reg, chan_1, TGSI_EXEC_DATA_UINT);
3276
3277 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
3278 chan->u[i][0] = src[0].u[i];
3279 chan->u[i][1] = src[1].u[i];
3280 }
3281 if (reg->Register.Absolute) {
3282 micro_dabs(chan, chan);
3283 }
3284 if (reg->Register.Negate) {
3285 micro_dneg(chan, chan);
3286 }
3287 }
3288
3289 static void
3290 store_double_channel(struct tgsi_exec_machine *mach,
3291 const union tgsi_double_channel *chan,
3292 const struct tgsi_full_dst_register *reg,
3293 const struct tgsi_full_instruction *inst,
3294 uint chan_0,
3295 uint chan_1)
3296 {
3297 union tgsi_exec_channel dst[2];
3298 uint i;
3299 union tgsi_double_channel temp;
3300 const uint execmask = mach->ExecMask;
3301
3302 if (!inst->Instruction.Saturate) {
3303 for (i = 0; i < TGSI_QUAD_SIZE; i++)
3304 if (execmask & (1 << i)) {
3305 dst[0].u[i] = chan->u[i][0];
3306 dst[1].u[i] = chan->u[i][1];
3307 }
3308 }
3309 else {
3310 for (i = 0; i < TGSI_QUAD_SIZE; i++)
3311 if (execmask & (1 << i)) {
3312 if (chan->d[i] < 0.0)
3313 temp.d[i] = 0.0;
3314 else if (chan->d[i] > 1.0)
3315 temp.d[i] = 1.0;
3316 else
3317 temp.d[i] = chan->d[i];
3318
3319 dst[0].u[i] = temp.u[i][0];
3320 dst[1].u[i] = temp.u[i][1];
3321 }
3322 }
3323
3324 store_dest_double(mach, &dst[0], reg, inst, chan_0, TGSI_EXEC_DATA_UINT);
3325 if (chan_1 != -1)
3326 store_dest_double(mach, &dst[1], reg, inst, chan_1, TGSI_EXEC_DATA_UINT);
3327 }
3328
3329 static void
3330 exec_double_unary(struct tgsi_exec_machine *mach,
3331 const struct tgsi_full_instruction *inst,
3332 micro_dop op)
3333 {
3334 union tgsi_double_channel src;
3335 union tgsi_double_channel dst;
3336
3337 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3338 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3339 op(&dst, &src);
3340 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3341 }
3342 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3343 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3344 op(&dst, &src);
3345 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3346 }
3347 }
3348
3349 static void
3350 exec_double_binary(struct tgsi_exec_machine *mach,
3351 const struct tgsi_full_instruction *inst,
3352 micro_dop op,
3353 enum tgsi_exec_datatype dst_datatype)
3354 {
3355 union tgsi_double_channel src[2];
3356 union tgsi_double_channel dst;
3357 int first_dest_chan, second_dest_chan;
3358 int wmask;
3359
3360 wmask = inst->Dst[0].Register.WriteMask;
3361 /* these are & because of the way DSLT etc store their destinations */
3362 if (wmask & TGSI_WRITEMASK_XY) {
3363 first_dest_chan = TGSI_CHAN_X;
3364 second_dest_chan = TGSI_CHAN_Y;
3365 if (dst_datatype == TGSI_EXEC_DATA_UINT) {
3366 first_dest_chan = (wmask & TGSI_WRITEMASK_X) ? TGSI_CHAN_X : TGSI_CHAN_Y;
3367 second_dest_chan = -1;
3368 }
3369
3370 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3371 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, TGSI_CHAN_Y);
3372 op(&dst, src);
3373 store_double_channel(mach, &dst, &inst->Dst[0], inst, first_dest_chan, second_dest_chan);
3374 }
3375
3376 if (wmask & TGSI_WRITEMASK_ZW) {
3377 first_dest_chan = TGSI_CHAN_Z;
3378 second_dest_chan = TGSI_CHAN_W;
3379 if (dst_datatype == TGSI_EXEC_DATA_UINT) {
3380 first_dest_chan = (wmask & TGSI_WRITEMASK_Z) ? TGSI_CHAN_Z : TGSI_CHAN_W;
3381 second_dest_chan = -1;
3382 }
3383
3384 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3385 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_CHAN_W);
3386 op(&dst, src);
3387 store_double_channel(mach, &dst, &inst->Dst[0], inst, first_dest_chan, second_dest_chan);
3388 }
3389 }
3390
3391 static void
3392 exec_double_trinary(struct tgsi_exec_machine *mach,
3393 const struct tgsi_full_instruction *inst,
3394 micro_dop op)
3395 {
3396 union tgsi_double_channel src[3];
3397 union tgsi_double_channel dst;
3398
3399 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3400 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3401 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, TGSI_CHAN_Y);
3402 fetch_double_channel(mach, &src[2], &inst->Src[2], TGSI_CHAN_X, TGSI_CHAN_Y);
3403 op(&dst, src);
3404 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3405 }
3406 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3407 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3408 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_CHAN_W);
3409 fetch_double_channel(mach, &src[2], &inst->Src[2], TGSI_CHAN_Z, TGSI_CHAN_W);
3410 op(&dst, src);
3411 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3412 }
3413 }
3414
3415 static void
3416 exec_f2d(struct tgsi_exec_machine *mach,
3417 const struct tgsi_full_instruction *inst)
3418 {
3419 union tgsi_exec_channel src;
3420 union tgsi_double_channel dst;
3421
3422 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3423 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3424 micro_f2d(&dst, &src);
3425 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3426 }
3427 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3428 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3429 micro_f2d(&dst, &src);
3430 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3431 }
3432 }
3433
3434 static void
3435 exec_d2f(struct tgsi_exec_machine *mach,
3436 const struct tgsi_full_instruction *inst)
3437 {
3438 union tgsi_double_channel src;
3439 union tgsi_exec_channel dst;
3440 int wm = inst->Dst[0].Register.WriteMask;
3441 int i;
3442 int bit;
3443 for (i = 0; i < 2; i++) {
3444 bit = ffs(wm);
3445 if (bit) {
3446 wm &= ~(1 << (bit - 1));
3447 if (i == 0)
3448 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3449 else
3450 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3451 micro_d2f(&dst, &src);
3452 store_dest(mach, &dst, &inst->Dst[0], inst, bit - 1, TGSI_EXEC_DATA_FLOAT);
3453 }
3454 }
3455 }
3456
3457 static void
3458 exec_i2d(struct tgsi_exec_machine *mach,
3459 const struct tgsi_full_instruction *inst)
3460 {
3461 union tgsi_exec_channel src;
3462 union tgsi_double_channel dst;
3463
3464 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3465 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
3466 micro_i2d(&dst, &src);
3467 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3468 }
3469 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3470 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_INT);
3471 micro_i2d(&dst, &src);
3472 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3473 }
3474 }
3475
3476 static void
3477 exec_d2i(struct tgsi_exec_machine *mach,
3478 const struct tgsi_full_instruction *inst)
3479 {
3480 union tgsi_double_channel src;
3481 union tgsi_exec_channel dst;
3482 int wm = inst->Dst[0].Register.WriteMask;
3483 int i;
3484 int bit;
3485 for (i = 0; i < 2; i++) {
3486 bit = ffs(wm);
3487 if (bit) {
3488 wm &= ~(1 << (bit - 1));
3489 if (i == 0)
3490 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3491 else
3492 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3493 micro_d2i(&dst, &src);
3494 store_dest(mach, &dst, &inst->Dst[0], inst, bit - 1, TGSI_EXEC_DATA_INT);
3495 }
3496 }
3497 }
3498 static void
3499 exec_u2d(struct tgsi_exec_machine *mach,
3500 const struct tgsi_full_instruction *inst)
3501 {
3502 union tgsi_exec_channel src;
3503 union tgsi_double_channel dst;
3504
3505 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3506 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3507 micro_u2d(&dst, &src);
3508 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3509 }
3510 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3511 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_UINT);
3512 micro_u2d(&dst, &src);
3513 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3514 }
3515 }
3516
3517 static void
3518 exec_d2u(struct tgsi_exec_machine *mach,
3519 const struct tgsi_full_instruction *inst)
3520 {
3521 union tgsi_double_channel src;
3522 union tgsi_exec_channel dst;
3523 int wm = inst->Dst[0].Register.WriteMask;
3524 int i;
3525 int bit;
3526 for (i = 0; i < 2; i++) {
3527 bit = ffs(wm);
3528 if (bit) {
3529 wm &= ~(1 << (bit - 1));
3530 if (i == 0)
3531 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3532 else
3533 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3534 micro_d2u(&dst, &src);
3535 store_dest(mach, &dst, &inst->Dst[0], inst, bit - 1, TGSI_EXEC_DATA_UINT);
3536 }
3537 }
3538 }
3539
3540 static void
3541 exec_dldexp(struct tgsi_exec_machine *mach,
3542 const struct tgsi_full_instruction *inst)
3543 {
3544 union tgsi_double_channel src0;
3545 union tgsi_exec_channel src1;
3546 union tgsi_double_channel dst;
3547 int wmask;
3548
3549 wmask = inst->Dst[0].Register.WriteMask;
3550 if (wmask & TGSI_WRITEMASK_XY) {
3551 fetch_double_channel(mach, &src0, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3552 fetch_source(mach, &src1, &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
3553 micro_dldexp(&dst, &src0, &src1);
3554 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3555 }
3556
3557 if (wmask & TGSI_WRITEMASK_ZW) {
3558 fetch_double_channel(mach, &src0, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3559 fetch_source(mach, &src1, &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_INT);
3560 micro_dldexp(&dst, &src0, &src1);
3561 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3562 }
3563 }
3564
3565 static void
3566 exec_dfracexp(struct tgsi_exec_machine *mach,
3567 const struct tgsi_full_instruction *inst)
3568 {
3569 union tgsi_double_channel src;
3570 union tgsi_double_channel dst;
3571 union tgsi_exec_channel dst_exp;
3572
3573 if (((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY)) {
3574 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3575 micro_dfracexp(&dst, &dst_exp, &src);
3576 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3577 store_dest(mach, &dst_exp, &inst->Dst[1], inst, ffs(inst->Dst[1].Register.WriteMask) - 1, TGSI_EXEC_DATA_INT);
3578 }
3579 if (((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW)) {
3580 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3581 micro_dfracexp(&dst, &dst_exp, &src);
3582 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3583 store_dest(mach, &dst_exp, &inst->Dst[1], inst, ffs(inst->Dst[1].Register.WriteMask) - 1, TGSI_EXEC_DATA_INT);
3584 }
3585 }
3586
3587
3588 static void
3589 micro_i2f(union tgsi_exec_channel *dst,
3590 const union tgsi_exec_channel *src)
3591 {
3592 dst->f[0] = (float)src->i[0];
3593 dst->f[1] = (float)src->i[1];
3594 dst->f[2] = (float)src->i[2];
3595 dst->f[3] = (float)src->i[3];
3596 }
3597
3598 static void
3599 micro_not(union tgsi_exec_channel *dst,
3600 const union tgsi_exec_channel *src)
3601 {
3602 dst->u[0] = ~src->u[0];
3603 dst->u[1] = ~src->u[1];
3604 dst->u[2] = ~src->u[2];
3605 dst->u[3] = ~src->u[3];
3606 }
3607
3608 static void
3609 micro_shl(union tgsi_exec_channel *dst,
3610 const union tgsi_exec_channel *src0,
3611 const union tgsi_exec_channel *src1)
3612 {
3613 unsigned masked_count;
3614 masked_count = src1->u[0] & 0x1f;
3615 dst->u[0] = src0->u[0] << masked_count;
3616 masked_count = src1->u[1] & 0x1f;
3617 dst->u[1] = src0->u[1] << masked_count;
3618 masked_count = src1->u[2] & 0x1f;
3619 dst->u[2] = src0->u[2] << masked_count;
3620 masked_count = src1->u[3] & 0x1f;
3621 dst->u[3] = src0->u[3] << masked_count;
3622 }
3623
3624 static void
3625 micro_and(union tgsi_exec_channel *dst,
3626 const union tgsi_exec_channel *src0,
3627 const union tgsi_exec_channel *src1)
3628 {
3629 dst->u[0] = src0->u[0] & src1->u[0];
3630 dst->u[1] = src0->u[1] & src1->u[1];
3631 dst->u[2] = src0->u[2] & src1->u[2];
3632 dst->u[3] = src0->u[3] & src1->u[3];
3633 }
3634
3635 static void
3636 micro_or(union tgsi_exec_channel *dst,
3637 const union tgsi_exec_channel *src0,
3638 const union tgsi_exec_channel *src1)
3639 {
3640 dst->u[0] = src0->u[0] | src1->u[0];
3641 dst->u[1] = src0->u[1] | src1->u[1];
3642 dst->u[2] = src0->u[2] | src1->u[2];
3643 dst->u[3] = src0->u[3] | src1->u[3];
3644 }
3645
3646 static void
3647 micro_xor(union tgsi_exec_channel *dst,
3648 const union tgsi_exec_channel *src0,
3649 const union tgsi_exec_channel *src1)
3650 {
3651 dst->u[0] = src0->u[0] ^ src1->u[0];
3652 dst->u[1] = src0->u[1] ^ src1->u[1];
3653 dst->u[2] = src0->u[2] ^ src1->u[2];
3654 dst->u[3] = src0->u[3] ^ src1->u[3];
3655 }
3656
3657 static void
3658 micro_mod(union tgsi_exec_channel *dst,
3659 const union tgsi_exec_channel *src0,
3660 const union tgsi_exec_channel *src1)
3661 {
3662 dst->i[0] = src0->i[0] % src1->i[0];
3663 dst->i[1] = src0->i[1] % src1->i[1];
3664 dst->i[2] = src0->i[2] % src1->i[2];
3665 dst->i[3] = src0->i[3] % src1->i[3];
3666 }
3667
3668 static void
3669 micro_f2i(union tgsi_exec_channel *dst,
3670 const union tgsi_exec_channel *src)
3671 {
3672 dst->i[0] = (int)src->f[0];
3673 dst->i[1] = (int)src->f[1];
3674 dst->i[2] = (int)src->f[2];
3675 dst->i[3] = (int)src->f[3];
3676 }
3677
3678 static void
3679 micro_fseq(union tgsi_exec_channel *dst,
3680 const union tgsi_exec_channel *src0,
3681 const union tgsi_exec_channel *src1)
3682 {
3683 dst->u[0] = src0->f[0] == src1->f[0] ? ~0 : 0;
3684 dst->u[1] = src0->f[1] == src1->f[1] ? ~0 : 0;
3685 dst->u[2] = src0->f[2] == src1->f[2] ? ~0 : 0;
3686 dst->u[3] = src0->f[3] == src1->f[3] ? ~0 : 0;
3687 }
3688
3689 static void
3690 micro_fsge(union tgsi_exec_channel *dst,
3691 const union tgsi_exec_channel *src0,
3692 const union tgsi_exec_channel *src1)
3693 {
3694 dst->u[0] = src0->f[0] >= src1->f[0] ? ~0 : 0;
3695 dst->u[1] = src0->f[1] >= src1->f[1] ? ~0 : 0;
3696 dst->u[2] = src0->f[2] >= src1->f[2] ? ~0 : 0;
3697 dst->u[3] = src0->f[3] >= src1->f[3] ? ~0 : 0;
3698 }
3699
3700 static void
3701 micro_fslt(union tgsi_exec_channel *dst,
3702 const union tgsi_exec_channel *src0,
3703 const union tgsi_exec_channel *src1)
3704 {
3705 dst->u[0] = src0->f[0] < src1->f[0] ? ~0 : 0;
3706 dst->u[1] = src0->f[1] < src1->f[1] ? ~0 : 0;
3707 dst->u[2] = src0->f[2] < src1->f[2] ? ~0 : 0;
3708 dst->u[3] = src0->f[3] < src1->f[3] ? ~0 : 0;
3709 }
3710
3711 static void
3712 micro_fsne(union tgsi_exec_channel *dst,
3713 const union tgsi_exec_channel *src0,
3714 const union tgsi_exec_channel *src1)
3715 {
3716 dst->u[0] = src0->f[0] != src1->f[0] ? ~0 : 0;
3717 dst->u[1] = src0->f[1] != src1->f[1] ? ~0 : 0;
3718 dst->u[2] = src0->f[2] != src1->f[2] ? ~0 : 0;
3719 dst->u[3] = src0->f[3] != src1->f[3] ? ~0 : 0;
3720 }
3721
3722 static void
3723 micro_idiv(union tgsi_exec_channel *dst,
3724 const union tgsi_exec_channel *src0,
3725 const union tgsi_exec_channel *src1)
3726 {
3727 dst->i[0] = src1->i[0] ? src0->i[0] / src1->i[0] : 0;
3728 dst->i[1] = src1->i[1] ? src0->i[1] / src1->i[1] : 0;
3729 dst->i[2] = src1->i[2] ? src0->i[2] / src1->i[2] : 0;
3730 dst->i[3] = src1->i[3] ? src0->i[3] / src1->i[3] : 0;
3731 }
3732
3733 static void
3734 micro_imax(union tgsi_exec_channel *dst,
3735 const union tgsi_exec_channel *src0,
3736 const union tgsi_exec_channel *src1)
3737 {
3738 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
3739 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
3740 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
3741 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
3742 }
3743
3744 static void
3745 micro_imin(union tgsi_exec_channel *dst,
3746 const union tgsi_exec_channel *src0,
3747 const union tgsi_exec_channel *src1)
3748 {
3749 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
3750 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
3751 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
3752 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
3753 }
3754
3755 static void
3756 micro_isge(union tgsi_exec_channel *dst,
3757 const union tgsi_exec_channel *src0,
3758 const union tgsi_exec_channel *src1)
3759 {
3760 dst->i[0] = src0->i[0] >= src1->i[0] ? -1 : 0;
3761 dst->i[1] = src0->i[1] >= src1->i[1] ? -1 : 0;
3762 dst->i[2] = src0->i[2] >= src1->i[2] ? -1 : 0;
3763 dst->i[3] = src0->i[3] >= src1->i[3] ? -1 : 0;
3764 }
3765
3766 static void
3767 micro_ishr(union tgsi_exec_channel *dst,
3768 const union tgsi_exec_channel *src0,
3769 const union tgsi_exec_channel *src1)
3770 {
3771 unsigned masked_count;
3772 masked_count = src1->i[0] & 0x1f;
3773 dst->i[0] = src0->i[0] >> masked_count;
3774 masked_count = src1->i[1] & 0x1f;
3775 dst->i[1] = src0->i[1] >> masked_count;
3776 masked_count = src1->i[2] & 0x1f;
3777 dst->i[2] = src0->i[2] >> masked_count;
3778 masked_count = src1->i[3] & 0x1f;
3779 dst->i[3] = src0->i[3] >> masked_count;
3780 }
3781
3782 static void
3783 micro_islt(union tgsi_exec_channel *dst,
3784 const union tgsi_exec_channel *src0,
3785 const union tgsi_exec_channel *src1)
3786 {
3787 dst->i[0] = src0->i[0] < src1->i[0] ? -1 : 0;
3788 dst->i[1] = src0->i[1] < src1->i[1] ? -1 : 0;
3789 dst->i[2] = src0->i[2] < src1->i[2] ? -1 : 0;
3790 dst->i[3] = src0->i[3] < src1->i[3] ? -1 : 0;
3791 }
3792
3793 static void
3794 micro_f2u(union tgsi_exec_channel *dst,
3795 const union tgsi_exec_channel *src)
3796 {
3797 dst->u[0] = (uint)src->f[0];
3798 dst->u[1] = (uint)src->f[1];
3799 dst->u[2] = (uint)src->f[2];
3800 dst->u[3] = (uint)src->f[3];
3801 }
3802
3803 static void
3804 micro_u2f(union tgsi_exec_channel *dst,
3805 const union tgsi_exec_channel *src)
3806 {
3807 dst->f[0] = (float)src->u[0];
3808 dst->f[1] = (float)src->u[1];
3809 dst->f[2] = (float)src->u[2];
3810 dst->f[3] = (float)src->u[3];
3811 }
3812
3813 static void
3814 micro_uadd(union tgsi_exec_channel *dst,
3815 const union tgsi_exec_channel *src0,
3816 const union tgsi_exec_channel *src1)
3817 {
3818 dst->u[0] = src0->u[0] + src1->u[0];
3819 dst->u[1] = src0->u[1] + src1->u[1];
3820 dst->u[2] = src0->u[2] + src1->u[2];
3821 dst->u[3] = src0->u[3] + src1->u[3];
3822 }
3823
3824 static void
3825 micro_udiv(union tgsi_exec_channel *dst,
3826 const union tgsi_exec_channel *src0,
3827 const union tgsi_exec_channel *src1)
3828 {
3829 dst->u[0] = src1->u[0] ? src0->u[0] / src1->u[0] : ~0u;
3830 dst->u[1] = src1->u[1] ? src0->u[1] / src1->u[1] : ~0u;
3831 dst->u[2] = src1->u[2] ? src0->u[2] / src1->u[2] : ~0u;
3832 dst->u[3] = src1->u[3] ? src0->u[3] / src1->u[3] : ~0u;
3833 }
3834
3835 static void
3836 micro_umad(union tgsi_exec_channel *dst,
3837 const union tgsi_exec_channel *src0,
3838 const union tgsi_exec_channel *src1,
3839 const union tgsi_exec_channel *src2)
3840 {
3841 dst->u[0] = src0->u[0] * src1->u[0] + src2->u[0];
3842 dst->u[1] = src0->u[1] * src1->u[1] + src2->u[1];
3843 dst->u[2] = src0->u[2] * src1->u[2] + src2->u[2];
3844 dst->u[3] = src0->u[3] * src1->u[3] + src2->u[3];
3845 }
3846
3847 static void
3848 micro_umax(union tgsi_exec_channel *dst,
3849 const union tgsi_exec_channel *src0,
3850 const union tgsi_exec_channel *src1)
3851 {
3852 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
3853 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
3854 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
3855 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
3856 }
3857
3858 static void
3859 micro_umin(union tgsi_exec_channel *dst,
3860 const union tgsi_exec_channel *src0,
3861 const union tgsi_exec_channel *src1)
3862 {
3863 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
3864 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
3865 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
3866 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
3867 }
3868
3869 static void
3870 micro_umod(union tgsi_exec_channel *dst,
3871 const union tgsi_exec_channel *src0,
3872 const union tgsi_exec_channel *src1)
3873 {
3874 dst->u[0] = src1->u[0] ? src0->u[0] % src1->u[0] : ~0u;
3875 dst->u[1] = src1->u[1] ? src0->u[1] % src1->u[1] : ~0u;
3876 dst->u[2] = src1->u[2] ? src0->u[2] % src1->u[2] : ~0u;
3877 dst->u[3] = src1->u[3] ? src0->u[3] % src1->u[3] : ~0u;
3878 }
3879
3880 static void
3881 micro_umul(union tgsi_exec_channel *dst,
3882 const union tgsi_exec_channel *src0,
3883 const union tgsi_exec_channel *src1)
3884 {
3885 dst->u[0] = src0->u[0] * src1->u[0];
3886 dst->u[1] = src0->u[1] * src1->u[1];
3887 dst->u[2] = src0->u[2] * src1->u[2];
3888 dst->u[3] = src0->u[3] * src1->u[3];
3889 }
3890
3891 static void
3892 micro_imul_hi(union tgsi_exec_channel *dst,
3893 const union tgsi_exec_channel *src0,
3894 const union tgsi_exec_channel *src1)
3895 {
3896 #define I64M(x, y) ((((int64_t)x) * ((int64_t)y)) >> 32)
3897 dst->i[0] = I64M(src0->i[0], src1->i[0]);
3898 dst->i[1] = I64M(src0->i[1], src1->i[1]);
3899 dst->i[2] = I64M(src0->i[2], src1->i[2]);
3900 dst->i[3] = I64M(src0->i[3], src1->i[3]);
3901 #undef I64M
3902 }
3903
3904 static void
3905 micro_umul_hi(union tgsi_exec_channel *dst,
3906 const union tgsi_exec_channel *src0,
3907 const union tgsi_exec_channel *src1)
3908 {
3909 #define U64M(x, y) ((((uint64_t)x) * ((uint64_t)y)) >> 32)
3910 dst->u[0] = U64M(src0->u[0], src1->u[0]);
3911 dst->u[1] = U64M(src0->u[1], src1->u[1]);
3912 dst->u[2] = U64M(src0->u[2], src1->u[2]);
3913 dst->u[3] = U64M(src0->u[3], src1->u[3]);
3914 #undef U64M
3915 }
3916
3917 static void
3918 micro_useq(union tgsi_exec_channel *dst,
3919 const union tgsi_exec_channel *src0,
3920 const union tgsi_exec_channel *src1)
3921 {
3922 dst->u[0] = src0->u[0] == src1->u[0] ? ~0 : 0;
3923 dst->u[1] = src0->u[1] == src1->u[1] ? ~0 : 0;
3924 dst->u[2] = src0->u[2] == src1->u[2] ? ~0 : 0;
3925 dst->u[3] = src0->u[3] == src1->u[3] ? ~0 : 0;
3926 }
3927
3928 static void
3929 micro_usge(union tgsi_exec_channel *dst,
3930 const union tgsi_exec_channel *src0,
3931 const union tgsi_exec_channel *src1)
3932 {
3933 dst->u[0] = src0->u[0] >= src1->u[0] ? ~0 : 0;
3934 dst->u[1] = src0->u[1] >= src1->u[1] ? ~0 : 0;
3935 dst->u[2] = src0->u[2] >= src1->u[2] ? ~0 : 0;
3936 dst->u[3] = src0->u[3] >= src1->u[3] ? ~0 : 0;
3937 }
3938
3939 static void
3940 micro_ushr(union tgsi_exec_channel *dst,
3941 const union tgsi_exec_channel *src0,
3942 const union tgsi_exec_channel *src1)
3943 {
3944 unsigned masked_count;
3945 masked_count = src1->u[0] & 0x1f;
3946 dst->u[0] = src0->u[0] >> masked_count;
3947 masked_count = src1->u[1] & 0x1f;
3948 dst->u[1] = src0->u[1] >> masked_count;
3949 masked_count = src1->u[2] & 0x1f;
3950 dst->u[2] = src0->u[2] >> masked_count;
3951 masked_count = src1->u[3] & 0x1f;
3952 dst->u[3] = src0->u[3] >> masked_count;
3953 }
3954
3955 static void
3956 micro_uslt(union tgsi_exec_channel *dst,
3957 const union tgsi_exec_channel *src0,
3958 const union tgsi_exec_channel *src1)
3959 {
3960 dst->u[0] = src0->u[0] < src1->u[0] ? ~0 : 0;
3961 dst->u[1] = src0->u[1] < src1->u[1] ? ~0 : 0;
3962 dst->u[2] = src0->u[2] < src1->u[2] ? ~0 : 0;
3963 dst->u[3] = src0->u[3] < src1->u[3] ? ~0 : 0;
3964 }
3965
3966 static void
3967 micro_usne(union tgsi_exec_channel *dst,
3968 const union tgsi_exec_channel *src0,
3969 const union tgsi_exec_channel *src1)
3970 {
3971 dst->u[0] = src0->u[0] != src1->u[0] ? ~0 : 0;
3972 dst->u[1] = src0->u[1] != src1->u[1] ? ~0 : 0;
3973 dst->u[2] = src0->u[2] != src1->u[2] ? ~0 : 0;
3974 dst->u[3] = src0->u[3] != src1->u[3] ? ~0 : 0;
3975 }
3976
3977 static void
3978 micro_uarl(union tgsi_exec_channel *dst,
3979 const union tgsi_exec_channel *src)
3980 {
3981 dst->i[0] = src->u[0];
3982 dst->i[1] = src->u[1];
3983 dst->i[2] = src->u[2];
3984 dst->i[3] = src->u[3];
3985 }
3986
3987 static void
3988 micro_ucmp(union tgsi_exec_channel *dst,
3989 const union tgsi_exec_channel *src0,
3990 const union tgsi_exec_channel *src1,
3991 const union tgsi_exec_channel *src2)
3992 {
3993 dst->u[0] = src0->u[0] ? src1->u[0] : src2->u[0];
3994 dst->u[1] = src0->u[1] ? src1->u[1] : src2->u[1];
3995 dst->u[2] = src0->u[2] ? src1->u[2] : src2->u[2];
3996 dst->u[3] = src0->u[3] ? src1->u[3] : src2->u[3];
3997 }
3998
3999 /**
4000 * Signed bitfield extract (i.e. sign-extend the extracted bits)
4001 */
4002 static void
4003 micro_ibfe(union tgsi_exec_channel *dst,
4004 const union tgsi_exec_channel *src0,
4005 const union tgsi_exec_channel *src1,
4006 const union tgsi_exec_channel *src2)
4007 {
4008 int i;
4009 for (i = 0; i < 4; i++) {
4010 int width = src2->i[i] & 0x1f;
4011 int offset = src1->i[i] & 0x1f;
4012 if (width == 0)
4013 dst->i[i] = 0;
4014 else if (width + offset < 32)
4015 dst->i[i] = (src0->i[i] << (32 - width - offset)) >> (32 - width);
4016 else
4017 dst->i[i] = src0->i[i] >> offset;
4018 }
4019 }
4020
4021 /**
4022 * Unsigned bitfield extract
4023 */
4024 static void
4025 micro_ubfe(union tgsi_exec_channel *dst,
4026 const union tgsi_exec_channel *src0,
4027 const union tgsi_exec_channel *src1,
4028 const union tgsi_exec_channel *src2)
4029 {
4030 int i;
4031 for (i = 0; i < 4; i++) {
4032 int width = src2->u[i] & 0x1f;
4033 int offset = src1->u[i] & 0x1f;
4034 if (width == 0)
4035 dst->u[i] = 0;
4036 else if (width + offset < 32)
4037 dst->u[i] = (src0->u[i] << (32 - width - offset)) >> (32 - width);
4038 else
4039 dst->u[i] = src0->u[i] >> offset;
4040 }
4041 }
4042
4043 /**
4044 * Bitfield insert: copy low bits from src1 into a region of src0.
4045 */
4046 static void
4047 micro_bfi(union tgsi_exec_channel *dst,
4048 const union tgsi_exec_channel *src0,
4049 const union tgsi_exec_channel *src1,
4050 const union tgsi_exec_channel *src2,
4051 const union tgsi_exec_channel *src3)
4052 {
4053 int i;
4054 for (i = 0; i < 4; i++) {
4055 int width = src3->u[i] & 0x1f;
4056 int offset = src2->u[i] & 0x1f;
4057 int bitmask = ((1 << width) - 1) << offset;
4058 dst->u[i] = ((src1->u[i] << offset) & bitmask) | (src0->u[i] & ~bitmask);
4059 }
4060 }
4061
4062 static void
4063 micro_brev(union tgsi_exec_channel *dst,
4064 const union tgsi_exec_channel *src)
4065 {
4066 dst->u[0] = util_bitreverse(src->u[0]);
4067 dst->u[1] = util_bitreverse(src->u[1]);
4068 dst->u[2] = util_bitreverse(src->u[2]);
4069 dst->u[3] = util_bitreverse(src->u[3]);
4070 }
4071
4072 static void
4073 micro_popc(union tgsi_exec_channel *dst,
4074 const union tgsi_exec_channel *src)
4075 {
4076 dst->u[0] = util_bitcount(src->u[0]);
4077 dst->u[1] = util_bitcount(src->u[1]);
4078 dst->u[2] = util_bitcount(src->u[2]);
4079 dst->u[3] = util_bitcount(src->u[3]);
4080 }
4081
4082 static void
4083 micro_lsb(union tgsi_exec_channel *dst,
4084 const union tgsi_exec_channel *src)
4085 {
4086 dst->i[0] = ffs(src->u[0]) - 1;
4087 dst->i[1] = ffs(src->u[1]) - 1;
4088 dst->i[2] = ffs(src->u[2]) - 1;
4089 dst->i[3] = ffs(src->u[3]) - 1;
4090 }
4091
4092 static void
4093 micro_imsb(union tgsi_exec_channel *dst,
4094 const union tgsi_exec_channel *src)
4095 {
4096 dst->i[0] = util_last_bit_signed(src->i[0]) - 1;
4097 dst->i[1] = util_last_bit_signed(src->i[1]) - 1;
4098 dst->i[2] = util_last_bit_signed(src->i[2]) - 1;
4099 dst->i[3] = util_last_bit_signed(src->i[3]) - 1;
4100 }
4101
4102 static void
4103 micro_umsb(union tgsi_exec_channel *dst,
4104 const union tgsi_exec_channel *src)
4105 {
4106 dst->i[0] = util_last_bit(src->u[0]) - 1;
4107 dst->i[1] = util_last_bit(src->u[1]) - 1;
4108 dst->i[2] = util_last_bit(src->u[2]) - 1;
4109 dst->i[3] = util_last_bit(src->u[3]) - 1;
4110 }
4111
4112 static void
4113 exec_instruction(
4114 struct tgsi_exec_machine *mach,
4115 const struct tgsi_full_instruction *inst,
4116 int *pc )
4117 {
4118 union tgsi_exec_channel r[10];
4119
4120 (*pc)++;
4121
4122 switch (inst->Instruction.Opcode) {
4123 case TGSI_OPCODE_ARL:
4124 exec_vector_unary(mach, inst, micro_arl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4125 break;
4126
4127 case TGSI_OPCODE_MOV:
4128 exec_vector_unary(mach, inst, micro_mov, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4129 break;
4130
4131 case TGSI_OPCODE_LIT:
4132 exec_lit(mach, inst);
4133 break;
4134
4135 case TGSI_OPCODE_RCP:
4136 exec_scalar_unary(mach, inst, micro_rcp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4137 break;
4138
4139 case TGSI_OPCODE_RSQ:
4140 exec_scalar_unary(mach, inst, micro_rsq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4141 break;
4142
4143 case TGSI_OPCODE_EXP:
4144 exec_exp(mach, inst);
4145 break;
4146
4147 case TGSI_OPCODE_LOG:
4148 exec_log(mach, inst);
4149 break;
4150
4151 case TGSI_OPCODE_MUL:
4152 exec_vector_binary(mach, inst, micro_mul, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4153 break;
4154
4155 case TGSI_OPCODE_ADD:
4156 exec_vector_binary(mach, inst, micro_add, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4157 break;
4158
4159 case TGSI_OPCODE_DP3:
4160 exec_dp3(mach, inst);
4161 break;
4162
4163 case TGSI_OPCODE_DP4:
4164 exec_dp4(mach, inst);
4165 break;
4166
4167 case TGSI_OPCODE_DST:
4168 exec_dst(mach, inst);
4169 break;
4170
4171 case TGSI_OPCODE_MIN:
4172 exec_vector_binary(mach, inst, micro_min, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4173 break;
4174
4175 case TGSI_OPCODE_MAX:
4176 exec_vector_binary(mach, inst, micro_max, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4177 break;
4178
4179 case TGSI_OPCODE_SLT:
4180 exec_vector_binary(mach, inst, micro_slt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4181 break;
4182
4183 case TGSI_OPCODE_SGE:
4184 exec_vector_binary(mach, inst, micro_sge, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4185 break;
4186
4187 case TGSI_OPCODE_MAD:
4188 exec_vector_trinary(mach, inst, micro_mad, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4189 break;
4190
4191 case TGSI_OPCODE_SUB:
4192 exec_vector_binary(mach, inst, micro_sub, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4193 break;
4194
4195 case TGSI_OPCODE_LRP:
4196 exec_vector_trinary(mach, inst, micro_lrp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4197 break;
4198
4199 case TGSI_OPCODE_SQRT:
4200 exec_scalar_unary(mach, inst, micro_sqrt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4201 break;
4202
4203 case TGSI_OPCODE_DP2A:
4204 exec_dp2a(mach, inst);
4205 break;
4206
4207 case TGSI_OPCODE_FRC:
4208 exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4209 break;
4210
4211 case TGSI_OPCODE_CLAMP:
4212 exec_vector_trinary(mach, inst, micro_clamp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4213 break;
4214
4215 case TGSI_OPCODE_FLR:
4216 exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4217 break;
4218
4219 case TGSI_OPCODE_ROUND:
4220 exec_vector_unary(mach, inst, micro_rnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4221 break;
4222
4223 case TGSI_OPCODE_EX2:
4224 exec_scalar_unary(mach, inst, micro_exp2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4225 break;
4226
4227 case TGSI_OPCODE_LG2:
4228 exec_scalar_unary(mach, inst, micro_lg2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4229 break;
4230
4231 case TGSI_OPCODE_POW:
4232 exec_scalar_binary(mach, inst, micro_pow, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4233 break;
4234
4235 case TGSI_OPCODE_XPD:
4236 exec_xpd(mach, inst);
4237 break;
4238
4239 case TGSI_OPCODE_ABS:
4240 exec_vector_unary(mach, inst, micro_abs, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4241 break;
4242
4243 case TGSI_OPCODE_DPH:
4244 exec_dph(mach, inst);
4245 break;
4246
4247 case TGSI_OPCODE_COS:
4248 exec_scalar_unary(mach, inst, micro_cos, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4249 break;
4250
4251 case TGSI_OPCODE_DDX:
4252 exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4253 break;
4254
4255 case TGSI_OPCODE_DDY:
4256 exec_vector_unary(mach, inst, micro_ddy, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4257 break;
4258
4259 case TGSI_OPCODE_KILL:
4260 exec_kill (mach, inst);
4261 break;
4262
4263 case TGSI_OPCODE_KILL_IF:
4264 exec_kill_if (mach, inst);
4265 break;
4266
4267 case TGSI_OPCODE_PK2H:
4268 assert (0);
4269 break;
4270
4271 case TGSI_OPCODE_PK2US:
4272 assert (0);
4273 break;
4274
4275 case TGSI_OPCODE_PK4B:
4276 assert (0);
4277 break;
4278
4279 case TGSI_OPCODE_PK4UB:
4280 assert (0);
4281 break;
4282
4283 case TGSI_OPCODE_SEQ:
4284 exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4285 break;
4286
4287 case TGSI_OPCODE_SGT:
4288 exec_vector_binary(mach, inst, micro_sgt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4289 break;
4290
4291 case TGSI_OPCODE_SIN:
4292 exec_scalar_unary(mach, inst, micro_sin, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4293 break;
4294
4295 case TGSI_OPCODE_SLE:
4296 exec_vector_binary(mach, inst, micro_sle, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4297 break;
4298
4299 case TGSI_OPCODE_SNE:
4300 exec_vector_binary(mach, inst, micro_sne, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4301 break;
4302
4303 case TGSI_OPCODE_TEX:
4304 /* simple texture lookup */
4305 /* src[0] = texcoord */
4306 /* src[1] = sampler unit */
4307 exec_tex(mach, inst, TEX_MODIFIER_NONE, 1);
4308 break;
4309
4310 case TGSI_OPCODE_TXB:
4311 /* Texture lookup with lod bias */
4312 /* src[0] = texcoord (src[0].w = LOD bias) */
4313 /* src[1] = sampler unit */
4314 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 1);
4315 break;
4316
4317 case TGSI_OPCODE_TXD:
4318 /* Texture lookup with explict partial derivatives */
4319 /* src[0] = texcoord */
4320 /* src[1] = d[strq]/dx */
4321 /* src[2] = d[strq]/dy */
4322 /* src[3] = sampler unit */
4323 exec_txd(mach, inst);
4324 break;
4325
4326 case TGSI_OPCODE_TXL:
4327 /* Texture lookup with explit LOD */
4328 /* src[0] = texcoord (src[0].w = LOD) */
4329 /* src[1] = sampler unit */
4330 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 1);
4331 break;
4332
4333 case TGSI_OPCODE_TXP:
4334 /* Texture lookup with projection */
4335 /* src[0] = texcoord (src[0].w = projection) */
4336 /* src[1] = sampler unit */
4337 exec_tex(mach, inst, TEX_MODIFIER_PROJECTED, 1);
4338 break;
4339
4340 case TGSI_OPCODE_TG4:
4341 /* src[0] = texcoord */
4342 /* src[1] = component */
4343 /* src[2] = sampler unit */
4344 exec_tex(mach, inst, TEX_MODIFIER_GATHER, 2);
4345 break;
4346
4347 case TGSI_OPCODE_UP2H:
4348 assert (0);
4349 break;
4350
4351 case TGSI_OPCODE_UP2US:
4352 assert (0);
4353 break;
4354
4355 case TGSI_OPCODE_UP4B:
4356 assert (0);
4357 break;
4358
4359 case TGSI_OPCODE_UP4UB:
4360 assert (0);
4361 break;
4362
4363 case TGSI_OPCODE_ARR:
4364 exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4365 break;
4366
4367 case TGSI_OPCODE_CAL:
4368 /* skip the call if no execution channels are enabled */
4369 if (mach->ExecMask) {
4370 /* do the call */
4371
4372 /* First, record the depths of the execution stacks.
4373 * This is important for deeply nested/looped return statements.
4374 * We have to unwind the stacks by the correct amount. For a
4375 * real code generator, we could determine the number of entries
4376 * to pop off each stack with simple static analysis and avoid
4377 * implementing this data structure at run time.
4378 */
4379 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
4380 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
4381 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
4382 mach->CallStack[mach->CallStackTop].SwitchStackTop = mach->SwitchStackTop;
4383 mach->CallStack[mach->CallStackTop].BreakStackTop = mach->BreakStackTop;
4384 /* note that PC was already incremented above */
4385 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
4386
4387 mach->CallStackTop++;
4388
4389 /* Second, push the Cond, Loop, Cont, Func stacks */
4390 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
4391 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4392 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4393 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
4394 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
4395 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
4396
4397 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
4398 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
4399 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
4400 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
4401 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
4402 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
4403
4404 /* Finally, jump to the subroutine. The label is a pointer
4405 * (an instruction number) to the BGNSUB instruction.
4406 */
4407 *pc = inst->Label.Label;
4408 assert(mach->Instructions[*pc].Instruction.Opcode
4409 == TGSI_OPCODE_BGNSUB);
4410 }
4411 break;
4412
4413 case TGSI_OPCODE_RET:
4414 mach->FuncMask &= ~mach->ExecMask;
4415 UPDATE_EXEC_MASK(mach);
4416
4417 if (mach->FuncMask == 0x0) {
4418 /* really return now (otherwise, keep executing */
4419
4420 if (mach->CallStackTop == 0) {
4421 /* returning from main() */
4422 mach->CondStackTop = 0;
4423 mach->LoopStackTop = 0;
4424 *pc = -1;
4425 return;
4426 }
4427
4428 assert(mach->CallStackTop > 0);
4429 mach->CallStackTop--;
4430
4431 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
4432 mach->CondMask = mach->CondStack[mach->CondStackTop];
4433
4434 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
4435 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
4436
4437 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
4438 mach->ContMask = mach->ContStack[mach->ContStackTop];
4439
4440 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
4441 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
4442
4443 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
4444 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
4445
4446 assert(mach->FuncStackTop > 0);
4447 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
4448
4449 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
4450
4451 UPDATE_EXEC_MASK(mach);
4452 }
4453 break;
4454
4455 case TGSI_OPCODE_SSG:
4456 exec_vector_unary(mach, inst, micro_sgn, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4457 break;
4458
4459 case TGSI_OPCODE_CMP:
4460 exec_vector_trinary(mach, inst, micro_cmp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4461 break;
4462
4463 case TGSI_OPCODE_SCS:
4464 exec_scs(mach, inst);
4465 break;
4466
4467 case TGSI_OPCODE_DIV:
4468 exec_vector_binary(mach, inst, micro_div, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4469 break;
4470
4471 case TGSI_OPCODE_DP2:
4472 exec_dp2(mach, inst);
4473 break;
4474
4475 case TGSI_OPCODE_IF:
4476 /* push CondMask */
4477 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
4478 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
4479 FETCH( &r[0], 0, TGSI_CHAN_X );
4480 /* update CondMask */
4481 if( ! r[0].f[0] ) {
4482 mach->CondMask &= ~0x1;
4483 }
4484 if( ! r[0].f[1] ) {
4485 mach->CondMask &= ~0x2;
4486 }
4487 if( ! r[0].f[2] ) {
4488 mach->CondMask &= ~0x4;
4489 }
4490 if( ! r[0].f[3] ) {
4491 mach->CondMask &= ~0x8;
4492 }
4493 UPDATE_EXEC_MASK(mach);
4494 /* Todo: If CondMask==0, jump to ELSE */
4495 break;
4496
4497 case TGSI_OPCODE_UIF:
4498 /* push CondMask */
4499 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
4500 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
4501 IFETCH( &r[0], 0, TGSI_CHAN_X );
4502 /* update CondMask */
4503 if( ! r[0].u[0] ) {
4504 mach->CondMask &= ~0x1;
4505 }
4506 if( ! r[0].u[1] ) {
4507 mach->CondMask &= ~0x2;
4508 }
4509 if( ! r[0].u[2] ) {
4510 mach->CondMask &= ~0x4;
4511 }
4512 if( ! r[0].u[3] ) {
4513 mach->CondMask &= ~0x8;
4514 }
4515 UPDATE_EXEC_MASK(mach);
4516 /* Todo: If CondMask==0, jump to ELSE */
4517 break;
4518
4519 case TGSI_OPCODE_ELSE:
4520 /* invert CondMask wrt previous mask */
4521 {
4522 uint prevMask;
4523 assert(mach->CondStackTop > 0);
4524 prevMask = mach->CondStack[mach->CondStackTop - 1];
4525 mach->CondMask = ~mach->CondMask & prevMask;
4526 UPDATE_EXEC_MASK(mach);
4527 /* Todo: If CondMask==0, jump to ENDIF */
4528 }
4529 break;
4530
4531 case TGSI_OPCODE_ENDIF:
4532 /* pop CondMask */
4533 assert(mach->CondStackTop > 0);
4534 mach->CondMask = mach->CondStack[--mach->CondStackTop];
4535 UPDATE_EXEC_MASK(mach);
4536 break;
4537
4538 case TGSI_OPCODE_END:
4539 /* make sure we end primitives which haven't
4540 * been explicitly emitted */
4541 conditional_emit_primitive(mach);
4542 /* halt execution */
4543 *pc = -1;
4544 break;
4545
4546 case TGSI_OPCODE_PUSHA:
4547 assert (0);
4548 break;
4549
4550 case TGSI_OPCODE_POPA:
4551 assert (0);
4552 break;
4553
4554 case TGSI_OPCODE_CEIL:
4555 exec_vector_unary(mach, inst, micro_ceil, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4556 break;
4557
4558 case TGSI_OPCODE_I2F:
4559 exec_vector_unary(mach, inst, micro_i2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
4560 break;
4561
4562 case TGSI_OPCODE_NOT:
4563 exec_vector_unary(mach, inst, micro_not, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4564 break;
4565
4566 case TGSI_OPCODE_TRUNC:
4567 exec_vector_unary(mach, inst, micro_trunc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4568 break;
4569
4570 case TGSI_OPCODE_SHL:
4571 exec_vector_binary(mach, inst, micro_shl, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4572 break;
4573
4574 case TGSI_OPCODE_AND:
4575 exec_vector_binary(mach, inst, micro_and, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4576 break;
4577
4578 case TGSI_OPCODE_OR:
4579 exec_vector_binary(mach, inst, micro_or, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4580 break;
4581
4582 case TGSI_OPCODE_MOD:
4583 exec_vector_binary(mach, inst, micro_mod, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4584 break;
4585
4586 case TGSI_OPCODE_XOR:
4587 exec_vector_binary(mach, inst, micro_xor, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4588 break;
4589
4590 case TGSI_OPCODE_SAD:
4591 assert (0);
4592 break;
4593
4594 case TGSI_OPCODE_TXF:
4595 exec_txf(mach, inst);
4596 break;
4597
4598 case TGSI_OPCODE_TXQ:
4599 exec_txq(mach, inst);
4600 break;
4601
4602 case TGSI_OPCODE_EMIT:
4603 emit_vertex(mach);
4604 break;
4605
4606 case TGSI_OPCODE_ENDPRIM:
4607 emit_primitive(mach);
4608 break;
4609
4610 case TGSI_OPCODE_BGNLOOP:
4611 /* push LoopMask and ContMasks */
4612 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4613 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4614 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4615 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
4616
4617 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
4618 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
4619 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
4620 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
4621 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_LOOP;
4622 break;
4623
4624 case TGSI_OPCODE_ENDLOOP:
4625 /* Restore ContMask, but don't pop */
4626 assert(mach->ContStackTop > 0);
4627 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
4628 UPDATE_EXEC_MASK(mach);
4629 if (mach->ExecMask) {
4630 /* repeat loop: jump to instruction just past BGNLOOP */
4631 assert(mach->LoopLabelStackTop > 0);
4632 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
4633 }
4634 else {
4635 /* exit loop: pop LoopMask */
4636 assert(mach->LoopStackTop > 0);
4637 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
4638 /* pop ContMask */
4639 assert(mach->ContStackTop > 0);
4640 mach->ContMask = mach->ContStack[--mach->ContStackTop];
4641 assert(mach->LoopLabelStackTop > 0);
4642 --mach->LoopLabelStackTop;
4643
4644 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
4645 }
4646 UPDATE_EXEC_MASK(mach);
4647 break;
4648
4649 case TGSI_OPCODE_BRK:
4650 exec_break(mach);
4651 break;
4652
4653 case TGSI_OPCODE_CONT:
4654 /* turn off cont channels for each enabled exec channel */
4655 mach->ContMask &= ~mach->ExecMask;
4656 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4657 UPDATE_EXEC_MASK(mach);
4658 break;
4659
4660 case TGSI_OPCODE_BGNSUB:
4661 /* no-op */
4662 break;
4663
4664 case TGSI_OPCODE_ENDSUB:
4665 /*
4666 * XXX: This really should be a no-op. We should never reach this opcode.
4667 */
4668
4669 assert(mach->CallStackTop > 0);
4670 mach->CallStackTop--;
4671
4672 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
4673 mach->CondMask = mach->CondStack[mach->CondStackTop];
4674
4675 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
4676 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
4677
4678 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
4679 mach->ContMask = mach->ContStack[mach->ContStackTop];
4680
4681 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
4682 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
4683
4684 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
4685 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
4686
4687 assert(mach->FuncStackTop > 0);
4688 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
4689
4690 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
4691
4692 UPDATE_EXEC_MASK(mach);
4693 break;
4694
4695 case TGSI_OPCODE_NOP:
4696 break;
4697
4698 case TGSI_OPCODE_BREAKC:
4699 IFETCH(&r[0], 0, TGSI_CHAN_X);
4700 /* update CondMask */
4701 if (r[0].u[0] && (mach->ExecMask & 0x1)) {
4702 mach->LoopMask &= ~0x1;
4703 }
4704 if (r[0].u[1] && (mach->ExecMask & 0x2)) {
4705 mach->LoopMask &= ~0x2;
4706 }
4707 if (r[0].u[2] && (mach->ExecMask & 0x4)) {
4708 mach->LoopMask &= ~0x4;
4709 }
4710 if (r[0].u[3] && (mach->ExecMask & 0x8)) {
4711 mach->LoopMask &= ~0x8;
4712 }
4713 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4714 UPDATE_EXEC_MASK(mach);
4715 break;
4716
4717 case TGSI_OPCODE_F2I:
4718 exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4719 break;
4720
4721 case TGSI_OPCODE_FSEQ:
4722 exec_vector_binary(mach, inst, micro_fseq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4723 break;
4724
4725 case TGSI_OPCODE_FSGE:
4726 exec_vector_binary(mach, inst, micro_fsge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4727 break;
4728
4729 case TGSI_OPCODE_FSLT:
4730 exec_vector_binary(mach, inst, micro_fslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4731 break;
4732
4733 case TGSI_OPCODE_FSNE:
4734 exec_vector_binary(mach, inst, micro_fsne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4735 break;
4736
4737 case TGSI_OPCODE_IDIV:
4738 exec_vector_binary(mach, inst, micro_idiv, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4739 break;
4740
4741 case TGSI_OPCODE_IMAX:
4742 exec_vector_binary(mach, inst, micro_imax, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4743 break;
4744
4745 case TGSI_OPCODE_IMIN:
4746 exec_vector_binary(mach, inst, micro_imin, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4747 break;
4748
4749 case TGSI_OPCODE_INEG:
4750 exec_vector_unary(mach, inst, micro_ineg, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4751 break;
4752
4753 case TGSI_OPCODE_ISGE:
4754 exec_vector_binary(mach, inst, micro_isge, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4755 break;
4756
4757 case TGSI_OPCODE_ISHR:
4758 exec_vector_binary(mach, inst, micro_ishr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4759 break;
4760
4761 case TGSI_OPCODE_ISLT:
4762 exec_vector_binary(mach, inst, micro_islt, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4763 break;
4764
4765 case TGSI_OPCODE_F2U:
4766 exec_vector_unary(mach, inst, micro_f2u, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4767 break;
4768
4769 case TGSI_OPCODE_U2F:
4770 exec_vector_unary(mach, inst, micro_u2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_UINT);
4771 break;
4772
4773 case TGSI_OPCODE_UADD:
4774 exec_vector_binary(mach, inst, micro_uadd, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4775 break;
4776
4777 case TGSI_OPCODE_UDIV:
4778 exec_vector_binary(mach, inst, micro_udiv, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4779 break;
4780
4781 case TGSI_OPCODE_UMAD:
4782 exec_vector_trinary(mach, inst, micro_umad, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4783 break;
4784
4785 case TGSI_OPCODE_UMAX:
4786 exec_vector_binary(mach, inst, micro_umax, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4787 break;
4788
4789 case TGSI_OPCODE_UMIN:
4790 exec_vector_binary(mach, inst, micro_umin, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4791 break;
4792
4793 case TGSI_OPCODE_UMOD:
4794 exec_vector_binary(mach, inst, micro_umod, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4795 break;
4796
4797 case TGSI_OPCODE_UMUL:
4798 exec_vector_binary(mach, inst, micro_umul, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4799 break;
4800
4801 case TGSI_OPCODE_IMUL_HI:
4802 exec_vector_binary(mach, inst, micro_imul_hi, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4803 break;
4804
4805 case TGSI_OPCODE_UMUL_HI:
4806 exec_vector_binary(mach, inst, micro_umul_hi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4807 break;
4808
4809 case TGSI_OPCODE_USEQ:
4810 exec_vector_binary(mach, inst, micro_useq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4811 break;
4812
4813 case TGSI_OPCODE_USGE:
4814 exec_vector_binary(mach, inst, micro_usge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4815 break;
4816
4817 case TGSI_OPCODE_USHR:
4818 exec_vector_binary(mach, inst, micro_ushr, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4819 break;
4820
4821 case TGSI_OPCODE_USLT:
4822 exec_vector_binary(mach, inst, micro_uslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4823 break;
4824
4825 case TGSI_OPCODE_USNE:
4826 exec_vector_binary(mach, inst, micro_usne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4827 break;
4828
4829 case TGSI_OPCODE_SWITCH:
4830 exec_switch(mach, inst);
4831 break;
4832
4833 case TGSI_OPCODE_CASE:
4834 exec_case(mach, inst);
4835 break;
4836
4837 case TGSI_OPCODE_DEFAULT:
4838 exec_default(mach);
4839 break;
4840
4841 case TGSI_OPCODE_ENDSWITCH:
4842 exec_endswitch(mach);
4843 break;
4844
4845 case TGSI_OPCODE_SAMPLE_I:
4846 exec_txf(mach, inst);
4847 break;
4848
4849 case TGSI_OPCODE_SAMPLE_I_MS:
4850 assert(0);
4851 break;
4852
4853 case TGSI_OPCODE_SAMPLE:
4854 exec_sample(mach, inst, TEX_MODIFIER_NONE, FALSE);
4855 break;
4856
4857 case TGSI_OPCODE_SAMPLE_B:
4858 exec_sample(mach, inst, TEX_MODIFIER_LOD_BIAS, FALSE);
4859 break;
4860
4861 case TGSI_OPCODE_SAMPLE_C:
4862 exec_sample(mach, inst, TEX_MODIFIER_NONE, TRUE);
4863 break;
4864
4865 case TGSI_OPCODE_SAMPLE_C_LZ:
4866 exec_sample(mach, inst, TEX_MODIFIER_LEVEL_ZERO, TRUE);
4867 break;
4868
4869 case TGSI_OPCODE_SAMPLE_D:
4870 exec_sample_d(mach, inst);
4871 break;
4872
4873 case TGSI_OPCODE_SAMPLE_L:
4874 exec_sample(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, FALSE);
4875 break;
4876
4877 case TGSI_OPCODE_GATHER4:
4878 assert(0);
4879 break;
4880
4881 case TGSI_OPCODE_SVIEWINFO:
4882 exec_txq(mach, inst);
4883 break;
4884
4885 case TGSI_OPCODE_SAMPLE_POS:
4886 assert(0);
4887 break;
4888
4889 case TGSI_OPCODE_SAMPLE_INFO:
4890 assert(0);
4891 break;
4892
4893 case TGSI_OPCODE_UARL:
4894 exec_vector_unary(mach, inst, micro_uarl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
4895 break;
4896
4897 case TGSI_OPCODE_UCMP:
4898 exec_vector_trinary(mach, inst, micro_ucmp, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4899 break;
4900
4901 case TGSI_OPCODE_IABS:
4902 exec_vector_unary(mach, inst, micro_iabs, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4903 break;
4904
4905 case TGSI_OPCODE_ISSG:
4906 exec_vector_unary(mach, inst, micro_isgn, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4907 break;
4908
4909 case TGSI_OPCODE_TEX2:
4910 /* simple texture lookup */
4911 /* src[0] = texcoord */
4912 /* src[1] = compare */
4913 /* src[2] = sampler unit */
4914 exec_tex(mach, inst, TEX_MODIFIER_NONE, 2);
4915 break;
4916 case TGSI_OPCODE_TXB2:
4917 /* simple texture lookup */
4918 /* src[0] = texcoord */
4919 /* src[1] = bias */
4920 /* src[2] = sampler unit */
4921 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 2);
4922 break;
4923 case TGSI_OPCODE_TXL2:
4924 /* simple texture lookup */
4925 /* src[0] = texcoord */
4926 /* src[1] = lod */
4927 /* src[2] = sampler unit */
4928 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 2);
4929 break;
4930
4931 case TGSI_OPCODE_IBFE:
4932 exec_vector_trinary(mach, inst, micro_ibfe, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4933 break;
4934 case TGSI_OPCODE_UBFE:
4935 exec_vector_trinary(mach, inst, micro_ubfe, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4936 break;
4937 case TGSI_OPCODE_BFI:
4938 exec_vector_quaternary(mach, inst, micro_bfi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4939 break;
4940 case TGSI_OPCODE_BREV:
4941 exec_vector_unary(mach, inst, micro_brev, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4942 break;
4943 case TGSI_OPCODE_POPC:
4944 exec_vector_unary(mach, inst, micro_popc, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4945 break;
4946 case TGSI_OPCODE_LSB:
4947 exec_vector_unary(mach, inst, micro_lsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
4948 break;
4949 case TGSI_OPCODE_IMSB:
4950 exec_vector_unary(mach, inst, micro_imsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4951 break;
4952 case TGSI_OPCODE_UMSB:
4953 exec_vector_unary(mach, inst, micro_umsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
4954 break;
4955
4956 case TGSI_OPCODE_F2D:
4957 exec_f2d(mach, inst);
4958 break;
4959
4960 case TGSI_OPCODE_D2F:
4961 exec_d2f(mach, inst);
4962 break;
4963
4964 case TGSI_OPCODE_DABS:
4965 exec_double_unary(mach, inst, micro_dabs);
4966 break;
4967
4968 case TGSI_OPCODE_DNEG:
4969 exec_double_unary(mach, inst, micro_dneg);
4970 break;
4971
4972 case TGSI_OPCODE_DADD:
4973 exec_double_binary(mach, inst, micro_dadd, TGSI_EXEC_DATA_DOUBLE);
4974 break;
4975
4976 case TGSI_OPCODE_DMUL:
4977 exec_double_binary(mach, inst, micro_dmul, TGSI_EXEC_DATA_DOUBLE);
4978 break;
4979
4980 case TGSI_OPCODE_DMAX:
4981 exec_double_binary(mach, inst, micro_dmax, TGSI_EXEC_DATA_DOUBLE);
4982 break;
4983
4984 case TGSI_OPCODE_DMIN:
4985 exec_double_binary(mach, inst, micro_dmin, TGSI_EXEC_DATA_DOUBLE);
4986 break;
4987
4988 case TGSI_OPCODE_DSLT:
4989 exec_double_binary(mach, inst, micro_dslt, TGSI_EXEC_DATA_UINT);
4990 break;
4991
4992 case TGSI_OPCODE_DSGE:
4993 exec_double_binary(mach, inst, micro_dsge, TGSI_EXEC_DATA_UINT);
4994 break;
4995
4996 case TGSI_OPCODE_DSEQ:
4997 exec_double_binary(mach, inst, micro_dseq, TGSI_EXEC_DATA_UINT);
4998 break;
4999
5000 case TGSI_OPCODE_DSNE:
5001 exec_double_binary(mach, inst, micro_dsne, TGSI_EXEC_DATA_UINT);
5002 break;
5003
5004 case TGSI_OPCODE_DRCP:
5005 exec_double_unary(mach, inst, micro_drcp);
5006 break;
5007
5008 case TGSI_OPCODE_DSQRT:
5009 exec_double_unary(mach, inst, micro_dsqrt);
5010 break;
5011
5012 case TGSI_OPCODE_DRSQ:
5013 exec_double_unary(mach, inst, micro_drsq);
5014 break;
5015
5016 case TGSI_OPCODE_DMAD:
5017 exec_double_trinary(mach, inst, micro_dmad);
5018 break;
5019
5020 case TGSI_OPCODE_DFRAC:
5021 exec_double_unary(mach, inst, micro_dfrac);
5022 break;
5023
5024 case TGSI_OPCODE_DLDEXP:
5025 exec_dldexp(mach, inst);
5026 break;
5027
5028 case TGSI_OPCODE_DFRACEXP:
5029 exec_dfracexp(mach, inst);
5030 break;
5031
5032 case TGSI_OPCODE_I2D:
5033 exec_i2d(mach, inst);
5034 break;
5035
5036 case TGSI_OPCODE_D2I:
5037 exec_d2i(mach, inst);
5038 break;
5039
5040 case TGSI_OPCODE_U2D:
5041 exec_u2d(mach, inst);
5042 break;
5043
5044 case TGSI_OPCODE_D2U:
5045 exec_d2u(mach, inst);
5046 break;
5047 default:
5048 assert( 0 );
5049 }
5050 }
5051
5052
5053 /**
5054 * Run TGSI interpreter.
5055 * \return bitmask of "alive" quad components
5056 */
5057 uint
5058 tgsi_exec_machine_run( struct tgsi_exec_machine *mach )
5059 {
5060 uint i;
5061 int pc = 0;
5062 uint default_mask = 0xf;
5063
5064 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
5065 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
5066
5067 if( mach->Processor == TGSI_PROCESSOR_GEOMETRY ) {
5068 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
5069 mach->Primitives[0] = 0;
5070 /* GS runs on a single primitive for now */
5071 default_mask = 0x1;
5072 }
5073
5074 mach->CondMask = default_mask;
5075 mach->LoopMask = default_mask;
5076 mach->ContMask = default_mask;
5077 mach->FuncMask = default_mask;
5078 mach->ExecMask = default_mask;
5079
5080 mach->Switch.mask = default_mask;
5081
5082 assert(mach->CondStackTop == 0);
5083 assert(mach->LoopStackTop == 0);
5084 assert(mach->ContStackTop == 0);
5085 assert(mach->SwitchStackTop == 0);
5086 assert(mach->BreakStackTop == 0);
5087 assert(mach->CallStackTop == 0);
5088
5089
5090 /* execute declarations (interpolants) */
5091 for (i = 0; i < mach->NumDeclarations; i++) {
5092 exec_declaration( mach, mach->Declarations+i );
5093 }
5094
5095 {
5096 #if DEBUG_EXECUTION
5097 struct tgsi_exec_vector temps[TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS];
5098 struct tgsi_exec_vector outputs[PIPE_MAX_ATTRIBS];
5099 uint inst = 1;
5100
5101 memset(mach->Temps, 0, sizeof(temps));
5102 memset(mach->Outputs, 0, sizeof(outputs));
5103 memset(temps, 0, sizeof(temps));
5104 memset(outputs, 0, sizeof(outputs));
5105 #endif
5106
5107 /* execute instructions, until pc is set to -1 */
5108 while (pc != -1) {
5109
5110 #if DEBUG_EXECUTION
5111 uint i;
5112
5113 tgsi_dump_instruction(&mach->Instructions[pc], inst++);
5114 #endif
5115
5116 assert(pc < (int) mach->NumInstructions);
5117 exec_instruction(mach, mach->Instructions + pc, &pc);
5118
5119 #if DEBUG_EXECUTION
5120 for (i = 0; i < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS; i++) {
5121 if (memcmp(&temps[i], &mach->Temps[i], sizeof(temps[i]))) {
5122 uint j;
5123
5124 memcpy(&temps[i], &mach->Temps[i], sizeof(temps[i]));
5125 debug_printf("TEMP[%2u] = ", i);
5126 for (j = 0; j < 4; j++) {
5127 if (j > 0) {
5128 debug_printf(" ");
5129 }
5130 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
5131 temps[i].xyzw[0].f[j], temps[i].xyzw[0].u[j],
5132 temps[i].xyzw[1].f[j], temps[i].xyzw[1].u[j],
5133 temps[i].xyzw[2].f[j], temps[i].xyzw[2].u[j],
5134 temps[i].xyzw[3].f[j], temps[i].xyzw[3].u[j]);
5135 }
5136 }
5137 }
5138 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
5139 if (memcmp(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]))) {
5140 uint j;
5141
5142 memcpy(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]));
5143 debug_printf("OUT[%2u] = ", i);
5144 for (j = 0; j < 4; j++) {
5145 if (j > 0) {
5146 debug_printf(" ");
5147 }
5148 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
5149 outputs[i].xyzw[0].f[j], outputs[i].xyzw[0].u[j],
5150 outputs[i].xyzw[1].f[j], outputs[i].xyzw[1].u[j],
5151 outputs[i].xyzw[2].f[j], outputs[i].xyzw[2].u[j],
5152 outputs[i].xyzw[3].f[j], outputs[i].xyzw[3].u[j]);
5153 }
5154 }
5155 }
5156 #endif
5157 }
5158 }
5159
5160 #if 0
5161 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
5162 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
5163 /*
5164 * Scale back depth component.
5165 */
5166 for (i = 0; i < 4; i++)
5167 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
5168 }
5169 #endif
5170
5171 /* Strictly speaking, these assertions aren't really needed but they
5172 * can potentially catch some bugs in the control flow code.
5173 */
5174 assert(mach->CondStackTop == 0);
5175 assert(mach->LoopStackTop == 0);
5176 assert(mach->ContStackTop == 0);
5177 assert(mach->SwitchStackTop == 0);
5178 assert(mach->BreakStackTop == 0);
5179 assert(mach->CallStackTop == 0);
5180
5181 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
5182 }