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tgsi: add support for image operations to tgsi_exec. (v2.1)
[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 VMware, Inc.
4 * All Rights Reserved.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
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24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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27 **************************************************************************/
28
29 /**
30 * TGSI interpreter/executor.
31 *
32 * Flow control information:
33 *
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
38 *
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
42 * See store_dest().
43 *
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
47 *
48 *
49 * Authors:
50 * Michal Krol
51 * Brian Paul
52 */
53
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_half.h"
62 #include "util/u_memory.h"
63 #include "util/u_math.h"
64
65
66 #define DEBUG_EXECUTION 0
67
68
69 #define FAST_MATH 0
70
71 #define TILE_TOP_LEFT 0
72 #define TILE_TOP_RIGHT 1
73 #define TILE_BOTTOM_LEFT 2
74 #define TILE_BOTTOM_RIGHT 3
75
76 union tgsi_double_channel {
77 double d[TGSI_QUAD_SIZE];
78 unsigned u[TGSI_QUAD_SIZE][2];
79 };
80
81 struct tgsi_double_vector {
82 union tgsi_double_channel xy;
83 union tgsi_double_channel zw;
84 };
85
86 static void
87 micro_abs(union tgsi_exec_channel *dst,
88 const union tgsi_exec_channel *src)
89 {
90 dst->f[0] = fabsf(src->f[0]);
91 dst->f[1] = fabsf(src->f[1]);
92 dst->f[2] = fabsf(src->f[2]);
93 dst->f[3] = fabsf(src->f[3]);
94 }
95
96 static void
97 micro_arl(union tgsi_exec_channel *dst,
98 const union tgsi_exec_channel *src)
99 {
100 dst->i[0] = (int)floorf(src->f[0]);
101 dst->i[1] = (int)floorf(src->f[1]);
102 dst->i[2] = (int)floorf(src->f[2]);
103 dst->i[3] = (int)floorf(src->f[3]);
104 }
105
106 static void
107 micro_arr(union tgsi_exec_channel *dst,
108 const union tgsi_exec_channel *src)
109 {
110 dst->i[0] = (int)floorf(src->f[0] + 0.5f);
111 dst->i[1] = (int)floorf(src->f[1] + 0.5f);
112 dst->i[2] = (int)floorf(src->f[2] + 0.5f);
113 dst->i[3] = (int)floorf(src->f[3] + 0.5f);
114 }
115
116 static void
117 micro_ceil(union tgsi_exec_channel *dst,
118 const union tgsi_exec_channel *src)
119 {
120 dst->f[0] = ceilf(src->f[0]);
121 dst->f[1] = ceilf(src->f[1]);
122 dst->f[2] = ceilf(src->f[2]);
123 dst->f[3] = ceilf(src->f[3]);
124 }
125
126 static void
127 micro_clamp(union tgsi_exec_channel *dst,
128 const union tgsi_exec_channel *src0,
129 const union tgsi_exec_channel *src1,
130 const union tgsi_exec_channel *src2)
131 {
132 dst->f[0] = src0->f[0] < src1->f[0] ? src1->f[0] : src0->f[0] > src2->f[0] ? src2->f[0] : src0->f[0];
133 dst->f[1] = src0->f[1] < src1->f[1] ? src1->f[1] : src0->f[1] > src2->f[1] ? src2->f[1] : src0->f[1];
134 dst->f[2] = src0->f[2] < src1->f[2] ? src1->f[2] : src0->f[2] > src2->f[2] ? src2->f[2] : src0->f[2];
135 dst->f[3] = src0->f[3] < src1->f[3] ? src1->f[3] : src0->f[3] > src2->f[3] ? src2->f[3] : src0->f[3];
136 }
137
138 static void
139 micro_cmp(union tgsi_exec_channel *dst,
140 const union tgsi_exec_channel *src0,
141 const union tgsi_exec_channel *src1,
142 const union tgsi_exec_channel *src2)
143 {
144 dst->f[0] = src0->f[0] < 0.0f ? src1->f[0] : src2->f[0];
145 dst->f[1] = src0->f[1] < 0.0f ? src1->f[1] : src2->f[1];
146 dst->f[2] = src0->f[2] < 0.0f ? src1->f[2] : src2->f[2];
147 dst->f[3] = src0->f[3] < 0.0f ? src1->f[3] : src2->f[3];
148 }
149
150 static void
151 micro_cos(union tgsi_exec_channel *dst,
152 const union tgsi_exec_channel *src)
153 {
154 dst->f[0] = cosf(src->f[0]);
155 dst->f[1] = cosf(src->f[1]);
156 dst->f[2] = cosf(src->f[2]);
157 dst->f[3] = cosf(src->f[3]);
158 }
159
160 static void
161 micro_d2f(union tgsi_exec_channel *dst,
162 const union tgsi_double_channel *src)
163 {
164 dst->f[0] = (float)src->d[0];
165 dst->f[1] = (float)src->d[1];
166 dst->f[2] = (float)src->d[2];
167 dst->f[3] = (float)src->d[3];
168 }
169
170 static void
171 micro_d2i(union tgsi_exec_channel *dst,
172 const union tgsi_double_channel *src)
173 {
174 dst->i[0] = (int)src->d[0];
175 dst->i[1] = (int)src->d[1];
176 dst->i[2] = (int)src->d[2];
177 dst->i[3] = (int)src->d[3];
178 }
179
180 static void
181 micro_d2u(union tgsi_exec_channel *dst,
182 const union tgsi_double_channel *src)
183 {
184 dst->u[0] = (unsigned)src->d[0];
185 dst->u[1] = (unsigned)src->d[1];
186 dst->u[2] = (unsigned)src->d[2];
187 dst->u[3] = (unsigned)src->d[3];
188 }
189 static void
190 micro_dabs(union tgsi_double_channel *dst,
191 const union tgsi_double_channel *src)
192 {
193 dst->d[0] = src->d[0] >= 0.0 ? src->d[0] : -src->d[0];
194 dst->d[1] = src->d[1] >= 0.0 ? src->d[1] : -src->d[1];
195 dst->d[2] = src->d[2] >= 0.0 ? src->d[2] : -src->d[2];
196 dst->d[3] = src->d[3] >= 0.0 ? src->d[3] : -src->d[3];
197 }
198
199 static void
200 micro_dadd(union tgsi_double_channel *dst,
201 const union tgsi_double_channel *src)
202 {
203 dst->d[0] = src[0].d[0] + src[1].d[0];
204 dst->d[1] = src[0].d[1] + src[1].d[1];
205 dst->d[2] = src[0].d[2] + src[1].d[2];
206 dst->d[3] = src[0].d[3] + src[1].d[3];
207 }
208
209 static void
210 micro_ddx(union tgsi_exec_channel *dst,
211 const union tgsi_exec_channel *src)
212 {
213 dst->f[0] =
214 dst->f[1] =
215 dst->f[2] =
216 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
217 }
218
219 static void
220 micro_ddy(union tgsi_exec_channel *dst,
221 const union tgsi_exec_channel *src)
222 {
223 dst->f[0] =
224 dst->f[1] =
225 dst->f[2] =
226 dst->f[3] = src->f[TILE_BOTTOM_LEFT] - src->f[TILE_TOP_LEFT];
227 }
228
229 static void
230 micro_dmul(union tgsi_double_channel *dst,
231 const union tgsi_double_channel *src)
232 {
233 dst->d[0] = src[0].d[0] * src[1].d[0];
234 dst->d[1] = src[0].d[1] * src[1].d[1];
235 dst->d[2] = src[0].d[2] * src[1].d[2];
236 dst->d[3] = src[0].d[3] * src[1].d[3];
237 }
238
239 static void
240 micro_dmax(union tgsi_double_channel *dst,
241 const union tgsi_double_channel *src)
242 {
243 dst->d[0] = src[0].d[0] > src[1].d[0] ? src[0].d[0] : src[1].d[0];
244 dst->d[1] = src[0].d[1] > src[1].d[1] ? src[0].d[1] : src[1].d[1];
245 dst->d[2] = src[0].d[2] > src[1].d[2] ? src[0].d[2] : src[1].d[2];
246 dst->d[3] = src[0].d[3] > src[1].d[3] ? src[0].d[3] : src[1].d[3];
247 }
248
249 static void
250 micro_dmin(union tgsi_double_channel *dst,
251 const union tgsi_double_channel *src)
252 {
253 dst->d[0] = src[0].d[0] < src[1].d[0] ? src[0].d[0] : src[1].d[0];
254 dst->d[1] = src[0].d[1] < src[1].d[1] ? src[0].d[1] : src[1].d[1];
255 dst->d[2] = src[0].d[2] < src[1].d[2] ? src[0].d[2] : src[1].d[2];
256 dst->d[3] = src[0].d[3] < src[1].d[3] ? src[0].d[3] : src[1].d[3];
257 }
258
259 static void
260 micro_dneg(union tgsi_double_channel *dst,
261 const union tgsi_double_channel *src)
262 {
263 dst->d[0] = -src->d[0];
264 dst->d[1] = -src->d[1];
265 dst->d[2] = -src->d[2];
266 dst->d[3] = -src->d[3];
267 }
268
269 static void
270 micro_dslt(union tgsi_double_channel *dst,
271 const union tgsi_double_channel *src)
272 {
273 dst->u[0][0] = src[0].d[0] < src[1].d[0] ? ~0U : 0U;
274 dst->u[1][0] = src[0].d[1] < src[1].d[1] ? ~0U : 0U;
275 dst->u[2][0] = src[0].d[2] < src[1].d[2] ? ~0U : 0U;
276 dst->u[3][0] = src[0].d[3] < src[1].d[3] ? ~0U : 0U;
277 }
278
279 static void
280 micro_dsne(union tgsi_double_channel *dst,
281 const union tgsi_double_channel *src)
282 {
283 dst->u[0][0] = src[0].d[0] != src[1].d[0] ? ~0U : 0U;
284 dst->u[1][0] = src[0].d[1] != src[1].d[1] ? ~0U : 0U;
285 dst->u[2][0] = src[0].d[2] != src[1].d[2] ? ~0U : 0U;
286 dst->u[3][0] = src[0].d[3] != src[1].d[3] ? ~0U : 0U;
287 }
288
289 static void
290 micro_dsge(union tgsi_double_channel *dst,
291 const union tgsi_double_channel *src)
292 {
293 dst->u[0][0] = src[0].d[0] >= src[1].d[0] ? ~0U : 0U;
294 dst->u[1][0] = src[0].d[1] >= src[1].d[1] ? ~0U : 0U;
295 dst->u[2][0] = src[0].d[2] >= src[1].d[2] ? ~0U : 0U;
296 dst->u[3][0] = src[0].d[3] >= src[1].d[3] ? ~0U : 0U;
297 }
298
299 static void
300 micro_dseq(union tgsi_double_channel *dst,
301 const union tgsi_double_channel *src)
302 {
303 dst->u[0][0] = src[0].d[0] == src[1].d[0] ? ~0U : 0U;
304 dst->u[1][0] = src[0].d[1] == src[1].d[1] ? ~0U : 0U;
305 dst->u[2][0] = src[0].d[2] == src[1].d[2] ? ~0U : 0U;
306 dst->u[3][0] = src[0].d[3] == src[1].d[3] ? ~0U : 0U;
307 }
308
309 static void
310 micro_drcp(union tgsi_double_channel *dst,
311 const union tgsi_double_channel *src)
312 {
313 dst->d[0] = 1.0 / src->d[0];
314 dst->d[1] = 1.0 / src->d[1];
315 dst->d[2] = 1.0 / src->d[2];
316 dst->d[3] = 1.0 / src->d[3];
317 }
318
319 static void
320 micro_dsqrt(union tgsi_double_channel *dst,
321 const union tgsi_double_channel *src)
322 {
323 dst->d[0] = sqrt(src->d[0]);
324 dst->d[1] = sqrt(src->d[1]);
325 dst->d[2] = sqrt(src->d[2]);
326 dst->d[3] = sqrt(src->d[3]);
327 }
328
329 static void
330 micro_drsq(union tgsi_double_channel *dst,
331 const union tgsi_double_channel *src)
332 {
333 dst->d[0] = 1.0 / sqrt(src->d[0]);
334 dst->d[1] = 1.0 / sqrt(src->d[1]);
335 dst->d[2] = 1.0 / sqrt(src->d[2]);
336 dst->d[3] = 1.0 / sqrt(src->d[3]);
337 }
338
339 static void
340 micro_dmad(union tgsi_double_channel *dst,
341 const union tgsi_double_channel *src)
342 {
343 dst->d[0] = src[0].d[0] * src[1].d[0] + src[2].d[0];
344 dst->d[1] = src[0].d[1] * src[1].d[1] + src[2].d[1];
345 dst->d[2] = src[0].d[2] * src[1].d[2] + src[2].d[2];
346 dst->d[3] = src[0].d[3] * src[1].d[3] + src[2].d[3];
347 }
348
349 static void
350 micro_dfrac(union tgsi_double_channel *dst,
351 const union tgsi_double_channel *src)
352 {
353 dst->d[0] = src->d[0] - floor(src->d[0]);
354 dst->d[1] = src->d[1] - floor(src->d[1]);
355 dst->d[2] = src->d[2] - floor(src->d[2]);
356 dst->d[3] = src->d[3] - floor(src->d[3]);
357 }
358
359 static void
360 micro_dldexp(union tgsi_double_channel *dst,
361 const union tgsi_double_channel *src0,
362 union tgsi_exec_channel *src1)
363 {
364 dst->d[0] = ldexp(src0->d[0], src1->i[0]);
365 dst->d[1] = ldexp(src0->d[1], src1->i[1]);
366 dst->d[2] = ldexp(src0->d[2], src1->i[2]);
367 dst->d[3] = ldexp(src0->d[3], src1->i[3]);
368 }
369
370 static void
371 micro_dfracexp(union tgsi_double_channel *dst,
372 union tgsi_exec_channel *dst_exp,
373 const union tgsi_double_channel *src)
374 {
375 dst->d[0] = frexp(src->d[0], &dst_exp->i[0]);
376 dst->d[1] = frexp(src->d[1], &dst_exp->i[1]);
377 dst->d[2] = frexp(src->d[2], &dst_exp->i[2]);
378 dst->d[3] = frexp(src->d[3], &dst_exp->i[3]);
379 }
380
381 static void
382 micro_exp2(union tgsi_exec_channel *dst,
383 const union tgsi_exec_channel *src)
384 {
385 #if FAST_MATH
386 dst->f[0] = util_fast_exp2(src->f[0]);
387 dst->f[1] = util_fast_exp2(src->f[1]);
388 dst->f[2] = util_fast_exp2(src->f[2]);
389 dst->f[3] = util_fast_exp2(src->f[3]);
390 #else
391 #if DEBUG
392 /* Inf is okay for this instruction, so clamp it to silence assertions. */
393 uint i;
394 union tgsi_exec_channel clamped;
395
396 for (i = 0; i < 4; i++) {
397 if (src->f[i] > 127.99999f) {
398 clamped.f[i] = 127.99999f;
399 } else if (src->f[i] < -126.99999f) {
400 clamped.f[i] = -126.99999f;
401 } else {
402 clamped.f[i] = src->f[i];
403 }
404 }
405 src = &clamped;
406 #endif /* DEBUG */
407
408 dst->f[0] = powf(2.0f, src->f[0]);
409 dst->f[1] = powf(2.0f, src->f[1]);
410 dst->f[2] = powf(2.0f, src->f[2]);
411 dst->f[3] = powf(2.0f, src->f[3]);
412 #endif /* FAST_MATH */
413 }
414
415 static void
416 micro_f2d(union tgsi_double_channel *dst,
417 const union tgsi_exec_channel *src)
418 {
419 dst->d[0] = (double)src->f[0];
420 dst->d[1] = (double)src->f[1];
421 dst->d[2] = (double)src->f[2];
422 dst->d[3] = (double)src->f[3];
423 }
424
425 static void
426 micro_flr(union tgsi_exec_channel *dst,
427 const union tgsi_exec_channel *src)
428 {
429 dst->f[0] = floorf(src->f[0]);
430 dst->f[1] = floorf(src->f[1]);
431 dst->f[2] = floorf(src->f[2]);
432 dst->f[3] = floorf(src->f[3]);
433 }
434
435 static void
436 micro_frc(union tgsi_exec_channel *dst,
437 const union tgsi_exec_channel *src)
438 {
439 dst->f[0] = src->f[0] - floorf(src->f[0]);
440 dst->f[1] = src->f[1] - floorf(src->f[1]);
441 dst->f[2] = src->f[2] - floorf(src->f[2]);
442 dst->f[3] = src->f[3] - floorf(src->f[3]);
443 }
444
445 static void
446 micro_i2d(union tgsi_double_channel *dst,
447 const union tgsi_exec_channel *src)
448 {
449 dst->d[0] = (double)src->i[0];
450 dst->d[1] = (double)src->i[1];
451 dst->d[2] = (double)src->i[2];
452 dst->d[3] = (double)src->i[3];
453 }
454
455 static void
456 micro_iabs(union tgsi_exec_channel *dst,
457 const union tgsi_exec_channel *src)
458 {
459 dst->i[0] = src->i[0] >= 0 ? src->i[0] : -src->i[0];
460 dst->i[1] = src->i[1] >= 0 ? src->i[1] : -src->i[1];
461 dst->i[2] = src->i[2] >= 0 ? src->i[2] : -src->i[2];
462 dst->i[3] = src->i[3] >= 0 ? src->i[3] : -src->i[3];
463 }
464
465 static void
466 micro_ineg(union tgsi_exec_channel *dst,
467 const union tgsi_exec_channel *src)
468 {
469 dst->i[0] = -src->i[0];
470 dst->i[1] = -src->i[1];
471 dst->i[2] = -src->i[2];
472 dst->i[3] = -src->i[3];
473 }
474
475 static void
476 micro_lg2(union tgsi_exec_channel *dst,
477 const union tgsi_exec_channel *src)
478 {
479 #if FAST_MATH
480 dst->f[0] = util_fast_log2(src->f[0]);
481 dst->f[1] = util_fast_log2(src->f[1]);
482 dst->f[2] = util_fast_log2(src->f[2]);
483 dst->f[3] = util_fast_log2(src->f[3]);
484 #else
485 dst->f[0] = logf(src->f[0]) * 1.442695f;
486 dst->f[1] = logf(src->f[1]) * 1.442695f;
487 dst->f[2] = logf(src->f[2]) * 1.442695f;
488 dst->f[3] = logf(src->f[3]) * 1.442695f;
489 #endif
490 }
491
492 static void
493 micro_lrp(union tgsi_exec_channel *dst,
494 const union tgsi_exec_channel *src0,
495 const union tgsi_exec_channel *src1,
496 const union tgsi_exec_channel *src2)
497 {
498 dst->f[0] = src0->f[0] * (src1->f[0] - src2->f[0]) + src2->f[0];
499 dst->f[1] = src0->f[1] * (src1->f[1] - src2->f[1]) + src2->f[1];
500 dst->f[2] = src0->f[2] * (src1->f[2] - src2->f[2]) + src2->f[2];
501 dst->f[3] = src0->f[3] * (src1->f[3] - src2->f[3]) + src2->f[3];
502 }
503
504 static void
505 micro_mad(union tgsi_exec_channel *dst,
506 const union tgsi_exec_channel *src0,
507 const union tgsi_exec_channel *src1,
508 const union tgsi_exec_channel *src2)
509 {
510 dst->f[0] = src0->f[0] * src1->f[0] + src2->f[0];
511 dst->f[1] = src0->f[1] * src1->f[1] + src2->f[1];
512 dst->f[2] = src0->f[2] * src1->f[2] + src2->f[2];
513 dst->f[3] = src0->f[3] * src1->f[3] + src2->f[3];
514 }
515
516 static void
517 micro_mov(union tgsi_exec_channel *dst,
518 const union tgsi_exec_channel *src)
519 {
520 dst->u[0] = src->u[0];
521 dst->u[1] = src->u[1];
522 dst->u[2] = src->u[2];
523 dst->u[3] = src->u[3];
524 }
525
526 static void
527 micro_rcp(union tgsi_exec_channel *dst,
528 const union tgsi_exec_channel *src)
529 {
530 #if 0 /* for debugging */
531 assert(src->f[0] != 0.0f);
532 assert(src->f[1] != 0.0f);
533 assert(src->f[2] != 0.0f);
534 assert(src->f[3] != 0.0f);
535 #endif
536 dst->f[0] = 1.0f / src->f[0];
537 dst->f[1] = 1.0f / src->f[1];
538 dst->f[2] = 1.0f / src->f[2];
539 dst->f[3] = 1.0f / src->f[3];
540 }
541
542 static void
543 micro_rnd(union tgsi_exec_channel *dst,
544 const union tgsi_exec_channel *src)
545 {
546 dst->f[0] = floorf(src->f[0] + 0.5f);
547 dst->f[1] = floorf(src->f[1] + 0.5f);
548 dst->f[2] = floorf(src->f[2] + 0.5f);
549 dst->f[3] = floorf(src->f[3] + 0.5f);
550 }
551
552 static void
553 micro_rsq(union tgsi_exec_channel *dst,
554 const union tgsi_exec_channel *src)
555 {
556 #if 0 /* for debugging */
557 assert(src->f[0] != 0.0f);
558 assert(src->f[1] != 0.0f);
559 assert(src->f[2] != 0.0f);
560 assert(src->f[3] != 0.0f);
561 #endif
562 dst->f[0] = 1.0f / sqrtf(src->f[0]);
563 dst->f[1] = 1.0f / sqrtf(src->f[1]);
564 dst->f[2] = 1.0f / sqrtf(src->f[2]);
565 dst->f[3] = 1.0f / sqrtf(src->f[3]);
566 }
567
568 static void
569 micro_sqrt(union tgsi_exec_channel *dst,
570 const union tgsi_exec_channel *src)
571 {
572 dst->f[0] = sqrtf(src->f[0]);
573 dst->f[1] = sqrtf(src->f[1]);
574 dst->f[2] = sqrtf(src->f[2]);
575 dst->f[3] = sqrtf(src->f[3]);
576 }
577
578 static void
579 micro_seq(union tgsi_exec_channel *dst,
580 const union tgsi_exec_channel *src0,
581 const union tgsi_exec_channel *src1)
582 {
583 dst->f[0] = src0->f[0] == src1->f[0] ? 1.0f : 0.0f;
584 dst->f[1] = src0->f[1] == src1->f[1] ? 1.0f : 0.0f;
585 dst->f[2] = src0->f[2] == src1->f[2] ? 1.0f : 0.0f;
586 dst->f[3] = src0->f[3] == src1->f[3] ? 1.0f : 0.0f;
587 }
588
589 static void
590 micro_sge(union tgsi_exec_channel *dst,
591 const union tgsi_exec_channel *src0,
592 const union tgsi_exec_channel *src1)
593 {
594 dst->f[0] = src0->f[0] >= src1->f[0] ? 1.0f : 0.0f;
595 dst->f[1] = src0->f[1] >= src1->f[1] ? 1.0f : 0.0f;
596 dst->f[2] = src0->f[2] >= src1->f[2] ? 1.0f : 0.0f;
597 dst->f[3] = src0->f[3] >= src1->f[3] ? 1.0f : 0.0f;
598 }
599
600 static void
601 micro_sgn(union tgsi_exec_channel *dst,
602 const union tgsi_exec_channel *src)
603 {
604 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
605 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
606 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
607 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
608 }
609
610 static void
611 micro_isgn(union tgsi_exec_channel *dst,
612 const union tgsi_exec_channel *src)
613 {
614 dst->i[0] = src->i[0] < 0 ? -1 : src->i[0] > 0 ? 1 : 0;
615 dst->i[1] = src->i[1] < 0 ? -1 : src->i[1] > 0 ? 1 : 0;
616 dst->i[2] = src->i[2] < 0 ? -1 : src->i[2] > 0 ? 1 : 0;
617 dst->i[3] = src->i[3] < 0 ? -1 : src->i[3] > 0 ? 1 : 0;
618 }
619
620 static void
621 micro_sgt(union tgsi_exec_channel *dst,
622 const union tgsi_exec_channel *src0,
623 const union tgsi_exec_channel *src1)
624 {
625 dst->f[0] = src0->f[0] > src1->f[0] ? 1.0f : 0.0f;
626 dst->f[1] = src0->f[1] > src1->f[1] ? 1.0f : 0.0f;
627 dst->f[2] = src0->f[2] > src1->f[2] ? 1.0f : 0.0f;
628 dst->f[3] = src0->f[3] > src1->f[3] ? 1.0f : 0.0f;
629 }
630
631 static void
632 micro_sin(union tgsi_exec_channel *dst,
633 const union tgsi_exec_channel *src)
634 {
635 dst->f[0] = sinf(src->f[0]);
636 dst->f[1] = sinf(src->f[1]);
637 dst->f[2] = sinf(src->f[2]);
638 dst->f[3] = sinf(src->f[3]);
639 }
640
641 static void
642 micro_sle(union tgsi_exec_channel *dst,
643 const union tgsi_exec_channel *src0,
644 const union tgsi_exec_channel *src1)
645 {
646 dst->f[0] = src0->f[0] <= src1->f[0] ? 1.0f : 0.0f;
647 dst->f[1] = src0->f[1] <= src1->f[1] ? 1.0f : 0.0f;
648 dst->f[2] = src0->f[2] <= src1->f[2] ? 1.0f : 0.0f;
649 dst->f[3] = src0->f[3] <= src1->f[3] ? 1.0f : 0.0f;
650 }
651
652 static void
653 micro_slt(union tgsi_exec_channel *dst,
654 const union tgsi_exec_channel *src0,
655 const union tgsi_exec_channel *src1)
656 {
657 dst->f[0] = src0->f[0] < src1->f[0] ? 1.0f : 0.0f;
658 dst->f[1] = src0->f[1] < src1->f[1] ? 1.0f : 0.0f;
659 dst->f[2] = src0->f[2] < src1->f[2] ? 1.0f : 0.0f;
660 dst->f[3] = src0->f[3] < src1->f[3] ? 1.0f : 0.0f;
661 }
662
663 static void
664 micro_sne(union tgsi_exec_channel *dst,
665 const union tgsi_exec_channel *src0,
666 const union tgsi_exec_channel *src1)
667 {
668 dst->f[0] = src0->f[0] != src1->f[0] ? 1.0f : 0.0f;
669 dst->f[1] = src0->f[1] != src1->f[1] ? 1.0f : 0.0f;
670 dst->f[2] = src0->f[2] != src1->f[2] ? 1.0f : 0.0f;
671 dst->f[3] = src0->f[3] != src1->f[3] ? 1.0f : 0.0f;
672 }
673
674 static void
675 micro_trunc(union tgsi_exec_channel *dst,
676 const union tgsi_exec_channel *src)
677 {
678 dst->f[0] = (float)(int)src->f[0];
679 dst->f[1] = (float)(int)src->f[1];
680 dst->f[2] = (float)(int)src->f[2];
681 dst->f[3] = (float)(int)src->f[3];
682 }
683
684 static void
685 micro_u2d(union tgsi_double_channel *dst,
686 const union tgsi_exec_channel *src)
687 {
688 dst->d[0] = (double)src->u[0];
689 dst->d[1] = (double)src->u[1];
690 dst->d[2] = (double)src->u[2];
691 dst->d[3] = (double)src->u[3];
692 }
693
694 enum tgsi_exec_datatype {
695 TGSI_EXEC_DATA_FLOAT,
696 TGSI_EXEC_DATA_INT,
697 TGSI_EXEC_DATA_UINT,
698 TGSI_EXEC_DATA_DOUBLE
699 };
700
701 /*
702 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
703 */
704 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
705 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
706 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
707 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
708 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
709 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
710
711
712 /** The execution mask depends on the conditional mask and the loop mask */
713 #define UPDATE_EXEC_MASK(MACH) \
714 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
715
716
717 static const union tgsi_exec_channel ZeroVec =
718 { { 0.0, 0.0, 0.0, 0.0 } };
719
720 static const union tgsi_exec_channel OneVec = {
721 {1.0f, 1.0f, 1.0f, 1.0f}
722 };
723
724 static const union tgsi_exec_channel P128Vec = {
725 {128.0f, 128.0f, 128.0f, 128.0f}
726 };
727
728 static const union tgsi_exec_channel M128Vec = {
729 {-128.0f, -128.0f, -128.0f, -128.0f}
730 };
731
732
733 /**
734 * Assert that none of the float values in 'chan' are infinite or NaN.
735 * NaN and Inf may occur normally during program execution and should
736 * not lead to crashes, etc. But when debugging, it's helpful to catch
737 * them.
738 */
739 static inline void
740 check_inf_or_nan(const union tgsi_exec_channel *chan)
741 {
742 assert(!util_is_inf_or_nan((chan)->f[0]));
743 assert(!util_is_inf_or_nan((chan)->f[1]));
744 assert(!util_is_inf_or_nan((chan)->f[2]));
745 assert(!util_is_inf_or_nan((chan)->f[3]));
746 }
747
748
749 #ifdef DEBUG
750 static void
751 print_chan(const char *msg, const union tgsi_exec_channel *chan)
752 {
753 debug_printf("%s = {%f, %f, %f, %f}\n",
754 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
755 }
756 #endif
757
758
759 #ifdef DEBUG
760 static void
761 print_temp(const struct tgsi_exec_machine *mach, uint index)
762 {
763 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
764 int i;
765 debug_printf("Temp[%u] =\n", index);
766 for (i = 0; i < 4; i++) {
767 debug_printf(" %c: { %f, %f, %f, %f }\n",
768 "XYZW"[i],
769 tmp->xyzw[i].f[0],
770 tmp->xyzw[i].f[1],
771 tmp->xyzw[i].f[2],
772 tmp->xyzw[i].f[3]);
773 }
774 }
775 #endif
776
777
778 void
779 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine *mach,
780 unsigned num_bufs,
781 const void **bufs,
782 const unsigned *buf_sizes)
783 {
784 unsigned i;
785
786 for (i = 0; i < num_bufs; i++) {
787 mach->Consts[i] = bufs[i];
788 mach->ConstsSize[i] = buf_sizes[i];
789 }
790 }
791
792
793 /**
794 * Check if there's a potential src/dst register data dependency when
795 * using SOA execution.
796 * Example:
797 * MOV T, T.yxwz;
798 * This would expand into:
799 * MOV t0, t1;
800 * MOV t1, t0;
801 * MOV t2, t3;
802 * MOV t3, t2;
803 * The second instruction will have the wrong value for t0 if executed as-is.
804 */
805 boolean
806 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
807 {
808 uint i, chan;
809
810 uint writemask = inst->Dst[0].Register.WriteMask;
811 if (writemask == TGSI_WRITEMASK_X ||
812 writemask == TGSI_WRITEMASK_Y ||
813 writemask == TGSI_WRITEMASK_Z ||
814 writemask == TGSI_WRITEMASK_W ||
815 writemask == TGSI_WRITEMASK_NONE) {
816 /* no chance of data dependency */
817 return FALSE;
818 }
819
820 /* loop over src regs */
821 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
822 if ((inst->Src[i].Register.File ==
823 inst->Dst[0].Register.File) &&
824 ((inst->Src[i].Register.Index ==
825 inst->Dst[0].Register.Index) ||
826 inst->Src[i].Register.Indirect ||
827 inst->Dst[0].Register.Indirect)) {
828 /* loop over dest channels */
829 uint channelsWritten = 0x0;
830 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
831 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
832 /* check if we're reading a channel that's been written */
833 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
834 if (channelsWritten & (1 << swizzle)) {
835 return TRUE;
836 }
837
838 channelsWritten |= (1 << chan);
839 }
840 }
841 }
842 }
843 return FALSE;
844 }
845
846
847 /**
848 * Initialize machine state by expanding tokens to full instructions,
849 * allocating temporary storage, setting up constants, etc.
850 * After this, we can call tgsi_exec_machine_run() many times.
851 */
852 void
853 tgsi_exec_machine_bind_shader(
854 struct tgsi_exec_machine *mach,
855 const struct tgsi_token *tokens,
856 struct tgsi_sampler *sampler,
857 struct tgsi_image *image)
858 {
859 uint k;
860 struct tgsi_parse_context parse;
861 struct tgsi_full_instruction *instructions;
862 struct tgsi_full_declaration *declarations;
863 uint maxInstructions = 10, numInstructions = 0;
864 uint maxDeclarations = 10, numDeclarations = 0;
865
866 #if 0
867 tgsi_dump(tokens, 0);
868 #endif
869
870 util_init_math();
871
872
873 mach->Tokens = tokens;
874 mach->Sampler = sampler;
875 mach->Image = image;
876
877 if (!tokens) {
878 /* unbind and free all */
879 FREE(mach->Declarations);
880 mach->Declarations = NULL;
881 mach->NumDeclarations = 0;
882
883 FREE(mach->Instructions);
884 mach->Instructions = NULL;
885 mach->NumInstructions = 0;
886
887 return;
888 }
889
890 k = tgsi_parse_init (&parse, mach->Tokens);
891 if (k != TGSI_PARSE_OK) {
892 debug_printf( "Problem parsing!\n" );
893 return;
894 }
895
896 mach->Processor = parse.FullHeader.Processor.Processor;
897 mach->ImmLimit = 0;
898 mach->NumOutputs = 0;
899
900 if (mach->Processor == TGSI_PROCESSOR_GEOMETRY &&
901 !mach->UsedGeometryShader) {
902 struct tgsi_exec_vector *inputs;
903 struct tgsi_exec_vector *outputs;
904
905 inputs = align_malloc(sizeof(struct tgsi_exec_vector) *
906 TGSI_MAX_PRIM_VERTICES * PIPE_MAX_SHADER_INPUTS,
907 16);
908
909 if (!inputs)
910 return;
911
912 outputs = align_malloc(sizeof(struct tgsi_exec_vector) *
913 TGSI_MAX_TOTAL_VERTICES, 16);
914
915 if (!outputs) {
916 align_free(inputs);
917 return;
918 }
919
920 align_free(mach->Inputs);
921 align_free(mach->Outputs);
922
923 mach->Inputs = inputs;
924 mach->Outputs = outputs;
925 mach->UsedGeometryShader = TRUE;
926 }
927
928 declarations = (struct tgsi_full_declaration *)
929 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
930
931 if (!declarations) {
932 return;
933 }
934
935 instructions = (struct tgsi_full_instruction *)
936 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
937
938 if (!instructions) {
939 FREE( declarations );
940 return;
941 }
942
943 while( !tgsi_parse_end_of_tokens( &parse ) ) {
944 uint i;
945
946 tgsi_parse_token( &parse );
947 switch( parse.FullToken.Token.Type ) {
948 case TGSI_TOKEN_TYPE_DECLARATION:
949 /* save expanded declaration */
950 if (numDeclarations == maxDeclarations) {
951 declarations = REALLOC(declarations,
952 maxDeclarations
953 * sizeof(struct tgsi_full_declaration),
954 (maxDeclarations + 10)
955 * sizeof(struct tgsi_full_declaration));
956 maxDeclarations += 10;
957 }
958 if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_OUTPUT) {
959 unsigned reg;
960 for (reg = parse.FullToken.FullDeclaration.Range.First;
961 reg <= parse.FullToken.FullDeclaration.Range.Last;
962 ++reg) {
963 ++mach->NumOutputs;
964 }
965 }
966 memcpy(declarations + numDeclarations,
967 &parse.FullToken.FullDeclaration,
968 sizeof(declarations[0]));
969 numDeclarations++;
970 break;
971
972 case TGSI_TOKEN_TYPE_IMMEDIATE:
973 {
974 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
975 assert( size <= 4 );
976 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
977
978 for( i = 0; i < size; i++ ) {
979 mach->Imms[mach->ImmLimit][i] =
980 parse.FullToken.FullImmediate.u[i].Float;
981 }
982 mach->ImmLimit += 1;
983 }
984 break;
985
986 case TGSI_TOKEN_TYPE_INSTRUCTION:
987
988 /* save expanded instruction */
989 if (numInstructions == maxInstructions) {
990 instructions = REALLOC(instructions,
991 maxInstructions
992 * sizeof(struct tgsi_full_instruction),
993 (maxInstructions + 10)
994 * sizeof(struct tgsi_full_instruction));
995 maxInstructions += 10;
996 }
997
998 memcpy(instructions + numInstructions,
999 &parse.FullToken.FullInstruction,
1000 sizeof(instructions[0]));
1001
1002 numInstructions++;
1003 break;
1004
1005 case TGSI_TOKEN_TYPE_PROPERTY:
1006 if (mach->Processor == TGSI_PROCESSOR_GEOMETRY) {
1007 if (parse.FullToken.FullProperty.Property.PropertyName == TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES) {
1008 mach->MaxOutputVertices = parse.FullToken.FullProperty.u[0].Data;
1009 }
1010 }
1011 break;
1012
1013 default:
1014 assert( 0 );
1015 }
1016 }
1017 tgsi_parse_free (&parse);
1018
1019 FREE(mach->Declarations);
1020 mach->Declarations = declarations;
1021 mach->NumDeclarations = numDeclarations;
1022
1023 FREE(mach->Instructions);
1024 mach->Instructions = instructions;
1025 mach->NumInstructions = numInstructions;
1026 }
1027
1028
1029 struct tgsi_exec_machine *
1030 tgsi_exec_machine_create( void )
1031 {
1032 struct tgsi_exec_machine *mach;
1033 uint i;
1034
1035 mach = align_malloc( sizeof *mach, 16 );
1036 if (!mach)
1037 goto fail;
1038
1039 memset(mach, 0, sizeof(*mach));
1040
1041 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
1042 mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
1043 mach->Predicates = &mach->Temps[TGSI_EXEC_TEMP_P0];
1044
1045 mach->Inputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_INPUTS, 16);
1046 mach->Outputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_OUTPUTS, 16);
1047 if (!mach->Inputs || !mach->Outputs)
1048 goto fail;
1049
1050 /* Setup constants needed by the SSE2 executor. */
1051 for( i = 0; i < 4; i++ ) {
1052 mach->Temps[TGSI_EXEC_TEMP_00000000_I].xyzw[TGSI_EXEC_TEMP_00000000_C].u[i] = 0x00000000;
1053 mach->Temps[TGSI_EXEC_TEMP_7FFFFFFF_I].xyzw[TGSI_EXEC_TEMP_7FFFFFFF_C].u[i] = 0x7FFFFFFF;
1054 mach->Temps[TGSI_EXEC_TEMP_80000000_I].xyzw[TGSI_EXEC_TEMP_80000000_C].u[i] = 0x80000000;
1055 mach->Temps[TGSI_EXEC_TEMP_FFFFFFFF_I].xyzw[TGSI_EXEC_TEMP_FFFFFFFF_C].u[i] = 0xFFFFFFFF; /* not used */
1056 mach->Temps[TGSI_EXEC_TEMP_ONE_I].xyzw[TGSI_EXEC_TEMP_ONE_C].f[i] = 1.0f;
1057 mach->Temps[TGSI_EXEC_TEMP_TWO_I].xyzw[TGSI_EXEC_TEMP_TWO_C].f[i] = 2.0f; /* not used */
1058 mach->Temps[TGSI_EXEC_TEMP_128_I].xyzw[TGSI_EXEC_TEMP_128_C].f[i] = 128.0f;
1059 mach->Temps[TGSI_EXEC_TEMP_MINUS_128_I].xyzw[TGSI_EXEC_TEMP_MINUS_128_C].f[i] = -128.0f;
1060 mach->Temps[TGSI_EXEC_TEMP_THREE_I].xyzw[TGSI_EXEC_TEMP_THREE_C].f[i] = 3.0f;
1061 mach->Temps[TGSI_EXEC_TEMP_HALF_I].xyzw[TGSI_EXEC_TEMP_HALF_C].f[i] = 0.5f;
1062 }
1063
1064 #ifdef DEBUG
1065 /* silence warnings */
1066 (void) print_chan;
1067 (void) print_temp;
1068 #endif
1069
1070 return mach;
1071
1072 fail:
1073 if (mach) {
1074 align_free(mach->Inputs);
1075 align_free(mach->Outputs);
1076 align_free(mach);
1077 }
1078 return NULL;
1079 }
1080
1081
1082 void
1083 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
1084 {
1085 if (mach) {
1086 FREE(mach->Instructions);
1087 FREE(mach->Declarations);
1088
1089 align_free(mach->Inputs);
1090 align_free(mach->Outputs);
1091
1092 align_free(mach);
1093 }
1094 }
1095
1096 static void
1097 micro_add(union tgsi_exec_channel *dst,
1098 const union tgsi_exec_channel *src0,
1099 const union tgsi_exec_channel *src1)
1100 {
1101 dst->f[0] = src0->f[0] + src1->f[0];
1102 dst->f[1] = src0->f[1] + src1->f[1];
1103 dst->f[2] = src0->f[2] + src1->f[2];
1104 dst->f[3] = src0->f[3] + src1->f[3];
1105 }
1106
1107 static void
1108 micro_div(
1109 union tgsi_exec_channel *dst,
1110 const union tgsi_exec_channel *src0,
1111 const union tgsi_exec_channel *src1 )
1112 {
1113 if (src1->f[0] != 0) {
1114 dst->f[0] = src0->f[0] / src1->f[0];
1115 }
1116 if (src1->f[1] != 0) {
1117 dst->f[1] = src0->f[1] / src1->f[1];
1118 }
1119 if (src1->f[2] != 0) {
1120 dst->f[2] = src0->f[2] / src1->f[2];
1121 }
1122 if (src1->f[3] != 0) {
1123 dst->f[3] = src0->f[3] / src1->f[3];
1124 }
1125 }
1126
1127 static void
1128 micro_lt(
1129 union tgsi_exec_channel *dst,
1130 const union tgsi_exec_channel *src0,
1131 const union tgsi_exec_channel *src1,
1132 const union tgsi_exec_channel *src2,
1133 const union tgsi_exec_channel *src3 )
1134 {
1135 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
1136 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
1137 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
1138 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
1139 }
1140
1141 static void
1142 micro_max(union tgsi_exec_channel *dst,
1143 const union tgsi_exec_channel *src0,
1144 const union tgsi_exec_channel *src1)
1145 {
1146 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
1147 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
1148 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
1149 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
1150 }
1151
1152 static void
1153 micro_min(union tgsi_exec_channel *dst,
1154 const union tgsi_exec_channel *src0,
1155 const union tgsi_exec_channel *src1)
1156 {
1157 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
1158 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
1159 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
1160 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
1161 }
1162
1163 static void
1164 micro_mul(union tgsi_exec_channel *dst,
1165 const union tgsi_exec_channel *src0,
1166 const union tgsi_exec_channel *src1)
1167 {
1168 dst->f[0] = src0->f[0] * src1->f[0];
1169 dst->f[1] = src0->f[1] * src1->f[1];
1170 dst->f[2] = src0->f[2] * src1->f[2];
1171 dst->f[3] = src0->f[3] * src1->f[3];
1172 }
1173
1174 static void
1175 micro_neg(
1176 union tgsi_exec_channel *dst,
1177 const union tgsi_exec_channel *src )
1178 {
1179 dst->f[0] = -src->f[0];
1180 dst->f[1] = -src->f[1];
1181 dst->f[2] = -src->f[2];
1182 dst->f[3] = -src->f[3];
1183 }
1184
1185 static void
1186 micro_pow(
1187 union tgsi_exec_channel *dst,
1188 const union tgsi_exec_channel *src0,
1189 const union tgsi_exec_channel *src1 )
1190 {
1191 #if FAST_MATH
1192 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
1193 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
1194 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
1195 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
1196 #else
1197 dst->f[0] = powf( src0->f[0], src1->f[0] );
1198 dst->f[1] = powf( src0->f[1], src1->f[1] );
1199 dst->f[2] = powf( src0->f[2], src1->f[2] );
1200 dst->f[3] = powf( src0->f[3], src1->f[3] );
1201 #endif
1202 }
1203
1204 static void
1205 micro_sub(union tgsi_exec_channel *dst,
1206 const union tgsi_exec_channel *src0,
1207 const union tgsi_exec_channel *src1)
1208 {
1209 dst->f[0] = src0->f[0] - src1->f[0];
1210 dst->f[1] = src0->f[1] - src1->f[1];
1211 dst->f[2] = src0->f[2] - src1->f[2];
1212 dst->f[3] = src0->f[3] - src1->f[3];
1213 }
1214
1215 static void
1216 fetch_src_file_channel(const struct tgsi_exec_machine *mach,
1217 const uint chan_index,
1218 const uint file,
1219 const uint swizzle,
1220 const union tgsi_exec_channel *index,
1221 const union tgsi_exec_channel *index2D,
1222 union tgsi_exec_channel *chan)
1223 {
1224 uint i;
1225
1226 assert(swizzle < 4);
1227
1228 switch (file) {
1229 case TGSI_FILE_CONSTANT:
1230 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1231 assert(index2D->i[i] >= 0 && index2D->i[i] < PIPE_MAX_CONSTANT_BUFFERS);
1232 assert(mach->Consts[index2D->i[i]]);
1233
1234 if (index->i[i] < 0) {
1235 chan->u[i] = 0;
1236 } else {
1237 /* NOTE: copying the const value as a uint instead of float */
1238 const uint constbuf = index2D->i[i];
1239 const uint *buf = (const uint *)mach->Consts[constbuf];
1240 const int pos = index->i[i] * 4 + swizzle;
1241 /* const buffer bounds check */
1242 if (pos < 0 || pos >= (int) mach->ConstsSize[constbuf]) {
1243 if (0) {
1244 /* Debug: print warning */
1245 static int count = 0;
1246 if (count++ < 100)
1247 debug_printf("TGSI Exec: const buffer index %d"
1248 " out of bounds\n", pos);
1249 }
1250 chan->u[i] = 0;
1251 }
1252 else
1253 chan->u[i] = buf[pos];
1254 }
1255 }
1256 break;
1257
1258 case TGSI_FILE_INPUT:
1259 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1260 /*
1261 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1262 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1263 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1264 index2D->i[i], index->i[i]);
1265 }*/
1266 int pos = index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i];
1267 assert(pos >= 0);
1268 assert(pos < TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS);
1269 chan->u[i] = mach->Inputs[pos].xyzw[swizzle].u[i];
1270 }
1271 break;
1272
1273 case TGSI_FILE_SYSTEM_VALUE:
1274 /* XXX no swizzling at this point. Will be needed if we put
1275 * gl_FragCoord, for example, in a sys value register.
1276 */
1277 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1278 chan->u[i] = mach->SystemValue[index->i[i]].u[i];
1279 }
1280 break;
1281
1282 case TGSI_FILE_TEMPORARY:
1283 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1284 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1285 assert(index2D->i[i] == 0);
1286
1287 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1288 }
1289 break;
1290
1291 case TGSI_FILE_IMMEDIATE:
1292 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1293 assert(index->i[i] >= 0 && index->i[i] < (int)mach->ImmLimit);
1294 assert(index2D->i[i] == 0);
1295
1296 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1297 }
1298 break;
1299
1300 case TGSI_FILE_ADDRESS:
1301 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1302 assert(index->i[i] >= 0);
1303 assert(index2D->i[i] == 0);
1304
1305 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1306 }
1307 break;
1308
1309 case TGSI_FILE_PREDICATE:
1310 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1311 assert(index->i[i] >= 0 && index->i[i] < TGSI_EXEC_NUM_PREDS);
1312 assert(index2D->i[i] == 0);
1313
1314 chan->u[i] = mach->Predicates[0].xyzw[swizzle].u[i];
1315 }
1316 break;
1317
1318 case TGSI_FILE_OUTPUT:
1319 /* vertex/fragment output vars can be read too */
1320 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1321 assert(index->i[i] >= 0);
1322 assert(index2D->i[i] == 0);
1323
1324 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1325 }
1326 break;
1327
1328 default:
1329 assert(0);
1330 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1331 chan->u[i] = 0;
1332 }
1333 }
1334 }
1335
1336 static void
1337 fetch_source_d(const struct tgsi_exec_machine *mach,
1338 union tgsi_exec_channel *chan,
1339 const struct tgsi_full_src_register *reg,
1340 const uint chan_index,
1341 enum tgsi_exec_datatype src_datatype)
1342 {
1343 union tgsi_exec_channel index;
1344 union tgsi_exec_channel index2D;
1345 uint swizzle;
1346
1347 /* We start with a direct index into a register file.
1348 *
1349 * file[1],
1350 * where:
1351 * file = Register.File
1352 * [1] = Register.Index
1353 */
1354 index.i[0] =
1355 index.i[1] =
1356 index.i[2] =
1357 index.i[3] = reg->Register.Index;
1358
1359 /* There is an extra source register that indirectly subscripts
1360 * a register file. The direct index now becomes an offset
1361 * that is being added to the indirect register.
1362 *
1363 * file[ind[2].x+1],
1364 * where:
1365 * ind = Indirect.File
1366 * [2] = Indirect.Index
1367 * .x = Indirect.SwizzleX
1368 */
1369 if (reg->Register.Indirect) {
1370 union tgsi_exec_channel index2;
1371 union tgsi_exec_channel indir_index;
1372 const uint execmask = mach->ExecMask;
1373 uint i;
1374
1375 /* which address register (always zero now) */
1376 index2.i[0] =
1377 index2.i[1] =
1378 index2.i[2] =
1379 index2.i[3] = reg->Indirect.Index;
1380 /* get current value of address register[swizzle] */
1381 swizzle = reg->Indirect.Swizzle;
1382 fetch_src_file_channel(mach,
1383 chan_index,
1384 reg->Indirect.File,
1385 swizzle,
1386 &index2,
1387 &ZeroVec,
1388 &indir_index);
1389
1390 /* add value of address register to the offset */
1391 index.i[0] += indir_index.i[0];
1392 index.i[1] += indir_index.i[1];
1393 index.i[2] += indir_index.i[2];
1394 index.i[3] += indir_index.i[3];
1395
1396 /* for disabled execution channels, zero-out the index to
1397 * avoid using a potential garbage value.
1398 */
1399 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1400 if ((execmask & (1 << i)) == 0)
1401 index.i[i] = 0;
1402 }
1403 }
1404
1405 /* There is an extra source register that is a second
1406 * subscript to a register file. Effectively it means that
1407 * the register file is actually a 2D array of registers.
1408 *
1409 * file[3][1],
1410 * where:
1411 * [3] = Dimension.Index
1412 */
1413 if (reg->Register.Dimension) {
1414 index2D.i[0] =
1415 index2D.i[1] =
1416 index2D.i[2] =
1417 index2D.i[3] = reg->Dimension.Index;
1418
1419 /* Again, the second subscript index can be addressed indirectly
1420 * identically to the first one.
1421 * Nothing stops us from indirectly addressing the indirect register,
1422 * but there is no need for that, so we won't exercise it.
1423 *
1424 * file[ind[4].y+3][1],
1425 * where:
1426 * ind = DimIndirect.File
1427 * [4] = DimIndirect.Index
1428 * .y = DimIndirect.SwizzleX
1429 */
1430 if (reg->Dimension.Indirect) {
1431 union tgsi_exec_channel index2;
1432 union tgsi_exec_channel indir_index;
1433 const uint execmask = mach->ExecMask;
1434 uint i;
1435
1436 index2.i[0] =
1437 index2.i[1] =
1438 index2.i[2] =
1439 index2.i[3] = reg->DimIndirect.Index;
1440
1441 swizzle = reg->DimIndirect.Swizzle;
1442 fetch_src_file_channel(mach,
1443 chan_index,
1444 reg->DimIndirect.File,
1445 swizzle,
1446 &index2,
1447 &ZeroVec,
1448 &indir_index);
1449
1450 index2D.i[0] += indir_index.i[0];
1451 index2D.i[1] += indir_index.i[1];
1452 index2D.i[2] += indir_index.i[2];
1453 index2D.i[3] += indir_index.i[3];
1454
1455 /* for disabled execution channels, zero-out the index to
1456 * avoid using a potential garbage value.
1457 */
1458 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1459 if ((execmask & (1 << i)) == 0) {
1460 index2D.i[i] = 0;
1461 }
1462 }
1463 }
1464
1465 /* If by any chance there was a need for a 3D array of register
1466 * files, we would have to check whether Dimension is followed
1467 * by a dimension register and continue the saga.
1468 */
1469 } else {
1470 index2D.i[0] =
1471 index2D.i[1] =
1472 index2D.i[2] =
1473 index2D.i[3] = 0;
1474 }
1475
1476 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1477 fetch_src_file_channel(mach,
1478 chan_index,
1479 reg->Register.File,
1480 swizzle,
1481 &index,
1482 &index2D,
1483 chan);
1484 }
1485
1486 static void
1487 fetch_source(const struct tgsi_exec_machine *mach,
1488 union tgsi_exec_channel *chan,
1489 const struct tgsi_full_src_register *reg,
1490 const uint chan_index,
1491 enum tgsi_exec_datatype src_datatype)
1492 {
1493 fetch_source_d(mach, chan, reg, chan_index, src_datatype);
1494
1495 if (reg->Register.Absolute) {
1496 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1497 micro_abs(chan, chan);
1498 } else {
1499 micro_iabs(chan, chan);
1500 }
1501 }
1502
1503 if (reg->Register.Negate) {
1504 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1505 micro_neg(chan, chan);
1506 } else {
1507 micro_ineg(chan, chan);
1508 }
1509 }
1510 }
1511
1512 static union tgsi_exec_channel *
1513 store_dest_dstret(struct tgsi_exec_machine *mach,
1514 const union tgsi_exec_channel *chan,
1515 const struct tgsi_full_dst_register *reg,
1516 const struct tgsi_full_instruction *inst,
1517 uint chan_index,
1518 enum tgsi_exec_datatype dst_datatype)
1519 {
1520 uint i;
1521 static union tgsi_exec_channel null;
1522 union tgsi_exec_channel *dst;
1523 union tgsi_exec_channel index2D;
1524 uint execmask = mach->ExecMask;
1525 int offset = 0; /* indirection offset */
1526 int index;
1527
1528 /* for debugging */
1529 if (0 && dst_datatype == TGSI_EXEC_DATA_FLOAT) {
1530 check_inf_or_nan(chan);
1531 }
1532
1533 /* There is an extra source register that indirectly subscripts
1534 * a register file. The direct index now becomes an offset
1535 * that is being added to the indirect register.
1536 *
1537 * file[ind[2].x+1],
1538 * where:
1539 * ind = Indirect.File
1540 * [2] = Indirect.Index
1541 * .x = Indirect.SwizzleX
1542 */
1543 if (reg->Register.Indirect) {
1544 union tgsi_exec_channel index;
1545 union tgsi_exec_channel indir_index;
1546 uint swizzle;
1547
1548 /* which address register (always zero for now) */
1549 index.i[0] =
1550 index.i[1] =
1551 index.i[2] =
1552 index.i[3] = reg->Indirect.Index;
1553
1554 /* get current value of address register[swizzle] */
1555 swizzle = reg->Indirect.Swizzle;
1556
1557 /* fetch values from the address/indirection register */
1558 fetch_src_file_channel(mach,
1559 chan_index,
1560 reg->Indirect.File,
1561 swizzle,
1562 &index,
1563 &ZeroVec,
1564 &indir_index);
1565
1566 /* save indirection offset */
1567 offset = indir_index.i[0];
1568 }
1569
1570 /* There is an extra source register that is a second
1571 * subscript to a register file. Effectively it means that
1572 * the register file is actually a 2D array of registers.
1573 *
1574 * file[3][1],
1575 * where:
1576 * [3] = Dimension.Index
1577 */
1578 if (reg->Register.Dimension) {
1579 index2D.i[0] =
1580 index2D.i[1] =
1581 index2D.i[2] =
1582 index2D.i[3] = reg->Dimension.Index;
1583
1584 /* Again, the second subscript index can be addressed indirectly
1585 * identically to the first one.
1586 * Nothing stops us from indirectly addressing the indirect register,
1587 * but there is no need for that, so we won't exercise it.
1588 *
1589 * file[ind[4].y+3][1],
1590 * where:
1591 * ind = DimIndirect.File
1592 * [4] = DimIndirect.Index
1593 * .y = DimIndirect.SwizzleX
1594 */
1595 if (reg->Dimension.Indirect) {
1596 union tgsi_exec_channel index2;
1597 union tgsi_exec_channel indir_index;
1598 const uint execmask = mach->ExecMask;
1599 unsigned swizzle;
1600 uint i;
1601
1602 index2.i[0] =
1603 index2.i[1] =
1604 index2.i[2] =
1605 index2.i[3] = reg->DimIndirect.Index;
1606
1607 swizzle = reg->DimIndirect.Swizzle;
1608 fetch_src_file_channel(mach,
1609 chan_index,
1610 reg->DimIndirect.File,
1611 swizzle,
1612 &index2,
1613 &ZeroVec,
1614 &indir_index);
1615
1616 index2D.i[0] += indir_index.i[0];
1617 index2D.i[1] += indir_index.i[1];
1618 index2D.i[2] += indir_index.i[2];
1619 index2D.i[3] += indir_index.i[3];
1620
1621 /* for disabled execution channels, zero-out the index to
1622 * avoid using a potential garbage value.
1623 */
1624 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1625 if ((execmask & (1 << i)) == 0) {
1626 index2D.i[i] = 0;
1627 }
1628 }
1629 }
1630
1631 /* If by any chance there was a need for a 3D array of register
1632 * files, we would have to check whether Dimension is followed
1633 * by a dimension register and continue the saga.
1634 */
1635 } else {
1636 index2D.i[0] =
1637 index2D.i[1] =
1638 index2D.i[2] =
1639 index2D.i[3] = 0;
1640 }
1641
1642 switch (reg->Register.File) {
1643 case TGSI_FILE_NULL:
1644 dst = &null;
1645 break;
1646
1647 case TGSI_FILE_OUTPUT:
1648 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1649 + reg->Register.Index;
1650 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1651 #if 0
1652 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1653 mach->NumOutputs, mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0],
1654 reg->Register.Index);
1655 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1656 debug_printf("STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1657 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1658 if (execmask & (1 << i))
1659 debug_printf("%f, ", chan->f[i]);
1660 debug_printf(")\n");
1661 }
1662 #endif
1663 break;
1664
1665 case TGSI_FILE_TEMPORARY:
1666 index = reg->Register.Index;
1667 assert( index < TGSI_EXEC_NUM_TEMPS );
1668 dst = &mach->Temps[offset + index].xyzw[chan_index];
1669 break;
1670
1671 case TGSI_FILE_ADDRESS:
1672 index = reg->Register.Index;
1673 dst = &mach->Addrs[index].xyzw[chan_index];
1674 break;
1675
1676 case TGSI_FILE_PREDICATE:
1677 index = reg->Register.Index;
1678 assert(index < TGSI_EXEC_NUM_PREDS);
1679 dst = &mach->Predicates[index].xyzw[chan_index];
1680 break;
1681
1682 default:
1683 assert( 0 );
1684 return NULL;
1685 }
1686
1687 if (inst->Instruction.Predicate) {
1688 uint swizzle;
1689 union tgsi_exec_channel *pred;
1690
1691 switch (chan_index) {
1692 case TGSI_CHAN_X:
1693 swizzle = inst->Predicate.SwizzleX;
1694 break;
1695 case TGSI_CHAN_Y:
1696 swizzle = inst->Predicate.SwizzleY;
1697 break;
1698 case TGSI_CHAN_Z:
1699 swizzle = inst->Predicate.SwizzleZ;
1700 break;
1701 case TGSI_CHAN_W:
1702 swizzle = inst->Predicate.SwizzleW;
1703 break;
1704 default:
1705 assert(0);
1706 return NULL;
1707 }
1708
1709 assert(inst->Predicate.Index == 0);
1710
1711 pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
1712
1713 if (inst->Predicate.Negate) {
1714 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1715 if (pred->u[i]) {
1716 execmask &= ~(1 << i);
1717 }
1718 }
1719 } else {
1720 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1721 if (!pred->u[i]) {
1722 execmask &= ~(1 << i);
1723 }
1724 }
1725 }
1726 }
1727
1728 return dst;
1729 }
1730
1731 static void
1732 store_dest_double(struct tgsi_exec_machine *mach,
1733 const union tgsi_exec_channel *chan,
1734 const struct tgsi_full_dst_register *reg,
1735 const struct tgsi_full_instruction *inst,
1736 uint chan_index,
1737 enum tgsi_exec_datatype dst_datatype)
1738 {
1739 union tgsi_exec_channel *dst;
1740 const uint execmask = mach->ExecMask;
1741 int i;
1742
1743 dst = store_dest_dstret(mach, chan, reg, inst, chan_index,
1744 dst_datatype);
1745 if (!dst)
1746 return;
1747
1748 /* doubles path */
1749 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1750 if (execmask & (1 << i))
1751 dst->i[i] = chan->i[i];
1752 }
1753
1754 static void
1755 store_dest(struct tgsi_exec_machine *mach,
1756 const union tgsi_exec_channel *chan,
1757 const struct tgsi_full_dst_register *reg,
1758 const struct tgsi_full_instruction *inst,
1759 uint chan_index,
1760 enum tgsi_exec_datatype dst_datatype)
1761 {
1762 union tgsi_exec_channel *dst;
1763 const uint execmask = mach->ExecMask;
1764 int i;
1765
1766 dst = store_dest_dstret(mach, chan, reg, inst, chan_index,
1767 dst_datatype);
1768 if (!dst)
1769 return;
1770
1771 if (!inst->Instruction.Saturate) {
1772 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1773 if (execmask & (1 << i))
1774 dst->i[i] = chan->i[i];
1775 }
1776 else {
1777 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1778 if (execmask & (1 << i)) {
1779 if (chan->f[i] < 0.0f)
1780 dst->f[i] = 0.0f;
1781 else if (chan->f[i] > 1.0f)
1782 dst->f[i] = 1.0f;
1783 else
1784 dst->i[i] = chan->i[i];
1785 }
1786 }
1787 }
1788
1789 #define FETCH(VAL,INDEX,CHAN)\
1790 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1791
1792 #define IFETCH(VAL,INDEX,CHAN)\
1793 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1794
1795
1796 /**
1797 * Execute ARB-style KIL which is predicated by a src register.
1798 * Kill fragment if any of the four values is less than zero.
1799 */
1800 static void
1801 exec_kill_if(struct tgsi_exec_machine *mach,
1802 const struct tgsi_full_instruction *inst)
1803 {
1804 uint uniquemask;
1805 uint chan_index;
1806 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1807 union tgsi_exec_channel r[1];
1808
1809 /* This mask stores component bits that were already tested. */
1810 uniquemask = 0;
1811
1812 for (chan_index = 0; chan_index < 4; chan_index++)
1813 {
1814 uint swizzle;
1815 uint i;
1816
1817 /* unswizzle channel */
1818 swizzle = tgsi_util_get_full_src_register_swizzle (
1819 &inst->Src[0],
1820 chan_index);
1821
1822 /* check if the component has not been already tested */
1823 if (uniquemask & (1 << swizzle))
1824 continue;
1825 uniquemask |= 1 << swizzle;
1826
1827 FETCH(&r[0], 0, chan_index);
1828 for (i = 0; i < 4; i++)
1829 if (r[0].f[i] < 0.0f)
1830 kilmask |= 1 << i;
1831 }
1832
1833 /* restrict to fragments currently executing */
1834 kilmask &= mach->ExecMask;
1835
1836 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1837 }
1838
1839 /**
1840 * Unconditional fragment kill/discard.
1841 */
1842 static void
1843 exec_kill(struct tgsi_exec_machine *mach,
1844 const struct tgsi_full_instruction *inst)
1845 {
1846 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1847
1848 /* kill fragment for all fragments currently executing */
1849 kilmask = mach->ExecMask;
1850 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1851 }
1852
1853 static void
1854 emit_vertex(struct tgsi_exec_machine *mach)
1855 {
1856 /* FIXME: check for exec mask correctly
1857 unsigned i;
1858 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1859 if ((mach->ExecMask & (1 << i)))
1860 */
1861 if (mach->ExecMask) {
1862 if (mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]] >= mach->MaxOutputVertices)
1863 return;
1864
1865 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += mach->NumOutputs;
1866 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
1867 }
1868 }
1869
1870 static void
1871 emit_primitive(struct tgsi_exec_machine *mach)
1872 {
1873 unsigned *prim_count = &mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0];
1874 /* FIXME: check for exec mask correctly
1875 unsigned i;
1876 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1877 if ((mach->ExecMask & (1 << i)))
1878 */
1879 if (mach->ExecMask) {
1880 ++(*prim_count);
1881 debug_assert((*prim_count * mach->NumOutputs) < mach->MaxGeometryShaderOutputs);
1882 mach->Primitives[*prim_count] = 0;
1883 }
1884 }
1885
1886 static void
1887 conditional_emit_primitive(struct tgsi_exec_machine *mach)
1888 {
1889 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1890 int emitted_verts =
1891 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]];
1892 if (emitted_verts) {
1893 emit_primitive(mach);
1894 }
1895 }
1896 }
1897
1898
1899 /*
1900 * Fetch four texture samples using STR texture coordinates.
1901 */
1902 static void
1903 fetch_texel( struct tgsi_sampler *sampler,
1904 const unsigned sview_idx,
1905 const unsigned sampler_idx,
1906 const union tgsi_exec_channel *s,
1907 const union tgsi_exec_channel *t,
1908 const union tgsi_exec_channel *p,
1909 const union tgsi_exec_channel *c0,
1910 const union tgsi_exec_channel *c1,
1911 float derivs[3][2][TGSI_QUAD_SIZE],
1912 const int8_t offset[3],
1913 enum tgsi_sampler_control control,
1914 union tgsi_exec_channel *r,
1915 union tgsi_exec_channel *g,
1916 union tgsi_exec_channel *b,
1917 union tgsi_exec_channel *a )
1918 {
1919 uint j;
1920 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
1921
1922 /* FIXME: handle explicit derivs, offsets */
1923 sampler->get_samples(sampler, sview_idx, sampler_idx,
1924 s->f, t->f, p->f, c0->f, c1->f, derivs, offset, control, rgba);
1925
1926 for (j = 0; j < 4; j++) {
1927 r->f[j] = rgba[0][j];
1928 g->f[j] = rgba[1][j];
1929 b->f[j] = rgba[2][j];
1930 a->f[j] = rgba[3][j];
1931 }
1932 }
1933
1934
1935 #define TEX_MODIFIER_NONE 0
1936 #define TEX_MODIFIER_PROJECTED 1
1937 #define TEX_MODIFIER_LOD_BIAS 2
1938 #define TEX_MODIFIER_EXPLICIT_LOD 3
1939 #define TEX_MODIFIER_LEVEL_ZERO 4
1940 #define TEX_MODIFIER_GATHER 5
1941
1942 /*
1943 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
1944 */
1945 static void
1946 fetch_texel_offsets(struct tgsi_exec_machine *mach,
1947 const struct tgsi_full_instruction *inst,
1948 int8_t offsets[3])
1949 {
1950 if (inst->Texture.NumOffsets == 1) {
1951 union tgsi_exec_channel index;
1952 union tgsi_exec_channel offset[3];
1953 index.i[0] = index.i[1] = index.i[2] = index.i[3] = inst->TexOffsets[0].Index;
1954 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1955 inst->TexOffsets[0].SwizzleX, &index, &ZeroVec, &offset[0]);
1956 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1957 inst->TexOffsets[0].SwizzleY, &index, &ZeroVec, &offset[1]);
1958 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1959 inst->TexOffsets[0].SwizzleZ, &index, &ZeroVec, &offset[2]);
1960 offsets[0] = offset[0].i[0];
1961 offsets[1] = offset[1].i[0];
1962 offsets[2] = offset[2].i[0];
1963 } else {
1964 assert(inst->Texture.NumOffsets == 0);
1965 offsets[0] = offsets[1] = offsets[2] = 0;
1966 }
1967 }
1968
1969
1970 /*
1971 * Fetch dx and dy values for one channel (s, t or r).
1972 * Put dx values into one float array, dy values into another.
1973 */
1974 static void
1975 fetch_assign_deriv_channel(struct tgsi_exec_machine *mach,
1976 const struct tgsi_full_instruction *inst,
1977 unsigned regdsrcx,
1978 unsigned chan,
1979 float derivs[2][TGSI_QUAD_SIZE])
1980 {
1981 union tgsi_exec_channel d;
1982 FETCH(&d, regdsrcx, chan);
1983 derivs[0][0] = d.f[0];
1984 derivs[0][1] = d.f[1];
1985 derivs[0][2] = d.f[2];
1986 derivs[0][3] = d.f[3];
1987 FETCH(&d, regdsrcx + 1, chan);
1988 derivs[1][0] = d.f[0];
1989 derivs[1][1] = d.f[1];
1990 derivs[1][2] = d.f[2];
1991 derivs[1][3] = d.f[3];
1992 }
1993
1994 static uint
1995 fetch_sampler_unit(struct tgsi_exec_machine *mach,
1996 const struct tgsi_full_instruction *inst,
1997 uint sampler)
1998 {
1999 uint unit;
2000 int i;
2001 if (inst->Src[sampler].Register.Indirect) {
2002 const struct tgsi_full_src_register *reg = &inst->Src[sampler];
2003 union tgsi_exec_channel indir_index, index2;
2004 const uint execmask = mach->ExecMask;
2005 index2.i[0] =
2006 index2.i[1] =
2007 index2.i[2] =
2008 index2.i[3] = reg->Indirect.Index;
2009
2010 fetch_src_file_channel(mach,
2011 0,
2012 reg->Indirect.File,
2013 reg->Indirect.Swizzle,
2014 &index2,
2015 &ZeroVec,
2016 &indir_index);
2017 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2018 if (execmask & (1 << i)) {
2019 unit = inst->Src[sampler].Register.Index + indir_index.i[i];
2020 break;
2021 }
2022 }
2023
2024 } else {
2025 unit = inst->Src[sampler].Register.Index;
2026 }
2027 return unit;
2028 }
2029
2030 /*
2031 * execute a texture instruction.
2032 *
2033 * modifier is used to control the channel routing for the
2034 * instruction variants like proj, lod, and texture with lod bias.
2035 * sampler indicates which src register the sampler is contained in.
2036 */
2037 static void
2038 exec_tex(struct tgsi_exec_machine *mach,
2039 const struct tgsi_full_instruction *inst,
2040 uint modifier, uint sampler)
2041 {
2042 const union tgsi_exec_channel *args[5], *proj = NULL;
2043 union tgsi_exec_channel r[5];
2044 enum tgsi_sampler_control control = TGSI_SAMPLER_LOD_NONE;
2045 uint chan;
2046 uint unit;
2047 int8_t offsets[3];
2048 int dim, shadow_ref, i;
2049
2050 unit = fetch_sampler_unit(mach, inst, sampler);
2051 /* always fetch all 3 offsets, overkill but keeps code simple */
2052 fetch_texel_offsets(mach, inst, offsets);
2053
2054 assert(modifier != TEX_MODIFIER_LEVEL_ZERO);
2055 assert(inst->Texture.Texture != TGSI_TEXTURE_BUFFER);
2056
2057 dim = tgsi_util_get_texture_coord_dim(inst->Texture.Texture, &shadow_ref);
2058
2059 assert(dim <= 4);
2060 if (shadow_ref >= 0)
2061 assert(shadow_ref >= dim && shadow_ref < Elements(args));
2062
2063 /* fetch modifier to the last argument */
2064 if (modifier != TEX_MODIFIER_NONE) {
2065 const int last = Elements(args) - 1;
2066
2067 /* fetch modifier from src0.w or src1.x */
2068 if (sampler == 1) {
2069 assert(dim <= TGSI_CHAN_W && shadow_ref != TGSI_CHAN_W);
2070 FETCH(&r[last], 0, TGSI_CHAN_W);
2071 }
2072 else {
2073 assert(shadow_ref != 4);
2074 FETCH(&r[last], 1, TGSI_CHAN_X);
2075 }
2076
2077 if (modifier != TEX_MODIFIER_PROJECTED) {
2078 args[last] = &r[last];
2079 }
2080 else {
2081 proj = &r[last];
2082 args[last] = &ZeroVec;
2083 }
2084
2085 /* point unused arguments to zero vector */
2086 for (i = dim; i < last; i++)
2087 args[i] = &ZeroVec;
2088
2089 if (modifier == TEX_MODIFIER_EXPLICIT_LOD)
2090 control = TGSI_SAMPLER_LOD_EXPLICIT;
2091 else if (modifier == TEX_MODIFIER_LOD_BIAS)
2092 control = TGSI_SAMPLER_LOD_BIAS;
2093 else if (modifier == TEX_MODIFIER_GATHER)
2094 control = TGSI_SAMPLER_GATHER;
2095 }
2096 else {
2097 for (i = dim; i < Elements(args); i++)
2098 args[i] = &ZeroVec;
2099 }
2100
2101 /* fetch coordinates */
2102 for (i = 0; i < dim; i++) {
2103 FETCH(&r[i], 0, TGSI_CHAN_X + i);
2104
2105 if (proj)
2106 micro_div(&r[i], &r[i], proj);
2107
2108 args[i] = &r[i];
2109 }
2110
2111 /* fetch reference value */
2112 if (shadow_ref >= 0) {
2113 FETCH(&r[shadow_ref], shadow_ref / 4, TGSI_CHAN_X + (shadow_ref % 4));
2114
2115 if (proj)
2116 micro_div(&r[shadow_ref], &r[shadow_ref], proj);
2117
2118 args[shadow_ref] = &r[shadow_ref];
2119 }
2120
2121 fetch_texel(mach->Sampler, unit, unit,
2122 args[0], args[1], args[2], args[3], args[4],
2123 NULL, offsets, control,
2124 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2125
2126 #if 0
2127 debug_printf("fetch r: %g %g %g %g\n",
2128 r[0].f[0], r[0].f[1], r[0].f[2], r[0].f[3]);
2129 debug_printf("fetch g: %g %g %g %g\n",
2130 r[1].f[0], r[1].f[1], r[1].f[2], r[1].f[3]);
2131 debug_printf("fetch b: %g %g %g %g\n",
2132 r[2].f[0], r[2].f[1], r[2].f[2], r[2].f[3]);
2133 debug_printf("fetch a: %g %g %g %g\n",
2134 r[3].f[0], r[3].f[1], r[3].f[2], r[3].f[3]);
2135 #endif
2136
2137 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2138 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2139 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2140 }
2141 }
2142 }
2143
2144 static void
2145 exec_lodq(struct tgsi_exec_machine *mach,
2146 const struct tgsi_full_instruction *inst)
2147 {
2148 uint unit;
2149 int dim;
2150 int i;
2151 union tgsi_exec_channel coords[4];
2152 const union tgsi_exec_channel *args[Elements(coords)];
2153 union tgsi_exec_channel r[2];
2154
2155 unit = fetch_sampler_unit(mach, inst, 1);
2156 dim = tgsi_util_get_texture_coord_dim(inst->Texture.Texture, NULL);
2157 assert(dim <= Elements(coords));
2158 /* fetch coordinates */
2159 for (i = 0; i < dim; i++) {
2160 FETCH(&coords[i], 0, TGSI_CHAN_X + i);
2161 args[i] = &coords[i];
2162 }
2163 for (i = dim; i < Elements(coords); i++) {
2164 args[i] = &ZeroVec;
2165 }
2166 mach->Sampler->query_lod(mach->Sampler, unit, unit,
2167 args[0]->f,
2168 args[1]->f,
2169 args[2]->f,
2170 args[3]->f,
2171 TGSI_SAMPLER_LOD_NONE,
2172 r[0].f,
2173 r[1].f);
2174
2175 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2176 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_X,
2177 TGSI_EXEC_DATA_FLOAT);
2178 }
2179 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2180 store_dest(mach, &r[1], &inst->Dst[0], inst, TGSI_CHAN_Y,
2181 TGSI_EXEC_DATA_FLOAT);
2182 }
2183 }
2184
2185 static void
2186 exec_txd(struct tgsi_exec_machine *mach,
2187 const struct tgsi_full_instruction *inst)
2188 {
2189 union tgsi_exec_channel r[4];
2190 float derivs[3][2][TGSI_QUAD_SIZE];
2191 uint chan;
2192 uint unit;
2193 int8_t offsets[3];
2194
2195 unit = fetch_sampler_unit(mach, inst, 3);
2196 /* always fetch all 3 offsets, overkill but keeps code simple */
2197 fetch_texel_offsets(mach, inst, offsets);
2198
2199 switch (inst->Texture.Texture) {
2200 case TGSI_TEXTURE_1D:
2201 FETCH(&r[0], 0, TGSI_CHAN_X);
2202
2203 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2204
2205 fetch_texel(mach->Sampler, unit, unit,
2206 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2207 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2208 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2209 break;
2210
2211 case TGSI_TEXTURE_SHADOW1D:
2212 case TGSI_TEXTURE_1D_ARRAY:
2213 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2214 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
2215 FETCH(&r[0], 0, TGSI_CHAN_X);
2216 FETCH(&r[1], 0, TGSI_CHAN_Y);
2217 FETCH(&r[2], 0, TGSI_CHAN_Z);
2218
2219 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2220
2221 fetch_texel(mach->Sampler, unit, unit,
2222 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2223 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2224 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2225 break;
2226
2227 case TGSI_TEXTURE_2D:
2228 case TGSI_TEXTURE_RECT:
2229 FETCH(&r[0], 0, TGSI_CHAN_X);
2230 FETCH(&r[1], 0, TGSI_CHAN_Y);
2231
2232 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2233 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2234
2235 fetch_texel(mach->Sampler, unit, unit,
2236 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2237 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2238 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2239 break;
2240
2241
2242 case TGSI_TEXTURE_SHADOW2D:
2243 case TGSI_TEXTURE_SHADOWRECT:
2244 case TGSI_TEXTURE_2D_ARRAY:
2245 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2246 /* only SHADOW2D_ARRAY actually needs W */
2247 FETCH(&r[0], 0, TGSI_CHAN_X);
2248 FETCH(&r[1], 0, TGSI_CHAN_Y);
2249 FETCH(&r[2], 0, TGSI_CHAN_Z);
2250 FETCH(&r[3], 0, TGSI_CHAN_W);
2251
2252 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2253 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2254
2255 fetch_texel(mach->Sampler, unit, unit,
2256 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
2257 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2258 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2259 break;
2260
2261 case TGSI_TEXTURE_3D:
2262 case TGSI_TEXTURE_CUBE:
2263 case TGSI_TEXTURE_CUBE_ARRAY:
2264 case TGSI_TEXTURE_SHADOWCUBE:
2265 /* only TEXTURE_CUBE_ARRAY and TEXTURE_SHADOWCUBE actually need W */
2266 FETCH(&r[0], 0, TGSI_CHAN_X);
2267 FETCH(&r[1], 0, TGSI_CHAN_Y);
2268 FETCH(&r[2], 0, TGSI_CHAN_Z);
2269 FETCH(&r[3], 0, TGSI_CHAN_W);
2270
2271 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2272 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2273 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Z, derivs[2]);
2274
2275 fetch_texel(mach->Sampler, unit, unit,
2276 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
2277 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2278 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2279 break;
2280
2281 default:
2282 assert(0);
2283 }
2284
2285 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2286 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2287 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2288 }
2289 }
2290 }
2291
2292
2293 static void
2294 exec_txf(struct tgsi_exec_machine *mach,
2295 const struct tgsi_full_instruction *inst)
2296 {
2297 union tgsi_exec_channel r[4];
2298 uint chan;
2299 uint unit;
2300 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
2301 int j;
2302 int8_t offsets[3];
2303 unsigned target;
2304
2305 unit = fetch_sampler_unit(mach, inst, 1);
2306 /* always fetch all 3 offsets, overkill but keeps code simple */
2307 fetch_texel_offsets(mach, inst, offsets);
2308
2309 IFETCH(&r[3], 0, TGSI_CHAN_W);
2310
2311 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I ||
2312 inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I_MS) {
2313 target = mach->SamplerViews[unit].Resource;
2314 }
2315 else {
2316 target = inst->Texture.Texture;
2317 }
2318 switch(target) {
2319 case TGSI_TEXTURE_3D:
2320 case TGSI_TEXTURE_2D_ARRAY:
2321 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2322 case TGSI_TEXTURE_2D_ARRAY_MSAA:
2323 IFETCH(&r[2], 0, TGSI_CHAN_Z);
2324 /* fallthrough */
2325 case TGSI_TEXTURE_2D:
2326 case TGSI_TEXTURE_RECT:
2327 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2328 case TGSI_TEXTURE_SHADOW2D:
2329 case TGSI_TEXTURE_SHADOWRECT:
2330 case TGSI_TEXTURE_1D_ARRAY:
2331 case TGSI_TEXTURE_2D_MSAA:
2332 IFETCH(&r[1], 0, TGSI_CHAN_Y);
2333 /* fallthrough */
2334 case TGSI_TEXTURE_BUFFER:
2335 case TGSI_TEXTURE_1D:
2336 case TGSI_TEXTURE_SHADOW1D:
2337 IFETCH(&r[0], 0, TGSI_CHAN_X);
2338 break;
2339 default:
2340 assert(0);
2341 break;
2342 }
2343
2344 mach->Sampler->get_texel(mach->Sampler, unit, r[0].i, r[1].i, r[2].i, r[3].i,
2345 offsets, rgba);
2346
2347 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
2348 r[0].f[j] = rgba[0][j];
2349 r[1].f[j] = rgba[1][j];
2350 r[2].f[j] = rgba[2][j];
2351 r[3].f[j] = rgba[3][j];
2352 }
2353
2354 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I ||
2355 inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I_MS) {
2356 unsigned char swizzles[4];
2357 swizzles[0] = inst->Src[1].Register.SwizzleX;
2358 swizzles[1] = inst->Src[1].Register.SwizzleY;
2359 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2360 swizzles[3] = inst->Src[1].Register.SwizzleW;
2361
2362 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2363 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2364 store_dest(mach, &r[swizzles[chan]],
2365 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2366 }
2367 }
2368 }
2369 else {
2370 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2371 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2372 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2373 }
2374 }
2375 }
2376 }
2377
2378 static void
2379 exec_txq(struct tgsi_exec_machine *mach,
2380 const struct tgsi_full_instruction *inst)
2381 {
2382 int result[4];
2383 union tgsi_exec_channel r[4], src;
2384 uint chan;
2385 uint unit;
2386 int i,j;
2387
2388 unit = fetch_sampler_unit(mach, inst, 1);
2389
2390 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
2391
2392 /* XXX: This interface can't return per-pixel values */
2393 mach->Sampler->get_dims(mach->Sampler, unit, src.i[0], result);
2394
2395 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2396 for (j = 0; j < 4; j++) {
2397 r[j].i[i] = result[j];
2398 }
2399 }
2400
2401 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2402 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2403 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
2404 TGSI_EXEC_DATA_INT);
2405 }
2406 }
2407 }
2408
2409 static void
2410 exec_sample(struct tgsi_exec_machine *mach,
2411 const struct tgsi_full_instruction *inst,
2412 uint modifier, boolean compare)
2413 {
2414 const uint resource_unit = inst->Src[1].Register.Index;
2415 const uint sampler_unit = inst->Src[2].Register.Index;
2416 union tgsi_exec_channel r[5], c1;
2417 const union tgsi_exec_channel *lod = &ZeroVec;
2418 enum tgsi_sampler_control control = TGSI_SAMPLER_LOD_NONE;
2419 uint chan;
2420 unsigned char swizzles[4];
2421 int8_t offsets[3];
2422
2423 /* always fetch all 3 offsets, overkill but keeps code simple */
2424 fetch_texel_offsets(mach, inst, offsets);
2425
2426 assert(modifier != TEX_MODIFIER_PROJECTED);
2427
2428 if (modifier != TEX_MODIFIER_NONE) {
2429 if (modifier == TEX_MODIFIER_LOD_BIAS) {
2430 FETCH(&c1, 3, TGSI_CHAN_X);
2431 lod = &c1;
2432 control = TGSI_SAMPLER_LOD_BIAS;
2433 }
2434 else if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
2435 FETCH(&c1, 3, TGSI_CHAN_X);
2436 lod = &c1;
2437 control = TGSI_SAMPLER_LOD_EXPLICIT;
2438 }
2439 else {
2440 assert(modifier == TEX_MODIFIER_LEVEL_ZERO);
2441 control = TGSI_SAMPLER_LOD_ZERO;
2442 }
2443 }
2444
2445 FETCH(&r[0], 0, TGSI_CHAN_X);
2446
2447 switch (mach->SamplerViews[resource_unit].Resource) {
2448 case TGSI_TEXTURE_1D:
2449 if (compare) {
2450 FETCH(&r[2], 3, TGSI_CHAN_X);
2451 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2452 &r[0], &ZeroVec, &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2453 NULL, offsets, control,
2454 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2455 }
2456 else {
2457 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2458 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2459 NULL, offsets, control,
2460 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2461 }
2462 break;
2463
2464 case TGSI_TEXTURE_1D_ARRAY:
2465 case TGSI_TEXTURE_2D:
2466 case TGSI_TEXTURE_RECT:
2467 FETCH(&r[1], 0, TGSI_CHAN_Y);
2468 if (compare) {
2469 FETCH(&r[2], 3, TGSI_CHAN_X);
2470 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2471 &r[0], &r[1], &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2472 NULL, offsets, control,
2473 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2474 }
2475 else {
2476 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2477 &r[0], &r[1], &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2478 NULL, offsets, control,
2479 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2480 }
2481 break;
2482
2483 case TGSI_TEXTURE_2D_ARRAY:
2484 case TGSI_TEXTURE_3D:
2485 case TGSI_TEXTURE_CUBE:
2486 FETCH(&r[1], 0, TGSI_CHAN_Y);
2487 FETCH(&r[2], 0, TGSI_CHAN_Z);
2488 if(compare) {
2489 FETCH(&r[3], 3, TGSI_CHAN_X);
2490 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2491 &r[0], &r[1], &r[2], &r[3], lod,
2492 NULL, offsets, control,
2493 &r[0], &r[1], &r[2], &r[3]);
2494 }
2495 else {
2496 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2497 &r[0], &r[1], &r[2], &ZeroVec, lod,
2498 NULL, offsets, control,
2499 &r[0], &r[1], &r[2], &r[3]);
2500 }
2501 break;
2502
2503 case TGSI_TEXTURE_CUBE_ARRAY:
2504 FETCH(&r[1], 0, TGSI_CHAN_Y);
2505 FETCH(&r[2], 0, TGSI_CHAN_Z);
2506 FETCH(&r[3], 0, TGSI_CHAN_W);
2507 if(compare) {
2508 FETCH(&r[4], 3, TGSI_CHAN_X);
2509 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2510 &r[0], &r[1], &r[2], &r[3], &r[4],
2511 NULL, offsets, control,
2512 &r[0], &r[1], &r[2], &r[3]);
2513 }
2514 else {
2515 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2516 &r[0], &r[1], &r[2], &r[3], lod,
2517 NULL, offsets, control,
2518 &r[0], &r[1], &r[2], &r[3]);
2519 }
2520 break;
2521
2522
2523 default:
2524 assert(0);
2525 }
2526
2527 swizzles[0] = inst->Src[1].Register.SwizzleX;
2528 swizzles[1] = inst->Src[1].Register.SwizzleY;
2529 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2530 swizzles[3] = inst->Src[1].Register.SwizzleW;
2531
2532 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2533 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2534 store_dest(mach, &r[swizzles[chan]],
2535 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2536 }
2537 }
2538 }
2539
2540 static void
2541 exec_sample_d(struct tgsi_exec_machine *mach,
2542 const struct tgsi_full_instruction *inst)
2543 {
2544 const uint resource_unit = inst->Src[1].Register.Index;
2545 const uint sampler_unit = inst->Src[2].Register.Index;
2546 union tgsi_exec_channel r[4];
2547 float derivs[3][2][TGSI_QUAD_SIZE];
2548 uint chan;
2549 unsigned char swizzles[4];
2550 int8_t offsets[3];
2551
2552 /* always fetch all 3 offsets, overkill but keeps code simple */
2553 fetch_texel_offsets(mach, inst, offsets);
2554
2555 FETCH(&r[0], 0, TGSI_CHAN_X);
2556
2557 switch (mach->SamplerViews[resource_unit].Resource) {
2558 case TGSI_TEXTURE_1D:
2559 case TGSI_TEXTURE_1D_ARRAY:
2560 /* only 1D array actually needs Y */
2561 FETCH(&r[1], 0, TGSI_CHAN_Y);
2562
2563 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2564
2565 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2566 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2567 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2568 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2569 break;
2570
2571 case TGSI_TEXTURE_2D:
2572 case TGSI_TEXTURE_RECT:
2573 case TGSI_TEXTURE_2D_ARRAY:
2574 /* only 2D array actually needs Z */
2575 FETCH(&r[1], 0, TGSI_CHAN_Y);
2576 FETCH(&r[2], 0, TGSI_CHAN_Z);
2577
2578 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2579 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2580
2581 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2582 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* inputs */
2583 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2584 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2585 break;
2586
2587 case TGSI_TEXTURE_3D:
2588 case TGSI_TEXTURE_CUBE:
2589 case TGSI_TEXTURE_CUBE_ARRAY:
2590 /* only cube array actually needs W */
2591 FETCH(&r[1], 0, TGSI_CHAN_Y);
2592 FETCH(&r[2], 0, TGSI_CHAN_Z);
2593 FETCH(&r[3], 0, TGSI_CHAN_W);
2594
2595 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2596 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2597 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Z, derivs[2]);
2598
2599 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2600 &r[0], &r[1], &r[2], &r[3], &ZeroVec,
2601 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2602 &r[0], &r[1], &r[2], &r[3]);
2603 break;
2604
2605 default:
2606 assert(0);
2607 }
2608
2609 swizzles[0] = inst->Src[1].Register.SwizzleX;
2610 swizzles[1] = inst->Src[1].Register.SwizzleY;
2611 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2612 swizzles[3] = inst->Src[1].Register.SwizzleW;
2613
2614 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2615 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2616 store_dest(mach, &r[swizzles[chan]],
2617 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2618 }
2619 }
2620 }
2621
2622
2623 /**
2624 * Evaluate a constant-valued coefficient at the position of the
2625 * current quad.
2626 */
2627 static void
2628 eval_constant_coef(
2629 struct tgsi_exec_machine *mach,
2630 unsigned attrib,
2631 unsigned chan )
2632 {
2633 unsigned i;
2634
2635 for( i = 0; i < TGSI_QUAD_SIZE; i++ ) {
2636 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
2637 }
2638 }
2639
2640 /**
2641 * Evaluate a linear-valued coefficient at the position of the
2642 * current quad.
2643 */
2644 static void
2645 eval_linear_coef(
2646 struct tgsi_exec_machine *mach,
2647 unsigned attrib,
2648 unsigned chan )
2649 {
2650 const float x = mach->QuadPos.xyzw[0].f[0];
2651 const float y = mach->QuadPos.xyzw[1].f[0];
2652 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2653 const float dady = mach->InterpCoefs[attrib].dady[chan];
2654 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2655 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
2656 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
2657 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
2658 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
2659 }
2660
2661 /**
2662 * Evaluate a perspective-valued coefficient at the position of the
2663 * current quad.
2664 */
2665 static void
2666 eval_perspective_coef(
2667 struct tgsi_exec_machine *mach,
2668 unsigned attrib,
2669 unsigned chan )
2670 {
2671 const float x = mach->QuadPos.xyzw[0].f[0];
2672 const float y = mach->QuadPos.xyzw[1].f[0];
2673 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2674 const float dady = mach->InterpCoefs[attrib].dady[chan];
2675 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2676 const float *w = mach->QuadPos.xyzw[3].f;
2677 /* divide by W here */
2678 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
2679 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
2680 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
2681 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
2682 }
2683
2684
2685 typedef void (* eval_coef_func)(
2686 struct tgsi_exec_machine *mach,
2687 unsigned attrib,
2688 unsigned chan );
2689
2690 static void
2691 exec_declaration(struct tgsi_exec_machine *mach,
2692 const struct tgsi_full_declaration *decl)
2693 {
2694 if (decl->Declaration.File == TGSI_FILE_SAMPLER_VIEW) {
2695 mach->SamplerViews[decl->Range.First] = decl->SamplerView;
2696 return;
2697 }
2698
2699 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
2700 if (decl->Declaration.File == TGSI_FILE_INPUT) {
2701 uint first, last, mask;
2702
2703 first = decl->Range.First;
2704 last = decl->Range.Last;
2705 mask = decl->Declaration.UsageMask;
2706
2707 /* XXX we could remove this special-case code since
2708 * mach->InterpCoefs[first].a0 should already have the
2709 * front/back-face value. But we should first update the
2710 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2711 * Then, we could remove the tgsi_exec_machine::Face field.
2712 */
2713 /* XXX make FACE a system value */
2714 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
2715 uint i;
2716
2717 assert(decl->Semantic.Index == 0);
2718 assert(first == last);
2719
2720 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2721 mach->Inputs[first].xyzw[0].f[i] = mach->Face;
2722 }
2723 } else {
2724 eval_coef_func eval;
2725 uint i, j;
2726
2727 switch (decl->Interp.Interpolate) {
2728 case TGSI_INTERPOLATE_CONSTANT:
2729 eval = eval_constant_coef;
2730 break;
2731
2732 case TGSI_INTERPOLATE_LINEAR:
2733 eval = eval_linear_coef;
2734 break;
2735
2736 case TGSI_INTERPOLATE_PERSPECTIVE:
2737 eval = eval_perspective_coef;
2738 break;
2739
2740 case TGSI_INTERPOLATE_COLOR:
2741 eval = mach->flatshade_color ? eval_constant_coef : eval_perspective_coef;
2742 break;
2743
2744 default:
2745 assert(0);
2746 return;
2747 }
2748
2749 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2750 if (mask & (1 << j)) {
2751 for (i = first; i <= last; i++) {
2752 eval(mach, i, j);
2753 }
2754 }
2755 }
2756 }
2757
2758 if (DEBUG_EXECUTION) {
2759 uint i, j;
2760 for (i = first; i <= last; ++i) {
2761 debug_printf("IN[%2u] = ", i);
2762 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2763 if (j > 0) {
2764 debug_printf(" ");
2765 }
2766 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
2767 mach->Inputs[i].xyzw[0].f[j], mach->Inputs[i].xyzw[0].u[j],
2768 mach->Inputs[i].xyzw[1].f[j], mach->Inputs[i].xyzw[1].u[j],
2769 mach->Inputs[i].xyzw[2].f[j], mach->Inputs[i].xyzw[2].u[j],
2770 mach->Inputs[i].xyzw[3].f[j], mach->Inputs[i].xyzw[3].u[j]);
2771 }
2772 }
2773 }
2774 }
2775 }
2776
2777 if (decl->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
2778 mach->SysSemanticToIndex[decl->Declaration.Semantic] = decl->Range.First;
2779 }
2780 }
2781
2782 typedef void (* micro_unary_op)(union tgsi_exec_channel *dst,
2783 const union tgsi_exec_channel *src);
2784
2785 static void
2786 exec_scalar_unary(struct tgsi_exec_machine *mach,
2787 const struct tgsi_full_instruction *inst,
2788 micro_unary_op op,
2789 enum tgsi_exec_datatype dst_datatype,
2790 enum tgsi_exec_datatype src_datatype)
2791 {
2792 unsigned int chan;
2793 union tgsi_exec_channel src;
2794 union tgsi_exec_channel dst;
2795
2796 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, src_datatype);
2797 op(&dst, &src);
2798 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2799 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2800 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2801 }
2802 }
2803 }
2804
2805 static void
2806 exec_vector_unary(struct tgsi_exec_machine *mach,
2807 const struct tgsi_full_instruction *inst,
2808 micro_unary_op op,
2809 enum tgsi_exec_datatype dst_datatype,
2810 enum tgsi_exec_datatype src_datatype)
2811 {
2812 unsigned int chan;
2813 struct tgsi_exec_vector dst;
2814
2815 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2816 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2817 union tgsi_exec_channel src;
2818
2819 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
2820 op(&dst.xyzw[chan], &src);
2821 }
2822 }
2823 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2824 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2825 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2826 }
2827 }
2828 }
2829
2830 typedef void (* micro_binary_op)(union tgsi_exec_channel *dst,
2831 const union tgsi_exec_channel *src0,
2832 const union tgsi_exec_channel *src1);
2833
2834 static void
2835 exec_scalar_binary(struct tgsi_exec_machine *mach,
2836 const struct tgsi_full_instruction *inst,
2837 micro_binary_op op,
2838 enum tgsi_exec_datatype dst_datatype,
2839 enum tgsi_exec_datatype src_datatype)
2840 {
2841 unsigned int chan;
2842 union tgsi_exec_channel src[2];
2843 union tgsi_exec_channel dst;
2844
2845 fetch_source(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, src_datatype);
2846 fetch_source(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, src_datatype);
2847 op(&dst, &src[0], &src[1]);
2848 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2849 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2850 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2851 }
2852 }
2853 }
2854
2855 static void
2856 exec_vector_binary(struct tgsi_exec_machine *mach,
2857 const struct tgsi_full_instruction *inst,
2858 micro_binary_op op,
2859 enum tgsi_exec_datatype dst_datatype,
2860 enum tgsi_exec_datatype src_datatype)
2861 {
2862 unsigned int chan;
2863 struct tgsi_exec_vector dst;
2864
2865 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2866 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2867 union tgsi_exec_channel src[2];
2868
2869 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2870 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2871 op(&dst.xyzw[chan], &src[0], &src[1]);
2872 }
2873 }
2874 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2875 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2876 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2877 }
2878 }
2879 }
2880
2881 typedef void (* micro_trinary_op)(union tgsi_exec_channel *dst,
2882 const union tgsi_exec_channel *src0,
2883 const union tgsi_exec_channel *src1,
2884 const union tgsi_exec_channel *src2);
2885
2886 static void
2887 exec_vector_trinary(struct tgsi_exec_machine *mach,
2888 const struct tgsi_full_instruction *inst,
2889 micro_trinary_op op,
2890 enum tgsi_exec_datatype dst_datatype,
2891 enum tgsi_exec_datatype src_datatype)
2892 {
2893 unsigned int chan;
2894 struct tgsi_exec_vector dst;
2895
2896 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2897 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2898 union tgsi_exec_channel src[3];
2899
2900 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2901 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2902 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2903 op(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
2904 }
2905 }
2906 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2907 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2908 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2909 }
2910 }
2911 }
2912
2913 typedef void (* micro_quaternary_op)(union tgsi_exec_channel *dst,
2914 const union tgsi_exec_channel *src0,
2915 const union tgsi_exec_channel *src1,
2916 const union tgsi_exec_channel *src2,
2917 const union tgsi_exec_channel *src3);
2918
2919 static void
2920 exec_vector_quaternary(struct tgsi_exec_machine *mach,
2921 const struct tgsi_full_instruction *inst,
2922 micro_quaternary_op op,
2923 enum tgsi_exec_datatype dst_datatype,
2924 enum tgsi_exec_datatype src_datatype)
2925 {
2926 unsigned int chan;
2927 struct tgsi_exec_vector dst;
2928
2929 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2930 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2931 union tgsi_exec_channel src[4];
2932
2933 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2934 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2935 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2936 fetch_source(mach, &src[3], &inst->Src[3], chan, src_datatype);
2937 op(&dst.xyzw[chan], &src[0], &src[1], &src[2], &src[3]);
2938 }
2939 }
2940 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2941 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2942 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2943 }
2944 }
2945 }
2946
2947 static void
2948 exec_dp3(struct tgsi_exec_machine *mach,
2949 const struct tgsi_full_instruction *inst)
2950 {
2951 unsigned int chan;
2952 union tgsi_exec_channel arg[3];
2953
2954 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2955 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2956 micro_mul(&arg[2], &arg[0], &arg[1]);
2957
2958 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_Z; chan++) {
2959 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2960 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2961 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2962 }
2963
2964 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2965 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2966 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2967 }
2968 }
2969 }
2970
2971 static void
2972 exec_dp4(struct tgsi_exec_machine *mach,
2973 const struct tgsi_full_instruction *inst)
2974 {
2975 unsigned int chan;
2976 union tgsi_exec_channel arg[3];
2977
2978 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2979 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2980 micro_mul(&arg[2], &arg[0], &arg[1]);
2981
2982 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_W; chan++) {
2983 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2984 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2985 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2986 }
2987
2988 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2989 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2990 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2991 }
2992 }
2993 }
2994
2995 static void
2996 exec_dp2a(struct tgsi_exec_machine *mach,
2997 const struct tgsi_full_instruction *inst)
2998 {
2999 unsigned int chan;
3000 union tgsi_exec_channel arg[3];
3001
3002 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3003 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3004 micro_mul(&arg[2], &arg[0], &arg[1]);
3005
3006 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3007 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3008 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
3009
3010 fetch_source(mach, &arg[1], &inst->Src[2], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3011 micro_add(&arg[0], &arg[0], &arg[1]);
3012
3013 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3014 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3015 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3016 }
3017 }
3018 }
3019
3020 static void
3021 exec_dph(struct tgsi_exec_machine *mach,
3022 const struct tgsi_full_instruction *inst)
3023 {
3024 unsigned int chan;
3025 union tgsi_exec_channel arg[3];
3026
3027 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3028 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3029 micro_mul(&arg[2], &arg[0], &arg[1]);
3030
3031 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3032 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3033 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
3034
3035 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3036 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3037 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
3038
3039 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3040 micro_add(&arg[0], &arg[0], &arg[1]);
3041
3042 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3043 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3044 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3045 }
3046 }
3047 }
3048
3049 static void
3050 exec_dp2(struct tgsi_exec_machine *mach,
3051 const struct tgsi_full_instruction *inst)
3052 {
3053 unsigned int chan;
3054 union tgsi_exec_channel arg[3];
3055
3056 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3057 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3058 micro_mul(&arg[2], &arg[0], &arg[1]);
3059
3060 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3061 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3062 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
3063
3064 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3065 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3066 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3067 }
3068 }
3069 }
3070
3071 static void
3072 exec_pk2h(struct tgsi_exec_machine *mach,
3073 const struct tgsi_full_instruction *inst)
3074 {
3075 unsigned chan;
3076 union tgsi_exec_channel arg[2], dst;
3077
3078 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3079 fetch_source(mach, &arg[1], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3080 for (chan = 0; chan < TGSI_QUAD_SIZE; chan++) {
3081 dst.u[chan] = util_float_to_half(arg[0].f[chan]) |
3082 (util_float_to_half(arg[1].f[chan]) << 16);
3083 }
3084 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3085 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3086 store_dest(mach, &dst, &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_UINT);
3087 }
3088 }
3089 }
3090
3091 static void
3092 exec_up2h(struct tgsi_exec_machine *mach,
3093 const struct tgsi_full_instruction *inst)
3094 {
3095 unsigned chan;
3096 union tgsi_exec_channel arg, dst[2];
3097
3098 fetch_source(mach, &arg, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3099 for (chan = 0; chan < TGSI_QUAD_SIZE; chan++) {
3100 dst[0].f[chan] = util_half_to_float(arg.u[chan] & 0xffff);
3101 dst[1].f[chan] = util_half_to_float(arg.u[chan] >> 16);
3102 }
3103 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3104 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3105 store_dest(mach, &dst[chan & 1], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3106 }
3107 }
3108 }
3109
3110 static void
3111 exec_scs(struct tgsi_exec_machine *mach,
3112 const struct tgsi_full_instruction *inst)
3113 {
3114 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) {
3115 union tgsi_exec_channel arg;
3116 union tgsi_exec_channel result;
3117
3118 fetch_source(mach, &arg, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3119
3120 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3121 micro_cos(&result, &arg);
3122 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3123 }
3124 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3125 micro_sin(&result, &arg);
3126 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3127 }
3128 }
3129 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3130 store_dest(mach, &ZeroVec, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3131 }
3132 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3133 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3134 }
3135 }
3136
3137 static void
3138 exec_xpd(struct tgsi_exec_machine *mach,
3139 const struct tgsi_full_instruction *inst)
3140 {
3141 union tgsi_exec_channel r[6];
3142 union tgsi_exec_channel d[3];
3143
3144 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3145 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3146
3147 micro_mul(&r[2], &r[0], &r[1]);
3148
3149 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3150 fetch_source(mach, &r[4], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3151
3152 micro_mul(&r[5], &r[3], &r[4] );
3153 micro_sub(&d[TGSI_CHAN_X], &r[2], &r[5]);
3154
3155 fetch_source(mach, &r[2], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3156
3157 micro_mul(&r[3], &r[3], &r[2]);
3158
3159 fetch_source(mach, &r[5], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3160
3161 micro_mul(&r[1], &r[1], &r[5]);
3162 micro_sub(&d[TGSI_CHAN_Y], &r[3], &r[1]);
3163
3164 micro_mul(&r[5], &r[5], &r[4]);
3165 micro_mul(&r[0], &r[0], &r[2]);
3166 micro_sub(&d[TGSI_CHAN_Z], &r[5], &r[0]);
3167
3168 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3169 store_dest(mach, &d[TGSI_CHAN_X], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3170 }
3171 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3172 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3173 }
3174 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3175 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3176 }
3177 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3178 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3179 }
3180 }
3181
3182 static void
3183 exec_dst(struct tgsi_exec_machine *mach,
3184 const struct tgsi_full_instruction *inst)
3185 {
3186 union tgsi_exec_channel r[2];
3187 union tgsi_exec_channel d[4];
3188
3189 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3190 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3191 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3192 micro_mul(&d[TGSI_CHAN_Y], &r[0], &r[1]);
3193 }
3194 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3195 fetch_source(mach, &d[TGSI_CHAN_Z], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3196 }
3197 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3198 fetch_source(mach, &d[TGSI_CHAN_W], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3199 }
3200
3201 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3202 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3203 }
3204 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3205 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3206 }
3207 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3208 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3209 }
3210 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3211 store_dest(mach, &d[TGSI_CHAN_W], &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3212 }
3213 }
3214
3215 static void
3216 exec_log(struct tgsi_exec_machine *mach,
3217 const struct tgsi_full_instruction *inst)
3218 {
3219 union tgsi_exec_channel r[3];
3220
3221 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3222 micro_abs(&r[2], &r[0]); /* r2 = abs(r0) */
3223 micro_lg2(&r[1], &r[2]); /* r1 = lg2(r2) */
3224 micro_flr(&r[0], &r[1]); /* r0 = floor(r1) */
3225 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3226 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3227 }
3228 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3229 micro_exp2(&r[0], &r[0]); /* r0 = 2 ^ r0 */
3230 micro_div(&r[0], &r[2], &r[0]); /* r0 = r2 / r0 */
3231 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3232 }
3233 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3234 store_dest(mach, &r[1], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3235 }
3236 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3237 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3238 }
3239 }
3240
3241 static void
3242 exec_exp(struct tgsi_exec_machine *mach,
3243 const struct tgsi_full_instruction *inst)
3244 {
3245 union tgsi_exec_channel r[3];
3246
3247 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3248 micro_flr(&r[1], &r[0]); /* r1 = floor(r0) */
3249 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3250 micro_exp2(&r[2], &r[1]); /* r2 = 2 ^ r1 */
3251 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3252 }
3253 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3254 micro_sub(&r[2], &r[0], &r[1]); /* r2 = r0 - r1 */
3255 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3256 }
3257 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3258 micro_exp2(&r[2], &r[0]); /* r2 = 2 ^ r0 */
3259 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3260 }
3261 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3262 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3263 }
3264 }
3265
3266 static void
3267 exec_lit(struct tgsi_exec_machine *mach,
3268 const struct tgsi_full_instruction *inst)
3269 {
3270 union tgsi_exec_channel r[3];
3271 union tgsi_exec_channel d[3];
3272
3273 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YZ) {
3274 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3275 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3276 fetch_source(mach, &r[1], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3277 micro_max(&r[1], &r[1], &ZeroVec);
3278
3279 fetch_source(mach, &r[2], &inst->Src[0], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3280 micro_min(&r[2], &r[2], &P128Vec);
3281 micro_max(&r[2], &r[2], &M128Vec);
3282 micro_pow(&r[1], &r[1], &r[2]);
3283 micro_lt(&d[TGSI_CHAN_Z], &ZeroVec, &r[0], &r[1], &ZeroVec);
3284 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3285 }
3286 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3287 micro_max(&d[TGSI_CHAN_Y], &r[0], &ZeroVec);
3288 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3289 }
3290 }
3291 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3292 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3293 }
3294
3295 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3296 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3297 }
3298 }
3299
3300 static void
3301 exec_break(struct tgsi_exec_machine *mach)
3302 {
3303 if (mach->BreakType == TGSI_EXEC_BREAK_INSIDE_LOOP) {
3304 /* turn off loop channels for each enabled exec channel */
3305 mach->LoopMask &= ~mach->ExecMask;
3306 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3307 UPDATE_EXEC_MASK(mach);
3308 } else {
3309 assert(mach->BreakType == TGSI_EXEC_BREAK_INSIDE_SWITCH);
3310
3311 mach->Switch.mask = 0x0;
3312
3313 UPDATE_EXEC_MASK(mach);
3314 }
3315 }
3316
3317 static void
3318 exec_switch(struct tgsi_exec_machine *mach,
3319 const struct tgsi_full_instruction *inst)
3320 {
3321 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3322 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3323
3324 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3325 fetch_source(mach, &mach->Switch.selector, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3326 mach->Switch.mask = 0x0;
3327 mach->Switch.defaultMask = 0x0;
3328
3329 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3330 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_SWITCH;
3331
3332 UPDATE_EXEC_MASK(mach);
3333 }
3334
3335 static void
3336 exec_case(struct tgsi_exec_machine *mach,
3337 const struct tgsi_full_instruction *inst)
3338 {
3339 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3340 union tgsi_exec_channel src;
3341 uint mask = 0;
3342
3343 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3344
3345 if (mach->Switch.selector.u[0] == src.u[0]) {
3346 mask |= 0x1;
3347 }
3348 if (mach->Switch.selector.u[1] == src.u[1]) {
3349 mask |= 0x2;
3350 }
3351 if (mach->Switch.selector.u[2] == src.u[2]) {
3352 mask |= 0x4;
3353 }
3354 if (mach->Switch.selector.u[3] == src.u[3]) {
3355 mask |= 0x8;
3356 }
3357
3358 mach->Switch.defaultMask |= mask;
3359
3360 mach->Switch.mask |= mask & prevMask;
3361
3362 UPDATE_EXEC_MASK(mach);
3363 }
3364
3365 /* FIXME: this will only work if default is last */
3366 static void
3367 exec_default(struct tgsi_exec_machine *mach)
3368 {
3369 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3370
3371 mach->Switch.mask |= ~mach->Switch.defaultMask & prevMask;
3372
3373 UPDATE_EXEC_MASK(mach);
3374 }
3375
3376 static void
3377 exec_endswitch(struct tgsi_exec_machine *mach)
3378 {
3379 mach->Switch = mach->SwitchStack[--mach->SwitchStackTop];
3380 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3381
3382 UPDATE_EXEC_MASK(mach);
3383 }
3384
3385 typedef void (* micro_dop)(union tgsi_double_channel *dst,
3386 const union tgsi_double_channel *src);
3387
3388 static void
3389 fetch_double_channel(struct tgsi_exec_machine *mach,
3390 union tgsi_double_channel *chan,
3391 const struct tgsi_full_src_register *reg,
3392 uint chan_0,
3393 uint chan_1)
3394 {
3395 union tgsi_exec_channel src[2];
3396 uint i;
3397
3398 fetch_source_d(mach, &src[0], reg, chan_0, TGSI_EXEC_DATA_UINT);
3399 fetch_source_d(mach, &src[1], reg, chan_1, TGSI_EXEC_DATA_UINT);
3400
3401 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
3402 chan->u[i][0] = src[0].u[i];
3403 chan->u[i][1] = src[1].u[i];
3404 }
3405 if (reg->Register.Absolute) {
3406 micro_dabs(chan, chan);
3407 }
3408 if (reg->Register.Negate) {
3409 micro_dneg(chan, chan);
3410 }
3411 }
3412
3413 static void
3414 store_double_channel(struct tgsi_exec_machine *mach,
3415 const union tgsi_double_channel *chan,
3416 const struct tgsi_full_dst_register *reg,
3417 const struct tgsi_full_instruction *inst,
3418 uint chan_0,
3419 uint chan_1)
3420 {
3421 union tgsi_exec_channel dst[2];
3422 uint i;
3423 union tgsi_double_channel temp;
3424 const uint execmask = mach->ExecMask;
3425
3426 if (!inst->Instruction.Saturate) {
3427 for (i = 0; i < TGSI_QUAD_SIZE; i++)
3428 if (execmask & (1 << i)) {
3429 dst[0].u[i] = chan->u[i][0];
3430 dst[1].u[i] = chan->u[i][1];
3431 }
3432 }
3433 else {
3434 for (i = 0; i < TGSI_QUAD_SIZE; i++)
3435 if (execmask & (1 << i)) {
3436 if (chan->d[i] < 0.0)
3437 temp.d[i] = 0.0;
3438 else if (chan->d[i] > 1.0)
3439 temp.d[i] = 1.0;
3440 else
3441 temp.d[i] = chan->d[i];
3442
3443 dst[0].u[i] = temp.u[i][0];
3444 dst[1].u[i] = temp.u[i][1];
3445 }
3446 }
3447
3448 store_dest_double(mach, &dst[0], reg, inst, chan_0, TGSI_EXEC_DATA_UINT);
3449 if (chan_1 != -1)
3450 store_dest_double(mach, &dst[1], reg, inst, chan_1, TGSI_EXEC_DATA_UINT);
3451 }
3452
3453 static void
3454 exec_double_unary(struct tgsi_exec_machine *mach,
3455 const struct tgsi_full_instruction *inst,
3456 micro_dop op)
3457 {
3458 union tgsi_double_channel src;
3459 union tgsi_double_channel dst;
3460
3461 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3462 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3463 op(&dst, &src);
3464 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3465 }
3466 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3467 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3468 op(&dst, &src);
3469 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3470 }
3471 }
3472
3473 static void
3474 exec_double_binary(struct tgsi_exec_machine *mach,
3475 const struct tgsi_full_instruction *inst,
3476 micro_dop op,
3477 enum tgsi_exec_datatype dst_datatype)
3478 {
3479 union tgsi_double_channel src[2];
3480 union tgsi_double_channel dst;
3481 int first_dest_chan, second_dest_chan;
3482 int wmask;
3483
3484 wmask = inst->Dst[0].Register.WriteMask;
3485 /* these are & because of the way DSLT etc store their destinations */
3486 if (wmask & TGSI_WRITEMASK_XY) {
3487 first_dest_chan = TGSI_CHAN_X;
3488 second_dest_chan = TGSI_CHAN_Y;
3489 if (dst_datatype == TGSI_EXEC_DATA_UINT) {
3490 first_dest_chan = (wmask & TGSI_WRITEMASK_X) ? TGSI_CHAN_X : TGSI_CHAN_Y;
3491 second_dest_chan = -1;
3492 }
3493
3494 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3495 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, TGSI_CHAN_Y);
3496 op(&dst, src);
3497 store_double_channel(mach, &dst, &inst->Dst[0], inst, first_dest_chan, second_dest_chan);
3498 }
3499
3500 if (wmask & TGSI_WRITEMASK_ZW) {
3501 first_dest_chan = TGSI_CHAN_Z;
3502 second_dest_chan = TGSI_CHAN_W;
3503 if (dst_datatype == TGSI_EXEC_DATA_UINT) {
3504 first_dest_chan = (wmask & TGSI_WRITEMASK_Z) ? TGSI_CHAN_Z : TGSI_CHAN_W;
3505 second_dest_chan = -1;
3506 }
3507
3508 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3509 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_CHAN_W);
3510 op(&dst, src);
3511 store_double_channel(mach, &dst, &inst->Dst[0], inst, first_dest_chan, second_dest_chan);
3512 }
3513 }
3514
3515 static void
3516 exec_double_trinary(struct tgsi_exec_machine *mach,
3517 const struct tgsi_full_instruction *inst,
3518 micro_dop op)
3519 {
3520 union tgsi_double_channel src[3];
3521 union tgsi_double_channel dst;
3522
3523 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3524 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3525 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, TGSI_CHAN_Y);
3526 fetch_double_channel(mach, &src[2], &inst->Src[2], TGSI_CHAN_X, TGSI_CHAN_Y);
3527 op(&dst, src);
3528 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3529 }
3530 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3531 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3532 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_CHAN_W);
3533 fetch_double_channel(mach, &src[2], &inst->Src[2], TGSI_CHAN_Z, TGSI_CHAN_W);
3534 op(&dst, src);
3535 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3536 }
3537 }
3538
3539 static void
3540 exec_f2d(struct tgsi_exec_machine *mach,
3541 const struct tgsi_full_instruction *inst)
3542 {
3543 union tgsi_exec_channel src;
3544 union tgsi_double_channel dst;
3545
3546 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3547 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3548 micro_f2d(&dst, &src);
3549 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3550 }
3551 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3552 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3553 micro_f2d(&dst, &src);
3554 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3555 }
3556 }
3557
3558 static void
3559 exec_d2f(struct tgsi_exec_machine *mach,
3560 const struct tgsi_full_instruction *inst)
3561 {
3562 union tgsi_double_channel src;
3563 union tgsi_exec_channel dst;
3564 int wm = inst->Dst[0].Register.WriteMask;
3565 int i;
3566 int bit;
3567 for (i = 0; i < 2; i++) {
3568 bit = ffs(wm);
3569 if (bit) {
3570 wm &= ~(1 << (bit - 1));
3571 if (i == 0)
3572 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3573 else
3574 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3575 micro_d2f(&dst, &src);
3576 store_dest(mach, &dst, &inst->Dst[0], inst, bit - 1, TGSI_EXEC_DATA_FLOAT);
3577 }
3578 }
3579 }
3580
3581 static void
3582 exec_i2d(struct tgsi_exec_machine *mach,
3583 const struct tgsi_full_instruction *inst)
3584 {
3585 union tgsi_exec_channel src;
3586 union tgsi_double_channel dst;
3587
3588 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3589 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
3590 micro_i2d(&dst, &src);
3591 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3592 }
3593 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3594 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_INT);
3595 micro_i2d(&dst, &src);
3596 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3597 }
3598 }
3599
3600 static void
3601 exec_d2i(struct tgsi_exec_machine *mach,
3602 const struct tgsi_full_instruction *inst)
3603 {
3604 union tgsi_double_channel src;
3605 union tgsi_exec_channel dst;
3606 int wm = inst->Dst[0].Register.WriteMask;
3607 int i;
3608 int bit;
3609 for (i = 0; i < 2; i++) {
3610 bit = ffs(wm);
3611 if (bit) {
3612 wm &= ~(1 << (bit - 1));
3613 if (i == 0)
3614 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3615 else
3616 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3617 micro_d2i(&dst, &src);
3618 store_dest(mach, &dst, &inst->Dst[0], inst, bit - 1, TGSI_EXEC_DATA_INT);
3619 }
3620 }
3621 }
3622 static void
3623 exec_u2d(struct tgsi_exec_machine *mach,
3624 const struct tgsi_full_instruction *inst)
3625 {
3626 union tgsi_exec_channel src;
3627 union tgsi_double_channel dst;
3628
3629 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3630 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3631 micro_u2d(&dst, &src);
3632 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3633 }
3634 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3635 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_UINT);
3636 micro_u2d(&dst, &src);
3637 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3638 }
3639 }
3640
3641 static void
3642 exec_d2u(struct tgsi_exec_machine *mach,
3643 const struct tgsi_full_instruction *inst)
3644 {
3645 union tgsi_double_channel src;
3646 union tgsi_exec_channel dst;
3647 int wm = inst->Dst[0].Register.WriteMask;
3648 int i;
3649 int bit;
3650 for (i = 0; i < 2; i++) {
3651 bit = ffs(wm);
3652 if (bit) {
3653 wm &= ~(1 << (bit - 1));
3654 if (i == 0)
3655 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3656 else
3657 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3658 micro_d2u(&dst, &src);
3659 store_dest(mach, &dst, &inst->Dst[0], inst, bit - 1, TGSI_EXEC_DATA_UINT);
3660 }
3661 }
3662 }
3663
3664 static void
3665 exec_dldexp(struct tgsi_exec_machine *mach,
3666 const struct tgsi_full_instruction *inst)
3667 {
3668 union tgsi_double_channel src0;
3669 union tgsi_exec_channel src1;
3670 union tgsi_double_channel dst;
3671 int wmask;
3672
3673 wmask = inst->Dst[0].Register.WriteMask;
3674 if (wmask & TGSI_WRITEMASK_XY) {
3675 fetch_double_channel(mach, &src0, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3676 fetch_source(mach, &src1, &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
3677 micro_dldexp(&dst, &src0, &src1);
3678 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3679 }
3680
3681 if (wmask & TGSI_WRITEMASK_ZW) {
3682 fetch_double_channel(mach, &src0, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3683 fetch_source(mach, &src1, &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_INT);
3684 micro_dldexp(&dst, &src0, &src1);
3685 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3686 }
3687 }
3688
3689 static void
3690 exec_dfracexp(struct tgsi_exec_machine *mach,
3691 const struct tgsi_full_instruction *inst)
3692 {
3693 union tgsi_double_channel src;
3694 union tgsi_double_channel dst;
3695 union tgsi_exec_channel dst_exp;
3696
3697 if (((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY)) {
3698 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3699 micro_dfracexp(&dst, &dst_exp, &src);
3700 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3701 store_dest(mach, &dst_exp, &inst->Dst[1], inst, ffs(inst->Dst[1].Register.WriteMask) - 1, TGSI_EXEC_DATA_INT);
3702 }
3703 if (((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW)) {
3704 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3705 micro_dfracexp(&dst, &dst_exp, &src);
3706 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3707 store_dest(mach, &dst_exp, &inst->Dst[1], inst, ffs(inst->Dst[1].Register.WriteMask) - 1, TGSI_EXEC_DATA_INT);
3708 }
3709 }
3710
3711 static int
3712 get_image_coord_dim(unsigned tgsi_tex)
3713 {
3714 int dim;
3715 switch (tgsi_tex) {
3716 case TGSI_TEXTURE_BUFFER:
3717 case TGSI_TEXTURE_1D:
3718 dim = 1;
3719 break;
3720 case TGSI_TEXTURE_2D:
3721 case TGSI_TEXTURE_RECT:
3722 case TGSI_TEXTURE_1D_ARRAY:
3723 case TGSI_TEXTURE_2D_MSAA:
3724 dim = 2;
3725 break;
3726 case TGSI_TEXTURE_3D:
3727 case TGSI_TEXTURE_CUBE:
3728 case TGSI_TEXTURE_2D_ARRAY:
3729 case TGSI_TEXTURE_2D_ARRAY_MSAA:
3730 case TGSI_TEXTURE_CUBE_ARRAY:
3731 dim = 3;
3732 break;
3733 default:
3734 assert(!"unknown texture target");
3735 dim = 0;
3736 break;
3737 }
3738
3739 return dim;
3740 }
3741
3742 static int
3743 get_image_coord_sample(unsigned tgsi_tex)
3744 {
3745 int sample = 0;
3746 switch (tgsi_tex) {
3747 case TGSI_TEXTURE_2D_MSAA:
3748 sample = 3;
3749 break;
3750 case TGSI_TEXTURE_2D_ARRAY_MSAA:
3751 sample = 4;
3752 break;
3753 default:
3754 break;
3755 }
3756 return sample;
3757 }
3758
3759 static void
3760 exec_load(struct tgsi_exec_machine *mach,
3761 const struct tgsi_full_instruction *inst)
3762 {
3763 union tgsi_exec_channel r[4], sample_r;
3764 uint unit;
3765 int sample;
3766 int i, j;
3767 int dim;
3768 uint chan;
3769 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
3770 struct tgsi_image_params params;
3771 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3772
3773 unit = fetch_sampler_unit(mach, inst, 0);
3774 dim = get_image_coord_dim(inst->Memory.Texture);
3775 sample = get_image_coord_sample(inst->Memory.Texture);
3776 assert(dim <= 3);
3777
3778 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3779 params.unit = unit;
3780 params.tgsi_tex_instr = inst->Memory.Texture;
3781 params.format = inst->Memory.Format;
3782
3783 for (i = 0; i < dim; i++) {
3784 IFETCH(&r[i], 1, TGSI_CHAN_X + i);
3785 }
3786
3787 if (sample)
3788 IFETCH(&sample_r, 1, TGSI_CHAN_X + sample);
3789
3790 mach->Image->load(mach->Image, &params,
3791 r[0].i, r[1].i, r[2].i, sample_r.i,
3792 rgba);
3793 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3794 r[0].f[j] = rgba[0][j];
3795 r[1].f[j] = rgba[1][j];
3796 r[2].f[j] = rgba[2][j];
3797 r[3].f[j] = rgba[3][j];
3798 }
3799 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3800 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3801 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3802 }
3803 }
3804 }
3805
3806 static void
3807 exec_store(struct tgsi_exec_machine *mach,
3808 const struct tgsi_full_instruction *inst)
3809 {
3810 union tgsi_exec_channel r[3], sample_r;
3811 union tgsi_exec_channel value[4];
3812 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
3813 struct tgsi_image_params params;
3814 int dim;
3815 int sample;
3816 int i, j;
3817 uint unit;
3818 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3819 unit = inst->Dst[0].Register.Index;
3820 dim = get_image_coord_dim(inst->Memory.Texture);
3821 sample = get_image_coord_sample(inst->Memory.Texture);
3822 assert(dim <= 3);
3823
3824 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3825 params.unit = unit;
3826 params.tgsi_tex_instr = inst->Memory.Texture;
3827 params.format = inst->Memory.Format;
3828
3829 for (i = 0; i < dim; i++) {
3830 IFETCH(&r[i], 0, TGSI_CHAN_X + i);
3831 }
3832
3833 for (i = 0; i < 4; i++) {
3834 FETCH(&value[i], 1, TGSI_CHAN_X + i);
3835 }
3836 if (sample)
3837 IFETCH(&sample_r, 0, TGSI_CHAN_X + sample);
3838
3839 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3840 rgba[0][j] = value[0].f[j];
3841 rgba[1][j] = value[1].f[j];
3842 rgba[2][j] = value[2].f[j];
3843 rgba[3][j] = value[3].f[j];
3844 }
3845
3846 mach->Image->store(mach->Image, &params,
3847 r[0].i, r[1].i, r[2].i, sample_r.i,
3848 rgba);
3849 }
3850
3851 static void
3852 exec_atomop(struct tgsi_exec_machine *mach,
3853 const struct tgsi_full_instruction *inst)
3854 {
3855 union tgsi_exec_channel r[3], sample_r;
3856 union tgsi_exec_channel value[4], value2[4];
3857 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
3858 float rgba2[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
3859 struct tgsi_image_params params;
3860 int dim;
3861 int sample;
3862 int i, j;
3863 uint unit, chan;
3864 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3865 unit = fetch_sampler_unit(mach, inst, 0);
3866 dim = get_image_coord_dim(inst->Memory.Texture);
3867 sample = get_image_coord_sample(inst->Memory.Texture);
3868 assert(dim <= 3);
3869
3870 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3871 params.unit = unit;
3872 params.tgsi_tex_instr = inst->Memory.Texture;
3873 params.format = inst->Memory.Format;
3874
3875 for (i = 0; i < dim; i++) {
3876 IFETCH(&r[i], 1, TGSI_CHAN_X + i);
3877 }
3878
3879 for (i = 0; i < 4; i++) {
3880 FETCH(&value[i], 2, TGSI_CHAN_X + i);
3881 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
3882 FETCH(&value2[i], 3, TGSI_CHAN_X + i);
3883 }
3884 if (sample)
3885 IFETCH(&sample_r, 1, TGSI_CHAN_X + sample);
3886
3887 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3888 rgba[0][j] = value[0].f[j];
3889 rgba[1][j] = value[1].f[j];
3890 rgba[2][j] = value[2].f[j];
3891 rgba[3][j] = value[3].f[j];
3892 }
3893 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
3894 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3895 rgba2[0][j] = value2[0].f[j];
3896 rgba2[1][j] = value2[1].f[j];
3897 rgba2[2][j] = value2[2].f[j];
3898 rgba2[3][j] = value2[3].f[j];
3899 }
3900 }
3901
3902 mach->Image->op(mach->Image, &params, inst->Instruction.Opcode,
3903 r[0].i, r[1].i, r[2].i, sample_r.i,
3904 rgba, rgba2);
3905
3906 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3907 r[0].f[j] = rgba[0][j];
3908 r[1].f[j] = rgba[1][j];
3909 r[2].f[j] = rgba[2][j];
3910 r[3].f[j] = rgba[3][j];
3911 }
3912 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3913 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3914 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3915 }
3916 }
3917 }
3918
3919 static void
3920 exec_resq(struct tgsi_exec_machine *mach,
3921 const struct tgsi_full_instruction *inst)
3922 {
3923 int result[4];
3924 union tgsi_exec_channel r[4];
3925 uint unit;
3926 int i, chan, j;
3927 struct tgsi_image_params params;
3928 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3929
3930 unit = fetch_sampler_unit(mach, inst, 0);
3931
3932 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3933 params.unit = unit;
3934 params.tgsi_tex_instr = inst->Memory.Texture;
3935 params.format = inst->Memory.Format;
3936
3937 mach->Image->get_dims(mach->Image, &params, result);
3938
3939 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
3940 for (j = 0; j < 4; j++) {
3941 r[j].i[i] = result[j];
3942 }
3943 }
3944
3945 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3946 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3947 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
3948 TGSI_EXEC_DATA_INT);
3949 }
3950 }
3951 }
3952
3953 static void
3954 micro_i2f(union tgsi_exec_channel *dst,
3955 const union tgsi_exec_channel *src)
3956 {
3957 dst->f[0] = (float)src->i[0];
3958 dst->f[1] = (float)src->i[1];
3959 dst->f[2] = (float)src->i[2];
3960 dst->f[3] = (float)src->i[3];
3961 }
3962
3963 static void
3964 micro_not(union tgsi_exec_channel *dst,
3965 const union tgsi_exec_channel *src)
3966 {
3967 dst->u[0] = ~src->u[0];
3968 dst->u[1] = ~src->u[1];
3969 dst->u[2] = ~src->u[2];
3970 dst->u[3] = ~src->u[3];
3971 }
3972
3973 static void
3974 micro_shl(union tgsi_exec_channel *dst,
3975 const union tgsi_exec_channel *src0,
3976 const union tgsi_exec_channel *src1)
3977 {
3978 unsigned masked_count;
3979 masked_count = src1->u[0] & 0x1f;
3980 dst->u[0] = src0->u[0] << masked_count;
3981 masked_count = src1->u[1] & 0x1f;
3982 dst->u[1] = src0->u[1] << masked_count;
3983 masked_count = src1->u[2] & 0x1f;
3984 dst->u[2] = src0->u[2] << masked_count;
3985 masked_count = src1->u[3] & 0x1f;
3986 dst->u[3] = src0->u[3] << masked_count;
3987 }
3988
3989 static void
3990 micro_and(union tgsi_exec_channel *dst,
3991 const union tgsi_exec_channel *src0,
3992 const union tgsi_exec_channel *src1)
3993 {
3994 dst->u[0] = src0->u[0] & src1->u[0];
3995 dst->u[1] = src0->u[1] & src1->u[1];
3996 dst->u[2] = src0->u[2] & src1->u[2];
3997 dst->u[3] = src0->u[3] & src1->u[3];
3998 }
3999
4000 static void
4001 micro_or(union tgsi_exec_channel *dst,
4002 const union tgsi_exec_channel *src0,
4003 const union tgsi_exec_channel *src1)
4004 {
4005 dst->u[0] = src0->u[0] | src1->u[0];
4006 dst->u[1] = src0->u[1] | src1->u[1];
4007 dst->u[2] = src0->u[2] | src1->u[2];
4008 dst->u[3] = src0->u[3] | src1->u[3];
4009 }
4010
4011 static void
4012 micro_xor(union tgsi_exec_channel *dst,
4013 const union tgsi_exec_channel *src0,
4014 const union tgsi_exec_channel *src1)
4015 {
4016 dst->u[0] = src0->u[0] ^ src1->u[0];
4017 dst->u[1] = src0->u[1] ^ src1->u[1];
4018 dst->u[2] = src0->u[2] ^ src1->u[2];
4019 dst->u[3] = src0->u[3] ^ src1->u[3];
4020 }
4021
4022 static void
4023 micro_mod(union tgsi_exec_channel *dst,
4024 const union tgsi_exec_channel *src0,
4025 const union tgsi_exec_channel *src1)
4026 {
4027 dst->i[0] = src0->i[0] % src1->i[0];
4028 dst->i[1] = src0->i[1] % src1->i[1];
4029 dst->i[2] = src0->i[2] % src1->i[2];
4030 dst->i[3] = src0->i[3] % src1->i[3];
4031 }
4032
4033 static void
4034 micro_f2i(union tgsi_exec_channel *dst,
4035 const union tgsi_exec_channel *src)
4036 {
4037 dst->i[0] = (int)src->f[0];
4038 dst->i[1] = (int)src->f[1];
4039 dst->i[2] = (int)src->f[2];
4040 dst->i[3] = (int)src->f[3];
4041 }
4042
4043 static void
4044 micro_fseq(union tgsi_exec_channel *dst,
4045 const union tgsi_exec_channel *src0,
4046 const union tgsi_exec_channel *src1)
4047 {
4048 dst->u[0] = src0->f[0] == src1->f[0] ? ~0 : 0;
4049 dst->u[1] = src0->f[1] == src1->f[1] ? ~0 : 0;
4050 dst->u[2] = src0->f[2] == src1->f[2] ? ~0 : 0;
4051 dst->u[3] = src0->f[3] == src1->f[3] ? ~0 : 0;
4052 }
4053
4054 static void
4055 micro_fsge(union tgsi_exec_channel *dst,
4056 const union tgsi_exec_channel *src0,
4057 const union tgsi_exec_channel *src1)
4058 {
4059 dst->u[0] = src0->f[0] >= src1->f[0] ? ~0 : 0;
4060 dst->u[1] = src0->f[1] >= src1->f[1] ? ~0 : 0;
4061 dst->u[2] = src0->f[2] >= src1->f[2] ? ~0 : 0;
4062 dst->u[3] = src0->f[3] >= src1->f[3] ? ~0 : 0;
4063 }
4064
4065 static void
4066 micro_fslt(union tgsi_exec_channel *dst,
4067 const union tgsi_exec_channel *src0,
4068 const union tgsi_exec_channel *src1)
4069 {
4070 dst->u[0] = src0->f[0] < src1->f[0] ? ~0 : 0;
4071 dst->u[1] = src0->f[1] < src1->f[1] ? ~0 : 0;
4072 dst->u[2] = src0->f[2] < src1->f[2] ? ~0 : 0;
4073 dst->u[3] = src0->f[3] < src1->f[3] ? ~0 : 0;
4074 }
4075
4076 static void
4077 micro_fsne(union tgsi_exec_channel *dst,
4078 const union tgsi_exec_channel *src0,
4079 const union tgsi_exec_channel *src1)
4080 {
4081 dst->u[0] = src0->f[0] != src1->f[0] ? ~0 : 0;
4082 dst->u[1] = src0->f[1] != src1->f[1] ? ~0 : 0;
4083 dst->u[2] = src0->f[2] != src1->f[2] ? ~0 : 0;
4084 dst->u[3] = src0->f[3] != src1->f[3] ? ~0 : 0;
4085 }
4086
4087 static void
4088 micro_idiv(union tgsi_exec_channel *dst,
4089 const union tgsi_exec_channel *src0,
4090 const union tgsi_exec_channel *src1)
4091 {
4092 dst->i[0] = src1->i[0] ? src0->i[0] / src1->i[0] : 0;
4093 dst->i[1] = src1->i[1] ? src0->i[1] / src1->i[1] : 0;
4094 dst->i[2] = src1->i[2] ? src0->i[2] / src1->i[2] : 0;
4095 dst->i[3] = src1->i[3] ? src0->i[3] / src1->i[3] : 0;
4096 }
4097
4098 static void
4099 micro_imax(union tgsi_exec_channel *dst,
4100 const union tgsi_exec_channel *src0,
4101 const union tgsi_exec_channel *src1)
4102 {
4103 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
4104 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
4105 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
4106 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
4107 }
4108
4109 static void
4110 micro_imin(union tgsi_exec_channel *dst,
4111 const union tgsi_exec_channel *src0,
4112 const union tgsi_exec_channel *src1)
4113 {
4114 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
4115 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
4116 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
4117 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
4118 }
4119
4120 static void
4121 micro_isge(union tgsi_exec_channel *dst,
4122 const union tgsi_exec_channel *src0,
4123 const union tgsi_exec_channel *src1)
4124 {
4125 dst->i[0] = src0->i[0] >= src1->i[0] ? -1 : 0;
4126 dst->i[1] = src0->i[1] >= src1->i[1] ? -1 : 0;
4127 dst->i[2] = src0->i[2] >= src1->i[2] ? -1 : 0;
4128 dst->i[3] = src0->i[3] >= src1->i[3] ? -1 : 0;
4129 }
4130
4131 static void
4132 micro_ishr(union tgsi_exec_channel *dst,
4133 const union tgsi_exec_channel *src0,
4134 const union tgsi_exec_channel *src1)
4135 {
4136 unsigned masked_count;
4137 masked_count = src1->i[0] & 0x1f;
4138 dst->i[0] = src0->i[0] >> masked_count;
4139 masked_count = src1->i[1] & 0x1f;
4140 dst->i[1] = src0->i[1] >> masked_count;
4141 masked_count = src1->i[2] & 0x1f;
4142 dst->i[2] = src0->i[2] >> masked_count;
4143 masked_count = src1->i[3] & 0x1f;
4144 dst->i[3] = src0->i[3] >> masked_count;
4145 }
4146
4147 static void
4148 micro_islt(union tgsi_exec_channel *dst,
4149 const union tgsi_exec_channel *src0,
4150 const union tgsi_exec_channel *src1)
4151 {
4152 dst->i[0] = src0->i[0] < src1->i[0] ? -1 : 0;
4153 dst->i[1] = src0->i[1] < src1->i[1] ? -1 : 0;
4154 dst->i[2] = src0->i[2] < src1->i[2] ? -1 : 0;
4155 dst->i[3] = src0->i[3] < src1->i[3] ? -1 : 0;
4156 }
4157
4158 static void
4159 micro_f2u(union tgsi_exec_channel *dst,
4160 const union tgsi_exec_channel *src)
4161 {
4162 dst->u[0] = (uint)src->f[0];
4163 dst->u[1] = (uint)src->f[1];
4164 dst->u[2] = (uint)src->f[2];
4165 dst->u[3] = (uint)src->f[3];
4166 }
4167
4168 static void
4169 micro_u2f(union tgsi_exec_channel *dst,
4170 const union tgsi_exec_channel *src)
4171 {
4172 dst->f[0] = (float)src->u[0];
4173 dst->f[1] = (float)src->u[1];
4174 dst->f[2] = (float)src->u[2];
4175 dst->f[3] = (float)src->u[3];
4176 }
4177
4178 static void
4179 micro_uadd(union tgsi_exec_channel *dst,
4180 const union tgsi_exec_channel *src0,
4181 const union tgsi_exec_channel *src1)
4182 {
4183 dst->u[0] = src0->u[0] + src1->u[0];
4184 dst->u[1] = src0->u[1] + src1->u[1];
4185 dst->u[2] = src0->u[2] + src1->u[2];
4186 dst->u[3] = src0->u[3] + src1->u[3];
4187 }
4188
4189 static void
4190 micro_udiv(union tgsi_exec_channel *dst,
4191 const union tgsi_exec_channel *src0,
4192 const union tgsi_exec_channel *src1)
4193 {
4194 dst->u[0] = src1->u[0] ? src0->u[0] / src1->u[0] : ~0u;
4195 dst->u[1] = src1->u[1] ? src0->u[1] / src1->u[1] : ~0u;
4196 dst->u[2] = src1->u[2] ? src0->u[2] / src1->u[2] : ~0u;
4197 dst->u[3] = src1->u[3] ? src0->u[3] / src1->u[3] : ~0u;
4198 }
4199
4200 static void
4201 micro_umad(union tgsi_exec_channel *dst,
4202 const union tgsi_exec_channel *src0,
4203 const union tgsi_exec_channel *src1,
4204 const union tgsi_exec_channel *src2)
4205 {
4206 dst->u[0] = src0->u[0] * src1->u[0] + src2->u[0];
4207 dst->u[1] = src0->u[1] * src1->u[1] + src2->u[1];
4208 dst->u[2] = src0->u[2] * src1->u[2] + src2->u[2];
4209 dst->u[3] = src0->u[3] * src1->u[3] + src2->u[3];
4210 }
4211
4212 static void
4213 micro_umax(union tgsi_exec_channel *dst,
4214 const union tgsi_exec_channel *src0,
4215 const union tgsi_exec_channel *src1)
4216 {
4217 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
4218 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
4219 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
4220 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
4221 }
4222
4223 static void
4224 micro_umin(union tgsi_exec_channel *dst,
4225 const union tgsi_exec_channel *src0,
4226 const union tgsi_exec_channel *src1)
4227 {
4228 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
4229 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
4230 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
4231 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
4232 }
4233
4234 static void
4235 micro_umod(union tgsi_exec_channel *dst,
4236 const union tgsi_exec_channel *src0,
4237 const union tgsi_exec_channel *src1)
4238 {
4239 dst->u[0] = src1->u[0] ? src0->u[0] % src1->u[0] : ~0u;
4240 dst->u[1] = src1->u[1] ? src0->u[1] % src1->u[1] : ~0u;
4241 dst->u[2] = src1->u[2] ? src0->u[2] % src1->u[2] : ~0u;
4242 dst->u[3] = src1->u[3] ? src0->u[3] % src1->u[3] : ~0u;
4243 }
4244
4245 static void
4246 micro_umul(union tgsi_exec_channel *dst,
4247 const union tgsi_exec_channel *src0,
4248 const union tgsi_exec_channel *src1)
4249 {
4250 dst->u[0] = src0->u[0] * src1->u[0];
4251 dst->u[1] = src0->u[1] * src1->u[1];
4252 dst->u[2] = src0->u[2] * src1->u[2];
4253 dst->u[3] = src0->u[3] * src1->u[3];
4254 }
4255
4256 static void
4257 micro_imul_hi(union tgsi_exec_channel *dst,
4258 const union tgsi_exec_channel *src0,
4259 const union tgsi_exec_channel *src1)
4260 {
4261 #define I64M(x, y) ((((int64_t)x) * ((int64_t)y)) >> 32)
4262 dst->i[0] = I64M(src0->i[0], src1->i[0]);
4263 dst->i[1] = I64M(src0->i[1], src1->i[1]);
4264 dst->i[2] = I64M(src0->i[2], src1->i[2]);
4265 dst->i[3] = I64M(src0->i[3], src1->i[3]);
4266 #undef I64M
4267 }
4268
4269 static void
4270 micro_umul_hi(union tgsi_exec_channel *dst,
4271 const union tgsi_exec_channel *src0,
4272 const union tgsi_exec_channel *src1)
4273 {
4274 #define U64M(x, y) ((((uint64_t)x) * ((uint64_t)y)) >> 32)
4275 dst->u[0] = U64M(src0->u[0], src1->u[0]);
4276 dst->u[1] = U64M(src0->u[1], src1->u[1]);
4277 dst->u[2] = U64M(src0->u[2], src1->u[2]);
4278 dst->u[3] = U64M(src0->u[3], src1->u[3]);
4279 #undef U64M
4280 }
4281
4282 static void
4283 micro_useq(union tgsi_exec_channel *dst,
4284 const union tgsi_exec_channel *src0,
4285 const union tgsi_exec_channel *src1)
4286 {
4287 dst->u[0] = src0->u[0] == src1->u[0] ? ~0 : 0;
4288 dst->u[1] = src0->u[1] == src1->u[1] ? ~0 : 0;
4289 dst->u[2] = src0->u[2] == src1->u[2] ? ~0 : 0;
4290 dst->u[3] = src0->u[3] == src1->u[3] ? ~0 : 0;
4291 }
4292
4293 static void
4294 micro_usge(union tgsi_exec_channel *dst,
4295 const union tgsi_exec_channel *src0,
4296 const union tgsi_exec_channel *src1)
4297 {
4298 dst->u[0] = src0->u[0] >= src1->u[0] ? ~0 : 0;
4299 dst->u[1] = src0->u[1] >= src1->u[1] ? ~0 : 0;
4300 dst->u[2] = src0->u[2] >= src1->u[2] ? ~0 : 0;
4301 dst->u[3] = src0->u[3] >= src1->u[3] ? ~0 : 0;
4302 }
4303
4304 static void
4305 micro_ushr(union tgsi_exec_channel *dst,
4306 const union tgsi_exec_channel *src0,
4307 const union tgsi_exec_channel *src1)
4308 {
4309 unsigned masked_count;
4310 masked_count = src1->u[0] & 0x1f;
4311 dst->u[0] = src0->u[0] >> masked_count;
4312 masked_count = src1->u[1] & 0x1f;
4313 dst->u[1] = src0->u[1] >> masked_count;
4314 masked_count = src1->u[2] & 0x1f;
4315 dst->u[2] = src0->u[2] >> masked_count;
4316 masked_count = src1->u[3] & 0x1f;
4317 dst->u[3] = src0->u[3] >> masked_count;
4318 }
4319
4320 static void
4321 micro_uslt(union tgsi_exec_channel *dst,
4322 const union tgsi_exec_channel *src0,
4323 const union tgsi_exec_channel *src1)
4324 {
4325 dst->u[0] = src0->u[0] < src1->u[0] ? ~0 : 0;
4326 dst->u[1] = src0->u[1] < src1->u[1] ? ~0 : 0;
4327 dst->u[2] = src0->u[2] < src1->u[2] ? ~0 : 0;
4328 dst->u[3] = src0->u[3] < src1->u[3] ? ~0 : 0;
4329 }
4330
4331 static void
4332 micro_usne(union tgsi_exec_channel *dst,
4333 const union tgsi_exec_channel *src0,
4334 const union tgsi_exec_channel *src1)
4335 {
4336 dst->u[0] = src0->u[0] != src1->u[0] ? ~0 : 0;
4337 dst->u[1] = src0->u[1] != src1->u[1] ? ~0 : 0;
4338 dst->u[2] = src0->u[2] != src1->u[2] ? ~0 : 0;
4339 dst->u[3] = src0->u[3] != src1->u[3] ? ~0 : 0;
4340 }
4341
4342 static void
4343 micro_uarl(union tgsi_exec_channel *dst,
4344 const union tgsi_exec_channel *src)
4345 {
4346 dst->i[0] = src->u[0];
4347 dst->i[1] = src->u[1];
4348 dst->i[2] = src->u[2];
4349 dst->i[3] = src->u[3];
4350 }
4351
4352 static void
4353 micro_ucmp(union tgsi_exec_channel *dst,
4354 const union tgsi_exec_channel *src0,
4355 const union tgsi_exec_channel *src1,
4356 const union tgsi_exec_channel *src2)
4357 {
4358 dst->u[0] = src0->u[0] ? src1->u[0] : src2->u[0];
4359 dst->u[1] = src0->u[1] ? src1->u[1] : src2->u[1];
4360 dst->u[2] = src0->u[2] ? src1->u[2] : src2->u[2];
4361 dst->u[3] = src0->u[3] ? src1->u[3] : src2->u[3];
4362 }
4363
4364 /**
4365 * Signed bitfield extract (i.e. sign-extend the extracted bits)
4366 */
4367 static void
4368 micro_ibfe(union tgsi_exec_channel *dst,
4369 const union tgsi_exec_channel *src0,
4370 const union tgsi_exec_channel *src1,
4371 const union tgsi_exec_channel *src2)
4372 {
4373 int i;
4374 for (i = 0; i < 4; i++) {
4375 int width = src2->i[i] & 0x1f;
4376 int offset = src1->i[i] & 0x1f;
4377 if (width == 0)
4378 dst->i[i] = 0;
4379 else if (width + offset < 32)
4380 dst->i[i] = (src0->i[i] << (32 - width - offset)) >> (32 - width);
4381 else
4382 dst->i[i] = src0->i[i] >> offset;
4383 }
4384 }
4385
4386 /**
4387 * Unsigned bitfield extract
4388 */
4389 static void
4390 micro_ubfe(union tgsi_exec_channel *dst,
4391 const union tgsi_exec_channel *src0,
4392 const union tgsi_exec_channel *src1,
4393 const union tgsi_exec_channel *src2)
4394 {
4395 int i;
4396 for (i = 0; i < 4; i++) {
4397 int width = src2->u[i] & 0x1f;
4398 int offset = src1->u[i] & 0x1f;
4399 if (width == 0)
4400 dst->u[i] = 0;
4401 else if (width + offset < 32)
4402 dst->u[i] = (src0->u[i] << (32 - width - offset)) >> (32 - width);
4403 else
4404 dst->u[i] = src0->u[i] >> offset;
4405 }
4406 }
4407
4408 /**
4409 * Bitfield insert: copy low bits from src1 into a region of src0.
4410 */
4411 static void
4412 micro_bfi(union tgsi_exec_channel *dst,
4413 const union tgsi_exec_channel *src0,
4414 const union tgsi_exec_channel *src1,
4415 const union tgsi_exec_channel *src2,
4416 const union tgsi_exec_channel *src3)
4417 {
4418 int i;
4419 for (i = 0; i < 4; i++) {
4420 int width = src3->u[i] & 0x1f;
4421 int offset = src2->u[i] & 0x1f;
4422 int bitmask = ((1 << width) - 1) << offset;
4423 dst->u[i] = ((src1->u[i] << offset) & bitmask) | (src0->u[i] & ~bitmask);
4424 }
4425 }
4426
4427 static void
4428 micro_brev(union tgsi_exec_channel *dst,
4429 const union tgsi_exec_channel *src)
4430 {
4431 dst->u[0] = util_bitreverse(src->u[0]);
4432 dst->u[1] = util_bitreverse(src->u[1]);
4433 dst->u[2] = util_bitreverse(src->u[2]);
4434 dst->u[3] = util_bitreverse(src->u[3]);
4435 }
4436
4437 static void
4438 micro_popc(union tgsi_exec_channel *dst,
4439 const union tgsi_exec_channel *src)
4440 {
4441 dst->u[0] = util_bitcount(src->u[0]);
4442 dst->u[1] = util_bitcount(src->u[1]);
4443 dst->u[2] = util_bitcount(src->u[2]);
4444 dst->u[3] = util_bitcount(src->u[3]);
4445 }
4446
4447 static void
4448 micro_lsb(union tgsi_exec_channel *dst,
4449 const union tgsi_exec_channel *src)
4450 {
4451 dst->i[0] = ffs(src->u[0]) - 1;
4452 dst->i[1] = ffs(src->u[1]) - 1;
4453 dst->i[2] = ffs(src->u[2]) - 1;
4454 dst->i[3] = ffs(src->u[3]) - 1;
4455 }
4456
4457 static void
4458 micro_imsb(union tgsi_exec_channel *dst,
4459 const union tgsi_exec_channel *src)
4460 {
4461 dst->i[0] = util_last_bit_signed(src->i[0]) - 1;
4462 dst->i[1] = util_last_bit_signed(src->i[1]) - 1;
4463 dst->i[2] = util_last_bit_signed(src->i[2]) - 1;
4464 dst->i[3] = util_last_bit_signed(src->i[3]) - 1;
4465 }
4466
4467 static void
4468 micro_umsb(union tgsi_exec_channel *dst,
4469 const union tgsi_exec_channel *src)
4470 {
4471 dst->i[0] = util_last_bit(src->u[0]) - 1;
4472 dst->i[1] = util_last_bit(src->u[1]) - 1;
4473 dst->i[2] = util_last_bit(src->u[2]) - 1;
4474 dst->i[3] = util_last_bit(src->u[3]) - 1;
4475 }
4476
4477 static void
4478 exec_instruction(
4479 struct tgsi_exec_machine *mach,
4480 const struct tgsi_full_instruction *inst,
4481 int *pc )
4482 {
4483 union tgsi_exec_channel r[10];
4484
4485 (*pc)++;
4486
4487 switch (inst->Instruction.Opcode) {
4488 case TGSI_OPCODE_ARL:
4489 exec_vector_unary(mach, inst, micro_arl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4490 break;
4491
4492 case TGSI_OPCODE_MOV:
4493 exec_vector_unary(mach, inst, micro_mov, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4494 break;
4495
4496 case TGSI_OPCODE_LIT:
4497 exec_lit(mach, inst);
4498 break;
4499
4500 case TGSI_OPCODE_RCP:
4501 exec_scalar_unary(mach, inst, micro_rcp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4502 break;
4503
4504 case TGSI_OPCODE_RSQ:
4505 exec_scalar_unary(mach, inst, micro_rsq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4506 break;
4507
4508 case TGSI_OPCODE_EXP:
4509 exec_exp(mach, inst);
4510 break;
4511
4512 case TGSI_OPCODE_LOG:
4513 exec_log(mach, inst);
4514 break;
4515
4516 case TGSI_OPCODE_MUL:
4517 exec_vector_binary(mach, inst, micro_mul, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4518 break;
4519
4520 case TGSI_OPCODE_ADD:
4521 exec_vector_binary(mach, inst, micro_add, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4522 break;
4523
4524 case TGSI_OPCODE_DP3:
4525 exec_dp3(mach, inst);
4526 break;
4527
4528 case TGSI_OPCODE_DP4:
4529 exec_dp4(mach, inst);
4530 break;
4531
4532 case TGSI_OPCODE_DST:
4533 exec_dst(mach, inst);
4534 break;
4535
4536 case TGSI_OPCODE_MIN:
4537 exec_vector_binary(mach, inst, micro_min, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4538 break;
4539
4540 case TGSI_OPCODE_MAX:
4541 exec_vector_binary(mach, inst, micro_max, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4542 break;
4543
4544 case TGSI_OPCODE_SLT:
4545 exec_vector_binary(mach, inst, micro_slt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4546 break;
4547
4548 case TGSI_OPCODE_SGE:
4549 exec_vector_binary(mach, inst, micro_sge, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4550 break;
4551
4552 case TGSI_OPCODE_MAD:
4553 exec_vector_trinary(mach, inst, micro_mad, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4554 break;
4555
4556 case TGSI_OPCODE_SUB:
4557 exec_vector_binary(mach, inst, micro_sub, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4558 break;
4559
4560 case TGSI_OPCODE_LRP:
4561 exec_vector_trinary(mach, inst, micro_lrp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4562 break;
4563
4564 case TGSI_OPCODE_SQRT:
4565 exec_scalar_unary(mach, inst, micro_sqrt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4566 break;
4567
4568 case TGSI_OPCODE_DP2A:
4569 exec_dp2a(mach, inst);
4570 break;
4571
4572 case TGSI_OPCODE_FRC:
4573 exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4574 break;
4575
4576 case TGSI_OPCODE_CLAMP:
4577 exec_vector_trinary(mach, inst, micro_clamp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4578 break;
4579
4580 case TGSI_OPCODE_FLR:
4581 exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4582 break;
4583
4584 case TGSI_OPCODE_ROUND:
4585 exec_vector_unary(mach, inst, micro_rnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4586 break;
4587
4588 case TGSI_OPCODE_EX2:
4589 exec_scalar_unary(mach, inst, micro_exp2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4590 break;
4591
4592 case TGSI_OPCODE_LG2:
4593 exec_scalar_unary(mach, inst, micro_lg2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4594 break;
4595
4596 case TGSI_OPCODE_POW:
4597 exec_scalar_binary(mach, inst, micro_pow, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4598 break;
4599
4600 case TGSI_OPCODE_XPD:
4601 exec_xpd(mach, inst);
4602 break;
4603
4604 case TGSI_OPCODE_ABS:
4605 exec_vector_unary(mach, inst, micro_abs, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4606 break;
4607
4608 case TGSI_OPCODE_DPH:
4609 exec_dph(mach, inst);
4610 break;
4611
4612 case TGSI_OPCODE_COS:
4613 exec_scalar_unary(mach, inst, micro_cos, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4614 break;
4615
4616 case TGSI_OPCODE_DDX:
4617 exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4618 break;
4619
4620 case TGSI_OPCODE_DDY:
4621 exec_vector_unary(mach, inst, micro_ddy, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4622 break;
4623
4624 case TGSI_OPCODE_KILL:
4625 exec_kill (mach, inst);
4626 break;
4627
4628 case TGSI_OPCODE_KILL_IF:
4629 exec_kill_if (mach, inst);
4630 break;
4631
4632 case TGSI_OPCODE_PK2H:
4633 exec_pk2h(mach, inst);
4634 break;
4635
4636 case TGSI_OPCODE_PK2US:
4637 assert (0);
4638 break;
4639
4640 case TGSI_OPCODE_PK4B:
4641 assert (0);
4642 break;
4643
4644 case TGSI_OPCODE_PK4UB:
4645 assert (0);
4646 break;
4647
4648 case TGSI_OPCODE_SEQ:
4649 exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4650 break;
4651
4652 case TGSI_OPCODE_SGT:
4653 exec_vector_binary(mach, inst, micro_sgt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4654 break;
4655
4656 case TGSI_OPCODE_SIN:
4657 exec_scalar_unary(mach, inst, micro_sin, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4658 break;
4659
4660 case TGSI_OPCODE_SLE:
4661 exec_vector_binary(mach, inst, micro_sle, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4662 break;
4663
4664 case TGSI_OPCODE_SNE:
4665 exec_vector_binary(mach, inst, micro_sne, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4666 break;
4667
4668 case TGSI_OPCODE_TEX:
4669 /* simple texture lookup */
4670 /* src[0] = texcoord */
4671 /* src[1] = sampler unit */
4672 exec_tex(mach, inst, TEX_MODIFIER_NONE, 1);
4673 break;
4674
4675 case TGSI_OPCODE_TXB:
4676 /* Texture lookup with lod bias */
4677 /* src[0] = texcoord (src[0].w = LOD bias) */
4678 /* src[1] = sampler unit */
4679 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 1);
4680 break;
4681
4682 case TGSI_OPCODE_TXD:
4683 /* Texture lookup with explict partial derivatives */
4684 /* src[0] = texcoord */
4685 /* src[1] = d[strq]/dx */
4686 /* src[2] = d[strq]/dy */
4687 /* src[3] = sampler unit */
4688 exec_txd(mach, inst);
4689 break;
4690
4691 case TGSI_OPCODE_TXL:
4692 /* Texture lookup with explit LOD */
4693 /* src[0] = texcoord (src[0].w = LOD) */
4694 /* src[1] = sampler unit */
4695 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 1);
4696 break;
4697
4698 case TGSI_OPCODE_TXP:
4699 /* Texture lookup with projection */
4700 /* src[0] = texcoord (src[0].w = projection) */
4701 /* src[1] = sampler unit */
4702 exec_tex(mach, inst, TEX_MODIFIER_PROJECTED, 1);
4703 break;
4704
4705 case TGSI_OPCODE_TG4:
4706 /* src[0] = texcoord */
4707 /* src[1] = component */
4708 /* src[2] = sampler unit */
4709 exec_tex(mach, inst, TEX_MODIFIER_GATHER, 2);
4710 break;
4711
4712 case TGSI_OPCODE_LODQ:
4713 /* src[0] = texcoord */
4714 /* src[1] = sampler unit */
4715 exec_lodq(mach, inst);
4716 break;
4717
4718 case TGSI_OPCODE_UP2H:
4719 exec_up2h(mach, inst);
4720 break;
4721
4722 case TGSI_OPCODE_UP2US:
4723 assert (0);
4724 break;
4725
4726 case TGSI_OPCODE_UP4B:
4727 assert (0);
4728 break;
4729
4730 case TGSI_OPCODE_UP4UB:
4731 assert (0);
4732 break;
4733
4734 case TGSI_OPCODE_ARR:
4735 exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4736 break;
4737
4738 case TGSI_OPCODE_CAL:
4739 /* skip the call if no execution channels are enabled */
4740 if (mach->ExecMask) {
4741 /* do the call */
4742
4743 /* First, record the depths of the execution stacks.
4744 * This is important for deeply nested/looped return statements.
4745 * We have to unwind the stacks by the correct amount. For a
4746 * real code generator, we could determine the number of entries
4747 * to pop off each stack with simple static analysis and avoid
4748 * implementing this data structure at run time.
4749 */
4750 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
4751 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
4752 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
4753 mach->CallStack[mach->CallStackTop].SwitchStackTop = mach->SwitchStackTop;
4754 mach->CallStack[mach->CallStackTop].BreakStackTop = mach->BreakStackTop;
4755 /* note that PC was already incremented above */
4756 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
4757
4758 mach->CallStackTop++;
4759
4760 /* Second, push the Cond, Loop, Cont, Func stacks */
4761 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
4762 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4763 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4764 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
4765 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
4766 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
4767
4768 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
4769 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
4770 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
4771 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
4772 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
4773 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
4774
4775 /* Finally, jump to the subroutine. The label is a pointer
4776 * (an instruction number) to the BGNSUB instruction.
4777 */
4778 *pc = inst->Label.Label;
4779 assert(mach->Instructions[*pc].Instruction.Opcode
4780 == TGSI_OPCODE_BGNSUB);
4781 }
4782 break;
4783
4784 case TGSI_OPCODE_RET:
4785 mach->FuncMask &= ~mach->ExecMask;
4786 UPDATE_EXEC_MASK(mach);
4787
4788 if (mach->FuncMask == 0x0) {
4789 /* really return now (otherwise, keep executing */
4790
4791 if (mach->CallStackTop == 0) {
4792 /* returning from main() */
4793 mach->CondStackTop = 0;
4794 mach->LoopStackTop = 0;
4795 *pc = -1;
4796 return;
4797 }
4798
4799 assert(mach->CallStackTop > 0);
4800 mach->CallStackTop--;
4801
4802 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
4803 mach->CondMask = mach->CondStack[mach->CondStackTop];
4804
4805 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
4806 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
4807
4808 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
4809 mach->ContMask = mach->ContStack[mach->ContStackTop];
4810
4811 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
4812 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
4813
4814 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
4815 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
4816
4817 assert(mach->FuncStackTop > 0);
4818 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
4819
4820 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
4821
4822 UPDATE_EXEC_MASK(mach);
4823 }
4824 break;
4825
4826 case TGSI_OPCODE_SSG:
4827 exec_vector_unary(mach, inst, micro_sgn, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4828 break;
4829
4830 case TGSI_OPCODE_CMP:
4831 exec_vector_trinary(mach, inst, micro_cmp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4832 break;
4833
4834 case TGSI_OPCODE_SCS:
4835 exec_scs(mach, inst);
4836 break;
4837
4838 case TGSI_OPCODE_DIV:
4839 exec_vector_binary(mach, inst, micro_div, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4840 break;
4841
4842 case TGSI_OPCODE_DP2:
4843 exec_dp2(mach, inst);
4844 break;
4845
4846 case TGSI_OPCODE_IF:
4847 /* push CondMask */
4848 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
4849 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
4850 FETCH( &r[0], 0, TGSI_CHAN_X );
4851 /* update CondMask */
4852 if( ! r[0].f[0] ) {
4853 mach->CondMask &= ~0x1;
4854 }
4855 if( ! r[0].f[1] ) {
4856 mach->CondMask &= ~0x2;
4857 }
4858 if( ! r[0].f[2] ) {
4859 mach->CondMask &= ~0x4;
4860 }
4861 if( ! r[0].f[3] ) {
4862 mach->CondMask &= ~0x8;
4863 }
4864 UPDATE_EXEC_MASK(mach);
4865 /* Todo: If CondMask==0, jump to ELSE */
4866 break;
4867
4868 case TGSI_OPCODE_UIF:
4869 /* push CondMask */
4870 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
4871 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
4872 IFETCH( &r[0], 0, TGSI_CHAN_X );
4873 /* update CondMask */
4874 if( ! r[0].u[0] ) {
4875 mach->CondMask &= ~0x1;
4876 }
4877 if( ! r[0].u[1] ) {
4878 mach->CondMask &= ~0x2;
4879 }
4880 if( ! r[0].u[2] ) {
4881 mach->CondMask &= ~0x4;
4882 }
4883 if( ! r[0].u[3] ) {
4884 mach->CondMask &= ~0x8;
4885 }
4886 UPDATE_EXEC_MASK(mach);
4887 /* Todo: If CondMask==0, jump to ELSE */
4888 break;
4889
4890 case TGSI_OPCODE_ELSE:
4891 /* invert CondMask wrt previous mask */
4892 {
4893 uint prevMask;
4894 assert(mach->CondStackTop > 0);
4895 prevMask = mach->CondStack[mach->CondStackTop - 1];
4896 mach->CondMask = ~mach->CondMask & prevMask;
4897 UPDATE_EXEC_MASK(mach);
4898 /* Todo: If CondMask==0, jump to ENDIF */
4899 }
4900 break;
4901
4902 case TGSI_OPCODE_ENDIF:
4903 /* pop CondMask */
4904 assert(mach->CondStackTop > 0);
4905 mach->CondMask = mach->CondStack[--mach->CondStackTop];
4906 UPDATE_EXEC_MASK(mach);
4907 break;
4908
4909 case TGSI_OPCODE_END:
4910 /* make sure we end primitives which haven't
4911 * been explicitly emitted */
4912 conditional_emit_primitive(mach);
4913 /* halt execution */
4914 *pc = -1;
4915 break;
4916
4917 case TGSI_OPCODE_PUSHA:
4918 assert (0);
4919 break;
4920
4921 case TGSI_OPCODE_POPA:
4922 assert (0);
4923 break;
4924
4925 case TGSI_OPCODE_CEIL:
4926 exec_vector_unary(mach, inst, micro_ceil, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4927 break;
4928
4929 case TGSI_OPCODE_I2F:
4930 exec_vector_unary(mach, inst, micro_i2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
4931 break;
4932
4933 case TGSI_OPCODE_NOT:
4934 exec_vector_unary(mach, inst, micro_not, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4935 break;
4936
4937 case TGSI_OPCODE_TRUNC:
4938 exec_vector_unary(mach, inst, micro_trunc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4939 break;
4940
4941 case TGSI_OPCODE_SHL:
4942 exec_vector_binary(mach, inst, micro_shl, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4943 break;
4944
4945 case TGSI_OPCODE_AND:
4946 exec_vector_binary(mach, inst, micro_and, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4947 break;
4948
4949 case TGSI_OPCODE_OR:
4950 exec_vector_binary(mach, inst, micro_or, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4951 break;
4952
4953 case TGSI_OPCODE_MOD:
4954 exec_vector_binary(mach, inst, micro_mod, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4955 break;
4956
4957 case TGSI_OPCODE_XOR:
4958 exec_vector_binary(mach, inst, micro_xor, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4959 break;
4960
4961 case TGSI_OPCODE_SAD:
4962 assert (0);
4963 break;
4964
4965 case TGSI_OPCODE_TXF:
4966 exec_txf(mach, inst);
4967 break;
4968
4969 case TGSI_OPCODE_TXQ:
4970 exec_txq(mach, inst);
4971 break;
4972
4973 case TGSI_OPCODE_EMIT:
4974 emit_vertex(mach);
4975 break;
4976
4977 case TGSI_OPCODE_ENDPRIM:
4978 emit_primitive(mach);
4979 break;
4980
4981 case TGSI_OPCODE_BGNLOOP:
4982 /* push LoopMask and ContMasks */
4983 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4984 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4985 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4986 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
4987
4988 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
4989 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
4990 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
4991 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
4992 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_LOOP;
4993 break;
4994
4995 case TGSI_OPCODE_ENDLOOP:
4996 /* Restore ContMask, but don't pop */
4997 assert(mach->ContStackTop > 0);
4998 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
4999 UPDATE_EXEC_MASK(mach);
5000 if (mach->ExecMask) {
5001 /* repeat loop: jump to instruction just past BGNLOOP */
5002 assert(mach->LoopLabelStackTop > 0);
5003 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
5004 }
5005 else {
5006 /* exit loop: pop LoopMask */
5007 assert(mach->LoopStackTop > 0);
5008 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
5009 /* pop ContMask */
5010 assert(mach->ContStackTop > 0);
5011 mach->ContMask = mach->ContStack[--mach->ContStackTop];
5012 assert(mach->LoopLabelStackTop > 0);
5013 --mach->LoopLabelStackTop;
5014
5015 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
5016 }
5017 UPDATE_EXEC_MASK(mach);
5018 break;
5019
5020 case TGSI_OPCODE_BRK:
5021 exec_break(mach);
5022 break;
5023
5024 case TGSI_OPCODE_CONT:
5025 /* turn off cont channels for each enabled exec channel */
5026 mach->ContMask &= ~mach->ExecMask;
5027 /* Todo: if mach->LoopMask == 0, jump to end of loop */
5028 UPDATE_EXEC_MASK(mach);
5029 break;
5030
5031 case TGSI_OPCODE_BGNSUB:
5032 /* no-op */
5033 break;
5034
5035 case TGSI_OPCODE_ENDSUB:
5036 /*
5037 * XXX: This really should be a no-op. We should never reach this opcode.
5038 */
5039
5040 assert(mach->CallStackTop > 0);
5041 mach->CallStackTop--;
5042
5043 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
5044 mach->CondMask = mach->CondStack[mach->CondStackTop];
5045
5046 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
5047 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
5048
5049 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
5050 mach->ContMask = mach->ContStack[mach->ContStackTop];
5051
5052 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
5053 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
5054
5055 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
5056 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
5057
5058 assert(mach->FuncStackTop > 0);
5059 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
5060
5061 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
5062
5063 UPDATE_EXEC_MASK(mach);
5064 break;
5065
5066 case TGSI_OPCODE_NOP:
5067 break;
5068
5069 case TGSI_OPCODE_BREAKC:
5070 IFETCH(&r[0], 0, TGSI_CHAN_X);
5071 /* update CondMask */
5072 if (r[0].u[0] && (mach->ExecMask & 0x1)) {
5073 mach->LoopMask &= ~0x1;
5074 }
5075 if (r[0].u[1] && (mach->ExecMask & 0x2)) {
5076 mach->LoopMask &= ~0x2;
5077 }
5078 if (r[0].u[2] && (mach->ExecMask & 0x4)) {
5079 mach->LoopMask &= ~0x4;
5080 }
5081 if (r[0].u[3] && (mach->ExecMask & 0x8)) {
5082 mach->LoopMask &= ~0x8;
5083 }
5084 /* Todo: if mach->LoopMask == 0, jump to end of loop */
5085 UPDATE_EXEC_MASK(mach);
5086 break;
5087
5088 case TGSI_OPCODE_F2I:
5089 exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
5090 break;
5091
5092 case TGSI_OPCODE_FSEQ:
5093 exec_vector_binary(mach, inst, micro_fseq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5094 break;
5095
5096 case TGSI_OPCODE_FSGE:
5097 exec_vector_binary(mach, inst, micro_fsge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5098 break;
5099
5100 case TGSI_OPCODE_FSLT:
5101 exec_vector_binary(mach, inst, micro_fslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5102 break;
5103
5104 case TGSI_OPCODE_FSNE:
5105 exec_vector_binary(mach, inst, micro_fsne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5106 break;
5107
5108 case TGSI_OPCODE_IDIV:
5109 exec_vector_binary(mach, inst, micro_idiv, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5110 break;
5111
5112 case TGSI_OPCODE_IMAX:
5113 exec_vector_binary(mach, inst, micro_imax, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5114 break;
5115
5116 case TGSI_OPCODE_IMIN:
5117 exec_vector_binary(mach, inst, micro_imin, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5118 break;
5119
5120 case TGSI_OPCODE_INEG:
5121 exec_vector_unary(mach, inst, micro_ineg, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5122 break;
5123
5124 case TGSI_OPCODE_ISGE:
5125 exec_vector_binary(mach, inst, micro_isge, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5126 break;
5127
5128 case TGSI_OPCODE_ISHR:
5129 exec_vector_binary(mach, inst, micro_ishr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5130 break;
5131
5132 case TGSI_OPCODE_ISLT:
5133 exec_vector_binary(mach, inst, micro_islt, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5134 break;
5135
5136 case TGSI_OPCODE_F2U:
5137 exec_vector_unary(mach, inst, micro_f2u, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5138 break;
5139
5140 case TGSI_OPCODE_U2F:
5141 exec_vector_unary(mach, inst, micro_u2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_UINT);
5142 break;
5143
5144 case TGSI_OPCODE_UADD:
5145 exec_vector_binary(mach, inst, micro_uadd, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5146 break;
5147
5148 case TGSI_OPCODE_UDIV:
5149 exec_vector_binary(mach, inst, micro_udiv, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5150 break;
5151
5152 case TGSI_OPCODE_UMAD:
5153 exec_vector_trinary(mach, inst, micro_umad, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5154 break;
5155
5156 case TGSI_OPCODE_UMAX:
5157 exec_vector_binary(mach, inst, micro_umax, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5158 break;
5159
5160 case TGSI_OPCODE_UMIN:
5161 exec_vector_binary(mach, inst, micro_umin, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5162 break;
5163
5164 case TGSI_OPCODE_UMOD:
5165 exec_vector_binary(mach, inst, micro_umod, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5166 break;
5167
5168 case TGSI_OPCODE_UMUL:
5169 exec_vector_binary(mach, inst, micro_umul, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5170 break;
5171
5172 case TGSI_OPCODE_IMUL_HI:
5173 exec_vector_binary(mach, inst, micro_imul_hi, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5174 break;
5175
5176 case TGSI_OPCODE_UMUL_HI:
5177 exec_vector_binary(mach, inst, micro_umul_hi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5178 break;
5179
5180 case TGSI_OPCODE_USEQ:
5181 exec_vector_binary(mach, inst, micro_useq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5182 break;
5183
5184 case TGSI_OPCODE_USGE:
5185 exec_vector_binary(mach, inst, micro_usge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5186 break;
5187
5188 case TGSI_OPCODE_USHR:
5189 exec_vector_binary(mach, inst, micro_ushr, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5190 break;
5191
5192 case TGSI_OPCODE_USLT:
5193 exec_vector_binary(mach, inst, micro_uslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5194 break;
5195
5196 case TGSI_OPCODE_USNE:
5197 exec_vector_binary(mach, inst, micro_usne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5198 break;
5199
5200 case TGSI_OPCODE_SWITCH:
5201 exec_switch(mach, inst);
5202 break;
5203
5204 case TGSI_OPCODE_CASE:
5205 exec_case(mach, inst);
5206 break;
5207
5208 case TGSI_OPCODE_DEFAULT:
5209 exec_default(mach);
5210 break;
5211
5212 case TGSI_OPCODE_ENDSWITCH:
5213 exec_endswitch(mach);
5214 break;
5215
5216 case TGSI_OPCODE_SAMPLE_I:
5217 exec_txf(mach, inst);
5218 break;
5219
5220 case TGSI_OPCODE_SAMPLE_I_MS:
5221 exec_txf(mach, inst);
5222 break;
5223
5224 case TGSI_OPCODE_SAMPLE:
5225 exec_sample(mach, inst, TEX_MODIFIER_NONE, FALSE);
5226 break;
5227
5228 case TGSI_OPCODE_SAMPLE_B:
5229 exec_sample(mach, inst, TEX_MODIFIER_LOD_BIAS, FALSE);
5230 break;
5231
5232 case TGSI_OPCODE_SAMPLE_C:
5233 exec_sample(mach, inst, TEX_MODIFIER_NONE, TRUE);
5234 break;
5235
5236 case TGSI_OPCODE_SAMPLE_C_LZ:
5237 exec_sample(mach, inst, TEX_MODIFIER_LEVEL_ZERO, TRUE);
5238 break;
5239
5240 case TGSI_OPCODE_SAMPLE_D:
5241 exec_sample_d(mach, inst);
5242 break;
5243
5244 case TGSI_OPCODE_SAMPLE_L:
5245 exec_sample(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, FALSE);
5246 break;
5247
5248 case TGSI_OPCODE_GATHER4:
5249 assert(0);
5250 break;
5251
5252 case TGSI_OPCODE_SVIEWINFO:
5253 exec_txq(mach, inst);
5254 break;
5255
5256 case TGSI_OPCODE_SAMPLE_POS:
5257 assert(0);
5258 break;
5259
5260 case TGSI_OPCODE_SAMPLE_INFO:
5261 assert(0);
5262 break;
5263
5264 case TGSI_OPCODE_UARL:
5265 exec_vector_unary(mach, inst, micro_uarl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
5266 break;
5267
5268 case TGSI_OPCODE_UCMP:
5269 exec_vector_trinary(mach, inst, micro_ucmp, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5270 break;
5271
5272 case TGSI_OPCODE_IABS:
5273 exec_vector_unary(mach, inst, micro_iabs, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5274 break;
5275
5276 case TGSI_OPCODE_ISSG:
5277 exec_vector_unary(mach, inst, micro_isgn, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5278 break;
5279
5280 case TGSI_OPCODE_TEX2:
5281 /* simple texture lookup */
5282 /* src[0] = texcoord */
5283 /* src[1] = compare */
5284 /* src[2] = sampler unit */
5285 exec_tex(mach, inst, TEX_MODIFIER_NONE, 2);
5286 break;
5287 case TGSI_OPCODE_TXB2:
5288 /* simple texture lookup */
5289 /* src[0] = texcoord */
5290 /* src[1] = bias */
5291 /* src[2] = sampler unit */
5292 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 2);
5293 break;
5294 case TGSI_OPCODE_TXL2:
5295 /* simple texture lookup */
5296 /* src[0] = texcoord */
5297 /* src[1] = lod */
5298 /* src[2] = sampler unit */
5299 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 2);
5300 break;
5301
5302 case TGSI_OPCODE_IBFE:
5303 exec_vector_trinary(mach, inst, micro_ibfe, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5304 break;
5305 case TGSI_OPCODE_UBFE:
5306 exec_vector_trinary(mach, inst, micro_ubfe, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5307 break;
5308 case TGSI_OPCODE_BFI:
5309 exec_vector_quaternary(mach, inst, micro_bfi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5310 break;
5311 case TGSI_OPCODE_BREV:
5312 exec_vector_unary(mach, inst, micro_brev, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5313 break;
5314 case TGSI_OPCODE_POPC:
5315 exec_vector_unary(mach, inst, micro_popc, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5316 break;
5317 case TGSI_OPCODE_LSB:
5318 exec_vector_unary(mach, inst, micro_lsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
5319 break;
5320 case TGSI_OPCODE_IMSB:
5321 exec_vector_unary(mach, inst, micro_imsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5322 break;
5323 case TGSI_OPCODE_UMSB:
5324 exec_vector_unary(mach, inst, micro_umsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
5325 break;
5326
5327 case TGSI_OPCODE_F2D:
5328 exec_f2d(mach, inst);
5329 break;
5330
5331 case TGSI_OPCODE_D2F:
5332 exec_d2f(mach, inst);
5333 break;
5334
5335 case TGSI_OPCODE_DABS:
5336 exec_double_unary(mach, inst, micro_dabs);
5337 break;
5338
5339 case TGSI_OPCODE_DNEG:
5340 exec_double_unary(mach, inst, micro_dneg);
5341 break;
5342
5343 case TGSI_OPCODE_DADD:
5344 exec_double_binary(mach, inst, micro_dadd, TGSI_EXEC_DATA_DOUBLE);
5345 break;
5346
5347 case TGSI_OPCODE_DMUL:
5348 exec_double_binary(mach, inst, micro_dmul, TGSI_EXEC_DATA_DOUBLE);
5349 break;
5350
5351 case TGSI_OPCODE_DMAX:
5352 exec_double_binary(mach, inst, micro_dmax, TGSI_EXEC_DATA_DOUBLE);
5353 break;
5354
5355 case TGSI_OPCODE_DMIN:
5356 exec_double_binary(mach, inst, micro_dmin, TGSI_EXEC_DATA_DOUBLE);
5357 break;
5358
5359 case TGSI_OPCODE_DSLT:
5360 exec_double_binary(mach, inst, micro_dslt, TGSI_EXEC_DATA_UINT);
5361 break;
5362
5363 case TGSI_OPCODE_DSGE:
5364 exec_double_binary(mach, inst, micro_dsge, TGSI_EXEC_DATA_UINT);
5365 break;
5366
5367 case TGSI_OPCODE_DSEQ:
5368 exec_double_binary(mach, inst, micro_dseq, TGSI_EXEC_DATA_UINT);
5369 break;
5370
5371 case TGSI_OPCODE_DSNE:
5372 exec_double_binary(mach, inst, micro_dsne, TGSI_EXEC_DATA_UINT);
5373 break;
5374
5375 case TGSI_OPCODE_DRCP:
5376 exec_double_unary(mach, inst, micro_drcp);
5377 break;
5378
5379 case TGSI_OPCODE_DSQRT:
5380 exec_double_unary(mach, inst, micro_dsqrt);
5381 break;
5382
5383 case TGSI_OPCODE_DRSQ:
5384 exec_double_unary(mach, inst, micro_drsq);
5385 break;
5386
5387 case TGSI_OPCODE_DMAD:
5388 exec_double_trinary(mach, inst, micro_dmad);
5389 break;
5390
5391 case TGSI_OPCODE_DFRAC:
5392 exec_double_unary(mach, inst, micro_dfrac);
5393 break;
5394
5395 case TGSI_OPCODE_DLDEXP:
5396 exec_dldexp(mach, inst);
5397 break;
5398
5399 case TGSI_OPCODE_DFRACEXP:
5400 exec_dfracexp(mach, inst);
5401 break;
5402
5403 case TGSI_OPCODE_I2D:
5404 exec_i2d(mach, inst);
5405 break;
5406
5407 case TGSI_OPCODE_D2I:
5408 exec_d2i(mach, inst);
5409 break;
5410
5411 case TGSI_OPCODE_U2D:
5412 exec_u2d(mach, inst);
5413 break;
5414
5415 case TGSI_OPCODE_D2U:
5416 exec_d2u(mach, inst);
5417 break;
5418
5419 case TGSI_OPCODE_LOAD:
5420 exec_load(mach, inst);
5421 break;
5422
5423 case TGSI_OPCODE_STORE:
5424 exec_store(mach, inst);
5425 break;
5426
5427 case TGSI_OPCODE_ATOMUADD:
5428 case TGSI_OPCODE_ATOMXCHG:
5429 case TGSI_OPCODE_ATOMCAS:
5430 case TGSI_OPCODE_ATOMAND:
5431 case TGSI_OPCODE_ATOMOR:
5432 case TGSI_OPCODE_ATOMXOR:
5433 case TGSI_OPCODE_ATOMUMIN:
5434 case TGSI_OPCODE_ATOMUMAX:
5435 case TGSI_OPCODE_ATOMIMIN:
5436 case TGSI_OPCODE_ATOMIMAX:
5437 exec_atomop(mach, inst);
5438 break;
5439
5440 case TGSI_OPCODE_RESQ:
5441 exec_resq(mach, inst);
5442 break;
5443 case TGSI_OPCODE_BARRIER:
5444 case TGSI_OPCODE_MEMBAR:
5445 break;
5446 default:
5447 assert( 0 );
5448 }
5449 }
5450
5451
5452 /**
5453 * Run TGSI interpreter.
5454 * \return bitmask of "alive" quad components
5455 */
5456 uint
5457 tgsi_exec_machine_run( struct tgsi_exec_machine *mach )
5458 {
5459 uint i;
5460 int pc = 0;
5461 uint default_mask = 0xf;
5462
5463 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
5464 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
5465
5466 if( mach->Processor == TGSI_PROCESSOR_GEOMETRY ) {
5467 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
5468 mach->Primitives[0] = 0;
5469 /* GS runs on a single primitive for now */
5470 default_mask = 0x1;
5471 }
5472
5473 if (mach->NonHelperMask == 0)
5474 mach->NonHelperMask = default_mask;
5475 mach->CondMask = default_mask;
5476 mach->LoopMask = default_mask;
5477 mach->ContMask = default_mask;
5478 mach->FuncMask = default_mask;
5479 mach->ExecMask = default_mask;
5480
5481 mach->Switch.mask = default_mask;
5482
5483 assert(mach->CondStackTop == 0);
5484 assert(mach->LoopStackTop == 0);
5485 assert(mach->ContStackTop == 0);
5486 assert(mach->SwitchStackTop == 0);
5487 assert(mach->BreakStackTop == 0);
5488 assert(mach->CallStackTop == 0);
5489
5490
5491 /* execute declarations (interpolants) */
5492 for (i = 0; i < mach->NumDeclarations; i++) {
5493 exec_declaration( mach, mach->Declarations+i );
5494 }
5495
5496 {
5497 #if DEBUG_EXECUTION
5498 struct tgsi_exec_vector temps[TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS];
5499 struct tgsi_exec_vector outputs[PIPE_MAX_ATTRIBS];
5500 uint inst = 1;
5501
5502 memset(mach->Temps, 0, sizeof(temps));
5503 memset(mach->Outputs, 0, sizeof(outputs));
5504 memset(temps, 0, sizeof(temps));
5505 memset(outputs, 0, sizeof(outputs));
5506 #endif
5507
5508 /* execute instructions, until pc is set to -1 */
5509 while (pc != -1) {
5510
5511 #if DEBUG_EXECUTION
5512 uint i;
5513
5514 tgsi_dump_instruction(&mach->Instructions[pc], inst++);
5515 #endif
5516
5517 assert(pc < (int) mach->NumInstructions);
5518 exec_instruction(mach, mach->Instructions + pc, &pc);
5519
5520 #if DEBUG_EXECUTION
5521 for (i = 0; i < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS; i++) {
5522 if (memcmp(&temps[i], &mach->Temps[i], sizeof(temps[i]))) {
5523 uint j;
5524
5525 memcpy(&temps[i], &mach->Temps[i], sizeof(temps[i]));
5526 debug_printf("TEMP[%2u] = ", i);
5527 for (j = 0; j < 4; j++) {
5528 if (j > 0) {
5529 debug_printf(" ");
5530 }
5531 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
5532 temps[i].xyzw[0].f[j], temps[i].xyzw[0].u[j],
5533 temps[i].xyzw[1].f[j], temps[i].xyzw[1].u[j],
5534 temps[i].xyzw[2].f[j], temps[i].xyzw[2].u[j],
5535 temps[i].xyzw[3].f[j], temps[i].xyzw[3].u[j]);
5536 }
5537 }
5538 }
5539 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
5540 if (memcmp(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]))) {
5541 uint j;
5542
5543 memcpy(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]));
5544 debug_printf("OUT[%2u] = ", i);
5545 for (j = 0; j < 4; j++) {
5546 if (j > 0) {
5547 debug_printf(" ");
5548 }
5549 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
5550 outputs[i].xyzw[0].f[j], outputs[i].xyzw[0].u[j],
5551 outputs[i].xyzw[1].f[j], outputs[i].xyzw[1].u[j],
5552 outputs[i].xyzw[2].f[j], outputs[i].xyzw[2].u[j],
5553 outputs[i].xyzw[3].f[j], outputs[i].xyzw[3].u[j]);
5554 }
5555 }
5556 }
5557 #endif
5558 }
5559 }
5560
5561 #if 0
5562 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
5563 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
5564 /*
5565 * Scale back depth component.
5566 */
5567 for (i = 0; i < 4; i++)
5568 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
5569 }
5570 #endif
5571
5572 /* Strictly speaking, these assertions aren't really needed but they
5573 * can potentially catch some bugs in the control flow code.
5574 */
5575 assert(mach->CondStackTop == 0);
5576 assert(mach->LoopStackTop == 0);
5577 assert(mach->ContStackTop == 0);
5578 assert(mach->SwitchStackTop == 0);
5579 assert(mach->BreakStackTop == 0);
5580 assert(mach->CallStackTop == 0);
5581
5582 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
5583 }