projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
tgsi: s/Elements/ARRAY_SIZE/
[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 VMware, Inc.
4 * All Rights Reserved.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 /**
30 * TGSI interpreter/executor.
31 *
32 * Flow control information:
33 *
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
38 *
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
42 * See store_dest().
43 *
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
47 *
48 *
49 * Authors:
50 * Michal Krol
51 * Brian Paul
52 */
53
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_half.h"
62 #include "util/u_memory.h"
63 #include "util/u_math.h"
64
65
66 #define DEBUG_EXECUTION 0
67
68
69 #define FAST_MATH 0
70
71 #define TILE_TOP_LEFT 0
72 #define TILE_TOP_RIGHT 1
73 #define TILE_BOTTOM_LEFT 2
74 #define TILE_BOTTOM_RIGHT 3
75
76 union tgsi_double_channel {
77 double d[TGSI_QUAD_SIZE];
78 unsigned u[TGSI_QUAD_SIZE][2];
79 };
80
81 struct tgsi_double_vector {
82 union tgsi_double_channel xy;
83 union tgsi_double_channel zw;
84 };
85
86 static void
87 micro_abs(union tgsi_exec_channel *dst,
88 const union tgsi_exec_channel *src)
89 {
90 dst->f[0] = fabsf(src->f[0]);
91 dst->f[1] = fabsf(src->f[1]);
92 dst->f[2] = fabsf(src->f[2]);
93 dst->f[3] = fabsf(src->f[3]);
94 }
95
96 static void
97 micro_arl(union tgsi_exec_channel *dst,
98 const union tgsi_exec_channel *src)
99 {
100 dst->i[0] = (int)floorf(src->f[0]);
101 dst->i[1] = (int)floorf(src->f[1]);
102 dst->i[2] = (int)floorf(src->f[2]);
103 dst->i[3] = (int)floorf(src->f[3]);
104 }
105
106 static void
107 micro_arr(union tgsi_exec_channel *dst,
108 const union tgsi_exec_channel *src)
109 {
110 dst->i[0] = (int)floorf(src->f[0] + 0.5f);
111 dst->i[1] = (int)floorf(src->f[1] + 0.5f);
112 dst->i[2] = (int)floorf(src->f[2] + 0.5f);
113 dst->i[3] = (int)floorf(src->f[3] + 0.5f);
114 }
115
116 static void
117 micro_ceil(union tgsi_exec_channel *dst,
118 const union tgsi_exec_channel *src)
119 {
120 dst->f[0] = ceilf(src->f[0]);
121 dst->f[1] = ceilf(src->f[1]);
122 dst->f[2] = ceilf(src->f[2]);
123 dst->f[3] = ceilf(src->f[3]);
124 }
125
126 static void
127 micro_clamp(union tgsi_exec_channel *dst,
128 const union tgsi_exec_channel *src0,
129 const union tgsi_exec_channel *src1,
130 const union tgsi_exec_channel *src2)
131 {
132 dst->f[0] = src0->f[0] < src1->f[0] ? src1->f[0] : src0->f[0] > src2->f[0] ? src2->f[0] : src0->f[0];
133 dst->f[1] = src0->f[1] < src1->f[1] ? src1->f[1] : src0->f[1] > src2->f[1] ? src2->f[1] : src0->f[1];
134 dst->f[2] = src0->f[2] < src1->f[2] ? src1->f[2] : src0->f[2] > src2->f[2] ? src2->f[2] : src0->f[2];
135 dst->f[3] = src0->f[3] < src1->f[3] ? src1->f[3] : src0->f[3] > src2->f[3] ? src2->f[3] : src0->f[3];
136 }
137
138 static void
139 micro_cmp(union tgsi_exec_channel *dst,
140 const union tgsi_exec_channel *src0,
141 const union tgsi_exec_channel *src1,
142 const union tgsi_exec_channel *src2)
143 {
144 dst->f[0] = src0->f[0] < 0.0f ? src1->f[0] : src2->f[0];
145 dst->f[1] = src0->f[1] < 0.0f ? src1->f[1] : src2->f[1];
146 dst->f[2] = src0->f[2] < 0.0f ? src1->f[2] : src2->f[2];
147 dst->f[3] = src0->f[3] < 0.0f ? src1->f[3] : src2->f[3];
148 }
149
150 static void
151 micro_cos(union tgsi_exec_channel *dst,
152 const union tgsi_exec_channel *src)
153 {
154 dst->f[0] = cosf(src->f[0]);
155 dst->f[1] = cosf(src->f[1]);
156 dst->f[2] = cosf(src->f[2]);
157 dst->f[3] = cosf(src->f[3]);
158 }
159
160 static void
161 micro_d2f(union tgsi_exec_channel *dst,
162 const union tgsi_double_channel *src)
163 {
164 dst->f[0] = (float)src->d[0];
165 dst->f[1] = (float)src->d[1];
166 dst->f[2] = (float)src->d[2];
167 dst->f[3] = (float)src->d[3];
168 }
169
170 static void
171 micro_d2i(union tgsi_exec_channel *dst,
172 const union tgsi_double_channel *src)
173 {
174 dst->i[0] = (int)src->d[0];
175 dst->i[1] = (int)src->d[1];
176 dst->i[2] = (int)src->d[2];
177 dst->i[3] = (int)src->d[3];
178 }
179
180 static void
181 micro_d2u(union tgsi_exec_channel *dst,
182 const union tgsi_double_channel *src)
183 {
184 dst->u[0] = (unsigned)src->d[0];
185 dst->u[1] = (unsigned)src->d[1];
186 dst->u[2] = (unsigned)src->d[2];
187 dst->u[3] = (unsigned)src->d[3];
188 }
189 static void
190 micro_dabs(union tgsi_double_channel *dst,
191 const union tgsi_double_channel *src)
192 {
193 dst->d[0] = src->d[0] >= 0.0 ? src->d[0] : -src->d[0];
194 dst->d[1] = src->d[1] >= 0.0 ? src->d[1] : -src->d[1];
195 dst->d[2] = src->d[2] >= 0.0 ? src->d[2] : -src->d[2];
196 dst->d[3] = src->d[3] >= 0.0 ? src->d[3] : -src->d[3];
197 }
198
199 static void
200 micro_dadd(union tgsi_double_channel *dst,
201 const union tgsi_double_channel *src)
202 {
203 dst->d[0] = src[0].d[0] + src[1].d[0];
204 dst->d[1] = src[0].d[1] + src[1].d[1];
205 dst->d[2] = src[0].d[2] + src[1].d[2];
206 dst->d[3] = src[0].d[3] + src[1].d[3];
207 }
208
209 static void
210 micro_ddx(union tgsi_exec_channel *dst,
211 const union tgsi_exec_channel *src)
212 {
213 dst->f[0] =
214 dst->f[1] =
215 dst->f[2] =
216 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
217 }
218
219 static void
220 micro_ddy(union tgsi_exec_channel *dst,
221 const union tgsi_exec_channel *src)
222 {
223 dst->f[0] =
224 dst->f[1] =
225 dst->f[2] =
226 dst->f[3] = src->f[TILE_BOTTOM_LEFT] - src->f[TILE_TOP_LEFT];
227 }
228
229 static void
230 micro_dmul(union tgsi_double_channel *dst,
231 const union tgsi_double_channel *src)
232 {
233 dst->d[0] = src[0].d[0] * src[1].d[0];
234 dst->d[1] = src[0].d[1] * src[1].d[1];
235 dst->d[2] = src[0].d[2] * src[1].d[2];
236 dst->d[3] = src[0].d[3] * src[1].d[3];
237 }
238
239 static void
240 micro_dmax(union tgsi_double_channel *dst,
241 const union tgsi_double_channel *src)
242 {
243 dst->d[0] = src[0].d[0] > src[1].d[0] ? src[0].d[0] : src[1].d[0];
244 dst->d[1] = src[0].d[1] > src[1].d[1] ? src[0].d[1] : src[1].d[1];
245 dst->d[2] = src[0].d[2] > src[1].d[2] ? src[0].d[2] : src[1].d[2];
246 dst->d[3] = src[0].d[3] > src[1].d[3] ? src[0].d[3] : src[1].d[3];
247 }
248
249 static void
250 micro_dmin(union tgsi_double_channel *dst,
251 const union tgsi_double_channel *src)
252 {
253 dst->d[0] = src[0].d[0] < src[1].d[0] ? src[0].d[0] : src[1].d[0];
254 dst->d[1] = src[0].d[1] < src[1].d[1] ? src[0].d[1] : src[1].d[1];
255 dst->d[2] = src[0].d[2] < src[1].d[2] ? src[0].d[2] : src[1].d[2];
256 dst->d[3] = src[0].d[3] < src[1].d[3] ? src[0].d[3] : src[1].d[3];
257 }
258
259 static void
260 micro_dneg(union tgsi_double_channel *dst,
261 const union tgsi_double_channel *src)
262 {
263 dst->d[0] = -src->d[0];
264 dst->d[1] = -src->d[1];
265 dst->d[2] = -src->d[2];
266 dst->d[3] = -src->d[3];
267 }
268
269 static void
270 micro_dslt(union tgsi_double_channel *dst,
271 const union tgsi_double_channel *src)
272 {
273 dst->u[0][0] = src[0].d[0] < src[1].d[0] ? ~0U : 0U;
274 dst->u[1][0] = src[0].d[1] < src[1].d[1] ? ~0U : 0U;
275 dst->u[2][0] = src[0].d[2] < src[1].d[2] ? ~0U : 0U;
276 dst->u[3][0] = src[0].d[3] < src[1].d[3] ? ~0U : 0U;
277 }
278
279 static void
280 micro_dsne(union tgsi_double_channel *dst,
281 const union tgsi_double_channel *src)
282 {
283 dst->u[0][0] = src[0].d[0] != src[1].d[0] ? ~0U : 0U;
284 dst->u[1][0] = src[0].d[1] != src[1].d[1] ? ~0U : 0U;
285 dst->u[2][0] = src[0].d[2] != src[1].d[2] ? ~0U : 0U;
286 dst->u[3][0] = src[0].d[3] != src[1].d[3] ? ~0U : 0U;
287 }
288
289 static void
290 micro_dsge(union tgsi_double_channel *dst,
291 const union tgsi_double_channel *src)
292 {
293 dst->u[0][0] = src[0].d[0] >= src[1].d[0] ? ~0U : 0U;
294 dst->u[1][0] = src[0].d[1] >= src[1].d[1] ? ~0U : 0U;
295 dst->u[2][0] = src[0].d[2] >= src[1].d[2] ? ~0U : 0U;
296 dst->u[3][0] = src[0].d[3] >= src[1].d[3] ? ~0U : 0U;
297 }
298
299 static void
300 micro_dseq(union tgsi_double_channel *dst,
301 const union tgsi_double_channel *src)
302 {
303 dst->u[0][0] = src[0].d[0] == src[1].d[0] ? ~0U : 0U;
304 dst->u[1][0] = src[0].d[1] == src[1].d[1] ? ~0U : 0U;
305 dst->u[2][0] = src[0].d[2] == src[1].d[2] ? ~0U : 0U;
306 dst->u[3][0] = src[0].d[3] == src[1].d[3] ? ~0U : 0U;
307 }
308
309 static void
310 micro_drcp(union tgsi_double_channel *dst,
311 const union tgsi_double_channel *src)
312 {
313 dst->d[0] = 1.0 / src->d[0];
314 dst->d[1] = 1.0 / src->d[1];
315 dst->d[2] = 1.0 / src->d[2];
316 dst->d[3] = 1.0 / src->d[3];
317 }
318
319 static void
320 micro_dsqrt(union tgsi_double_channel *dst,
321 const union tgsi_double_channel *src)
322 {
323 dst->d[0] = sqrt(src->d[0]);
324 dst->d[1] = sqrt(src->d[1]);
325 dst->d[2] = sqrt(src->d[2]);
326 dst->d[3] = sqrt(src->d[3]);
327 }
328
329 static void
330 micro_drsq(union tgsi_double_channel *dst,
331 const union tgsi_double_channel *src)
332 {
333 dst->d[0] = 1.0 / sqrt(src->d[0]);
334 dst->d[1] = 1.0 / sqrt(src->d[1]);
335 dst->d[2] = 1.0 / sqrt(src->d[2]);
336 dst->d[3] = 1.0 / sqrt(src->d[3]);
337 }
338
339 static void
340 micro_dmad(union tgsi_double_channel *dst,
341 const union tgsi_double_channel *src)
342 {
343 dst->d[0] = src[0].d[0] * src[1].d[0] + src[2].d[0];
344 dst->d[1] = src[0].d[1] * src[1].d[1] + src[2].d[1];
345 dst->d[2] = src[0].d[2] * src[1].d[2] + src[2].d[2];
346 dst->d[3] = src[0].d[3] * src[1].d[3] + src[2].d[3];
347 }
348
349 static void
350 micro_dfrac(union tgsi_double_channel *dst,
351 const union tgsi_double_channel *src)
352 {
353 dst->d[0] = src->d[0] - floor(src->d[0]);
354 dst->d[1] = src->d[1] - floor(src->d[1]);
355 dst->d[2] = src->d[2] - floor(src->d[2]);
356 dst->d[3] = src->d[3] - floor(src->d[3]);
357 }
358
359 static void
360 micro_dldexp(union tgsi_double_channel *dst,
361 const union tgsi_double_channel *src0,
362 union tgsi_exec_channel *src1)
363 {
364 dst->d[0] = ldexp(src0->d[0], src1->i[0]);
365 dst->d[1] = ldexp(src0->d[1], src1->i[1]);
366 dst->d[2] = ldexp(src0->d[2], src1->i[2]);
367 dst->d[3] = ldexp(src0->d[3], src1->i[3]);
368 }
369
370 static void
371 micro_dfracexp(union tgsi_double_channel *dst,
372 union tgsi_exec_channel *dst_exp,
373 const union tgsi_double_channel *src)
374 {
375 dst->d[0] = frexp(src->d[0], &dst_exp->i[0]);
376 dst->d[1] = frexp(src->d[1], &dst_exp->i[1]);
377 dst->d[2] = frexp(src->d[2], &dst_exp->i[2]);
378 dst->d[3] = frexp(src->d[3], &dst_exp->i[3]);
379 }
380
381 static void
382 micro_exp2(union tgsi_exec_channel *dst,
383 const union tgsi_exec_channel *src)
384 {
385 #if FAST_MATH
386 dst->f[0] = util_fast_exp2(src->f[0]);
387 dst->f[1] = util_fast_exp2(src->f[1]);
388 dst->f[2] = util_fast_exp2(src->f[2]);
389 dst->f[3] = util_fast_exp2(src->f[3]);
390 #else
391 #if DEBUG
392 /* Inf is okay for this instruction, so clamp it to silence assertions. */
393 uint i;
394 union tgsi_exec_channel clamped;
395
396 for (i = 0; i < 4; i++) {
397 if (src->f[i] > 127.99999f) {
398 clamped.f[i] = 127.99999f;
399 } else if (src->f[i] < -126.99999f) {
400 clamped.f[i] = -126.99999f;
401 } else {
402 clamped.f[i] = src->f[i];
403 }
404 }
405 src = &clamped;
406 #endif /* DEBUG */
407
408 dst->f[0] = powf(2.0f, src->f[0]);
409 dst->f[1] = powf(2.0f, src->f[1]);
410 dst->f[2] = powf(2.0f, src->f[2]);
411 dst->f[3] = powf(2.0f, src->f[3]);
412 #endif /* FAST_MATH */
413 }
414
415 static void
416 micro_f2d(union tgsi_double_channel *dst,
417 const union tgsi_exec_channel *src)
418 {
419 dst->d[0] = (double)src->f[0];
420 dst->d[1] = (double)src->f[1];
421 dst->d[2] = (double)src->f[2];
422 dst->d[3] = (double)src->f[3];
423 }
424
425 static void
426 micro_flr(union tgsi_exec_channel *dst,
427 const union tgsi_exec_channel *src)
428 {
429 dst->f[0] = floorf(src->f[0]);
430 dst->f[1] = floorf(src->f[1]);
431 dst->f[2] = floorf(src->f[2]);
432 dst->f[3] = floorf(src->f[3]);
433 }
434
435 static void
436 micro_frc(union tgsi_exec_channel *dst,
437 const union tgsi_exec_channel *src)
438 {
439 dst->f[0] = src->f[0] - floorf(src->f[0]);
440 dst->f[1] = src->f[1] - floorf(src->f[1]);
441 dst->f[2] = src->f[2] - floorf(src->f[2]);
442 dst->f[3] = src->f[3] - floorf(src->f[3]);
443 }
444
445 static void
446 micro_i2d(union tgsi_double_channel *dst,
447 const union tgsi_exec_channel *src)
448 {
449 dst->d[0] = (double)src->i[0];
450 dst->d[1] = (double)src->i[1];
451 dst->d[2] = (double)src->i[2];
452 dst->d[3] = (double)src->i[3];
453 }
454
455 static void
456 micro_iabs(union tgsi_exec_channel *dst,
457 const union tgsi_exec_channel *src)
458 {
459 dst->i[0] = src->i[0] >= 0 ? src->i[0] : -src->i[0];
460 dst->i[1] = src->i[1] >= 0 ? src->i[1] : -src->i[1];
461 dst->i[2] = src->i[2] >= 0 ? src->i[2] : -src->i[2];
462 dst->i[3] = src->i[3] >= 0 ? src->i[3] : -src->i[3];
463 }
464
465 static void
466 micro_ineg(union tgsi_exec_channel *dst,
467 const union tgsi_exec_channel *src)
468 {
469 dst->i[0] = -src->i[0];
470 dst->i[1] = -src->i[1];
471 dst->i[2] = -src->i[2];
472 dst->i[3] = -src->i[3];
473 }
474
475 static void
476 micro_lg2(union tgsi_exec_channel *dst,
477 const union tgsi_exec_channel *src)
478 {
479 #if FAST_MATH
480 dst->f[0] = util_fast_log2(src->f[0]);
481 dst->f[1] = util_fast_log2(src->f[1]);
482 dst->f[2] = util_fast_log2(src->f[2]);
483 dst->f[3] = util_fast_log2(src->f[3]);
484 #else
485 dst->f[0] = logf(src->f[0]) * 1.442695f;
486 dst->f[1] = logf(src->f[1]) * 1.442695f;
487 dst->f[2] = logf(src->f[2]) * 1.442695f;
488 dst->f[3] = logf(src->f[3]) * 1.442695f;
489 #endif
490 }
491
492 static void
493 micro_lrp(union tgsi_exec_channel *dst,
494 const union tgsi_exec_channel *src0,
495 const union tgsi_exec_channel *src1,
496 const union tgsi_exec_channel *src2)
497 {
498 dst->f[0] = src0->f[0] * (src1->f[0] - src2->f[0]) + src2->f[0];
499 dst->f[1] = src0->f[1] * (src1->f[1] - src2->f[1]) + src2->f[1];
500 dst->f[2] = src0->f[2] * (src1->f[2] - src2->f[2]) + src2->f[2];
501 dst->f[3] = src0->f[3] * (src1->f[3] - src2->f[3]) + src2->f[3];
502 }
503
504 static void
505 micro_mad(union tgsi_exec_channel *dst,
506 const union tgsi_exec_channel *src0,
507 const union tgsi_exec_channel *src1,
508 const union tgsi_exec_channel *src2)
509 {
510 dst->f[0] = src0->f[0] * src1->f[0] + src2->f[0];
511 dst->f[1] = src0->f[1] * src1->f[1] + src2->f[1];
512 dst->f[2] = src0->f[2] * src1->f[2] + src2->f[2];
513 dst->f[3] = src0->f[3] * src1->f[3] + src2->f[3];
514 }
515
516 static void
517 micro_mov(union tgsi_exec_channel *dst,
518 const union tgsi_exec_channel *src)
519 {
520 dst->u[0] = src->u[0];
521 dst->u[1] = src->u[1];
522 dst->u[2] = src->u[2];
523 dst->u[3] = src->u[3];
524 }
525
526 static void
527 micro_rcp(union tgsi_exec_channel *dst,
528 const union tgsi_exec_channel *src)
529 {
530 #if 0 /* for debugging */
531 assert(src->f[0] != 0.0f);
532 assert(src->f[1] != 0.0f);
533 assert(src->f[2] != 0.0f);
534 assert(src->f[3] != 0.0f);
535 #endif
536 dst->f[0] = 1.0f / src->f[0];
537 dst->f[1] = 1.0f / src->f[1];
538 dst->f[2] = 1.0f / src->f[2];
539 dst->f[3] = 1.0f / src->f[3];
540 }
541
542 static void
543 micro_rnd(union tgsi_exec_channel *dst,
544 const union tgsi_exec_channel *src)
545 {
546 dst->f[0] = floorf(src->f[0] + 0.5f);
547 dst->f[1] = floorf(src->f[1] + 0.5f);
548 dst->f[2] = floorf(src->f[2] + 0.5f);
549 dst->f[3] = floorf(src->f[3] + 0.5f);
550 }
551
552 static void
553 micro_rsq(union tgsi_exec_channel *dst,
554 const union tgsi_exec_channel *src)
555 {
556 #if 0 /* for debugging */
557 assert(src->f[0] != 0.0f);
558 assert(src->f[1] != 0.0f);
559 assert(src->f[2] != 0.0f);
560 assert(src->f[3] != 0.0f);
561 #endif
562 dst->f[0] = 1.0f / sqrtf(src->f[0]);
563 dst->f[1] = 1.0f / sqrtf(src->f[1]);
564 dst->f[2] = 1.0f / sqrtf(src->f[2]);
565 dst->f[3] = 1.0f / sqrtf(src->f[3]);
566 }
567
568 static void
569 micro_sqrt(union tgsi_exec_channel *dst,
570 const union tgsi_exec_channel *src)
571 {
572 dst->f[0] = sqrtf(src->f[0]);
573 dst->f[1] = sqrtf(src->f[1]);
574 dst->f[2] = sqrtf(src->f[2]);
575 dst->f[3] = sqrtf(src->f[3]);
576 }
577
578 static void
579 micro_seq(union tgsi_exec_channel *dst,
580 const union tgsi_exec_channel *src0,
581 const union tgsi_exec_channel *src1)
582 {
583 dst->f[0] = src0->f[0] == src1->f[0] ? 1.0f : 0.0f;
584 dst->f[1] = src0->f[1] == src1->f[1] ? 1.0f : 0.0f;
585 dst->f[2] = src0->f[2] == src1->f[2] ? 1.0f : 0.0f;
586 dst->f[3] = src0->f[3] == src1->f[3] ? 1.0f : 0.0f;
587 }
588
589 static void
590 micro_sge(union tgsi_exec_channel *dst,
591 const union tgsi_exec_channel *src0,
592 const union tgsi_exec_channel *src1)
593 {
594 dst->f[0] = src0->f[0] >= src1->f[0] ? 1.0f : 0.0f;
595 dst->f[1] = src0->f[1] >= src1->f[1] ? 1.0f : 0.0f;
596 dst->f[2] = src0->f[2] >= src1->f[2] ? 1.0f : 0.0f;
597 dst->f[3] = src0->f[3] >= src1->f[3] ? 1.0f : 0.0f;
598 }
599
600 static void
601 micro_sgn(union tgsi_exec_channel *dst,
602 const union tgsi_exec_channel *src)
603 {
604 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
605 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
606 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
607 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
608 }
609
610 static void
611 micro_isgn(union tgsi_exec_channel *dst,
612 const union tgsi_exec_channel *src)
613 {
614 dst->i[0] = src->i[0] < 0 ? -1 : src->i[0] > 0 ? 1 : 0;
615 dst->i[1] = src->i[1] < 0 ? -1 : src->i[1] > 0 ? 1 : 0;
616 dst->i[2] = src->i[2] < 0 ? -1 : src->i[2] > 0 ? 1 : 0;
617 dst->i[3] = src->i[3] < 0 ? -1 : src->i[3] > 0 ? 1 : 0;
618 }
619
620 static void
621 micro_sgt(union tgsi_exec_channel *dst,
622 const union tgsi_exec_channel *src0,
623 const union tgsi_exec_channel *src1)
624 {
625 dst->f[0] = src0->f[0] > src1->f[0] ? 1.0f : 0.0f;
626 dst->f[1] = src0->f[1] > src1->f[1] ? 1.0f : 0.0f;
627 dst->f[2] = src0->f[2] > src1->f[2] ? 1.0f : 0.0f;
628 dst->f[3] = src0->f[3] > src1->f[3] ? 1.0f : 0.0f;
629 }
630
631 static void
632 micro_sin(union tgsi_exec_channel *dst,
633 const union tgsi_exec_channel *src)
634 {
635 dst->f[0] = sinf(src->f[0]);
636 dst->f[1] = sinf(src->f[1]);
637 dst->f[2] = sinf(src->f[2]);
638 dst->f[3] = sinf(src->f[3]);
639 }
640
641 static void
642 micro_sle(union tgsi_exec_channel *dst,
643 const union tgsi_exec_channel *src0,
644 const union tgsi_exec_channel *src1)
645 {
646 dst->f[0] = src0->f[0] <= src1->f[0] ? 1.0f : 0.0f;
647 dst->f[1] = src0->f[1] <= src1->f[1] ? 1.0f : 0.0f;
648 dst->f[2] = src0->f[2] <= src1->f[2] ? 1.0f : 0.0f;
649 dst->f[3] = src0->f[3] <= src1->f[3] ? 1.0f : 0.0f;
650 }
651
652 static void
653 micro_slt(union tgsi_exec_channel *dst,
654 const union tgsi_exec_channel *src0,
655 const union tgsi_exec_channel *src1)
656 {
657 dst->f[0] = src0->f[0] < src1->f[0] ? 1.0f : 0.0f;
658 dst->f[1] = src0->f[1] < src1->f[1] ? 1.0f : 0.0f;
659 dst->f[2] = src0->f[2] < src1->f[2] ? 1.0f : 0.0f;
660 dst->f[3] = src0->f[3] < src1->f[3] ? 1.0f : 0.0f;
661 }
662
663 static void
664 micro_sne(union tgsi_exec_channel *dst,
665 const union tgsi_exec_channel *src0,
666 const union tgsi_exec_channel *src1)
667 {
668 dst->f[0] = src0->f[0] != src1->f[0] ? 1.0f : 0.0f;
669 dst->f[1] = src0->f[1] != src1->f[1] ? 1.0f : 0.0f;
670 dst->f[2] = src0->f[2] != src1->f[2] ? 1.0f : 0.0f;
671 dst->f[3] = src0->f[3] != src1->f[3] ? 1.0f : 0.0f;
672 }
673
674 static void
675 micro_trunc(union tgsi_exec_channel *dst,
676 const union tgsi_exec_channel *src)
677 {
678 dst->f[0] = (float)(int)src->f[0];
679 dst->f[1] = (float)(int)src->f[1];
680 dst->f[2] = (float)(int)src->f[2];
681 dst->f[3] = (float)(int)src->f[3];
682 }
683
684 static void
685 micro_u2d(union tgsi_double_channel *dst,
686 const union tgsi_exec_channel *src)
687 {
688 dst->d[0] = (double)src->u[0];
689 dst->d[1] = (double)src->u[1];
690 dst->d[2] = (double)src->u[2];
691 dst->d[3] = (double)src->u[3];
692 }
693
694 enum tgsi_exec_datatype {
695 TGSI_EXEC_DATA_FLOAT,
696 TGSI_EXEC_DATA_INT,
697 TGSI_EXEC_DATA_UINT,
698 TGSI_EXEC_DATA_DOUBLE
699 };
700
701 /*
702 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
703 */
704 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
705 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
706 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
707 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
708 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
709 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
710
711
712 /** The execution mask depends on the conditional mask and the loop mask */
713 #define UPDATE_EXEC_MASK(MACH) \
714 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
715
716
717 static const union tgsi_exec_channel ZeroVec =
718 { { 0.0, 0.0, 0.0, 0.0 } };
719
720 static const union tgsi_exec_channel OneVec = {
721 {1.0f, 1.0f, 1.0f, 1.0f}
722 };
723
724 static const union tgsi_exec_channel P128Vec = {
725 {128.0f, 128.0f, 128.0f, 128.0f}
726 };
727
728 static const union tgsi_exec_channel M128Vec = {
729 {-128.0f, -128.0f, -128.0f, -128.0f}
730 };
731
732
733 /**
734 * Assert that none of the float values in 'chan' are infinite or NaN.
735 * NaN and Inf may occur normally during program execution and should
736 * not lead to crashes, etc. But when debugging, it's helpful to catch
737 * them.
738 */
739 static inline void
740 check_inf_or_nan(const union tgsi_exec_channel *chan)
741 {
742 assert(!util_is_inf_or_nan((chan)->f[0]));
743 assert(!util_is_inf_or_nan((chan)->f[1]));
744 assert(!util_is_inf_or_nan((chan)->f[2]));
745 assert(!util_is_inf_or_nan((chan)->f[3]));
746 }
747
748
749 #ifdef DEBUG
750 static void
751 print_chan(const char *msg, const union tgsi_exec_channel *chan)
752 {
753 debug_printf("%s = {%f, %f, %f, %f}\n",
754 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
755 }
756 #endif
757
758
759 #ifdef DEBUG
760 static void
761 print_temp(const struct tgsi_exec_machine *mach, uint index)
762 {
763 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
764 int i;
765 debug_printf("Temp[%u] =\n", index);
766 for (i = 0; i < 4; i++) {
767 debug_printf(" %c: { %f, %f, %f, %f }\n",
768 "XYZW"[i],
769 tmp->xyzw[i].f[0],
770 tmp->xyzw[i].f[1],
771 tmp->xyzw[i].f[2],
772 tmp->xyzw[i].f[3]);
773 }
774 }
775 #endif
776
777
778 void
779 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine *mach,
780 unsigned num_bufs,
781 const void **bufs,
782 const unsigned *buf_sizes)
783 {
784 unsigned i;
785
786 for (i = 0; i < num_bufs; i++) {
787 mach->Consts[i] = bufs[i];
788 mach->ConstsSize[i] = buf_sizes[i];
789 }
790 }
791
792
793 /**
794 * Check if there's a potential src/dst register data dependency when
795 * using SOA execution.
796 * Example:
797 * MOV T, T.yxwz;
798 * This would expand into:
799 * MOV t0, t1;
800 * MOV t1, t0;
801 * MOV t2, t3;
802 * MOV t3, t2;
803 * The second instruction will have the wrong value for t0 if executed as-is.
804 */
805 boolean
806 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
807 {
808 uint i, chan;
809
810 uint writemask = inst->Dst[0].Register.WriteMask;
811 if (writemask == TGSI_WRITEMASK_X ||
812 writemask == TGSI_WRITEMASK_Y ||
813 writemask == TGSI_WRITEMASK_Z ||
814 writemask == TGSI_WRITEMASK_W ||
815 writemask == TGSI_WRITEMASK_NONE) {
816 /* no chance of data dependency */
817 return FALSE;
818 }
819
820 /* loop over src regs */
821 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
822 if ((inst->Src[i].Register.File ==
823 inst->Dst[0].Register.File) &&
824 ((inst->Src[i].Register.Index ==
825 inst->Dst[0].Register.Index) ||
826 inst->Src[i].Register.Indirect ||
827 inst->Dst[0].Register.Indirect)) {
828 /* loop over dest channels */
829 uint channelsWritten = 0x0;
830 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
831 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
832 /* check if we're reading a channel that's been written */
833 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
834 if (channelsWritten & (1 << swizzle)) {
835 return TRUE;
836 }
837
838 channelsWritten |= (1 << chan);
839 }
840 }
841 }
842 }
843 return FALSE;
844 }
845
846
847 /**
848 * Initialize machine state by expanding tokens to full instructions,
849 * allocating temporary storage, setting up constants, etc.
850 * After this, we can call tgsi_exec_machine_run() many times.
851 */
852 void
853 tgsi_exec_machine_bind_shader(
854 struct tgsi_exec_machine *mach,
855 const struct tgsi_token *tokens,
856 struct tgsi_sampler *sampler,
857 struct tgsi_image *image,
858 struct tgsi_buffer *buffer)
859 {
860 uint k;
861 struct tgsi_parse_context parse;
862 struct tgsi_full_instruction *instructions;
863 struct tgsi_full_declaration *declarations;
864 uint maxInstructions = 10, numInstructions = 0;
865 uint maxDeclarations = 10, numDeclarations = 0;
866
867 #if 0
868 tgsi_dump(tokens, 0);
869 #endif
870
871 util_init_math();
872
873
874 mach->Tokens = tokens;
875 mach->Sampler = sampler;
876 mach->Image = image;
877 mach->Buffer = buffer;
878
879 if (!tokens) {
880 /* unbind and free all */
881 FREE(mach->Declarations);
882 mach->Declarations = NULL;
883 mach->NumDeclarations = 0;
884
885 FREE(mach->Instructions);
886 mach->Instructions = NULL;
887 mach->NumInstructions = 0;
888
889 return;
890 }
891
892 k = tgsi_parse_init (&parse, mach->Tokens);
893 if (k != TGSI_PARSE_OK) {
894 debug_printf( "Problem parsing!\n" );
895 return;
896 }
897
898 mach->ImmLimit = 0;
899 mach->NumOutputs = 0;
900
901 for (k = 0; k < TGSI_SEMANTIC_COUNT; k++)
902 mach->SysSemanticToIndex[k] = -1;
903
904 if (mach->ShaderType == PIPE_SHADER_GEOMETRY &&
905 !mach->UsedGeometryShader) {
906 struct tgsi_exec_vector *inputs;
907 struct tgsi_exec_vector *outputs;
908
909 inputs = align_malloc(sizeof(struct tgsi_exec_vector) *
910 TGSI_MAX_PRIM_VERTICES * PIPE_MAX_SHADER_INPUTS,
911 16);
912
913 if (!inputs)
914 return;
915
916 outputs = align_malloc(sizeof(struct tgsi_exec_vector) *
917 TGSI_MAX_TOTAL_VERTICES, 16);
918
919 if (!outputs) {
920 align_free(inputs);
921 return;
922 }
923
924 align_free(mach->Inputs);
925 align_free(mach->Outputs);
926
927 mach->Inputs = inputs;
928 mach->Outputs = outputs;
929 mach->UsedGeometryShader = TRUE;
930 }
931
932 declarations = (struct tgsi_full_declaration *)
933 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
934
935 if (!declarations) {
936 return;
937 }
938
939 instructions = (struct tgsi_full_instruction *)
940 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
941
942 if (!instructions) {
943 FREE( declarations );
944 return;
945 }
946
947 while( !tgsi_parse_end_of_tokens( &parse ) ) {
948 uint i;
949
950 tgsi_parse_token( &parse );
951 switch( parse.FullToken.Token.Type ) {
952 case TGSI_TOKEN_TYPE_DECLARATION:
953 /* save expanded declaration */
954 if (numDeclarations == maxDeclarations) {
955 declarations = REALLOC(declarations,
956 maxDeclarations
957 * sizeof(struct tgsi_full_declaration),
958 (maxDeclarations + 10)
959 * sizeof(struct tgsi_full_declaration));
960 maxDeclarations += 10;
961 }
962 if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_OUTPUT) {
963 unsigned reg;
964 for (reg = parse.FullToken.FullDeclaration.Range.First;
965 reg <= parse.FullToken.FullDeclaration.Range.Last;
966 ++reg) {
967 ++mach->NumOutputs;
968 }
969 }
970 else if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
971 const struct tgsi_full_declaration *decl = &parse.FullToken.FullDeclaration;
972 mach->SysSemanticToIndex[decl->Semantic.Name] = decl->Range.First;
973 }
974
975 memcpy(declarations + numDeclarations,
976 &parse.FullToken.FullDeclaration,
977 sizeof(declarations[0]));
978 numDeclarations++;
979 break;
980
981 case TGSI_TOKEN_TYPE_IMMEDIATE:
982 {
983 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
984 assert( size <= 4 );
985 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
986
987 for( i = 0; i < size; i++ ) {
988 mach->Imms[mach->ImmLimit][i] =
989 parse.FullToken.FullImmediate.u[i].Float;
990 }
991 mach->ImmLimit += 1;
992 }
993 break;
994
995 case TGSI_TOKEN_TYPE_INSTRUCTION:
996
997 /* save expanded instruction */
998 if (numInstructions == maxInstructions) {
999 instructions = REALLOC(instructions,
1000 maxInstructions
1001 * sizeof(struct tgsi_full_instruction),
1002 (maxInstructions + 10)
1003 * sizeof(struct tgsi_full_instruction));
1004 maxInstructions += 10;
1005 }
1006
1007 memcpy(instructions + numInstructions,
1008 &parse.FullToken.FullInstruction,
1009 sizeof(instructions[0]));
1010
1011 numInstructions++;
1012 break;
1013
1014 case TGSI_TOKEN_TYPE_PROPERTY:
1015 if (mach->ShaderType == PIPE_SHADER_GEOMETRY) {
1016 if (parse.FullToken.FullProperty.Property.PropertyName == TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES) {
1017 mach->MaxOutputVertices = parse.FullToken.FullProperty.u[0].Data;
1018 }
1019 }
1020 break;
1021
1022 default:
1023 assert( 0 );
1024 }
1025 }
1026 tgsi_parse_free (&parse);
1027
1028 FREE(mach->Declarations);
1029 mach->Declarations = declarations;
1030 mach->NumDeclarations = numDeclarations;
1031
1032 FREE(mach->Instructions);
1033 mach->Instructions = instructions;
1034 mach->NumInstructions = numInstructions;
1035 }
1036
1037
1038 struct tgsi_exec_machine *
1039 tgsi_exec_machine_create(enum pipe_shader_type shader_type)
1040 {
1041 struct tgsi_exec_machine *mach;
1042 uint i;
1043
1044 mach = align_malloc( sizeof *mach, 16 );
1045 if (!mach)
1046 goto fail;
1047
1048 memset(mach, 0, sizeof(*mach));
1049
1050 mach->ShaderType = shader_type;
1051 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
1052 mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
1053 mach->Predicates = &mach->Temps[TGSI_EXEC_TEMP_P0];
1054
1055 if (shader_type != PIPE_SHADER_COMPUTE) {
1056 mach->Inputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_INPUTS, 16);
1057 mach->Outputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_OUTPUTS, 16);
1058 if (!mach->Inputs || !mach->Outputs)
1059 goto fail;
1060 }
1061
1062 /* Setup constants needed by the SSE2 executor. */
1063 for( i = 0; i < 4; i++ ) {
1064 mach->Temps[TGSI_EXEC_TEMP_00000000_I].xyzw[TGSI_EXEC_TEMP_00000000_C].u[i] = 0x00000000;
1065 mach->Temps[TGSI_EXEC_TEMP_7FFFFFFF_I].xyzw[TGSI_EXEC_TEMP_7FFFFFFF_C].u[i] = 0x7FFFFFFF;
1066 mach->Temps[TGSI_EXEC_TEMP_80000000_I].xyzw[TGSI_EXEC_TEMP_80000000_C].u[i] = 0x80000000;
1067 mach->Temps[TGSI_EXEC_TEMP_FFFFFFFF_I].xyzw[TGSI_EXEC_TEMP_FFFFFFFF_C].u[i] = 0xFFFFFFFF; /* not used */
1068 mach->Temps[TGSI_EXEC_TEMP_ONE_I].xyzw[TGSI_EXEC_TEMP_ONE_C].f[i] = 1.0f;
1069 mach->Temps[TGSI_EXEC_TEMP_TWO_I].xyzw[TGSI_EXEC_TEMP_TWO_C].f[i] = 2.0f; /* not used */
1070 mach->Temps[TGSI_EXEC_TEMP_128_I].xyzw[TGSI_EXEC_TEMP_128_C].f[i] = 128.0f;
1071 mach->Temps[TGSI_EXEC_TEMP_MINUS_128_I].xyzw[TGSI_EXEC_TEMP_MINUS_128_C].f[i] = -128.0f;
1072 mach->Temps[TGSI_EXEC_TEMP_THREE_I].xyzw[TGSI_EXEC_TEMP_THREE_C].f[i] = 3.0f;
1073 mach->Temps[TGSI_EXEC_TEMP_HALF_I].xyzw[TGSI_EXEC_TEMP_HALF_C].f[i] = 0.5f;
1074 }
1075
1076 #ifdef DEBUG
1077 /* silence warnings */
1078 (void) print_chan;
1079 (void) print_temp;
1080 #endif
1081
1082 return mach;
1083
1084 fail:
1085 if (mach) {
1086 align_free(mach->Inputs);
1087 align_free(mach->Outputs);
1088 align_free(mach);
1089 }
1090 return NULL;
1091 }
1092
1093
1094 void
1095 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
1096 {
1097 if (mach) {
1098 FREE(mach->Instructions);
1099 FREE(mach->Declarations);
1100
1101 align_free(mach->Inputs);
1102 align_free(mach->Outputs);
1103
1104 align_free(mach);
1105 }
1106 }
1107
1108 static void
1109 micro_add(union tgsi_exec_channel *dst,
1110 const union tgsi_exec_channel *src0,
1111 const union tgsi_exec_channel *src1)
1112 {
1113 dst->f[0] = src0->f[0] + src1->f[0];
1114 dst->f[1] = src0->f[1] + src1->f[1];
1115 dst->f[2] = src0->f[2] + src1->f[2];
1116 dst->f[3] = src0->f[3] + src1->f[3];
1117 }
1118
1119 static void
1120 micro_div(
1121 union tgsi_exec_channel *dst,
1122 const union tgsi_exec_channel *src0,
1123 const union tgsi_exec_channel *src1 )
1124 {
1125 if (src1->f[0] != 0) {
1126 dst->f[0] = src0->f[0] / src1->f[0];
1127 }
1128 if (src1->f[1] != 0) {
1129 dst->f[1] = src0->f[1] / src1->f[1];
1130 }
1131 if (src1->f[2] != 0) {
1132 dst->f[2] = src0->f[2] / src1->f[2];
1133 }
1134 if (src1->f[3] != 0) {
1135 dst->f[3] = src0->f[3] / src1->f[3];
1136 }
1137 }
1138
1139 static void
1140 micro_lt(
1141 union tgsi_exec_channel *dst,
1142 const union tgsi_exec_channel *src0,
1143 const union tgsi_exec_channel *src1,
1144 const union tgsi_exec_channel *src2,
1145 const union tgsi_exec_channel *src3 )
1146 {
1147 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
1148 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
1149 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
1150 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
1151 }
1152
1153 static void
1154 micro_max(union tgsi_exec_channel *dst,
1155 const union tgsi_exec_channel *src0,
1156 const union tgsi_exec_channel *src1)
1157 {
1158 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
1159 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
1160 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
1161 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
1162 }
1163
1164 static void
1165 micro_min(union tgsi_exec_channel *dst,
1166 const union tgsi_exec_channel *src0,
1167 const union tgsi_exec_channel *src1)
1168 {
1169 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
1170 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
1171 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
1172 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
1173 }
1174
1175 static void
1176 micro_mul(union tgsi_exec_channel *dst,
1177 const union tgsi_exec_channel *src0,
1178 const union tgsi_exec_channel *src1)
1179 {
1180 dst->f[0] = src0->f[0] * src1->f[0];
1181 dst->f[1] = src0->f[1] * src1->f[1];
1182 dst->f[2] = src0->f[2] * src1->f[2];
1183 dst->f[3] = src0->f[3] * src1->f[3];
1184 }
1185
1186 static void
1187 micro_neg(
1188 union tgsi_exec_channel *dst,
1189 const union tgsi_exec_channel *src )
1190 {
1191 dst->f[0] = -src->f[0];
1192 dst->f[1] = -src->f[1];
1193 dst->f[2] = -src->f[2];
1194 dst->f[3] = -src->f[3];
1195 }
1196
1197 static void
1198 micro_pow(
1199 union tgsi_exec_channel *dst,
1200 const union tgsi_exec_channel *src0,
1201 const union tgsi_exec_channel *src1 )
1202 {
1203 #if FAST_MATH
1204 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
1205 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
1206 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
1207 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
1208 #else
1209 dst->f[0] = powf( src0->f[0], src1->f[0] );
1210 dst->f[1] = powf( src0->f[1], src1->f[1] );
1211 dst->f[2] = powf( src0->f[2], src1->f[2] );
1212 dst->f[3] = powf( src0->f[3], src1->f[3] );
1213 #endif
1214 }
1215
1216 static void
1217 micro_sub(union tgsi_exec_channel *dst,
1218 const union tgsi_exec_channel *src0,
1219 const union tgsi_exec_channel *src1)
1220 {
1221 dst->f[0] = src0->f[0] - src1->f[0];
1222 dst->f[1] = src0->f[1] - src1->f[1];
1223 dst->f[2] = src0->f[2] - src1->f[2];
1224 dst->f[3] = src0->f[3] - src1->f[3];
1225 }
1226
1227 static void
1228 fetch_src_file_channel(const struct tgsi_exec_machine *mach,
1229 const uint chan_index,
1230 const uint file,
1231 const uint swizzle,
1232 const union tgsi_exec_channel *index,
1233 const union tgsi_exec_channel *index2D,
1234 union tgsi_exec_channel *chan)
1235 {
1236 uint i;
1237
1238 assert(swizzle < 4);
1239
1240 switch (file) {
1241 case TGSI_FILE_CONSTANT:
1242 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1243 assert(index2D->i[i] >= 0 && index2D->i[i] < PIPE_MAX_CONSTANT_BUFFERS);
1244 assert(mach->Consts[index2D->i[i]]);
1245
1246 if (index->i[i] < 0) {
1247 chan->u[i] = 0;
1248 } else {
1249 /* NOTE: copying the const value as a uint instead of float */
1250 const uint constbuf = index2D->i[i];
1251 const uint *buf = (const uint *)mach->Consts[constbuf];
1252 const int pos = index->i[i] * 4 + swizzle;
1253 /* const buffer bounds check */
1254 if (pos < 0 || pos >= (int) mach->ConstsSize[constbuf]) {
1255 if (0) {
1256 /* Debug: print warning */
1257 static int count = 0;
1258 if (count++ < 100)
1259 debug_printf("TGSI Exec: const buffer index %d"
1260 " out of bounds\n", pos);
1261 }
1262 chan->u[i] = 0;
1263 }
1264 else
1265 chan->u[i] = buf[pos];
1266 }
1267 }
1268 break;
1269
1270 case TGSI_FILE_INPUT:
1271 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1272 /*
1273 if (PIPE_SHADER_GEOMETRY == mach->ShaderType) {
1274 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1275 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1276 index2D->i[i], index->i[i]);
1277 }*/
1278 int pos = index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i];
1279 assert(pos >= 0);
1280 assert(pos < TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS);
1281 chan->u[i] = mach->Inputs[pos].xyzw[swizzle].u[i];
1282 }
1283 break;
1284
1285 case TGSI_FILE_SYSTEM_VALUE:
1286 /* XXX no swizzling at this point. Will be needed if we put
1287 * gl_FragCoord, for example, in a sys value register.
1288 */
1289 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1290 chan->u[i] = mach->SystemValue[index->i[i]].xyzw[swizzle].u[i];
1291 }
1292 break;
1293
1294 case TGSI_FILE_TEMPORARY:
1295 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1296 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1297 assert(index2D->i[i] == 0);
1298
1299 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1300 }
1301 break;
1302
1303 case TGSI_FILE_IMMEDIATE:
1304 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1305 assert(index->i[i] >= 0 && index->i[i] < (int)mach->ImmLimit);
1306 assert(index2D->i[i] == 0);
1307
1308 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1309 }
1310 break;
1311
1312 case TGSI_FILE_ADDRESS:
1313 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1314 assert(index->i[i] >= 0);
1315 assert(index2D->i[i] == 0);
1316
1317 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1318 }
1319 break;
1320
1321 case TGSI_FILE_PREDICATE:
1322 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1323 assert(index->i[i] >= 0 && index->i[i] < TGSI_EXEC_NUM_PREDS);
1324 assert(index2D->i[i] == 0);
1325
1326 chan->u[i] = mach->Predicates[0].xyzw[swizzle].u[i];
1327 }
1328 break;
1329
1330 case TGSI_FILE_OUTPUT:
1331 /* vertex/fragment output vars can be read too */
1332 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1333 assert(index->i[i] >= 0);
1334 assert(index2D->i[i] == 0);
1335
1336 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1337 }
1338 break;
1339
1340 default:
1341 assert(0);
1342 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1343 chan->u[i] = 0;
1344 }
1345 }
1346 }
1347
1348 static void
1349 fetch_source_d(const struct tgsi_exec_machine *mach,
1350 union tgsi_exec_channel *chan,
1351 const struct tgsi_full_src_register *reg,
1352 const uint chan_index,
1353 enum tgsi_exec_datatype src_datatype)
1354 {
1355 union tgsi_exec_channel index;
1356 union tgsi_exec_channel index2D;
1357 uint swizzle;
1358
1359 /* We start with a direct index into a register file.
1360 *
1361 * file[1],
1362 * where:
1363 * file = Register.File
1364 * [1] = Register.Index
1365 */
1366 index.i[0] =
1367 index.i[1] =
1368 index.i[2] =
1369 index.i[3] = reg->Register.Index;
1370
1371 /* There is an extra source register that indirectly subscripts
1372 * a register file. The direct index now becomes an offset
1373 * that is being added to the indirect register.
1374 *
1375 * file[ind[2].x+1],
1376 * where:
1377 * ind = Indirect.File
1378 * [2] = Indirect.Index
1379 * .x = Indirect.SwizzleX
1380 */
1381 if (reg->Register.Indirect) {
1382 union tgsi_exec_channel index2;
1383 union tgsi_exec_channel indir_index;
1384 const uint execmask = mach->ExecMask;
1385 uint i;
1386
1387 /* which address register (always zero now) */
1388 index2.i[0] =
1389 index2.i[1] =
1390 index2.i[2] =
1391 index2.i[3] = reg->Indirect.Index;
1392 /* get current value of address register[swizzle] */
1393 swizzle = reg->Indirect.Swizzle;
1394 fetch_src_file_channel(mach,
1395 chan_index,
1396 reg->Indirect.File,
1397 swizzle,
1398 &index2,
1399 &ZeroVec,
1400 &indir_index);
1401
1402 /* add value of address register to the offset */
1403 index.i[0] += indir_index.i[0];
1404 index.i[1] += indir_index.i[1];
1405 index.i[2] += indir_index.i[2];
1406 index.i[3] += indir_index.i[3];
1407
1408 /* for disabled execution channels, zero-out the index to
1409 * avoid using a potential garbage value.
1410 */
1411 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1412 if ((execmask & (1 << i)) == 0)
1413 index.i[i] = 0;
1414 }
1415 }
1416
1417 /* There is an extra source register that is a second
1418 * subscript to a register file. Effectively it means that
1419 * the register file is actually a 2D array of registers.
1420 *
1421 * file[3][1],
1422 * where:
1423 * [3] = Dimension.Index
1424 */
1425 if (reg->Register.Dimension) {
1426 index2D.i[0] =
1427 index2D.i[1] =
1428 index2D.i[2] =
1429 index2D.i[3] = reg->Dimension.Index;
1430
1431 /* Again, the second subscript index can be addressed indirectly
1432 * identically to the first one.
1433 * Nothing stops us from indirectly addressing the indirect register,
1434 * but there is no need for that, so we won't exercise it.
1435 *
1436 * file[ind[4].y+3][1],
1437 * where:
1438 * ind = DimIndirect.File
1439 * [4] = DimIndirect.Index
1440 * .y = DimIndirect.SwizzleX
1441 */
1442 if (reg->Dimension.Indirect) {
1443 union tgsi_exec_channel index2;
1444 union tgsi_exec_channel indir_index;
1445 const uint execmask = mach->ExecMask;
1446 uint i;
1447
1448 index2.i[0] =
1449 index2.i[1] =
1450 index2.i[2] =
1451 index2.i[3] = reg->DimIndirect.Index;
1452
1453 swizzle = reg->DimIndirect.Swizzle;
1454 fetch_src_file_channel(mach,
1455 chan_index,
1456 reg->DimIndirect.File,
1457 swizzle,
1458 &index2,
1459 &ZeroVec,
1460 &indir_index);
1461
1462 index2D.i[0] += indir_index.i[0];
1463 index2D.i[1] += indir_index.i[1];
1464 index2D.i[2] += indir_index.i[2];
1465 index2D.i[3] += indir_index.i[3];
1466
1467 /* for disabled execution channels, zero-out the index to
1468 * avoid using a potential garbage value.
1469 */
1470 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1471 if ((execmask & (1 << i)) == 0) {
1472 index2D.i[i] = 0;
1473 }
1474 }
1475 }
1476
1477 /* If by any chance there was a need for a 3D array of register
1478 * files, we would have to check whether Dimension is followed
1479 * by a dimension register and continue the saga.
1480 */
1481 } else {
1482 index2D.i[0] =
1483 index2D.i[1] =
1484 index2D.i[2] =
1485 index2D.i[3] = 0;
1486 }
1487
1488 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1489 fetch_src_file_channel(mach,
1490 chan_index,
1491 reg->Register.File,
1492 swizzle,
1493 &index,
1494 &index2D,
1495 chan);
1496 }
1497
1498 static void
1499 fetch_source(const struct tgsi_exec_machine *mach,
1500 union tgsi_exec_channel *chan,
1501 const struct tgsi_full_src_register *reg,
1502 const uint chan_index,
1503 enum tgsi_exec_datatype src_datatype)
1504 {
1505 fetch_source_d(mach, chan, reg, chan_index, src_datatype);
1506
1507 if (reg->Register.Absolute) {
1508 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1509 micro_abs(chan, chan);
1510 } else {
1511 micro_iabs(chan, chan);
1512 }
1513 }
1514
1515 if (reg->Register.Negate) {
1516 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1517 micro_neg(chan, chan);
1518 } else {
1519 micro_ineg(chan, chan);
1520 }
1521 }
1522 }
1523
1524 static union tgsi_exec_channel *
1525 store_dest_dstret(struct tgsi_exec_machine *mach,
1526 const union tgsi_exec_channel *chan,
1527 const struct tgsi_full_dst_register *reg,
1528 const struct tgsi_full_instruction *inst,
1529 uint chan_index,
1530 enum tgsi_exec_datatype dst_datatype)
1531 {
1532 uint i;
1533 static union tgsi_exec_channel null;
1534 union tgsi_exec_channel *dst;
1535 union tgsi_exec_channel index2D;
1536 uint execmask = mach->ExecMask;
1537 int offset = 0; /* indirection offset */
1538 int index;
1539
1540 /* for debugging */
1541 if (0 && dst_datatype == TGSI_EXEC_DATA_FLOAT) {
1542 check_inf_or_nan(chan);
1543 }
1544
1545 /* There is an extra source register that indirectly subscripts
1546 * a register file. The direct index now becomes an offset
1547 * that is being added to the indirect register.
1548 *
1549 * file[ind[2].x+1],
1550 * where:
1551 * ind = Indirect.File
1552 * [2] = Indirect.Index
1553 * .x = Indirect.SwizzleX
1554 */
1555 if (reg->Register.Indirect) {
1556 union tgsi_exec_channel index;
1557 union tgsi_exec_channel indir_index;
1558 uint swizzle;
1559
1560 /* which address register (always zero for now) */
1561 index.i[0] =
1562 index.i[1] =
1563 index.i[2] =
1564 index.i[3] = reg->Indirect.Index;
1565
1566 /* get current value of address register[swizzle] */
1567 swizzle = reg->Indirect.Swizzle;
1568
1569 /* fetch values from the address/indirection register */
1570 fetch_src_file_channel(mach,
1571 chan_index,
1572 reg->Indirect.File,
1573 swizzle,
1574 &index,
1575 &ZeroVec,
1576 &indir_index);
1577
1578 /* save indirection offset */
1579 offset = indir_index.i[0];
1580 }
1581
1582 /* There is an extra source register that is a second
1583 * subscript to a register file. Effectively it means that
1584 * the register file is actually a 2D array of registers.
1585 *
1586 * file[3][1],
1587 * where:
1588 * [3] = Dimension.Index
1589 */
1590 if (reg->Register.Dimension) {
1591 index2D.i[0] =
1592 index2D.i[1] =
1593 index2D.i[2] =
1594 index2D.i[3] = reg->Dimension.Index;
1595
1596 /* Again, the second subscript index can be addressed indirectly
1597 * identically to the first one.
1598 * Nothing stops us from indirectly addressing the indirect register,
1599 * but there is no need for that, so we won't exercise it.
1600 *
1601 * file[ind[4].y+3][1],
1602 * where:
1603 * ind = DimIndirect.File
1604 * [4] = DimIndirect.Index
1605 * .y = DimIndirect.SwizzleX
1606 */
1607 if (reg->Dimension.Indirect) {
1608 union tgsi_exec_channel index2;
1609 union tgsi_exec_channel indir_index;
1610 const uint execmask = mach->ExecMask;
1611 unsigned swizzle;
1612 uint i;
1613
1614 index2.i[0] =
1615 index2.i[1] =
1616 index2.i[2] =
1617 index2.i[3] = reg->DimIndirect.Index;
1618
1619 swizzle = reg->DimIndirect.Swizzle;
1620 fetch_src_file_channel(mach,
1621 chan_index,
1622 reg->DimIndirect.File,
1623 swizzle,
1624 &index2,
1625 &ZeroVec,
1626 &indir_index);
1627
1628 index2D.i[0] += indir_index.i[0];
1629 index2D.i[1] += indir_index.i[1];
1630 index2D.i[2] += indir_index.i[2];
1631 index2D.i[3] += indir_index.i[3];
1632
1633 /* for disabled execution channels, zero-out the index to
1634 * avoid using a potential garbage value.
1635 */
1636 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1637 if ((execmask & (1 << i)) == 0) {
1638 index2D.i[i] = 0;
1639 }
1640 }
1641 }
1642
1643 /* If by any chance there was a need for a 3D array of register
1644 * files, we would have to check whether Dimension is followed
1645 * by a dimension register and continue the saga.
1646 */
1647 } else {
1648 index2D.i[0] =
1649 index2D.i[1] =
1650 index2D.i[2] =
1651 index2D.i[3] = 0;
1652 }
1653
1654 switch (reg->Register.File) {
1655 case TGSI_FILE_NULL:
1656 dst = &null;
1657 break;
1658
1659 case TGSI_FILE_OUTPUT:
1660 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1661 + reg->Register.Index;
1662 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1663 #if 0
1664 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1665 mach->NumOutputs, mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0],
1666 reg->Register.Index);
1667 if (PIPE_SHADER_GEOMETRY == mach->ShaderType) {
1668 debug_printf("STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1669 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1670 if (execmask & (1 << i))
1671 debug_printf("%f, ", chan->f[i]);
1672 debug_printf(")\n");
1673 }
1674 #endif
1675 break;
1676
1677 case TGSI_FILE_TEMPORARY:
1678 index = reg->Register.Index;
1679 assert( index < TGSI_EXEC_NUM_TEMPS );
1680 dst = &mach->Temps[offset + index].xyzw[chan_index];
1681 break;
1682
1683 case TGSI_FILE_ADDRESS:
1684 index = reg->Register.Index;
1685 dst = &mach->Addrs[index].xyzw[chan_index];
1686 break;
1687
1688 case TGSI_FILE_PREDICATE:
1689 index = reg->Register.Index;
1690 assert(index < TGSI_EXEC_NUM_PREDS);
1691 dst = &mach->Predicates[index].xyzw[chan_index];
1692 break;
1693
1694 default:
1695 assert( 0 );
1696 return NULL;
1697 }
1698
1699 if (inst->Instruction.Predicate) {
1700 uint swizzle;
1701 union tgsi_exec_channel *pred;
1702
1703 switch (chan_index) {
1704 case TGSI_CHAN_X:
1705 swizzle = inst->Predicate.SwizzleX;
1706 break;
1707 case TGSI_CHAN_Y:
1708 swizzle = inst->Predicate.SwizzleY;
1709 break;
1710 case TGSI_CHAN_Z:
1711 swizzle = inst->Predicate.SwizzleZ;
1712 break;
1713 case TGSI_CHAN_W:
1714 swizzle = inst->Predicate.SwizzleW;
1715 break;
1716 default:
1717 assert(0);
1718 return NULL;
1719 }
1720
1721 assert(inst->Predicate.Index == 0);
1722
1723 pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
1724
1725 if (inst->Predicate.Negate) {
1726 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1727 if (pred->u[i]) {
1728 execmask &= ~(1 << i);
1729 }
1730 }
1731 } else {
1732 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1733 if (!pred->u[i]) {
1734 execmask &= ~(1 << i);
1735 }
1736 }
1737 }
1738 }
1739
1740 return dst;
1741 }
1742
1743 static void
1744 store_dest_double(struct tgsi_exec_machine *mach,
1745 const union tgsi_exec_channel *chan,
1746 const struct tgsi_full_dst_register *reg,
1747 const struct tgsi_full_instruction *inst,
1748 uint chan_index,
1749 enum tgsi_exec_datatype dst_datatype)
1750 {
1751 union tgsi_exec_channel *dst;
1752 const uint execmask = mach->ExecMask;
1753 int i;
1754
1755 dst = store_dest_dstret(mach, chan, reg, inst, chan_index,
1756 dst_datatype);
1757 if (!dst)
1758 return;
1759
1760 /* doubles path */
1761 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1762 if (execmask & (1 << i))
1763 dst->i[i] = chan->i[i];
1764 }
1765
1766 static void
1767 store_dest(struct tgsi_exec_machine *mach,
1768 const union tgsi_exec_channel *chan,
1769 const struct tgsi_full_dst_register *reg,
1770 const struct tgsi_full_instruction *inst,
1771 uint chan_index,
1772 enum tgsi_exec_datatype dst_datatype)
1773 {
1774 union tgsi_exec_channel *dst;
1775 const uint execmask = mach->ExecMask;
1776 int i;
1777
1778 dst = store_dest_dstret(mach, chan, reg, inst, chan_index,
1779 dst_datatype);
1780 if (!dst)
1781 return;
1782
1783 if (!inst->Instruction.Saturate) {
1784 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1785 if (execmask & (1 << i))
1786 dst->i[i] = chan->i[i];
1787 }
1788 else {
1789 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1790 if (execmask & (1 << i)) {
1791 if (chan->f[i] < 0.0f)
1792 dst->f[i] = 0.0f;
1793 else if (chan->f[i] > 1.0f)
1794 dst->f[i] = 1.0f;
1795 else
1796 dst->i[i] = chan->i[i];
1797 }
1798 }
1799 }
1800
1801 #define FETCH(VAL,INDEX,CHAN)\
1802 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1803
1804 #define IFETCH(VAL,INDEX,CHAN)\
1805 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1806
1807
1808 /**
1809 * Execute ARB-style KIL which is predicated by a src register.
1810 * Kill fragment if any of the four values is less than zero.
1811 */
1812 static void
1813 exec_kill_if(struct tgsi_exec_machine *mach,
1814 const struct tgsi_full_instruction *inst)
1815 {
1816 uint uniquemask;
1817 uint chan_index;
1818 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1819 union tgsi_exec_channel r[1];
1820
1821 /* This mask stores component bits that were already tested. */
1822 uniquemask = 0;
1823
1824 for (chan_index = 0; chan_index < 4; chan_index++)
1825 {
1826 uint swizzle;
1827 uint i;
1828
1829 /* unswizzle channel */
1830 swizzle = tgsi_util_get_full_src_register_swizzle (
1831 &inst->Src[0],
1832 chan_index);
1833
1834 /* check if the component has not been already tested */
1835 if (uniquemask & (1 << swizzle))
1836 continue;
1837 uniquemask |= 1 << swizzle;
1838
1839 FETCH(&r[0], 0, chan_index);
1840 for (i = 0; i < 4; i++)
1841 if (r[0].f[i] < 0.0f)
1842 kilmask |= 1 << i;
1843 }
1844
1845 /* restrict to fragments currently executing */
1846 kilmask &= mach->ExecMask;
1847
1848 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1849 }
1850
1851 /**
1852 * Unconditional fragment kill/discard.
1853 */
1854 static void
1855 exec_kill(struct tgsi_exec_machine *mach,
1856 const struct tgsi_full_instruction *inst)
1857 {
1858 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1859
1860 /* kill fragment for all fragments currently executing */
1861 kilmask = mach->ExecMask;
1862 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1863 }
1864
1865 static void
1866 emit_vertex(struct tgsi_exec_machine *mach)
1867 {
1868 /* FIXME: check for exec mask correctly
1869 unsigned i;
1870 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1871 if ((mach->ExecMask & (1 << i)))
1872 */
1873 if (mach->ExecMask) {
1874 if (mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]] >= mach->MaxOutputVertices)
1875 return;
1876
1877 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += mach->NumOutputs;
1878 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
1879 }
1880 }
1881
1882 static void
1883 emit_primitive(struct tgsi_exec_machine *mach)
1884 {
1885 unsigned *prim_count = &mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0];
1886 /* FIXME: check for exec mask correctly
1887 unsigned i;
1888 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1889 if ((mach->ExecMask & (1 << i)))
1890 */
1891 if (mach->ExecMask) {
1892 ++(*prim_count);
1893 debug_assert((*prim_count * mach->NumOutputs) < mach->MaxGeometryShaderOutputs);
1894 mach->Primitives[*prim_count] = 0;
1895 }
1896 }
1897
1898 static void
1899 conditional_emit_primitive(struct tgsi_exec_machine *mach)
1900 {
1901 if (PIPE_SHADER_GEOMETRY == mach->ShaderType) {
1902 int emitted_verts =
1903 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]];
1904 if (emitted_verts) {
1905 emit_primitive(mach);
1906 }
1907 }
1908 }
1909
1910
1911 /*
1912 * Fetch four texture samples using STR texture coordinates.
1913 */
1914 static void
1915 fetch_texel( struct tgsi_sampler *sampler,
1916 const unsigned sview_idx,
1917 const unsigned sampler_idx,
1918 const union tgsi_exec_channel *s,
1919 const union tgsi_exec_channel *t,
1920 const union tgsi_exec_channel *p,
1921 const union tgsi_exec_channel *c0,
1922 const union tgsi_exec_channel *c1,
1923 float derivs[3][2][TGSI_QUAD_SIZE],
1924 const int8_t offset[3],
1925 enum tgsi_sampler_control control,
1926 union tgsi_exec_channel *r,
1927 union tgsi_exec_channel *g,
1928 union tgsi_exec_channel *b,
1929 union tgsi_exec_channel *a )
1930 {
1931 uint j;
1932 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
1933
1934 /* FIXME: handle explicit derivs, offsets */
1935 sampler->get_samples(sampler, sview_idx, sampler_idx,
1936 s->f, t->f, p->f, c0->f, c1->f, derivs, offset, control, rgba);
1937
1938 for (j = 0; j < 4; j++) {
1939 r->f[j] = rgba[0][j];
1940 g->f[j] = rgba[1][j];
1941 b->f[j] = rgba[2][j];
1942 a->f[j] = rgba[3][j];
1943 }
1944 }
1945
1946
1947 #define TEX_MODIFIER_NONE 0
1948 #define TEX_MODIFIER_PROJECTED 1
1949 #define TEX_MODIFIER_LOD_BIAS 2
1950 #define TEX_MODIFIER_EXPLICIT_LOD 3
1951 #define TEX_MODIFIER_LEVEL_ZERO 4
1952 #define TEX_MODIFIER_GATHER 5
1953
1954 /*
1955 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
1956 */
1957 static void
1958 fetch_texel_offsets(struct tgsi_exec_machine *mach,
1959 const struct tgsi_full_instruction *inst,
1960 int8_t offsets[3])
1961 {
1962 if (inst->Texture.NumOffsets == 1) {
1963 union tgsi_exec_channel index;
1964 union tgsi_exec_channel offset[3];
1965 index.i[0] = index.i[1] = index.i[2] = index.i[3] = inst->TexOffsets[0].Index;
1966 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1967 inst->TexOffsets[0].SwizzleX, &index, &ZeroVec, &offset[0]);
1968 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1969 inst->TexOffsets[0].SwizzleY, &index, &ZeroVec, &offset[1]);
1970 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1971 inst->TexOffsets[0].SwizzleZ, &index, &ZeroVec, &offset[2]);
1972 offsets[0] = offset[0].i[0];
1973 offsets[1] = offset[1].i[0];
1974 offsets[2] = offset[2].i[0];
1975 } else {
1976 assert(inst->Texture.NumOffsets == 0);
1977 offsets[0] = offsets[1] = offsets[2] = 0;
1978 }
1979 }
1980
1981
1982 /*
1983 * Fetch dx and dy values for one channel (s, t or r).
1984 * Put dx values into one float array, dy values into another.
1985 */
1986 static void
1987 fetch_assign_deriv_channel(struct tgsi_exec_machine *mach,
1988 const struct tgsi_full_instruction *inst,
1989 unsigned regdsrcx,
1990 unsigned chan,
1991 float derivs[2][TGSI_QUAD_SIZE])
1992 {
1993 union tgsi_exec_channel d;
1994 FETCH(&d, regdsrcx, chan);
1995 derivs[0][0] = d.f[0];
1996 derivs[0][1] = d.f[1];
1997 derivs[0][2] = d.f[2];
1998 derivs[0][3] = d.f[3];
1999 FETCH(&d, regdsrcx + 1, chan);
2000 derivs[1][0] = d.f[0];
2001 derivs[1][1] = d.f[1];
2002 derivs[1][2] = d.f[2];
2003 derivs[1][3] = d.f[3];
2004 }
2005
2006 static uint
2007 fetch_sampler_unit(struct tgsi_exec_machine *mach,
2008 const struct tgsi_full_instruction *inst,
2009 uint sampler)
2010 {
2011 uint unit = 0;
2012 int i;
2013 if (inst->Src[sampler].Register.Indirect) {
2014 const struct tgsi_full_src_register *reg = &inst->Src[sampler];
2015 union tgsi_exec_channel indir_index, index2;
2016 const uint execmask = mach->ExecMask;
2017 index2.i[0] =
2018 index2.i[1] =
2019 index2.i[2] =
2020 index2.i[3] = reg->Indirect.Index;
2021
2022 fetch_src_file_channel(mach,
2023 0,
2024 reg->Indirect.File,
2025 reg->Indirect.Swizzle,
2026 &index2,
2027 &ZeroVec,
2028 &indir_index);
2029 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2030 if (execmask & (1 << i)) {
2031 unit = inst->Src[sampler].Register.Index + indir_index.i[i];
2032 break;
2033 }
2034 }
2035
2036 } else {
2037 unit = inst->Src[sampler].Register.Index;
2038 }
2039 return unit;
2040 }
2041
2042 /*
2043 * execute a texture instruction.
2044 *
2045 * modifier is used to control the channel routing for the
2046 * instruction variants like proj, lod, and texture with lod bias.
2047 * sampler indicates which src register the sampler is contained in.
2048 */
2049 static void
2050 exec_tex(struct tgsi_exec_machine *mach,
2051 const struct tgsi_full_instruction *inst,
2052 uint modifier, uint sampler)
2053 {
2054 const union tgsi_exec_channel *args[5], *proj = NULL;
2055 union tgsi_exec_channel r[5];
2056 enum tgsi_sampler_control control = TGSI_SAMPLER_LOD_NONE;
2057 uint chan;
2058 uint unit;
2059 int8_t offsets[3];
2060 int dim, shadow_ref, i;
2061
2062 unit = fetch_sampler_unit(mach, inst, sampler);
2063 /* always fetch all 3 offsets, overkill but keeps code simple */
2064 fetch_texel_offsets(mach, inst, offsets);
2065
2066 assert(modifier != TEX_MODIFIER_LEVEL_ZERO);
2067 assert(inst->Texture.Texture != TGSI_TEXTURE_BUFFER);
2068
2069 dim = tgsi_util_get_texture_coord_dim(inst->Texture.Texture);
2070 shadow_ref = tgsi_util_get_shadow_ref_src_index(inst->Texture.Texture);
2071
2072 assert(dim <= 4);
2073 if (shadow_ref >= 0)
2074 assert(shadow_ref >= dim && shadow_ref < ARRAY_SIZE(args));
2075
2076 /* fetch modifier to the last argument */
2077 if (modifier != TEX_MODIFIER_NONE) {
2078 const int last = ARRAY_SIZE(args) - 1;
2079
2080 /* fetch modifier from src0.w or src1.x */
2081 if (sampler == 1) {
2082 assert(dim <= TGSI_CHAN_W && shadow_ref != TGSI_CHAN_W);
2083 FETCH(&r[last], 0, TGSI_CHAN_W);
2084 }
2085 else {
2086 assert(shadow_ref != 4);
2087 FETCH(&r[last], 1, TGSI_CHAN_X);
2088 }
2089
2090 if (modifier != TEX_MODIFIER_PROJECTED) {
2091 args[last] = &r[last];
2092 }
2093 else {
2094 proj = &r[last];
2095 args[last] = &ZeroVec;
2096 }
2097
2098 /* point unused arguments to zero vector */
2099 for (i = dim; i < last; i++)
2100 args[i] = &ZeroVec;
2101
2102 if (modifier == TEX_MODIFIER_EXPLICIT_LOD)
2103 control = TGSI_SAMPLER_LOD_EXPLICIT;
2104 else if (modifier == TEX_MODIFIER_LOD_BIAS)
2105 control = TGSI_SAMPLER_LOD_BIAS;
2106 else if (modifier == TEX_MODIFIER_GATHER)
2107 control = TGSI_SAMPLER_GATHER;
2108 }
2109 else {
2110 for (i = dim; i < ARRAY_SIZE(args); i++)
2111 args[i] = &ZeroVec;
2112 }
2113
2114 /* fetch coordinates */
2115 for (i = 0; i < dim; i++) {
2116 FETCH(&r[i], 0, TGSI_CHAN_X + i);
2117
2118 if (proj)
2119 micro_div(&r[i], &r[i], proj);
2120
2121 args[i] = &r[i];
2122 }
2123
2124 /* fetch reference value */
2125 if (shadow_ref >= 0) {
2126 FETCH(&r[shadow_ref], shadow_ref / 4, TGSI_CHAN_X + (shadow_ref % 4));
2127
2128 if (proj)
2129 micro_div(&r[shadow_ref], &r[shadow_ref], proj);
2130
2131 args[shadow_ref] = &r[shadow_ref];
2132 }
2133
2134 fetch_texel(mach->Sampler, unit, unit,
2135 args[0], args[1], args[2], args[3], args[4],
2136 NULL, offsets, control,
2137 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2138
2139 #if 0
2140 debug_printf("fetch r: %g %g %g %g\n",
2141 r[0].f[0], r[0].f[1], r[0].f[2], r[0].f[3]);
2142 debug_printf("fetch g: %g %g %g %g\n",
2143 r[1].f[0], r[1].f[1], r[1].f[2], r[1].f[3]);
2144 debug_printf("fetch b: %g %g %g %g\n",
2145 r[2].f[0], r[2].f[1], r[2].f[2], r[2].f[3]);
2146 debug_printf("fetch a: %g %g %g %g\n",
2147 r[3].f[0], r[3].f[1], r[3].f[2], r[3].f[3]);
2148 #endif
2149
2150 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2151 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2152 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2153 }
2154 }
2155 }
2156
2157 static void
2158 exec_lodq(struct tgsi_exec_machine *mach,
2159 const struct tgsi_full_instruction *inst)
2160 {
2161 uint unit;
2162 int dim;
2163 int i;
2164 union tgsi_exec_channel coords[4];
2165 const union tgsi_exec_channel *args[ARRAY_SIZE(coords)];
2166 union tgsi_exec_channel r[2];
2167
2168 unit = fetch_sampler_unit(mach, inst, 1);
2169 dim = tgsi_util_get_texture_coord_dim(inst->Texture.Texture);
2170 assert(dim <= ARRAY_SIZE(coords));
2171 /* fetch coordinates */
2172 for (i = 0; i < dim; i++) {
2173 FETCH(&coords[i], 0, TGSI_CHAN_X + i);
2174 args[i] = &coords[i];
2175 }
2176 for (i = dim; i < ARRAY_SIZE(coords); i++) {
2177 args[i] = &ZeroVec;
2178 }
2179 mach->Sampler->query_lod(mach->Sampler, unit, unit,
2180 args[0]->f,
2181 args[1]->f,
2182 args[2]->f,
2183 args[3]->f,
2184 TGSI_SAMPLER_LOD_NONE,
2185 r[0].f,
2186 r[1].f);
2187
2188 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2189 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_X,
2190 TGSI_EXEC_DATA_FLOAT);
2191 }
2192 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2193 store_dest(mach, &r[1], &inst->Dst[0], inst, TGSI_CHAN_Y,
2194 TGSI_EXEC_DATA_FLOAT);
2195 }
2196 }
2197
2198 static void
2199 exec_txd(struct tgsi_exec_machine *mach,
2200 const struct tgsi_full_instruction *inst)
2201 {
2202 union tgsi_exec_channel r[4];
2203 float derivs[3][2][TGSI_QUAD_SIZE];
2204 uint chan;
2205 uint unit;
2206 int8_t offsets[3];
2207
2208 unit = fetch_sampler_unit(mach, inst, 3);
2209 /* always fetch all 3 offsets, overkill but keeps code simple */
2210 fetch_texel_offsets(mach, inst, offsets);
2211
2212 switch (inst->Texture.Texture) {
2213 case TGSI_TEXTURE_1D:
2214 FETCH(&r[0], 0, TGSI_CHAN_X);
2215
2216 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2217
2218 fetch_texel(mach->Sampler, unit, unit,
2219 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2220 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2221 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2222 break;
2223
2224 case TGSI_TEXTURE_SHADOW1D:
2225 case TGSI_TEXTURE_1D_ARRAY:
2226 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2227 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
2228 FETCH(&r[0], 0, TGSI_CHAN_X);
2229 FETCH(&r[1], 0, TGSI_CHAN_Y);
2230 FETCH(&r[2], 0, TGSI_CHAN_Z);
2231
2232 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2233
2234 fetch_texel(mach->Sampler, unit, unit,
2235 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2236 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2237 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2238 break;
2239
2240 case TGSI_TEXTURE_2D:
2241 case TGSI_TEXTURE_RECT:
2242 FETCH(&r[0], 0, TGSI_CHAN_X);
2243 FETCH(&r[1], 0, TGSI_CHAN_Y);
2244
2245 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2246 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2247
2248 fetch_texel(mach->Sampler, unit, unit,
2249 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2250 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2251 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2252 break;
2253
2254
2255 case TGSI_TEXTURE_SHADOW2D:
2256 case TGSI_TEXTURE_SHADOWRECT:
2257 case TGSI_TEXTURE_2D_ARRAY:
2258 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2259 /* only SHADOW2D_ARRAY actually needs W */
2260 FETCH(&r[0], 0, TGSI_CHAN_X);
2261 FETCH(&r[1], 0, TGSI_CHAN_Y);
2262 FETCH(&r[2], 0, TGSI_CHAN_Z);
2263 FETCH(&r[3], 0, TGSI_CHAN_W);
2264
2265 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2266 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2267
2268 fetch_texel(mach->Sampler, unit, unit,
2269 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
2270 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2271 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2272 break;
2273
2274 case TGSI_TEXTURE_3D:
2275 case TGSI_TEXTURE_CUBE:
2276 case TGSI_TEXTURE_CUBE_ARRAY:
2277 case TGSI_TEXTURE_SHADOWCUBE:
2278 /* only TEXTURE_CUBE_ARRAY and TEXTURE_SHADOWCUBE actually need W */
2279 FETCH(&r[0], 0, TGSI_CHAN_X);
2280 FETCH(&r[1], 0, TGSI_CHAN_Y);
2281 FETCH(&r[2], 0, TGSI_CHAN_Z);
2282 FETCH(&r[3], 0, TGSI_CHAN_W);
2283
2284 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2285 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2286 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Z, derivs[2]);
2287
2288 fetch_texel(mach->Sampler, unit, unit,
2289 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
2290 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2291 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2292 break;
2293
2294 default:
2295 assert(0);
2296 }
2297
2298 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2299 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2300 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2301 }
2302 }
2303 }
2304
2305
2306 static void
2307 exec_txf(struct tgsi_exec_machine *mach,
2308 const struct tgsi_full_instruction *inst)
2309 {
2310 union tgsi_exec_channel r[4];
2311 uint chan;
2312 uint unit;
2313 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
2314 int j;
2315 int8_t offsets[3];
2316 unsigned target;
2317
2318 unit = fetch_sampler_unit(mach, inst, 1);
2319 /* always fetch all 3 offsets, overkill but keeps code simple */
2320 fetch_texel_offsets(mach, inst, offsets);
2321
2322 IFETCH(&r[3], 0, TGSI_CHAN_W);
2323
2324 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I ||
2325 inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I_MS) {
2326 target = mach->SamplerViews[unit].Resource;
2327 }
2328 else {
2329 target = inst->Texture.Texture;
2330 }
2331 switch(target) {
2332 case TGSI_TEXTURE_3D:
2333 case TGSI_TEXTURE_2D_ARRAY:
2334 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2335 case TGSI_TEXTURE_2D_ARRAY_MSAA:
2336 IFETCH(&r[2], 0, TGSI_CHAN_Z);
2337 /* fallthrough */
2338 case TGSI_TEXTURE_2D:
2339 case TGSI_TEXTURE_RECT:
2340 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2341 case TGSI_TEXTURE_SHADOW2D:
2342 case TGSI_TEXTURE_SHADOWRECT:
2343 case TGSI_TEXTURE_1D_ARRAY:
2344 case TGSI_TEXTURE_2D_MSAA:
2345 IFETCH(&r[1], 0, TGSI_CHAN_Y);
2346 /* fallthrough */
2347 case TGSI_TEXTURE_BUFFER:
2348 case TGSI_TEXTURE_1D:
2349 case TGSI_TEXTURE_SHADOW1D:
2350 IFETCH(&r[0], 0, TGSI_CHAN_X);
2351 break;
2352 default:
2353 assert(0);
2354 break;
2355 }
2356
2357 mach->Sampler->get_texel(mach->Sampler, unit, r[0].i, r[1].i, r[2].i, r[3].i,
2358 offsets, rgba);
2359
2360 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
2361 r[0].f[j] = rgba[0][j];
2362 r[1].f[j] = rgba[1][j];
2363 r[2].f[j] = rgba[2][j];
2364 r[3].f[j] = rgba[3][j];
2365 }
2366
2367 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I ||
2368 inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I_MS) {
2369 unsigned char swizzles[4];
2370 swizzles[0] = inst->Src[1].Register.SwizzleX;
2371 swizzles[1] = inst->Src[1].Register.SwizzleY;
2372 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2373 swizzles[3] = inst->Src[1].Register.SwizzleW;
2374
2375 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2376 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2377 store_dest(mach, &r[swizzles[chan]],
2378 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2379 }
2380 }
2381 }
2382 else {
2383 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2384 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2385 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2386 }
2387 }
2388 }
2389 }
2390
2391 static void
2392 exec_txq(struct tgsi_exec_machine *mach,
2393 const struct tgsi_full_instruction *inst)
2394 {
2395 int result[4];
2396 union tgsi_exec_channel r[4], src;
2397 uint chan;
2398 uint unit;
2399 int i,j;
2400
2401 unit = fetch_sampler_unit(mach, inst, 1);
2402
2403 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
2404
2405 /* XXX: This interface can't return per-pixel values */
2406 mach->Sampler->get_dims(mach->Sampler, unit, src.i[0], result);
2407
2408 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2409 for (j = 0; j < 4; j++) {
2410 r[j].i[i] = result[j];
2411 }
2412 }
2413
2414 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2415 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2416 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
2417 TGSI_EXEC_DATA_INT);
2418 }
2419 }
2420 }
2421
2422 static void
2423 exec_sample(struct tgsi_exec_machine *mach,
2424 const struct tgsi_full_instruction *inst,
2425 uint modifier, boolean compare)
2426 {
2427 const uint resource_unit = inst->Src[1].Register.Index;
2428 const uint sampler_unit = inst->Src[2].Register.Index;
2429 union tgsi_exec_channel r[5], c1;
2430 const union tgsi_exec_channel *lod = &ZeroVec;
2431 enum tgsi_sampler_control control = TGSI_SAMPLER_LOD_NONE;
2432 uint chan;
2433 unsigned char swizzles[4];
2434 int8_t offsets[3];
2435
2436 /* always fetch all 3 offsets, overkill but keeps code simple */
2437 fetch_texel_offsets(mach, inst, offsets);
2438
2439 assert(modifier != TEX_MODIFIER_PROJECTED);
2440
2441 if (modifier != TEX_MODIFIER_NONE) {
2442 if (modifier == TEX_MODIFIER_LOD_BIAS) {
2443 FETCH(&c1, 3, TGSI_CHAN_X);
2444 lod = &c1;
2445 control = TGSI_SAMPLER_LOD_BIAS;
2446 }
2447 else if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
2448 FETCH(&c1, 3, TGSI_CHAN_X);
2449 lod = &c1;
2450 control = TGSI_SAMPLER_LOD_EXPLICIT;
2451 }
2452 else {
2453 assert(modifier == TEX_MODIFIER_LEVEL_ZERO);
2454 control = TGSI_SAMPLER_LOD_ZERO;
2455 }
2456 }
2457
2458 FETCH(&r[0], 0, TGSI_CHAN_X);
2459
2460 switch (mach->SamplerViews[resource_unit].Resource) {
2461 case TGSI_TEXTURE_1D:
2462 if (compare) {
2463 FETCH(&r[2], 3, TGSI_CHAN_X);
2464 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2465 &r[0], &ZeroVec, &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2466 NULL, offsets, control,
2467 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2468 }
2469 else {
2470 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2471 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2472 NULL, offsets, control,
2473 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2474 }
2475 break;
2476
2477 case TGSI_TEXTURE_1D_ARRAY:
2478 case TGSI_TEXTURE_2D:
2479 case TGSI_TEXTURE_RECT:
2480 FETCH(&r[1], 0, TGSI_CHAN_Y);
2481 if (compare) {
2482 FETCH(&r[2], 3, TGSI_CHAN_X);
2483 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2484 &r[0], &r[1], &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2485 NULL, offsets, control,
2486 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2487 }
2488 else {
2489 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2490 &r[0], &r[1], &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2491 NULL, offsets, control,
2492 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2493 }
2494 break;
2495
2496 case TGSI_TEXTURE_2D_ARRAY:
2497 case TGSI_TEXTURE_3D:
2498 case TGSI_TEXTURE_CUBE:
2499 FETCH(&r[1], 0, TGSI_CHAN_Y);
2500 FETCH(&r[2], 0, TGSI_CHAN_Z);
2501 if(compare) {
2502 FETCH(&r[3], 3, TGSI_CHAN_X);
2503 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2504 &r[0], &r[1], &r[2], &r[3], lod,
2505 NULL, offsets, control,
2506 &r[0], &r[1], &r[2], &r[3]);
2507 }
2508 else {
2509 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2510 &r[0], &r[1], &r[2], &ZeroVec, lod,
2511 NULL, offsets, control,
2512 &r[0], &r[1], &r[2], &r[3]);
2513 }
2514 break;
2515
2516 case TGSI_TEXTURE_CUBE_ARRAY:
2517 FETCH(&r[1], 0, TGSI_CHAN_Y);
2518 FETCH(&r[2], 0, TGSI_CHAN_Z);
2519 FETCH(&r[3], 0, TGSI_CHAN_W);
2520 if(compare) {
2521 FETCH(&r[4], 3, TGSI_CHAN_X);
2522 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2523 &r[0], &r[1], &r[2], &r[3], &r[4],
2524 NULL, offsets, control,
2525 &r[0], &r[1], &r[2], &r[3]);
2526 }
2527 else {
2528 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2529 &r[0], &r[1], &r[2], &r[3], lod,
2530 NULL, offsets, control,
2531 &r[0], &r[1], &r[2], &r[3]);
2532 }
2533 break;
2534
2535
2536 default:
2537 assert(0);
2538 }
2539
2540 swizzles[0] = inst->Src[1].Register.SwizzleX;
2541 swizzles[1] = inst->Src[1].Register.SwizzleY;
2542 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2543 swizzles[3] = inst->Src[1].Register.SwizzleW;
2544
2545 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2546 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2547 store_dest(mach, &r[swizzles[chan]],
2548 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2549 }
2550 }
2551 }
2552
2553 static void
2554 exec_sample_d(struct tgsi_exec_machine *mach,
2555 const struct tgsi_full_instruction *inst)
2556 {
2557 const uint resource_unit = inst->Src[1].Register.Index;
2558 const uint sampler_unit = inst->Src[2].Register.Index;
2559 union tgsi_exec_channel r[4];
2560 float derivs[3][2][TGSI_QUAD_SIZE];
2561 uint chan;
2562 unsigned char swizzles[4];
2563 int8_t offsets[3];
2564
2565 /* always fetch all 3 offsets, overkill but keeps code simple */
2566 fetch_texel_offsets(mach, inst, offsets);
2567
2568 FETCH(&r[0], 0, TGSI_CHAN_X);
2569
2570 switch (mach->SamplerViews[resource_unit].Resource) {
2571 case TGSI_TEXTURE_1D:
2572 case TGSI_TEXTURE_1D_ARRAY:
2573 /* only 1D array actually needs Y */
2574 FETCH(&r[1], 0, TGSI_CHAN_Y);
2575
2576 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2577
2578 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2579 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2580 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2581 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2582 break;
2583
2584 case TGSI_TEXTURE_2D:
2585 case TGSI_TEXTURE_RECT:
2586 case TGSI_TEXTURE_2D_ARRAY:
2587 /* only 2D array actually needs Z */
2588 FETCH(&r[1], 0, TGSI_CHAN_Y);
2589 FETCH(&r[2], 0, TGSI_CHAN_Z);
2590
2591 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2592 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2593
2594 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2595 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* inputs */
2596 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2597 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2598 break;
2599
2600 case TGSI_TEXTURE_3D:
2601 case TGSI_TEXTURE_CUBE:
2602 case TGSI_TEXTURE_CUBE_ARRAY:
2603 /* only cube array actually needs W */
2604 FETCH(&r[1], 0, TGSI_CHAN_Y);
2605 FETCH(&r[2], 0, TGSI_CHAN_Z);
2606 FETCH(&r[3], 0, TGSI_CHAN_W);
2607
2608 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2609 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2610 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Z, derivs[2]);
2611
2612 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2613 &r[0], &r[1], &r[2], &r[3], &ZeroVec,
2614 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2615 &r[0], &r[1], &r[2], &r[3]);
2616 break;
2617
2618 default:
2619 assert(0);
2620 }
2621
2622 swizzles[0] = inst->Src[1].Register.SwizzleX;
2623 swizzles[1] = inst->Src[1].Register.SwizzleY;
2624 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2625 swizzles[3] = inst->Src[1].Register.SwizzleW;
2626
2627 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2628 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2629 store_dest(mach, &r[swizzles[chan]],
2630 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2631 }
2632 }
2633 }
2634
2635
2636 /**
2637 * Evaluate a constant-valued coefficient at the position of the
2638 * current quad.
2639 */
2640 static void
2641 eval_constant_coef(
2642 struct tgsi_exec_machine *mach,
2643 unsigned attrib,
2644 unsigned chan )
2645 {
2646 unsigned i;
2647
2648 for( i = 0; i < TGSI_QUAD_SIZE; i++ ) {
2649 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
2650 }
2651 }
2652
2653 /**
2654 * Evaluate a linear-valued coefficient at the position of the
2655 * current quad.
2656 */
2657 static void
2658 eval_linear_coef(
2659 struct tgsi_exec_machine *mach,
2660 unsigned attrib,
2661 unsigned chan )
2662 {
2663 const float x = mach->QuadPos.xyzw[0].f[0];
2664 const float y = mach->QuadPos.xyzw[1].f[0];
2665 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2666 const float dady = mach->InterpCoefs[attrib].dady[chan];
2667 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2668 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
2669 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
2670 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
2671 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
2672 }
2673
2674 /**
2675 * Evaluate a perspective-valued coefficient at the position of the
2676 * current quad.
2677 */
2678 static void
2679 eval_perspective_coef(
2680 struct tgsi_exec_machine *mach,
2681 unsigned attrib,
2682 unsigned chan )
2683 {
2684 const float x = mach->QuadPos.xyzw[0].f[0];
2685 const float y = mach->QuadPos.xyzw[1].f[0];
2686 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2687 const float dady = mach->InterpCoefs[attrib].dady[chan];
2688 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2689 const float *w = mach->QuadPos.xyzw[3].f;
2690 /* divide by W here */
2691 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
2692 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
2693 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
2694 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
2695 }
2696
2697
2698 typedef void (* eval_coef_func)(
2699 struct tgsi_exec_machine *mach,
2700 unsigned attrib,
2701 unsigned chan );
2702
2703 static void
2704 exec_declaration(struct tgsi_exec_machine *mach,
2705 const struct tgsi_full_declaration *decl)
2706 {
2707 if (decl->Declaration.File == TGSI_FILE_SAMPLER_VIEW) {
2708 mach->SamplerViews[decl->Range.First] = decl->SamplerView;
2709 return;
2710 }
2711
2712 if (mach->ShaderType == PIPE_SHADER_FRAGMENT) {
2713 if (decl->Declaration.File == TGSI_FILE_INPUT) {
2714 uint first, last, mask;
2715
2716 first = decl->Range.First;
2717 last = decl->Range.Last;
2718 mask = decl->Declaration.UsageMask;
2719
2720 /* XXX we could remove this special-case code since
2721 * mach->InterpCoefs[first].a0 should already have the
2722 * front/back-face value. But we should first update the
2723 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2724 * Then, we could remove the tgsi_exec_machine::Face field.
2725 */
2726 /* XXX make FACE a system value */
2727 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
2728 uint i;
2729
2730 assert(decl->Semantic.Index == 0);
2731 assert(first == last);
2732
2733 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2734 mach->Inputs[first].xyzw[0].f[i] = mach->Face;
2735 }
2736 } else {
2737 eval_coef_func eval;
2738 uint i, j;
2739
2740 switch (decl->Interp.Interpolate) {
2741 case TGSI_INTERPOLATE_CONSTANT:
2742 eval = eval_constant_coef;
2743 break;
2744
2745 case TGSI_INTERPOLATE_LINEAR:
2746 eval = eval_linear_coef;
2747 break;
2748
2749 case TGSI_INTERPOLATE_PERSPECTIVE:
2750 eval = eval_perspective_coef;
2751 break;
2752
2753 case TGSI_INTERPOLATE_COLOR:
2754 eval = mach->flatshade_color ? eval_constant_coef : eval_perspective_coef;
2755 break;
2756
2757 default:
2758 assert(0);
2759 return;
2760 }
2761
2762 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2763 if (mask & (1 << j)) {
2764 for (i = first; i <= last; i++) {
2765 eval(mach, i, j);
2766 }
2767 }
2768 }
2769 }
2770
2771 if (DEBUG_EXECUTION) {
2772 uint i, j;
2773 for (i = first; i <= last; ++i) {
2774 debug_printf("IN[%2u] = ", i);
2775 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2776 if (j > 0) {
2777 debug_printf(" ");
2778 }
2779 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
2780 mach->Inputs[i].xyzw[0].f[j], mach->Inputs[i].xyzw[0].u[j],
2781 mach->Inputs[i].xyzw[1].f[j], mach->Inputs[i].xyzw[1].u[j],
2782 mach->Inputs[i].xyzw[2].f[j], mach->Inputs[i].xyzw[2].u[j],
2783 mach->Inputs[i].xyzw[3].f[j], mach->Inputs[i].xyzw[3].u[j]);
2784 }
2785 }
2786 }
2787 }
2788 }
2789
2790 }
2791
2792 typedef void (* micro_unary_op)(union tgsi_exec_channel *dst,
2793 const union tgsi_exec_channel *src);
2794
2795 static void
2796 exec_scalar_unary(struct tgsi_exec_machine *mach,
2797 const struct tgsi_full_instruction *inst,
2798 micro_unary_op op,
2799 enum tgsi_exec_datatype dst_datatype,
2800 enum tgsi_exec_datatype src_datatype)
2801 {
2802 unsigned int chan;
2803 union tgsi_exec_channel src;
2804 union tgsi_exec_channel dst;
2805
2806 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, src_datatype);
2807 op(&dst, &src);
2808 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2809 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2810 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2811 }
2812 }
2813 }
2814
2815 static void
2816 exec_vector_unary(struct tgsi_exec_machine *mach,
2817 const struct tgsi_full_instruction *inst,
2818 micro_unary_op op,
2819 enum tgsi_exec_datatype dst_datatype,
2820 enum tgsi_exec_datatype src_datatype)
2821 {
2822 unsigned int chan;
2823 struct tgsi_exec_vector dst;
2824
2825 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2826 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2827 union tgsi_exec_channel src;
2828
2829 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
2830 op(&dst.xyzw[chan], &src);
2831 }
2832 }
2833 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2834 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2835 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2836 }
2837 }
2838 }
2839
2840 typedef void (* micro_binary_op)(union tgsi_exec_channel *dst,
2841 const union tgsi_exec_channel *src0,
2842 const union tgsi_exec_channel *src1);
2843
2844 static void
2845 exec_scalar_binary(struct tgsi_exec_machine *mach,
2846 const struct tgsi_full_instruction *inst,
2847 micro_binary_op op,
2848 enum tgsi_exec_datatype dst_datatype,
2849 enum tgsi_exec_datatype src_datatype)
2850 {
2851 unsigned int chan;
2852 union tgsi_exec_channel src[2];
2853 union tgsi_exec_channel dst;
2854
2855 fetch_source(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, src_datatype);
2856 fetch_source(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, src_datatype);
2857 op(&dst, &src[0], &src[1]);
2858 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2859 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2860 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2861 }
2862 }
2863 }
2864
2865 static void
2866 exec_vector_binary(struct tgsi_exec_machine *mach,
2867 const struct tgsi_full_instruction *inst,
2868 micro_binary_op op,
2869 enum tgsi_exec_datatype dst_datatype,
2870 enum tgsi_exec_datatype src_datatype)
2871 {
2872 unsigned int chan;
2873 struct tgsi_exec_vector dst;
2874
2875 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2876 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2877 union tgsi_exec_channel src[2];
2878
2879 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2880 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2881 op(&dst.xyzw[chan], &src[0], &src[1]);
2882 }
2883 }
2884 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2885 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2886 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2887 }
2888 }
2889 }
2890
2891 typedef void (* micro_trinary_op)(union tgsi_exec_channel *dst,
2892 const union tgsi_exec_channel *src0,
2893 const union tgsi_exec_channel *src1,
2894 const union tgsi_exec_channel *src2);
2895
2896 static void
2897 exec_vector_trinary(struct tgsi_exec_machine *mach,
2898 const struct tgsi_full_instruction *inst,
2899 micro_trinary_op op,
2900 enum tgsi_exec_datatype dst_datatype,
2901 enum tgsi_exec_datatype src_datatype)
2902 {
2903 unsigned int chan;
2904 struct tgsi_exec_vector dst;
2905
2906 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2907 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2908 union tgsi_exec_channel src[3];
2909
2910 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2911 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2912 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2913 op(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
2914 }
2915 }
2916 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2917 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2918 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2919 }
2920 }
2921 }
2922
2923 typedef void (* micro_quaternary_op)(union tgsi_exec_channel *dst,
2924 const union tgsi_exec_channel *src0,
2925 const union tgsi_exec_channel *src1,
2926 const union tgsi_exec_channel *src2,
2927 const union tgsi_exec_channel *src3);
2928
2929 static void
2930 exec_vector_quaternary(struct tgsi_exec_machine *mach,
2931 const struct tgsi_full_instruction *inst,
2932 micro_quaternary_op op,
2933 enum tgsi_exec_datatype dst_datatype,
2934 enum tgsi_exec_datatype src_datatype)
2935 {
2936 unsigned int chan;
2937 struct tgsi_exec_vector dst;
2938
2939 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2940 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2941 union tgsi_exec_channel src[4];
2942
2943 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2944 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2945 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2946 fetch_source(mach, &src[3], &inst->Src[3], chan, src_datatype);
2947 op(&dst.xyzw[chan], &src[0], &src[1], &src[2], &src[3]);
2948 }
2949 }
2950 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2951 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2952 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2953 }
2954 }
2955 }
2956
2957 static void
2958 exec_dp3(struct tgsi_exec_machine *mach,
2959 const struct tgsi_full_instruction *inst)
2960 {
2961 unsigned int chan;
2962 union tgsi_exec_channel arg[3];
2963
2964 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2965 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2966 micro_mul(&arg[2], &arg[0], &arg[1]);
2967
2968 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_Z; chan++) {
2969 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2970 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2971 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2972 }
2973
2974 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2975 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2976 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2977 }
2978 }
2979 }
2980
2981 static void
2982 exec_dp4(struct tgsi_exec_machine *mach,
2983 const struct tgsi_full_instruction *inst)
2984 {
2985 unsigned int chan;
2986 union tgsi_exec_channel arg[3];
2987
2988 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2989 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2990 micro_mul(&arg[2], &arg[0], &arg[1]);
2991
2992 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_W; chan++) {
2993 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2994 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2995 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2996 }
2997
2998 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2999 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3000 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3001 }
3002 }
3003 }
3004
3005 static void
3006 exec_dp2a(struct tgsi_exec_machine *mach,
3007 const struct tgsi_full_instruction *inst)
3008 {
3009 unsigned int chan;
3010 union tgsi_exec_channel arg[3];
3011
3012 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3013 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3014 micro_mul(&arg[2], &arg[0], &arg[1]);
3015
3016 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3017 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3018 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
3019
3020 fetch_source(mach, &arg[1], &inst->Src[2], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3021 micro_add(&arg[0], &arg[0], &arg[1]);
3022
3023 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3024 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3025 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3026 }
3027 }
3028 }
3029
3030 static void
3031 exec_dph(struct tgsi_exec_machine *mach,
3032 const struct tgsi_full_instruction *inst)
3033 {
3034 unsigned int chan;
3035 union tgsi_exec_channel arg[3];
3036
3037 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3038 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3039 micro_mul(&arg[2], &arg[0], &arg[1]);
3040
3041 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3042 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3043 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
3044
3045 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3046 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3047 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
3048
3049 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3050 micro_add(&arg[0], &arg[0], &arg[1]);
3051
3052 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3053 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3054 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3055 }
3056 }
3057 }
3058
3059 static void
3060 exec_dp2(struct tgsi_exec_machine *mach,
3061 const struct tgsi_full_instruction *inst)
3062 {
3063 unsigned int chan;
3064 union tgsi_exec_channel arg[3];
3065
3066 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3067 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3068 micro_mul(&arg[2], &arg[0], &arg[1]);
3069
3070 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3071 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3072 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
3073
3074 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3075 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3076 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3077 }
3078 }
3079 }
3080
3081 static void
3082 exec_pk2h(struct tgsi_exec_machine *mach,
3083 const struct tgsi_full_instruction *inst)
3084 {
3085 unsigned chan;
3086 union tgsi_exec_channel arg[2], dst;
3087
3088 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3089 fetch_source(mach, &arg[1], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3090 for (chan = 0; chan < TGSI_QUAD_SIZE; chan++) {
3091 dst.u[chan] = util_float_to_half(arg[0].f[chan]) |
3092 (util_float_to_half(arg[1].f[chan]) << 16);
3093 }
3094 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3095 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3096 store_dest(mach, &dst, &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_UINT);
3097 }
3098 }
3099 }
3100
3101 static void
3102 exec_up2h(struct tgsi_exec_machine *mach,
3103 const struct tgsi_full_instruction *inst)
3104 {
3105 unsigned chan;
3106 union tgsi_exec_channel arg, dst[2];
3107
3108 fetch_source(mach, &arg, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3109 for (chan = 0; chan < TGSI_QUAD_SIZE; chan++) {
3110 dst[0].f[chan] = util_half_to_float(arg.u[chan] & 0xffff);
3111 dst[1].f[chan] = util_half_to_float(arg.u[chan] >> 16);
3112 }
3113 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3114 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3115 store_dest(mach, &dst[chan & 1], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3116 }
3117 }
3118 }
3119
3120 static void
3121 exec_scs(struct tgsi_exec_machine *mach,
3122 const struct tgsi_full_instruction *inst)
3123 {
3124 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) {
3125 union tgsi_exec_channel arg;
3126 union tgsi_exec_channel result;
3127
3128 fetch_source(mach, &arg, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3129
3130 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3131 micro_cos(&result, &arg);
3132 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3133 }
3134 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3135 micro_sin(&result, &arg);
3136 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3137 }
3138 }
3139 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3140 store_dest(mach, &ZeroVec, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3141 }
3142 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3143 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3144 }
3145 }
3146
3147 static void
3148 exec_xpd(struct tgsi_exec_machine *mach,
3149 const struct tgsi_full_instruction *inst)
3150 {
3151 union tgsi_exec_channel r[6];
3152 union tgsi_exec_channel d[3];
3153
3154 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3155 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3156
3157 micro_mul(&r[2], &r[0], &r[1]);
3158
3159 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3160 fetch_source(mach, &r[4], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3161
3162 micro_mul(&r[5], &r[3], &r[4] );
3163 micro_sub(&d[TGSI_CHAN_X], &r[2], &r[5]);
3164
3165 fetch_source(mach, &r[2], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3166
3167 micro_mul(&r[3], &r[3], &r[2]);
3168
3169 fetch_source(mach, &r[5], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3170
3171 micro_mul(&r[1], &r[1], &r[5]);
3172 micro_sub(&d[TGSI_CHAN_Y], &r[3], &r[1]);
3173
3174 micro_mul(&r[5], &r[5], &r[4]);
3175 micro_mul(&r[0], &r[0], &r[2]);
3176 micro_sub(&d[TGSI_CHAN_Z], &r[5], &r[0]);
3177
3178 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3179 store_dest(mach, &d[TGSI_CHAN_X], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3180 }
3181 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3182 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3183 }
3184 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3185 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3186 }
3187 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3188 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3189 }
3190 }
3191
3192 static void
3193 exec_dst(struct tgsi_exec_machine *mach,
3194 const struct tgsi_full_instruction *inst)
3195 {
3196 union tgsi_exec_channel r[2];
3197 union tgsi_exec_channel d[4];
3198
3199 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3200 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3201 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3202 micro_mul(&d[TGSI_CHAN_Y], &r[0], &r[1]);
3203 }
3204 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3205 fetch_source(mach, &d[TGSI_CHAN_Z], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3206 }
3207 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3208 fetch_source(mach, &d[TGSI_CHAN_W], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3209 }
3210
3211 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3212 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3213 }
3214 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3215 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3216 }
3217 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3218 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3219 }
3220 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3221 store_dest(mach, &d[TGSI_CHAN_W], &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3222 }
3223 }
3224
3225 static void
3226 exec_log(struct tgsi_exec_machine *mach,
3227 const struct tgsi_full_instruction *inst)
3228 {
3229 union tgsi_exec_channel r[3];
3230
3231 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3232 micro_abs(&r[2], &r[0]); /* r2 = abs(r0) */
3233 micro_lg2(&r[1], &r[2]); /* r1 = lg2(r2) */
3234 micro_flr(&r[0], &r[1]); /* r0 = floor(r1) */
3235 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3236 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3237 }
3238 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3239 micro_exp2(&r[0], &r[0]); /* r0 = 2 ^ r0 */
3240 micro_div(&r[0], &r[2], &r[0]); /* r0 = r2 / r0 */
3241 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3242 }
3243 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3244 store_dest(mach, &r[1], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3245 }
3246 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3247 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3248 }
3249 }
3250
3251 static void
3252 exec_exp(struct tgsi_exec_machine *mach,
3253 const struct tgsi_full_instruction *inst)
3254 {
3255 union tgsi_exec_channel r[3];
3256
3257 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3258 micro_flr(&r[1], &r[0]); /* r1 = floor(r0) */
3259 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3260 micro_exp2(&r[2], &r[1]); /* r2 = 2 ^ r1 */
3261 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3262 }
3263 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3264 micro_sub(&r[2], &r[0], &r[1]); /* r2 = r0 - r1 */
3265 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3266 }
3267 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3268 micro_exp2(&r[2], &r[0]); /* r2 = 2 ^ r0 */
3269 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3270 }
3271 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3272 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3273 }
3274 }
3275
3276 static void
3277 exec_lit(struct tgsi_exec_machine *mach,
3278 const struct tgsi_full_instruction *inst)
3279 {
3280 union tgsi_exec_channel r[3];
3281 union tgsi_exec_channel d[3];
3282
3283 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YZ) {
3284 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3285 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3286 fetch_source(mach, &r[1], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3287 micro_max(&r[1], &r[1], &ZeroVec);
3288
3289 fetch_source(mach, &r[2], &inst->Src[0], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3290 micro_min(&r[2], &r[2], &P128Vec);
3291 micro_max(&r[2], &r[2], &M128Vec);
3292 micro_pow(&r[1], &r[1], &r[2]);
3293 micro_lt(&d[TGSI_CHAN_Z], &ZeroVec, &r[0], &r[1], &ZeroVec);
3294 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3295 }
3296 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3297 micro_max(&d[TGSI_CHAN_Y], &r[0], &ZeroVec);
3298 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3299 }
3300 }
3301 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3302 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3303 }
3304
3305 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3306 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3307 }
3308 }
3309
3310 static void
3311 exec_break(struct tgsi_exec_machine *mach)
3312 {
3313 if (mach->BreakType == TGSI_EXEC_BREAK_INSIDE_LOOP) {
3314 /* turn off loop channels for each enabled exec channel */
3315 mach->LoopMask &= ~mach->ExecMask;
3316 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3317 UPDATE_EXEC_MASK(mach);
3318 } else {
3319 assert(mach->BreakType == TGSI_EXEC_BREAK_INSIDE_SWITCH);
3320
3321 mach->Switch.mask = 0x0;
3322
3323 UPDATE_EXEC_MASK(mach);
3324 }
3325 }
3326
3327 static void
3328 exec_switch(struct tgsi_exec_machine *mach,
3329 const struct tgsi_full_instruction *inst)
3330 {
3331 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3332 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3333
3334 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3335 fetch_source(mach, &mach->Switch.selector, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3336 mach->Switch.mask = 0x0;
3337 mach->Switch.defaultMask = 0x0;
3338
3339 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3340 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_SWITCH;
3341
3342 UPDATE_EXEC_MASK(mach);
3343 }
3344
3345 static void
3346 exec_case(struct tgsi_exec_machine *mach,
3347 const struct tgsi_full_instruction *inst)
3348 {
3349 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3350 union tgsi_exec_channel src;
3351 uint mask = 0;
3352
3353 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3354
3355 if (mach->Switch.selector.u[0] == src.u[0]) {
3356 mask |= 0x1;
3357 }
3358 if (mach->Switch.selector.u[1] == src.u[1]) {
3359 mask |= 0x2;
3360 }
3361 if (mach->Switch.selector.u[2] == src.u[2]) {
3362 mask |= 0x4;
3363 }
3364 if (mach->Switch.selector.u[3] == src.u[3]) {
3365 mask |= 0x8;
3366 }
3367
3368 mach->Switch.defaultMask |= mask;
3369
3370 mach->Switch.mask |= mask & prevMask;
3371
3372 UPDATE_EXEC_MASK(mach);
3373 }
3374
3375 /* FIXME: this will only work if default is last */
3376 static void
3377 exec_default(struct tgsi_exec_machine *mach)
3378 {
3379 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3380
3381 mach->Switch.mask |= ~mach->Switch.defaultMask & prevMask;
3382
3383 UPDATE_EXEC_MASK(mach);
3384 }
3385
3386 static void
3387 exec_endswitch(struct tgsi_exec_machine *mach)
3388 {
3389 mach->Switch = mach->SwitchStack[--mach->SwitchStackTop];
3390 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3391
3392 UPDATE_EXEC_MASK(mach);
3393 }
3394
3395 typedef void (* micro_dop)(union tgsi_double_channel *dst,
3396 const union tgsi_double_channel *src);
3397
3398 static void
3399 fetch_double_channel(struct tgsi_exec_machine *mach,
3400 union tgsi_double_channel *chan,
3401 const struct tgsi_full_src_register *reg,
3402 uint chan_0,
3403 uint chan_1)
3404 {
3405 union tgsi_exec_channel src[2];
3406 uint i;
3407
3408 fetch_source_d(mach, &src[0], reg, chan_0, TGSI_EXEC_DATA_UINT);
3409 fetch_source_d(mach, &src[1], reg, chan_1, TGSI_EXEC_DATA_UINT);
3410
3411 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
3412 chan->u[i][0] = src[0].u[i];
3413 chan->u[i][1] = src[1].u[i];
3414 }
3415 if (reg->Register.Absolute) {
3416 micro_dabs(chan, chan);
3417 }
3418 if (reg->Register.Negate) {
3419 micro_dneg(chan, chan);
3420 }
3421 }
3422
3423 static void
3424 store_double_channel(struct tgsi_exec_machine *mach,
3425 const union tgsi_double_channel *chan,
3426 const struct tgsi_full_dst_register *reg,
3427 const struct tgsi_full_instruction *inst,
3428 uint chan_0,
3429 uint chan_1)
3430 {
3431 union tgsi_exec_channel dst[2];
3432 uint i;
3433 union tgsi_double_channel temp;
3434 const uint execmask = mach->ExecMask;
3435
3436 if (!inst->Instruction.Saturate) {
3437 for (i = 0; i < TGSI_QUAD_SIZE; i++)
3438 if (execmask & (1 << i)) {
3439 dst[0].u[i] = chan->u[i][0];
3440 dst[1].u[i] = chan->u[i][1];
3441 }
3442 }
3443 else {
3444 for (i = 0; i < TGSI_QUAD_SIZE; i++)
3445 if (execmask & (1 << i)) {
3446 if (chan->d[i] < 0.0)
3447 temp.d[i] = 0.0;
3448 else if (chan->d[i] > 1.0)
3449 temp.d[i] = 1.0;
3450 else
3451 temp.d[i] = chan->d[i];
3452
3453 dst[0].u[i] = temp.u[i][0];
3454 dst[1].u[i] = temp.u[i][1];
3455 }
3456 }
3457
3458 store_dest_double(mach, &dst[0], reg, inst, chan_0, TGSI_EXEC_DATA_UINT);
3459 if (chan_1 != -1)
3460 store_dest_double(mach, &dst[1], reg, inst, chan_1, TGSI_EXEC_DATA_UINT);
3461 }
3462
3463 static void
3464 exec_double_unary(struct tgsi_exec_machine *mach,
3465 const struct tgsi_full_instruction *inst,
3466 micro_dop op)
3467 {
3468 union tgsi_double_channel src;
3469 union tgsi_double_channel dst;
3470
3471 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3472 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3473 op(&dst, &src);
3474 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3475 }
3476 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3477 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3478 op(&dst, &src);
3479 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3480 }
3481 }
3482
3483 static void
3484 exec_double_binary(struct tgsi_exec_machine *mach,
3485 const struct tgsi_full_instruction *inst,
3486 micro_dop op,
3487 enum tgsi_exec_datatype dst_datatype)
3488 {
3489 union tgsi_double_channel src[2];
3490 union tgsi_double_channel dst;
3491 int first_dest_chan, second_dest_chan;
3492 int wmask;
3493
3494 wmask = inst->Dst[0].Register.WriteMask;
3495 /* these are & because of the way DSLT etc store their destinations */
3496 if (wmask & TGSI_WRITEMASK_XY) {
3497 first_dest_chan = TGSI_CHAN_X;
3498 second_dest_chan = TGSI_CHAN_Y;
3499 if (dst_datatype == TGSI_EXEC_DATA_UINT) {
3500 first_dest_chan = (wmask & TGSI_WRITEMASK_X) ? TGSI_CHAN_X : TGSI_CHAN_Y;
3501 second_dest_chan = -1;
3502 }
3503
3504 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3505 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, TGSI_CHAN_Y);
3506 op(&dst, src);
3507 store_double_channel(mach, &dst, &inst->Dst[0], inst, first_dest_chan, second_dest_chan);
3508 }
3509
3510 if (wmask & TGSI_WRITEMASK_ZW) {
3511 first_dest_chan = TGSI_CHAN_Z;
3512 second_dest_chan = TGSI_CHAN_W;
3513 if (dst_datatype == TGSI_EXEC_DATA_UINT) {
3514 first_dest_chan = (wmask & TGSI_WRITEMASK_Z) ? TGSI_CHAN_Z : TGSI_CHAN_W;
3515 second_dest_chan = -1;
3516 }
3517
3518 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3519 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_CHAN_W);
3520 op(&dst, src);
3521 store_double_channel(mach, &dst, &inst->Dst[0], inst, first_dest_chan, second_dest_chan);
3522 }
3523 }
3524
3525 static void
3526 exec_double_trinary(struct tgsi_exec_machine *mach,
3527 const struct tgsi_full_instruction *inst,
3528 micro_dop op)
3529 {
3530 union tgsi_double_channel src[3];
3531 union tgsi_double_channel dst;
3532
3533 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3534 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3535 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, TGSI_CHAN_Y);
3536 fetch_double_channel(mach, &src[2], &inst->Src[2], TGSI_CHAN_X, TGSI_CHAN_Y);
3537 op(&dst, src);
3538 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3539 }
3540 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3541 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3542 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_CHAN_W);
3543 fetch_double_channel(mach, &src[2], &inst->Src[2], TGSI_CHAN_Z, TGSI_CHAN_W);
3544 op(&dst, src);
3545 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3546 }
3547 }
3548
3549 static void
3550 exec_f2d(struct tgsi_exec_machine *mach,
3551 const struct tgsi_full_instruction *inst)
3552 {
3553 union tgsi_exec_channel src;
3554 union tgsi_double_channel dst;
3555
3556 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3557 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3558 micro_f2d(&dst, &src);
3559 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3560 }
3561 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3562 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3563 micro_f2d(&dst, &src);
3564 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3565 }
3566 }
3567
3568 static void
3569 exec_d2f(struct tgsi_exec_machine *mach,
3570 const struct tgsi_full_instruction *inst)
3571 {
3572 union tgsi_double_channel src;
3573 union tgsi_exec_channel dst;
3574 int wm = inst->Dst[0].Register.WriteMask;
3575 int i;
3576 int bit;
3577 for (i = 0; i < 2; i++) {
3578 bit = ffs(wm);
3579 if (bit) {
3580 wm &= ~(1 << (bit - 1));
3581 if (i == 0)
3582 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3583 else
3584 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3585 micro_d2f(&dst, &src);
3586 store_dest(mach, &dst, &inst->Dst[0], inst, bit - 1, TGSI_EXEC_DATA_FLOAT);
3587 }
3588 }
3589 }
3590
3591 static void
3592 exec_i2d(struct tgsi_exec_machine *mach,
3593 const struct tgsi_full_instruction *inst)
3594 {
3595 union tgsi_exec_channel src;
3596 union tgsi_double_channel dst;
3597
3598 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3599 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
3600 micro_i2d(&dst, &src);
3601 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3602 }
3603 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3604 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_INT);
3605 micro_i2d(&dst, &src);
3606 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3607 }
3608 }
3609
3610 static void
3611 exec_d2i(struct tgsi_exec_machine *mach,
3612 const struct tgsi_full_instruction *inst)
3613 {
3614 union tgsi_double_channel src;
3615 union tgsi_exec_channel dst;
3616 int wm = inst->Dst[0].Register.WriteMask;
3617 int i;
3618 int bit;
3619 for (i = 0; i < 2; i++) {
3620 bit = ffs(wm);
3621 if (bit) {
3622 wm &= ~(1 << (bit - 1));
3623 if (i == 0)
3624 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3625 else
3626 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3627 micro_d2i(&dst, &src);
3628 store_dest(mach, &dst, &inst->Dst[0], inst, bit - 1, TGSI_EXEC_DATA_INT);
3629 }
3630 }
3631 }
3632 static void
3633 exec_u2d(struct tgsi_exec_machine *mach,
3634 const struct tgsi_full_instruction *inst)
3635 {
3636 union tgsi_exec_channel src;
3637 union tgsi_double_channel dst;
3638
3639 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3640 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3641 micro_u2d(&dst, &src);
3642 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3643 }
3644 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3645 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_UINT);
3646 micro_u2d(&dst, &src);
3647 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3648 }
3649 }
3650
3651 static void
3652 exec_d2u(struct tgsi_exec_machine *mach,
3653 const struct tgsi_full_instruction *inst)
3654 {
3655 union tgsi_double_channel src;
3656 union tgsi_exec_channel dst;
3657 int wm = inst->Dst[0].Register.WriteMask;
3658 int i;
3659 int bit;
3660 for (i = 0; i < 2; i++) {
3661 bit = ffs(wm);
3662 if (bit) {
3663 wm &= ~(1 << (bit - 1));
3664 if (i == 0)
3665 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3666 else
3667 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3668 micro_d2u(&dst, &src);
3669 store_dest(mach, &dst, &inst->Dst[0], inst, bit - 1, TGSI_EXEC_DATA_UINT);
3670 }
3671 }
3672 }
3673
3674 static void
3675 exec_dldexp(struct tgsi_exec_machine *mach,
3676 const struct tgsi_full_instruction *inst)
3677 {
3678 union tgsi_double_channel src0;
3679 union tgsi_exec_channel src1;
3680 union tgsi_double_channel dst;
3681 int wmask;
3682
3683 wmask = inst->Dst[0].Register.WriteMask;
3684 if (wmask & TGSI_WRITEMASK_XY) {
3685 fetch_double_channel(mach, &src0, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3686 fetch_source(mach, &src1, &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
3687 micro_dldexp(&dst, &src0, &src1);
3688 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3689 }
3690
3691 if (wmask & TGSI_WRITEMASK_ZW) {
3692 fetch_double_channel(mach, &src0, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3693 fetch_source(mach, &src1, &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_INT);
3694 micro_dldexp(&dst, &src0, &src1);
3695 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3696 }
3697 }
3698
3699 static void
3700 exec_dfracexp(struct tgsi_exec_machine *mach,
3701 const struct tgsi_full_instruction *inst)
3702 {
3703 union tgsi_double_channel src;
3704 union tgsi_double_channel dst;
3705 union tgsi_exec_channel dst_exp;
3706
3707 if (((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY)) {
3708 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3709 micro_dfracexp(&dst, &dst_exp, &src);
3710 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3711 store_dest(mach, &dst_exp, &inst->Dst[1], inst, ffs(inst->Dst[1].Register.WriteMask) - 1, TGSI_EXEC_DATA_INT);
3712 }
3713 if (((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW)) {
3714 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3715 micro_dfracexp(&dst, &dst_exp, &src);
3716 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3717 store_dest(mach, &dst_exp, &inst->Dst[1], inst, ffs(inst->Dst[1].Register.WriteMask) - 1, TGSI_EXEC_DATA_INT);
3718 }
3719 }
3720
3721 static int
3722 get_image_coord_dim(unsigned tgsi_tex)
3723 {
3724 int dim;
3725 switch (tgsi_tex) {
3726 case TGSI_TEXTURE_BUFFER:
3727 case TGSI_TEXTURE_1D:
3728 dim = 1;
3729 break;
3730 case TGSI_TEXTURE_2D:
3731 case TGSI_TEXTURE_RECT:
3732 case TGSI_TEXTURE_1D_ARRAY:
3733 case TGSI_TEXTURE_2D_MSAA:
3734 dim = 2;
3735 break;
3736 case TGSI_TEXTURE_3D:
3737 case TGSI_TEXTURE_CUBE:
3738 case TGSI_TEXTURE_2D_ARRAY:
3739 case TGSI_TEXTURE_2D_ARRAY_MSAA:
3740 case TGSI_TEXTURE_CUBE_ARRAY:
3741 dim = 3;
3742 break;
3743 default:
3744 assert(!"unknown texture target");
3745 dim = 0;
3746 break;
3747 }
3748
3749 return dim;
3750 }
3751
3752 static int
3753 get_image_coord_sample(unsigned tgsi_tex)
3754 {
3755 int sample = 0;
3756 switch (tgsi_tex) {
3757 case TGSI_TEXTURE_2D_MSAA:
3758 sample = 3;
3759 break;
3760 case TGSI_TEXTURE_2D_ARRAY_MSAA:
3761 sample = 4;
3762 break;
3763 default:
3764 break;
3765 }
3766 return sample;
3767 }
3768
3769 static void
3770 exec_load_img(struct tgsi_exec_machine *mach,
3771 const struct tgsi_full_instruction *inst)
3772 {
3773 union tgsi_exec_channel r[4], sample_r;
3774 uint unit;
3775 int sample;
3776 int i, j;
3777 int dim;
3778 uint chan;
3779 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
3780 struct tgsi_image_params params;
3781 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3782
3783 unit = fetch_sampler_unit(mach, inst, 0);
3784 dim = get_image_coord_dim(inst->Memory.Texture);
3785 sample = get_image_coord_sample(inst->Memory.Texture);
3786 assert(dim <= 3);
3787
3788 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3789 params.unit = unit;
3790 params.tgsi_tex_instr = inst->Memory.Texture;
3791 params.format = inst->Memory.Format;
3792
3793 for (i = 0; i < dim; i++) {
3794 IFETCH(&r[i], 1, TGSI_CHAN_X + i);
3795 }
3796
3797 if (sample)
3798 IFETCH(&sample_r, 1, TGSI_CHAN_X + sample);
3799
3800 mach->Image->load(mach->Image, &params,
3801 r[0].i, r[1].i, r[2].i, sample_r.i,
3802 rgba);
3803 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3804 r[0].f[j] = rgba[0][j];
3805 r[1].f[j] = rgba[1][j];
3806 r[2].f[j] = rgba[2][j];
3807 r[3].f[j] = rgba[3][j];
3808 }
3809 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3810 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3811 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3812 }
3813 }
3814 }
3815
3816 static void
3817 exec_load_buf(struct tgsi_exec_machine *mach,
3818 const struct tgsi_full_instruction *inst)
3819 {
3820 union tgsi_exec_channel r[4];
3821 uint unit;
3822 int j;
3823 uint chan;
3824 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
3825 struct tgsi_buffer_params params;
3826 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3827
3828 unit = fetch_sampler_unit(mach, inst, 0);
3829
3830 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3831 params.unit = unit;
3832 IFETCH(&r[0], 1, TGSI_CHAN_X);
3833
3834 mach->Buffer->load(mach->Buffer, &params,
3835 r[0].i, rgba);
3836 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3837 r[0].f[j] = rgba[0][j];
3838 r[1].f[j] = rgba[1][j];
3839 r[2].f[j] = rgba[2][j];
3840 r[3].f[j] = rgba[3][j];
3841 }
3842 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3843 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3844 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3845 }
3846 }
3847 }
3848
3849 static void
3850 exec_load_mem(struct tgsi_exec_machine *mach,
3851 const struct tgsi_full_instruction *inst)
3852 {
3853 union tgsi_exec_channel r[3];
3854 uint chan;
3855 char *ptr = mach->LocalMem;
3856 uint32_t offset;
3857 int j;
3858
3859 IFETCH(&r[0], 1, TGSI_CHAN_X);
3860 if (r[0].u[0] >= mach->LocalMemSize)
3861 return;
3862
3863 offset = r[0].u[0];
3864 ptr += offset;
3865
3866 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3867 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3868 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3869 memcpy(&r[chan].u[j], ptr + (4 * chan), 4);
3870 }
3871 }
3872 }
3873
3874 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3875 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3876 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3877 }
3878 }
3879 }
3880
3881 static void
3882 exec_load(struct tgsi_exec_machine *mach,
3883 const struct tgsi_full_instruction *inst)
3884 {
3885 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
3886 exec_load_img(mach, inst);
3887 else if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
3888 exec_load_buf(mach, inst);
3889 else if (inst->Src[0].Register.File == TGSI_FILE_MEMORY)
3890 exec_load_mem(mach, inst);
3891 }
3892
3893 static void
3894 exec_store_img(struct tgsi_exec_machine *mach,
3895 const struct tgsi_full_instruction *inst)
3896 {
3897 union tgsi_exec_channel r[3], sample_r;
3898 union tgsi_exec_channel value[4];
3899 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
3900 struct tgsi_image_params params;
3901 int dim;
3902 int sample;
3903 int i, j;
3904 uint unit;
3905 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3906 unit = inst->Dst[0].Register.Index;
3907 dim = get_image_coord_dim(inst->Memory.Texture);
3908 sample = get_image_coord_sample(inst->Memory.Texture);
3909 assert(dim <= 3);
3910
3911 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3912 params.unit = unit;
3913 params.tgsi_tex_instr = inst->Memory.Texture;
3914 params.format = inst->Memory.Format;
3915
3916 for (i = 0; i < dim; i++) {
3917 IFETCH(&r[i], 0, TGSI_CHAN_X + i);
3918 }
3919
3920 for (i = 0; i < 4; i++) {
3921 FETCH(&value[i], 1, TGSI_CHAN_X + i);
3922 }
3923 if (sample)
3924 IFETCH(&sample_r, 0, TGSI_CHAN_X + sample);
3925
3926 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3927 rgba[0][j] = value[0].f[j];
3928 rgba[1][j] = value[1].f[j];
3929 rgba[2][j] = value[2].f[j];
3930 rgba[3][j] = value[3].f[j];
3931 }
3932
3933 mach->Image->store(mach->Image, &params,
3934 r[0].i, r[1].i, r[2].i, sample_r.i,
3935 rgba);
3936 }
3937
3938 static void
3939 exec_store_buf(struct tgsi_exec_machine *mach,
3940 const struct tgsi_full_instruction *inst)
3941 {
3942 union tgsi_exec_channel r[3];
3943 union tgsi_exec_channel value[4];
3944 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
3945 struct tgsi_buffer_params params;
3946 int i, j;
3947 uint unit;
3948 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3949
3950 unit = inst->Dst[0].Register.Index;
3951
3952 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3953 params.unit = unit;
3954 params.writemask = inst->Dst[0].Register.WriteMask;
3955
3956 IFETCH(&r[0], 0, TGSI_CHAN_X);
3957 for (i = 0; i < 4; i++) {
3958 FETCH(&value[i], 1, TGSI_CHAN_X + i);
3959 }
3960
3961 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3962 rgba[0][j] = value[0].f[j];
3963 rgba[1][j] = value[1].f[j];
3964 rgba[2][j] = value[2].f[j];
3965 rgba[3][j] = value[3].f[j];
3966 }
3967
3968 mach->Buffer->store(mach->Buffer, &params,
3969 r[0].i,
3970 rgba);
3971 }
3972
3973 static void
3974 exec_store_mem(struct tgsi_exec_machine *mach,
3975 const struct tgsi_full_instruction *inst)
3976 {
3977 union tgsi_exec_channel r[3];
3978 union tgsi_exec_channel value[4];
3979 uint i, chan;
3980 char *ptr = mach->LocalMem;
3981 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3982 int execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3983
3984 IFETCH(&r[0], 0, TGSI_CHAN_X);
3985
3986 for (i = 0; i < 4; i++) {
3987 FETCH(&value[i], 1, TGSI_CHAN_X + i);
3988 }
3989
3990 if (r[0].u[0] >= mach->LocalMemSize)
3991 return;
3992 ptr += r[0].u[0];
3993
3994 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
3995 if (execmask & (1 << i)) {
3996 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3997 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3998 memcpy(ptr + (chan * 4), &value[chan].u[0], 4);
3999 }
4000 }
4001 }
4002 }
4003 }
4004
4005 static void
4006 exec_store(struct tgsi_exec_machine *mach,
4007 const struct tgsi_full_instruction *inst)
4008 {
4009 if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE)
4010 exec_store_img(mach, inst);
4011 else if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER)
4012 exec_store_buf(mach, inst);
4013 else if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY)
4014 exec_store_mem(mach, inst);
4015 }
4016
4017 static void
4018 exec_atomop_img(struct tgsi_exec_machine *mach,
4019 const struct tgsi_full_instruction *inst)
4020 {
4021 union tgsi_exec_channel r[4], sample_r;
4022 union tgsi_exec_channel value[4], value2[4];
4023 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
4024 float rgba2[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
4025 struct tgsi_image_params params;
4026 int dim;
4027 int sample;
4028 int i, j;
4029 uint unit, chan;
4030 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4031 unit = fetch_sampler_unit(mach, inst, 0);
4032 dim = get_image_coord_dim(inst->Memory.Texture);
4033 sample = get_image_coord_sample(inst->Memory.Texture);
4034 assert(dim <= 3);
4035
4036 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4037 params.unit = unit;
4038 params.tgsi_tex_instr = inst->Memory.Texture;
4039 params.format = inst->Memory.Format;
4040
4041 for (i = 0; i < dim; i++) {
4042 IFETCH(&r[i], 1, TGSI_CHAN_X + i);
4043 }
4044
4045 for (i = 0; i < 4; i++) {
4046 FETCH(&value[i], 2, TGSI_CHAN_X + i);
4047 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4048 FETCH(&value2[i], 3, TGSI_CHAN_X + i);
4049 }
4050 if (sample)
4051 IFETCH(&sample_r, 1, TGSI_CHAN_X + sample);
4052
4053 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4054 rgba[0][j] = value[0].f[j];
4055 rgba[1][j] = value[1].f[j];
4056 rgba[2][j] = value[2].f[j];
4057 rgba[3][j] = value[3].f[j];
4058 }
4059 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
4060 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4061 rgba2[0][j] = value2[0].f[j];
4062 rgba2[1][j] = value2[1].f[j];
4063 rgba2[2][j] = value2[2].f[j];
4064 rgba2[3][j] = value2[3].f[j];
4065 }
4066 }
4067
4068 mach->Image->op(mach->Image, &params, inst->Instruction.Opcode,
4069 r[0].i, r[1].i, r[2].i, sample_r.i,
4070 rgba, rgba2);
4071
4072 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4073 r[0].f[j] = rgba[0][j];
4074 r[1].f[j] = rgba[1][j];
4075 r[2].f[j] = rgba[2][j];
4076 r[3].f[j] = rgba[3][j];
4077 }
4078 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4079 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4080 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
4081 }
4082 }
4083 }
4084
4085 static void
4086 exec_atomop_buf(struct tgsi_exec_machine *mach,
4087 const struct tgsi_full_instruction *inst)
4088 {
4089 union tgsi_exec_channel r[4];
4090 union tgsi_exec_channel value[4], value2[4];
4091 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
4092 float rgba2[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
4093 struct tgsi_buffer_params params;
4094 int i, j;
4095 uint unit, chan;
4096 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4097
4098 unit = fetch_sampler_unit(mach, inst, 0);
4099
4100 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4101 params.unit = unit;
4102 params.writemask = inst->Dst[0].Register.WriteMask;
4103
4104 IFETCH(&r[0], 1, TGSI_CHAN_X);
4105
4106 for (i = 0; i < 4; i++) {
4107 FETCH(&value[i], 2, TGSI_CHAN_X + i);
4108 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4109 FETCH(&value2[i], 3, TGSI_CHAN_X + i);
4110 }
4111
4112 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4113 rgba[0][j] = value[0].f[j];
4114 rgba[1][j] = value[1].f[j];
4115 rgba[2][j] = value[2].f[j];
4116 rgba[3][j] = value[3].f[j];
4117 }
4118 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
4119 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4120 rgba2[0][j] = value2[0].f[j];
4121 rgba2[1][j] = value2[1].f[j];
4122 rgba2[2][j] = value2[2].f[j];
4123 rgba2[3][j] = value2[3].f[j];
4124 }
4125 }
4126
4127 mach->Buffer->op(mach->Buffer, &params, inst->Instruction.Opcode,
4128 r[0].i,
4129 rgba, rgba2);
4130
4131 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4132 r[0].f[j] = rgba[0][j];
4133 r[1].f[j] = rgba[1][j];
4134 r[2].f[j] = rgba[2][j];
4135 r[3].f[j] = rgba[3][j];
4136 }
4137 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4138 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4139 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
4140 }
4141 }
4142 }
4143
4144 static void
4145 exec_atomop_mem(struct tgsi_exec_machine *mach,
4146 const struct tgsi_full_instruction *inst)
4147 {
4148 union tgsi_exec_channel r[4];
4149 union tgsi_exec_channel value[4], value2[4];
4150 char *ptr = mach->LocalMem;
4151 uint32_t val;
4152 uint chan, i;
4153 uint32_t offset;
4154 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4155 int execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4156 IFETCH(&r[0], 1, TGSI_CHAN_X);
4157
4158 if (r[0].u[0] >= mach->LocalMemSize)
4159 return;
4160
4161 offset = r[0].u[0];
4162 ptr += offset;
4163 for (i = 0; i < 4; i++) {
4164 FETCH(&value[i], 2, TGSI_CHAN_X + i);
4165 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4166 FETCH(&value2[i], 3, TGSI_CHAN_X + i);
4167 }
4168
4169 memcpy(&r[0].u[0], ptr, 4);
4170 val = r[0].u[0];
4171 switch (inst->Instruction.Opcode) {
4172 case TGSI_OPCODE_ATOMUADD:
4173 val += value[0].u[0];
4174 break;
4175 case TGSI_OPCODE_ATOMXOR:
4176 val ^= value[0].u[0];
4177 break;
4178 case TGSI_OPCODE_ATOMOR:
4179 val |= value[0].u[0];
4180 break;
4181 case TGSI_OPCODE_ATOMAND:
4182 val &= value[0].u[0];
4183 break;
4184 case TGSI_OPCODE_ATOMUMIN:
4185 val = MIN2(val, value[0].u[0]);
4186 break;
4187 case TGSI_OPCODE_ATOMUMAX:
4188 val = MAX2(val, value[0].u[0]);
4189 break;
4190 case TGSI_OPCODE_ATOMIMIN:
4191 val = MIN2(r[0].i[0], value[0].i[0]);
4192 break;
4193 case TGSI_OPCODE_ATOMIMAX:
4194 val = MAX2(r[0].i[0], value[0].i[0]);
4195 break;
4196 case TGSI_OPCODE_ATOMXCHG:
4197 val = value[0].i[0];
4198 break;
4199 case TGSI_OPCODE_ATOMCAS:
4200 if (val == value[0].u[0])
4201 val = value2[0].u[0];
4202 break;
4203 default:
4204 break;
4205 }
4206 for (i = 0; i < TGSI_QUAD_SIZE; i++)
4207 if (execmask & (1 << i))
4208 memcpy(ptr, &val, 4);
4209
4210 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4211 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4212 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
4213 }
4214 }
4215 }
4216
4217 static void
4218 exec_atomop(struct tgsi_exec_machine *mach,
4219 const struct tgsi_full_instruction *inst)
4220 {
4221 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
4222 exec_atomop_img(mach, inst);
4223 else if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
4224 exec_atomop_buf(mach, inst);
4225 else if (inst->Src[0].Register.File == TGSI_FILE_MEMORY)
4226 exec_atomop_mem(mach, inst);
4227 }
4228
4229 static void
4230 exec_resq_img(struct tgsi_exec_machine *mach,
4231 const struct tgsi_full_instruction *inst)
4232 {
4233 int result[4];
4234 union tgsi_exec_channel r[4];
4235 uint unit;
4236 int i, chan, j;
4237 struct tgsi_image_params params;
4238 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4239
4240 unit = fetch_sampler_unit(mach, inst, 0);
4241
4242 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4243 params.unit = unit;
4244 params.tgsi_tex_instr = inst->Memory.Texture;
4245 params.format = inst->Memory.Format;
4246
4247 mach->Image->get_dims(mach->Image, &params, result);
4248
4249 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
4250 for (j = 0; j < 4; j++) {
4251 r[j].i[i] = result[j];
4252 }
4253 }
4254
4255 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4256 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4257 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
4258 TGSI_EXEC_DATA_INT);
4259 }
4260 }
4261 }
4262
4263 static void
4264 exec_resq_buf(struct tgsi_exec_machine *mach,
4265 const struct tgsi_full_instruction *inst)
4266 {
4267 int result;
4268 union tgsi_exec_channel r[4];
4269 uint unit;
4270 int i, chan;
4271 struct tgsi_buffer_params params;
4272 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4273
4274 unit = fetch_sampler_unit(mach, inst, 0);
4275
4276 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4277 params.unit = unit;
4278
4279 mach->Buffer->get_dims(mach->Buffer, &params, &result);
4280
4281 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
4282 r[0].i[i] = result;
4283 }
4284
4285 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4286 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4287 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
4288 TGSI_EXEC_DATA_INT);
4289 }
4290 }
4291 }
4292
4293 static void
4294 exec_resq(struct tgsi_exec_machine *mach,
4295 const struct tgsi_full_instruction *inst)
4296 {
4297 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
4298 exec_resq_img(mach, inst);
4299 else
4300 exec_resq_buf(mach, inst);
4301 }
4302
4303 static void
4304 micro_i2f(union tgsi_exec_channel *dst,
4305 const union tgsi_exec_channel *src)
4306 {
4307 dst->f[0] = (float)src->i[0];
4308 dst->f[1] = (float)src->i[1];
4309 dst->f[2] = (float)src->i[2];
4310 dst->f[3] = (float)src->i[3];
4311 }
4312
4313 static void
4314 micro_not(union tgsi_exec_channel *dst,
4315 const union tgsi_exec_channel *src)
4316 {
4317 dst->u[0] = ~src->u[0];
4318 dst->u[1] = ~src->u[1];
4319 dst->u[2] = ~src->u[2];
4320 dst->u[3] = ~src->u[3];
4321 }
4322
4323 static void
4324 micro_shl(union tgsi_exec_channel *dst,
4325 const union tgsi_exec_channel *src0,
4326 const union tgsi_exec_channel *src1)
4327 {
4328 unsigned masked_count;
4329 masked_count = src1->u[0] & 0x1f;
4330 dst->u[0] = src0->u[0] << masked_count;
4331 masked_count = src1->u[1] & 0x1f;
4332 dst->u[1] = src0->u[1] << masked_count;
4333 masked_count = src1->u[2] & 0x1f;
4334 dst->u[2] = src0->u[2] << masked_count;
4335 masked_count = src1->u[3] & 0x1f;
4336 dst->u[3] = src0->u[3] << masked_count;
4337 }
4338
4339 static void
4340 micro_and(union tgsi_exec_channel *dst,
4341 const union tgsi_exec_channel *src0,
4342 const union tgsi_exec_channel *src1)
4343 {
4344 dst->u[0] = src0->u[0] & src1->u[0];
4345 dst->u[1] = src0->u[1] & src1->u[1];
4346 dst->u[2] = src0->u[2] & src1->u[2];
4347 dst->u[3] = src0->u[3] & src1->u[3];
4348 }
4349
4350 static void
4351 micro_or(union tgsi_exec_channel *dst,
4352 const union tgsi_exec_channel *src0,
4353 const union tgsi_exec_channel *src1)
4354 {
4355 dst->u[0] = src0->u[0] | src1->u[0];
4356 dst->u[1] = src0->u[1] | src1->u[1];
4357 dst->u[2] = src0->u[2] | src1->u[2];
4358 dst->u[3] = src0->u[3] | src1->u[3];
4359 }
4360
4361 static void
4362 micro_xor(union tgsi_exec_channel *dst,
4363 const union tgsi_exec_channel *src0,
4364 const union tgsi_exec_channel *src1)
4365 {
4366 dst->u[0] = src0->u[0] ^ src1->u[0];
4367 dst->u[1] = src0->u[1] ^ src1->u[1];
4368 dst->u[2] = src0->u[2] ^ src1->u[2];
4369 dst->u[3] = src0->u[3] ^ src1->u[3];
4370 }
4371
4372 static void
4373 micro_mod(union tgsi_exec_channel *dst,
4374 const union tgsi_exec_channel *src0,
4375 const union tgsi_exec_channel *src1)
4376 {
4377 dst->i[0] = src0->i[0] % src1->i[0];
4378 dst->i[1] = src0->i[1] % src1->i[1];
4379 dst->i[2] = src0->i[2] % src1->i[2];
4380 dst->i[3] = src0->i[3] % src1->i[3];
4381 }
4382
4383 static void
4384 micro_f2i(union tgsi_exec_channel *dst,
4385 const union tgsi_exec_channel *src)
4386 {
4387 dst->i[0] = (int)src->f[0];
4388 dst->i[1] = (int)src->f[1];
4389 dst->i[2] = (int)src->f[2];
4390 dst->i[3] = (int)src->f[3];
4391 }
4392
4393 static void
4394 micro_fseq(union tgsi_exec_channel *dst,
4395 const union tgsi_exec_channel *src0,
4396 const union tgsi_exec_channel *src1)
4397 {
4398 dst->u[0] = src0->f[0] == src1->f[0] ? ~0 : 0;
4399 dst->u[1] = src0->f[1] == src1->f[1] ? ~0 : 0;
4400 dst->u[2] = src0->f[2] == src1->f[2] ? ~0 : 0;
4401 dst->u[3] = src0->f[3] == src1->f[3] ? ~0 : 0;
4402 }
4403
4404 static void
4405 micro_fsge(union tgsi_exec_channel *dst,
4406 const union tgsi_exec_channel *src0,
4407 const union tgsi_exec_channel *src1)
4408 {
4409 dst->u[0] = src0->f[0] >= src1->f[0] ? ~0 : 0;
4410 dst->u[1] = src0->f[1] >= src1->f[1] ? ~0 : 0;
4411 dst->u[2] = src0->f[2] >= src1->f[2] ? ~0 : 0;
4412 dst->u[3] = src0->f[3] >= src1->f[3] ? ~0 : 0;
4413 }
4414
4415 static void
4416 micro_fslt(union tgsi_exec_channel *dst,
4417 const union tgsi_exec_channel *src0,
4418 const union tgsi_exec_channel *src1)
4419 {
4420 dst->u[0] = src0->f[0] < src1->f[0] ? ~0 : 0;
4421 dst->u[1] = src0->f[1] < src1->f[1] ? ~0 : 0;
4422 dst->u[2] = src0->f[2] < src1->f[2] ? ~0 : 0;
4423 dst->u[3] = src0->f[3] < src1->f[3] ? ~0 : 0;
4424 }
4425
4426 static void
4427 micro_fsne(union tgsi_exec_channel *dst,
4428 const union tgsi_exec_channel *src0,
4429 const union tgsi_exec_channel *src1)
4430 {
4431 dst->u[0] = src0->f[0] != src1->f[0] ? ~0 : 0;
4432 dst->u[1] = src0->f[1] != src1->f[1] ? ~0 : 0;
4433 dst->u[2] = src0->f[2] != src1->f[2] ? ~0 : 0;
4434 dst->u[3] = src0->f[3] != src1->f[3] ? ~0 : 0;
4435 }
4436
4437 static void
4438 micro_idiv(union tgsi_exec_channel *dst,
4439 const union tgsi_exec_channel *src0,
4440 const union tgsi_exec_channel *src1)
4441 {
4442 dst->i[0] = src1->i[0] ? src0->i[0] / src1->i[0] : 0;
4443 dst->i[1] = src1->i[1] ? src0->i[1] / src1->i[1] : 0;
4444 dst->i[2] = src1->i[2] ? src0->i[2] / src1->i[2] : 0;
4445 dst->i[3] = src1->i[3] ? src0->i[3] / src1->i[3] : 0;
4446 }
4447
4448 static void
4449 micro_imax(union tgsi_exec_channel *dst,
4450 const union tgsi_exec_channel *src0,
4451 const union tgsi_exec_channel *src1)
4452 {
4453 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
4454 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
4455 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
4456 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
4457 }
4458
4459 static void
4460 micro_imin(union tgsi_exec_channel *dst,
4461 const union tgsi_exec_channel *src0,
4462 const union tgsi_exec_channel *src1)
4463 {
4464 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
4465 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
4466 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
4467 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
4468 }
4469
4470 static void
4471 micro_isge(union tgsi_exec_channel *dst,
4472 const union tgsi_exec_channel *src0,
4473 const union tgsi_exec_channel *src1)
4474 {
4475 dst->i[0] = src0->i[0] >= src1->i[0] ? -1 : 0;
4476 dst->i[1] = src0->i[1] >= src1->i[1] ? -1 : 0;
4477 dst->i[2] = src0->i[2] >= src1->i[2] ? -1 : 0;
4478 dst->i[3] = src0->i[3] >= src1->i[3] ? -1 : 0;
4479 }
4480
4481 static void
4482 micro_ishr(union tgsi_exec_channel *dst,
4483 const union tgsi_exec_channel *src0,
4484 const union tgsi_exec_channel *src1)
4485 {
4486 unsigned masked_count;
4487 masked_count = src1->i[0] & 0x1f;
4488 dst->i[0] = src0->i[0] >> masked_count;
4489 masked_count = src1->i[1] & 0x1f;
4490 dst->i[1] = src0->i[1] >> masked_count;
4491 masked_count = src1->i[2] & 0x1f;
4492 dst->i[2] = src0->i[2] >> masked_count;
4493 masked_count = src1->i[3] & 0x1f;
4494 dst->i[3] = src0->i[3] >> masked_count;
4495 }
4496
4497 static void
4498 micro_islt(union tgsi_exec_channel *dst,
4499 const union tgsi_exec_channel *src0,
4500 const union tgsi_exec_channel *src1)
4501 {
4502 dst->i[0] = src0->i[0] < src1->i[0] ? -1 : 0;
4503 dst->i[1] = src0->i[1] < src1->i[1] ? -1 : 0;
4504 dst->i[2] = src0->i[2] < src1->i[2] ? -1 : 0;
4505 dst->i[3] = src0->i[3] < src1->i[3] ? -1 : 0;
4506 }
4507
4508 static void
4509 micro_f2u(union tgsi_exec_channel *dst,
4510 const union tgsi_exec_channel *src)
4511 {
4512 dst->u[0] = (uint)src->f[0];
4513 dst->u[1] = (uint)src->f[1];
4514 dst->u[2] = (uint)src->f[2];
4515 dst->u[3] = (uint)src->f[3];
4516 }
4517
4518 static void
4519 micro_u2f(union tgsi_exec_channel *dst,
4520 const union tgsi_exec_channel *src)
4521 {
4522 dst->f[0] = (float)src->u[0];
4523 dst->f[1] = (float)src->u[1];
4524 dst->f[2] = (float)src->u[2];
4525 dst->f[3] = (float)src->u[3];
4526 }
4527
4528 static void
4529 micro_uadd(union tgsi_exec_channel *dst,
4530 const union tgsi_exec_channel *src0,
4531 const union tgsi_exec_channel *src1)
4532 {
4533 dst->u[0] = src0->u[0] + src1->u[0];
4534 dst->u[1] = src0->u[1] + src1->u[1];
4535 dst->u[2] = src0->u[2] + src1->u[2];
4536 dst->u[3] = src0->u[3] + src1->u[3];
4537 }
4538
4539 static void
4540 micro_udiv(union tgsi_exec_channel *dst,
4541 const union tgsi_exec_channel *src0,
4542 const union tgsi_exec_channel *src1)
4543 {
4544 dst->u[0] = src1->u[0] ? src0->u[0] / src1->u[0] : ~0u;
4545 dst->u[1] = src1->u[1] ? src0->u[1] / src1->u[1] : ~0u;
4546 dst->u[2] = src1->u[2] ? src0->u[2] / src1->u[2] : ~0u;
4547 dst->u[3] = src1->u[3] ? src0->u[3] / src1->u[3] : ~0u;
4548 }
4549
4550 static void
4551 micro_umad(union tgsi_exec_channel *dst,
4552 const union tgsi_exec_channel *src0,
4553 const union tgsi_exec_channel *src1,
4554 const union tgsi_exec_channel *src2)
4555 {
4556 dst->u[0] = src0->u[0] * src1->u[0] + src2->u[0];
4557 dst->u[1] = src0->u[1] * src1->u[1] + src2->u[1];
4558 dst->u[2] = src0->u[2] * src1->u[2] + src2->u[2];
4559 dst->u[3] = src0->u[3] * src1->u[3] + src2->u[3];
4560 }
4561
4562 static void
4563 micro_umax(union tgsi_exec_channel *dst,
4564 const union tgsi_exec_channel *src0,
4565 const union tgsi_exec_channel *src1)
4566 {
4567 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
4568 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
4569 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
4570 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
4571 }
4572
4573 static void
4574 micro_umin(union tgsi_exec_channel *dst,
4575 const union tgsi_exec_channel *src0,
4576 const union tgsi_exec_channel *src1)
4577 {
4578 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
4579 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
4580 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
4581 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
4582 }
4583
4584 static void
4585 micro_umod(union tgsi_exec_channel *dst,
4586 const union tgsi_exec_channel *src0,
4587 const union tgsi_exec_channel *src1)
4588 {
4589 dst->u[0] = src1->u[0] ? src0->u[0] % src1->u[0] : ~0u;
4590 dst->u[1] = src1->u[1] ? src0->u[1] % src1->u[1] : ~0u;
4591 dst->u[2] = src1->u[2] ? src0->u[2] % src1->u[2] : ~0u;
4592 dst->u[3] = src1->u[3] ? src0->u[3] % src1->u[3] : ~0u;
4593 }
4594
4595 static void
4596 micro_umul(union tgsi_exec_channel *dst,
4597 const union tgsi_exec_channel *src0,
4598 const union tgsi_exec_channel *src1)
4599 {
4600 dst->u[0] = src0->u[0] * src1->u[0];
4601 dst->u[1] = src0->u[1] * src1->u[1];
4602 dst->u[2] = src0->u[2] * src1->u[2];
4603 dst->u[3] = src0->u[3] * src1->u[3];
4604 }
4605
4606 static void
4607 micro_imul_hi(union tgsi_exec_channel *dst,
4608 const union tgsi_exec_channel *src0,
4609 const union tgsi_exec_channel *src1)
4610 {
4611 #define I64M(x, y) ((((int64_t)x) * ((int64_t)y)) >> 32)
4612 dst->i[0] = I64M(src0->i[0], src1->i[0]);
4613 dst->i[1] = I64M(src0->i[1], src1->i[1]);
4614 dst->i[2] = I64M(src0->i[2], src1->i[2]);
4615 dst->i[3] = I64M(src0->i[3], src1->i[3]);
4616 #undef I64M
4617 }
4618
4619 static void
4620 micro_umul_hi(union tgsi_exec_channel *dst,
4621 const union tgsi_exec_channel *src0,
4622 const union tgsi_exec_channel *src1)
4623 {
4624 #define U64M(x, y) ((((uint64_t)x) * ((uint64_t)y)) >> 32)
4625 dst->u[0] = U64M(src0->u[0], src1->u[0]);
4626 dst->u[1] = U64M(src0->u[1], src1->u[1]);
4627 dst->u[2] = U64M(src0->u[2], src1->u[2]);
4628 dst->u[3] = U64M(src0->u[3], src1->u[3]);
4629 #undef U64M
4630 }
4631
4632 static void
4633 micro_useq(union tgsi_exec_channel *dst,
4634 const union tgsi_exec_channel *src0,
4635 const union tgsi_exec_channel *src1)
4636 {
4637 dst->u[0] = src0->u[0] == src1->u[0] ? ~0 : 0;
4638 dst->u[1] = src0->u[1] == src1->u[1] ? ~0 : 0;
4639 dst->u[2] = src0->u[2] == src1->u[2] ? ~0 : 0;
4640 dst->u[3] = src0->u[3] == src1->u[3] ? ~0 : 0;
4641 }
4642
4643 static void
4644 micro_usge(union tgsi_exec_channel *dst,
4645 const union tgsi_exec_channel *src0,
4646 const union tgsi_exec_channel *src1)
4647 {
4648 dst->u[0] = src0->u[0] >= src1->u[0] ? ~0 : 0;
4649 dst->u[1] = src0->u[1] >= src1->u[1] ? ~0 : 0;
4650 dst->u[2] = src0->u[2] >= src1->u[2] ? ~0 : 0;
4651 dst->u[3] = src0->u[3] >= src1->u[3] ? ~0 : 0;
4652 }
4653
4654 static void
4655 micro_ushr(union tgsi_exec_channel *dst,
4656 const union tgsi_exec_channel *src0,
4657 const union tgsi_exec_channel *src1)
4658 {
4659 unsigned masked_count;
4660 masked_count = src1->u[0] & 0x1f;
4661 dst->u[0] = src0->u[0] >> masked_count;
4662 masked_count = src1->u[1] & 0x1f;
4663 dst->u[1] = src0->u[1] >> masked_count;
4664 masked_count = src1->u[2] & 0x1f;
4665 dst->u[2] = src0->u[2] >> masked_count;
4666 masked_count = src1->u[3] & 0x1f;
4667 dst->u[3] = src0->u[3] >> masked_count;
4668 }
4669
4670 static void
4671 micro_uslt(union tgsi_exec_channel *dst,
4672 const union tgsi_exec_channel *src0,
4673 const union tgsi_exec_channel *src1)
4674 {
4675 dst->u[0] = src0->u[0] < src1->u[0] ? ~0 : 0;
4676 dst->u[1] = src0->u[1] < src1->u[1] ? ~0 : 0;
4677 dst->u[2] = src0->u[2] < src1->u[2] ? ~0 : 0;
4678 dst->u[3] = src0->u[3] < src1->u[3] ? ~0 : 0;
4679 }
4680
4681 static void
4682 micro_usne(union tgsi_exec_channel *dst,
4683 const union tgsi_exec_channel *src0,
4684 const union tgsi_exec_channel *src1)
4685 {
4686 dst->u[0] = src0->u[0] != src1->u[0] ? ~0 : 0;
4687 dst->u[1] = src0->u[1] != src1->u[1] ? ~0 : 0;
4688 dst->u[2] = src0->u[2] != src1->u[2] ? ~0 : 0;
4689 dst->u[3] = src0->u[3] != src1->u[3] ? ~0 : 0;
4690 }
4691
4692 static void
4693 micro_uarl(union tgsi_exec_channel *dst,
4694 const union tgsi_exec_channel *src)
4695 {
4696 dst->i[0] = src->u[0];
4697 dst->i[1] = src->u[1];
4698 dst->i[2] = src->u[2];
4699 dst->i[3] = src->u[3];
4700 }
4701
4702 static void
4703 micro_ucmp(union tgsi_exec_channel *dst,
4704 const union tgsi_exec_channel *src0,
4705 const union tgsi_exec_channel *src1,
4706 const union tgsi_exec_channel *src2)
4707 {
4708 dst->u[0] = src0->u[0] ? src1->u[0] : src2->u[0];
4709 dst->u[1] = src0->u[1] ? src1->u[1] : src2->u[1];
4710 dst->u[2] = src0->u[2] ? src1->u[2] : src2->u[2];
4711 dst->u[3] = src0->u[3] ? src1->u[3] : src2->u[3];
4712 }
4713
4714 /**
4715 * Signed bitfield extract (i.e. sign-extend the extracted bits)
4716 */
4717 static void
4718 micro_ibfe(union tgsi_exec_channel *dst,
4719 const union tgsi_exec_channel *src0,
4720 const union tgsi_exec_channel *src1,
4721 const union tgsi_exec_channel *src2)
4722 {
4723 int i;
4724 for (i = 0; i < 4; i++) {
4725 int width = src2->i[i] & 0x1f;
4726 int offset = src1->i[i] & 0x1f;
4727 if (width == 0)
4728 dst->i[i] = 0;
4729 else if (width + offset < 32)
4730 dst->i[i] = (src0->i[i] << (32 - width - offset)) >> (32 - width);
4731 else
4732 dst->i[i] = src0->i[i] >> offset;
4733 }
4734 }
4735
4736 /**
4737 * Unsigned bitfield extract
4738 */
4739 static void
4740 micro_ubfe(union tgsi_exec_channel *dst,
4741 const union tgsi_exec_channel *src0,
4742 const union tgsi_exec_channel *src1,
4743 const union tgsi_exec_channel *src2)
4744 {
4745 int i;
4746 for (i = 0; i < 4; i++) {
4747 int width = src2->u[i] & 0x1f;
4748 int offset = src1->u[i] & 0x1f;
4749 if (width == 0)
4750 dst->u[i] = 0;
4751 else if (width + offset < 32)
4752 dst->u[i] = (src0->u[i] << (32 - width - offset)) >> (32 - width);
4753 else
4754 dst->u[i] = src0->u[i] >> offset;
4755 }
4756 }
4757
4758 /**
4759 * Bitfield insert: copy low bits from src1 into a region of src0.
4760 */
4761 static void
4762 micro_bfi(union tgsi_exec_channel *dst,
4763 const union tgsi_exec_channel *src0,
4764 const union tgsi_exec_channel *src1,
4765 const union tgsi_exec_channel *src2,
4766 const union tgsi_exec_channel *src3)
4767 {
4768 int i;
4769 for (i = 0; i < 4; i++) {
4770 int width = src3->u[i] & 0x1f;
4771 int offset = src2->u[i] & 0x1f;
4772 int bitmask = ((1 << width) - 1) << offset;
4773 dst->u[i] = ((src1->u[i] << offset) & bitmask) | (src0->u[i] & ~bitmask);
4774 }
4775 }
4776
4777 static void
4778 micro_brev(union tgsi_exec_channel *dst,
4779 const union tgsi_exec_channel *src)
4780 {
4781 dst->u[0] = util_bitreverse(src->u[0]);
4782 dst->u[1] = util_bitreverse(src->u[1]);
4783 dst->u[2] = util_bitreverse(src->u[2]);
4784 dst->u[3] = util_bitreverse(src->u[3]);
4785 }
4786
4787 static void
4788 micro_popc(union tgsi_exec_channel *dst,
4789 const union tgsi_exec_channel *src)
4790 {
4791 dst->u[0] = util_bitcount(src->u[0]);
4792 dst->u[1] = util_bitcount(src->u[1]);
4793 dst->u[2] = util_bitcount(src->u[2]);
4794 dst->u[3] = util_bitcount(src->u[3]);
4795 }
4796
4797 static void
4798 micro_lsb(union tgsi_exec_channel *dst,
4799 const union tgsi_exec_channel *src)
4800 {
4801 dst->i[0] = ffs(src->u[0]) - 1;
4802 dst->i[1] = ffs(src->u[1]) - 1;
4803 dst->i[2] = ffs(src->u[2]) - 1;
4804 dst->i[3] = ffs(src->u[3]) - 1;
4805 }
4806
4807 static void
4808 micro_imsb(union tgsi_exec_channel *dst,
4809 const union tgsi_exec_channel *src)
4810 {
4811 dst->i[0] = util_last_bit_signed(src->i[0]) - 1;
4812 dst->i[1] = util_last_bit_signed(src->i[1]) - 1;
4813 dst->i[2] = util_last_bit_signed(src->i[2]) - 1;
4814 dst->i[3] = util_last_bit_signed(src->i[3]) - 1;
4815 }
4816
4817 static void
4818 micro_umsb(union tgsi_exec_channel *dst,
4819 const union tgsi_exec_channel *src)
4820 {
4821 dst->i[0] = util_last_bit(src->u[0]) - 1;
4822 dst->i[1] = util_last_bit(src->u[1]) - 1;
4823 dst->i[2] = util_last_bit(src->u[2]) - 1;
4824 dst->i[3] = util_last_bit(src->u[3]) - 1;
4825 }
4826
4827 /**
4828 * Execute a TGSI instruction.
4829 * Returns TRUE if a barrier instruction is hit,
4830 * otherwise FALSE.
4831 */
4832 static boolean
4833 exec_instruction(
4834 struct tgsi_exec_machine *mach,
4835 const struct tgsi_full_instruction *inst,
4836 int *pc )
4837 {
4838 union tgsi_exec_channel r[10];
4839
4840 (*pc)++;
4841
4842 switch (inst->Instruction.Opcode) {
4843 case TGSI_OPCODE_ARL:
4844 exec_vector_unary(mach, inst, micro_arl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4845 break;
4846
4847 case TGSI_OPCODE_MOV:
4848 exec_vector_unary(mach, inst, micro_mov, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4849 break;
4850
4851 case TGSI_OPCODE_LIT:
4852 exec_lit(mach, inst);
4853 break;
4854
4855 case TGSI_OPCODE_RCP:
4856 exec_scalar_unary(mach, inst, micro_rcp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4857 break;
4858
4859 case TGSI_OPCODE_RSQ:
4860 exec_scalar_unary(mach, inst, micro_rsq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4861 break;
4862
4863 case TGSI_OPCODE_EXP:
4864 exec_exp(mach, inst);
4865 break;
4866
4867 case TGSI_OPCODE_LOG:
4868 exec_log(mach, inst);
4869 break;
4870
4871 case TGSI_OPCODE_MUL:
4872 exec_vector_binary(mach, inst, micro_mul, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4873 break;
4874
4875 case TGSI_OPCODE_ADD:
4876 exec_vector_binary(mach, inst, micro_add, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4877 break;
4878
4879 case TGSI_OPCODE_DP3:
4880 exec_dp3(mach, inst);
4881 break;
4882
4883 case TGSI_OPCODE_DP4:
4884 exec_dp4(mach, inst);
4885 break;
4886
4887 case TGSI_OPCODE_DST:
4888 exec_dst(mach, inst);
4889 break;
4890
4891 case TGSI_OPCODE_MIN:
4892 exec_vector_binary(mach, inst, micro_min, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4893 break;
4894
4895 case TGSI_OPCODE_MAX:
4896 exec_vector_binary(mach, inst, micro_max, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4897 break;
4898
4899 case TGSI_OPCODE_SLT:
4900 exec_vector_binary(mach, inst, micro_slt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4901 break;
4902
4903 case TGSI_OPCODE_SGE:
4904 exec_vector_binary(mach, inst, micro_sge, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4905 break;
4906
4907 case TGSI_OPCODE_MAD:
4908 exec_vector_trinary(mach, inst, micro_mad, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4909 break;
4910
4911 case TGSI_OPCODE_SUB:
4912 exec_vector_binary(mach, inst, micro_sub, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4913 break;
4914
4915 case TGSI_OPCODE_LRP:
4916 exec_vector_trinary(mach, inst, micro_lrp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4917 break;
4918
4919 case TGSI_OPCODE_SQRT:
4920 exec_scalar_unary(mach, inst, micro_sqrt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4921 break;
4922
4923 case TGSI_OPCODE_DP2A:
4924 exec_dp2a(mach, inst);
4925 break;
4926
4927 case TGSI_OPCODE_FRC:
4928 exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4929 break;
4930
4931 case TGSI_OPCODE_CLAMP:
4932 exec_vector_trinary(mach, inst, micro_clamp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4933 break;
4934
4935 case TGSI_OPCODE_FLR:
4936 exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4937 break;
4938
4939 case TGSI_OPCODE_ROUND:
4940 exec_vector_unary(mach, inst, micro_rnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4941 break;
4942
4943 case TGSI_OPCODE_EX2:
4944 exec_scalar_unary(mach, inst, micro_exp2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4945 break;
4946
4947 case TGSI_OPCODE_LG2:
4948 exec_scalar_unary(mach, inst, micro_lg2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4949 break;
4950
4951 case TGSI_OPCODE_POW:
4952 exec_scalar_binary(mach, inst, micro_pow, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4953 break;
4954
4955 case TGSI_OPCODE_XPD:
4956 exec_xpd(mach, inst);
4957 break;
4958
4959 case TGSI_OPCODE_ABS:
4960 exec_vector_unary(mach, inst, micro_abs, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4961 break;
4962
4963 case TGSI_OPCODE_DPH:
4964 exec_dph(mach, inst);
4965 break;
4966
4967 case TGSI_OPCODE_COS:
4968 exec_scalar_unary(mach, inst, micro_cos, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4969 break;
4970
4971 case TGSI_OPCODE_DDX:
4972 exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4973 break;
4974
4975 case TGSI_OPCODE_DDY:
4976 exec_vector_unary(mach, inst, micro_ddy, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4977 break;
4978
4979 case TGSI_OPCODE_KILL:
4980 exec_kill (mach, inst);
4981 break;
4982
4983 case TGSI_OPCODE_KILL_IF:
4984 exec_kill_if (mach, inst);
4985 break;
4986
4987 case TGSI_OPCODE_PK2H:
4988 exec_pk2h(mach, inst);
4989 break;
4990
4991 case TGSI_OPCODE_PK2US:
4992 assert (0);
4993 break;
4994
4995 case TGSI_OPCODE_PK4B:
4996 assert (0);
4997 break;
4998
4999 case TGSI_OPCODE_PK4UB:
5000 assert (0);
5001 break;
5002
5003 case TGSI_OPCODE_SEQ:
5004 exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5005 break;
5006
5007 case TGSI_OPCODE_SGT:
5008 exec_vector_binary(mach, inst, micro_sgt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5009 break;
5010
5011 case TGSI_OPCODE_SIN:
5012 exec_scalar_unary(mach, inst, micro_sin, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5013 break;
5014
5015 case TGSI_OPCODE_SLE:
5016 exec_vector_binary(mach, inst, micro_sle, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5017 break;
5018
5019 case TGSI_OPCODE_SNE:
5020 exec_vector_binary(mach, inst, micro_sne, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5021 break;
5022
5023 case TGSI_OPCODE_TEX:
5024 /* simple texture lookup */
5025 /* src[0] = texcoord */
5026 /* src[1] = sampler unit */
5027 exec_tex(mach, inst, TEX_MODIFIER_NONE, 1);
5028 break;
5029
5030 case TGSI_OPCODE_TXB:
5031 /* Texture lookup with lod bias */
5032 /* src[0] = texcoord (src[0].w = LOD bias) */
5033 /* src[1] = sampler unit */
5034 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 1);
5035 break;
5036
5037 case TGSI_OPCODE_TXD:
5038 /* Texture lookup with explict partial derivatives */
5039 /* src[0] = texcoord */
5040 /* src[1] = d[strq]/dx */
5041 /* src[2] = d[strq]/dy */
5042 /* src[3] = sampler unit */
5043 exec_txd(mach, inst);
5044 break;
5045
5046 case TGSI_OPCODE_TXL:
5047 /* Texture lookup with explit LOD */
5048 /* src[0] = texcoord (src[0].w = LOD) */
5049 /* src[1] = sampler unit */
5050 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 1);
5051 break;
5052
5053 case TGSI_OPCODE_TXP:
5054 /* Texture lookup with projection */
5055 /* src[0] = texcoord (src[0].w = projection) */
5056 /* src[1] = sampler unit */
5057 exec_tex(mach, inst, TEX_MODIFIER_PROJECTED, 1);
5058 break;
5059
5060 case TGSI_OPCODE_TG4:
5061 /* src[0] = texcoord */
5062 /* src[1] = component */
5063 /* src[2] = sampler unit */
5064 exec_tex(mach, inst, TEX_MODIFIER_GATHER, 2);
5065 break;
5066
5067 case TGSI_OPCODE_LODQ:
5068 /* src[0] = texcoord */
5069 /* src[1] = sampler unit */
5070 exec_lodq(mach, inst);
5071 break;
5072
5073 case TGSI_OPCODE_UP2H:
5074 exec_up2h(mach, inst);
5075 break;
5076
5077 case TGSI_OPCODE_UP2US:
5078 assert (0);
5079 break;
5080
5081 case TGSI_OPCODE_UP4B:
5082 assert (0);
5083 break;
5084
5085 case TGSI_OPCODE_UP4UB:
5086 assert (0);
5087 break;
5088
5089 case TGSI_OPCODE_ARR:
5090 exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
5091 break;
5092
5093 case TGSI_OPCODE_CAL:
5094 /* skip the call if no execution channels are enabled */
5095 if (mach->ExecMask) {
5096 /* do the call */
5097
5098 /* First, record the depths of the execution stacks.
5099 * This is important for deeply nested/looped return statements.
5100 * We have to unwind the stacks by the correct amount. For a
5101 * real code generator, we could determine the number of entries
5102 * to pop off each stack with simple static analysis and avoid
5103 * implementing this data structure at run time.
5104 */
5105 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
5106 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
5107 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
5108 mach->CallStack[mach->CallStackTop].SwitchStackTop = mach->SwitchStackTop;
5109 mach->CallStack[mach->CallStackTop].BreakStackTop = mach->BreakStackTop;
5110 /* note that PC was already incremented above */
5111 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
5112
5113 mach->CallStackTop++;
5114
5115 /* Second, push the Cond, Loop, Cont, Func stacks */
5116 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
5117 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5118 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5119 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
5120 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
5121 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
5122
5123 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
5124 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
5125 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
5126 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
5127 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
5128 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
5129
5130 /* Finally, jump to the subroutine. The label is a pointer
5131 * (an instruction number) to the BGNSUB instruction.
5132 */
5133 *pc = inst->Label.Label;
5134 assert(mach->Instructions[*pc].Instruction.Opcode
5135 == TGSI_OPCODE_BGNSUB);
5136 }
5137 break;
5138
5139 case TGSI_OPCODE_RET:
5140 mach->FuncMask &= ~mach->ExecMask;
5141 UPDATE_EXEC_MASK(mach);
5142
5143 if (mach->FuncMask == 0x0) {
5144 /* really return now (otherwise, keep executing */
5145
5146 if (mach->CallStackTop == 0) {
5147 /* returning from main() */
5148 mach->CondStackTop = 0;
5149 mach->LoopStackTop = 0;
5150 *pc = -1;
5151 return FALSE;
5152 }
5153
5154 assert(mach->CallStackTop > 0);
5155 mach->CallStackTop--;
5156
5157 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
5158 mach->CondMask = mach->CondStack[mach->CondStackTop];
5159
5160 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
5161 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
5162
5163 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
5164 mach->ContMask = mach->ContStack[mach->ContStackTop];
5165
5166 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
5167 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
5168
5169 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
5170 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
5171
5172 assert(mach->FuncStackTop > 0);
5173 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
5174
5175 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
5176
5177 UPDATE_EXEC_MASK(mach);
5178 }
5179 break;
5180
5181 case TGSI_OPCODE_SSG:
5182 exec_vector_unary(mach, inst, micro_sgn, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5183 break;
5184
5185 case TGSI_OPCODE_CMP:
5186 exec_vector_trinary(mach, inst, micro_cmp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5187 break;
5188
5189 case TGSI_OPCODE_SCS:
5190 exec_scs(mach, inst);
5191 break;
5192
5193 case TGSI_OPCODE_DIV:
5194 exec_vector_binary(mach, inst, micro_div, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5195 break;
5196
5197 case TGSI_OPCODE_DP2:
5198 exec_dp2(mach, inst);
5199 break;
5200
5201 case TGSI_OPCODE_IF:
5202 /* push CondMask */
5203 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
5204 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
5205 FETCH( &r[0], 0, TGSI_CHAN_X );
5206 /* update CondMask */
5207 if( ! r[0].f[0] ) {
5208 mach->CondMask &= ~0x1;
5209 }
5210 if( ! r[0].f[1] ) {
5211 mach->CondMask &= ~0x2;
5212 }
5213 if( ! r[0].f[2] ) {
5214 mach->CondMask &= ~0x4;
5215 }
5216 if( ! r[0].f[3] ) {
5217 mach->CondMask &= ~0x8;
5218 }
5219 UPDATE_EXEC_MASK(mach);
5220 /* Todo: If CondMask==0, jump to ELSE */
5221 break;
5222
5223 case TGSI_OPCODE_UIF:
5224 /* push CondMask */
5225 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
5226 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
5227 IFETCH( &r[0], 0, TGSI_CHAN_X );
5228 /* update CondMask */
5229 if( ! r[0].u[0] ) {
5230 mach->CondMask &= ~0x1;
5231 }
5232 if( ! r[0].u[1] ) {
5233 mach->CondMask &= ~0x2;
5234 }
5235 if( ! r[0].u[2] ) {
5236 mach->CondMask &= ~0x4;
5237 }
5238 if( ! r[0].u[3] ) {
5239 mach->CondMask &= ~0x8;
5240 }
5241 UPDATE_EXEC_MASK(mach);
5242 /* Todo: If CondMask==0, jump to ELSE */
5243 break;
5244
5245 case TGSI_OPCODE_ELSE:
5246 /* invert CondMask wrt previous mask */
5247 {
5248 uint prevMask;
5249 assert(mach->CondStackTop > 0);
5250 prevMask = mach->CondStack[mach->CondStackTop - 1];
5251 mach->CondMask = ~mach->CondMask & prevMask;
5252 UPDATE_EXEC_MASK(mach);
5253 /* Todo: If CondMask==0, jump to ENDIF */
5254 }
5255 break;
5256
5257 case TGSI_OPCODE_ENDIF:
5258 /* pop CondMask */
5259 assert(mach->CondStackTop > 0);
5260 mach->CondMask = mach->CondStack[--mach->CondStackTop];
5261 UPDATE_EXEC_MASK(mach);
5262 break;
5263
5264 case TGSI_OPCODE_END:
5265 /* make sure we end primitives which haven't
5266 * been explicitly emitted */
5267 conditional_emit_primitive(mach);
5268 /* halt execution */
5269 *pc = -1;
5270 break;
5271
5272 case TGSI_OPCODE_PUSHA:
5273 assert (0);
5274 break;
5275
5276 case TGSI_OPCODE_POPA:
5277 assert (0);
5278 break;
5279
5280 case TGSI_OPCODE_CEIL:
5281 exec_vector_unary(mach, inst, micro_ceil, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5282 break;
5283
5284 case TGSI_OPCODE_I2F:
5285 exec_vector_unary(mach, inst, micro_i2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
5286 break;
5287
5288 case TGSI_OPCODE_NOT:
5289 exec_vector_unary(mach, inst, micro_not, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5290 break;
5291
5292 case TGSI_OPCODE_TRUNC:
5293 exec_vector_unary(mach, inst, micro_trunc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5294 break;
5295
5296 case TGSI_OPCODE_SHL:
5297 exec_vector_binary(mach, inst, micro_shl, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5298 break;
5299
5300 case TGSI_OPCODE_AND:
5301 exec_vector_binary(mach, inst, micro_and, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5302 break;
5303
5304 case TGSI_OPCODE_OR:
5305 exec_vector_binary(mach, inst, micro_or, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5306 break;
5307
5308 case TGSI_OPCODE_MOD:
5309 exec_vector_binary(mach, inst, micro_mod, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5310 break;
5311
5312 case TGSI_OPCODE_XOR:
5313 exec_vector_binary(mach, inst, micro_xor, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5314 break;
5315
5316 case TGSI_OPCODE_SAD:
5317 assert (0);
5318 break;
5319
5320 case TGSI_OPCODE_TXF:
5321 exec_txf(mach, inst);
5322 break;
5323
5324 case TGSI_OPCODE_TXQ:
5325 exec_txq(mach, inst);
5326 break;
5327
5328 case TGSI_OPCODE_EMIT:
5329 emit_vertex(mach);
5330 break;
5331
5332 case TGSI_OPCODE_ENDPRIM:
5333 emit_primitive(mach);
5334 break;
5335
5336 case TGSI_OPCODE_BGNLOOP:
5337 /* push LoopMask and ContMasks */
5338 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5339 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5340 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5341 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
5342
5343 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
5344 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
5345 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
5346 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
5347 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_LOOP;
5348 break;
5349
5350 case TGSI_OPCODE_ENDLOOP:
5351 /* Restore ContMask, but don't pop */
5352 assert(mach->ContStackTop > 0);
5353 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
5354 UPDATE_EXEC_MASK(mach);
5355 if (mach->ExecMask) {
5356 /* repeat loop: jump to instruction just past BGNLOOP */
5357 assert(mach->LoopLabelStackTop > 0);
5358 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
5359 }
5360 else {
5361 /* exit loop: pop LoopMask */
5362 assert(mach->LoopStackTop > 0);
5363 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
5364 /* pop ContMask */
5365 assert(mach->ContStackTop > 0);
5366 mach->ContMask = mach->ContStack[--mach->ContStackTop];
5367 assert(mach->LoopLabelStackTop > 0);
5368 --mach->LoopLabelStackTop;
5369
5370 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
5371 }
5372 UPDATE_EXEC_MASK(mach);
5373 break;
5374
5375 case TGSI_OPCODE_BRK:
5376 exec_break(mach);
5377 break;
5378
5379 case TGSI_OPCODE_CONT:
5380 /* turn off cont channels for each enabled exec channel */
5381 mach->ContMask &= ~mach->ExecMask;
5382 /* Todo: if mach->LoopMask == 0, jump to end of loop */
5383 UPDATE_EXEC_MASK(mach);
5384 break;
5385
5386 case TGSI_OPCODE_BGNSUB:
5387 /* no-op */
5388 break;
5389
5390 case TGSI_OPCODE_ENDSUB:
5391 /*
5392 * XXX: This really should be a no-op. We should never reach this opcode.
5393 */
5394
5395 assert(mach->CallStackTop > 0);
5396 mach->CallStackTop--;
5397
5398 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
5399 mach->CondMask = mach->CondStack[mach->CondStackTop];
5400
5401 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
5402 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
5403
5404 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
5405 mach->ContMask = mach->ContStack[mach->ContStackTop];
5406
5407 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
5408 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
5409
5410 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
5411 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
5412
5413 assert(mach->FuncStackTop > 0);
5414 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
5415
5416 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
5417
5418 UPDATE_EXEC_MASK(mach);
5419 break;
5420
5421 case TGSI_OPCODE_NOP:
5422 break;
5423
5424 case TGSI_OPCODE_BREAKC:
5425 IFETCH(&r[0], 0, TGSI_CHAN_X);
5426 /* update CondMask */
5427 if (r[0].u[0] && (mach->ExecMask & 0x1)) {
5428 mach->LoopMask &= ~0x1;
5429 }
5430 if (r[0].u[1] && (mach->ExecMask & 0x2)) {
5431 mach->LoopMask &= ~0x2;
5432 }
5433 if (r[0].u[2] && (mach->ExecMask & 0x4)) {
5434 mach->LoopMask &= ~0x4;
5435 }
5436 if (r[0].u[3] && (mach->ExecMask & 0x8)) {
5437 mach->LoopMask &= ~0x8;
5438 }
5439 /* Todo: if mach->LoopMask == 0, jump to end of loop */
5440 UPDATE_EXEC_MASK(mach);
5441 break;
5442
5443 case TGSI_OPCODE_F2I:
5444 exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
5445 break;
5446
5447 case TGSI_OPCODE_FSEQ:
5448 exec_vector_binary(mach, inst, micro_fseq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5449 break;
5450
5451 case TGSI_OPCODE_FSGE:
5452 exec_vector_binary(mach, inst, micro_fsge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5453 break;
5454
5455 case TGSI_OPCODE_FSLT:
5456 exec_vector_binary(mach, inst, micro_fslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5457 break;
5458
5459 case TGSI_OPCODE_FSNE:
5460 exec_vector_binary(mach, inst, micro_fsne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5461 break;
5462
5463 case TGSI_OPCODE_IDIV:
5464 exec_vector_binary(mach, inst, micro_idiv, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5465 break;
5466
5467 case TGSI_OPCODE_IMAX:
5468 exec_vector_binary(mach, inst, micro_imax, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5469 break;
5470
5471 case TGSI_OPCODE_IMIN:
5472 exec_vector_binary(mach, inst, micro_imin, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5473 break;
5474
5475 case TGSI_OPCODE_INEG:
5476 exec_vector_unary(mach, inst, micro_ineg, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5477 break;
5478
5479 case TGSI_OPCODE_ISGE:
5480 exec_vector_binary(mach, inst, micro_isge, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5481 break;
5482
5483 case TGSI_OPCODE_ISHR:
5484 exec_vector_binary(mach, inst, micro_ishr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5485 break;
5486
5487 case TGSI_OPCODE_ISLT:
5488 exec_vector_binary(mach, inst, micro_islt, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5489 break;
5490
5491 case TGSI_OPCODE_F2U:
5492 exec_vector_unary(mach, inst, micro_f2u, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5493 break;
5494
5495 case TGSI_OPCODE_U2F:
5496 exec_vector_unary(mach, inst, micro_u2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_UINT);
5497 break;
5498
5499 case TGSI_OPCODE_UADD:
5500 exec_vector_binary(mach, inst, micro_uadd, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5501 break;
5502
5503 case TGSI_OPCODE_UDIV:
5504 exec_vector_binary(mach, inst, micro_udiv, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5505 break;
5506
5507 case TGSI_OPCODE_UMAD:
5508 exec_vector_trinary(mach, inst, micro_umad, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5509 break;
5510
5511 case TGSI_OPCODE_UMAX:
5512 exec_vector_binary(mach, inst, micro_umax, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5513 break;
5514
5515 case TGSI_OPCODE_UMIN:
5516 exec_vector_binary(mach, inst, micro_umin, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5517 break;
5518
5519 case TGSI_OPCODE_UMOD:
5520 exec_vector_binary(mach, inst, micro_umod, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5521 break;
5522
5523 case TGSI_OPCODE_UMUL:
5524 exec_vector_binary(mach, inst, micro_umul, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5525 break;
5526
5527 case TGSI_OPCODE_IMUL_HI:
5528 exec_vector_binary(mach, inst, micro_imul_hi, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5529 break;
5530
5531 case TGSI_OPCODE_UMUL_HI:
5532 exec_vector_binary(mach, inst, micro_umul_hi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5533 break;
5534
5535 case TGSI_OPCODE_USEQ:
5536 exec_vector_binary(mach, inst, micro_useq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5537 break;
5538
5539 case TGSI_OPCODE_USGE:
5540 exec_vector_binary(mach, inst, micro_usge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5541 break;
5542
5543 case TGSI_OPCODE_USHR:
5544 exec_vector_binary(mach, inst, micro_ushr, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5545 break;
5546
5547 case TGSI_OPCODE_USLT:
5548 exec_vector_binary(mach, inst, micro_uslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5549 break;
5550
5551 case TGSI_OPCODE_USNE:
5552 exec_vector_binary(mach, inst, micro_usne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5553 break;
5554
5555 case TGSI_OPCODE_SWITCH:
5556 exec_switch(mach, inst);
5557 break;
5558
5559 case TGSI_OPCODE_CASE:
5560 exec_case(mach, inst);
5561 break;
5562
5563 case TGSI_OPCODE_DEFAULT:
5564 exec_default(mach);
5565 break;
5566
5567 case TGSI_OPCODE_ENDSWITCH:
5568 exec_endswitch(mach);
5569 break;
5570
5571 case TGSI_OPCODE_SAMPLE_I:
5572 exec_txf(mach, inst);
5573 break;
5574
5575 case TGSI_OPCODE_SAMPLE_I_MS:
5576 exec_txf(mach, inst);
5577 break;
5578
5579 case TGSI_OPCODE_SAMPLE:
5580 exec_sample(mach, inst, TEX_MODIFIER_NONE, FALSE);
5581 break;
5582
5583 case TGSI_OPCODE_SAMPLE_B:
5584 exec_sample(mach, inst, TEX_MODIFIER_LOD_BIAS, FALSE);
5585 break;
5586
5587 case TGSI_OPCODE_SAMPLE_C:
5588 exec_sample(mach, inst, TEX_MODIFIER_NONE, TRUE);
5589 break;
5590
5591 case TGSI_OPCODE_SAMPLE_C_LZ:
5592 exec_sample(mach, inst, TEX_MODIFIER_LEVEL_ZERO, TRUE);
5593 break;
5594
5595 case TGSI_OPCODE_SAMPLE_D:
5596 exec_sample_d(mach, inst);
5597 break;
5598
5599 case TGSI_OPCODE_SAMPLE_L:
5600 exec_sample(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, FALSE);
5601 break;
5602
5603 case TGSI_OPCODE_GATHER4:
5604 assert(0);
5605 break;
5606
5607 case TGSI_OPCODE_SVIEWINFO:
5608 exec_txq(mach, inst);
5609 break;
5610
5611 case TGSI_OPCODE_SAMPLE_POS:
5612 assert(0);
5613 break;
5614
5615 case TGSI_OPCODE_SAMPLE_INFO:
5616 assert(0);
5617 break;
5618
5619 case TGSI_OPCODE_UARL:
5620 exec_vector_unary(mach, inst, micro_uarl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
5621 break;
5622
5623 case TGSI_OPCODE_UCMP:
5624 exec_vector_trinary(mach, inst, micro_ucmp, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5625 break;
5626
5627 case TGSI_OPCODE_IABS:
5628 exec_vector_unary(mach, inst, micro_iabs, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5629 break;
5630
5631 case TGSI_OPCODE_ISSG:
5632 exec_vector_unary(mach, inst, micro_isgn, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5633 break;
5634
5635 case TGSI_OPCODE_TEX2:
5636 /* simple texture lookup */
5637 /* src[0] = texcoord */
5638 /* src[1] = compare */
5639 /* src[2] = sampler unit */
5640 exec_tex(mach, inst, TEX_MODIFIER_NONE, 2);
5641 break;
5642 case TGSI_OPCODE_TXB2:
5643 /* simple texture lookup */
5644 /* src[0] = texcoord */
5645 /* src[1] = bias */
5646 /* src[2] = sampler unit */
5647 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 2);
5648 break;
5649 case TGSI_OPCODE_TXL2:
5650 /* simple texture lookup */
5651 /* src[0] = texcoord */
5652 /* src[1] = lod */
5653 /* src[2] = sampler unit */
5654 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 2);
5655 break;
5656
5657 case TGSI_OPCODE_IBFE:
5658 exec_vector_trinary(mach, inst, micro_ibfe, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5659 break;
5660 case TGSI_OPCODE_UBFE:
5661 exec_vector_trinary(mach, inst, micro_ubfe, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5662 break;
5663 case TGSI_OPCODE_BFI:
5664 exec_vector_quaternary(mach, inst, micro_bfi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5665 break;
5666 case TGSI_OPCODE_BREV:
5667 exec_vector_unary(mach, inst, micro_brev, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5668 break;
5669 case TGSI_OPCODE_POPC:
5670 exec_vector_unary(mach, inst, micro_popc, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5671 break;
5672 case TGSI_OPCODE_LSB:
5673 exec_vector_unary(mach, inst, micro_lsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
5674 break;
5675 case TGSI_OPCODE_IMSB:
5676 exec_vector_unary(mach, inst, micro_imsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5677 break;
5678 case TGSI_OPCODE_UMSB:
5679 exec_vector_unary(mach, inst, micro_umsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
5680 break;
5681
5682 case TGSI_OPCODE_F2D:
5683 exec_f2d(mach, inst);
5684 break;
5685
5686 case TGSI_OPCODE_D2F:
5687 exec_d2f(mach, inst);
5688 break;
5689
5690 case TGSI_OPCODE_DABS:
5691 exec_double_unary(mach, inst, micro_dabs);
5692 break;
5693
5694 case TGSI_OPCODE_DNEG:
5695 exec_double_unary(mach, inst, micro_dneg);
5696 break;
5697
5698 case TGSI_OPCODE_DADD:
5699 exec_double_binary(mach, inst, micro_dadd, TGSI_EXEC_DATA_DOUBLE);
5700 break;
5701
5702 case TGSI_OPCODE_DMUL:
5703 exec_double_binary(mach, inst, micro_dmul, TGSI_EXEC_DATA_DOUBLE);
5704 break;
5705
5706 case TGSI_OPCODE_DMAX:
5707 exec_double_binary(mach, inst, micro_dmax, TGSI_EXEC_DATA_DOUBLE);
5708 break;
5709
5710 case TGSI_OPCODE_DMIN:
5711 exec_double_binary(mach, inst, micro_dmin, TGSI_EXEC_DATA_DOUBLE);
5712 break;
5713
5714 case TGSI_OPCODE_DSLT:
5715 exec_double_binary(mach, inst, micro_dslt, TGSI_EXEC_DATA_UINT);
5716 break;
5717
5718 case TGSI_OPCODE_DSGE:
5719 exec_double_binary(mach, inst, micro_dsge, TGSI_EXEC_DATA_UINT);
5720 break;
5721
5722 case TGSI_OPCODE_DSEQ:
5723 exec_double_binary(mach, inst, micro_dseq, TGSI_EXEC_DATA_UINT);
5724 break;
5725
5726 case TGSI_OPCODE_DSNE:
5727 exec_double_binary(mach, inst, micro_dsne, TGSI_EXEC_DATA_UINT);
5728 break;
5729
5730 case TGSI_OPCODE_DRCP:
5731 exec_double_unary(mach, inst, micro_drcp);
5732 break;
5733
5734 case TGSI_OPCODE_DSQRT:
5735 exec_double_unary(mach, inst, micro_dsqrt);
5736 break;
5737
5738 case TGSI_OPCODE_DRSQ:
5739 exec_double_unary(mach, inst, micro_drsq);
5740 break;
5741
5742 case TGSI_OPCODE_DMAD:
5743 exec_double_trinary(mach, inst, micro_dmad);
5744 break;
5745
5746 case TGSI_OPCODE_DFRAC:
5747 exec_double_unary(mach, inst, micro_dfrac);
5748 break;
5749
5750 case TGSI_OPCODE_DLDEXP:
5751 exec_dldexp(mach, inst);
5752 break;
5753
5754 case TGSI_OPCODE_DFRACEXP:
5755 exec_dfracexp(mach, inst);
5756 break;
5757
5758 case TGSI_OPCODE_I2D:
5759 exec_i2d(mach, inst);
5760 break;
5761
5762 case TGSI_OPCODE_D2I:
5763 exec_d2i(mach, inst);
5764 break;
5765
5766 case TGSI_OPCODE_U2D:
5767 exec_u2d(mach, inst);
5768 break;
5769
5770 case TGSI_OPCODE_D2U:
5771 exec_d2u(mach, inst);
5772 break;
5773
5774 case TGSI_OPCODE_LOAD:
5775 exec_load(mach, inst);
5776 break;
5777
5778 case TGSI_OPCODE_STORE:
5779 exec_store(mach, inst);
5780 break;
5781
5782 case TGSI_OPCODE_ATOMUADD:
5783 case TGSI_OPCODE_ATOMXCHG:
5784 case TGSI_OPCODE_ATOMCAS:
5785 case TGSI_OPCODE_ATOMAND:
5786 case TGSI_OPCODE_ATOMOR:
5787 case TGSI_OPCODE_ATOMXOR:
5788 case TGSI_OPCODE_ATOMUMIN:
5789 case TGSI_OPCODE_ATOMUMAX:
5790 case TGSI_OPCODE_ATOMIMIN:
5791 case TGSI_OPCODE_ATOMIMAX:
5792 exec_atomop(mach, inst);
5793 break;
5794
5795 case TGSI_OPCODE_RESQ:
5796 exec_resq(mach, inst);
5797 break;
5798 case TGSI_OPCODE_BARRIER:
5799 case TGSI_OPCODE_MEMBAR:
5800 return TRUE;
5801 break;
5802 default:
5803 assert( 0 );
5804 }
5805 return FALSE;
5806 }
5807
5808 static void
5809 tgsi_exec_machine_setup_masks(struct tgsi_exec_machine *mach)
5810 {
5811 uint default_mask = 0xf;
5812
5813 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
5814 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
5815
5816 if (mach->ShaderType == PIPE_SHADER_GEOMETRY) {
5817 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
5818 mach->Primitives[0] = 0;
5819 /* GS runs on a single primitive for now */
5820 default_mask = 0x1;
5821 }
5822
5823 if (mach->NonHelperMask == 0)
5824 mach->NonHelperMask = default_mask;
5825 mach->CondMask = default_mask;
5826 mach->LoopMask = default_mask;
5827 mach->ContMask = default_mask;
5828 mach->FuncMask = default_mask;
5829 mach->ExecMask = default_mask;
5830
5831 mach->Switch.mask = default_mask;
5832
5833 assert(mach->CondStackTop == 0);
5834 assert(mach->LoopStackTop == 0);
5835 assert(mach->ContStackTop == 0);
5836 assert(mach->SwitchStackTop == 0);
5837 assert(mach->BreakStackTop == 0);
5838 assert(mach->CallStackTop == 0);
5839 }
5840
5841 /**
5842 * Run TGSI interpreter.
5843 * \return bitmask of "alive" quad components
5844 */
5845 uint
5846 tgsi_exec_machine_run( struct tgsi_exec_machine *mach, int start_pc )
5847 {
5848 uint i;
5849
5850 mach->pc = start_pc;
5851
5852 if (!start_pc) {
5853 tgsi_exec_machine_setup_masks(mach);
5854
5855 /* execute declarations (interpolants) */
5856 for (i = 0; i < mach->NumDeclarations; i++) {
5857 exec_declaration( mach, mach->Declarations+i );
5858 }
5859 }
5860
5861 {
5862 #if DEBUG_EXECUTION
5863 struct tgsi_exec_vector temps[TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS];
5864 struct tgsi_exec_vector outputs[PIPE_MAX_ATTRIBS];
5865 uint inst = 1;
5866
5867 if (!start_pc) {
5868 memset(mach->Temps, 0, sizeof(temps));
5869 if (mach->Outputs)
5870 memset(mach->Outputs, 0, sizeof(outputs));
5871 memset(temps, 0, sizeof(temps));
5872 memset(outputs, 0, sizeof(outputs));
5873 }
5874 #endif
5875
5876 /* execute instructions, until pc is set to -1 */
5877 while (mach->pc != -1) {
5878 boolean barrier_hit;
5879 #if DEBUG_EXECUTION
5880 uint i;
5881
5882 tgsi_dump_instruction(&mach->Instructions[mach->pc], inst++);
5883 #endif
5884
5885 assert(mach->pc < (int) mach->NumInstructions);
5886 barrier_hit = exec_instruction(mach, mach->Instructions + mach->pc, &mach->pc);
5887
5888 /* for compute shaders if we hit a barrier return now for later rescheduling */
5889 if (barrier_hit && mach->ShaderType == PIPE_SHADER_COMPUTE)
5890 return 0;
5891
5892 #if DEBUG_EXECUTION
5893 for (i = 0; i < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS; i++) {
5894 if (memcmp(&temps[i], &mach->Temps[i], sizeof(temps[i]))) {
5895 uint j;
5896
5897 memcpy(&temps[i], &mach->Temps[i], sizeof(temps[i]));
5898 debug_printf("TEMP[%2u] = ", i);
5899 for (j = 0; j < 4; j++) {
5900 if (j > 0) {
5901 debug_printf(" ");
5902 }
5903 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
5904 temps[i].xyzw[0].f[j], temps[i].xyzw[0].u[j],
5905 temps[i].xyzw[1].f[j], temps[i].xyzw[1].u[j],
5906 temps[i].xyzw[2].f[j], temps[i].xyzw[2].u[j],
5907 temps[i].xyzw[3].f[j], temps[i].xyzw[3].u[j]);
5908 }
5909 }
5910 }
5911 if (mach->Outputs) {
5912 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
5913 if (memcmp(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]))) {
5914 uint j;
5915
5916 memcpy(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]));
5917 debug_printf("OUT[%2u] = ", i);
5918 for (j = 0; j < 4; j++) {
5919 if (j > 0) {
5920 debug_printf(" ");
5921 }
5922 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
5923 outputs[i].xyzw[0].f[j], outputs[i].xyzw[0].u[j],
5924 outputs[i].xyzw[1].f[j], outputs[i].xyzw[1].u[j],
5925 outputs[i].xyzw[2].f[j], outputs[i].xyzw[2].u[j],
5926 outputs[i].xyzw[3].f[j], outputs[i].xyzw[3].u[j]);
5927 }
5928 }
5929 }
5930 }
5931 #endif
5932 }
5933 }
5934
5935 #if 0
5936 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
5937 if (mach->ShaderType == PIPE_SHADER_FRAGMENT) {
5938 /*
5939 * Scale back depth component.
5940 */
5941 for (i = 0; i < 4; i++)
5942 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
5943 }
5944 #endif
5945
5946 /* Strictly speaking, these assertions aren't really needed but they
5947 * can potentially catch some bugs in the control flow code.
5948 */
5949 assert(mach->CondStackTop == 0);
5950 assert(mach->LoopStackTop == 0);
5951 assert(mach->ContStackTop == 0);
5952 assert(mach->SwitchStackTop == 0);
5953 assert(mach->BreakStackTop == 0);
5954 assert(mach->CallStackTop == 0);
5955
5956 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
5957 }