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tgsi: clarify the semantics of DFRACEXP
[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 VMware, Inc.
4 * All Rights Reserved.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
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11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
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24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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28
29 /**
30 * TGSI interpreter/executor.
31 *
32 * Flow control information:
33 *
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
38 *
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
42 * See store_dest().
43 *
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
47 *
48 *
49 * Authors:
50 * Michal Krol
51 * Brian Paul
52 */
53
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_half.h"
62 #include "util/u_memory.h"
63 #include "util/u_math.h"
64 #include "util/rounding.h"
65
66
67 #define DEBUG_EXECUTION 0
68
69
70 #define FAST_MATH 0
71
72 #define TILE_TOP_LEFT 0
73 #define TILE_TOP_RIGHT 1
74 #define TILE_BOTTOM_LEFT 2
75 #define TILE_BOTTOM_RIGHT 3
76
77 union tgsi_double_channel {
78 double d[TGSI_QUAD_SIZE];
79 unsigned u[TGSI_QUAD_SIZE][2];
80 uint64_t u64[TGSI_QUAD_SIZE];
81 int64_t i64[TGSI_QUAD_SIZE];
82 };
83
84 struct tgsi_double_vector {
85 union tgsi_double_channel xy;
86 union tgsi_double_channel zw;
87 };
88
89 static void
90 micro_abs(union tgsi_exec_channel *dst,
91 const union tgsi_exec_channel *src)
92 {
93 dst->f[0] = fabsf(src->f[0]);
94 dst->f[1] = fabsf(src->f[1]);
95 dst->f[2] = fabsf(src->f[2]);
96 dst->f[3] = fabsf(src->f[3]);
97 }
98
99 static void
100 micro_arl(union tgsi_exec_channel *dst,
101 const union tgsi_exec_channel *src)
102 {
103 dst->i[0] = (int)floorf(src->f[0]);
104 dst->i[1] = (int)floorf(src->f[1]);
105 dst->i[2] = (int)floorf(src->f[2]);
106 dst->i[3] = (int)floorf(src->f[3]);
107 }
108
109 static void
110 micro_arr(union tgsi_exec_channel *dst,
111 const union tgsi_exec_channel *src)
112 {
113 dst->i[0] = (int)floorf(src->f[0] + 0.5f);
114 dst->i[1] = (int)floorf(src->f[1] + 0.5f);
115 dst->i[2] = (int)floorf(src->f[2] + 0.5f);
116 dst->i[3] = (int)floorf(src->f[3] + 0.5f);
117 }
118
119 static void
120 micro_ceil(union tgsi_exec_channel *dst,
121 const union tgsi_exec_channel *src)
122 {
123 dst->f[0] = ceilf(src->f[0]);
124 dst->f[1] = ceilf(src->f[1]);
125 dst->f[2] = ceilf(src->f[2]);
126 dst->f[3] = ceilf(src->f[3]);
127 }
128
129 static void
130 micro_cmp(union tgsi_exec_channel *dst,
131 const union tgsi_exec_channel *src0,
132 const union tgsi_exec_channel *src1,
133 const union tgsi_exec_channel *src2)
134 {
135 dst->f[0] = src0->f[0] < 0.0f ? src1->f[0] : src2->f[0];
136 dst->f[1] = src0->f[1] < 0.0f ? src1->f[1] : src2->f[1];
137 dst->f[2] = src0->f[2] < 0.0f ? src1->f[2] : src2->f[2];
138 dst->f[3] = src0->f[3] < 0.0f ? src1->f[3] : src2->f[3];
139 }
140
141 static void
142 micro_cos(union tgsi_exec_channel *dst,
143 const union tgsi_exec_channel *src)
144 {
145 dst->f[0] = cosf(src->f[0]);
146 dst->f[1] = cosf(src->f[1]);
147 dst->f[2] = cosf(src->f[2]);
148 dst->f[3] = cosf(src->f[3]);
149 }
150
151 static void
152 micro_d2f(union tgsi_exec_channel *dst,
153 const union tgsi_double_channel *src)
154 {
155 dst->f[0] = (float)src->d[0];
156 dst->f[1] = (float)src->d[1];
157 dst->f[2] = (float)src->d[2];
158 dst->f[3] = (float)src->d[3];
159 }
160
161 static void
162 micro_d2i(union tgsi_exec_channel *dst,
163 const union tgsi_double_channel *src)
164 {
165 dst->i[0] = (int)src->d[0];
166 dst->i[1] = (int)src->d[1];
167 dst->i[2] = (int)src->d[2];
168 dst->i[3] = (int)src->d[3];
169 }
170
171 static void
172 micro_d2u(union tgsi_exec_channel *dst,
173 const union tgsi_double_channel *src)
174 {
175 dst->u[0] = (unsigned)src->d[0];
176 dst->u[1] = (unsigned)src->d[1];
177 dst->u[2] = (unsigned)src->d[2];
178 dst->u[3] = (unsigned)src->d[3];
179 }
180 static void
181 micro_dabs(union tgsi_double_channel *dst,
182 const union tgsi_double_channel *src)
183 {
184 dst->d[0] = src->d[0] >= 0.0 ? src->d[0] : -src->d[0];
185 dst->d[1] = src->d[1] >= 0.0 ? src->d[1] : -src->d[1];
186 dst->d[2] = src->d[2] >= 0.0 ? src->d[2] : -src->d[2];
187 dst->d[3] = src->d[3] >= 0.0 ? src->d[3] : -src->d[3];
188 }
189
190 static void
191 micro_dadd(union tgsi_double_channel *dst,
192 const union tgsi_double_channel *src)
193 {
194 dst->d[0] = src[0].d[0] + src[1].d[0];
195 dst->d[1] = src[0].d[1] + src[1].d[1];
196 dst->d[2] = src[0].d[2] + src[1].d[2];
197 dst->d[3] = src[0].d[3] + src[1].d[3];
198 }
199
200 static void
201 micro_ddiv(union tgsi_double_channel *dst,
202 const union tgsi_double_channel *src)
203 {
204 dst->d[0] = src[0].d[0] / src[1].d[0];
205 dst->d[1] = src[0].d[1] / src[1].d[1];
206 dst->d[2] = src[0].d[2] / src[1].d[2];
207 dst->d[3] = src[0].d[3] / src[1].d[3];
208 }
209
210 static void
211 micro_ddx(union tgsi_exec_channel *dst,
212 const union tgsi_exec_channel *src)
213 {
214 dst->f[0] =
215 dst->f[1] =
216 dst->f[2] =
217 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
218 }
219
220 static void
221 micro_ddy(union tgsi_exec_channel *dst,
222 const union tgsi_exec_channel *src)
223 {
224 dst->f[0] =
225 dst->f[1] =
226 dst->f[2] =
227 dst->f[3] = src->f[TILE_BOTTOM_LEFT] - src->f[TILE_TOP_LEFT];
228 }
229
230 static void
231 micro_dmul(union tgsi_double_channel *dst,
232 const union tgsi_double_channel *src)
233 {
234 dst->d[0] = src[0].d[0] * src[1].d[0];
235 dst->d[1] = src[0].d[1] * src[1].d[1];
236 dst->d[2] = src[0].d[2] * src[1].d[2];
237 dst->d[3] = src[0].d[3] * src[1].d[3];
238 }
239
240 static void
241 micro_dmax(union tgsi_double_channel *dst,
242 const union tgsi_double_channel *src)
243 {
244 dst->d[0] = src[0].d[0] > src[1].d[0] ? src[0].d[0] : src[1].d[0];
245 dst->d[1] = src[0].d[1] > src[1].d[1] ? src[0].d[1] : src[1].d[1];
246 dst->d[2] = src[0].d[2] > src[1].d[2] ? src[0].d[2] : src[1].d[2];
247 dst->d[3] = src[0].d[3] > src[1].d[3] ? src[0].d[3] : src[1].d[3];
248 }
249
250 static void
251 micro_dmin(union tgsi_double_channel *dst,
252 const union tgsi_double_channel *src)
253 {
254 dst->d[0] = src[0].d[0] < src[1].d[0] ? src[0].d[0] : src[1].d[0];
255 dst->d[1] = src[0].d[1] < src[1].d[1] ? src[0].d[1] : src[1].d[1];
256 dst->d[2] = src[0].d[2] < src[1].d[2] ? src[0].d[2] : src[1].d[2];
257 dst->d[3] = src[0].d[3] < src[1].d[3] ? src[0].d[3] : src[1].d[3];
258 }
259
260 static void
261 micro_dneg(union tgsi_double_channel *dst,
262 const union tgsi_double_channel *src)
263 {
264 dst->d[0] = -src->d[0];
265 dst->d[1] = -src->d[1];
266 dst->d[2] = -src->d[2];
267 dst->d[3] = -src->d[3];
268 }
269
270 static void
271 micro_dslt(union tgsi_double_channel *dst,
272 const union tgsi_double_channel *src)
273 {
274 dst->u[0][0] = src[0].d[0] < src[1].d[0] ? ~0U : 0U;
275 dst->u[1][0] = src[0].d[1] < src[1].d[1] ? ~0U : 0U;
276 dst->u[2][0] = src[0].d[2] < src[1].d[2] ? ~0U : 0U;
277 dst->u[3][0] = src[0].d[3] < src[1].d[3] ? ~0U : 0U;
278 }
279
280 static void
281 micro_dsne(union tgsi_double_channel *dst,
282 const union tgsi_double_channel *src)
283 {
284 dst->u[0][0] = src[0].d[0] != src[1].d[0] ? ~0U : 0U;
285 dst->u[1][0] = src[0].d[1] != src[1].d[1] ? ~0U : 0U;
286 dst->u[2][0] = src[0].d[2] != src[1].d[2] ? ~0U : 0U;
287 dst->u[3][0] = src[0].d[3] != src[1].d[3] ? ~0U : 0U;
288 }
289
290 static void
291 micro_dsge(union tgsi_double_channel *dst,
292 const union tgsi_double_channel *src)
293 {
294 dst->u[0][0] = src[0].d[0] >= src[1].d[0] ? ~0U : 0U;
295 dst->u[1][0] = src[0].d[1] >= src[1].d[1] ? ~0U : 0U;
296 dst->u[2][0] = src[0].d[2] >= src[1].d[2] ? ~0U : 0U;
297 dst->u[3][0] = src[0].d[3] >= src[1].d[3] ? ~0U : 0U;
298 }
299
300 static void
301 micro_dseq(union tgsi_double_channel *dst,
302 const union tgsi_double_channel *src)
303 {
304 dst->u[0][0] = src[0].d[0] == src[1].d[0] ? ~0U : 0U;
305 dst->u[1][0] = src[0].d[1] == src[1].d[1] ? ~0U : 0U;
306 dst->u[2][0] = src[0].d[2] == src[1].d[2] ? ~0U : 0U;
307 dst->u[3][0] = src[0].d[3] == src[1].d[3] ? ~0U : 0U;
308 }
309
310 static void
311 micro_drcp(union tgsi_double_channel *dst,
312 const union tgsi_double_channel *src)
313 {
314 dst->d[0] = 1.0 / src->d[0];
315 dst->d[1] = 1.0 / src->d[1];
316 dst->d[2] = 1.0 / src->d[2];
317 dst->d[3] = 1.0 / src->d[3];
318 }
319
320 static void
321 micro_dsqrt(union tgsi_double_channel *dst,
322 const union tgsi_double_channel *src)
323 {
324 dst->d[0] = sqrt(src->d[0]);
325 dst->d[1] = sqrt(src->d[1]);
326 dst->d[2] = sqrt(src->d[2]);
327 dst->d[3] = sqrt(src->d[3]);
328 }
329
330 static void
331 micro_drsq(union tgsi_double_channel *dst,
332 const union tgsi_double_channel *src)
333 {
334 dst->d[0] = 1.0 / sqrt(src->d[0]);
335 dst->d[1] = 1.0 / sqrt(src->d[1]);
336 dst->d[2] = 1.0 / sqrt(src->d[2]);
337 dst->d[3] = 1.0 / sqrt(src->d[3]);
338 }
339
340 static void
341 micro_dmad(union tgsi_double_channel *dst,
342 const union tgsi_double_channel *src)
343 {
344 dst->d[0] = src[0].d[0] * src[1].d[0] + src[2].d[0];
345 dst->d[1] = src[0].d[1] * src[1].d[1] + src[2].d[1];
346 dst->d[2] = src[0].d[2] * src[1].d[2] + src[2].d[2];
347 dst->d[3] = src[0].d[3] * src[1].d[3] + src[2].d[3];
348 }
349
350 static void
351 micro_dfrac(union tgsi_double_channel *dst,
352 const union tgsi_double_channel *src)
353 {
354 dst->d[0] = src->d[0] - floor(src->d[0]);
355 dst->d[1] = src->d[1] - floor(src->d[1]);
356 dst->d[2] = src->d[2] - floor(src->d[2]);
357 dst->d[3] = src->d[3] - floor(src->d[3]);
358 }
359
360 static void
361 micro_dldexp(union tgsi_double_channel *dst,
362 const union tgsi_double_channel *src0,
363 union tgsi_exec_channel *src1)
364 {
365 dst->d[0] = ldexp(src0->d[0], src1->i[0]);
366 dst->d[1] = ldexp(src0->d[1], src1->i[1]);
367 dst->d[2] = ldexp(src0->d[2], src1->i[2]);
368 dst->d[3] = ldexp(src0->d[3], src1->i[3]);
369 }
370
371 static void
372 micro_dfracexp(union tgsi_double_channel *dst,
373 union tgsi_exec_channel *dst_exp,
374 const union tgsi_double_channel *src)
375 {
376 dst->d[0] = frexp(src->d[0], &dst_exp->i[0]);
377 dst->d[1] = frexp(src->d[1], &dst_exp->i[1]);
378 dst->d[2] = frexp(src->d[2], &dst_exp->i[2]);
379 dst->d[3] = frexp(src->d[3], &dst_exp->i[3]);
380 }
381
382 static void
383 micro_exp2(union tgsi_exec_channel *dst,
384 const union tgsi_exec_channel *src)
385 {
386 #if FAST_MATH
387 dst->f[0] = util_fast_exp2(src->f[0]);
388 dst->f[1] = util_fast_exp2(src->f[1]);
389 dst->f[2] = util_fast_exp2(src->f[2]);
390 dst->f[3] = util_fast_exp2(src->f[3]);
391 #else
392 #if DEBUG
393 /* Inf is okay for this instruction, so clamp it to silence assertions. */
394 uint i;
395 union tgsi_exec_channel clamped;
396
397 for (i = 0; i < 4; i++) {
398 if (src->f[i] > 127.99999f) {
399 clamped.f[i] = 127.99999f;
400 } else if (src->f[i] < -126.99999f) {
401 clamped.f[i] = -126.99999f;
402 } else {
403 clamped.f[i] = src->f[i];
404 }
405 }
406 src = &clamped;
407 #endif /* DEBUG */
408
409 dst->f[0] = powf(2.0f, src->f[0]);
410 dst->f[1] = powf(2.0f, src->f[1]);
411 dst->f[2] = powf(2.0f, src->f[2]);
412 dst->f[3] = powf(2.0f, src->f[3]);
413 #endif /* FAST_MATH */
414 }
415
416 static void
417 micro_f2d(union tgsi_double_channel *dst,
418 const union tgsi_exec_channel *src)
419 {
420 dst->d[0] = (double)src->f[0];
421 dst->d[1] = (double)src->f[1];
422 dst->d[2] = (double)src->f[2];
423 dst->d[3] = (double)src->f[3];
424 }
425
426 static void
427 micro_flr(union tgsi_exec_channel *dst,
428 const union tgsi_exec_channel *src)
429 {
430 dst->f[0] = floorf(src->f[0]);
431 dst->f[1] = floorf(src->f[1]);
432 dst->f[2] = floorf(src->f[2]);
433 dst->f[3] = floorf(src->f[3]);
434 }
435
436 static void
437 micro_frc(union tgsi_exec_channel *dst,
438 const union tgsi_exec_channel *src)
439 {
440 dst->f[0] = src->f[0] - floorf(src->f[0]);
441 dst->f[1] = src->f[1] - floorf(src->f[1]);
442 dst->f[2] = src->f[2] - floorf(src->f[2]);
443 dst->f[3] = src->f[3] - floorf(src->f[3]);
444 }
445
446 static void
447 micro_i2d(union tgsi_double_channel *dst,
448 const union tgsi_exec_channel *src)
449 {
450 dst->d[0] = (double)src->i[0];
451 dst->d[1] = (double)src->i[1];
452 dst->d[2] = (double)src->i[2];
453 dst->d[3] = (double)src->i[3];
454 }
455
456 static void
457 micro_iabs(union tgsi_exec_channel *dst,
458 const union tgsi_exec_channel *src)
459 {
460 dst->i[0] = src->i[0] >= 0 ? src->i[0] : -src->i[0];
461 dst->i[1] = src->i[1] >= 0 ? src->i[1] : -src->i[1];
462 dst->i[2] = src->i[2] >= 0 ? src->i[2] : -src->i[2];
463 dst->i[3] = src->i[3] >= 0 ? src->i[3] : -src->i[3];
464 }
465
466 static void
467 micro_ineg(union tgsi_exec_channel *dst,
468 const union tgsi_exec_channel *src)
469 {
470 dst->i[0] = -src->i[0];
471 dst->i[1] = -src->i[1];
472 dst->i[2] = -src->i[2];
473 dst->i[3] = -src->i[3];
474 }
475
476 static void
477 micro_lg2(union tgsi_exec_channel *dst,
478 const union tgsi_exec_channel *src)
479 {
480 #if FAST_MATH
481 dst->f[0] = util_fast_log2(src->f[0]);
482 dst->f[1] = util_fast_log2(src->f[1]);
483 dst->f[2] = util_fast_log2(src->f[2]);
484 dst->f[3] = util_fast_log2(src->f[3]);
485 #else
486 dst->f[0] = logf(src->f[0]) * 1.442695f;
487 dst->f[1] = logf(src->f[1]) * 1.442695f;
488 dst->f[2] = logf(src->f[2]) * 1.442695f;
489 dst->f[3] = logf(src->f[3]) * 1.442695f;
490 #endif
491 }
492
493 static void
494 micro_lrp(union tgsi_exec_channel *dst,
495 const union tgsi_exec_channel *src0,
496 const union tgsi_exec_channel *src1,
497 const union tgsi_exec_channel *src2)
498 {
499 dst->f[0] = src0->f[0] * (src1->f[0] - src2->f[0]) + src2->f[0];
500 dst->f[1] = src0->f[1] * (src1->f[1] - src2->f[1]) + src2->f[1];
501 dst->f[2] = src0->f[2] * (src1->f[2] - src2->f[2]) + src2->f[2];
502 dst->f[3] = src0->f[3] * (src1->f[3] - src2->f[3]) + src2->f[3];
503 }
504
505 static void
506 micro_mad(union tgsi_exec_channel *dst,
507 const union tgsi_exec_channel *src0,
508 const union tgsi_exec_channel *src1,
509 const union tgsi_exec_channel *src2)
510 {
511 dst->f[0] = src0->f[0] * src1->f[0] + src2->f[0];
512 dst->f[1] = src0->f[1] * src1->f[1] + src2->f[1];
513 dst->f[2] = src0->f[2] * src1->f[2] + src2->f[2];
514 dst->f[3] = src0->f[3] * src1->f[3] + src2->f[3];
515 }
516
517 static void
518 micro_mov(union tgsi_exec_channel *dst,
519 const union tgsi_exec_channel *src)
520 {
521 dst->u[0] = src->u[0];
522 dst->u[1] = src->u[1];
523 dst->u[2] = src->u[2];
524 dst->u[3] = src->u[3];
525 }
526
527 static void
528 micro_rcp(union tgsi_exec_channel *dst,
529 const union tgsi_exec_channel *src)
530 {
531 #if 0 /* for debugging */
532 assert(src->f[0] != 0.0f);
533 assert(src->f[1] != 0.0f);
534 assert(src->f[2] != 0.0f);
535 assert(src->f[3] != 0.0f);
536 #endif
537 dst->f[0] = 1.0f / src->f[0];
538 dst->f[1] = 1.0f / src->f[1];
539 dst->f[2] = 1.0f / src->f[2];
540 dst->f[3] = 1.0f / src->f[3];
541 }
542
543 static void
544 micro_rnd(union tgsi_exec_channel *dst,
545 const union tgsi_exec_channel *src)
546 {
547 dst->f[0] = _mesa_roundevenf(src->f[0]);
548 dst->f[1] = _mesa_roundevenf(src->f[1]);
549 dst->f[2] = _mesa_roundevenf(src->f[2]);
550 dst->f[3] = _mesa_roundevenf(src->f[3]);
551 }
552
553 static void
554 micro_rsq(union tgsi_exec_channel *dst,
555 const union tgsi_exec_channel *src)
556 {
557 #if 0 /* for debugging */
558 assert(src->f[0] != 0.0f);
559 assert(src->f[1] != 0.0f);
560 assert(src->f[2] != 0.0f);
561 assert(src->f[3] != 0.0f);
562 #endif
563 dst->f[0] = 1.0f / sqrtf(src->f[0]);
564 dst->f[1] = 1.0f / sqrtf(src->f[1]);
565 dst->f[2] = 1.0f / sqrtf(src->f[2]);
566 dst->f[3] = 1.0f / sqrtf(src->f[3]);
567 }
568
569 static void
570 micro_sqrt(union tgsi_exec_channel *dst,
571 const union tgsi_exec_channel *src)
572 {
573 dst->f[0] = sqrtf(src->f[0]);
574 dst->f[1] = sqrtf(src->f[1]);
575 dst->f[2] = sqrtf(src->f[2]);
576 dst->f[3] = sqrtf(src->f[3]);
577 }
578
579 static void
580 micro_seq(union tgsi_exec_channel *dst,
581 const union tgsi_exec_channel *src0,
582 const union tgsi_exec_channel *src1)
583 {
584 dst->f[0] = src0->f[0] == src1->f[0] ? 1.0f : 0.0f;
585 dst->f[1] = src0->f[1] == src1->f[1] ? 1.0f : 0.0f;
586 dst->f[2] = src0->f[2] == src1->f[2] ? 1.0f : 0.0f;
587 dst->f[3] = src0->f[3] == src1->f[3] ? 1.0f : 0.0f;
588 }
589
590 static void
591 micro_sge(union tgsi_exec_channel *dst,
592 const union tgsi_exec_channel *src0,
593 const union tgsi_exec_channel *src1)
594 {
595 dst->f[0] = src0->f[0] >= src1->f[0] ? 1.0f : 0.0f;
596 dst->f[1] = src0->f[1] >= src1->f[1] ? 1.0f : 0.0f;
597 dst->f[2] = src0->f[2] >= src1->f[2] ? 1.0f : 0.0f;
598 dst->f[3] = src0->f[3] >= src1->f[3] ? 1.0f : 0.0f;
599 }
600
601 static void
602 micro_sgn(union tgsi_exec_channel *dst,
603 const union tgsi_exec_channel *src)
604 {
605 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
606 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
607 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
608 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
609 }
610
611 static void
612 micro_isgn(union tgsi_exec_channel *dst,
613 const union tgsi_exec_channel *src)
614 {
615 dst->i[0] = src->i[0] < 0 ? -1 : src->i[0] > 0 ? 1 : 0;
616 dst->i[1] = src->i[1] < 0 ? -1 : src->i[1] > 0 ? 1 : 0;
617 dst->i[2] = src->i[2] < 0 ? -1 : src->i[2] > 0 ? 1 : 0;
618 dst->i[3] = src->i[3] < 0 ? -1 : src->i[3] > 0 ? 1 : 0;
619 }
620
621 static void
622 micro_sgt(union tgsi_exec_channel *dst,
623 const union tgsi_exec_channel *src0,
624 const union tgsi_exec_channel *src1)
625 {
626 dst->f[0] = src0->f[0] > src1->f[0] ? 1.0f : 0.0f;
627 dst->f[1] = src0->f[1] > src1->f[1] ? 1.0f : 0.0f;
628 dst->f[2] = src0->f[2] > src1->f[2] ? 1.0f : 0.0f;
629 dst->f[3] = src0->f[3] > src1->f[3] ? 1.0f : 0.0f;
630 }
631
632 static void
633 micro_sin(union tgsi_exec_channel *dst,
634 const union tgsi_exec_channel *src)
635 {
636 dst->f[0] = sinf(src->f[0]);
637 dst->f[1] = sinf(src->f[1]);
638 dst->f[2] = sinf(src->f[2]);
639 dst->f[3] = sinf(src->f[3]);
640 }
641
642 static void
643 micro_sle(union tgsi_exec_channel *dst,
644 const union tgsi_exec_channel *src0,
645 const union tgsi_exec_channel *src1)
646 {
647 dst->f[0] = src0->f[0] <= src1->f[0] ? 1.0f : 0.0f;
648 dst->f[1] = src0->f[1] <= src1->f[1] ? 1.0f : 0.0f;
649 dst->f[2] = src0->f[2] <= src1->f[2] ? 1.0f : 0.0f;
650 dst->f[3] = src0->f[3] <= src1->f[3] ? 1.0f : 0.0f;
651 }
652
653 static void
654 micro_slt(union tgsi_exec_channel *dst,
655 const union tgsi_exec_channel *src0,
656 const union tgsi_exec_channel *src1)
657 {
658 dst->f[0] = src0->f[0] < src1->f[0] ? 1.0f : 0.0f;
659 dst->f[1] = src0->f[1] < src1->f[1] ? 1.0f : 0.0f;
660 dst->f[2] = src0->f[2] < src1->f[2] ? 1.0f : 0.0f;
661 dst->f[3] = src0->f[3] < src1->f[3] ? 1.0f : 0.0f;
662 }
663
664 static void
665 micro_sne(union tgsi_exec_channel *dst,
666 const union tgsi_exec_channel *src0,
667 const union tgsi_exec_channel *src1)
668 {
669 dst->f[0] = src0->f[0] != src1->f[0] ? 1.0f : 0.0f;
670 dst->f[1] = src0->f[1] != src1->f[1] ? 1.0f : 0.0f;
671 dst->f[2] = src0->f[2] != src1->f[2] ? 1.0f : 0.0f;
672 dst->f[3] = src0->f[3] != src1->f[3] ? 1.0f : 0.0f;
673 }
674
675 static void
676 micro_trunc(union tgsi_exec_channel *dst,
677 const union tgsi_exec_channel *src)
678 {
679 dst->f[0] = truncf(src->f[0]);
680 dst->f[1] = truncf(src->f[1]);
681 dst->f[2] = truncf(src->f[2]);
682 dst->f[3] = truncf(src->f[3]);
683 }
684
685 static void
686 micro_u2d(union tgsi_double_channel *dst,
687 const union tgsi_exec_channel *src)
688 {
689 dst->d[0] = (double)src->u[0];
690 dst->d[1] = (double)src->u[1];
691 dst->d[2] = (double)src->u[2];
692 dst->d[3] = (double)src->u[3];
693 }
694
695 static void
696 micro_i64abs(union tgsi_double_channel *dst,
697 const union tgsi_double_channel *src)
698 {
699 dst->i64[0] = src->i64[0] >= 0.0 ? src->i64[0] : -src->i64[0];
700 dst->i64[1] = src->i64[1] >= 0.0 ? src->i64[1] : -src->i64[1];
701 dst->i64[2] = src->i64[2] >= 0.0 ? src->i64[2] : -src->i64[2];
702 dst->i64[3] = src->i64[3] >= 0.0 ? src->i64[3] : -src->i64[3];
703 }
704
705 static void
706 micro_i64sgn(union tgsi_double_channel *dst,
707 const union tgsi_double_channel *src)
708 {
709 dst->i64[0] = src->i64[0] < 0 ? -1 : src->i64[0] > 0 ? 1 : 0;
710 dst->i64[1] = src->i64[1] < 0 ? -1 : src->i64[1] > 0 ? 1 : 0;
711 dst->i64[2] = src->i64[2] < 0 ? -1 : src->i64[2] > 0 ? 1 : 0;
712 dst->i64[3] = src->i64[3] < 0 ? -1 : src->i64[3] > 0 ? 1 : 0;
713 }
714
715 static void
716 micro_i64neg(union tgsi_double_channel *dst,
717 const union tgsi_double_channel *src)
718 {
719 dst->i64[0] = -src->i64[0];
720 dst->i64[1] = -src->i64[1];
721 dst->i64[2] = -src->i64[2];
722 dst->i64[3] = -src->i64[3];
723 }
724
725 static void
726 micro_u64seq(union tgsi_double_channel *dst,
727 const union tgsi_double_channel *src)
728 {
729 dst->u[0][0] = src[0].u64[0] == src[1].u64[0] ? ~0U : 0U;
730 dst->u[1][0] = src[0].u64[1] == src[1].u64[1] ? ~0U : 0U;
731 dst->u[2][0] = src[0].u64[2] == src[1].u64[2] ? ~0U : 0U;
732 dst->u[3][0] = src[0].u64[3] == src[1].u64[3] ? ~0U : 0U;
733 }
734
735 static void
736 micro_u64sne(union tgsi_double_channel *dst,
737 const union tgsi_double_channel *src)
738 {
739 dst->u[0][0] = src[0].u64[0] != src[1].u64[0] ? ~0U : 0U;
740 dst->u[1][0] = src[0].u64[1] != src[1].u64[1] ? ~0U : 0U;
741 dst->u[2][0] = src[0].u64[2] != src[1].u64[2] ? ~0U : 0U;
742 dst->u[3][0] = src[0].u64[3] != src[1].u64[3] ? ~0U : 0U;
743 }
744
745 static void
746 micro_i64slt(union tgsi_double_channel *dst,
747 const union tgsi_double_channel *src)
748 {
749 dst->u[0][0] = src[0].i64[0] < src[1].i64[0] ? ~0U : 0U;
750 dst->u[1][0] = src[0].i64[1] < src[1].i64[1] ? ~0U : 0U;
751 dst->u[2][0] = src[0].i64[2] < src[1].i64[2] ? ~0U : 0U;
752 dst->u[3][0] = src[0].i64[3] < src[1].i64[3] ? ~0U : 0U;
753 }
754
755 static void
756 micro_u64slt(union tgsi_double_channel *dst,
757 const union tgsi_double_channel *src)
758 {
759 dst->u[0][0] = src[0].u64[0] < src[1].u64[0] ? ~0U : 0U;
760 dst->u[1][0] = src[0].u64[1] < src[1].u64[1] ? ~0U : 0U;
761 dst->u[2][0] = src[0].u64[2] < src[1].u64[2] ? ~0U : 0U;
762 dst->u[3][0] = src[0].u64[3] < src[1].u64[3] ? ~0U : 0U;
763 }
764
765 static void
766 micro_i64sge(union tgsi_double_channel *dst,
767 const union tgsi_double_channel *src)
768 {
769 dst->u[0][0] = src[0].i64[0] >= src[1].i64[0] ? ~0U : 0U;
770 dst->u[1][0] = src[0].i64[1] >= src[1].i64[1] ? ~0U : 0U;
771 dst->u[2][0] = src[0].i64[2] >= src[1].i64[2] ? ~0U : 0U;
772 dst->u[3][0] = src[0].i64[3] >= src[1].i64[3] ? ~0U : 0U;
773 }
774
775 static void
776 micro_u64sge(union tgsi_double_channel *dst,
777 const union tgsi_double_channel *src)
778 {
779 dst->u[0][0] = src[0].u64[0] >= src[1].u64[0] ? ~0U : 0U;
780 dst->u[1][0] = src[0].u64[1] >= src[1].u64[1] ? ~0U : 0U;
781 dst->u[2][0] = src[0].u64[2] >= src[1].u64[2] ? ~0U : 0U;
782 dst->u[3][0] = src[0].u64[3] >= src[1].u64[3] ? ~0U : 0U;
783 }
784
785 static void
786 micro_u64max(union tgsi_double_channel *dst,
787 const union tgsi_double_channel *src)
788 {
789 dst->u64[0] = src[0].u64[0] > src[1].u64[0] ? src[0].u64[0] : src[1].u64[0];
790 dst->u64[1] = src[0].u64[1] > src[1].u64[1] ? src[0].u64[1] : src[1].u64[1];
791 dst->u64[2] = src[0].u64[2] > src[1].u64[2] ? src[0].u64[2] : src[1].u64[2];
792 dst->u64[3] = src[0].u64[3] > src[1].u64[3] ? src[0].u64[3] : src[1].u64[3];
793 }
794
795 static void
796 micro_i64max(union tgsi_double_channel *dst,
797 const union tgsi_double_channel *src)
798 {
799 dst->i64[0] = src[0].i64[0] > src[1].i64[0] ? src[0].i64[0] : src[1].i64[0];
800 dst->i64[1] = src[0].i64[1] > src[1].i64[1] ? src[0].i64[1] : src[1].i64[1];
801 dst->i64[2] = src[0].i64[2] > src[1].i64[2] ? src[0].i64[2] : src[1].i64[2];
802 dst->i64[3] = src[0].i64[3] > src[1].i64[3] ? src[0].i64[3] : src[1].i64[3];
803 }
804
805 static void
806 micro_u64min(union tgsi_double_channel *dst,
807 const union tgsi_double_channel *src)
808 {
809 dst->u64[0] = src[0].u64[0] < src[1].u64[0] ? src[0].u64[0] : src[1].u64[0];
810 dst->u64[1] = src[0].u64[1] < src[1].u64[1] ? src[0].u64[1] : src[1].u64[1];
811 dst->u64[2] = src[0].u64[2] < src[1].u64[2] ? src[0].u64[2] : src[1].u64[2];
812 dst->u64[3] = src[0].u64[3] < src[1].u64[3] ? src[0].u64[3] : src[1].u64[3];
813 }
814
815 static void
816 micro_i64min(union tgsi_double_channel *dst,
817 const union tgsi_double_channel *src)
818 {
819 dst->i64[0] = src[0].i64[0] < src[1].i64[0] ? src[0].i64[0] : src[1].i64[0];
820 dst->i64[1] = src[0].i64[1] < src[1].i64[1] ? src[0].i64[1] : src[1].i64[1];
821 dst->i64[2] = src[0].i64[2] < src[1].i64[2] ? src[0].i64[2] : src[1].i64[2];
822 dst->i64[3] = src[0].i64[3] < src[1].i64[3] ? src[0].i64[3] : src[1].i64[3];
823 }
824
825 static void
826 micro_u64add(union tgsi_double_channel *dst,
827 const union tgsi_double_channel *src)
828 {
829 dst->u64[0] = src[0].u64[0] + src[1].u64[0];
830 dst->u64[1] = src[0].u64[1] + src[1].u64[1];
831 dst->u64[2] = src[0].u64[2] + src[1].u64[2];
832 dst->u64[3] = src[0].u64[3] + src[1].u64[3];
833 }
834
835 static void
836 micro_u64mul(union tgsi_double_channel *dst,
837 const union tgsi_double_channel *src)
838 {
839 dst->u64[0] = src[0].u64[0] * src[1].u64[0];
840 dst->u64[1] = src[0].u64[1] * src[1].u64[1];
841 dst->u64[2] = src[0].u64[2] * src[1].u64[2];
842 dst->u64[3] = src[0].u64[3] * src[1].u64[3];
843 }
844
845 static void
846 micro_u64div(union tgsi_double_channel *dst,
847 const union tgsi_double_channel *src)
848 {
849 dst->u64[0] = src[1].u64[0] ? src[0].u64[0] / src[1].u64[0] : ~0ull;
850 dst->u64[1] = src[1].u64[1] ? src[0].u64[1] / src[1].u64[1] : ~0ull;
851 dst->u64[2] = src[1].u64[2] ? src[0].u64[2] / src[1].u64[2] : ~0ull;
852 dst->u64[3] = src[1].u64[3] ? src[0].u64[3] / src[1].u64[3] : ~0ull;
853 }
854
855 static void
856 micro_i64div(union tgsi_double_channel *dst,
857 const union tgsi_double_channel *src)
858 {
859 dst->i64[0] = src[1].i64[0] ? src[0].i64[0] / src[1].i64[0] : 0;
860 dst->i64[1] = src[1].i64[1] ? src[0].i64[1] / src[1].i64[1] : 0;
861 dst->i64[2] = src[1].i64[2] ? src[0].i64[2] / src[1].i64[2] : 0;
862 dst->i64[3] = src[1].i64[3] ? src[0].i64[3] / src[1].i64[3] : 0;
863 }
864
865 static void
866 micro_u64mod(union tgsi_double_channel *dst,
867 const union tgsi_double_channel *src)
868 {
869 dst->u64[0] = src[1].u64[0] ? src[0].u64[0] % src[1].u64[0] : ~0ull;
870 dst->u64[1] = src[1].u64[1] ? src[0].u64[1] % src[1].u64[1] : ~0ull;
871 dst->u64[2] = src[1].u64[2] ? src[0].u64[2] % src[1].u64[2] : ~0ull;
872 dst->u64[3] = src[1].u64[3] ? src[0].u64[3] % src[1].u64[3] : ~0ull;
873 }
874
875 static void
876 micro_i64mod(union tgsi_double_channel *dst,
877 const union tgsi_double_channel *src)
878 {
879 dst->i64[0] = src[1].i64[0] ? src[0].i64[0] % src[1].i64[0] : ~0ll;
880 dst->i64[1] = src[1].i64[1] ? src[0].i64[1] % src[1].i64[1] : ~0ll;
881 dst->i64[2] = src[1].i64[2] ? src[0].i64[2] % src[1].i64[2] : ~0ll;
882 dst->i64[3] = src[1].i64[3] ? src[0].i64[3] % src[1].i64[3] : ~0ll;
883 }
884
885 static void
886 micro_u64shl(union tgsi_double_channel *dst,
887 const union tgsi_double_channel *src0,
888 union tgsi_exec_channel *src1)
889 {
890 unsigned masked_count;
891 masked_count = src1->u[0] & 0x3f;
892 dst->u64[0] = src0->u64[0] << masked_count;
893 masked_count = src1->u[1] & 0x3f;
894 dst->u64[1] = src0->u64[1] << masked_count;
895 masked_count = src1->u[2] & 0x3f;
896 dst->u64[2] = src0->u64[2] << masked_count;
897 masked_count = src1->u[3] & 0x3f;
898 dst->u64[3] = src0->u64[3] << masked_count;
899 }
900
901 static void
902 micro_i64shr(union tgsi_double_channel *dst,
903 const union tgsi_double_channel *src0,
904 union tgsi_exec_channel *src1)
905 {
906 unsigned masked_count;
907 masked_count = src1->u[0] & 0x3f;
908 dst->i64[0] = src0->i64[0] >> masked_count;
909 masked_count = src1->u[1] & 0x3f;
910 dst->i64[1] = src0->i64[1] >> masked_count;
911 masked_count = src1->u[2] & 0x3f;
912 dst->i64[2] = src0->i64[2] >> masked_count;
913 masked_count = src1->u[3] & 0x3f;
914 dst->i64[3] = src0->i64[3] >> masked_count;
915 }
916
917 static void
918 micro_u64shr(union tgsi_double_channel *dst,
919 const union tgsi_double_channel *src0,
920 union tgsi_exec_channel *src1)
921 {
922 unsigned masked_count;
923 masked_count = src1->u[0] & 0x3f;
924 dst->u64[0] = src0->u64[0] >> masked_count;
925 masked_count = src1->u[1] & 0x3f;
926 dst->u64[1] = src0->u64[1] >> masked_count;
927 masked_count = src1->u[2] & 0x3f;
928 dst->u64[2] = src0->u64[2] >> masked_count;
929 masked_count = src1->u[3] & 0x3f;
930 dst->u64[3] = src0->u64[3] >> masked_count;
931 }
932
933 enum tgsi_exec_datatype {
934 TGSI_EXEC_DATA_FLOAT,
935 TGSI_EXEC_DATA_INT,
936 TGSI_EXEC_DATA_UINT,
937 TGSI_EXEC_DATA_DOUBLE,
938 TGSI_EXEC_DATA_INT64,
939 TGSI_EXEC_DATA_UINT64,
940 };
941
942 /*
943 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
944 */
945 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
946 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
947 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
948 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
949 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
950 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
951
952
953 /** The execution mask depends on the conditional mask and the loop mask */
954 #define UPDATE_EXEC_MASK(MACH) \
955 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
956
957
958 static const union tgsi_exec_channel ZeroVec =
959 { { 0.0, 0.0, 0.0, 0.0 } };
960
961 static const union tgsi_exec_channel OneVec = {
962 {1.0f, 1.0f, 1.0f, 1.0f}
963 };
964
965 static const union tgsi_exec_channel P128Vec = {
966 {128.0f, 128.0f, 128.0f, 128.0f}
967 };
968
969 static const union tgsi_exec_channel M128Vec = {
970 {-128.0f, -128.0f, -128.0f, -128.0f}
971 };
972
973
974 /**
975 * Assert that none of the float values in 'chan' are infinite or NaN.
976 * NaN and Inf may occur normally during program execution and should
977 * not lead to crashes, etc. But when debugging, it's helpful to catch
978 * them.
979 */
980 static inline void
981 check_inf_or_nan(const union tgsi_exec_channel *chan)
982 {
983 assert(!util_is_inf_or_nan((chan)->f[0]));
984 assert(!util_is_inf_or_nan((chan)->f[1]));
985 assert(!util_is_inf_or_nan((chan)->f[2]));
986 assert(!util_is_inf_or_nan((chan)->f[3]));
987 }
988
989
990 #ifdef DEBUG
991 static void
992 print_chan(const char *msg, const union tgsi_exec_channel *chan)
993 {
994 debug_printf("%s = {%f, %f, %f, %f}\n",
995 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
996 }
997 #endif
998
999
1000 #ifdef DEBUG
1001 static void
1002 print_temp(const struct tgsi_exec_machine *mach, uint index)
1003 {
1004 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
1005 int i;
1006 debug_printf("Temp[%u] =\n", index);
1007 for (i = 0; i < 4; i++) {
1008 debug_printf(" %c: { %f, %f, %f, %f }\n",
1009 "XYZW"[i],
1010 tmp->xyzw[i].f[0],
1011 tmp->xyzw[i].f[1],
1012 tmp->xyzw[i].f[2],
1013 tmp->xyzw[i].f[3]);
1014 }
1015 }
1016 #endif
1017
1018
1019 void
1020 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine *mach,
1021 unsigned num_bufs,
1022 const void **bufs,
1023 const unsigned *buf_sizes)
1024 {
1025 unsigned i;
1026
1027 for (i = 0; i < num_bufs; i++) {
1028 mach->Consts[i] = bufs[i];
1029 mach->ConstsSize[i] = buf_sizes[i];
1030 }
1031 }
1032
1033
1034 /**
1035 * Check if there's a potential src/dst register data dependency when
1036 * using SOA execution.
1037 * Example:
1038 * MOV T, T.yxwz;
1039 * This would expand into:
1040 * MOV t0, t1;
1041 * MOV t1, t0;
1042 * MOV t2, t3;
1043 * MOV t3, t2;
1044 * The second instruction will have the wrong value for t0 if executed as-is.
1045 */
1046 boolean
1047 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
1048 {
1049 uint i, chan;
1050
1051 uint writemask = inst->Dst[0].Register.WriteMask;
1052 if (writemask == TGSI_WRITEMASK_X ||
1053 writemask == TGSI_WRITEMASK_Y ||
1054 writemask == TGSI_WRITEMASK_Z ||
1055 writemask == TGSI_WRITEMASK_W ||
1056 writemask == TGSI_WRITEMASK_NONE) {
1057 /* no chance of data dependency */
1058 return FALSE;
1059 }
1060
1061 /* loop over src regs */
1062 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1063 if ((inst->Src[i].Register.File ==
1064 inst->Dst[0].Register.File) &&
1065 ((inst->Src[i].Register.Index ==
1066 inst->Dst[0].Register.Index) ||
1067 inst->Src[i].Register.Indirect ||
1068 inst->Dst[0].Register.Indirect)) {
1069 /* loop over dest channels */
1070 uint channelsWritten = 0x0;
1071 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1072 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1073 /* check if we're reading a channel that's been written */
1074 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
1075 if (channelsWritten & (1 << swizzle)) {
1076 return TRUE;
1077 }
1078
1079 channelsWritten |= (1 << chan);
1080 }
1081 }
1082 }
1083 }
1084 return FALSE;
1085 }
1086
1087
1088 /**
1089 * Initialize machine state by expanding tokens to full instructions,
1090 * allocating temporary storage, setting up constants, etc.
1091 * After this, we can call tgsi_exec_machine_run() many times.
1092 */
1093 void
1094 tgsi_exec_machine_bind_shader(
1095 struct tgsi_exec_machine *mach,
1096 const struct tgsi_token *tokens,
1097 struct tgsi_sampler *sampler,
1098 struct tgsi_image *image,
1099 struct tgsi_buffer *buffer)
1100 {
1101 uint k;
1102 struct tgsi_parse_context parse;
1103 struct tgsi_full_instruction *instructions;
1104 struct tgsi_full_declaration *declarations;
1105 uint maxInstructions = 10, numInstructions = 0;
1106 uint maxDeclarations = 10, numDeclarations = 0;
1107
1108 #if 0
1109 tgsi_dump(tokens, 0);
1110 #endif
1111
1112 util_init_math();
1113
1114
1115 mach->Tokens = tokens;
1116 mach->Sampler = sampler;
1117 mach->Image = image;
1118 mach->Buffer = buffer;
1119
1120 if (!tokens) {
1121 /* unbind and free all */
1122 FREE(mach->Declarations);
1123 mach->Declarations = NULL;
1124 mach->NumDeclarations = 0;
1125
1126 FREE(mach->Instructions);
1127 mach->Instructions = NULL;
1128 mach->NumInstructions = 0;
1129
1130 return;
1131 }
1132
1133 k = tgsi_parse_init (&parse, mach->Tokens);
1134 if (k != TGSI_PARSE_OK) {
1135 debug_printf( "Problem parsing!\n" );
1136 return;
1137 }
1138
1139 mach->ImmLimit = 0;
1140 mach->NumOutputs = 0;
1141
1142 for (k = 0; k < TGSI_SEMANTIC_COUNT; k++)
1143 mach->SysSemanticToIndex[k] = -1;
1144
1145 if (mach->ShaderType == PIPE_SHADER_GEOMETRY &&
1146 !mach->UsedGeometryShader) {
1147 struct tgsi_exec_vector *inputs;
1148 struct tgsi_exec_vector *outputs;
1149
1150 inputs = align_malloc(sizeof(struct tgsi_exec_vector) *
1151 TGSI_MAX_PRIM_VERTICES * PIPE_MAX_SHADER_INPUTS,
1152 16);
1153
1154 if (!inputs)
1155 return;
1156
1157 outputs = align_malloc(sizeof(struct tgsi_exec_vector) *
1158 TGSI_MAX_TOTAL_VERTICES, 16);
1159
1160 if (!outputs) {
1161 align_free(inputs);
1162 return;
1163 }
1164
1165 align_free(mach->Inputs);
1166 align_free(mach->Outputs);
1167
1168 mach->Inputs = inputs;
1169 mach->Outputs = outputs;
1170 mach->UsedGeometryShader = TRUE;
1171 }
1172
1173 declarations = (struct tgsi_full_declaration *)
1174 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
1175
1176 if (!declarations) {
1177 return;
1178 }
1179
1180 instructions = (struct tgsi_full_instruction *)
1181 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
1182
1183 if (!instructions) {
1184 FREE( declarations );
1185 return;
1186 }
1187
1188 while( !tgsi_parse_end_of_tokens( &parse ) ) {
1189 uint i;
1190
1191 tgsi_parse_token( &parse );
1192 switch( parse.FullToken.Token.Type ) {
1193 case TGSI_TOKEN_TYPE_DECLARATION:
1194 /* save expanded declaration */
1195 if (numDeclarations == maxDeclarations) {
1196 declarations = REALLOC(declarations,
1197 maxDeclarations
1198 * sizeof(struct tgsi_full_declaration),
1199 (maxDeclarations + 10)
1200 * sizeof(struct tgsi_full_declaration));
1201 maxDeclarations += 10;
1202 }
1203 if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_OUTPUT) {
1204 unsigned reg;
1205 for (reg = parse.FullToken.FullDeclaration.Range.First;
1206 reg <= parse.FullToken.FullDeclaration.Range.Last;
1207 ++reg) {
1208 ++mach->NumOutputs;
1209 }
1210 }
1211 else if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
1212 const struct tgsi_full_declaration *decl = &parse.FullToken.FullDeclaration;
1213 mach->SysSemanticToIndex[decl->Semantic.Name] = decl->Range.First;
1214 }
1215
1216 memcpy(declarations + numDeclarations,
1217 &parse.FullToken.FullDeclaration,
1218 sizeof(declarations[0]));
1219 numDeclarations++;
1220 break;
1221
1222 case TGSI_TOKEN_TYPE_IMMEDIATE:
1223 {
1224 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
1225 assert( size <= 4 );
1226 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
1227
1228 for( i = 0; i < size; i++ ) {
1229 mach->Imms[mach->ImmLimit][i] =
1230 parse.FullToken.FullImmediate.u[i].Float;
1231 }
1232 mach->ImmLimit += 1;
1233 }
1234 break;
1235
1236 case TGSI_TOKEN_TYPE_INSTRUCTION:
1237
1238 /* save expanded instruction */
1239 if (numInstructions == maxInstructions) {
1240 instructions = REALLOC(instructions,
1241 maxInstructions
1242 * sizeof(struct tgsi_full_instruction),
1243 (maxInstructions + 10)
1244 * sizeof(struct tgsi_full_instruction));
1245 maxInstructions += 10;
1246 }
1247
1248 memcpy(instructions + numInstructions,
1249 &parse.FullToken.FullInstruction,
1250 sizeof(instructions[0]));
1251
1252 numInstructions++;
1253 break;
1254
1255 case TGSI_TOKEN_TYPE_PROPERTY:
1256 if (mach->ShaderType == PIPE_SHADER_GEOMETRY) {
1257 if (parse.FullToken.FullProperty.Property.PropertyName == TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES) {
1258 mach->MaxOutputVertices = parse.FullToken.FullProperty.u[0].Data;
1259 }
1260 }
1261 break;
1262
1263 default:
1264 assert( 0 );
1265 }
1266 }
1267 tgsi_parse_free (&parse);
1268
1269 FREE(mach->Declarations);
1270 mach->Declarations = declarations;
1271 mach->NumDeclarations = numDeclarations;
1272
1273 FREE(mach->Instructions);
1274 mach->Instructions = instructions;
1275 mach->NumInstructions = numInstructions;
1276 }
1277
1278
1279 struct tgsi_exec_machine *
1280 tgsi_exec_machine_create(enum pipe_shader_type shader_type)
1281 {
1282 struct tgsi_exec_machine *mach;
1283 uint i;
1284
1285 mach = align_malloc( sizeof *mach, 16 );
1286 if (!mach)
1287 goto fail;
1288
1289 memset(mach, 0, sizeof(*mach));
1290
1291 mach->ShaderType = shader_type;
1292 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
1293 mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
1294
1295 if (shader_type != PIPE_SHADER_COMPUTE) {
1296 mach->Inputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_INPUTS, 16);
1297 mach->Outputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_OUTPUTS, 16);
1298 if (!mach->Inputs || !mach->Outputs)
1299 goto fail;
1300 }
1301
1302 /* Setup constants needed by the SSE2 executor. */
1303 for( i = 0; i < 4; i++ ) {
1304 mach->Temps[TGSI_EXEC_TEMP_00000000_I].xyzw[TGSI_EXEC_TEMP_00000000_C].u[i] = 0x00000000;
1305 mach->Temps[TGSI_EXEC_TEMP_7FFFFFFF_I].xyzw[TGSI_EXEC_TEMP_7FFFFFFF_C].u[i] = 0x7FFFFFFF;
1306 mach->Temps[TGSI_EXEC_TEMP_80000000_I].xyzw[TGSI_EXEC_TEMP_80000000_C].u[i] = 0x80000000;
1307 mach->Temps[TGSI_EXEC_TEMP_FFFFFFFF_I].xyzw[TGSI_EXEC_TEMP_FFFFFFFF_C].u[i] = 0xFFFFFFFF; /* not used */
1308 mach->Temps[TGSI_EXEC_TEMP_ONE_I].xyzw[TGSI_EXEC_TEMP_ONE_C].f[i] = 1.0f;
1309 mach->Temps[TGSI_EXEC_TEMP_TWO_I].xyzw[TGSI_EXEC_TEMP_TWO_C].f[i] = 2.0f; /* not used */
1310 mach->Temps[TGSI_EXEC_TEMP_128_I].xyzw[TGSI_EXEC_TEMP_128_C].f[i] = 128.0f;
1311 mach->Temps[TGSI_EXEC_TEMP_MINUS_128_I].xyzw[TGSI_EXEC_TEMP_MINUS_128_C].f[i] = -128.0f;
1312 mach->Temps[TGSI_EXEC_TEMP_THREE_I].xyzw[TGSI_EXEC_TEMP_THREE_C].f[i] = 3.0f;
1313 mach->Temps[TGSI_EXEC_TEMP_HALF_I].xyzw[TGSI_EXEC_TEMP_HALF_C].f[i] = 0.5f;
1314 }
1315
1316 #ifdef DEBUG
1317 /* silence warnings */
1318 (void) print_chan;
1319 (void) print_temp;
1320 #endif
1321
1322 return mach;
1323
1324 fail:
1325 if (mach) {
1326 align_free(mach->Inputs);
1327 align_free(mach->Outputs);
1328 align_free(mach);
1329 }
1330 return NULL;
1331 }
1332
1333
1334 void
1335 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
1336 {
1337 if (mach) {
1338 FREE(mach->Instructions);
1339 FREE(mach->Declarations);
1340
1341 align_free(mach->Inputs);
1342 align_free(mach->Outputs);
1343
1344 align_free(mach);
1345 }
1346 }
1347
1348 static void
1349 micro_add(union tgsi_exec_channel *dst,
1350 const union tgsi_exec_channel *src0,
1351 const union tgsi_exec_channel *src1)
1352 {
1353 dst->f[0] = src0->f[0] + src1->f[0];
1354 dst->f[1] = src0->f[1] + src1->f[1];
1355 dst->f[2] = src0->f[2] + src1->f[2];
1356 dst->f[3] = src0->f[3] + src1->f[3];
1357 }
1358
1359 static void
1360 micro_div(
1361 union tgsi_exec_channel *dst,
1362 const union tgsi_exec_channel *src0,
1363 const union tgsi_exec_channel *src1 )
1364 {
1365 if (src1->f[0] != 0) {
1366 dst->f[0] = src0->f[0] / src1->f[0];
1367 }
1368 if (src1->f[1] != 0) {
1369 dst->f[1] = src0->f[1] / src1->f[1];
1370 }
1371 if (src1->f[2] != 0) {
1372 dst->f[2] = src0->f[2] / src1->f[2];
1373 }
1374 if (src1->f[3] != 0) {
1375 dst->f[3] = src0->f[3] / src1->f[3];
1376 }
1377 }
1378
1379 static void
1380 micro_lt(
1381 union tgsi_exec_channel *dst,
1382 const union tgsi_exec_channel *src0,
1383 const union tgsi_exec_channel *src1,
1384 const union tgsi_exec_channel *src2,
1385 const union tgsi_exec_channel *src3 )
1386 {
1387 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
1388 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
1389 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
1390 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
1391 }
1392
1393 static void
1394 micro_max(union tgsi_exec_channel *dst,
1395 const union tgsi_exec_channel *src0,
1396 const union tgsi_exec_channel *src1)
1397 {
1398 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
1399 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
1400 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
1401 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
1402 }
1403
1404 static void
1405 micro_min(union tgsi_exec_channel *dst,
1406 const union tgsi_exec_channel *src0,
1407 const union tgsi_exec_channel *src1)
1408 {
1409 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
1410 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
1411 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
1412 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
1413 }
1414
1415 static void
1416 micro_mul(union tgsi_exec_channel *dst,
1417 const union tgsi_exec_channel *src0,
1418 const union tgsi_exec_channel *src1)
1419 {
1420 dst->f[0] = src0->f[0] * src1->f[0];
1421 dst->f[1] = src0->f[1] * src1->f[1];
1422 dst->f[2] = src0->f[2] * src1->f[2];
1423 dst->f[3] = src0->f[3] * src1->f[3];
1424 }
1425
1426 static void
1427 micro_neg(
1428 union tgsi_exec_channel *dst,
1429 const union tgsi_exec_channel *src )
1430 {
1431 dst->f[0] = -src->f[0];
1432 dst->f[1] = -src->f[1];
1433 dst->f[2] = -src->f[2];
1434 dst->f[3] = -src->f[3];
1435 }
1436
1437 static void
1438 micro_pow(
1439 union tgsi_exec_channel *dst,
1440 const union tgsi_exec_channel *src0,
1441 const union tgsi_exec_channel *src1 )
1442 {
1443 #if FAST_MATH
1444 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
1445 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
1446 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
1447 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
1448 #else
1449 dst->f[0] = powf( src0->f[0], src1->f[0] );
1450 dst->f[1] = powf( src0->f[1], src1->f[1] );
1451 dst->f[2] = powf( src0->f[2], src1->f[2] );
1452 dst->f[3] = powf( src0->f[3], src1->f[3] );
1453 #endif
1454 }
1455
1456 static void
1457 micro_sub(union tgsi_exec_channel *dst,
1458 const union tgsi_exec_channel *src0,
1459 const union tgsi_exec_channel *src1)
1460 {
1461 dst->f[0] = src0->f[0] - src1->f[0];
1462 dst->f[1] = src0->f[1] - src1->f[1];
1463 dst->f[2] = src0->f[2] - src1->f[2];
1464 dst->f[3] = src0->f[3] - src1->f[3];
1465 }
1466
1467 static void
1468 fetch_src_file_channel(const struct tgsi_exec_machine *mach,
1469 const uint chan_index,
1470 const uint file,
1471 const uint swizzle,
1472 const union tgsi_exec_channel *index,
1473 const union tgsi_exec_channel *index2D,
1474 union tgsi_exec_channel *chan)
1475 {
1476 uint i;
1477
1478 assert(swizzle < 4);
1479
1480 switch (file) {
1481 case TGSI_FILE_CONSTANT:
1482 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1483 assert(index2D->i[i] >= 0 && index2D->i[i] < PIPE_MAX_CONSTANT_BUFFERS);
1484 assert(mach->Consts[index2D->i[i]]);
1485
1486 if (index->i[i] < 0) {
1487 chan->u[i] = 0;
1488 } else {
1489 /* NOTE: copying the const value as a uint instead of float */
1490 const uint constbuf = index2D->i[i];
1491 const uint *buf = (const uint *)mach->Consts[constbuf];
1492 const int pos = index->i[i] * 4 + swizzle;
1493 /* const buffer bounds check */
1494 if (pos < 0 || pos >= (int) mach->ConstsSize[constbuf]) {
1495 if (0) {
1496 /* Debug: print warning */
1497 static int count = 0;
1498 if (count++ < 100)
1499 debug_printf("TGSI Exec: const buffer index %d"
1500 " out of bounds\n", pos);
1501 }
1502 chan->u[i] = 0;
1503 }
1504 else
1505 chan->u[i] = buf[pos];
1506 }
1507 }
1508 break;
1509
1510 case TGSI_FILE_INPUT:
1511 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1512 /*
1513 if (PIPE_SHADER_GEOMETRY == mach->ShaderType) {
1514 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1515 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1516 index2D->i[i], index->i[i]);
1517 }*/
1518 int pos = index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i];
1519 assert(pos >= 0);
1520 assert(pos < TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS);
1521 chan->u[i] = mach->Inputs[pos].xyzw[swizzle].u[i];
1522 }
1523 break;
1524
1525 case TGSI_FILE_SYSTEM_VALUE:
1526 /* XXX no swizzling at this point. Will be needed if we put
1527 * gl_FragCoord, for example, in a sys value register.
1528 */
1529 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1530 chan->u[i] = mach->SystemValue[index->i[i]].xyzw[swizzle].u[i];
1531 }
1532 break;
1533
1534 case TGSI_FILE_TEMPORARY:
1535 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1536 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1537 assert(index2D->i[i] == 0);
1538
1539 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1540 }
1541 break;
1542
1543 case TGSI_FILE_IMMEDIATE:
1544 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1545 assert(index->i[i] >= 0 && index->i[i] < (int)mach->ImmLimit);
1546 assert(index2D->i[i] == 0);
1547
1548 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1549 }
1550 break;
1551
1552 case TGSI_FILE_ADDRESS:
1553 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1554 assert(index->i[i] >= 0);
1555 assert(index2D->i[i] == 0);
1556
1557 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1558 }
1559 break;
1560
1561 case TGSI_FILE_OUTPUT:
1562 /* vertex/fragment output vars can be read too */
1563 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1564 assert(index->i[i] >= 0);
1565 assert(index2D->i[i] == 0);
1566
1567 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1568 }
1569 break;
1570
1571 default:
1572 assert(0);
1573 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1574 chan->u[i] = 0;
1575 }
1576 }
1577 }
1578
1579 static void
1580 fetch_source_d(const struct tgsi_exec_machine *mach,
1581 union tgsi_exec_channel *chan,
1582 const struct tgsi_full_src_register *reg,
1583 const uint chan_index,
1584 enum tgsi_exec_datatype src_datatype)
1585 {
1586 union tgsi_exec_channel index;
1587 union tgsi_exec_channel index2D;
1588 uint swizzle;
1589
1590 /* We start with a direct index into a register file.
1591 *
1592 * file[1],
1593 * where:
1594 * file = Register.File
1595 * [1] = Register.Index
1596 */
1597 index.i[0] =
1598 index.i[1] =
1599 index.i[2] =
1600 index.i[3] = reg->Register.Index;
1601
1602 /* There is an extra source register that indirectly subscripts
1603 * a register file. The direct index now becomes an offset
1604 * that is being added to the indirect register.
1605 *
1606 * file[ind[2].x+1],
1607 * where:
1608 * ind = Indirect.File
1609 * [2] = Indirect.Index
1610 * .x = Indirect.SwizzleX
1611 */
1612 if (reg->Register.Indirect) {
1613 union tgsi_exec_channel index2;
1614 union tgsi_exec_channel indir_index;
1615 const uint execmask = mach->ExecMask;
1616 uint i;
1617
1618 /* which address register (always zero now) */
1619 index2.i[0] =
1620 index2.i[1] =
1621 index2.i[2] =
1622 index2.i[3] = reg->Indirect.Index;
1623 /* get current value of address register[swizzle] */
1624 swizzle = reg->Indirect.Swizzle;
1625 fetch_src_file_channel(mach,
1626 chan_index,
1627 reg->Indirect.File,
1628 swizzle,
1629 &index2,
1630 &ZeroVec,
1631 &indir_index);
1632
1633 /* add value of address register to the offset */
1634 index.i[0] += indir_index.i[0];
1635 index.i[1] += indir_index.i[1];
1636 index.i[2] += indir_index.i[2];
1637 index.i[3] += indir_index.i[3];
1638
1639 /* for disabled execution channels, zero-out the index to
1640 * avoid using a potential garbage value.
1641 */
1642 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1643 if ((execmask & (1 << i)) == 0)
1644 index.i[i] = 0;
1645 }
1646 }
1647
1648 /* There is an extra source register that is a second
1649 * subscript to a register file. Effectively it means that
1650 * the register file is actually a 2D array of registers.
1651 *
1652 * file[3][1],
1653 * where:
1654 * [3] = Dimension.Index
1655 */
1656 if (reg->Register.Dimension) {
1657 index2D.i[0] =
1658 index2D.i[1] =
1659 index2D.i[2] =
1660 index2D.i[3] = reg->Dimension.Index;
1661
1662 /* Again, the second subscript index can be addressed indirectly
1663 * identically to the first one.
1664 * Nothing stops us from indirectly addressing the indirect register,
1665 * but there is no need for that, so we won't exercise it.
1666 *
1667 * file[ind[4].y+3][1],
1668 * where:
1669 * ind = DimIndirect.File
1670 * [4] = DimIndirect.Index
1671 * .y = DimIndirect.SwizzleX
1672 */
1673 if (reg->Dimension.Indirect) {
1674 union tgsi_exec_channel index2;
1675 union tgsi_exec_channel indir_index;
1676 const uint execmask = mach->ExecMask;
1677 uint i;
1678
1679 index2.i[0] =
1680 index2.i[1] =
1681 index2.i[2] =
1682 index2.i[3] = reg->DimIndirect.Index;
1683
1684 swizzle = reg->DimIndirect.Swizzle;
1685 fetch_src_file_channel(mach,
1686 chan_index,
1687 reg->DimIndirect.File,
1688 swizzle,
1689 &index2,
1690 &ZeroVec,
1691 &indir_index);
1692
1693 index2D.i[0] += indir_index.i[0];
1694 index2D.i[1] += indir_index.i[1];
1695 index2D.i[2] += indir_index.i[2];
1696 index2D.i[3] += indir_index.i[3];
1697
1698 /* for disabled execution channels, zero-out the index to
1699 * avoid using a potential garbage value.
1700 */
1701 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1702 if ((execmask & (1 << i)) == 0) {
1703 index2D.i[i] = 0;
1704 }
1705 }
1706 }
1707
1708 /* If by any chance there was a need for a 3D array of register
1709 * files, we would have to check whether Dimension is followed
1710 * by a dimension register and continue the saga.
1711 */
1712 } else {
1713 index2D.i[0] =
1714 index2D.i[1] =
1715 index2D.i[2] =
1716 index2D.i[3] = 0;
1717 }
1718
1719 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1720 fetch_src_file_channel(mach,
1721 chan_index,
1722 reg->Register.File,
1723 swizzle,
1724 &index,
1725 &index2D,
1726 chan);
1727 }
1728
1729 static void
1730 fetch_source(const struct tgsi_exec_machine *mach,
1731 union tgsi_exec_channel *chan,
1732 const struct tgsi_full_src_register *reg,
1733 const uint chan_index,
1734 enum tgsi_exec_datatype src_datatype)
1735 {
1736 fetch_source_d(mach, chan, reg, chan_index, src_datatype);
1737
1738 if (reg->Register.Absolute) {
1739 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1740 micro_abs(chan, chan);
1741 } else {
1742 micro_iabs(chan, chan);
1743 }
1744 }
1745
1746 if (reg->Register.Negate) {
1747 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1748 micro_neg(chan, chan);
1749 } else {
1750 micro_ineg(chan, chan);
1751 }
1752 }
1753 }
1754
1755 static union tgsi_exec_channel *
1756 store_dest_dstret(struct tgsi_exec_machine *mach,
1757 const union tgsi_exec_channel *chan,
1758 const struct tgsi_full_dst_register *reg,
1759 const struct tgsi_full_instruction *inst,
1760 uint chan_index,
1761 enum tgsi_exec_datatype dst_datatype)
1762 {
1763 static union tgsi_exec_channel null;
1764 union tgsi_exec_channel *dst;
1765 union tgsi_exec_channel index2D;
1766 int offset = 0; /* indirection offset */
1767 int index;
1768
1769 /* for debugging */
1770 if (0 && dst_datatype == TGSI_EXEC_DATA_FLOAT) {
1771 check_inf_or_nan(chan);
1772 }
1773
1774 /* There is an extra source register that indirectly subscripts
1775 * a register file. The direct index now becomes an offset
1776 * that is being added to the indirect register.
1777 *
1778 * file[ind[2].x+1],
1779 * where:
1780 * ind = Indirect.File
1781 * [2] = Indirect.Index
1782 * .x = Indirect.SwizzleX
1783 */
1784 if (reg->Register.Indirect) {
1785 union tgsi_exec_channel index;
1786 union tgsi_exec_channel indir_index;
1787 uint swizzle;
1788
1789 /* which address register (always zero for now) */
1790 index.i[0] =
1791 index.i[1] =
1792 index.i[2] =
1793 index.i[3] = reg->Indirect.Index;
1794
1795 /* get current value of address register[swizzle] */
1796 swizzle = reg->Indirect.Swizzle;
1797
1798 /* fetch values from the address/indirection register */
1799 fetch_src_file_channel(mach,
1800 chan_index,
1801 reg->Indirect.File,
1802 swizzle,
1803 &index,
1804 &ZeroVec,
1805 &indir_index);
1806
1807 /* save indirection offset */
1808 offset = indir_index.i[0];
1809 }
1810
1811 /* There is an extra source register that is a second
1812 * subscript to a register file. Effectively it means that
1813 * the register file is actually a 2D array of registers.
1814 *
1815 * file[3][1],
1816 * where:
1817 * [3] = Dimension.Index
1818 */
1819 if (reg->Register.Dimension) {
1820 index2D.i[0] =
1821 index2D.i[1] =
1822 index2D.i[2] =
1823 index2D.i[3] = reg->Dimension.Index;
1824
1825 /* Again, the second subscript index can be addressed indirectly
1826 * identically to the first one.
1827 * Nothing stops us from indirectly addressing the indirect register,
1828 * but there is no need for that, so we won't exercise it.
1829 *
1830 * file[ind[4].y+3][1],
1831 * where:
1832 * ind = DimIndirect.File
1833 * [4] = DimIndirect.Index
1834 * .y = DimIndirect.SwizzleX
1835 */
1836 if (reg->Dimension.Indirect) {
1837 union tgsi_exec_channel index2;
1838 union tgsi_exec_channel indir_index;
1839 const uint execmask = mach->ExecMask;
1840 unsigned swizzle;
1841 uint i;
1842
1843 index2.i[0] =
1844 index2.i[1] =
1845 index2.i[2] =
1846 index2.i[3] = reg->DimIndirect.Index;
1847
1848 swizzle = reg->DimIndirect.Swizzle;
1849 fetch_src_file_channel(mach,
1850 chan_index,
1851 reg->DimIndirect.File,
1852 swizzle,
1853 &index2,
1854 &ZeroVec,
1855 &indir_index);
1856
1857 index2D.i[0] += indir_index.i[0];
1858 index2D.i[1] += indir_index.i[1];
1859 index2D.i[2] += indir_index.i[2];
1860 index2D.i[3] += indir_index.i[3];
1861
1862 /* for disabled execution channels, zero-out the index to
1863 * avoid using a potential garbage value.
1864 */
1865 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1866 if ((execmask & (1 << i)) == 0) {
1867 index2D.i[i] = 0;
1868 }
1869 }
1870 }
1871
1872 /* If by any chance there was a need for a 3D array of register
1873 * files, we would have to check whether Dimension is followed
1874 * by a dimension register and continue the saga.
1875 */
1876 } else {
1877 index2D.i[0] =
1878 index2D.i[1] =
1879 index2D.i[2] =
1880 index2D.i[3] = 0;
1881 }
1882
1883 switch (reg->Register.File) {
1884 case TGSI_FILE_NULL:
1885 dst = &null;
1886 break;
1887
1888 case TGSI_FILE_OUTPUT:
1889 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1890 + reg->Register.Index;
1891 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1892 #if 0
1893 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1894 mach->NumOutputs, mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0],
1895 reg->Register.Index);
1896 if (PIPE_SHADER_GEOMETRY == mach->ShaderType) {
1897 debug_printf("STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1898 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1899 if (execmask & (1 << i))
1900 debug_printf("%f, ", chan->f[i]);
1901 debug_printf(")\n");
1902 }
1903 #endif
1904 break;
1905
1906 case TGSI_FILE_TEMPORARY:
1907 index = reg->Register.Index;
1908 assert( index < TGSI_EXEC_NUM_TEMPS );
1909 dst = &mach->Temps[offset + index].xyzw[chan_index];
1910 break;
1911
1912 case TGSI_FILE_ADDRESS:
1913 index = reg->Register.Index;
1914 dst = &mach->Addrs[index].xyzw[chan_index];
1915 break;
1916
1917 default:
1918 assert( 0 );
1919 return NULL;
1920 }
1921
1922 return dst;
1923 }
1924
1925 static void
1926 store_dest_double(struct tgsi_exec_machine *mach,
1927 const union tgsi_exec_channel *chan,
1928 const struct tgsi_full_dst_register *reg,
1929 const struct tgsi_full_instruction *inst,
1930 uint chan_index,
1931 enum tgsi_exec_datatype dst_datatype)
1932 {
1933 union tgsi_exec_channel *dst;
1934 const uint execmask = mach->ExecMask;
1935 int i;
1936
1937 dst = store_dest_dstret(mach, chan, reg, inst, chan_index,
1938 dst_datatype);
1939 if (!dst)
1940 return;
1941
1942 /* doubles path */
1943 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1944 if (execmask & (1 << i))
1945 dst->i[i] = chan->i[i];
1946 }
1947
1948 static void
1949 store_dest(struct tgsi_exec_machine *mach,
1950 const union tgsi_exec_channel *chan,
1951 const struct tgsi_full_dst_register *reg,
1952 const struct tgsi_full_instruction *inst,
1953 uint chan_index,
1954 enum tgsi_exec_datatype dst_datatype)
1955 {
1956 union tgsi_exec_channel *dst;
1957 const uint execmask = mach->ExecMask;
1958 int i;
1959
1960 dst = store_dest_dstret(mach, chan, reg, inst, chan_index,
1961 dst_datatype);
1962 if (!dst)
1963 return;
1964
1965 if (!inst->Instruction.Saturate) {
1966 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1967 if (execmask & (1 << i))
1968 dst->i[i] = chan->i[i];
1969 }
1970 else {
1971 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1972 if (execmask & (1 << i)) {
1973 if (chan->f[i] < 0.0f)
1974 dst->f[i] = 0.0f;
1975 else if (chan->f[i] > 1.0f)
1976 dst->f[i] = 1.0f;
1977 else
1978 dst->i[i] = chan->i[i];
1979 }
1980 }
1981 }
1982
1983 #define FETCH(VAL,INDEX,CHAN)\
1984 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1985
1986 #define IFETCH(VAL,INDEX,CHAN)\
1987 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1988
1989
1990 /**
1991 * Execute ARB-style KIL which is predicated by a src register.
1992 * Kill fragment if any of the four values is less than zero.
1993 */
1994 static void
1995 exec_kill_if(struct tgsi_exec_machine *mach,
1996 const struct tgsi_full_instruction *inst)
1997 {
1998 uint uniquemask;
1999 uint chan_index;
2000 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
2001 union tgsi_exec_channel r[1];
2002
2003 /* This mask stores component bits that were already tested. */
2004 uniquemask = 0;
2005
2006 for (chan_index = 0; chan_index < 4; chan_index++)
2007 {
2008 uint swizzle;
2009 uint i;
2010
2011 /* unswizzle channel */
2012 swizzle = tgsi_util_get_full_src_register_swizzle (
2013 &inst->Src[0],
2014 chan_index);
2015
2016 /* check if the component has not been already tested */
2017 if (uniquemask & (1 << swizzle))
2018 continue;
2019 uniquemask |= 1 << swizzle;
2020
2021 FETCH(&r[0], 0, chan_index);
2022 for (i = 0; i < 4; i++)
2023 if (r[0].f[i] < 0.0f)
2024 kilmask |= 1 << i;
2025 }
2026
2027 /* restrict to fragments currently executing */
2028 kilmask &= mach->ExecMask;
2029
2030 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
2031 }
2032
2033 /**
2034 * Unconditional fragment kill/discard.
2035 */
2036 static void
2037 exec_kill(struct tgsi_exec_machine *mach,
2038 const struct tgsi_full_instruction *inst)
2039 {
2040 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
2041
2042 /* kill fragment for all fragments currently executing */
2043 kilmask = mach->ExecMask;
2044 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
2045 }
2046
2047 static void
2048 emit_vertex(struct tgsi_exec_machine *mach)
2049 {
2050 /* FIXME: check for exec mask correctly
2051 unsigned i;
2052 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
2053 if ((mach->ExecMask & (1 << i)))
2054 */
2055 if (mach->ExecMask) {
2056 if (mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]] >= mach->MaxOutputVertices)
2057 return;
2058
2059 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += mach->NumOutputs;
2060 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
2061 }
2062 }
2063
2064 static void
2065 emit_primitive(struct tgsi_exec_machine *mach)
2066 {
2067 unsigned *prim_count = &mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0];
2068 /* FIXME: check for exec mask correctly
2069 unsigned i;
2070 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
2071 if ((mach->ExecMask & (1 << i)))
2072 */
2073 if (mach->ExecMask) {
2074 ++(*prim_count);
2075 debug_assert((*prim_count * mach->NumOutputs) < mach->MaxGeometryShaderOutputs);
2076 mach->Primitives[*prim_count] = 0;
2077 }
2078 }
2079
2080 static void
2081 conditional_emit_primitive(struct tgsi_exec_machine *mach)
2082 {
2083 if (PIPE_SHADER_GEOMETRY == mach->ShaderType) {
2084 int emitted_verts =
2085 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]];
2086 if (emitted_verts) {
2087 emit_primitive(mach);
2088 }
2089 }
2090 }
2091
2092
2093 /*
2094 * Fetch four texture samples using STR texture coordinates.
2095 */
2096 static void
2097 fetch_texel( struct tgsi_sampler *sampler,
2098 const unsigned sview_idx,
2099 const unsigned sampler_idx,
2100 const union tgsi_exec_channel *s,
2101 const union tgsi_exec_channel *t,
2102 const union tgsi_exec_channel *p,
2103 const union tgsi_exec_channel *c0,
2104 const union tgsi_exec_channel *c1,
2105 float derivs[3][2][TGSI_QUAD_SIZE],
2106 const int8_t offset[3],
2107 enum tgsi_sampler_control control,
2108 union tgsi_exec_channel *r,
2109 union tgsi_exec_channel *g,
2110 union tgsi_exec_channel *b,
2111 union tgsi_exec_channel *a )
2112 {
2113 uint j;
2114 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
2115
2116 /* FIXME: handle explicit derivs, offsets */
2117 sampler->get_samples(sampler, sview_idx, sampler_idx,
2118 s->f, t->f, p->f, c0->f, c1->f, derivs, offset, control, rgba);
2119
2120 for (j = 0; j < 4; j++) {
2121 r->f[j] = rgba[0][j];
2122 g->f[j] = rgba[1][j];
2123 b->f[j] = rgba[2][j];
2124 a->f[j] = rgba[3][j];
2125 }
2126 }
2127
2128
2129 #define TEX_MODIFIER_NONE 0
2130 #define TEX_MODIFIER_PROJECTED 1
2131 #define TEX_MODIFIER_LOD_BIAS 2
2132 #define TEX_MODIFIER_EXPLICIT_LOD 3
2133 #define TEX_MODIFIER_LEVEL_ZERO 4
2134 #define TEX_MODIFIER_GATHER 5
2135
2136 /*
2137 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
2138 */
2139 static void
2140 fetch_texel_offsets(struct tgsi_exec_machine *mach,
2141 const struct tgsi_full_instruction *inst,
2142 int8_t offsets[3])
2143 {
2144 if (inst->Texture.NumOffsets == 1) {
2145 union tgsi_exec_channel index;
2146 union tgsi_exec_channel offset[3];
2147 index.i[0] = index.i[1] = index.i[2] = index.i[3] = inst->TexOffsets[0].Index;
2148 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
2149 inst->TexOffsets[0].SwizzleX, &index, &ZeroVec, &offset[0]);
2150 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
2151 inst->TexOffsets[0].SwizzleY, &index, &ZeroVec, &offset[1]);
2152 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
2153 inst->TexOffsets[0].SwizzleZ, &index, &ZeroVec, &offset[2]);
2154 offsets[0] = offset[0].i[0];
2155 offsets[1] = offset[1].i[0];
2156 offsets[2] = offset[2].i[0];
2157 } else {
2158 assert(inst->Texture.NumOffsets == 0);
2159 offsets[0] = offsets[1] = offsets[2] = 0;
2160 }
2161 }
2162
2163
2164 /*
2165 * Fetch dx and dy values for one channel (s, t or r).
2166 * Put dx values into one float array, dy values into another.
2167 */
2168 static void
2169 fetch_assign_deriv_channel(struct tgsi_exec_machine *mach,
2170 const struct tgsi_full_instruction *inst,
2171 unsigned regdsrcx,
2172 unsigned chan,
2173 float derivs[2][TGSI_QUAD_SIZE])
2174 {
2175 union tgsi_exec_channel d;
2176 FETCH(&d, regdsrcx, chan);
2177 derivs[0][0] = d.f[0];
2178 derivs[0][1] = d.f[1];
2179 derivs[0][2] = d.f[2];
2180 derivs[0][3] = d.f[3];
2181 FETCH(&d, regdsrcx + 1, chan);
2182 derivs[1][0] = d.f[0];
2183 derivs[1][1] = d.f[1];
2184 derivs[1][2] = d.f[2];
2185 derivs[1][3] = d.f[3];
2186 }
2187
2188 static uint
2189 fetch_sampler_unit(struct tgsi_exec_machine *mach,
2190 const struct tgsi_full_instruction *inst,
2191 uint sampler)
2192 {
2193 uint unit = 0;
2194 int i;
2195 if (inst->Src[sampler].Register.Indirect) {
2196 const struct tgsi_full_src_register *reg = &inst->Src[sampler];
2197 union tgsi_exec_channel indir_index, index2;
2198 const uint execmask = mach->ExecMask;
2199 index2.i[0] =
2200 index2.i[1] =
2201 index2.i[2] =
2202 index2.i[3] = reg->Indirect.Index;
2203
2204 fetch_src_file_channel(mach,
2205 0,
2206 reg->Indirect.File,
2207 reg->Indirect.Swizzle,
2208 &index2,
2209 &ZeroVec,
2210 &indir_index);
2211 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2212 if (execmask & (1 << i)) {
2213 unit = inst->Src[sampler].Register.Index + indir_index.i[i];
2214 break;
2215 }
2216 }
2217
2218 } else {
2219 unit = inst->Src[sampler].Register.Index;
2220 }
2221 return unit;
2222 }
2223
2224 /*
2225 * execute a texture instruction.
2226 *
2227 * modifier is used to control the channel routing for the
2228 * instruction variants like proj, lod, and texture with lod bias.
2229 * sampler indicates which src register the sampler is contained in.
2230 */
2231 static void
2232 exec_tex(struct tgsi_exec_machine *mach,
2233 const struct tgsi_full_instruction *inst,
2234 uint modifier, uint sampler)
2235 {
2236 const union tgsi_exec_channel *args[5], *proj = NULL;
2237 union tgsi_exec_channel r[5];
2238 enum tgsi_sampler_control control = TGSI_SAMPLER_LOD_NONE;
2239 uint chan;
2240 uint unit;
2241 int8_t offsets[3];
2242 int dim, shadow_ref, i;
2243
2244 unit = fetch_sampler_unit(mach, inst, sampler);
2245 /* always fetch all 3 offsets, overkill but keeps code simple */
2246 fetch_texel_offsets(mach, inst, offsets);
2247
2248 assert(modifier != TEX_MODIFIER_LEVEL_ZERO);
2249 assert(inst->Texture.Texture != TGSI_TEXTURE_BUFFER);
2250
2251 dim = tgsi_util_get_texture_coord_dim(inst->Texture.Texture);
2252 shadow_ref = tgsi_util_get_shadow_ref_src_index(inst->Texture.Texture);
2253
2254 assert(dim <= 4);
2255 if (shadow_ref >= 0)
2256 assert(shadow_ref >= dim && shadow_ref < ARRAY_SIZE(args));
2257
2258 /* fetch modifier to the last argument */
2259 if (modifier != TEX_MODIFIER_NONE) {
2260 const int last = ARRAY_SIZE(args) - 1;
2261
2262 /* fetch modifier from src0.w or src1.x */
2263 if (sampler == 1) {
2264 assert(dim <= TGSI_CHAN_W && shadow_ref != TGSI_CHAN_W);
2265 FETCH(&r[last], 0, TGSI_CHAN_W);
2266 }
2267 else {
2268 assert(shadow_ref != 4);
2269 FETCH(&r[last], 1, TGSI_CHAN_X);
2270 }
2271
2272 if (modifier != TEX_MODIFIER_PROJECTED) {
2273 args[last] = &r[last];
2274 }
2275 else {
2276 proj = &r[last];
2277 args[last] = &ZeroVec;
2278 }
2279
2280 /* point unused arguments to zero vector */
2281 for (i = dim; i < last; i++)
2282 args[i] = &ZeroVec;
2283
2284 if (modifier == TEX_MODIFIER_EXPLICIT_LOD)
2285 control = TGSI_SAMPLER_LOD_EXPLICIT;
2286 else if (modifier == TEX_MODIFIER_LOD_BIAS)
2287 control = TGSI_SAMPLER_LOD_BIAS;
2288 else if (modifier == TEX_MODIFIER_GATHER)
2289 control = TGSI_SAMPLER_GATHER;
2290 }
2291 else {
2292 for (i = dim; i < ARRAY_SIZE(args); i++)
2293 args[i] = &ZeroVec;
2294 }
2295
2296 /* fetch coordinates */
2297 for (i = 0; i < dim; i++) {
2298 FETCH(&r[i], 0, TGSI_CHAN_X + i);
2299
2300 if (proj)
2301 micro_div(&r[i], &r[i], proj);
2302
2303 args[i] = &r[i];
2304 }
2305
2306 /* fetch reference value */
2307 if (shadow_ref >= 0) {
2308 FETCH(&r[shadow_ref], shadow_ref / 4, TGSI_CHAN_X + (shadow_ref % 4));
2309
2310 if (proj)
2311 micro_div(&r[shadow_ref], &r[shadow_ref], proj);
2312
2313 args[shadow_ref] = &r[shadow_ref];
2314 }
2315
2316 fetch_texel(mach->Sampler, unit, unit,
2317 args[0], args[1], args[2], args[3], args[4],
2318 NULL, offsets, control,
2319 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2320
2321 #if 0
2322 debug_printf("fetch r: %g %g %g %g\n",
2323 r[0].f[0], r[0].f[1], r[0].f[2], r[0].f[3]);
2324 debug_printf("fetch g: %g %g %g %g\n",
2325 r[1].f[0], r[1].f[1], r[1].f[2], r[1].f[3]);
2326 debug_printf("fetch b: %g %g %g %g\n",
2327 r[2].f[0], r[2].f[1], r[2].f[2], r[2].f[3]);
2328 debug_printf("fetch a: %g %g %g %g\n",
2329 r[3].f[0], r[3].f[1], r[3].f[2], r[3].f[3]);
2330 #endif
2331
2332 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2333 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2334 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2335 }
2336 }
2337 }
2338
2339 static void
2340 exec_lodq(struct tgsi_exec_machine *mach,
2341 const struct tgsi_full_instruction *inst)
2342 {
2343 uint unit;
2344 int dim;
2345 int i;
2346 union tgsi_exec_channel coords[4];
2347 const union tgsi_exec_channel *args[ARRAY_SIZE(coords)];
2348 union tgsi_exec_channel r[2];
2349
2350 unit = fetch_sampler_unit(mach, inst, 1);
2351 dim = tgsi_util_get_texture_coord_dim(inst->Texture.Texture);
2352 assert(dim <= ARRAY_SIZE(coords));
2353 /* fetch coordinates */
2354 for (i = 0; i < dim; i++) {
2355 FETCH(&coords[i], 0, TGSI_CHAN_X + i);
2356 args[i] = &coords[i];
2357 }
2358 for (i = dim; i < ARRAY_SIZE(coords); i++) {
2359 args[i] = &ZeroVec;
2360 }
2361 mach->Sampler->query_lod(mach->Sampler, unit, unit,
2362 args[0]->f,
2363 args[1]->f,
2364 args[2]->f,
2365 args[3]->f,
2366 TGSI_SAMPLER_LOD_NONE,
2367 r[0].f,
2368 r[1].f);
2369
2370 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2371 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_X,
2372 TGSI_EXEC_DATA_FLOAT);
2373 }
2374 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2375 store_dest(mach, &r[1], &inst->Dst[0], inst, TGSI_CHAN_Y,
2376 TGSI_EXEC_DATA_FLOAT);
2377 }
2378 }
2379
2380 static void
2381 exec_txd(struct tgsi_exec_machine *mach,
2382 const struct tgsi_full_instruction *inst)
2383 {
2384 union tgsi_exec_channel r[4];
2385 float derivs[3][2][TGSI_QUAD_SIZE];
2386 uint chan;
2387 uint unit;
2388 int8_t offsets[3];
2389
2390 unit = fetch_sampler_unit(mach, inst, 3);
2391 /* always fetch all 3 offsets, overkill but keeps code simple */
2392 fetch_texel_offsets(mach, inst, offsets);
2393
2394 switch (inst->Texture.Texture) {
2395 case TGSI_TEXTURE_1D:
2396 FETCH(&r[0], 0, TGSI_CHAN_X);
2397
2398 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2399
2400 fetch_texel(mach->Sampler, unit, unit,
2401 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2402 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2403 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2404 break;
2405
2406 case TGSI_TEXTURE_SHADOW1D:
2407 case TGSI_TEXTURE_1D_ARRAY:
2408 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2409 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
2410 FETCH(&r[0], 0, TGSI_CHAN_X);
2411 FETCH(&r[1], 0, TGSI_CHAN_Y);
2412 FETCH(&r[2], 0, TGSI_CHAN_Z);
2413
2414 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2415
2416 fetch_texel(mach->Sampler, unit, unit,
2417 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2418 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2419 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2420 break;
2421
2422 case TGSI_TEXTURE_2D:
2423 case TGSI_TEXTURE_RECT:
2424 FETCH(&r[0], 0, TGSI_CHAN_X);
2425 FETCH(&r[1], 0, TGSI_CHAN_Y);
2426
2427 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2428 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2429
2430 fetch_texel(mach->Sampler, unit, unit,
2431 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2432 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2433 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2434 break;
2435
2436
2437 case TGSI_TEXTURE_SHADOW2D:
2438 case TGSI_TEXTURE_SHADOWRECT:
2439 case TGSI_TEXTURE_2D_ARRAY:
2440 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2441 /* only SHADOW2D_ARRAY actually needs W */
2442 FETCH(&r[0], 0, TGSI_CHAN_X);
2443 FETCH(&r[1], 0, TGSI_CHAN_Y);
2444 FETCH(&r[2], 0, TGSI_CHAN_Z);
2445 FETCH(&r[3], 0, TGSI_CHAN_W);
2446
2447 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2448 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2449
2450 fetch_texel(mach->Sampler, unit, unit,
2451 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
2452 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2453 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2454 break;
2455
2456 case TGSI_TEXTURE_3D:
2457 case TGSI_TEXTURE_CUBE:
2458 case TGSI_TEXTURE_CUBE_ARRAY:
2459 case TGSI_TEXTURE_SHADOWCUBE:
2460 /* only TEXTURE_CUBE_ARRAY and TEXTURE_SHADOWCUBE actually need W */
2461 FETCH(&r[0], 0, TGSI_CHAN_X);
2462 FETCH(&r[1], 0, TGSI_CHAN_Y);
2463 FETCH(&r[2], 0, TGSI_CHAN_Z);
2464 FETCH(&r[3], 0, TGSI_CHAN_W);
2465
2466 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2467 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2468 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Z, derivs[2]);
2469
2470 fetch_texel(mach->Sampler, unit, unit,
2471 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
2472 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2473 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2474 break;
2475
2476 default:
2477 assert(0);
2478 }
2479
2480 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2481 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2482 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2483 }
2484 }
2485 }
2486
2487
2488 static void
2489 exec_txf(struct tgsi_exec_machine *mach,
2490 const struct tgsi_full_instruction *inst)
2491 {
2492 union tgsi_exec_channel r[4];
2493 uint chan;
2494 uint unit;
2495 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
2496 int j;
2497 int8_t offsets[3];
2498 unsigned target;
2499
2500 unit = fetch_sampler_unit(mach, inst, 1);
2501 /* always fetch all 3 offsets, overkill but keeps code simple */
2502 fetch_texel_offsets(mach, inst, offsets);
2503
2504 IFETCH(&r[3], 0, TGSI_CHAN_W);
2505
2506 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I ||
2507 inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I_MS) {
2508 target = mach->SamplerViews[unit].Resource;
2509 }
2510 else {
2511 target = inst->Texture.Texture;
2512 }
2513 switch(target) {
2514 case TGSI_TEXTURE_3D:
2515 case TGSI_TEXTURE_2D_ARRAY:
2516 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2517 case TGSI_TEXTURE_2D_ARRAY_MSAA:
2518 IFETCH(&r[2], 0, TGSI_CHAN_Z);
2519 /* fallthrough */
2520 case TGSI_TEXTURE_2D:
2521 case TGSI_TEXTURE_RECT:
2522 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2523 case TGSI_TEXTURE_SHADOW2D:
2524 case TGSI_TEXTURE_SHADOWRECT:
2525 case TGSI_TEXTURE_1D_ARRAY:
2526 case TGSI_TEXTURE_2D_MSAA:
2527 IFETCH(&r[1], 0, TGSI_CHAN_Y);
2528 /* fallthrough */
2529 case TGSI_TEXTURE_BUFFER:
2530 case TGSI_TEXTURE_1D:
2531 case TGSI_TEXTURE_SHADOW1D:
2532 IFETCH(&r[0], 0, TGSI_CHAN_X);
2533 break;
2534 default:
2535 assert(0);
2536 break;
2537 }
2538
2539 mach->Sampler->get_texel(mach->Sampler, unit, r[0].i, r[1].i, r[2].i, r[3].i,
2540 offsets, rgba);
2541
2542 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
2543 r[0].f[j] = rgba[0][j];
2544 r[1].f[j] = rgba[1][j];
2545 r[2].f[j] = rgba[2][j];
2546 r[3].f[j] = rgba[3][j];
2547 }
2548
2549 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I ||
2550 inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I_MS) {
2551 unsigned char swizzles[4];
2552 swizzles[0] = inst->Src[1].Register.SwizzleX;
2553 swizzles[1] = inst->Src[1].Register.SwizzleY;
2554 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2555 swizzles[3] = inst->Src[1].Register.SwizzleW;
2556
2557 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2558 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2559 store_dest(mach, &r[swizzles[chan]],
2560 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2561 }
2562 }
2563 }
2564 else {
2565 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2566 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2567 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2568 }
2569 }
2570 }
2571 }
2572
2573 static void
2574 exec_txq(struct tgsi_exec_machine *mach,
2575 const struct tgsi_full_instruction *inst)
2576 {
2577 int result[4];
2578 union tgsi_exec_channel r[4], src;
2579 uint chan;
2580 uint unit;
2581 int i,j;
2582
2583 unit = fetch_sampler_unit(mach, inst, 1);
2584
2585 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
2586
2587 /* XXX: This interface can't return per-pixel values */
2588 mach->Sampler->get_dims(mach->Sampler, unit, src.i[0], result);
2589
2590 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2591 for (j = 0; j < 4; j++) {
2592 r[j].i[i] = result[j];
2593 }
2594 }
2595
2596 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2597 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2598 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
2599 TGSI_EXEC_DATA_INT);
2600 }
2601 }
2602 }
2603
2604 static void
2605 exec_sample(struct tgsi_exec_machine *mach,
2606 const struct tgsi_full_instruction *inst,
2607 uint modifier, boolean compare)
2608 {
2609 const uint resource_unit = inst->Src[1].Register.Index;
2610 const uint sampler_unit = inst->Src[2].Register.Index;
2611 union tgsi_exec_channel r[5], c1;
2612 const union tgsi_exec_channel *lod = &ZeroVec;
2613 enum tgsi_sampler_control control = TGSI_SAMPLER_LOD_NONE;
2614 uint chan;
2615 unsigned char swizzles[4];
2616 int8_t offsets[3];
2617
2618 /* always fetch all 3 offsets, overkill but keeps code simple */
2619 fetch_texel_offsets(mach, inst, offsets);
2620
2621 assert(modifier != TEX_MODIFIER_PROJECTED);
2622
2623 if (modifier != TEX_MODIFIER_NONE) {
2624 if (modifier == TEX_MODIFIER_LOD_BIAS) {
2625 FETCH(&c1, 3, TGSI_CHAN_X);
2626 lod = &c1;
2627 control = TGSI_SAMPLER_LOD_BIAS;
2628 }
2629 else if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
2630 FETCH(&c1, 3, TGSI_CHAN_X);
2631 lod = &c1;
2632 control = TGSI_SAMPLER_LOD_EXPLICIT;
2633 }
2634 else if (modifier == TEX_MODIFIER_GATHER) {
2635 control = TGSI_SAMPLER_GATHER;
2636 }
2637 else {
2638 assert(modifier == TEX_MODIFIER_LEVEL_ZERO);
2639 control = TGSI_SAMPLER_LOD_ZERO;
2640 }
2641 }
2642
2643 FETCH(&r[0], 0, TGSI_CHAN_X);
2644
2645 switch (mach->SamplerViews[resource_unit].Resource) {
2646 case TGSI_TEXTURE_1D:
2647 if (compare) {
2648 FETCH(&r[2], 3, TGSI_CHAN_X);
2649 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2650 &r[0], &ZeroVec, &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2651 NULL, offsets, control,
2652 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2653 }
2654 else {
2655 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2656 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2657 NULL, offsets, control,
2658 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2659 }
2660 break;
2661
2662 case TGSI_TEXTURE_1D_ARRAY:
2663 case TGSI_TEXTURE_2D:
2664 case TGSI_TEXTURE_RECT:
2665 FETCH(&r[1], 0, TGSI_CHAN_Y);
2666 if (compare) {
2667 FETCH(&r[2], 3, TGSI_CHAN_X);
2668 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2669 &r[0], &r[1], &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2670 NULL, offsets, control,
2671 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2672 }
2673 else {
2674 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2675 &r[0], &r[1], &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2676 NULL, offsets, control,
2677 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2678 }
2679 break;
2680
2681 case TGSI_TEXTURE_2D_ARRAY:
2682 case TGSI_TEXTURE_3D:
2683 case TGSI_TEXTURE_CUBE:
2684 FETCH(&r[1], 0, TGSI_CHAN_Y);
2685 FETCH(&r[2], 0, TGSI_CHAN_Z);
2686 if(compare) {
2687 FETCH(&r[3], 3, TGSI_CHAN_X);
2688 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2689 &r[0], &r[1], &r[2], &r[3], lod,
2690 NULL, offsets, control,
2691 &r[0], &r[1], &r[2], &r[3]);
2692 }
2693 else {
2694 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2695 &r[0], &r[1], &r[2], &ZeroVec, lod,
2696 NULL, offsets, control,
2697 &r[0], &r[1], &r[2], &r[3]);
2698 }
2699 break;
2700
2701 case TGSI_TEXTURE_CUBE_ARRAY:
2702 FETCH(&r[1], 0, TGSI_CHAN_Y);
2703 FETCH(&r[2], 0, TGSI_CHAN_Z);
2704 FETCH(&r[3], 0, TGSI_CHAN_W);
2705 if(compare) {
2706 FETCH(&r[4], 3, TGSI_CHAN_X);
2707 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2708 &r[0], &r[1], &r[2], &r[3], &r[4],
2709 NULL, offsets, control,
2710 &r[0], &r[1], &r[2], &r[3]);
2711 }
2712 else {
2713 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2714 &r[0], &r[1], &r[2], &r[3], lod,
2715 NULL, offsets, control,
2716 &r[0], &r[1], &r[2], &r[3]);
2717 }
2718 break;
2719
2720
2721 default:
2722 assert(0);
2723 }
2724
2725 swizzles[0] = inst->Src[1].Register.SwizzleX;
2726 swizzles[1] = inst->Src[1].Register.SwizzleY;
2727 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2728 swizzles[3] = inst->Src[1].Register.SwizzleW;
2729
2730 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2731 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2732 store_dest(mach, &r[swizzles[chan]],
2733 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2734 }
2735 }
2736 }
2737
2738 static void
2739 exec_sample_d(struct tgsi_exec_machine *mach,
2740 const struct tgsi_full_instruction *inst)
2741 {
2742 const uint resource_unit = inst->Src[1].Register.Index;
2743 const uint sampler_unit = inst->Src[2].Register.Index;
2744 union tgsi_exec_channel r[4];
2745 float derivs[3][2][TGSI_QUAD_SIZE];
2746 uint chan;
2747 unsigned char swizzles[4];
2748 int8_t offsets[3];
2749
2750 /* always fetch all 3 offsets, overkill but keeps code simple */
2751 fetch_texel_offsets(mach, inst, offsets);
2752
2753 FETCH(&r[0], 0, TGSI_CHAN_X);
2754
2755 switch (mach->SamplerViews[resource_unit].Resource) {
2756 case TGSI_TEXTURE_1D:
2757 case TGSI_TEXTURE_1D_ARRAY:
2758 /* only 1D array actually needs Y */
2759 FETCH(&r[1], 0, TGSI_CHAN_Y);
2760
2761 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2762
2763 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2764 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2765 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2766 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2767 break;
2768
2769 case TGSI_TEXTURE_2D:
2770 case TGSI_TEXTURE_RECT:
2771 case TGSI_TEXTURE_2D_ARRAY:
2772 /* only 2D array actually needs Z */
2773 FETCH(&r[1], 0, TGSI_CHAN_Y);
2774 FETCH(&r[2], 0, TGSI_CHAN_Z);
2775
2776 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2777 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2778
2779 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2780 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* inputs */
2781 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2782 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2783 break;
2784
2785 case TGSI_TEXTURE_3D:
2786 case TGSI_TEXTURE_CUBE:
2787 case TGSI_TEXTURE_CUBE_ARRAY:
2788 /* only cube array actually needs W */
2789 FETCH(&r[1], 0, TGSI_CHAN_Y);
2790 FETCH(&r[2], 0, TGSI_CHAN_Z);
2791 FETCH(&r[3], 0, TGSI_CHAN_W);
2792
2793 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2794 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2795 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Z, derivs[2]);
2796
2797 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2798 &r[0], &r[1], &r[2], &r[3], &ZeroVec,
2799 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2800 &r[0], &r[1], &r[2], &r[3]);
2801 break;
2802
2803 default:
2804 assert(0);
2805 }
2806
2807 swizzles[0] = inst->Src[1].Register.SwizzleX;
2808 swizzles[1] = inst->Src[1].Register.SwizzleY;
2809 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2810 swizzles[3] = inst->Src[1].Register.SwizzleW;
2811
2812 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2813 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2814 store_dest(mach, &r[swizzles[chan]],
2815 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2816 }
2817 }
2818 }
2819
2820
2821 /**
2822 * Evaluate a constant-valued coefficient at the position of the
2823 * current quad.
2824 */
2825 static void
2826 eval_constant_coef(
2827 struct tgsi_exec_machine *mach,
2828 unsigned attrib,
2829 unsigned chan )
2830 {
2831 unsigned i;
2832
2833 for( i = 0; i < TGSI_QUAD_SIZE; i++ ) {
2834 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
2835 }
2836 }
2837
2838 /**
2839 * Evaluate a linear-valued coefficient at the position of the
2840 * current quad.
2841 */
2842 static void
2843 eval_linear_coef(
2844 struct tgsi_exec_machine *mach,
2845 unsigned attrib,
2846 unsigned chan )
2847 {
2848 const float x = mach->QuadPos.xyzw[0].f[0];
2849 const float y = mach->QuadPos.xyzw[1].f[0];
2850 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2851 const float dady = mach->InterpCoefs[attrib].dady[chan];
2852 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2853 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
2854 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
2855 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
2856 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
2857 }
2858
2859 /**
2860 * Evaluate a perspective-valued coefficient at the position of the
2861 * current quad.
2862 */
2863 static void
2864 eval_perspective_coef(
2865 struct tgsi_exec_machine *mach,
2866 unsigned attrib,
2867 unsigned chan )
2868 {
2869 const float x = mach->QuadPos.xyzw[0].f[0];
2870 const float y = mach->QuadPos.xyzw[1].f[0];
2871 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2872 const float dady = mach->InterpCoefs[attrib].dady[chan];
2873 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2874 const float *w = mach->QuadPos.xyzw[3].f;
2875 /* divide by W here */
2876 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
2877 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
2878 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
2879 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
2880 }
2881
2882
2883 typedef void (* eval_coef_func)(
2884 struct tgsi_exec_machine *mach,
2885 unsigned attrib,
2886 unsigned chan );
2887
2888 static void
2889 exec_declaration(struct tgsi_exec_machine *mach,
2890 const struct tgsi_full_declaration *decl)
2891 {
2892 if (decl->Declaration.File == TGSI_FILE_SAMPLER_VIEW) {
2893 mach->SamplerViews[decl->Range.First] = decl->SamplerView;
2894 return;
2895 }
2896
2897 if (mach->ShaderType == PIPE_SHADER_FRAGMENT) {
2898 if (decl->Declaration.File == TGSI_FILE_INPUT) {
2899 uint first, last, mask;
2900
2901 first = decl->Range.First;
2902 last = decl->Range.Last;
2903 mask = decl->Declaration.UsageMask;
2904
2905 /* XXX we could remove this special-case code since
2906 * mach->InterpCoefs[first].a0 should already have the
2907 * front/back-face value. But we should first update the
2908 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2909 * Then, we could remove the tgsi_exec_machine::Face field.
2910 */
2911 /* XXX make FACE a system value */
2912 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
2913 uint i;
2914
2915 assert(decl->Semantic.Index == 0);
2916 assert(first == last);
2917
2918 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2919 mach->Inputs[first].xyzw[0].f[i] = mach->Face;
2920 }
2921 } else {
2922 eval_coef_func eval;
2923 uint i, j;
2924
2925 switch (decl->Interp.Interpolate) {
2926 case TGSI_INTERPOLATE_CONSTANT:
2927 eval = eval_constant_coef;
2928 break;
2929
2930 case TGSI_INTERPOLATE_LINEAR:
2931 eval = eval_linear_coef;
2932 break;
2933
2934 case TGSI_INTERPOLATE_PERSPECTIVE:
2935 eval = eval_perspective_coef;
2936 break;
2937
2938 case TGSI_INTERPOLATE_COLOR:
2939 eval = mach->flatshade_color ? eval_constant_coef : eval_perspective_coef;
2940 break;
2941
2942 default:
2943 assert(0);
2944 return;
2945 }
2946
2947 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2948 if (mask & (1 << j)) {
2949 for (i = first; i <= last; i++) {
2950 eval(mach, i, j);
2951 }
2952 }
2953 }
2954 }
2955
2956 if (DEBUG_EXECUTION) {
2957 uint i, j;
2958 for (i = first; i <= last; ++i) {
2959 debug_printf("IN[%2u] = ", i);
2960 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2961 if (j > 0) {
2962 debug_printf(" ");
2963 }
2964 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
2965 mach->Inputs[i].xyzw[0].f[j], mach->Inputs[i].xyzw[0].u[j],
2966 mach->Inputs[i].xyzw[1].f[j], mach->Inputs[i].xyzw[1].u[j],
2967 mach->Inputs[i].xyzw[2].f[j], mach->Inputs[i].xyzw[2].u[j],
2968 mach->Inputs[i].xyzw[3].f[j], mach->Inputs[i].xyzw[3].u[j]);
2969 }
2970 }
2971 }
2972 }
2973 }
2974
2975 }
2976
2977 typedef void (* micro_unary_op)(union tgsi_exec_channel *dst,
2978 const union tgsi_exec_channel *src);
2979
2980 static void
2981 exec_scalar_unary(struct tgsi_exec_machine *mach,
2982 const struct tgsi_full_instruction *inst,
2983 micro_unary_op op,
2984 enum tgsi_exec_datatype dst_datatype,
2985 enum tgsi_exec_datatype src_datatype)
2986 {
2987 unsigned int chan;
2988 union tgsi_exec_channel src;
2989 union tgsi_exec_channel dst;
2990
2991 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, src_datatype);
2992 op(&dst, &src);
2993 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2994 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2995 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2996 }
2997 }
2998 }
2999
3000 static void
3001 exec_vector_unary(struct tgsi_exec_machine *mach,
3002 const struct tgsi_full_instruction *inst,
3003 micro_unary_op op,
3004 enum tgsi_exec_datatype dst_datatype,
3005 enum tgsi_exec_datatype src_datatype)
3006 {
3007 unsigned int chan;
3008 struct tgsi_exec_vector dst;
3009
3010 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3011 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3012 union tgsi_exec_channel src;
3013
3014 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
3015 op(&dst.xyzw[chan], &src);
3016 }
3017 }
3018 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3019 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3020 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
3021 }
3022 }
3023 }
3024
3025 typedef void (* micro_binary_op)(union tgsi_exec_channel *dst,
3026 const union tgsi_exec_channel *src0,
3027 const union tgsi_exec_channel *src1);
3028
3029 static void
3030 exec_scalar_binary(struct tgsi_exec_machine *mach,
3031 const struct tgsi_full_instruction *inst,
3032 micro_binary_op op,
3033 enum tgsi_exec_datatype dst_datatype,
3034 enum tgsi_exec_datatype src_datatype)
3035 {
3036 unsigned int chan;
3037 union tgsi_exec_channel src[2];
3038 union tgsi_exec_channel dst;
3039
3040 fetch_source(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, src_datatype);
3041 fetch_source(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, src_datatype);
3042 op(&dst, &src[0], &src[1]);
3043 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3044 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3045 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
3046 }
3047 }
3048 }
3049
3050 static void
3051 exec_vector_binary(struct tgsi_exec_machine *mach,
3052 const struct tgsi_full_instruction *inst,
3053 micro_binary_op op,
3054 enum tgsi_exec_datatype dst_datatype,
3055 enum tgsi_exec_datatype src_datatype)
3056 {
3057 unsigned int chan;
3058 struct tgsi_exec_vector dst;
3059
3060 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3061 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3062 union tgsi_exec_channel src[2];
3063
3064 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
3065 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
3066 op(&dst.xyzw[chan], &src[0], &src[1]);
3067 }
3068 }
3069 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3070 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3071 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
3072 }
3073 }
3074 }
3075
3076 typedef void (* micro_trinary_op)(union tgsi_exec_channel *dst,
3077 const union tgsi_exec_channel *src0,
3078 const union tgsi_exec_channel *src1,
3079 const union tgsi_exec_channel *src2);
3080
3081 static void
3082 exec_vector_trinary(struct tgsi_exec_machine *mach,
3083 const struct tgsi_full_instruction *inst,
3084 micro_trinary_op op,
3085 enum tgsi_exec_datatype dst_datatype,
3086 enum tgsi_exec_datatype src_datatype)
3087 {
3088 unsigned int chan;
3089 struct tgsi_exec_vector dst;
3090
3091 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3092 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3093 union tgsi_exec_channel src[3];
3094
3095 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
3096 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
3097 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
3098 op(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
3099 }
3100 }
3101 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3102 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3103 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
3104 }
3105 }
3106 }
3107
3108 typedef void (* micro_quaternary_op)(union tgsi_exec_channel *dst,
3109 const union tgsi_exec_channel *src0,
3110 const union tgsi_exec_channel *src1,
3111 const union tgsi_exec_channel *src2,
3112 const union tgsi_exec_channel *src3);
3113
3114 static void
3115 exec_vector_quaternary(struct tgsi_exec_machine *mach,
3116 const struct tgsi_full_instruction *inst,
3117 micro_quaternary_op op,
3118 enum tgsi_exec_datatype dst_datatype,
3119 enum tgsi_exec_datatype src_datatype)
3120 {
3121 unsigned int chan;
3122 struct tgsi_exec_vector dst;
3123
3124 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3125 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3126 union tgsi_exec_channel src[4];
3127
3128 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
3129 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
3130 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
3131 fetch_source(mach, &src[3], &inst->Src[3], chan, src_datatype);
3132 op(&dst.xyzw[chan], &src[0], &src[1], &src[2], &src[3]);
3133 }
3134 }
3135 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3136 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3137 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
3138 }
3139 }
3140 }
3141
3142 static void
3143 exec_dp3(struct tgsi_exec_machine *mach,
3144 const struct tgsi_full_instruction *inst)
3145 {
3146 unsigned int chan;
3147 union tgsi_exec_channel arg[3];
3148
3149 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3150 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3151 micro_mul(&arg[2], &arg[0], &arg[1]);
3152
3153 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_Z; chan++) {
3154 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
3155 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
3156 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
3157 }
3158
3159 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3160 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3161 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3162 }
3163 }
3164 }
3165
3166 static void
3167 exec_dp4(struct tgsi_exec_machine *mach,
3168 const struct tgsi_full_instruction *inst)
3169 {
3170 unsigned int chan;
3171 union tgsi_exec_channel arg[3];
3172
3173 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3174 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3175 micro_mul(&arg[2], &arg[0], &arg[1]);
3176
3177 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_W; chan++) {
3178 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
3179 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
3180 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
3181 }
3182
3183 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3184 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3185 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3186 }
3187 }
3188 }
3189
3190 static void
3191 exec_dp2(struct tgsi_exec_machine *mach,
3192 const struct tgsi_full_instruction *inst)
3193 {
3194 unsigned int chan;
3195 union tgsi_exec_channel arg[3];
3196
3197 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3198 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3199 micro_mul(&arg[2], &arg[0], &arg[1]);
3200
3201 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3202 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3203 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
3204
3205 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3206 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3207 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3208 }
3209 }
3210 }
3211
3212 static void
3213 exec_pk2h(struct tgsi_exec_machine *mach,
3214 const struct tgsi_full_instruction *inst)
3215 {
3216 unsigned chan;
3217 union tgsi_exec_channel arg[2], dst;
3218
3219 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3220 fetch_source(mach, &arg[1], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3221 for (chan = 0; chan < TGSI_QUAD_SIZE; chan++) {
3222 dst.u[chan] = util_float_to_half(arg[0].f[chan]) |
3223 (util_float_to_half(arg[1].f[chan]) << 16);
3224 }
3225 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3226 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3227 store_dest(mach, &dst, &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_UINT);
3228 }
3229 }
3230 }
3231
3232 static void
3233 exec_up2h(struct tgsi_exec_machine *mach,
3234 const struct tgsi_full_instruction *inst)
3235 {
3236 unsigned chan;
3237 union tgsi_exec_channel arg, dst[2];
3238
3239 fetch_source(mach, &arg, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3240 for (chan = 0; chan < TGSI_QUAD_SIZE; chan++) {
3241 dst[0].f[chan] = util_half_to_float(arg.u[chan] & 0xffff);
3242 dst[1].f[chan] = util_half_to_float(arg.u[chan] >> 16);
3243 }
3244 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3245 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3246 store_dest(mach, &dst[chan & 1], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3247 }
3248 }
3249 }
3250
3251 static void
3252 micro_ucmp(union tgsi_exec_channel *dst,
3253 const union tgsi_exec_channel *src0,
3254 const union tgsi_exec_channel *src1,
3255 const union tgsi_exec_channel *src2)
3256 {
3257 dst->f[0] = src0->u[0] ? src1->f[0] : src2->f[0];
3258 dst->f[1] = src0->u[1] ? src1->f[1] : src2->f[1];
3259 dst->f[2] = src0->u[2] ? src1->f[2] : src2->f[2];
3260 dst->f[3] = src0->u[3] ? src1->f[3] : src2->f[3];
3261 }
3262
3263 static void
3264 exec_ucmp(struct tgsi_exec_machine *mach,
3265 const struct tgsi_full_instruction *inst)
3266 {
3267 unsigned int chan;
3268 struct tgsi_exec_vector dst;
3269
3270 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3271 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3272 union tgsi_exec_channel src[3];
3273
3274 fetch_source(mach, &src[0], &inst->Src[0], chan,
3275 TGSI_EXEC_DATA_UINT);
3276 fetch_source(mach, &src[1], &inst->Src[1], chan,
3277 TGSI_EXEC_DATA_FLOAT);
3278 fetch_source(mach, &src[2], &inst->Src[2], chan,
3279 TGSI_EXEC_DATA_FLOAT);
3280 micro_ucmp(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
3281 }
3282 }
3283 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3284 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3285 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan,
3286 TGSI_EXEC_DATA_FLOAT);
3287 }
3288 }
3289 }
3290
3291 static void
3292 exec_dst(struct tgsi_exec_machine *mach,
3293 const struct tgsi_full_instruction *inst)
3294 {
3295 union tgsi_exec_channel r[2];
3296 union tgsi_exec_channel d[4];
3297
3298 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3299 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3300 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3301 micro_mul(&d[TGSI_CHAN_Y], &r[0], &r[1]);
3302 }
3303 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3304 fetch_source(mach, &d[TGSI_CHAN_Z], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3305 }
3306 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3307 fetch_source(mach, &d[TGSI_CHAN_W], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3308 }
3309
3310 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3311 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3312 }
3313 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3314 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3315 }
3316 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3317 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3318 }
3319 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3320 store_dest(mach, &d[TGSI_CHAN_W], &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3321 }
3322 }
3323
3324 static void
3325 exec_log(struct tgsi_exec_machine *mach,
3326 const struct tgsi_full_instruction *inst)
3327 {
3328 union tgsi_exec_channel r[3];
3329
3330 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3331 micro_abs(&r[2], &r[0]); /* r2 = abs(r0) */
3332 micro_lg2(&r[1], &r[2]); /* r1 = lg2(r2) */
3333 micro_flr(&r[0], &r[1]); /* r0 = floor(r1) */
3334 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3335 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3336 }
3337 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3338 micro_exp2(&r[0], &r[0]); /* r0 = 2 ^ r0 */
3339 micro_div(&r[0], &r[2], &r[0]); /* r0 = r2 / r0 */
3340 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3341 }
3342 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3343 store_dest(mach, &r[1], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3344 }
3345 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3346 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3347 }
3348 }
3349
3350 static void
3351 exec_exp(struct tgsi_exec_machine *mach,
3352 const struct tgsi_full_instruction *inst)
3353 {
3354 union tgsi_exec_channel r[3];
3355
3356 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3357 micro_flr(&r[1], &r[0]); /* r1 = floor(r0) */
3358 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3359 micro_exp2(&r[2], &r[1]); /* r2 = 2 ^ r1 */
3360 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3361 }
3362 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3363 micro_sub(&r[2], &r[0], &r[1]); /* r2 = r0 - r1 */
3364 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3365 }
3366 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3367 micro_exp2(&r[2], &r[0]); /* r2 = 2 ^ r0 */
3368 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3369 }
3370 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3371 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3372 }
3373 }
3374
3375 static void
3376 exec_lit(struct tgsi_exec_machine *mach,
3377 const struct tgsi_full_instruction *inst)
3378 {
3379 union tgsi_exec_channel r[3];
3380 union tgsi_exec_channel d[3];
3381
3382 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YZ) {
3383 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3384 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3385 fetch_source(mach, &r[1], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3386 micro_max(&r[1], &r[1], &ZeroVec);
3387
3388 fetch_source(mach, &r[2], &inst->Src[0], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3389 micro_min(&r[2], &r[2], &P128Vec);
3390 micro_max(&r[2], &r[2], &M128Vec);
3391 micro_pow(&r[1], &r[1], &r[2]);
3392 micro_lt(&d[TGSI_CHAN_Z], &ZeroVec, &r[0], &r[1], &ZeroVec);
3393 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3394 }
3395 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3396 micro_max(&d[TGSI_CHAN_Y], &r[0], &ZeroVec);
3397 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3398 }
3399 }
3400 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3401 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3402 }
3403
3404 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3405 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3406 }
3407 }
3408
3409 static void
3410 exec_break(struct tgsi_exec_machine *mach)
3411 {
3412 if (mach->BreakType == TGSI_EXEC_BREAK_INSIDE_LOOP) {
3413 /* turn off loop channels for each enabled exec channel */
3414 mach->LoopMask &= ~mach->ExecMask;
3415 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3416 UPDATE_EXEC_MASK(mach);
3417 } else {
3418 assert(mach->BreakType == TGSI_EXEC_BREAK_INSIDE_SWITCH);
3419
3420 mach->Switch.mask = 0x0;
3421
3422 UPDATE_EXEC_MASK(mach);
3423 }
3424 }
3425
3426 static void
3427 exec_switch(struct tgsi_exec_machine *mach,
3428 const struct tgsi_full_instruction *inst)
3429 {
3430 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3431 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3432
3433 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3434 fetch_source(mach, &mach->Switch.selector, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3435 mach->Switch.mask = 0x0;
3436 mach->Switch.defaultMask = 0x0;
3437
3438 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3439 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_SWITCH;
3440
3441 UPDATE_EXEC_MASK(mach);
3442 }
3443
3444 static void
3445 exec_case(struct tgsi_exec_machine *mach,
3446 const struct tgsi_full_instruction *inst)
3447 {
3448 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3449 union tgsi_exec_channel src;
3450 uint mask = 0;
3451
3452 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3453
3454 if (mach->Switch.selector.u[0] == src.u[0]) {
3455 mask |= 0x1;
3456 }
3457 if (mach->Switch.selector.u[1] == src.u[1]) {
3458 mask |= 0x2;
3459 }
3460 if (mach->Switch.selector.u[2] == src.u[2]) {
3461 mask |= 0x4;
3462 }
3463 if (mach->Switch.selector.u[3] == src.u[3]) {
3464 mask |= 0x8;
3465 }
3466
3467 mach->Switch.defaultMask |= mask;
3468
3469 mach->Switch.mask |= mask & prevMask;
3470
3471 UPDATE_EXEC_MASK(mach);
3472 }
3473
3474 /* FIXME: this will only work if default is last */
3475 static void
3476 exec_default(struct tgsi_exec_machine *mach)
3477 {
3478 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3479
3480 mach->Switch.mask |= ~mach->Switch.defaultMask & prevMask;
3481
3482 UPDATE_EXEC_MASK(mach);
3483 }
3484
3485 static void
3486 exec_endswitch(struct tgsi_exec_machine *mach)
3487 {
3488 mach->Switch = mach->SwitchStack[--mach->SwitchStackTop];
3489 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3490
3491 UPDATE_EXEC_MASK(mach);
3492 }
3493
3494 typedef void (* micro_dop)(union tgsi_double_channel *dst,
3495 const union tgsi_double_channel *src);
3496
3497 typedef void (* micro_dop_sop)(union tgsi_double_channel *dst,
3498 const union tgsi_double_channel *src0,
3499 union tgsi_exec_channel *src1);
3500
3501 typedef void (* micro_dop_s)(union tgsi_double_channel *dst,
3502 const union tgsi_exec_channel *src);
3503
3504 typedef void (* micro_sop_d)(union tgsi_exec_channel *dst,
3505 const union tgsi_double_channel *src);
3506
3507 static void
3508 fetch_double_channel(struct tgsi_exec_machine *mach,
3509 union tgsi_double_channel *chan,
3510 const struct tgsi_full_src_register *reg,
3511 uint chan_0,
3512 uint chan_1)
3513 {
3514 union tgsi_exec_channel src[2];
3515 uint i;
3516
3517 fetch_source_d(mach, &src[0], reg, chan_0, TGSI_EXEC_DATA_UINT);
3518 fetch_source_d(mach, &src[1], reg, chan_1, TGSI_EXEC_DATA_UINT);
3519
3520 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
3521 chan->u[i][0] = src[0].u[i];
3522 chan->u[i][1] = src[1].u[i];
3523 }
3524 if (reg->Register.Absolute) {
3525 micro_dabs(chan, chan);
3526 }
3527 if (reg->Register.Negate) {
3528 micro_dneg(chan, chan);
3529 }
3530 }
3531
3532 static void
3533 store_double_channel(struct tgsi_exec_machine *mach,
3534 const union tgsi_double_channel *chan,
3535 const struct tgsi_full_dst_register *reg,
3536 const struct tgsi_full_instruction *inst,
3537 uint chan_0,
3538 uint chan_1)
3539 {
3540 union tgsi_exec_channel dst[2];
3541 uint i;
3542 union tgsi_double_channel temp;
3543 const uint execmask = mach->ExecMask;
3544
3545 if (!inst->Instruction.Saturate) {
3546 for (i = 0; i < TGSI_QUAD_SIZE; i++)
3547 if (execmask & (1 << i)) {
3548 dst[0].u[i] = chan->u[i][0];
3549 dst[1].u[i] = chan->u[i][1];
3550 }
3551 }
3552 else {
3553 for (i = 0; i < TGSI_QUAD_SIZE; i++)
3554 if (execmask & (1 << i)) {
3555 if (chan->d[i] < 0.0)
3556 temp.d[i] = 0.0;
3557 else if (chan->d[i] > 1.0)
3558 temp.d[i] = 1.0;
3559 else
3560 temp.d[i] = chan->d[i];
3561
3562 dst[0].u[i] = temp.u[i][0];
3563 dst[1].u[i] = temp.u[i][1];
3564 }
3565 }
3566
3567 store_dest_double(mach, &dst[0], reg, inst, chan_0, TGSI_EXEC_DATA_UINT);
3568 if (chan_1 != -1)
3569 store_dest_double(mach, &dst[1], reg, inst, chan_1, TGSI_EXEC_DATA_UINT);
3570 }
3571
3572 static void
3573 exec_double_unary(struct tgsi_exec_machine *mach,
3574 const struct tgsi_full_instruction *inst,
3575 micro_dop op)
3576 {
3577 union tgsi_double_channel src;
3578 union tgsi_double_channel dst;
3579
3580 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3581 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3582 op(&dst, &src);
3583 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3584 }
3585 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3586 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3587 op(&dst, &src);
3588 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3589 }
3590 }
3591
3592 static void
3593 exec_double_binary(struct tgsi_exec_machine *mach,
3594 const struct tgsi_full_instruction *inst,
3595 micro_dop op,
3596 enum tgsi_exec_datatype dst_datatype)
3597 {
3598 union tgsi_double_channel src[2];
3599 union tgsi_double_channel dst;
3600 int first_dest_chan, second_dest_chan;
3601 int wmask;
3602
3603 wmask = inst->Dst[0].Register.WriteMask;
3604 /* these are & because of the way DSLT etc store their destinations */
3605 if (wmask & TGSI_WRITEMASK_XY) {
3606 first_dest_chan = TGSI_CHAN_X;
3607 second_dest_chan = TGSI_CHAN_Y;
3608 if (dst_datatype == TGSI_EXEC_DATA_UINT) {
3609 first_dest_chan = (wmask & TGSI_WRITEMASK_X) ? TGSI_CHAN_X : TGSI_CHAN_Y;
3610 second_dest_chan = -1;
3611 }
3612
3613 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3614 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, TGSI_CHAN_Y);
3615 op(&dst, src);
3616 store_double_channel(mach, &dst, &inst->Dst[0], inst, first_dest_chan, second_dest_chan);
3617 }
3618
3619 if (wmask & TGSI_WRITEMASK_ZW) {
3620 first_dest_chan = TGSI_CHAN_Z;
3621 second_dest_chan = TGSI_CHAN_W;
3622 if (dst_datatype == TGSI_EXEC_DATA_UINT) {
3623 first_dest_chan = (wmask & TGSI_WRITEMASK_Z) ? TGSI_CHAN_Z : TGSI_CHAN_W;
3624 second_dest_chan = -1;
3625 }
3626
3627 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3628 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_CHAN_W);
3629 op(&dst, src);
3630 store_double_channel(mach, &dst, &inst->Dst[0], inst, first_dest_chan, second_dest_chan);
3631 }
3632 }
3633
3634 static void
3635 exec_double_trinary(struct tgsi_exec_machine *mach,
3636 const struct tgsi_full_instruction *inst,
3637 micro_dop op)
3638 {
3639 union tgsi_double_channel src[3];
3640 union tgsi_double_channel dst;
3641
3642 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3643 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3644 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, TGSI_CHAN_Y);
3645 fetch_double_channel(mach, &src[2], &inst->Src[2], TGSI_CHAN_X, TGSI_CHAN_Y);
3646 op(&dst, src);
3647 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3648 }
3649 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3650 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3651 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_CHAN_W);
3652 fetch_double_channel(mach, &src[2], &inst->Src[2], TGSI_CHAN_Z, TGSI_CHAN_W);
3653 op(&dst, src);
3654 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3655 }
3656 }
3657
3658 static void
3659 exec_dldexp(struct tgsi_exec_machine *mach,
3660 const struct tgsi_full_instruction *inst)
3661 {
3662 union tgsi_double_channel src0;
3663 union tgsi_exec_channel src1;
3664 union tgsi_double_channel dst;
3665 int wmask;
3666
3667 wmask = inst->Dst[0].Register.WriteMask;
3668 if (wmask & TGSI_WRITEMASK_XY) {
3669 fetch_double_channel(mach, &src0, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3670 fetch_source(mach, &src1, &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
3671 micro_dldexp(&dst, &src0, &src1);
3672 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3673 }
3674
3675 if (wmask & TGSI_WRITEMASK_ZW) {
3676 fetch_double_channel(mach, &src0, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3677 fetch_source(mach, &src1, &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_INT);
3678 micro_dldexp(&dst, &src0, &src1);
3679 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3680 }
3681 }
3682
3683 static void
3684 exec_dfracexp(struct tgsi_exec_machine *mach,
3685 const struct tgsi_full_instruction *inst)
3686 {
3687 union tgsi_double_channel src;
3688 union tgsi_double_channel dst;
3689 union tgsi_exec_channel dst_exp;
3690
3691 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3692 micro_dfracexp(&dst, &dst_exp, &src);
3693 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY)
3694 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3695 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW)
3696 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3697 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3698 if (inst->Dst[1].Register.WriteMask & (1 << chan))
3699 store_dest(mach, &dst_exp, &inst->Dst[1], inst, chan, TGSI_EXEC_DATA_INT);
3700 }
3701 }
3702
3703 static void
3704 exec_arg0_64_arg1_32(struct tgsi_exec_machine *mach,
3705 const struct tgsi_full_instruction *inst,
3706 micro_dop_sop op)
3707 {
3708 union tgsi_double_channel src0;
3709 union tgsi_exec_channel src1;
3710 union tgsi_double_channel dst;
3711 int wmask;
3712
3713 wmask = inst->Dst[0].Register.WriteMask;
3714 if (wmask & TGSI_WRITEMASK_XY) {
3715 fetch_double_channel(mach, &src0, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3716 fetch_source(mach, &src1, &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
3717 op(&dst, &src0, &src1);
3718 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3719 }
3720
3721 if (wmask & TGSI_WRITEMASK_ZW) {
3722 fetch_double_channel(mach, &src0, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3723 fetch_source(mach, &src1, &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_INT);
3724 op(&dst, &src0, &src1);
3725 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3726 }
3727 }
3728
3729 static int
3730 get_image_coord_dim(unsigned tgsi_tex)
3731 {
3732 int dim;
3733 switch (tgsi_tex) {
3734 case TGSI_TEXTURE_BUFFER:
3735 case TGSI_TEXTURE_1D:
3736 dim = 1;
3737 break;
3738 case TGSI_TEXTURE_2D:
3739 case TGSI_TEXTURE_RECT:
3740 case TGSI_TEXTURE_1D_ARRAY:
3741 case TGSI_TEXTURE_2D_MSAA:
3742 dim = 2;
3743 break;
3744 case TGSI_TEXTURE_3D:
3745 case TGSI_TEXTURE_CUBE:
3746 case TGSI_TEXTURE_2D_ARRAY:
3747 case TGSI_TEXTURE_2D_ARRAY_MSAA:
3748 case TGSI_TEXTURE_CUBE_ARRAY:
3749 dim = 3;
3750 break;
3751 default:
3752 assert(!"unknown texture target");
3753 dim = 0;
3754 break;
3755 }
3756
3757 return dim;
3758 }
3759
3760 static int
3761 get_image_coord_sample(unsigned tgsi_tex)
3762 {
3763 int sample = 0;
3764 switch (tgsi_tex) {
3765 case TGSI_TEXTURE_2D_MSAA:
3766 sample = 3;
3767 break;
3768 case TGSI_TEXTURE_2D_ARRAY_MSAA:
3769 sample = 4;
3770 break;
3771 default:
3772 break;
3773 }
3774 return sample;
3775 }
3776
3777 static void
3778 exec_load_img(struct tgsi_exec_machine *mach,
3779 const struct tgsi_full_instruction *inst)
3780 {
3781 union tgsi_exec_channel r[4], sample_r;
3782 uint unit;
3783 int sample;
3784 int i, j;
3785 int dim;
3786 uint chan;
3787 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
3788 struct tgsi_image_params params;
3789 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3790
3791 unit = fetch_sampler_unit(mach, inst, 0);
3792 dim = get_image_coord_dim(inst->Memory.Texture);
3793 sample = get_image_coord_sample(inst->Memory.Texture);
3794 assert(dim <= 3);
3795
3796 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3797 params.unit = unit;
3798 params.tgsi_tex_instr = inst->Memory.Texture;
3799 params.format = inst->Memory.Format;
3800
3801 for (i = 0; i < dim; i++) {
3802 IFETCH(&r[i], 1, TGSI_CHAN_X + i);
3803 }
3804
3805 if (sample)
3806 IFETCH(&sample_r, 1, TGSI_CHAN_X + sample);
3807
3808 mach->Image->load(mach->Image, &params,
3809 r[0].i, r[1].i, r[2].i, sample_r.i,
3810 rgba);
3811 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3812 r[0].f[j] = rgba[0][j];
3813 r[1].f[j] = rgba[1][j];
3814 r[2].f[j] = rgba[2][j];
3815 r[3].f[j] = rgba[3][j];
3816 }
3817 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3818 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3819 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3820 }
3821 }
3822 }
3823
3824 static void
3825 exec_load_buf(struct tgsi_exec_machine *mach,
3826 const struct tgsi_full_instruction *inst)
3827 {
3828 union tgsi_exec_channel r[4];
3829 uint unit;
3830 int j;
3831 uint chan;
3832 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
3833 struct tgsi_buffer_params params;
3834 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3835
3836 unit = fetch_sampler_unit(mach, inst, 0);
3837
3838 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3839 params.unit = unit;
3840 IFETCH(&r[0], 1, TGSI_CHAN_X);
3841
3842 mach->Buffer->load(mach->Buffer, &params,
3843 r[0].i, rgba);
3844 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3845 r[0].f[j] = rgba[0][j];
3846 r[1].f[j] = rgba[1][j];
3847 r[2].f[j] = rgba[2][j];
3848 r[3].f[j] = rgba[3][j];
3849 }
3850 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3851 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3852 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3853 }
3854 }
3855 }
3856
3857 static void
3858 exec_load_mem(struct tgsi_exec_machine *mach,
3859 const struct tgsi_full_instruction *inst)
3860 {
3861 union tgsi_exec_channel r[4];
3862 uint chan;
3863 char *ptr = mach->LocalMem;
3864 uint32_t offset;
3865 int j;
3866
3867 IFETCH(&r[0], 1, TGSI_CHAN_X);
3868 if (r[0].u[0] >= mach->LocalMemSize)
3869 return;
3870
3871 offset = r[0].u[0];
3872 ptr += offset;
3873
3874 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3875 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3876 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3877 memcpy(&r[chan].u[j], ptr + (4 * chan), 4);
3878 }
3879 }
3880 }
3881
3882 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3883 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3884 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3885 }
3886 }
3887 }
3888
3889 static void
3890 exec_load(struct tgsi_exec_machine *mach,
3891 const struct tgsi_full_instruction *inst)
3892 {
3893 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
3894 exec_load_img(mach, inst);
3895 else if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
3896 exec_load_buf(mach, inst);
3897 else if (inst->Src[0].Register.File == TGSI_FILE_MEMORY)
3898 exec_load_mem(mach, inst);
3899 }
3900
3901 static void
3902 exec_store_img(struct tgsi_exec_machine *mach,
3903 const struct tgsi_full_instruction *inst)
3904 {
3905 union tgsi_exec_channel r[3], sample_r;
3906 union tgsi_exec_channel value[4];
3907 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
3908 struct tgsi_image_params params;
3909 int dim;
3910 int sample;
3911 int i, j;
3912 uint unit;
3913 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3914 unit = inst->Dst[0].Register.Index;
3915 dim = get_image_coord_dim(inst->Memory.Texture);
3916 sample = get_image_coord_sample(inst->Memory.Texture);
3917 assert(dim <= 3);
3918
3919 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3920 params.unit = unit;
3921 params.tgsi_tex_instr = inst->Memory.Texture;
3922 params.format = inst->Memory.Format;
3923
3924 for (i = 0; i < dim; i++) {
3925 IFETCH(&r[i], 0, TGSI_CHAN_X + i);
3926 }
3927
3928 for (i = 0; i < 4; i++) {
3929 FETCH(&value[i], 1, TGSI_CHAN_X + i);
3930 }
3931 if (sample)
3932 IFETCH(&sample_r, 0, TGSI_CHAN_X + sample);
3933
3934 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3935 rgba[0][j] = value[0].f[j];
3936 rgba[1][j] = value[1].f[j];
3937 rgba[2][j] = value[2].f[j];
3938 rgba[3][j] = value[3].f[j];
3939 }
3940
3941 mach->Image->store(mach->Image, &params,
3942 r[0].i, r[1].i, r[2].i, sample_r.i,
3943 rgba);
3944 }
3945
3946 static void
3947 exec_store_buf(struct tgsi_exec_machine *mach,
3948 const struct tgsi_full_instruction *inst)
3949 {
3950 union tgsi_exec_channel r[3];
3951 union tgsi_exec_channel value[4];
3952 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
3953 struct tgsi_buffer_params params;
3954 int i, j;
3955 uint unit;
3956 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3957
3958 unit = inst->Dst[0].Register.Index;
3959
3960 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3961 params.unit = unit;
3962 params.writemask = inst->Dst[0].Register.WriteMask;
3963
3964 IFETCH(&r[0], 0, TGSI_CHAN_X);
3965 for (i = 0; i < 4; i++) {
3966 FETCH(&value[i], 1, TGSI_CHAN_X + i);
3967 }
3968
3969 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3970 rgba[0][j] = value[0].f[j];
3971 rgba[1][j] = value[1].f[j];
3972 rgba[2][j] = value[2].f[j];
3973 rgba[3][j] = value[3].f[j];
3974 }
3975
3976 mach->Buffer->store(mach->Buffer, &params,
3977 r[0].i,
3978 rgba);
3979 }
3980
3981 static void
3982 exec_store_mem(struct tgsi_exec_machine *mach,
3983 const struct tgsi_full_instruction *inst)
3984 {
3985 union tgsi_exec_channel r[3];
3986 union tgsi_exec_channel value[4];
3987 uint i, chan;
3988 char *ptr = mach->LocalMem;
3989 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3990 int execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3991
3992 IFETCH(&r[0], 0, TGSI_CHAN_X);
3993
3994 for (i = 0; i < 4; i++) {
3995 FETCH(&value[i], 1, TGSI_CHAN_X + i);
3996 }
3997
3998 if (r[0].u[0] >= mach->LocalMemSize)
3999 return;
4000 ptr += r[0].u[0];
4001
4002 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
4003 if (execmask & (1 << i)) {
4004 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4005 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4006 memcpy(ptr + (chan * 4), &value[chan].u[0], 4);
4007 }
4008 }
4009 }
4010 }
4011 }
4012
4013 static void
4014 exec_store(struct tgsi_exec_machine *mach,
4015 const struct tgsi_full_instruction *inst)
4016 {
4017 if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE)
4018 exec_store_img(mach, inst);
4019 else if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER)
4020 exec_store_buf(mach, inst);
4021 else if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY)
4022 exec_store_mem(mach, inst);
4023 }
4024
4025 static void
4026 exec_atomop_img(struct tgsi_exec_machine *mach,
4027 const struct tgsi_full_instruction *inst)
4028 {
4029 union tgsi_exec_channel r[4], sample_r;
4030 union tgsi_exec_channel value[4], value2[4];
4031 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
4032 float rgba2[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
4033 struct tgsi_image_params params;
4034 int dim;
4035 int sample;
4036 int i, j;
4037 uint unit, chan;
4038 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4039 unit = fetch_sampler_unit(mach, inst, 0);
4040 dim = get_image_coord_dim(inst->Memory.Texture);
4041 sample = get_image_coord_sample(inst->Memory.Texture);
4042 assert(dim <= 3);
4043
4044 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4045 params.unit = unit;
4046 params.tgsi_tex_instr = inst->Memory.Texture;
4047 params.format = inst->Memory.Format;
4048
4049 for (i = 0; i < dim; i++) {
4050 IFETCH(&r[i], 1, TGSI_CHAN_X + i);
4051 }
4052
4053 for (i = 0; i < 4; i++) {
4054 FETCH(&value[i], 2, TGSI_CHAN_X + i);
4055 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4056 FETCH(&value2[i], 3, TGSI_CHAN_X + i);
4057 }
4058 if (sample)
4059 IFETCH(&sample_r, 1, TGSI_CHAN_X + sample);
4060
4061 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4062 rgba[0][j] = value[0].f[j];
4063 rgba[1][j] = value[1].f[j];
4064 rgba[2][j] = value[2].f[j];
4065 rgba[3][j] = value[3].f[j];
4066 }
4067 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
4068 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4069 rgba2[0][j] = value2[0].f[j];
4070 rgba2[1][j] = value2[1].f[j];
4071 rgba2[2][j] = value2[2].f[j];
4072 rgba2[3][j] = value2[3].f[j];
4073 }
4074 }
4075
4076 mach->Image->op(mach->Image, &params, inst->Instruction.Opcode,
4077 r[0].i, r[1].i, r[2].i, sample_r.i,
4078 rgba, rgba2);
4079
4080 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4081 r[0].f[j] = rgba[0][j];
4082 r[1].f[j] = rgba[1][j];
4083 r[2].f[j] = rgba[2][j];
4084 r[3].f[j] = rgba[3][j];
4085 }
4086 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4087 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4088 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
4089 }
4090 }
4091 }
4092
4093 static void
4094 exec_atomop_buf(struct tgsi_exec_machine *mach,
4095 const struct tgsi_full_instruction *inst)
4096 {
4097 union tgsi_exec_channel r[4];
4098 union tgsi_exec_channel value[4], value2[4];
4099 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
4100 float rgba2[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
4101 struct tgsi_buffer_params params;
4102 int i, j;
4103 uint unit, chan;
4104 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4105
4106 unit = fetch_sampler_unit(mach, inst, 0);
4107
4108 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4109 params.unit = unit;
4110 params.writemask = inst->Dst[0].Register.WriteMask;
4111
4112 IFETCH(&r[0], 1, TGSI_CHAN_X);
4113
4114 for (i = 0; i < 4; i++) {
4115 FETCH(&value[i], 2, TGSI_CHAN_X + i);
4116 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4117 FETCH(&value2[i], 3, TGSI_CHAN_X + i);
4118 }
4119
4120 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4121 rgba[0][j] = value[0].f[j];
4122 rgba[1][j] = value[1].f[j];
4123 rgba[2][j] = value[2].f[j];
4124 rgba[3][j] = value[3].f[j];
4125 }
4126 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
4127 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4128 rgba2[0][j] = value2[0].f[j];
4129 rgba2[1][j] = value2[1].f[j];
4130 rgba2[2][j] = value2[2].f[j];
4131 rgba2[3][j] = value2[3].f[j];
4132 }
4133 }
4134
4135 mach->Buffer->op(mach->Buffer, &params, inst->Instruction.Opcode,
4136 r[0].i,
4137 rgba, rgba2);
4138
4139 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4140 r[0].f[j] = rgba[0][j];
4141 r[1].f[j] = rgba[1][j];
4142 r[2].f[j] = rgba[2][j];
4143 r[3].f[j] = rgba[3][j];
4144 }
4145 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4146 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4147 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
4148 }
4149 }
4150 }
4151
4152 static void
4153 exec_atomop_mem(struct tgsi_exec_machine *mach,
4154 const struct tgsi_full_instruction *inst)
4155 {
4156 union tgsi_exec_channel r[4];
4157 union tgsi_exec_channel value[4], value2[4];
4158 char *ptr = mach->LocalMem;
4159 uint32_t val;
4160 uint chan, i;
4161 uint32_t offset;
4162 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4163 int execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4164 IFETCH(&r[0], 1, TGSI_CHAN_X);
4165
4166 if (r[0].u[0] >= mach->LocalMemSize)
4167 return;
4168
4169 offset = r[0].u[0];
4170 ptr += offset;
4171 for (i = 0; i < 4; i++) {
4172 FETCH(&value[i], 2, TGSI_CHAN_X + i);
4173 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4174 FETCH(&value2[i], 3, TGSI_CHAN_X + i);
4175 }
4176
4177 memcpy(&r[0].u[0], ptr, 4);
4178 val = r[0].u[0];
4179 switch (inst->Instruction.Opcode) {
4180 case TGSI_OPCODE_ATOMUADD:
4181 val += value[0].u[0];
4182 break;
4183 case TGSI_OPCODE_ATOMXOR:
4184 val ^= value[0].u[0];
4185 break;
4186 case TGSI_OPCODE_ATOMOR:
4187 val |= value[0].u[0];
4188 break;
4189 case TGSI_OPCODE_ATOMAND:
4190 val &= value[0].u[0];
4191 break;
4192 case TGSI_OPCODE_ATOMUMIN:
4193 val = MIN2(val, value[0].u[0]);
4194 break;
4195 case TGSI_OPCODE_ATOMUMAX:
4196 val = MAX2(val, value[0].u[0]);
4197 break;
4198 case TGSI_OPCODE_ATOMIMIN:
4199 val = MIN2(r[0].i[0], value[0].i[0]);
4200 break;
4201 case TGSI_OPCODE_ATOMIMAX:
4202 val = MAX2(r[0].i[0], value[0].i[0]);
4203 break;
4204 case TGSI_OPCODE_ATOMXCHG:
4205 val = value[0].i[0];
4206 break;
4207 case TGSI_OPCODE_ATOMCAS:
4208 if (val == value[0].u[0])
4209 val = value2[0].u[0];
4210 break;
4211 default:
4212 break;
4213 }
4214 for (i = 0; i < TGSI_QUAD_SIZE; i++)
4215 if (execmask & (1 << i))
4216 memcpy(ptr, &val, 4);
4217
4218 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4219 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4220 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
4221 }
4222 }
4223 }
4224
4225 static void
4226 exec_atomop(struct tgsi_exec_machine *mach,
4227 const struct tgsi_full_instruction *inst)
4228 {
4229 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
4230 exec_atomop_img(mach, inst);
4231 else if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
4232 exec_atomop_buf(mach, inst);
4233 else if (inst->Src[0].Register.File == TGSI_FILE_MEMORY)
4234 exec_atomop_mem(mach, inst);
4235 }
4236
4237 static void
4238 exec_resq_img(struct tgsi_exec_machine *mach,
4239 const struct tgsi_full_instruction *inst)
4240 {
4241 int result[4];
4242 union tgsi_exec_channel r[4];
4243 uint unit;
4244 int i, chan, j;
4245 struct tgsi_image_params params;
4246 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4247
4248 unit = fetch_sampler_unit(mach, inst, 0);
4249
4250 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4251 params.unit = unit;
4252 params.tgsi_tex_instr = inst->Memory.Texture;
4253 params.format = inst->Memory.Format;
4254
4255 mach->Image->get_dims(mach->Image, &params, result);
4256
4257 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
4258 for (j = 0; j < 4; j++) {
4259 r[j].i[i] = result[j];
4260 }
4261 }
4262
4263 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4264 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4265 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
4266 TGSI_EXEC_DATA_INT);
4267 }
4268 }
4269 }
4270
4271 static void
4272 exec_resq_buf(struct tgsi_exec_machine *mach,
4273 const struct tgsi_full_instruction *inst)
4274 {
4275 int result;
4276 union tgsi_exec_channel r[4];
4277 uint unit;
4278 int i, chan;
4279 struct tgsi_buffer_params params;
4280 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4281
4282 unit = fetch_sampler_unit(mach, inst, 0);
4283
4284 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4285 params.unit = unit;
4286
4287 mach->Buffer->get_dims(mach->Buffer, &params, &result);
4288
4289 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
4290 r[0].i[i] = result;
4291 }
4292
4293 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4294 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4295 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
4296 TGSI_EXEC_DATA_INT);
4297 }
4298 }
4299 }
4300
4301 static void
4302 exec_resq(struct tgsi_exec_machine *mach,
4303 const struct tgsi_full_instruction *inst)
4304 {
4305 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
4306 exec_resq_img(mach, inst);
4307 else
4308 exec_resq_buf(mach, inst);
4309 }
4310
4311 static void
4312 micro_f2u64(union tgsi_double_channel *dst,
4313 const union tgsi_exec_channel *src)
4314 {
4315 dst->u64[0] = (uint64_t)src->f[0];
4316 dst->u64[1] = (uint64_t)src->f[1];
4317 dst->u64[2] = (uint64_t)src->f[2];
4318 dst->u64[3] = (uint64_t)src->f[3];
4319 }
4320
4321 static void
4322 micro_f2i64(union tgsi_double_channel *dst,
4323 const union tgsi_exec_channel *src)
4324 {
4325 dst->i64[0] = (int64_t)src->f[0];
4326 dst->i64[1] = (int64_t)src->f[1];
4327 dst->i64[2] = (int64_t)src->f[2];
4328 dst->i64[3] = (int64_t)src->f[3];
4329 }
4330
4331 static void
4332 micro_u2i64(union tgsi_double_channel *dst,
4333 const union tgsi_exec_channel *src)
4334 {
4335 dst->u64[0] = (uint64_t)src->u[0];
4336 dst->u64[1] = (uint64_t)src->u[1];
4337 dst->u64[2] = (uint64_t)src->u[2];
4338 dst->u64[3] = (uint64_t)src->u[3];
4339 }
4340
4341 static void
4342 micro_i2i64(union tgsi_double_channel *dst,
4343 const union tgsi_exec_channel *src)
4344 {
4345 dst->i64[0] = (int64_t)src->i[0];
4346 dst->i64[1] = (int64_t)src->i[1];
4347 dst->i64[2] = (int64_t)src->i[2];
4348 dst->i64[3] = (int64_t)src->i[3];
4349 }
4350
4351 static void
4352 micro_d2u64(union tgsi_double_channel *dst,
4353 const union tgsi_double_channel *src)
4354 {
4355 dst->u64[0] = (uint64_t)src->d[0];
4356 dst->u64[1] = (uint64_t)src->d[1];
4357 dst->u64[2] = (uint64_t)src->d[2];
4358 dst->u64[3] = (uint64_t)src->d[3];
4359 }
4360
4361 static void
4362 micro_d2i64(union tgsi_double_channel *dst,
4363 const union tgsi_double_channel *src)
4364 {
4365 dst->i64[0] = (int64_t)src->d[0];
4366 dst->i64[1] = (int64_t)src->d[1];
4367 dst->i64[2] = (int64_t)src->d[2];
4368 dst->i64[3] = (int64_t)src->d[3];
4369 }
4370
4371 static void
4372 micro_u642d(union tgsi_double_channel *dst,
4373 const union tgsi_double_channel *src)
4374 {
4375 dst->d[0] = (double)src->u64[0];
4376 dst->d[1] = (double)src->u64[1];
4377 dst->d[2] = (double)src->u64[2];
4378 dst->d[3] = (double)src->u64[3];
4379 }
4380
4381 static void
4382 micro_i642d(union tgsi_double_channel *dst,
4383 const union tgsi_double_channel *src)
4384 {
4385 dst->d[0] = (double)src->i64[0];
4386 dst->d[1] = (double)src->i64[1];
4387 dst->d[2] = (double)src->i64[2];
4388 dst->d[3] = (double)src->i64[3];
4389 }
4390
4391 static void
4392 micro_u642f(union tgsi_exec_channel *dst,
4393 const union tgsi_double_channel *src)
4394 {
4395 dst->f[0] = (float)src->u64[0];
4396 dst->f[1] = (float)src->u64[1];
4397 dst->f[2] = (float)src->u64[2];
4398 dst->f[3] = (float)src->u64[3];
4399 }
4400
4401 static void
4402 micro_i642f(union tgsi_exec_channel *dst,
4403 const union tgsi_double_channel *src)
4404 {
4405 dst->f[0] = (float)src->i64[0];
4406 dst->f[1] = (float)src->i64[1];
4407 dst->f[2] = (float)src->i64[2];
4408 dst->f[3] = (float)src->i64[3];
4409 }
4410
4411 static void
4412 exec_t_2_64(struct tgsi_exec_machine *mach,
4413 const struct tgsi_full_instruction *inst,
4414 micro_dop_s op,
4415 enum tgsi_exec_datatype src_datatype)
4416 {
4417 union tgsi_exec_channel src;
4418 union tgsi_double_channel dst;
4419
4420 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
4421 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, src_datatype);
4422 op(&dst, &src);
4423 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
4424 }
4425 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
4426 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_Y, src_datatype);
4427 op(&dst, &src);
4428 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
4429 }
4430 }
4431
4432 static void
4433 exec_64_2_t(struct tgsi_exec_machine *mach,
4434 const struct tgsi_full_instruction *inst,
4435 micro_sop_d op,
4436 enum tgsi_exec_datatype dst_datatype)
4437 {
4438 union tgsi_double_channel src;
4439 union tgsi_exec_channel dst;
4440 int wm = inst->Dst[0].Register.WriteMask;
4441 int i;
4442 int bit;
4443 for (i = 0; i < 2; i++) {
4444 bit = ffs(wm);
4445 if (bit) {
4446 wm &= ~(1 << (bit - 1));
4447 if (i == 0)
4448 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
4449 else
4450 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
4451 op(&dst, &src);
4452 store_dest(mach, &dst, &inst->Dst[0], inst, bit - 1, dst_datatype);
4453 }
4454 }
4455 }
4456
4457 static void
4458 micro_i2f(union tgsi_exec_channel *dst,
4459 const union tgsi_exec_channel *src)
4460 {
4461 dst->f[0] = (float)src->i[0];
4462 dst->f[1] = (float)src->i[1];
4463 dst->f[2] = (float)src->i[2];
4464 dst->f[3] = (float)src->i[3];
4465 }
4466
4467 static void
4468 micro_not(union tgsi_exec_channel *dst,
4469 const union tgsi_exec_channel *src)
4470 {
4471 dst->u[0] = ~src->u[0];
4472 dst->u[1] = ~src->u[1];
4473 dst->u[2] = ~src->u[2];
4474 dst->u[3] = ~src->u[3];
4475 }
4476
4477 static void
4478 micro_shl(union tgsi_exec_channel *dst,
4479 const union tgsi_exec_channel *src0,
4480 const union tgsi_exec_channel *src1)
4481 {
4482 unsigned masked_count;
4483 masked_count = src1->u[0] & 0x1f;
4484 dst->u[0] = src0->u[0] << masked_count;
4485 masked_count = src1->u[1] & 0x1f;
4486 dst->u[1] = src0->u[1] << masked_count;
4487 masked_count = src1->u[2] & 0x1f;
4488 dst->u[2] = src0->u[2] << masked_count;
4489 masked_count = src1->u[3] & 0x1f;
4490 dst->u[3] = src0->u[3] << masked_count;
4491 }
4492
4493 static void
4494 micro_and(union tgsi_exec_channel *dst,
4495 const union tgsi_exec_channel *src0,
4496 const union tgsi_exec_channel *src1)
4497 {
4498 dst->u[0] = src0->u[0] & src1->u[0];
4499 dst->u[1] = src0->u[1] & src1->u[1];
4500 dst->u[2] = src0->u[2] & src1->u[2];
4501 dst->u[3] = src0->u[3] & src1->u[3];
4502 }
4503
4504 static void
4505 micro_or(union tgsi_exec_channel *dst,
4506 const union tgsi_exec_channel *src0,
4507 const union tgsi_exec_channel *src1)
4508 {
4509 dst->u[0] = src0->u[0] | src1->u[0];
4510 dst->u[1] = src0->u[1] | src1->u[1];
4511 dst->u[2] = src0->u[2] | src1->u[2];
4512 dst->u[3] = src0->u[3] | src1->u[3];
4513 }
4514
4515 static void
4516 micro_xor(union tgsi_exec_channel *dst,
4517 const union tgsi_exec_channel *src0,
4518 const union tgsi_exec_channel *src1)
4519 {
4520 dst->u[0] = src0->u[0] ^ src1->u[0];
4521 dst->u[1] = src0->u[1] ^ src1->u[1];
4522 dst->u[2] = src0->u[2] ^ src1->u[2];
4523 dst->u[3] = src0->u[3] ^ src1->u[3];
4524 }
4525
4526 static void
4527 micro_mod(union tgsi_exec_channel *dst,
4528 const union tgsi_exec_channel *src0,
4529 const union tgsi_exec_channel *src1)
4530 {
4531 dst->i[0] = src1->i[0] ? src0->i[0] % src1->i[0] : ~0;
4532 dst->i[1] = src1->i[1] ? src0->i[1] % src1->i[1] : ~0;
4533 dst->i[2] = src1->i[2] ? src0->i[2] % src1->i[2] : ~0;
4534 dst->i[3] = src1->i[3] ? src0->i[3] % src1->i[3] : ~0;
4535 }
4536
4537 static void
4538 micro_f2i(union tgsi_exec_channel *dst,
4539 const union tgsi_exec_channel *src)
4540 {
4541 dst->i[0] = (int)src->f[0];
4542 dst->i[1] = (int)src->f[1];
4543 dst->i[2] = (int)src->f[2];
4544 dst->i[3] = (int)src->f[3];
4545 }
4546
4547 static void
4548 micro_fseq(union tgsi_exec_channel *dst,
4549 const union tgsi_exec_channel *src0,
4550 const union tgsi_exec_channel *src1)
4551 {
4552 dst->u[0] = src0->f[0] == src1->f[0] ? ~0 : 0;
4553 dst->u[1] = src0->f[1] == src1->f[1] ? ~0 : 0;
4554 dst->u[2] = src0->f[2] == src1->f[2] ? ~0 : 0;
4555 dst->u[3] = src0->f[3] == src1->f[3] ? ~0 : 0;
4556 }
4557
4558 static void
4559 micro_fsge(union tgsi_exec_channel *dst,
4560 const union tgsi_exec_channel *src0,
4561 const union tgsi_exec_channel *src1)
4562 {
4563 dst->u[0] = src0->f[0] >= src1->f[0] ? ~0 : 0;
4564 dst->u[1] = src0->f[1] >= src1->f[1] ? ~0 : 0;
4565 dst->u[2] = src0->f[2] >= src1->f[2] ? ~0 : 0;
4566 dst->u[3] = src0->f[3] >= src1->f[3] ? ~0 : 0;
4567 }
4568
4569 static void
4570 micro_fslt(union tgsi_exec_channel *dst,
4571 const union tgsi_exec_channel *src0,
4572 const union tgsi_exec_channel *src1)
4573 {
4574 dst->u[0] = src0->f[0] < src1->f[0] ? ~0 : 0;
4575 dst->u[1] = src0->f[1] < src1->f[1] ? ~0 : 0;
4576 dst->u[2] = src0->f[2] < src1->f[2] ? ~0 : 0;
4577 dst->u[3] = src0->f[3] < src1->f[3] ? ~0 : 0;
4578 }
4579
4580 static void
4581 micro_fsne(union tgsi_exec_channel *dst,
4582 const union tgsi_exec_channel *src0,
4583 const union tgsi_exec_channel *src1)
4584 {
4585 dst->u[0] = src0->f[0] != src1->f[0] ? ~0 : 0;
4586 dst->u[1] = src0->f[1] != src1->f[1] ? ~0 : 0;
4587 dst->u[2] = src0->f[2] != src1->f[2] ? ~0 : 0;
4588 dst->u[3] = src0->f[3] != src1->f[3] ? ~0 : 0;
4589 }
4590
4591 static void
4592 micro_idiv(union tgsi_exec_channel *dst,
4593 const union tgsi_exec_channel *src0,
4594 const union tgsi_exec_channel *src1)
4595 {
4596 dst->i[0] = src1->i[0] ? src0->i[0] / src1->i[0] : 0;
4597 dst->i[1] = src1->i[1] ? src0->i[1] / src1->i[1] : 0;
4598 dst->i[2] = src1->i[2] ? src0->i[2] / src1->i[2] : 0;
4599 dst->i[3] = src1->i[3] ? src0->i[3] / src1->i[3] : 0;
4600 }
4601
4602 static void
4603 micro_imax(union tgsi_exec_channel *dst,
4604 const union tgsi_exec_channel *src0,
4605 const union tgsi_exec_channel *src1)
4606 {
4607 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
4608 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
4609 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
4610 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
4611 }
4612
4613 static void
4614 micro_imin(union tgsi_exec_channel *dst,
4615 const union tgsi_exec_channel *src0,
4616 const union tgsi_exec_channel *src1)
4617 {
4618 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
4619 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
4620 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
4621 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
4622 }
4623
4624 static void
4625 micro_isge(union tgsi_exec_channel *dst,
4626 const union tgsi_exec_channel *src0,
4627 const union tgsi_exec_channel *src1)
4628 {
4629 dst->i[0] = src0->i[0] >= src1->i[0] ? -1 : 0;
4630 dst->i[1] = src0->i[1] >= src1->i[1] ? -1 : 0;
4631 dst->i[2] = src0->i[2] >= src1->i[2] ? -1 : 0;
4632 dst->i[3] = src0->i[3] >= src1->i[3] ? -1 : 0;
4633 }
4634
4635 static void
4636 micro_ishr(union tgsi_exec_channel *dst,
4637 const union tgsi_exec_channel *src0,
4638 const union tgsi_exec_channel *src1)
4639 {
4640 unsigned masked_count;
4641 masked_count = src1->i[0] & 0x1f;
4642 dst->i[0] = src0->i[0] >> masked_count;
4643 masked_count = src1->i[1] & 0x1f;
4644 dst->i[1] = src0->i[1] >> masked_count;
4645 masked_count = src1->i[2] & 0x1f;
4646 dst->i[2] = src0->i[2] >> masked_count;
4647 masked_count = src1->i[3] & 0x1f;
4648 dst->i[3] = src0->i[3] >> masked_count;
4649 }
4650
4651 static void
4652 micro_islt(union tgsi_exec_channel *dst,
4653 const union tgsi_exec_channel *src0,
4654 const union tgsi_exec_channel *src1)
4655 {
4656 dst->i[0] = src0->i[0] < src1->i[0] ? -1 : 0;
4657 dst->i[1] = src0->i[1] < src1->i[1] ? -1 : 0;
4658 dst->i[2] = src0->i[2] < src1->i[2] ? -1 : 0;
4659 dst->i[3] = src0->i[3] < src1->i[3] ? -1 : 0;
4660 }
4661
4662 static void
4663 micro_f2u(union tgsi_exec_channel *dst,
4664 const union tgsi_exec_channel *src)
4665 {
4666 dst->u[0] = (uint)src->f[0];
4667 dst->u[1] = (uint)src->f[1];
4668 dst->u[2] = (uint)src->f[2];
4669 dst->u[3] = (uint)src->f[3];
4670 }
4671
4672 static void
4673 micro_u2f(union tgsi_exec_channel *dst,
4674 const union tgsi_exec_channel *src)
4675 {
4676 dst->f[0] = (float)src->u[0];
4677 dst->f[1] = (float)src->u[1];
4678 dst->f[2] = (float)src->u[2];
4679 dst->f[3] = (float)src->u[3];
4680 }
4681
4682 static void
4683 micro_uadd(union tgsi_exec_channel *dst,
4684 const union tgsi_exec_channel *src0,
4685 const union tgsi_exec_channel *src1)
4686 {
4687 dst->u[0] = src0->u[0] + src1->u[0];
4688 dst->u[1] = src0->u[1] + src1->u[1];
4689 dst->u[2] = src0->u[2] + src1->u[2];
4690 dst->u[3] = src0->u[3] + src1->u[3];
4691 }
4692
4693 static void
4694 micro_udiv(union tgsi_exec_channel *dst,
4695 const union tgsi_exec_channel *src0,
4696 const union tgsi_exec_channel *src1)
4697 {
4698 dst->u[0] = src1->u[0] ? src0->u[0] / src1->u[0] : ~0u;
4699 dst->u[1] = src1->u[1] ? src0->u[1] / src1->u[1] : ~0u;
4700 dst->u[2] = src1->u[2] ? src0->u[2] / src1->u[2] : ~0u;
4701 dst->u[3] = src1->u[3] ? src0->u[3] / src1->u[3] : ~0u;
4702 }
4703
4704 static void
4705 micro_umad(union tgsi_exec_channel *dst,
4706 const union tgsi_exec_channel *src0,
4707 const union tgsi_exec_channel *src1,
4708 const union tgsi_exec_channel *src2)
4709 {
4710 dst->u[0] = src0->u[0] * src1->u[0] + src2->u[0];
4711 dst->u[1] = src0->u[1] * src1->u[1] + src2->u[1];
4712 dst->u[2] = src0->u[2] * src1->u[2] + src2->u[2];
4713 dst->u[3] = src0->u[3] * src1->u[3] + src2->u[3];
4714 }
4715
4716 static void
4717 micro_umax(union tgsi_exec_channel *dst,
4718 const union tgsi_exec_channel *src0,
4719 const union tgsi_exec_channel *src1)
4720 {
4721 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
4722 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
4723 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
4724 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
4725 }
4726
4727 static void
4728 micro_umin(union tgsi_exec_channel *dst,
4729 const union tgsi_exec_channel *src0,
4730 const union tgsi_exec_channel *src1)
4731 {
4732 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
4733 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
4734 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
4735 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
4736 }
4737
4738 static void
4739 micro_umod(union tgsi_exec_channel *dst,
4740 const union tgsi_exec_channel *src0,
4741 const union tgsi_exec_channel *src1)
4742 {
4743 dst->u[0] = src1->u[0] ? src0->u[0] % src1->u[0] : ~0u;
4744 dst->u[1] = src1->u[1] ? src0->u[1] % src1->u[1] : ~0u;
4745 dst->u[2] = src1->u[2] ? src0->u[2] % src1->u[2] : ~0u;
4746 dst->u[3] = src1->u[3] ? src0->u[3] % src1->u[3] : ~0u;
4747 }
4748
4749 static void
4750 micro_umul(union tgsi_exec_channel *dst,
4751 const union tgsi_exec_channel *src0,
4752 const union tgsi_exec_channel *src1)
4753 {
4754 dst->u[0] = src0->u[0] * src1->u[0];
4755 dst->u[1] = src0->u[1] * src1->u[1];
4756 dst->u[2] = src0->u[2] * src1->u[2];
4757 dst->u[3] = src0->u[3] * src1->u[3];
4758 }
4759
4760 static void
4761 micro_imul_hi(union tgsi_exec_channel *dst,
4762 const union tgsi_exec_channel *src0,
4763 const union tgsi_exec_channel *src1)
4764 {
4765 #define I64M(x, y) ((((int64_t)x) * ((int64_t)y)) >> 32)
4766 dst->i[0] = I64M(src0->i[0], src1->i[0]);
4767 dst->i[1] = I64M(src0->i[1], src1->i[1]);
4768 dst->i[2] = I64M(src0->i[2], src1->i[2]);
4769 dst->i[3] = I64M(src0->i[3], src1->i[3]);
4770 #undef I64M
4771 }
4772
4773 static void
4774 micro_umul_hi(union tgsi_exec_channel *dst,
4775 const union tgsi_exec_channel *src0,
4776 const union tgsi_exec_channel *src1)
4777 {
4778 #define U64M(x, y) ((((uint64_t)x) * ((uint64_t)y)) >> 32)
4779 dst->u[0] = U64M(src0->u[0], src1->u[0]);
4780 dst->u[1] = U64M(src0->u[1], src1->u[1]);
4781 dst->u[2] = U64M(src0->u[2], src1->u[2]);
4782 dst->u[3] = U64M(src0->u[3], src1->u[3]);
4783 #undef U64M
4784 }
4785
4786 static void
4787 micro_useq(union tgsi_exec_channel *dst,
4788 const union tgsi_exec_channel *src0,
4789 const union tgsi_exec_channel *src1)
4790 {
4791 dst->u[0] = src0->u[0] == src1->u[0] ? ~0 : 0;
4792 dst->u[1] = src0->u[1] == src1->u[1] ? ~0 : 0;
4793 dst->u[2] = src0->u[2] == src1->u[2] ? ~0 : 0;
4794 dst->u[3] = src0->u[3] == src1->u[3] ? ~0 : 0;
4795 }
4796
4797 static void
4798 micro_usge(union tgsi_exec_channel *dst,
4799 const union tgsi_exec_channel *src0,
4800 const union tgsi_exec_channel *src1)
4801 {
4802 dst->u[0] = src0->u[0] >= src1->u[0] ? ~0 : 0;
4803 dst->u[1] = src0->u[1] >= src1->u[1] ? ~0 : 0;
4804 dst->u[2] = src0->u[2] >= src1->u[2] ? ~0 : 0;
4805 dst->u[3] = src0->u[3] >= src1->u[3] ? ~0 : 0;
4806 }
4807
4808 static void
4809 micro_ushr(union tgsi_exec_channel *dst,
4810 const union tgsi_exec_channel *src0,
4811 const union tgsi_exec_channel *src1)
4812 {
4813 unsigned masked_count;
4814 masked_count = src1->u[0] & 0x1f;
4815 dst->u[0] = src0->u[0] >> masked_count;
4816 masked_count = src1->u[1] & 0x1f;
4817 dst->u[1] = src0->u[1] >> masked_count;
4818 masked_count = src1->u[2] & 0x1f;
4819 dst->u[2] = src0->u[2] >> masked_count;
4820 masked_count = src1->u[3] & 0x1f;
4821 dst->u[3] = src0->u[3] >> masked_count;
4822 }
4823
4824 static void
4825 micro_uslt(union tgsi_exec_channel *dst,
4826 const union tgsi_exec_channel *src0,
4827 const union tgsi_exec_channel *src1)
4828 {
4829 dst->u[0] = src0->u[0] < src1->u[0] ? ~0 : 0;
4830 dst->u[1] = src0->u[1] < src1->u[1] ? ~0 : 0;
4831 dst->u[2] = src0->u[2] < src1->u[2] ? ~0 : 0;
4832 dst->u[3] = src0->u[3] < src1->u[3] ? ~0 : 0;
4833 }
4834
4835 static void
4836 micro_usne(union tgsi_exec_channel *dst,
4837 const union tgsi_exec_channel *src0,
4838 const union tgsi_exec_channel *src1)
4839 {
4840 dst->u[0] = src0->u[0] != src1->u[0] ? ~0 : 0;
4841 dst->u[1] = src0->u[1] != src1->u[1] ? ~0 : 0;
4842 dst->u[2] = src0->u[2] != src1->u[2] ? ~0 : 0;
4843 dst->u[3] = src0->u[3] != src1->u[3] ? ~0 : 0;
4844 }
4845
4846 static void
4847 micro_uarl(union tgsi_exec_channel *dst,
4848 const union tgsi_exec_channel *src)
4849 {
4850 dst->i[0] = src->u[0];
4851 dst->i[1] = src->u[1];
4852 dst->i[2] = src->u[2];
4853 dst->i[3] = src->u[3];
4854 }
4855
4856 /**
4857 * Signed bitfield extract (i.e. sign-extend the extracted bits)
4858 */
4859 static void
4860 micro_ibfe(union tgsi_exec_channel *dst,
4861 const union tgsi_exec_channel *src0,
4862 const union tgsi_exec_channel *src1,
4863 const union tgsi_exec_channel *src2)
4864 {
4865 int i;
4866 for (i = 0; i < 4; i++) {
4867 int width = src2->i[i] & 0x1f;
4868 int offset = src1->i[i] & 0x1f;
4869 if (width == 0)
4870 dst->i[i] = 0;
4871 else if (width + offset < 32)
4872 dst->i[i] = (src0->i[i] << (32 - width - offset)) >> (32 - width);
4873 else
4874 dst->i[i] = src0->i[i] >> offset;
4875 }
4876 }
4877
4878 /**
4879 * Unsigned bitfield extract
4880 */
4881 static void
4882 micro_ubfe(union tgsi_exec_channel *dst,
4883 const union tgsi_exec_channel *src0,
4884 const union tgsi_exec_channel *src1,
4885 const union tgsi_exec_channel *src2)
4886 {
4887 int i;
4888 for (i = 0; i < 4; i++) {
4889 int width = src2->u[i] & 0x1f;
4890 int offset = src1->u[i] & 0x1f;
4891 if (width == 0)
4892 dst->u[i] = 0;
4893 else if (width + offset < 32)
4894 dst->u[i] = (src0->u[i] << (32 - width - offset)) >> (32 - width);
4895 else
4896 dst->u[i] = src0->u[i] >> offset;
4897 }
4898 }
4899
4900 /**
4901 * Bitfield insert: copy low bits from src1 into a region of src0.
4902 */
4903 static void
4904 micro_bfi(union tgsi_exec_channel *dst,
4905 const union tgsi_exec_channel *src0,
4906 const union tgsi_exec_channel *src1,
4907 const union tgsi_exec_channel *src2,
4908 const union tgsi_exec_channel *src3)
4909 {
4910 int i;
4911 for (i = 0; i < 4; i++) {
4912 int width = src3->u[i] & 0x1f;
4913 int offset = src2->u[i] & 0x1f;
4914 int bitmask = ((1 << width) - 1) << offset;
4915 dst->u[i] = ((src1->u[i] << offset) & bitmask) | (src0->u[i] & ~bitmask);
4916 }
4917 }
4918
4919 static void
4920 micro_brev(union tgsi_exec_channel *dst,
4921 const union tgsi_exec_channel *src)
4922 {
4923 dst->u[0] = util_bitreverse(src->u[0]);
4924 dst->u[1] = util_bitreverse(src->u[1]);
4925 dst->u[2] = util_bitreverse(src->u[2]);
4926 dst->u[3] = util_bitreverse(src->u[3]);
4927 }
4928
4929 static void
4930 micro_popc(union tgsi_exec_channel *dst,
4931 const union tgsi_exec_channel *src)
4932 {
4933 dst->u[0] = util_bitcount(src->u[0]);
4934 dst->u[1] = util_bitcount(src->u[1]);
4935 dst->u[2] = util_bitcount(src->u[2]);
4936 dst->u[3] = util_bitcount(src->u[3]);
4937 }
4938
4939 static void
4940 micro_lsb(union tgsi_exec_channel *dst,
4941 const union tgsi_exec_channel *src)
4942 {
4943 dst->i[0] = ffs(src->u[0]) - 1;
4944 dst->i[1] = ffs(src->u[1]) - 1;
4945 dst->i[2] = ffs(src->u[2]) - 1;
4946 dst->i[3] = ffs(src->u[3]) - 1;
4947 }
4948
4949 static void
4950 micro_imsb(union tgsi_exec_channel *dst,
4951 const union tgsi_exec_channel *src)
4952 {
4953 dst->i[0] = util_last_bit_signed(src->i[0]) - 1;
4954 dst->i[1] = util_last_bit_signed(src->i[1]) - 1;
4955 dst->i[2] = util_last_bit_signed(src->i[2]) - 1;
4956 dst->i[3] = util_last_bit_signed(src->i[3]) - 1;
4957 }
4958
4959 static void
4960 micro_umsb(union tgsi_exec_channel *dst,
4961 const union tgsi_exec_channel *src)
4962 {
4963 dst->i[0] = util_last_bit(src->u[0]) - 1;
4964 dst->i[1] = util_last_bit(src->u[1]) - 1;
4965 dst->i[2] = util_last_bit(src->u[2]) - 1;
4966 dst->i[3] = util_last_bit(src->u[3]) - 1;
4967 }
4968
4969 /**
4970 * Execute a TGSI instruction.
4971 * Returns TRUE if a barrier instruction is hit,
4972 * otherwise FALSE.
4973 */
4974 static boolean
4975 exec_instruction(
4976 struct tgsi_exec_machine *mach,
4977 const struct tgsi_full_instruction *inst,
4978 int *pc )
4979 {
4980 union tgsi_exec_channel r[10];
4981
4982 (*pc)++;
4983
4984 switch (inst->Instruction.Opcode) {
4985 case TGSI_OPCODE_ARL:
4986 exec_vector_unary(mach, inst, micro_arl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4987 break;
4988
4989 case TGSI_OPCODE_MOV:
4990 exec_vector_unary(mach, inst, micro_mov, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4991 break;
4992
4993 case TGSI_OPCODE_LIT:
4994 exec_lit(mach, inst);
4995 break;
4996
4997 case TGSI_OPCODE_RCP:
4998 exec_scalar_unary(mach, inst, micro_rcp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4999 break;
5000
5001 case TGSI_OPCODE_RSQ:
5002 exec_scalar_unary(mach, inst, micro_rsq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5003 break;
5004
5005 case TGSI_OPCODE_EXP:
5006 exec_exp(mach, inst);
5007 break;
5008
5009 case TGSI_OPCODE_LOG:
5010 exec_log(mach, inst);
5011 break;
5012
5013 case TGSI_OPCODE_MUL:
5014 exec_vector_binary(mach, inst, micro_mul, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5015 break;
5016
5017 case TGSI_OPCODE_ADD:
5018 exec_vector_binary(mach, inst, micro_add, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5019 break;
5020
5021 case TGSI_OPCODE_DP3:
5022 exec_dp3(mach, inst);
5023 break;
5024
5025 case TGSI_OPCODE_DP4:
5026 exec_dp4(mach, inst);
5027 break;
5028
5029 case TGSI_OPCODE_DST:
5030 exec_dst(mach, inst);
5031 break;
5032
5033 case TGSI_OPCODE_MIN:
5034 exec_vector_binary(mach, inst, micro_min, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5035 break;
5036
5037 case TGSI_OPCODE_MAX:
5038 exec_vector_binary(mach, inst, micro_max, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5039 break;
5040
5041 case TGSI_OPCODE_SLT:
5042 exec_vector_binary(mach, inst, micro_slt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5043 break;
5044
5045 case TGSI_OPCODE_SGE:
5046 exec_vector_binary(mach, inst, micro_sge, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5047 break;
5048
5049 case TGSI_OPCODE_MAD:
5050 exec_vector_trinary(mach, inst, micro_mad, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5051 break;
5052
5053 case TGSI_OPCODE_LRP:
5054 exec_vector_trinary(mach, inst, micro_lrp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5055 break;
5056
5057 case TGSI_OPCODE_SQRT:
5058 exec_scalar_unary(mach, inst, micro_sqrt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5059 break;
5060
5061 case TGSI_OPCODE_FRC:
5062 exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5063 break;
5064
5065 case TGSI_OPCODE_FLR:
5066 exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5067 break;
5068
5069 case TGSI_OPCODE_ROUND:
5070 exec_vector_unary(mach, inst, micro_rnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5071 break;
5072
5073 case TGSI_OPCODE_EX2:
5074 exec_scalar_unary(mach, inst, micro_exp2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5075 break;
5076
5077 case TGSI_OPCODE_LG2:
5078 exec_scalar_unary(mach, inst, micro_lg2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5079 break;
5080
5081 case TGSI_OPCODE_POW:
5082 exec_scalar_binary(mach, inst, micro_pow, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5083 break;
5084
5085 case TGSI_OPCODE_COS:
5086 exec_scalar_unary(mach, inst, micro_cos, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5087 break;
5088
5089 case TGSI_OPCODE_DDX:
5090 exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5091 break;
5092
5093 case TGSI_OPCODE_DDY:
5094 exec_vector_unary(mach, inst, micro_ddy, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5095 break;
5096
5097 case TGSI_OPCODE_KILL:
5098 exec_kill (mach, inst);
5099 break;
5100
5101 case TGSI_OPCODE_KILL_IF:
5102 exec_kill_if (mach, inst);
5103 break;
5104
5105 case TGSI_OPCODE_PK2H:
5106 exec_pk2h(mach, inst);
5107 break;
5108
5109 case TGSI_OPCODE_PK2US:
5110 assert (0);
5111 break;
5112
5113 case TGSI_OPCODE_PK4B:
5114 assert (0);
5115 break;
5116
5117 case TGSI_OPCODE_PK4UB:
5118 assert (0);
5119 break;
5120
5121 case TGSI_OPCODE_SEQ:
5122 exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5123 break;
5124
5125 case TGSI_OPCODE_SGT:
5126 exec_vector_binary(mach, inst, micro_sgt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5127 break;
5128
5129 case TGSI_OPCODE_SIN:
5130 exec_scalar_unary(mach, inst, micro_sin, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5131 break;
5132
5133 case TGSI_OPCODE_SLE:
5134 exec_vector_binary(mach, inst, micro_sle, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5135 break;
5136
5137 case TGSI_OPCODE_SNE:
5138 exec_vector_binary(mach, inst, micro_sne, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5139 break;
5140
5141 case TGSI_OPCODE_TEX:
5142 /* simple texture lookup */
5143 /* src[0] = texcoord */
5144 /* src[1] = sampler unit */
5145 exec_tex(mach, inst, TEX_MODIFIER_NONE, 1);
5146 break;
5147
5148 case TGSI_OPCODE_TXB:
5149 /* Texture lookup with lod bias */
5150 /* src[0] = texcoord (src[0].w = LOD bias) */
5151 /* src[1] = sampler unit */
5152 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 1);
5153 break;
5154
5155 case TGSI_OPCODE_TXD:
5156 /* Texture lookup with explict partial derivatives */
5157 /* src[0] = texcoord */
5158 /* src[1] = d[strq]/dx */
5159 /* src[2] = d[strq]/dy */
5160 /* src[3] = sampler unit */
5161 exec_txd(mach, inst);
5162 break;
5163
5164 case TGSI_OPCODE_TXL:
5165 /* Texture lookup with explit LOD */
5166 /* src[0] = texcoord (src[0].w = LOD) */
5167 /* src[1] = sampler unit */
5168 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 1);
5169 break;
5170
5171 case TGSI_OPCODE_TXP:
5172 /* Texture lookup with projection */
5173 /* src[0] = texcoord (src[0].w = projection) */
5174 /* src[1] = sampler unit */
5175 exec_tex(mach, inst, TEX_MODIFIER_PROJECTED, 1);
5176 break;
5177
5178 case TGSI_OPCODE_TG4:
5179 /* src[0] = texcoord */
5180 /* src[1] = component */
5181 /* src[2] = sampler unit */
5182 exec_tex(mach, inst, TEX_MODIFIER_GATHER, 2);
5183 break;
5184
5185 case TGSI_OPCODE_LODQ:
5186 /* src[0] = texcoord */
5187 /* src[1] = sampler unit */
5188 exec_lodq(mach, inst);
5189 break;
5190
5191 case TGSI_OPCODE_UP2H:
5192 exec_up2h(mach, inst);
5193 break;
5194
5195 case TGSI_OPCODE_UP2US:
5196 assert (0);
5197 break;
5198
5199 case TGSI_OPCODE_UP4B:
5200 assert (0);
5201 break;
5202
5203 case TGSI_OPCODE_UP4UB:
5204 assert (0);
5205 break;
5206
5207 case TGSI_OPCODE_ARR:
5208 exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
5209 break;
5210
5211 case TGSI_OPCODE_CAL:
5212 /* skip the call if no execution channels are enabled */
5213 if (mach->ExecMask) {
5214 /* do the call */
5215
5216 /* First, record the depths of the execution stacks.
5217 * This is important for deeply nested/looped return statements.
5218 * We have to unwind the stacks by the correct amount. For a
5219 * real code generator, we could determine the number of entries
5220 * to pop off each stack with simple static analysis and avoid
5221 * implementing this data structure at run time.
5222 */
5223 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
5224 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
5225 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
5226 mach->CallStack[mach->CallStackTop].SwitchStackTop = mach->SwitchStackTop;
5227 mach->CallStack[mach->CallStackTop].BreakStackTop = mach->BreakStackTop;
5228 /* note that PC was already incremented above */
5229 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
5230
5231 mach->CallStackTop++;
5232
5233 /* Second, push the Cond, Loop, Cont, Func stacks */
5234 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
5235 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5236 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5237 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
5238 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
5239 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
5240
5241 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
5242 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
5243 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
5244 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
5245 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
5246 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
5247
5248 /* Finally, jump to the subroutine. The label is a pointer
5249 * (an instruction number) to the BGNSUB instruction.
5250 */
5251 *pc = inst->Label.Label;
5252 assert(mach->Instructions[*pc].Instruction.Opcode
5253 == TGSI_OPCODE_BGNSUB);
5254 }
5255 break;
5256
5257 case TGSI_OPCODE_RET:
5258 mach->FuncMask &= ~mach->ExecMask;
5259 UPDATE_EXEC_MASK(mach);
5260
5261 if (mach->FuncMask == 0x0) {
5262 /* really return now (otherwise, keep executing */
5263
5264 if (mach->CallStackTop == 0) {
5265 /* returning from main() */
5266 mach->CondStackTop = 0;
5267 mach->LoopStackTop = 0;
5268 mach->ContStackTop = 0;
5269 mach->LoopLabelStackTop = 0;
5270 mach->SwitchStackTop = 0;
5271 mach->BreakStackTop = 0;
5272 *pc = -1;
5273 return FALSE;
5274 }
5275
5276 assert(mach->CallStackTop > 0);
5277 mach->CallStackTop--;
5278
5279 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
5280 mach->CondMask = mach->CondStack[mach->CondStackTop];
5281
5282 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
5283 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
5284
5285 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
5286 mach->ContMask = mach->ContStack[mach->ContStackTop];
5287
5288 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
5289 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
5290
5291 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
5292 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
5293
5294 assert(mach->FuncStackTop > 0);
5295 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
5296
5297 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
5298
5299 UPDATE_EXEC_MASK(mach);
5300 }
5301 break;
5302
5303 case TGSI_OPCODE_SSG:
5304 exec_vector_unary(mach, inst, micro_sgn, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5305 break;
5306
5307 case TGSI_OPCODE_CMP:
5308 exec_vector_trinary(mach, inst, micro_cmp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5309 break;
5310
5311 case TGSI_OPCODE_DIV:
5312 exec_vector_binary(mach, inst, micro_div, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5313 break;
5314
5315 case TGSI_OPCODE_DP2:
5316 exec_dp2(mach, inst);
5317 break;
5318
5319 case TGSI_OPCODE_IF:
5320 /* push CondMask */
5321 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
5322 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
5323 FETCH( &r[0], 0, TGSI_CHAN_X );
5324 /* update CondMask */
5325 if( ! r[0].f[0] ) {
5326 mach->CondMask &= ~0x1;
5327 }
5328 if( ! r[0].f[1] ) {
5329 mach->CondMask &= ~0x2;
5330 }
5331 if( ! r[0].f[2] ) {
5332 mach->CondMask &= ~0x4;
5333 }
5334 if( ! r[0].f[3] ) {
5335 mach->CondMask &= ~0x8;
5336 }
5337 UPDATE_EXEC_MASK(mach);
5338 /* Todo: If CondMask==0, jump to ELSE */
5339 break;
5340
5341 case TGSI_OPCODE_UIF:
5342 /* push CondMask */
5343 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
5344 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
5345 IFETCH( &r[0], 0, TGSI_CHAN_X );
5346 /* update CondMask */
5347 if( ! r[0].u[0] ) {
5348 mach->CondMask &= ~0x1;
5349 }
5350 if( ! r[0].u[1] ) {
5351 mach->CondMask &= ~0x2;
5352 }
5353 if( ! r[0].u[2] ) {
5354 mach->CondMask &= ~0x4;
5355 }
5356 if( ! r[0].u[3] ) {
5357 mach->CondMask &= ~0x8;
5358 }
5359 UPDATE_EXEC_MASK(mach);
5360 /* Todo: If CondMask==0, jump to ELSE */
5361 break;
5362
5363 case TGSI_OPCODE_ELSE:
5364 /* invert CondMask wrt previous mask */
5365 {
5366 uint prevMask;
5367 assert(mach->CondStackTop > 0);
5368 prevMask = mach->CondStack[mach->CondStackTop - 1];
5369 mach->CondMask = ~mach->CondMask & prevMask;
5370 UPDATE_EXEC_MASK(mach);
5371 /* Todo: If CondMask==0, jump to ENDIF */
5372 }
5373 break;
5374
5375 case TGSI_OPCODE_ENDIF:
5376 /* pop CondMask */
5377 assert(mach->CondStackTop > 0);
5378 mach->CondMask = mach->CondStack[--mach->CondStackTop];
5379 UPDATE_EXEC_MASK(mach);
5380 break;
5381
5382 case TGSI_OPCODE_END:
5383 /* make sure we end primitives which haven't
5384 * been explicitly emitted */
5385 conditional_emit_primitive(mach);
5386 /* halt execution */
5387 *pc = -1;
5388 break;
5389
5390 case TGSI_OPCODE_CEIL:
5391 exec_vector_unary(mach, inst, micro_ceil, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5392 break;
5393
5394 case TGSI_OPCODE_I2F:
5395 exec_vector_unary(mach, inst, micro_i2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
5396 break;
5397
5398 case TGSI_OPCODE_NOT:
5399 exec_vector_unary(mach, inst, micro_not, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5400 break;
5401
5402 case TGSI_OPCODE_TRUNC:
5403 exec_vector_unary(mach, inst, micro_trunc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5404 break;
5405
5406 case TGSI_OPCODE_SHL:
5407 exec_vector_binary(mach, inst, micro_shl, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5408 break;
5409
5410 case TGSI_OPCODE_AND:
5411 exec_vector_binary(mach, inst, micro_and, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5412 break;
5413
5414 case TGSI_OPCODE_OR:
5415 exec_vector_binary(mach, inst, micro_or, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5416 break;
5417
5418 case TGSI_OPCODE_MOD:
5419 exec_vector_binary(mach, inst, micro_mod, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5420 break;
5421
5422 case TGSI_OPCODE_XOR:
5423 exec_vector_binary(mach, inst, micro_xor, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5424 break;
5425
5426 case TGSI_OPCODE_TXF:
5427 exec_txf(mach, inst);
5428 break;
5429
5430 case TGSI_OPCODE_TXQ:
5431 exec_txq(mach, inst);
5432 break;
5433
5434 case TGSI_OPCODE_EMIT:
5435 emit_vertex(mach);
5436 break;
5437
5438 case TGSI_OPCODE_ENDPRIM:
5439 emit_primitive(mach);
5440 break;
5441
5442 case TGSI_OPCODE_BGNLOOP:
5443 /* push LoopMask and ContMasks */
5444 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5445 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5446 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5447 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
5448
5449 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
5450 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
5451 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
5452 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
5453 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_LOOP;
5454 break;
5455
5456 case TGSI_OPCODE_ENDLOOP:
5457 /* Restore ContMask, but don't pop */
5458 assert(mach->ContStackTop > 0);
5459 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
5460 UPDATE_EXEC_MASK(mach);
5461 if (mach->ExecMask) {
5462 /* repeat loop: jump to instruction just past BGNLOOP */
5463 assert(mach->LoopLabelStackTop > 0);
5464 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
5465 }
5466 else {
5467 /* exit loop: pop LoopMask */
5468 assert(mach->LoopStackTop > 0);
5469 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
5470 /* pop ContMask */
5471 assert(mach->ContStackTop > 0);
5472 mach->ContMask = mach->ContStack[--mach->ContStackTop];
5473 assert(mach->LoopLabelStackTop > 0);
5474 --mach->LoopLabelStackTop;
5475
5476 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
5477 }
5478 UPDATE_EXEC_MASK(mach);
5479 break;
5480
5481 case TGSI_OPCODE_BRK:
5482 exec_break(mach);
5483 break;
5484
5485 case TGSI_OPCODE_CONT:
5486 /* turn off cont channels for each enabled exec channel */
5487 mach->ContMask &= ~mach->ExecMask;
5488 /* Todo: if mach->LoopMask == 0, jump to end of loop */
5489 UPDATE_EXEC_MASK(mach);
5490 break;
5491
5492 case TGSI_OPCODE_BGNSUB:
5493 /* no-op */
5494 break;
5495
5496 case TGSI_OPCODE_ENDSUB:
5497 /*
5498 * XXX: This really should be a no-op. We should never reach this opcode.
5499 */
5500
5501 assert(mach->CallStackTop > 0);
5502 mach->CallStackTop--;
5503
5504 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
5505 mach->CondMask = mach->CondStack[mach->CondStackTop];
5506
5507 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
5508 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
5509
5510 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
5511 mach->ContMask = mach->ContStack[mach->ContStackTop];
5512
5513 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
5514 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
5515
5516 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
5517 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
5518
5519 assert(mach->FuncStackTop > 0);
5520 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
5521
5522 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
5523
5524 UPDATE_EXEC_MASK(mach);
5525 break;
5526
5527 case TGSI_OPCODE_NOP:
5528 break;
5529
5530 case TGSI_OPCODE_F2I:
5531 exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
5532 break;
5533
5534 case TGSI_OPCODE_FSEQ:
5535 exec_vector_binary(mach, inst, micro_fseq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5536 break;
5537
5538 case TGSI_OPCODE_FSGE:
5539 exec_vector_binary(mach, inst, micro_fsge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5540 break;
5541
5542 case TGSI_OPCODE_FSLT:
5543 exec_vector_binary(mach, inst, micro_fslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5544 break;
5545
5546 case TGSI_OPCODE_FSNE:
5547 exec_vector_binary(mach, inst, micro_fsne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5548 break;
5549
5550 case TGSI_OPCODE_IDIV:
5551 exec_vector_binary(mach, inst, micro_idiv, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5552 break;
5553
5554 case TGSI_OPCODE_IMAX:
5555 exec_vector_binary(mach, inst, micro_imax, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5556 break;
5557
5558 case TGSI_OPCODE_IMIN:
5559 exec_vector_binary(mach, inst, micro_imin, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5560 break;
5561
5562 case TGSI_OPCODE_INEG:
5563 exec_vector_unary(mach, inst, micro_ineg, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5564 break;
5565
5566 case TGSI_OPCODE_ISGE:
5567 exec_vector_binary(mach, inst, micro_isge, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5568 break;
5569
5570 case TGSI_OPCODE_ISHR:
5571 exec_vector_binary(mach, inst, micro_ishr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5572 break;
5573
5574 case TGSI_OPCODE_ISLT:
5575 exec_vector_binary(mach, inst, micro_islt, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5576 break;
5577
5578 case TGSI_OPCODE_F2U:
5579 exec_vector_unary(mach, inst, micro_f2u, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5580 break;
5581
5582 case TGSI_OPCODE_U2F:
5583 exec_vector_unary(mach, inst, micro_u2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_UINT);
5584 break;
5585
5586 case TGSI_OPCODE_UADD:
5587 exec_vector_binary(mach, inst, micro_uadd, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5588 break;
5589
5590 case TGSI_OPCODE_UDIV:
5591 exec_vector_binary(mach, inst, micro_udiv, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5592 break;
5593
5594 case TGSI_OPCODE_UMAD:
5595 exec_vector_trinary(mach, inst, micro_umad, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5596 break;
5597
5598 case TGSI_OPCODE_UMAX:
5599 exec_vector_binary(mach, inst, micro_umax, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5600 break;
5601
5602 case TGSI_OPCODE_UMIN:
5603 exec_vector_binary(mach, inst, micro_umin, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5604 break;
5605
5606 case TGSI_OPCODE_UMOD:
5607 exec_vector_binary(mach, inst, micro_umod, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5608 break;
5609
5610 case TGSI_OPCODE_UMUL:
5611 exec_vector_binary(mach, inst, micro_umul, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5612 break;
5613
5614 case TGSI_OPCODE_IMUL_HI:
5615 exec_vector_binary(mach, inst, micro_imul_hi, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5616 break;
5617
5618 case TGSI_OPCODE_UMUL_HI:
5619 exec_vector_binary(mach, inst, micro_umul_hi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5620 break;
5621
5622 case TGSI_OPCODE_USEQ:
5623 exec_vector_binary(mach, inst, micro_useq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5624 break;
5625
5626 case TGSI_OPCODE_USGE:
5627 exec_vector_binary(mach, inst, micro_usge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5628 break;
5629
5630 case TGSI_OPCODE_USHR:
5631 exec_vector_binary(mach, inst, micro_ushr, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5632 break;
5633
5634 case TGSI_OPCODE_USLT:
5635 exec_vector_binary(mach, inst, micro_uslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5636 break;
5637
5638 case TGSI_OPCODE_USNE:
5639 exec_vector_binary(mach, inst, micro_usne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5640 break;
5641
5642 case TGSI_OPCODE_SWITCH:
5643 exec_switch(mach, inst);
5644 break;
5645
5646 case TGSI_OPCODE_CASE:
5647 exec_case(mach, inst);
5648 break;
5649
5650 case TGSI_OPCODE_DEFAULT:
5651 exec_default(mach);
5652 break;
5653
5654 case TGSI_OPCODE_ENDSWITCH:
5655 exec_endswitch(mach);
5656 break;
5657
5658 case TGSI_OPCODE_SAMPLE_I:
5659 exec_txf(mach, inst);
5660 break;
5661
5662 case TGSI_OPCODE_SAMPLE_I_MS:
5663 exec_txf(mach, inst);
5664 break;
5665
5666 case TGSI_OPCODE_SAMPLE:
5667 exec_sample(mach, inst, TEX_MODIFIER_NONE, FALSE);
5668 break;
5669
5670 case TGSI_OPCODE_SAMPLE_B:
5671 exec_sample(mach, inst, TEX_MODIFIER_LOD_BIAS, FALSE);
5672 break;
5673
5674 case TGSI_OPCODE_SAMPLE_C:
5675 exec_sample(mach, inst, TEX_MODIFIER_NONE, TRUE);
5676 break;
5677
5678 case TGSI_OPCODE_SAMPLE_C_LZ:
5679 exec_sample(mach, inst, TEX_MODIFIER_LEVEL_ZERO, TRUE);
5680 break;
5681
5682 case TGSI_OPCODE_SAMPLE_D:
5683 exec_sample_d(mach, inst);
5684 break;
5685
5686 case TGSI_OPCODE_SAMPLE_L:
5687 exec_sample(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, FALSE);
5688 break;
5689
5690 case TGSI_OPCODE_GATHER4:
5691 exec_sample(mach, inst, TEX_MODIFIER_GATHER, FALSE);
5692 break;
5693
5694 case TGSI_OPCODE_SVIEWINFO:
5695 exec_txq(mach, inst);
5696 break;
5697
5698 case TGSI_OPCODE_SAMPLE_POS:
5699 assert(0);
5700 break;
5701
5702 case TGSI_OPCODE_SAMPLE_INFO:
5703 assert(0);
5704 break;
5705
5706 case TGSI_OPCODE_UARL:
5707 exec_vector_unary(mach, inst, micro_uarl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
5708 break;
5709
5710 case TGSI_OPCODE_UCMP:
5711 exec_ucmp(mach, inst);
5712 break;
5713
5714 case TGSI_OPCODE_IABS:
5715 exec_vector_unary(mach, inst, micro_iabs, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5716 break;
5717
5718 case TGSI_OPCODE_ISSG:
5719 exec_vector_unary(mach, inst, micro_isgn, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5720 break;
5721
5722 case TGSI_OPCODE_TEX2:
5723 /* simple texture lookup */
5724 /* src[0] = texcoord */
5725 /* src[1] = compare */
5726 /* src[2] = sampler unit */
5727 exec_tex(mach, inst, TEX_MODIFIER_NONE, 2);
5728 break;
5729 case TGSI_OPCODE_TXB2:
5730 /* simple texture lookup */
5731 /* src[0] = texcoord */
5732 /* src[1] = bias */
5733 /* src[2] = sampler unit */
5734 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 2);
5735 break;
5736 case TGSI_OPCODE_TXL2:
5737 /* simple texture lookup */
5738 /* src[0] = texcoord */
5739 /* src[1] = lod */
5740 /* src[2] = sampler unit */
5741 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 2);
5742 break;
5743
5744 case TGSI_OPCODE_IBFE:
5745 exec_vector_trinary(mach, inst, micro_ibfe, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5746 break;
5747 case TGSI_OPCODE_UBFE:
5748 exec_vector_trinary(mach, inst, micro_ubfe, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5749 break;
5750 case TGSI_OPCODE_BFI:
5751 exec_vector_quaternary(mach, inst, micro_bfi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5752 break;
5753 case TGSI_OPCODE_BREV:
5754 exec_vector_unary(mach, inst, micro_brev, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5755 break;
5756 case TGSI_OPCODE_POPC:
5757 exec_vector_unary(mach, inst, micro_popc, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5758 break;
5759 case TGSI_OPCODE_LSB:
5760 exec_vector_unary(mach, inst, micro_lsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
5761 break;
5762 case TGSI_OPCODE_IMSB:
5763 exec_vector_unary(mach, inst, micro_imsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5764 break;
5765 case TGSI_OPCODE_UMSB:
5766 exec_vector_unary(mach, inst, micro_umsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
5767 break;
5768
5769 case TGSI_OPCODE_F2D:
5770 exec_t_2_64(mach, inst, micro_f2d, TGSI_EXEC_DATA_FLOAT);
5771 break;
5772
5773 case TGSI_OPCODE_D2F:
5774 exec_64_2_t(mach, inst, micro_d2f, TGSI_EXEC_DATA_FLOAT);
5775 break;
5776
5777 case TGSI_OPCODE_DABS:
5778 exec_double_unary(mach, inst, micro_dabs);
5779 break;
5780
5781 case TGSI_OPCODE_DNEG:
5782 exec_double_unary(mach, inst, micro_dneg);
5783 break;
5784
5785 case TGSI_OPCODE_DADD:
5786 exec_double_binary(mach, inst, micro_dadd, TGSI_EXEC_DATA_DOUBLE);
5787 break;
5788
5789 case TGSI_OPCODE_DDIV:
5790 exec_double_binary(mach, inst, micro_ddiv, TGSI_EXEC_DATA_DOUBLE);
5791 break;
5792
5793 case TGSI_OPCODE_DMUL:
5794 exec_double_binary(mach, inst, micro_dmul, TGSI_EXEC_DATA_DOUBLE);
5795 break;
5796
5797 case TGSI_OPCODE_DMAX:
5798 exec_double_binary(mach, inst, micro_dmax, TGSI_EXEC_DATA_DOUBLE);
5799 break;
5800
5801 case TGSI_OPCODE_DMIN:
5802 exec_double_binary(mach, inst, micro_dmin, TGSI_EXEC_DATA_DOUBLE);
5803 break;
5804
5805 case TGSI_OPCODE_DSLT:
5806 exec_double_binary(mach, inst, micro_dslt, TGSI_EXEC_DATA_UINT);
5807 break;
5808
5809 case TGSI_OPCODE_DSGE:
5810 exec_double_binary(mach, inst, micro_dsge, TGSI_EXEC_DATA_UINT);
5811 break;
5812
5813 case TGSI_OPCODE_DSEQ:
5814 exec_double_binary(mach, inst, micro_dseq, TGSI_EXEC_DATA_UINT);
5815 break;
5816
5817 case TGSI_OPCODE_DSNE:
5818 exec_double_binary(mach, inst, micro_dsne, TGSI_EXEC_DATA_UINT);
5819 break;
5820
5821 case TGSI_OPCODE_DRCP:
5822 exec_double_unary(mach, inst, micro_drcp);
5823 break;
5824
5825 case TGSI_OPCODE_DSQRT:
5826 exec_double_unary(mach, inst, micro_dsqrt);
5827 break;
5828
5829 case TGSI_OPCODE_DRSQ:
5830 exec_double_unary(mach, inst, micro_drsq);
5831 break;
5832
5833 case TGSI_OPCODE_DMAD:
5834 exec_double_trinary(mach, inst, micro_dmad);
5835 break;
5836
5837 case TGSI_OPCODE_DFRAC:
5838 exec_double_unary(mach, inst, micro_dfrac);
5839 break;
5840
5841 case TGSI_OPCODE_DLDEXP:
5842 exec_dldexp(mach, inst);
5843 break;
5844
5845 case TGSI_OPCODE_DFRACEXP:
5846 exec_dfracexp(mach, inst);
5847 break;
5848
5849 case TGSI_OPCODE_I2D:
5850 exec_t_2_64(mach, inst, micro_i2d, TGSI_EXEC_DATA_INT);
5851 break;
5852
5853 case TGSI_OPCODE_D2I:
5854 exec_64_2_t(mach, inst, micro_d2i, TGSI_EXEC_DATA_INT);
5855 break;
5856
5857 case TGSI_OPCODE_U2D:
5858 exec_t_2_64(mach, inst, micro_u2d, TGSI_EXEC_DATA_UINT);
5859 break;
5860
5861 case TGSI_OPCODE_D2U:
5862 exec_64_2_t(mach, inst, micro_d2u, TGSI_EXEC_DATA_INT);
5863 break;
5864
5865 case TGSI_OPCODE_LOAD:
5866 exec_load(mach, inst);
5867 break;
5868
5869 case TGSI_OPCODE_STORE:
5870 exec_store(mach, inst);
5871 break;
5872
5873 case TGSI_OPCODE_ATOMUADD:
5874 case TGSI_OPCODE_ATOMXCHG:
5875 case TGSI_OPCODE_ATOMCAS:
5876 case TGSI_OPCODE_ATOMAND:
5877 case TGSI_OPCODE_ATOMOR:
5878 case TGSI_OPCODE_ATOMXOR:
5879 case TGSI_OPCODE_ATOMUMIN:
5880 case TGSI_OPCODE_ATOMUMAX:
5881 case TGSI_OPCODE_ATOMIMIN:
5882 case TGSI_OPCODE_ATOMIMAX:
5883 exec_atomop(mach, inst);
5884 break;
5885
5886 case TGSI_OPCODE_RESQ:
5887 exec_resq(mach, inst);
5888 break;
5889 case TGSI_OPCODE_BARRIER:
5890 case TGSI_OPCODE_MEMBAR:
5891 return TRUE;
5892 break;
5893
5894 case TGSI_OPCODE_I64ABS:
5895 exec_double_unary(mach, inst, micro_i64abs);
5896 break;
5897
5898 case TGSI_OPCODE_I64SSG:
5899 exec_double_unary(mach, inst, micro_i64sgn);
5900 break;
5901
5902 case TGSI_OPCODE_I64NEG:
5903 exec_double_unary(mach, inst, micro_i64neg);
5904 break;
5905
5906 case TGSI_OPCODE_U64SEQ:
5907 exec_double_binary(mach, inst, micro_u64seq, TGSI_EXEC_DATA_UINT);
5908 break;
5909
5910 case TGSI_OPCODE_U64SNE:
5911 exec_double_binary(mach, inst, micro_u64sne, TGSI_EXEC_DATA_UINT);
5912 break;
5913
5914 case TGSI_OPCODE_I64SLT:
5915 exec_double_binary(mach, inst, micro_i64slt, TGSI_EXEC_DATA_UINT);
5916 break;
5917 case TGSI_OPCODE_U64SLT:
5918 exec_double_binary(mach, inst, micro_u64slt, TGSI_EXEC_DATA_UINT);
5919 break;
5920
5921 case TGSI_OPCODE_I64SGE:
5922 exec_double_binary(mach, inst, micro_i64sge, TGSI_EXEC_DATA_UINT);
5923 break;
5924 case TGSI_OPCODE_U64SGE:
5925 exec_double_binary(mach, inst, micro_u64sge, TGSI_EXEC_DATA_UINT);
5926 break;
5927
5928 case TGSI_OPCODE_I64MIN:
5929 exec_double_binary(mach, inst, micro_i64min, TGSI_EXEC_DATA_INT64);
5930 break;
5931 case TGSI_OPCODE_U64MIN:
5932 exec_double_binary(mach, inst, micro_u64min, TGSI_EXEC_DATA_UINT64);
5933 break;
5934 case TGSI_OPCODE_I64MAX:
5935 exec_double_binary(mach, inst, micro_i64max, TGSI_EXEC_DATA_INT64);
5936 break;
5937 case TGSI_OPCODE_U64MAX:
5938 exec_double_binary(mach, inst, micro_u64max, TGSI_EXEC_DATA_UINT64);
5939 break;
5940 case TGSI_OPCODE_U64ADD:
5941 exec_double_binary(mach, inst, micro_u64add, TGSI_EXEC_DATA_UINT64);
5942 break;
5943 case TGSI_OPCODE_U64MUL:
5944 exec_double_binary(mach, inst, micro_u64mul, TGSI_EXEC_DATA_UINT64);
5945 break;
5946 case TGSI_OPCODE_U64SHL:
5947 exec_arg0_64_arg1_32(mach, inst, micro_u64shl);
5948 break;
5949 case TGSI_OPCODE_I64SHR:
5950 exec_arg0_64_arg1_32(mach, inst, micro_i64shr);
5951 break;
5952 case TGSI_OPCODE_U64SHR:
5953 exec_arg0_64_arg1_32(mach, inst, micro_u64shr);
5954 break;
5955 case TGSI_OPCODE_U64DIV:
5956 exec_double_binary(mach, inst, micro_u64div, TGSI_EXEC_DATA_UINT64);
5957 break;
5958 case TGSI_OPCODE_I64DIV:
5959 exec_double_binary(mach, inst, micro_i64div, TGSI_EXEC_DATA_INT64);
5960 break;
5961 case TGSI_OPCODE_U64MOD:
5962 exec_double_binary(mach, inst, micro_u64mod, TGSI_EXEC_DATA_UINT64);
5963 break;
5964 case TGSI_OPCODE_I64MOD:
5965 exec_double_binary(mach, inst, micro_i64mod, TGSI_EXEC_DATA_INT64);
5966 break;
5967
5968 case TGSI_OPCODE_F2U64:
5969 exec_t_2_64(mach, inst, micro_f2u64, TGSI_EXEC_DATA_FLOAT);
5970 break;
5971
5972 case TGSI_OPCODE_F2I64:
5973 exec_t_2_64(mach, inst, micro_f2i64, TGSI_EXEC_DATA_FLOAT);
5974 break;
5975
5976 case TGSI_OPCODE_U2I64:
5977 exec_t_2_64(mach, inst, micro_u2i64, TGSI_EXEC_DATA_INT);
5978 break;
5979 case TGSI_OPCODE_I2I64:
5980 exec_t_2_64(mach, inst, micro_i2i64, TGSI_EXEC_DATA_INT);
5981 break;
5982
5983 case TGSI_OPCODE_D2U64:
5984 exec_double_unary(mach, inst, micro_d2u64);
5985 break;
5986
5987 case TGSI_OPCODE_D2I64:
5988 exec_double_unary(mach, inst, micro_d2i64);
5989 break;
5990
5991 case TGSI_OPCODE_U642F:
5992 exec_64_2_t(mach, inst, micro_u642f, TGSI_EXEC_DATA_FLOAT);
5993 break;
5994 case TGSI_OPCODE_I642F:
5995 exec_64_2_t(mach, inst, micro_i642f, TGSI_EXEC_DATA_FLOAT);
5996 break;
5997
5998 case TGSI_OPCODE_U642D:
5999 exec_double_unary(mach, inst, micro_u642d);
6000 break;
6001 case TGSI_OPCODE_I642D:
6002 exec_double_unary(mach, inst, micro_i642d);
6003 break;
6004
6005 default:
6006 assert( 0 );
6007 }
6008 return FALSE;
6009 }
6010
6011 static void
6012 tgsi_exec_machine_setup_masks(struct tgsi_exec_machine *mach)
6013 {
6014 uint default_mask = 0xf;
6015
6016 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
6017 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
6018
6019 if (mach->ShaderType == PIPE_SHADER_GEOMETRY) {
6020 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
6021 mach->Primitives[0] = 0;
6022 /* GS runs on a single primitive for now */
6023 default_mask = 0x1;
6024 }
6025
6026 if (mach->NonHelperMask == 0)
6027 mach->NonHelperMask = default_mask;
6028 mach->CondMask = default_mask;
6029 mach->LoopMask = default_mask;
6030 mach->ContMask = default_mask;
6031 mach->FuncMask = default_mask;
6032 mach->ExecMask = default_mask;
6033
6034 mach->Switch.mask = default_mask;
6035
6036 assert(mach->CondStackTop == 0);
6037 assert(mach->LoopStackTop == 0);
6038 assert(mach->ContStackTop == 0);
6039 assert(mach->SwitchStackTop == 0);
6040 assert(mach->BreakStackTop == 0);
6041 assert(mach->CallStackTop == 0);
6042 }
6043
6044 /**
6045 * Run TGSI interpreter.
6046 * \return bitmask of "alive" quad components
6047 */
6048 uint
6049 tgsi_exec_machine_run( struct tgsi_exec_machine *mach, int start_pc )
6050 {
6051 uint i;
6052
6053 mach->pc = start_pc;
6054
6055 if (!start_pc) {
6056 tgsi_exec_machine_setup_masks(mach);
6057
6058 /* execute declarations (interpolants) */
6059 for (i = 0; i < mach->NumDeclarations; i++) {
6060 exec_declaration( mach, mach->Declarations+i );
6061 }
6062 }
6063
6064 {
6065 #if DEBUG_EXECUTION
6066 struct tgsi_exec_vector temps[TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS];
6067 struct tgsi_exec_vector outputs[PIPE_MAX_ATTRIBS];
6068 uint inst = 1;
6069
6070 if (!start_pc) {
6071 memset(mach->Temps, 0, sizeof(temps));
6072 if (mach->Outputs)
6073 memset(mach->Outputs, 0, sizeof(outputs));
6074 memset(temps, 0, sizeof(temps));
6075 memset(outputs, 0, sizeof(outputs));
6076 }
6077 #endif
6078
6079 /* execute instructions, until pc is set to -1 */
6080 while (mach->pc != -1) {
6081 boolean barrier_hit;
6082 #if DEBUG_EXECUTION
6083 uint i;
6084
6085 tgsi_dump_instruction(&mach->Instructions[mach->pc], inst++);
6086 #endif
6087
6088 assert(mach->pc < (int) mach->NumInstructions);
6089 barrier_hit = exec_instruction(mach, mach->Instructions + mach->pc, &mach->pc);
6090
6091 /* for compute shaders if we hit a barrier return now for later rescheduling */
6092 if (barrier_hit && mach->ShaderType == PIPE_SHADER_COMPUTE)
6093 return 0;
6094
6095 #if DEBUG_EXECUTION
6096 for (i = 0; i < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS; i++) {
6097 if (memcmp(&temps[i], &mach->Temps[i], sizeof(temps[i]))) {
6098 uint j;
6099
6100 memcpy(&temps[i], &mach->Temps[i], sizeof(temps[i]));
6101 debug_printf("TEMP[%2u] = ", i);
6102 for (j = 0; j < 4; j++) {
6103 if (j > 0) {
6104 debug_printf(" ");
6105 }
6106 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
6107 temps[i].xyzw[0].f[j], temps[i].xyzw[0].u[j],
6108 temps[i].xyzw[1].f[j], temps[i].xyzw[1].u[j],
6109 temps[i].xyzw[2].f[j], temps[i].xyzw[2].u[j],
6110 temps[i].xyzw[3].f[j], temps[i].xyzw[3].u[j]);
6111 }
6112 }
6113 }
6114 if (mach->Outputs) {
6115 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
6116 if (memcmp(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]))) {
6117 uint j;
6118
6119 memcpy(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]));
6120 debug_printf("OUT[%2u] = ", i);
6121 for (j = 0; j < 4; j++) {
6122 if (j > 0) {
6123 debug_printf(" ");
6124 }
6125 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
6126 outputs[i].xyzw[0].f[j], outputs[i].xyzw[0].u[j],
6127 outputs[i].xyzw[1].f[j], outputs[i].xyzw[1].u[j],
6128 outputs[i].xyzw[2].f[j], outputs[i].xyzw[2].u[j],
6129 outputs[i].xyzw[3].f[j], outputs[i].xyzw[3].u[j]);
6130 }
6131 }
6132 }
6133 }
6134 #endif
6135 }
6136 }
6137
6138 #if 0
6139 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
6140 if (mach->ShaderType == PIPE_SHADER_FRAGMENT) {
6141 /*
6142 * Scale back depth component.
6143 */
6144 for (i = 0; i < 4; i++)
6145 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
6146 }
6147 #endif
6148
6149 /* Strictly speaking, these assertions aren't really needed but they
6150 * can potentially catch some bugs in the control flow code.
6151 */
6152 assert(mach->CondStackTop == 0);
6153 assert(mach->LoopStackTop == 0);
6154 assert(mach->ContStackTop == 0);
6155 assert(mach->SwitchStackTop == 0);
6156 assert(mach->BreakStackTop == 0);
6157 assert(mach->CallStackTop == 0);
6158
6159 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
6160 }