1 /**************************************************************************
3 * Copyright 2007-2008 VMware, Inc.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 **************************************************************************/
30 * TGSI interpreter/executor.
32 * Flow control information:
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_half.h"
62 #include "util/u_memory.h"
63 #include "util/u_math.h"
64 #include "util/rounding.h"
67 #define DEBUG_EXECUTION 0
72 #define TILE_TOP_LEFT 0
73 #define TILE_TOP_RIGHT 1
74 #define TILE_BOTTOM_LEFT 2
75 #define TILE_BOTTOM_RIGHT 3
77 union tgsi_double_channel
{
78 double d
[TGSI_QUAD_SIZE
];
79 unsigned u
[TGSI_QUAD_SIZE
][2];
80 uint64_t u64
[TGSI_QUAD_SIZE
];
81 int64_t i64
[TGSI_QUAD_SIZE
];
84 struct tgsi_double_vector
{
85 union tgsi_double_channel xy
;
86 union tgsi_double_channel zw
;
90 micro_abs(union tgsi_exec_channel
*dst
,
91 const union tgsi_exec_channel
*src
)
93 dst
->f
[0] = fabsf(src
->f
[0]);
94 dst
->f
[1] = fabsf(src
->f
[1]);
95 dst
->f
[2] = fabsf(src
->f
[2]);
96 dst
->f
[3] = fabsf(src
->f
[3]);
100 micro_arl(union tgsi_exec_channel
*dst
,
101 const union tgsi_exec_channel
*src
)
103 dst
->i
[0] = (int)floorf(src
->f
[0]);
104 dst
->i
[1] = (int)floorf(src
->f
[1]);
105 dst
->i
[2] = (int)floorf(src
->f
[2]);
106 dst
->i
[3] = (int)floorf(src
->f
[3]);
110 micro_arr(union tgsi_exec_channel
*dst
,
111 const union tgsi_exec_channel
*src
)
113 dst
->i
[0] = (int)floorf(src
->f
[0] + 0.5f
);
114 dst
->i
[1] = (int)floorf(src
->f
[1] + 0.5f
);
115 dst
->i
[2] = (int)floorf(src
->f
[2] + 0.5f
);
116 dst
->i
[3] = (int)floorf(src
->f
[3] + 0.5f
);
120 micro_ceil(union tgsi_exec_channel
*dst
,
121 const union tgsi_exec_channel
*src
)
123 dst
->f
[0] = ceilf(src
->f
[0]);
124 dst
->f
[1] = ceilf(src
->f
[1]);
125 dst
->f
[2] = ceilf(src
->f
[2]);
126 dst
->f
[3] = ceilf(src
->f
[3]);
130 micro_cmp(union tgsi_exec_channel
*dst
,
131 const union tgsi_exec_channel
*src0
,
132 const union tgsi_exec_channel
*src1
,
133 const union tgsi_exec_channel
*src2
)
135 dst
->f
[0] = src0
->f
[0] < 0.0f
? src1
->f
[0] : src2
->f
[0];
136 dst
->f
[1] = src0
->f
[1] < 0.0f
? src1
->f
[1] : src2
->f
[1];
137 dst
->f
[2] = src0
->f
[2] < 0.0f
? src1
->f
[2] : src2
->f
[2];
138 dst
->f
[3] = src0
->f
[3] < 0.0f
? src1
->f
[3] : src2
->f
[3];
142 micro_cos(union tgsi_exec_channel
*dst
,
143 const union tgsi_exec_channel
*src
)
145 dst
->f
[0] = cosf(src
->f
[0]);
146 dst
->f
[1] = cosf(src
->f
[1]);
147 dst
->f
[2] = cosf(src
->f
[2]);
148 dst
->f
[3] = cosf(src
->f
[3]);
152 micro_d2f(union tgsi_exec_channel
*dst
,
153 const union tgsi_double_channel
*src
)
155 dst
->f
[0] = (float)src
->d
[0];
156 dst
->f
[1] = (float)src
->d
[1];
157 dst
->f
[2] = (float)src
->d
[2];
158 dst
->f
[3] = (float)src
->d
[3];
162 micro_d2i(union tgsi_exec_channel
*dst
,
163 const union tgsi_double_channel
*src
)
165 dst
->i
[0] = (int)src
->d
[0];
166 dst
->i
[1] = (int)src
->d
[1];
167 dst
->i
[2] = (int)src
->d
[2];
168 dst
->i
[3] = (int)src
->d
[3];
172 micro_d2u(union tgsi_exec_channel
*dst
,
173 const union tgsi_double_channel
*src
)
175 dst
->u
[0] = (unsigned)src
->d
[0];
176 dst
->u
[1] = (unsigned)src
->d
[1];
177 dst
->u
[2] = (unsigned)src
->d
[2];
178 dst
->u
[3] = (unsigned)src
->d
[3];
181 micro_dabs(union tgsi_double_channel
*dst
,
182 const union tgsi_double_channel
*src
)
184 dst
->d
[0] = src
->d
[0] >= 0.0 ? src
->d
[0] : -src
->d
[0];
185 dst
->d
[1] = src
->d
[1] >= 0.0 ? src
->d
[1] : -src
->d
[1];
186 dst
->d
[2] = src
->d
[2] >= 0.0 ? src
->d
[2] : -src
->d
[2];
187 dst
->d
[3] = src
->d
[3] >= 0.0 ? src
->d
[3] : -src
->d
[3];
191 micro_dadd(union tgsi_double_channel
*dst
,
192 const union tgsi_double_channel
*src
)
194 dst
->d
[0] = src
[0].d
[0] + src
[1].d
[0];
195 dst
->d
[1] = src
[0].d
[1] + src
[1].d
[1];
196 dst
->d
[2] = src
[0].d
[2] + src
[1].d
[2];
197 dst
->d
[3] = src
[0].d
[3] + src
[1].d
[3];
201 micro_ddiv(union tgsi_double_channel
*dst
,
202 const union tgsi_double_channel
*src
)
204 dst
->d
[0] = src
[0].d
[0] / src
[1].d
[0];
205 dst
->d
[1] = src
[0].d
[1] / src
[1].d
[1];
206 dst
->d
[2] = src
[0].d
[2] / src
[1].d
[2];
207 dst
->d
[3] = src
[0].d
[3] / src
[1].d
[3];
211 micro_ddx(union tgsi_exec_channel
*dst
,
212 const union tgsi_exec_channel
*src
)
217 dst
->f
[3] = src
->f
[TILE_BOTTOM_RIGHT
] - src
->f
[TILE_BOTTOM_LEFT
];
221 micro_ddy(union tgsi_exec_channel
*dst
,
222 const union tgsi_exec_channel
*src
)
227 dst
->f
[3] = src
->f
[TILE_BOTTOM_LEFT
] - src
->f
[TILE_TOP_LEFT
];
231 micro_dmul(union tgsi_double_channel
*dst
,
232 const union tgsi_double_channel
*src
)
234 dst
->d
[0] = src
[0].d
[0] * src
[1].d
[0];
235 dst
->d
[1] = src
[0].d
[1] * src
[1].d
[1];
236 dst
->d
[2] = src
[0].d
[2] * src
[1].d
[2];
237 dst
->d
[3] = src
[0].d
[3] * src
[1].d
[3];
241 micro_dmax(union tgsi_double_channel
*dst
,
242 const union tgsi_double_channel
*src
)
244 dst
->d
[0] = src
[0].d
[0] > src
[1].d
[0] ? src
[0].d
[0] : src
[1].d
[0];
245 dst
->d
[1] = src
[0].d
[1] > src
[1].d
[1] ? src
[0].d
[1] : src
[1].d
[1];
246 dst
->d
[2] = src
[0].d
[2] > src
[1].d
[2] ? src
[0].d
[2] : src
[1].d
[2];
247 dst
->d
[3] = src
[0].d
[3] > src
[1].d
[3] ? src
[0].d
[3] : src
[1].d
[3];
251 micro_dmin(union tgsi_double_channel
*dst
,
252 const union tgsi_double_channel
*src
)
254 dst
->d
[0] = src
[0].d
[0] < src
[1].d
[0] ? src
[0].d
[0] : src
[1].d
[0];
255 dst
->d
[1] = src
[0].d
[1] < src
[1].d
[1] ? src
[0].d
[1] : src
[1].d
[1];
256 dst
->d
[2] = src
[0].d
[2] < src
[1].d
[2] ? src
[0].d
[2] : src
[1].d
[2];
257 dst
->d
[3] = src
[0].d
[3] < src
[1].d
[3] ? src
[0].d
[3] : src
[1].d
[3];
261 micro_dneg(union tgsi_double_channel
*dst
,
262 const union tgsi_double_channel
*src
)
264 dst
->d
[0] = -src
->d
[0];
265 dst
->d
[1] = -src
->d
[1];
266 dst
->d
[2] = -src
->d
[2];
267 dst
->d
[3] = -src
->d
[3];
271 micro_dslt(union tgsi_double_channel
*dst
,
272 const union tgsi_double_channel
*src
)
274 dst
->u
[0][0] = src
[0].d
[0] < src
[1].d
[0] ? ~0U : 0U;
275 dst
->u
[1][0] = src
[0].d
[1] < src
[1].d
[1] ? ~0U : 0U;
276 dst
->u
[2][0] = src
[0].d
[2] < src
[1].d
[2] ? ~0U : 0U;
277 dst
->u
[3][0] = src
[0].d
[3] < src
[1].d
[3] ? ~0U : 0U;
281 micro_dsne(union tgsi_double_channel
*dst
,
282 const union tgsi_double_channel
*src
)
284 dst
->u
[0][0] = src
[0].d
[0] != src
[1].d
[0] ? ~0U : 0U;
285 dst
->u
[1][0] = src
[0].d
[1] != src
[1].d
[1] ? ~0U : 0U;
286 dst
->u
[2][0] = src
[0].d
[2] != src
[1].d
[2] ? ~0U : 0U;
287 dst
->u
[3][0] = src
[0].d
[3] != src
[1].d
[3] ? ~0U : 0U;
291 micro_dsge(union tgsi_double_channel
*dst
,
292 const union tgsi_double_channel
*src
)
294 dst
->u
[0][0] = src
[0].d
[0] >= src
[1].d
[0] ? ~0U : 0U;
295 dst
->u
[1][0] = src
[0].d
[1] >= src
[1].d
[1] ? ~0U : 0U;
296 dst
->u
[2][0] = src
[0].d
[2] >= src
[1].d
[2] ? ~0U : 0U;
297 dst
->u
[3][0] = src
[0].d
[3] >= src
[1].d
[3] ? ~0U : 0U;
301 micro_dseq(union tgsi_double_channel
*dst
,
302 const union tgsi_double_channel
*src
)
304 dst
->u
[0][0] = src
[0].d
[0] == src
[1].d
[0] ? ~0U : 0U;
305 dst
->u
[1][0] = src
[0].d
[1] == src
[1].d
[1] ? ~0U : 0U;
306 dst
->u
[2][0] = src
[0].d
[2] == src
[1].d
[2] ? ~0U : 0U;
307 dst
->u
[3][0] = src
[0].d
[3] == src
[1].d
[3] ? ~0U : 0U;
311 micro_drcp(union tgsi_double_channel
*dst
,
312 const union tgsi_double_channel
*src
)
314 dst
->d
[0] = 1.0 / src
->d
[0];
315 dst
->d
[1] = 1.0 / src
->d
[1];
316 dst
->d
[2] = 1.0 / src
->d
[2];
317 dst
->d
[3] = 1.0 / src
->d
[3];
321 micro_dsqrt(union tgsi_double_channel
*dst
,
322 const union tgsi_double_channel
*src
)
324 dst
->d
[0] = sqrt(src
->d
[0]);
325 dst
->d
[1] = sqrt(src
->d
[1]);
326 dst
->d
[2] = sqrt(src
->d
[2]);
327 dst
->d
[3] = sqrt(src
->d
[3]);
331 micro_drsq(union tgsi_double_channel
*dst
,
332 const union tgsi_double_channel
*src
)
334 dst
->d
[0] = 1.0 / sqrt(src
->d
[0]);
335 dst
->d
[1] = 1.0 / sqrt(src
->d
[1]);
336 dst
->d
[2] = 1.0 / sqrt(src
->d
[2]);
337 dst
->d
[3] = 1.0 / sqrt(src
->d
[3]);
341 micro_dmad(union tgsi_double_channel
*dst
,
342 const union tgsi_double_channel
*src
)
344 dst
->d
[0] = src
[0].d
[0] * src
[1].d
[0] + src
[2].d
[0];
345 dst
->d
[1] = src
[0].d
[1] * src
[1].d
[1] + src
[2].d
[1];
346 dst
->d
[2] = src
[0].d
[2] * src
[1].d
[2] + src
[2].d
[2];
347 dst
->d
[3] = src
[0].d
[3] * src
[1].d
[3] + src
[2].d
[3];
351 micro_dfrac(union tgsi_double_channel
*dst
,
352 const union tgsi_double_channel
*src
)
354 dst
->d
[0] = src
->d
[0] - floor(src
->d
[0]);
355 dst
->d
[1] = src
->d
[1] - floor(src
->d
[1]);
356 dst
->d
[2] = src
->d
[2] - floor(src
->d
[2]);
357 dst
->d
[3] = src
->d
[3] - floor(src
->d
[3]);
361 micro_dldexp(union tgsi_double_channel
*dst
,
362 const union tgsi_double_channel
*src0
,
363 union tgsi_exec_channel
*src1
)
365 dst
->d
[0] = ldexp(src0
->d
[0], src1
->i
[0]);
366 dst
->d
[1] = ldexp(src0
->d
[1], src1
->i
[1]);
367 dst
->d
[2] = ldexp(src0
->d
[2], src1
->i
[2]);
368 dst
->d
[3] = ldexp(src0
->d
[3], src1
->i
[3]);
372 micro_dfracexp(union tgsi_double_channel
*dst
,
373 union tgsi_exec_channel
*dst_exp
,
374 const union tgsi_double_channel
*src
)
376 dst
->d
[0] = frexp(src
->d
[0], &dst_exp
->i
[0]);
377 dst
->d
[1] = frexp(src
->d
[1], &dst_exp
->i
[1]);
378 dst
->d
[2] = frexp(src
->d
[2], &dst_exp
->i
[2]);
379 dst
->d
[3] = frexp(src
->d
[3], &dst_exp
->i
[3]);
383 micro_exp2(union tgsi_exec_channel
*dst
,
384 const union tgsi_exec_channel
*src
)
387 dst
->f
[0] = util_fast_exp2(src
->f
[0]);
388 dst
->f
[1] = util_fast_exp2(src
->f
[1]);
389 dst
->f
[2] = util_fast_exp2(src
->f
[2]);
390 dst
->f
[3] = util_fast_exp2(src
->f
[3]);
393 /* Inf is okay for this instruction, so clamp it to silence assertions. */
395 union tgsi_exec_channel clamped
;
397 for (i
= 0; i
< 4; i
++) {
398 if (src
->f
[i
] > 127.99999f
) {
399 clamped
.f
[i
] = 127.99999f
;
400 } else if (src
->f
[i
] < -126.99999f
) {
401 clamped
.f
[i
] = -126.99999f
;
403 clamped
.f
[i
] = src
->f
[i
];
409 dst
->f
[0] = powf(2.0f
, src
->f
[0]);
410 dst
->f
[1] = powf(2.0f
, src
->f
[1]);
411 dst
->f
[2] = powf(2.0f
, src
->f
[2]);
412 dst
->f
[3] = powf(2.0f
, src
->f
[3]);
413 #endif /* FAST_MATH */
417 micro_f2d(union tgsi_double_channel
*dst
,
418 const union tgsi_exec_channel
*src
)
420 dst
->d
[0] = (double)src
->f
[0];
421 dst
->d
[1] = (double)src
->f
[1];
422 dst
->d
[2] = (double)src
->f
[2];
423 dst
->d
[3] = (double)src
->f
[3];
427 micro_flr(union tgsi_exec_channel
*dst
,
428 const union tgsi_exec_channel
*src
)
430 dst
->f
[0] = floorf(src
->f
[0]);
431 dst
->f
[1] = floorf(src
->f
[1]);
432 dst
->f
[2] = floorf(src
->f
[2]);
433 dst
->f
[3] = floorf(src
->f
[3]);
437 micro_frc(union tgsi_exec_channel
*dst
,
438 const union tgsi_exec_channel
*src
)
440 dst
->f
[0] = src
->f
[0] - floorf(src
->f
[0]);
441 dst
->f
[1] = src
->f
[1] - floorf(src
->f
[1]);
442 dst
->f
[2] = src
->f
[2] - floorf(src
->f
[2]);
443 dst
->f
[3] = src
->f
[3] - floorf(src
->f
[3]);
447 micro_i2d(union tgsi_double_channel
*dst
,
448 const union tgsi_exec_channel
*src
)
450 dst
->d
[0] = (double)src
->i
[0];
451 dst
->d
[1] = (double)src
->i
[1];
452 dst
->d
[2] = (double)src
->i
[2];
453 dst
->d
[3] = (double)src
->i
[3];
457 micro_iabs(union tgsi_exec_channel
*dst
,
458 const union tgsi_exec_channel
*src
)
460 dst
->i
[0] = src
->i
[0] >= 0 ? src
->i
[0] : -src
->i
[0];
461 dst
->i
[1] = src
->i
[1] >= 0 ? src
->i
[1] : -src
->i
[1];
462 dst
->i
[2] = src
->i
[2] >= 0 ? src
->i
[2] : -src
->i
[2];
463 dst
->i
[3] = src
->i
[3] >= 0 ? src
->i
[3] : -src
->i
[3];
467 micro_ineg(union tgsi_exec_channel
*dst
,
468 const union tgsi_exec_channel
*src
)
470 dst
->i
[0] = -src
->i
[0];
471 dst
->i
[1] = -src
->i
[1];
472 dst
->i
[2] = -src
->i
[2];
473 dst
->i
[3] = -src
->i
[3];
477 micro_lg2(union tgsi_exec_channel
*dst
,
478 const union tgsi_exec_channel
*src
)
481 dst
->f
[0] = util_fast_log2(src
->f
[0]);
482 dst
->f
[1] = util_fast_log2(src
->f
[1]);
483 dst
->f
[2] = util_fast_log2(src
->f
[2]);
484 dst
->f
[3] = util_fast_log2(src
->f
[3]);
486 dst
->f
[0] = logf(src
->f
[0]) * 1.442695f
;
487 dst
->f
[1] = logf(src
->f
[1]) * 1.442695f
;
488 dst
->f
[2] = logf(src
->f
[2]) * 1.442695f
;
489 dst
->f
[3] = logf(src
->f
[3]) * 1.442695f
;
494 micro_lrp(union tgsi_exec_channel
*dst
,
495 const union tgsi_exec_channel
*src0
,
496 const union tgsi_exec_channel
*src1
,
497 const union tgsi_exec_channel
*src2
)
499 dst
->f
[0] = src0
->f
[0] * (src1
->f
[0] - src2
->f
[0]) + src2
->f
[0];
500 dst
->f
[1] = src0
->f
[1] * (src1
->f
[1] - src2
->f
[1]) + src2
->f
[1];
501 dst
->f
[2] = src0
->f
[2] * (src1
->f
[2] - src2
->f
[2]) + src2
->f
[2];
502 dst
->f
[3] = src0
->f
[3] * (src1
->f
[3] - src2
->f
[3]) + src2
->f
[3];
506 micro_mad(union tgsi_exec_channel
*dst
,
507 const union tgsi_exec_channel
*src0
,
508 const union tgsi_exec_channel
*src1
,
509 const union tgsi_exec_channel
*src2
)
511 dst
->f
[0] = src0
->f
[0] * src1
->f
[0] + src2
->f
[0];
512 dst
->f
[1] = src0
->f
[1] * src1
->f
[1] + src2
->f
[1];
513 dst
->f
[2] = src0
->f
[2] * src1
->f
[2] + src2
->f
[2];
514 dst
->f
[3] = src0
->f
[3] * src1
->f
[3] + src2
->f
[3];
518 micro_mov(union tgsi_exec_channel
*dst
,
519 const union tgsi_exec_channel
*src
)
521 dst
->u
[0] = src
->u
[0];
522 dst
->u
[1] = src
->u
[1];
523 dst
->u
[2] = src
->u
[2];
524 dst
->u
[3] = src
->u
[3];
528 micro_rcp(union tgsi_exec_channel
*dst
,
529 const union tgsi_exec_channel
*src
)
531 #if 0 /* for debugging */
532 assert(src
->f
[0] != 0.0f
);
533 assert(src
->f
[1] != 0.0f
);
534 assert(src
->f
[2] != 0.0f
);
535 assert(src
->f
[3] != 0.0f
);
537 dst
->f
[0] = 1.0f
/ src
->f
[0];
538 dst
->f
[1] = 1.0f
/ src
->f
[1];
539 dst
->f
[2] = 1.0f
/ src
->f
[2];
540 dst
->f
[3] = 1.0f
/ src
->f
[3];
544 micro_rnd(union tgsi_exec_channel
*dst
,
545 const union tgsi_exec_channel
*src
)
547 dst
->f
[0] = _mesa_roundevenf(src
->f
[0]);
548 dst
->f
[1] = _mesa_roundevenf(src
->f
[1]);
549 dst
->f
[2] = _mesa_roundevenf(src
->f
[2]);
550 dst
->f
[3] = _mesa_roundevenf(src
->f
[3]);
554 micro_rsq(union tgsi_exec_channel
*dst
,
555 const union tgsi_exec_channel
*src
)
557 #if 0 /* for debugging */
558 assert(src
->f
[0] != 0.0f
);
559 assert(src
->f
[1] != 0.0f
);
560 assert(src
->f
[2] != 0.0f
);
561 assert(src
->f
[3] != 0.0f
);
563 dst
->f
[0] = 1.0f
/ sqrtf(src
->f
[0]);
564 dst
->f
[1] = 1.0f
/ sqrtf(src
->f
[1]);
565 dst
->f
[2] = 1.0f
/ sqrtf(src
->f
[2]);
566 dst
->f
[3] = 1.0f
/ sqrtf(src
->f
[3]);
570 micro_sqrt(union tgsi_exec_channel
*dst
,
571 const union tgsi_exec_channel
*src
)
573 dst
->f
[0] = sqrtf(src
->f
[0]);
574 dst
->f
[1] = sqrtf(src
->f
[1]);
575 dst
->f
[2] = sqrtf(src
->f
[2]);
576 dst
->f
[3] = sqrtf(src
->f
[3]);
580 micro_seq(union tgsi_exec_channel
*dst
,
581 const union tgsi_exec_channel
*src0
,
582 const union tgsi_exec_channel
*src1
)
584 dst
->f
[0] = src0
->f
[0] == src1
->f
[0] ? 1.0f
: 0.0f
;
585 dst
->f
[1] = src0
->f
[1] == src1
->f
[1] ? 1.0f
: 0.0f
;
586 dst
->f
[2] = src0
->f
[2] == src1
->f
[2] ? 1.0f
: 0.0f
;
587 dst
->f
[3] = src0
->f
[3] == src1
->f
[3] ? 1.0f
: 0.0f
;
591 micro_sge(union tgsi_exec_channel
*dst
,
592 const union tgsi_exec_channel
*src0
,
593 const union tgsi_exec_channel
*src1
)
595 dst
->f
[0] = src0
->f
[0] >= src1
->f
[0] ? 1.0f
: 0.0f
;
596 dst
->f
[1] = src0
->f
[1] >= src1
->f
[1] ? 1.0f
: 0.0f
;
597 dst
->f
[2] = src0
->f
[2] >= src1
->f
[2] ? 1.0f
: 0.0f
;
598 dst
->f
[3] = src0
->f
[3] >= src1
->f
[3] ? 1.0f
: 0.0f
;
602 micro_sgn(union tgsi_exec_channel
*dst
,
603 const union tgsi_exec_channel
*src
)
605 dst
->f
[0] = src
->f
[0] < 0.0f
? -1.0f
: src
->f
[0] > 0.0f
? 1.0f
: 0.0f
;
606 dst
->f
[1] = src
->f
[1] < 0.0f
? -1.0f
: src
->f
[1] > 0.0f
? 1.0f
: 0.0f
;
607 dst
->f
[2] = src
->f
[2] < 0.0f
? -1.0f
: src
->f
[2] > 0.0f
? 1.0f
: 0.0f
;
608 dst
->f
[3] = src
->f
[3] < 0.0f
? -1.0f
: src
->f
[3] > 0.0f
? 1.0f
: 0.0f
;
612 micro_isgn(union tgsi_exec_channel
*dst
,
613 const union tgsi_exec_channel
*src
)
615 dst
->i
[0] = src
->i
[0] < 0 ? -1 : src
->i
[0] > 0 ? 1 : 0;
616 dst
->i
[1] = src
->i
[1] < 0 ? -1 : src
->i
[1] > 0 ? 1 : 0;
617 dst
->i
[2] = src
->i
[2] < 0 ? -1 : src
->i
[2] > 0 ? 1 : 0;
618 dst
->i
[3] = src
->i
[3] < 0 ? -1 : src
->i
[3] > 0 ? 1 : 0;
622 micro_sgt(union tgsi_exec_channel
*dst
,
623 const union tgsi_exec_channel
*src0
,
624 const union tgsi_exec_channel
*src1
)
626 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? 1.0f
: 0.0f
;
627 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? 1.0f
: 0.0f
;
628 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? 1.0f
: 0.0f
;
629 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? 1.0f
: 0.0f
;
633 micro_sin(union tgsi_exec_channel
*dst
,
634 const union tgsi_exec_channel
*src
)
636 dst
->f
[0] = sinf(src
->f
[0]);
637 dst
->f
[1] = sinf(src
->f
[1]);
638 dst
->f
[2] = sinf(src
->f
[2]);
639 dst
->f
[3] = sinf(src
->f
[3]);
643 micro_sle(union tgsi_exec_channel
*dst
,
644 const union tgsi_exec_channel
*src0
,
645 const union tgsi_exec_channel
*src1
)
647 dst
->f
[0] = src0
->f
[0] <= src1
->f
[0] ? 1.0f
: 0.0f
;
648 dst
->f
[1] = src0
->f
[1] <= src1
->f
[1] ? 1.0f
: 0.0f
;
649 dst
->f
[2] = src0
->f
[2] <= src1
->f
[2] ? 1.0f
: 0.0f
;
650 dst
->f
[3] = src0
->f
[3] <= src1
->f
[3] ? 1.0f
: 0.0f
;
654 micro_slt(union tgsi_exec_channel
*dst
,
655 const union tgsi_exec_channel
*src0
,
656 const union tgsi_exec_channel
*src1
)
658 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? 1.0f
: 0.0f
;
659 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? 1.0f
: 0.0f
;
660 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? 1.0f
: 0.0f
;
661 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? 1.0f
: 0.0f
;
665 micro_sne(union tgsi_exec_channel
*dst
,
666 const union tgsi_exec_channel
*src0
,
667 const union tgsi_exec_channel
*src1
)
669 dst
->f
[0] = src0
->f
[0] != src1
->f
[0] ? 1.0f
: 0.0f
;
670 dst
->f
[1] = src0
->f
[1] != src1
->f
[1] ? 1.0f
: 0.0f
;
671 dst
->f
[2] = src0
->f
[2] != src1
->f
[2] ? 1.0f
: 0.0f
;
672 dst
->f
[3] = src0
->f
[3] != src1
->f
[3] ? 1.0f
: 0.0f
;
676 micro_trunc(union tgsi_exec_channel
*dst
,
677 const union tgsi_exec_channel
*src
)
679 dst
->f
[0] = truncf(src
->f
[0]);
680 dst
->f
[1] = truncf(src
->f
[1]);
681 dst
->f
[2] = truncf(src
->f
[2]);
682 dst
->f
[3] = truncf(src
->f
[3]);
686 micro_u2d(union tgsi_double_channel
*dst
,
687 const union tgsi_exec_channel
*src
)
689 dst
->d
[0] = (double)src
->u
[0];
690 dst
->d
[1] = (double)src
->u
[1];
691 dst
->d
[2] = (double)src
->u
[2];
692 dst
->d
[3] = (double)src
->u
[3];
696 micro_i64abs(union tgsi_double_channel
*dst
,
697 const union tgsi_double_channel
*src
)
699 dst
->i64
[0] = src
->i64
[0] >= 0.0 ? src
->i64
[0] : -src
->i64
[0];
700 dst
->i64
[1] = src
->i64
[1] >= 0.0 ? src
->i64
[1] : -src
->i64
[1];
701 dst
->i64
[2] = src
->i64
[2] >= 0.0 ? src
->i64
[2] : -src
->i64
[2];
702 dst
->i64
[3] = src
->i64
[3] >= 0.0 ? src
->i64
[3] : -src
->i64
[3];
706 micro_i64sgn(union tgsi_double_channel
*dst
,
707 const union tgsi_double_channel
*src
)
709 dst
->i64
[0] = src
->i64
[0] < 0 ? -1 : src
->i64
[0] > 0 ? 1 : 0;
710 dst
->i64
[1] = src
->i64
[1] < 0 ? -1 : src
->i64
[1] > 0 ? 1 : 0;
711 dst
->i64
[2] = src
->i64
[2] < 0 ? -1 : src
->i64
[2] > 0 ? 1 : 0;
712 dst
->i64
[3] = src
->i64
[3] < 0 ? -1 : src
->i64
[3] > 0 ? 1 : 0;
716 micro_i64neg(union tgsi_double_channel
*dst
,
717 const union tgsi_double_channel
*src
)
719 dst
->i64
[0] = -src
->i64
[0];
720 dst
->i64
[1] = -src
->i64
[1];
721 dst
->i64
[2] = -src
->i64
[2];
722 dst
->i64
[3] = -src
->i64
[3];
726 micro_u64seq(union tgsi_double_channel
*dst
,
727 const union tgsi_double_channel
*src
)
729 dst
->u
[0][0] = src
[0].u64
[0] == src
[1].u64
[0] ? ~0U : 0U;
730 dst
->u
[1][0] = src
[0].u64
[1] == src
[1].u64
[1] ? ~0U : 0U;
731 dst
->u
[2][0] = src
[0].u64
[2] == src
[1].u64
[2] ? ~0U : 0U;
732 dst
->u
[3][0] = src
[0].u64
[3] == src
[1].u64
[3] ? ~0U : 0U;
736 micro_u64sne(union tgsi_double_channel
*dst
,
737 const union tgsi_double_channel
*src
)
739 dst
->u
[0][0] = src
[0].u64
[0] != src
[1].u64
[0] ? ~0U : 0U;
740 dst
->u
[1][0] = src
[0].u64
[1] != src
[1].u64
[1] ? ~0U : 0U;
741 dst
->u
[2][0] = src
[0].u64
[2] != src
[1].u64
[2] ? ~0U : 0U;
742 dst
->u
[3][0] = src
[0].u64
[3] != src
[1].u64
[3] ? ~0U : 0U;
746 micro_i64slt(union tgsi_double_channel
*dst
,
747 const union tgsi_double_channel
*src
)
749 dst
->u
[0][0] = src
[0].i64
[0] < src
[1].i64
[0] ? ~0U : 0U;
750 dst
->u
[1][0] = src
[0].i64
[1] < src
[1].i64
[1] ? ~0U : 0U;
751 dst
->u
[2][0] = src
[0].i64
[2] < src
[1].i64
[2] ? ~0U : 0U;
752 dst
->u
[3][0] = src
[0].i64
[3] < src
[1].i64
[3] ? ~0U : 0U;
756 micro_u64slt(union tgsi_double_channel
*dst
,
757 const union tgsi_double_channel
*src
)
759 dst
->u
[0][0] = src
[0].u64
[0] < src
[1].u64
[0] ? ~0U : 0U;
760 dst
->u
[1][0] = src
[0].u64
[1] < src
[1].u64
[1] ? ~0U : 0U;
761 dst
->u
[2][0] = src
[0].u64
[2] < src
[1].u64
[2] ? ~0U : 0U;
762 dst
->u
[3][0] = src
[0].u64
[3] < src
[1].u64
[3] ? ~0U : 0U;
766 micro_i64sge(union tgsi_double_channel
*dst
,
767 const union tgsi_double_channel
*src
)
769 dst
->u
[0][0] = src
[0].i64
[0] >= src
[1].i64
[0] ? ~0U : 0U;
770 dst
->u
[1][0] = src
[0].i64
[1] >= src
[1].i64
[1] ? ~0U : 0U;
771 dst
->u
[2][0] = src
[0].i64
[2] >= src
[1].i64
[2] ? ~0U : 0U;
772 dst
->u
[3][0] = src
[0].i64
[3] >= src
[1].i64
[3] ? ~0U : 0U;
776 micro_u64sge(union tgsi_double_channel
*dst
,
777 const union tgsi_double_channel
*src
)
779 dst
->u
[0][0] = src
[0].u64
[0] >= src
[1].u64
[0] ? ~0U : 0U;
780 dst
->u
[1][0] = src
[0].u64
[1] >= src
[1].u64
[1] ? ~0U : 0U;
781 dst
->u
[2][0] = src
[0].u64
[2] >= src
[1].u64
[2] ? ~0U : 0U;
782 dst
->u
[3][0] = src
[0].u64
[3] >= src
[1].u64
[3] ? ~0U : 0U;
786 micro_u64max(union tgsi_double_channel
*dst
,
787 const union tgsi_double_channel
*src
)
789 dst
->u64
[0] = src
[0].u64
[0] > src
[1].u64
[0] ? src
[0].u64
[0] : src
[1].u64
[0];
790 dst
->u64
[1] = src
[0].u64
[1] > src
[1].u64
[1] ? src
[0].u64
[1] : src
[1].u64
[1];
791 dst
->u64
[2] = src
[0].u64
[2] > src
[1].u64
[2] ? src
[0].u64
[2] : src
[1].u64
[2];
792 dst
->u64
[3] = src
[0].u64
[3] > src
[1].u64
[3] ? src
[0].u64
[3] : src
[1].u64
[3];
796 micro_i64max(union tgsi_double_channel
*dst
,
797 const union tgsi_double_channel
*src
)
799 dst
->i64
[0] = src
[0].i64
[0] > src
[1].i64
[0] ? src
[0].i64
[0] : src
[1].i64
[0];
800 dst
->i64
[1] = src
[0].i64
[1] > src
[1].i64
[1] ? src
[0].i64
[1] : src
[1].i64
[1];
801 dst
->i64
[2] = src
[0].i64
[2] > src
[1].i64
[2] ? src
[0].i64
[2] : src
[1].i64
[2];
802 dst
->i64
[3] = src
[0].i64
[3] > src
[1].i64
[3] ? src
[0].i64
[3] : src
[1].i64
[3];
806 micro_u64min(union tgsi_double_channel
*dst
,
807 const union tgsi_double_channel
*src
)
809 dst
->u64
[0] = src
[0].u64
[0] < src
[1].u64
[0] ? src
[0].u64
[0] : src
[1].u64
[0];
810 dst
->u64
[1] = src
[0].u64
[1] < src
[1].u64
[1] ? src
[0].u64
[1] : src
[1].u64
[1];
811 dst
->u64
[2] = src
[0].u64
[2] < src
[1].u64
[2] ? src
[0].u64
[2] : src
[1].u64
[2];
812 dst
->u64
[3] = src
[0].u64
[3] < src
[1].u64
[3] ? src
[0].u64
[3] : src
[1].u64
[3];
816 micro_i64min(union tgsi_double_channel
*dst
,
817 const union tgsi_double_channel
*src
)
819 dst
->i64
[0] = src
[0].i64
[0] < src
[1].i64
[0] ? src
[0].i64
[0] : src
[1].i64
[0];
820 dst
->i64
[1] = src
[0].i64
[1] < src
[1].i64
[1] ? src
[0].i64
[1] : src
[1].i64
[1];
821 dst
->i64
[2] = src
[0].i64
[2] < src
[1].i64
[2] ? src
[0].i64
[2] : src
[1].i64
[2];
822 dst
->i64
[3] = src
[0].i64
[3] < src
[1].i64
[3] ? src
[0].i64
[3] : src
[1].i64
[3];
826 micro_u64add(union tgsi_double_channel
*dst
,
827 const union tgsi_double_channel
*src
)
829 dst
->u64
[0] = src
[0].u64
[0] + src
[1].u64
[0];
830 dst
->u64
[1] = src
[0].u64
[1] + src
[1].u64
[1];
831 dst
->u64
[2] = src
[0].u64
[2] + src
[1].u64
[2];
832 dst
->u64
[3] = src
[0].u64
[3] + src
[1].u64
[3];
836 micro_u64mul(union tgsi_double_channel
*dst
,
837 const union tgsi_double_channel
*src
)
839 dst
->u64
[0] = src
[0].u64
[0] * src
[1].u64
[0];
840 dst
->u64
[1] = src
[0].u64
[1] * src
[1].u64
[1];
841 dst
->u64
[2] = src
[0].u64
[2] * src
[1].u64
[2];
842 dst
->u64
[3] = src
[0].u64
[3] * src
[1].u64
[3];
846 micro_u64div(union tgsi_double_channel
*dst
,
847 const union tgsi_double_channel
*src
)
849 dst
->u64
[0] = src
[1].u64
[0] ? src
[0].u64
[0] / src
[1].u64
[0] : ~0ull;
850 dst
->u64
[1] = src
[1].u64
[1] ? src
[0].u64
[1] / src
[1].u64
[1] : ~0ull;
851 dst
->u64
[2] = src
[1].u64
[2] ? src
[0].u64
[2] / src
[1].u64
[2] : ~0ull;
852 dst
->u64
[3] = src
[1].u64
[3] ? src
[0].u64
[3] / src
[1].u64
[3] : ~0ull;
856 micro_i64div(union tgsi_double_channel
*dst
,
857 const union tgsi_double_channel
*src
)
859 dst
->i64
[0] = src
[1].i64
[0] ? src
[0].i64
[0] / src
[1].i64
[0] : 0;
860 dst
->i64
[1] = src
[1].i64
[1] ? src
[0].i64
[1] / src
[1].i64
[1] : 0;
861 dst
->i64
[2] = src
[1].i64
[2] ? src
[0].i64
[2] / src
[1].i64
[2] : 0;
862 dst
->i64
[3] = src
[1].i64
[3] ? src
[0].i64
[3] / src
[1].i64
[3] : 0;
866 micro_u64mod(union tgsi_double_channel
*dst
,
867 const union tgsi_double_channel
*src
)
869 dst
->u64
[0] = src
[1].u64
[0] ? src
[0].u64
[0] % src
[1].u64
[0] : ~0ull;
870 dst
->u64
[1] = src
[1].u64
[1] ? src
[0].u64
[1] % src
[1].u64
[1] : ~0ull;
871 dst
->u64
[2] = src
[1].u64
[2] ? src
[0].u64
[2] % src
[1].u64
[2] : ~0ull;
872 dst
->u64
[3] = src
[1].u64
[3] ? src
[0].u64
[3] % src
[1].u64
[3] : ~0ull;
876 micro_i64mod(union tgsi_double_channel
*dst
,
877 const union tgsi_double_channel
*src
)
879 dst
->i64
[0] = src
[1].i64
[0] ? src
[0].i64
[0] % src
[1].i64
[0] : ~0ll;
880 dst
->i64
[1] = src
[1].i64
[1] ? src
[0].i64
[1] % src
[1].i64
[1] : ~0ll;
881 dst
->i64
[2] = src
[1].i64
[2] ? src
[0].i64
[2] % src
[1].i64
[2] : ~0ll;
882 dst
->i64
[3] = src
[1].i64
[3] ? src
[0].i64
[3] % src
[1].i64
[3] : ~0ll;
886 micro_u64shl(union tgsi_double_channel
*dst
,
887 const union tgsi_double_channel
*src0
,
888 union tgsi_exec_channel
*src1
)
890 unsigned masked_count
;
891 masked_count
= src1
->u
[0] & 0x3f;
892 dst
->u64
[0] = src0
->u64
[0] << masked_count
;
893 masked_count
= src1
->u
[1] & 0x3f;
894 dst
->u64
[1] = src0
->u64
[1] << masked_count
;
895 masked_count
= src1
->u
[2] & 0x3f;
896 dst
->u64
[2] = src0
->u64
[2] << masked_count
;
897 masked_count
= src1
->u
[3] & 0x3f;
898 dst
->u64
[3] = src0
->u64
[3] << masked_count
;
902 micro_i64shr(union tgsi_double_channel
*dst
,
903 const union tgsi_double_channel
*src0
,
904 union tgsi_exec_channel
*src1
)
906 unsigned masked_count
;
907 masked_count
= src1
->u
[0] & 0x3f;
908 dst
->i64
[0] = src0
->i64
[0] >> masked_count
;
909 masked_count
= src1
->u
[1] & 0x3f;
910 dst
->i64
[1] = src0
->i64
[1] >> masked_count
;
911 masked_count
= src1
->u
[2] & 0x3f;
912 dst
->i64
[2] = src0
->i64
[2] >> masked_count
;
913 masked_count
= src1
->u
[3] & 0x3f;
914 dst
->i64
[3] = src0
->i64
[3] >> masked_count
;
918 micro_u64shr(union tgsi_double_channel
*dst
,
919 const union tgsi_double_channel
*src0
,
920 union tgsi_exec_channel
*src1
)
922 unsigned masked_count
;
923 masked_count
= src1
->u
[0] & 0x3f;
924 dst
->u64
[0] = src0
->u64
[0] >> masked_count
;
925 masked_count
= src1
->u
[1] & 0x3f;
926 dst
->u64
[1] = src0
->u64
[1] >> masked_count
;
927 masked_count
= src1
->u
[2] & 0x3f;
928 dst
->u64
[2] = src0
->u64
[2] >> masked_count
;
929 masked_count
= src1
->u
[3] & 0x3f;
930 dst
->u64
[3] = src0
->u64
[3] >> masked_count
;
933 enum tgsi_exec_datatype
{
934 TGSI_EXEC_DATA_FLOAT
,
937 TGSI_EXEC_DATA_DOUBLE
,
938 TGSI_EXEC_DATA_INT64
,
939 TGSI_EXEC_DATA_UINT64
,
943 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
945 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
946 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
947 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
948 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
949 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
950 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
953 /** The execution mask depends on the conditional mask and the loop mask */
954 #define UPDATE_EXEC_MASK(MACH) \
955 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
958 static const union tgsi_exec_channel ZeroVec
=
959 { { 0.0, 0.0, 0.0, 0.0 } };
961 static const union tgsi_exec_channel OneVec
= {
962 {1.0f
, 1.0f
, 1.0f
, 1.0f
}
965 static const union tgsi_exec_channel P128Vec
= {
966 {128.0f
, 128.0f
, 128.0f
, 128.0f
}
969 static const union tgsi_exec_channel M128Vec
= {
970 {-128.0f
, -128.0f
, -128.0f
, -128.0f
}
975 * Assert that none of the float values in 'chan' are infinite or NaN.
976 * NaN and Inf may occur normally during program execution and should
977 * not lead to crashes, etc. But when debugging, it's helpful to catch
981 check_inf_or_nan(const union tgsi_exec_channel
*chan
)
983 assert(!util_is_inf_or_nan((chan
)->f
[0]));
984 assert(!util_is_inf_or_nan((chan
)->f
[1]));
985 assert(!util_is_inf_or_nan((chan
)->f
[2]));
986 assert(!util_is_inf_or_nan((chan
)->f
[3]));
992 print_chan(const char *msg
, const union tgsi_exec_channel
*chan
)
994 debug_printf("%s = {%f, %f, %f, %f}\n",
995 msg
, chan
->f
[0], chan
->f
[1], chan
->f
[2], chan
->f
[3]);
1002 print_temp(const struct tgsi_exec_machine
*mach
, uint index
)
1004 const struct tgsi_exec_vector
*tmp
= &mach
->Temps
[index
];
1006 debug_printf("Temp[%u] =\n", index
);
1007 for (i
= 0; i
< 4; i
++) {
1008 debug_printf(" %c: { %f, %f, %f, %f }\n",
1020 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine
*mach
,
1023 const unsigned *buf_sizes
)
1027 for (i
= 0; i
< num_bufs
; i
++) {
1028 mach
->Consts
[i
] = bufs
[i
];
1029 mach
->ConstsSize
[i
] = buf_sizes
[i
];
1035 * Check if there's a potential src/dst register data dependency when
1036 * using SOA execution.
1039 * This would expand into:
1044 * The second instruction will have the wrong value for t0 if executed as-is.
1047 tgsi_check_soa_dependencies(const struct tgsi_full_instruction
*inst
)
1051 uint writemask
= inst
->Dst
[0].Register
.WriteMask
;
1052 if (writemask
== TGSI_WRITEMASK_X
||
1053 writemask
== TGSI_WRITEMASK_Y
||
1054 writemask
== TGSI_WRITEMASK_Z
||
1055 writemask
== TGSI_WRITEMASK_W
||
1056 writemask
== TGSI_WRITEMASK_NONE
) {
1057 /* no chance of data dependency */
1061 /* loop over src regs */
1062 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1063 if ((inst
->Src
[i
].Register
.File
==
1064 inst
->Dst
[0].Register
.File
) &&
1065 ((inst
->Src
[i
].Register
.Index
==
1066 inst
->Dst
[0].Register
.Index
) ||
1067 inst
->Src
[i
].Register
.Indirect
||
1068 inst
->Dst
[0].Register
.Indirect
)) {
1069 /* loop over dest channels */
1070 uint channelsWritten
= 0x0;
1071 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1072 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
1073 /* check if we're reading a channel that's been written */
1074 uint swizzle
= tgsi_util_get_full_src_register_swizzle(&inst
->Src
[i
], chan
);
1075 if (channelsWritten
& (1 << swizzle
)) {
1079 channelsWritten
|= (1 << chan
);
1089 * Initialize machine state by expanding tokens to full instructions,
1090 * allocating temporary storage, setting up constants, etc.
1091 * After this, we can call tgsi_exec_machine_run() many times.
1094 tgsi_exec_machine_bind_shader(
1095 struct tgsi_exec_machine
*mach
,
1096 const struct tgsi_token
*tokens
,
1097 struct tgsi_sampler
*sampler
,
1098 struct tgsi_image
*image
,
1099 struct tgsi_buffer
*buffer
)
1102 struct tgsi_parse_context parse
;
1103 struct tgsi_full_instruction
*instructions
;
1104 struct tgsi_full_declaration
*declarations
;
1105 uint maxInstructions
= 10, numInstructions
= 0;
1106 uint maxDeclarations
= 10, numDeclarations
= 0;
1109 tgsi_dump(tokens
, 0);
1115 mach
->Tokens
= tokens
;
1116 mach
->Sampler
= sampler
;
1117 mach
->Image
= image
;
1118 mach
->Buffer
= buffer
;
1121 /* unbind and free all */
1122 FREE(mach
->Declarations
);
1123 mach
->Declarations
= NULL
;
1124 mach
->NumDeclarations
= 0;
1126 FREE(mach
->Instructions
);
1127 mach
->Instructions
= NULL
;
1128 mach
->NumInstructions
= 0;
1133 k
= tgsi_parse_init (&parse
, mach
->Tokens
);
1134 if (k
!= TGSI_PARSE_OK
) {
1135 debug_printf( "Problem parsing!\n" );
1140 mach
->NumOutputs
= 0;
1142 for (k
= 0; k
< TGSI_SEMANTIC_COUNT
; k
++)
1143 mach
->SysSemanticToIndex
[k
] = -1;
1145 if (mach
->ShaderType
== PIPE_SHADER_GEOMETRY
&&
1146 !mach
->UsedGeometryShader
) {
1147 struct tgsi_exec_vector
*inputs
;
1148 struct tgsi_exec_vector
*outputs
;
1150 inputs
= align_malloc(sizeof(struct tgsi_exec_vector
) *
1151 TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_SHADER_INPUTS
,
1157 outputs
= align_malloc(sizeof(struct tgsi_exec_vector
) *
1158 TGSI_MAX_TOTAL_VERTICES
, 16);
1165 align_free(mach
->Inputs
);
1166 align_free(mach
->Outputs
);
1168 mach
->Inputs
= inputs
;
1169 mach
->Outputs
= outputs
;
1170 mach
->UsedGeometryShader
= TRUE
;
1173 declarations
= (struct tgsi_full_declaration
*)
1174 MALLOC( maxDeclarations
* sizeof(struct tgsi_full_declaration
) );
1176 if (!declarations
) {
1180 instructions
= (struct tgsi_full_instruction
*)
1181 MALLOC( maxInstructions
* sizeof(struct tgsi_full_instruction
) );
1183 if (!instructions
) {
1184 FREE( declarations
);
1188 while( !tgsi_parse_end_of_tokens( &parse
) ) {
1191 tgsi_parse_token( &parse
);
1192 switch( parse
.FullToken
.Token
.Type
) {
1193 case TGSI_TOKEN_TYPE_DECLARATION
:
1194 /* save expanded declaration */
1195 if (numDeclarations
== maxDeclarations
) {
1196 declarations
= REALLOC(declarations
,
1198 * sizeof(struct tgsi_full_declaration
),
1199 (maxDeclarations
+ 10)
1200 * sizeof(struct tgsi_full_declaration
));
1201 maxDeclarations
+= 10;
1203 if (parse
.FullToken
.FullDeclaration
.Declaration
.File
== TGSI_FILE_OUTPUT
) {
1205 for (reg
= parse
.FullToken
.FullDeclaration
.Range
.First
;
1206 reg
<= parse
.FullToken
.FullDeclaration
.Range
.Last
;
1211 else if (parse
.FullToken
.FullDeclaration
.Declaration
.File
== TGSI_FILE_SYSTEM_VALUE
) {
1212 const struct tgsi_full_declaration
*decl
= &parse
.FullToken
.FullDeclaration
;
1213 mach
->SysSemanticToIndex
[decl
->Semantic
.Name
] = decl
->Range
.First
;
1216 memcpy(declarations
+ numDeclarations
,
1217 &parse
.FullToken
.FullDeclaration
,
1218 sizeof(declarations
[0]));
1222 case TGSI_TOKEN_TYPE_IMMEDIATE
:
1224 uint size
= parse
.FullToken
.FullImmediate
.Immediate
.NrTokens
- 1;
1225 assert( size
<= 4 );
1226 if (mach
->ImmLimit
>= mach
->ImmsReserved
) {
1227 unsigned newReserved
= mach
->ImmsReserved
? 2 * mach
->ImmsReserved
: 128;
1228 float4
*imms
= REALLOC(mach
->Imms
, mach
->ImmsReserved
, newReserved
* sizeof(float4
));
1230 mach
->ImmsReserved
= newReserved
;
1233 debug_printf("Unable to (re)allocate space for immidiate constants\n");
1238 for( i
= 0; i
< size
; i
++ ) {
1239 mach
->Imms
[mach
->ImmLimit
][i
] =
1240 parse
.FullToken
.FullImmediate
.u
[i
].Float
;
1242 mach
->ImmLimit
+= 1;
1246 case TGSI_TOKEN_TYPE_INSTRUCTION
:
1248 /* save expanded instruction */
1249 if (numInstructions
== maxInstructions
) {
1250 instructions
= REALLOC(instructions
,
1252 * sizeof(struct tgsi_full_instruction
),
1253 (maxInstructions
+ 10)
1254 * sizeof(struct tgsi_full_instruction
));
1255 maxInstructions
+= 10;
1258 memcpy(instructions
+ numInstructions
,
1259 &parse
.FullToken
.FullInstruction
,
1260 sizeof(instructions
[0]));
1265 case TGSI_TOKEN_TYPE_PROPERTY
:
1266 if (mach
->ShaderType
== PIPE_SHADER_GEOMETRY
) {
1267 if (parse
.FullToken
.FullProperty
.Property
.PropertyName
== TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
) {
1268 mach
->MaxOutputVertices
= parse
.FullToken
.FullProperty
.u
[0].Data
;
1277 tgsi_parse_free (&parse
);
1279 FREE(mach
->Declarations
);
1280 mach
->Declarations
= declarations
;
1281 mach
->NumDeclarations
= numDeclarations
;
1283 FREE(mach
->Instructions
);
1284 mach
->Instructions
= instructions
;
1285 mach
->NumInstructions
= numInstructions
;
1289 struct tgsi_exec_machine
*
1290 tgsi_exec_machine_create(enum pipe_shader_type shader_type
)
1292 struct tgsi_exec_machine
*mach
;
1295 mach
= align_malloc( sizeof *mach
, 16 );
1299 memset(mach
, 0, sizeof(*mach
));
1301 mach
->ShaderType
= shader_type
;
1302 mach
->Addrs
= &mach
->Temps
[TGSI_EXEC_TEMP_ADDR
];
1303 mach
->MaxGeometryShaderOutputs
= TGSI_MAX_TOTAL_VERTICES
;
1305 if (shader_type
!= PIPE_SHADER_COMPUTE
) {
1306 mach
->Inputs
= align_malloc(sizeof(struct tgsi_exec_vector
) * PIPE_MAX_SHADER_INPUTS
, 16);
1307 mach
->Outputs
= align_malloc(sizeof(struct tgsi_exec_vector
) * PIPE_MAX_SHADER_OUTPUTS
, 16);
1308 if (!mach
->Inputs
|| !mach
->Outputs
)
1312 /* Setup constants needed by the SSE2 executor. */
1313 for( i
= 0; i
< 4; i
++ ) {
1314 mach
->Temps
[TGSI_EXEC_TEMP_00000000_I
].xyzw
[TGSI_EXEC_TEMP_00000000_C
].u
[i
] = 0x00000000;
1315 mach
->Temps
[TGSI_EXEC_TEMP_7FFFFFFF_I
].xyzw
[TGSI_EXEC_TEMP_7FFFFFFF_C
].u
[i
] = 0x7FFFFFFF;
1316 mach
->Temps
[TGSI_EXEC_TEMP_80000000_I
].xyzw
[TGSI_EXEC_TEMP_80000000_C
].u
[i
] = 0x80000000;
1317 mach
->Temps
[TGSI_EXEC_TEMP_FFFFFFFF_I
].xyzw
[TGSI_EXEC_TEMP_FFFFFFFF_C
].u
[i
] = 0xFFFFFFFF; /* not used */
1318 mach
->Temps
[TGSI_EXEC_TEMP_ONE_I
].xyzw
[TGSI_EXEC_TEMP_ONE_C
].f
[i
] = 1.0f
;
1319 mach
->Temps
[TGSI_EXEC_TEMP_TWO_I
].xyzw
[TGSI_EXEC_TEMP_TWO_C
].f
[i
] = 2.0f
; /* not used */
1320 mach
->Temps
[TGSI_EXEC_TEMP_128_I
].xyzw
[TGSI_EXEC_TEMP_128_C
].f
[i
] = 128.0f
;
1321 mach
->Temps
[TGSI_EXEC_TEMP_MINUS_128_I
].xyzw
[TGSI_EXEC_TEMP_MINUS_128_C
].f
[i
] = -128.0f
;
1322 mach
->Temps
[TGSI_EXEC_TEMP_THREE_I
].xyzw
[TGSI_EXEC_TEMP_THREE_C
].f
[i
] = 3.0f
;
1323 mach
->Temps
[TGSI_EXEC_TEMP_HALF_I
].xyzw
[TGSI_EXEC_TEMP_HALF_C
].f
[i
] = 0.5f
;
1327 /* silence warnings */
1336 align_free(mach
->Inputs
);
1337 align_free(mach
->Outputs
);
1345 tgsi_exec_machine_destroy(struct tgsi_exec_machine
*mach
)
1348 FREE(mach
->Instructions
);
1349 FREE(mach
->Declarations
);
1352 align_free(mach
->Inputs
);
1353 align_free(mach
->Outputs
);
1360 micro_add(union tgsi_exec_channel
*dst
,
1361 const union tgsi_exec_channel
*src0
,
1362 const union tgsi_exec_channel
*src1
)
1364 dst
->f
[0] = src0
->f
[0] + src1
->f
[0];
1365 dst
->f
[1] = src0
->f
[1] + src1
->f
[1];
1366 dst
->f
[2] = src0
->f
[2] + src1
->f
[2];
1367 dst
->f
[3] = src0
->f
[3] + src1
->f
[3];
1372 union tgsi_exec_channel
*dst
,
1373 const union tgsi_exec_channel
*src0
,
1374 const union tgsi_exec_channel
*src1
)
1376 if (src1
->f
[0] != 0) {
1377 dst
->f
[0] = src0
->f
[0] / src1
->f
[0];
1379 if (src1
->f
[1] != 0) {
1380 dst
->f
[1] = src0
->f
[1] / src1
->f
[1];
1382 if (src1
->f
[2] != 0) {
1383 dst
->f
[2] = src0
->f
[2] / src1
->f
[2];
1385 if (src1
->f
[3] != 0) {
1386 dst
->f
[3] = src0
->f
[3] / src1
->f
[3];
1392 union tgsi_exec_channel
*dst
,
1393 const union tgsi_exec_channel
*src0
,
1394 const union tgsi_exec_channel
*src1
,
1395 const union tgsi_exec_channel
*src2
,
1396 const union tgsi_exec_channel
*src3
)
1398 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src2
->f
[0] : src3
->f
[0];
1399 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src2
->f
[1] : src3
->f
[1];
1400 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src2
->f
[2] : src3
->f
[2];
1401 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src2
->f
[3] : src3
->f
[3];
1405 micro_max(union tgsi_exec_channel
*dst
,
1406 const union tgsi_exec_channel
*src0
,
1407 const union tgsi_exec_channel
*src1
)
1409 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
1410 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
1411 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
1412 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
1416 micro_min(union tgsi_exec_channel
*dst
,
1417 const union tgsi_exec_channel
*src0
,
1418 const union tgsi_exec_channel
*src1
)
1420 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
1421 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
1422 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
1423 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
1427 micro_mul(union tgsi_exec_channel
*dst
,
1428 const union tgsi_exec_channel
*src0
,
1429 const union tgsi_exec_channel
*src1
)
1431 dst
->f
[0] = src0
->f
[0] * src1
->f
[0];
1432 dst
->f
[1] = src0
->f
[1] * src1
->f
[1];
1433 dst
->f
[2] = src0
->f
[2] * src1
->f
[2];
1434 dst
->f
[3] = src0
->f
[3] * src1
->f
[3];
1439 union tgsi_exec_channel
*dst
,
1440 const union tgsi_exec_channel
*src
)
1442 dst
->f
[0] = -src
->f
[0];
1443 dst
->f
[1] = -src
->f
[1];
1444 dst
->f
[2] = -src
->f
[2];
1445 dst
->f
[3] = -src
->f
[3];
1450 union tgsi_exec_channel
*dst
,
1451 const union tgsi_exec_channel
*src0
,
1452 const union tgsi_exec_channel
*src1
)
1455 dst
->f
[0] = util_fast_pow( src0
->f
[0], src1
->f
[0] );
1456 dst
->f
[1] = util_fast_pow( src0
->f
[1], src1
->f
[1] );
1457 dst
->f
[2] = util_fast_pow( src0
->f
[2], src1
->f
[2] );
1458 dst
->f
[3] = util_fast_pow( src0
->f
[3], src1
->f
[3] );
1460 dst
->f
[0] = powf( src0
->f
[0], src1
->f
[0] );
1461 dst
->f
[1] = powf( src0
->f
[1], src1
->f
[1] );
1462 dst
->f
[2] = powf( src0
->f
[2], src1
->f
[2] );
1463 dst
->f
[3] = powf( src0
->f
[3], src1
->f
[3] );
1468 micro_ldexp(union tgsi_exec_channel
*dst
,
1469 const union tgsi_exec_channel
*src0
,
1470 const union tgsi_exec_channel
*src1
)
1472 dst
->f
[0] = ldexpf(src0
->f
[0], src1
->i
[0]);
1473 dst
->f
[1] = ldexpf(src0
->f
[1], src1
->i
[1]);
1474 dst
->f
[2] = ldexpf(src0
->f
[2], src1
->i
[2]);
1475 dst
->f
[3] = ldexpf(src0
->f
[3], src1
->i
[3]);
1479 micro_sub(union tgsi_exec_channel
*dst
,
1480 const union tgsi_exec_channel
*src0
,
1481 const union tgsi_exec_channel
*src1
)
1483 dst
->f
[0] = src0
->f
[0] - src1
->f
[0];
1484 dst
->f
[1] = src0
->f
[1] - src1
->f
[1];
1485 dst
->f
[2] = src0
->f
[2] - src1
->f
[2];
1486 dst
->f
[3] = src0
->f
[3] - src1
->f
[3];
1490 fetch_src_file_channel(const struct tgsi_exec_machine
*mach
,
1493 const union tgsi_exec_channel
*index
,
1494 const union tgsi_exec_channel
*index2D
,
1495 union tgsi_exec_channel
*chan
)
1499 assert(swizzle
< 4);
1502 case TGSI_FILE_CONSTANT
:
1503 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1504 assert(index2D
->i
[i
] >= 0 && index2D
->i
[i
] < PIPE_MAX_CONSTANT_BUFFERS
);
1505 assert(mach
->Consts
[index2D
->i
[i
]]);
1507 if (index
->i
[i
] < 0) {
1510 /* NOTE: copying the const value as a uint instead of float */
1511 const uint constbuf
= index2D
->i
[i
];
1512 const uint
*buf
= (const uint
*)mach
->Consts
[constbuf
];
1513 const int pos
= index
->i
[i
] * 4 + swizzle
;
1514 /* const buffer bounds check */
1515 if (pos
< 0 || pos
>= (int) mach
->ConstsSize
[constbuf
]) {
1517 /* Debug: print warning */
1518 static int count
= 0;
1520 debug_printf("TGSI Exec: const buffer index %d"
1521 " out of bounds\n", pos
);
1526 chan
->u
[i
] = buf
[pos
];
1531 case TGSI_FILE_INPUT
:
1532 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1534 if (PIPE_SHADER_GEOMETRY == mach->ShaderType) {
1535 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1536 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1537 index2D->i[i], index->i[i]);
1539 int pos
= index2D
->i
[i
] * TGSI_EXEC_MAX_INPUT_ATTRIBS
+ index
->i
[i
];
1541 assert(pos
< TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_ATTRIBS
);
1542 chan
->u
[i
] = mach
->Inputs
[pos
].xyzw
[swizzle
].u
[i
];
1546 case TGSI_FILE_SYSTEM_VALUE
:
1547 /* XXX no swizzling at this point. Will be needed if we put
1548 * gl_FragCoord, for example, in a sys value register.
1550 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1551 chan
->u
[i
] = mach
->SystemValue
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1555 case TGSI_FILE_TEMPORARY
:
1556 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1557 assert(index
->i
[i
] < TGSI_EXEC_NUM_TEMPS
);
1558 assert(index2D
->i
[i
] == 0);
1560 chan
->u
[i
] = mach
->Temps
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1564 case TGSI_FILE_IMMEDIATE
:
1565 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1566 assert(index
->i
[i
] >= 0 && index
->i
[i
] < (int)mach
->ImmLimit
);
1567 assert(index2D
->i
[i
] == 0);
1569 chan
->f
[i
] = mach
->Imms
[index
->i
[i
]][swizzle
];
1573 case TGSI_FILE_ADDRESS
:
1574 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1575 assert(index
->i
[i
] >= 0);
1576 assert(index2D
->i
[i
] == 0);
1578 chan
->u
[i
] = mach
->Addrs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1582 case TGSI_FILE_OUTPUT
:
1583 /* vertex/fragment output vars can be read too */
1584 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1585 assert(index
->i
[i
] >= 0);
1586 assert(index2D
->i
[i
] == 0);
1588 chan
->u
[i
] = mach
->Outputs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1594 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1601 fetch_source_d(const struct tgsi_exec_machine
*mach
,
1602 union tgsi_exec_channel
*chan
,
1603 const struct tgsi_full_src_register
*reg
,
1604 const uint chan_index
)
1606 union tgsi_exec_channel index
;
1607 union tgsi_exec_channel index2D
;
1610 /* We start with a direct index into a register file.
1614 * file = Register.File
1615 * [1] = Register.Index
1620 index
.i
[3] = reg
->Register
.Index
;
1622 /* There is an extra source register that indirectly subscripts
1623 * a register file. The direct index now becomes an offset
1624 * that is being added to the indirect register.
1628 * ind = Indirect.File
1629 * [2] = Indirect.Index
1630 * .x = Indirect.SwizzleX
1632 if (reg
->Register
.Indirect
) {
1633 union tgsi_exec_channel index2
;
1634 union tgsi_exec_channel indir_index
;
1635 const uint execmask
= mach
->ExecMask
;
1638 /* which address register (always zero now) */
1642 index2
.i
[3] = reg
->Indirect
.Index
;
1643 /* get current value of address register[swizzle] */
1644 swizzle
= reg
->Indirect
.Swizzle
;
1645 fetch_src_file_channel(mach
,
1652 /* add value of address register to the offset */
1653 index
.i
[0] += indir_index
.i
[0];
1654 index
.i
[1] += indir_index
.i
[1];
1655 index
.i
[2] += indir_index
.i
[2];
1656 index
.i
[3] += indir_index
.i
[3];
1658 /* for disabled execution channels, zero-out the index to
1659 * avoid using a potential garbage value.
1661 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1662 if ((execmask
& (1 << i
)) == 0)
1667 /* There is an extra source register that is a second
1668 * subscript to a register file. Effectively it means that
1669 * the register file is actually a 2D array of registers.
1673 * [3] = Dimension.Index
1675 if (reg
->Register
.Dimension
) {
1679 index2D
.i
[3] = reg
->Dimension
.Index
;
1681 /* Again, the second subscript index can be addressed indirectly
1682 * identically to the first one.
1683 * Nothing stops us from indirectly addressing the indirect register,
1684 * but there is no need for that, so we won't exercise it.
1686 * file[ind[4].y+3][1],
1688 * ind = DimIndirect.File
1689 * [4] = DimIndirect.Index
1690 * .y = DimIndirect.SwizzleX
1692 if (reg
->Dimension
.Indirect
) {
1693 union tgsi_exec_channel index2
;
1694 union tgsi_exec_channel indir_index
;
1695 const uint execmask
= mach
->ExecMask
;
1701 index2
.i
[3] = reg
->DimIndirect
.Index
;
1703 swizzle
= reg
->DimIndirect
.Swizzle
;
1704 fetch_src_file_channel(mach
,
1705 reg
->DimIndirect
.File
,
1711 index2D
.i
[0] += indir_index
.i
[0];
1712 index2D
.i
[1] += indir_index
.i
[1];
1713 index2D
.i
[2] += indir_index
.i
[2];
1714 index2D
.i
[3] += indir_index
.i
[3];
1716 /* for disabled execution channels, zero-out the index to
1717 * avoid using a potential garbage value.
1719 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1720 if ((execmask
& (1 << i
)) == 0) {
1726 /* If by any chance there was a need for a 3D array of register
1727 * files, we would have to check whether Dimension is followed
1728 * by a dimension register and continue the saga.
1737 swizzle
= tgsi_util_get_full_src_register_swizzle( reg
, chan_index
);
1738 fetch_src_file_channel(mach
,
1747 fetch_source(const struct tgsi_exec_machine
*mach
,
1748 union tgsi_exec_channel
*chan
,
1749 const struct tgsi_full_src_register
*reg
,
1750 const uint chan_index
,
1751 enum tgsi_exec_datatype src_datatype
)
1753 fetch_source_d(mach
, chan
, reg
, chan_index
);
1755 if (reg
->Register
.Absolute
) {
1756 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1757 micro_abs(chan
, chan
);
1759 micro_iabs(chan
, chan
);
1763 if (reg
->Register
.Negate
) {
1764 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1765 micro_neg(chan
, chan
);
1767 micro_ineg(chan
, chan
);
1772 static union tgsi_exec_channel
*
1773 store_dest_dstret(struct tgsi_exec_machine
*mach
,
1774 const union tgsi_exec_channel
*chan
,
1775 const struct tgsi_full_dst_register
*reg
,
1777 enum tgsi_exec_datatype dst_datatype
)
1779 static union tgsi_exec_channel null
;
1780 union tgsi_exec_channel
*dst
;
1781 union tgsi_exec_channel index2D
;
1782 int offset
= 0; /* indirection offset */
1786 if (0 && dst_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1787 check_inf_or_nan(chan
);
1790 /* There is an extra source register that indirectly subscripts
1791 * a register file. The direct index now becomes an offset
1792 * that is being added to the indirect register.
1796 * ind = Indirect.File
1797 * [2] = Indirect.Index
1798 * .x = Indirect.SwizzleX
1800 if (reg
->Register
.Indirect
) {
1801 union tgsi_exec_channel index
;
1802 union tgsi_exec_channel indir_index
;
1805 /* which address register (always zero for now) */
1809 index
.i
[3] = reg
->Indirect
.Index
;
1811 /* get current value of address register[swizzle] */
1812 swizzle
= reg
->Indirect
.Swizzle
;
1814 /* fetch values from the address/indirection register */
1815 fetch_src_file_channel(mach
,
1822 /* save indirection offset */
1823 offset
= indir_index
.i
[0];
1826 /* There is an extra source register that is a second
1827 * subscript to a register file. Effectively it means that
1828 * the register file is actually a 2D array of registers.
1832 * [3] = Dimension.Index
1834 if (reg
->Register
.Dimension
) {
1838 index2D
.i
[3] = reg
->Dimension
.Index
;
1840 /* Again, the second subscript index can be addressed indirectly
1841 * identically to the first one.
1842 * Nothing stops us from indirectly addressing the indirect register,
1843 * but there is no need for that, so we won't exercise it.
1845 * file[ind[4].y+3][1],
1847 * ind = DimIndirect.File
1848 * [4] = DimIndirect.Index
1849 * .y = DimIndirect.SwizzleX
1851 if (reg
->Dimension
.Indirect
) {
1852 union tgsi_exec_channel index2
;
1853 union tgsi_exec_channel indir_index
;
1854 const uint execmask
= mach
->ExecMask
;
1861 index2
.i
[3] = reg
->DimIndirect
.Index
;
1863 swizzle
= reg
->DimIndirect
.Swizzle
;
1864 fetch_src_file_channel(mach
,
1865 reg
->DimIndirect
.File
,
1871 index2D
.i
[0] += indir_index
.i
[0];
1872 index2D
.i
[1] += indir_index
.i
[1];
1873 index2D
.i
[2] += indir_index
.i
[2];
1874 index2D
.i
[3] += indir_index
.i
[3];
1876 /* for disabled execution channels, zero-out the index to
1877 * avoid using a potential garbage value.
1879 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1880 if ((execmask
& (1 << i
)) == 0) {
1886 /* If by any chance there was a need for a 3D array of register
1887 * files, we would have to check whether Dimension is followed
1888 * by a dimension register and continue the saga.
1897 switch (reg
->Register
.File
) {
1898 case TGSI_FILE_NULL
:
1902 case TGSI_FILE_OUTPUT
:
1903 index
= mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0]
1904 + reg
->Register
.Index
;
1905 dst
= &mach
->Outputs
[offset
+ index
].xyzw
[chan_index
];
1907 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1908 mach
->NumOutputs
, mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0],
1909 reg
->Register
.Index
);
1910 if (PIPE_SHADER_GEOMETRY
== mach
->ShaderType
) {
1911 debug_printf("STORING OUT[%d] mask(%d), = (", offset
+ index
, execmask
);
1912 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1913 if (execmask
& (1 << i
))
1914 debug_printf("%f, ", chan
->f
[i
]);
1915 debug_printf(")\n");
1920 case TGSI_FILE_TEMPORARY
:
1921 index
= reg
->Register
.Index
;
1922 assert( index
< TGSI_EXEC_NUM_TEMPS
);
1923 dst
= &mach
->Temps
[offset
+ index
].xyzw
[chan_index
];
1926 case TGSI_FILE_ADDRESS
:
1927 index
= reg
->Register
.Index
;
1928 dst
= &mach
->Addrs
[index
].xyzw
[chan_index
];
1940 store_dest_double(struct tgsi_exec_machine
*mach
,
1941 const union tgsi_exec_channel
*chan
,
1942 const struct tgsi_full_dst_register
*reg
,
1944 enum tgsi_exec_datatype dst_datatype
)
1946 union tgsi_exec_channel
*dst
;
1947 const uint execmask
= mach
->ExecMask
;
1950 dst
= store_dest_dstret(mach
, chan
, reg
, chan_index
, dst_datatype
);
1955 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1956 if (execmask
& (1 << i
))
1957 dst
->i
[i
] = chan
->i
[i
];
1961 store_dest(struct tgsi_exec_machine
*mach
,
1962 const union tgsi_exec_channel
*chan
,
1963 const struct tgsi_full_dst_register
*reg
,
1964 const struct tgsi_full_instruction
*inst
,
1966 enum tgsi_exec_datatype dst_datatype
)
1968 union tgsi_exec_channel
*dst
;
1969 const uint execmask
= mach
->ExecMask
;
1972 dst
= store_dest_dstret(mach
, chan
, reg
, chan_index
, dst_datatype
);
1976 if (!inst
->Instruction
.Saturate
) {
1977 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1978 if (execmask
& (1 << i
))
1979 dst
->i
[i
] = chan
->i
[i
];
1982 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1983 if (execmask
& (1 << i
)) {
1984 if (chan
->f
[i
] < 0.0f
)
1986 else if (chan
->f
[i
] > 1.0f
)
1989 dst
->i
[i
] = chan
->i
[i
];
1994 #define FETCH(VAL,INDEX,CHAN)\
1995 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1997 #define IFETCH(VAL,INDEX,CHAN)\
1998 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
2002 * Execute ARB-style KIL which is predicated by a src register.
2003 * Kill fragment if any of the four values is less than zero.
2006 exec_kill_if(struct tgsi_exec_machine
*mach
,
2007 const struct tgsi_full_instruction
*inst
)
2011 uint kilmask
= 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
2012 union tgsi_exec_channel r
[1];
2014 /* This mask stores component bits that were already tested. */
2017 for (chan_index
= 0; chan_index
< 4; chan_index
++)
2022 /* unswizzle channel */
2023 swizzle
= tgsi_util_get_full_src_register_swizzle (
2027 /* check if the component has not been already tested */
2028 if (uniquemask
& (1 << swizzle
))
2030 uniquemask
|= 1 << swizzle
;
2032 FETCH(&r
[0], 0, chan_index
);
2033 for (i
= 0; i
< 4; i
++)
2034 if (r
[0].f
[i
] < 0.0f
)
2038 /* restrict to fragments currently executing */
2039 kilmask
&= mach
->ExecMask
;
2041 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
2045 * Unconditional fragment kill/discard.
2048 exec_kill(struct tgsi_exec_machine
*mach
)
2050 uint kilmask
; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
2052 /* kill fragment for all fragments currently executing */
2053 kilmask
= mach
->ExecMask
;
2054 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
2058 emit_vertex(struct tgsi_exec_machine
*mach
)
2060 /* FIXME: check for exec mask correctly
2062 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
2063 if ((mach->ExecMask & (1 << i)))
2065 if (mach
->ExecMask
) {
2066 if (mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]] >= mach
->MaxOutputVertices
)
2069 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] += mach
->NumOutputs
;
2070 mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]]++;
2075 emit_primitive(struct tgsi_exec_machine
*mach
)
2077 unsigned *prim_count
= &mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0];
2078 /* FIXME: check for exec mask correctly
2080 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
2081 if ((mach->ExecMask & (1 << i)))
2083 if (mach
->ExecMask
) {
2085 debug_assert((*prim_count
* mach
->NumOutputs
) < mach
->MaxGeometryShaderOutputs
);
2086 mach
->Primitives
[*prim_count
] = 0;
2091 conditional_emit_primitive(struct tgsi_exec_machine
*mach
)
2093 if (PIPE_SHADER_GEOMETRY
== mach
->ShaderType
) {
2095 mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]];
2096 if (emitted_verts
) {
2097 emit_primitive(mach
);
2104 * Fetch four texture samples using STR texture coordinates.
2107 fetch_texel( struct tgsi_sampler
*sampler
,
2108 const unsigned sview_idx
,
2109 const unsigned sampler_idx
,
2110 const union tgsi_exec_channel
*s
,
2111 const union tgsi_exec_channel
*t
,
2112 const union tgsi_exec_channel
*p
,
2113 const union tgsi_exec_channel
*c0
,
2114 const union tgsi_exec_channel
*c1
,
2115 float derivs
[3][2][TGSI_QUAD_SIZE
],
2116 const int8_t offset
[3],
2117 enum tgsi_sampler_control control
,
2118 union tgsi_exec_channel
*r
,
2119 union tgsi_exec_channel
*g
,
2120 union tgsi_exec_channel
*b
,
2121 union tgsi_exec_channel
*a
)
2124 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
2126 /* FIXME: handle explicit derivs, offsets */
2127 sampler
->get_samples(sampler
, sview_idx
, sampler_idx
,
2128 s
->f
, t
->f
, p
->f
, c0
->f
, c1
->f
, derivs
, offset
, control
, rgba
);
2130 for (j
= 0; j
< 4; j
++) {
2131 r
->f
[j
] = rgba
[0][j
];
2132 g
->f
[j
] = rgba
[1][j
];
2133 b
->f
[j
] = rgba
[2][j
];
2134 a
->f
[j
] = rgba
[3][j
];
2139 #define TEX_MODIFIER_NONE 0
2140 #define TEX_MODIFIER_PROJECTED 1
2141 #define TEX_MODIFIER_LOD_BIAS 2
2142 #define TEX_MODIFIER_EXPLICIT_LOD 3
2143 #define TEX_MODIFIER_LEVEL_ZERO 4
2144 #define TEX_MODIFIER_GATHER 5
2147 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
2150 fetch_texel_offsets(struct tgsi_exec_machine
*mach
,
2151 const struct tgsi_full_instruction
*inst
,
2154 if (inst
->Texture
.NumOffsets
== 1) {
2155 union tgsi_exec_channel index
;
2156 union tgsi_exec_channel offset
[3];
2157 index
.i
[0] = index
.i
[1] = index
.i
[2] = index
.i
[3] = inst
->TexOffsets
[0].Index
;
2158 fetch_src_file_channel(mach
, inst
->TexOffsets
[0].File
,
2159 inst
->TexOffsets
[0].SwizzleX
, &index
, &ZeroVec
, &offset
[0]);
2160 fetch_src_file_channel(mach
, inst
->TexOffsets
[0].File
,
2161 inst
->TexOffsets
[0].SwizzleY
, &index
, &ZeroVec
, &offset
[1]);
2162 fetch_src_file_channel(mach
, inst
->TexOffsets
[0].File
,
2163 inst
->TexOffsets
[0].SwizzleZ
, &index
, &ZeroVec
, &offset
[2]);
2164 offsets
[0] = offset
[0].i
[0];
2165 offsets
[1] = offset
[1].i
[0];
2166 offsets
[2] = offset
[2].i
[0];
2168 assert(inst
->Texture
.NumOffsets
== 0);
2169 offsets
[0] = offsets
[1] = offsets
[2] = 0;
2175 * Fetch dx and dy values for one channel (s, t or r).
2176 * Put dx values into one float array, dy values into another.
2179 fetch_assign_deriv_channel(struct tgsi_exec_machine
*mach
,
2180 const struct tgsi_full_instruction
*inst
,
2183 float derivs
[2][TGSI_QUAD_SIZE
])
2185 union tgsi_exec_channel d
;
2186 FETCH(&d
, regdsrcx
, chan
);
2187 derivs
[0][0] = d
.f
[0];
2188 derivs
[0][1] = d
.f
[1];
2189 derivs
[0][2] = d
.f
[2];
2190 derivs
[0][3] = d
.f
[3];
2191 FETCH(&d
, regdsrcx
+ 1, chan
);
2192 derivs
[1][0] = d
.f
[0];
2193 derivs
[1][1] = d
.f
[1];
2194 derivs
[1][2] = d
.f
[2];
2195 derivs
[1][3] = d
.f
[3];
2199 fetch_sampler_unit(struct tgsi_exec_machine
*mach
,
2200 const struct tgsi_full_instruction
*inst
,
2205 if (inst
->Src
[sampler
].Register
.Indirect
) {
2206 const struct tgsi_full_src_register
*reg
= &inst
->Src
[sampler
];
2207 union tgsi_exec_channel indir_index
, index2
;
2208 const uint execmask
= mach
->ExecMask
;
2212 index2
.i
[3] = reg
->Indirect
.Index
;
2214 fetch_src_file_channel(mach
,
2216 reg
->Indirect
.Swizzle
,
2220 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2221 if (execmask
& (1 << i
)) {
2222 unit
= inst
->Src
[sampler
].Register
.Index
+ indir_index
.i
[i
];
2228 unit
= inst
->Src
[sampler
].Register
.Index
;
2234 * execute a texture instruction.
2236 * modifier is used to control the channel routing for the
2237 * instruction variants like proj, lod, and texture with lod bias.
2238 * sampler indicates which src register the sampler is contained in.
2241 exec_tex(struct tgsi_exec_machine
*mach
,
2242 const struct tgsi_full_instruction
*inst
,
2243 uint modifier
, uint sampler
)
2245 const union tgsi_exec_channel
*args
[5], *proj
= NULL
;
2246 union tgsi_exec_channel r
[5];
2247 enum tgsi_sampler_control control
= TGSI_SAMPLER_LOD_NONE
;
2251 int dim
, shadow_ref
, i
;
2253 unit
= fetch_sampler_unit(mach
, inst
, sampler
);
2254 /* always fetch all 3 offsets, overkill but keeps code simple */
2255 fetch_texel_offsets(mach
, inst
, offsets
);
2257 assert(modifier
!= TEX_MODIFIER_LEVEL_ZERO
);
2258 assert(inst
->Texture
.Texture
!= TGSI_TEXTURE_BUFFER
);
2260 dim
= tgsi_util_get_texture_coord_dim(inst
->Texture
.Texture
);
2261 shadow_ref
= tgsi_util_get_shadow_ref_src_index(inst
->Texture
.Texture
);
2264 if (shadow_ref
>= 0)
2265 assert(shadow_ref
>= dim
&& shadow_ref
< (int)ARRAY_SIZE(args
));
2267 /* fetch modifier to the last argument */
2268 if (modifier
!= TEX_MODIFIER_NONE
) {
2269 const int last
= ARRAY_SIZE(args
) - 1;
2271 /* fetch modifier from src0.w or src1.x */
2273 assert(dim
<= TGSI_CHAN_W
&& shadow_ref
!= TGSI_CHAN_W
);
2274 FETCH(&r
[last
], 0, TGSI_CHAN_W
);
2277 assert(shadow_ref
!= 4);
2278 FETCH(&r
[last
], 1, TGSI_CHAN_X
);
2281 if (modifier
!= TEX_MODIFIER_PROJECTED
) {
2282 args
[last
] = &r
[last
];
2286 args
[last
] = &ZeroVec
;
2289 /* point unused arguments to zero vector */
2290 for (i
= dim
; i
< last
; i
++)
2293 if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
)
2294 control
= TGSI_SAMPLER_LOD_EXPLICIT
;
2295 else if (modifier
== TEX_MODIFIER_LOD_BIAS
)
2296 control
= TGSI_SAMPLER_LOD_BIAS
;
2297 else if (modifier
== TEX_MODIFIER_GATHER
)
2298 control
= TGSI_SAMPLER_GATHER
;
2301 for (i
= dim
; i
< (int)ARRAY_SIZE(args
); i
++)
2305 /* fetch coordinates */
2306 for (i
= 0; i
< dim
; i
++) {
2307 FETCH(&r
[i
], 0, TGSI_CHAN_X
+ i
);
2310 micro_div(&r
[i
], &r
[i
], proj
);
2315 /* fetch reference value */
2316 if (shadow_ref
>= 0) {
2317 FETCH(&r
[shadow_ref
], shadow_ref
/ 4, TGSI_CHAN_X
+ (shadow_ref
% 4));
2320 micro_div(&r
[shadow_ref
], &r
[shadow_ref
], proj
);
2322 args
[shadow_ref
] = &r
[shadow_ref
];
2325 fetch_texel(mach
->Sampler
, unit
, unit
,
2326 args
[0], args
[1], args
[2], args
[3], args
[4],
2327 NULL
, offsets
, control
,
2328 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2331 debug_printf("fetch r: %g %g %g %g\n",
2332 r
[0].f
[0], r
[0].f
[1], r
[0].f
[2], r
[0].f
[3]);
2333 debug_printf("fetch g: %g %g %g %g\n",
2334 r
[1].f
[0], r
[1].f
[1], r
[1].f
[2], r
[1].f
[3]);
2335 debug_printf("fetch b: %g %g %g %g\n",
2336 r
[2].f
[0], r
[2].f
[1], r
[2].f
[2], r
[2].f
[3]);
2337 debug_printf("fetch a: %g %g %g %g\n",
2338 r
[3].f
[0], r
[3].f
[1], r
[3].f
[2], r
[3].f
[3]);
2341 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2342 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2343 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2349 exec_lodq(struct tgsi_exec_machine
*mach
,
2350 const struct tgsi_full_instruction
*inst
)
2352 uint resource_unit
, sampler_unit
;
2355 union tgsi_exec_channel coords
[4];
2356 const union tgsi_exec_channel
*args
[ARRAY_SIZE(coords
)];
2357 union tgsi_exec_channel r
[2];
2359 resource_unit
= fetch_sampler_unit(mach
, inst
, 1);
2360 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_LOD
) {
2361 uint target
= mach
->SamplerViews
[resource_unit
].Resource
;
2362 dim
= tgsi_util_get_texture_coord_dim(target
);
2363 sampler_unit
= fetch_sampler_unit(mach
, inst
, 2);
2365 dim
= tgsi_util_get_texture_coord_dim(inst
->Texture
.Texture
);
2366 sampler_unit
= resource_unit
;
2368 assert(dim
<= ARRAY_SIZE(coords
));
2369 /* fetch coordinates */
2370 for (i
= 0; i
< dim
; i
++) {
2371 FETCH(&coords
[i
], 0, TGSI_CHAN_X
+ i
);
2372 args
[i
] = &coords
[i
];
2374 for (i
= dim
; i
< ARRAY_SIZE(coords
); i
++) {
2377 mach
->Sampler
->query_lod(mach
->Sampler
, resource_unit
, sampler_unit
,
2382 TGSI_SAMPLER_LOD_NONE
,
2386 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2387 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
,
2388 TGSI_EXEC_DATA_FLOAT
);
2390 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2391 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
,
2392 TGSI_EXEC_DATA_FLOAT
);
2394 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_LOD
) {
2395 unsigned char swizzles
[4];
2397 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2398 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2399 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2400 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2402 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2403 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2404 if (swizzles
[chan
] >= 2) {
2405 store_dest(mach
, &ZeroVec
,
2406 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2408 store_dest(mach
, &r
[swizzles
[chan
]],
2409 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2414 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2415 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
,
2416 TGSI_EXEC_DATA_FLOAT
);
2418 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2419 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
,
2420 TGSI_EXEC_DATA_FLOAT
);
2426 exec_txd(struct tgsi_exec_machine
*mach
,
2427 const struct tgsi_full_instruction
*inst
)
2429 union tgsi_exec_channel r
[4];
2430 float derivs
[3][2][TGSI_QUAD_SIZE
];
2435 unit
= fetch_sampler_unit(mach
, inst
, 3);
2436 /* always fetch all 3 offsets, overkill but keeps code simple */
2437 fetch_texel_offsets(mach
, inst
, offsets
);
2439 switch (inst
->Texture
.Texture
) {
2440 case TGSI_TEXTURE_1D
:
2441 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2443 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2445 fetch_texel(mach
->Sampler
, unit
, unit
,
2446 &r
[0], &ZeroVec
, &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2447 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2448 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2451 case TGSI_TEXTURE_SHADOW1D
:
2452 case TGSI_TEXTURE_1D_ARRAY
:
2453 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
2454 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
2455 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2456 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2457 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2459 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2461 fetch_texel(mach
->Sampler
, unit
, unit
,
2462 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2463 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2464 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2467 case TGSI_TEXTURE_2D
:
2468 case TGSI_TEXTURE_RECT
:
2469 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2470 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2472 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2473 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2475 fetch_texel(mach
->Sampler
, unit
, unit
,
2476 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2477 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2478 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2482 case TGSI_TEXTURE_SHADOW2D
:
2483 case TGSI_TEXTURE_SHADOWRECT
:
2484 case TGSI_TEXTURE_2D_ARRAY
:
2485 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
2486 /* only SHADOW2D_ARRAY actually needs W */
2487 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2488 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2489 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2490 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2492 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2493 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2495 fetch_texel(mach
->Sampler
, unit
, unit
,
2496 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
, /* inputs */
2497 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2498 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2501 case TGSI_TEXTURE_3D
:
2502 case TGSI_TEXTURE_CUBE
:
2503 case TGSI_TEXTURE_CUBE_ARRAY
:
2504 case TGSI_TEXTURE_SHADOWCUBE
:
2505 /* only TEXTURE_CUBE_ARRAY and TEXTURE_SHADOWCUBE actually need W */
2506 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2507 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2508 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2509 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2511 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2512 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2513 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Z
, derivs
[2]);
2515 fetch_texel(mach
->Sampler
, unit
, unit
,
2516 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
, /* inputs */
2517 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2518 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2525 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2526 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2527 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2534 exec_txf(struct tgsi_exec_machine
*mach
,
2535 const struct tgsi_full_instruction
*inst
)
2537 union tgsi_exec_channel r
[4];
2540 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
2545 unit
= fetch_sampler_unit(mach
, inst
, 1);
2546 /* always fetch all 3 offsets, overkill but keeps code simple */
2547 fetch_texel_offsets(mach
, inst
, offsets
);
2549 IFETCH(&r
[3], 0, TGSI_CHAN_W
);
2551 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I
||
2552 inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I_MS
) {
2553 target
= mach
->SamplerViews
[unit
].Resource
;
2556 target
= inst
->Texture
.Texture
;
2559 case TGSI_TEXTURE_3D
:
2560 case TGSI_TEXTURE_2D_ARRAY
:
2561 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
2562 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
2563 IFETCH(&r
[2], 0, TGSI_CHAN_Z
);
2565 case TGSI_TEXTURE_2D
:
2566 case TGSI_TEXTURE_RECT
:
2567 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
2568 case TGSI_TEXTURE_SHADOW2D
:
2569 case TGSI_TEXTURE_SHADOWRECT
:
2570 case TGSI_TEXTURE_1D_ARRAY
:
2571 case TGSI_TEXTURE_2D_MSAA
:
2572 IFETCH(&r
[1], 0, TGSI_CHAN_Y
);
2574 case TGSI_TEXTURE_BUFFER
:
2575 case TGSI_TEXTURE_1D
:
2576 case TGSI_TEXTURE_SHADOW1D
:
2577 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
2584 mach
->Sampler
->get_texel(mach
->Sampler
, unit
, r
[0].i
, r
[1].i
, r
[2].i
, r
[3].i
,
2587 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
2588 r
[0].f
[j
] = rgba
[0][j
];
2589 r
[1].f
[j
] = rgba
[1][j
];
2590 r
[2].f
[j
] = rgba
[2][j
];
2591 r
[3].f
[j
] = rgba
[3][j
];
2594 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I
||
2595 inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I_MS
) {
2596 unsigned char swizzles
[4];
2597 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2598 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2599 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2600 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2602 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2603 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2604 store_dest(mach
, &r
[swizzles
[chan
]],
2605 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2610 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2611 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2612 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2619 exec_txq(struct tgsi_exec_machine
*mach
,
2620 const struct tgsi_full_instruction
*inst
)
2623 union tgsi_exec_channel r
[4], src
;
2628 unit
= fetch_sampler_unit(mach
, inst
, 1);
2630 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
2632 /* XXX: This interface can't return per-pixel values */
2633 mach
->Sampler
->get_dims(mach
->Sampler
, unit
, src
.i
[0], result
);
2635 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2636 for (j
= 0; j
< 4; j
++) {
2637 r
[j
].i
[i
] = result
[j
];
2641 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2642 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2643 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
2644 TGSI_EXEC_DATA_INT
);
2650 exec_sample(struct tgsi_exec_machine
*mach
,
2651 const struct tgsi_full_instruction
*inst
,
2652 uint modifier
, boolean compare
)
2654 const uint resource_unit
= inst
->Src
[1].Register
.Index
;
2655 const uint sampler_unit
= inst
->Src
[2].Register
.Index
;
2656 union tgsi_exec_channel r
[5], c1
;
2657 const union tgsi_exec_channel
*lod
= &ZeroVec
;
2658 enum tgsi_sampler_control control
= TGSI_SAMPLER_LOD_NONE
;
2660 unsigned char swizzles
[4];
2663 /* always fetch all 3 offsets, overkill but keeps code simple */
2664 fetch_texel_offsets(mach
, inst
, offsets
);
2666 assert(modifier
!= TEX_MODIFIER_PROJECTED
);
2668 if (modifier
!= TEX_MODIFIER_NONE
) {
2669 if (modifier
== TEX_MODIFIER_LOD_BIAS
) {
2670 FETCH(&c1
, 3, TGSI_CHAN_X
);
2672 control
= TGSI_SAMPLER_LOD_BIAS
;
2674 else if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
) {
2675 FETCH(&c1
, 3, TGSI_CHAN_X
);
2677 control
= TGSI_SAMPLER_LOD_EXPLICIT
;
2679 else if (modifier
== TEX_MODIFIER_GATHER
) {
2680 control
= TGSI_SAMPLER_GATHER
;
2683 assert(modifier
== TEX_MODIFIER_LEVEL_ZERO
);
2684 control
= TGSI_SAMPLER_LOD_ZERO
;
2688 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2690 switch (mach
->SamplerViews
[resource_unit
].Resource
) {
2691 case TGSI_TEXTURE_1D
:
2693 FETCH(&r
[2], 3, TGSI_CHAN_X
);
2694 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2695 &r
[0], &ZeroVec
, &r
[2], &ZeroVec
, lod
, /* S, T, P, C, LOD */
2696 NULL
, offsets
, control
,
2697 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2700 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2701 &r
[0], &ZeroVec
, &ZeroVec
, &ZeroVec
, lod
, /* S, T, P, C, LOD */
2702 NULL
, offsets
, control
,
2703 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2707 case TGSI_TEXTURE_1D_ARRAY
:
2708 case TGSI_TEXTURE_2D
:
2709 case TGSI_TEXTURE_RECT
:
2710 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2712 FETCH(&r
[2], 3, TGSI_CHAN_X
);
2713 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2714 &r
[0], &r
[1], &r
[2], &ZeroVec
, lod
, /* S, T, P, C, LOD */
2715 NULL
, offsets
, control
,
2716 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2719 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2720 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, lod
, /* S, T, P, C, LOD */
2721 NULL
, offsets
, control
,
2722 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2726 case TGSI_TEXTURE_2D_ARRAY
:
2727 case TGSI_TEXTURE_3D
:
2728 case TGSI_TEXTURE_CUBE
:
2729 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2730 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2732 FETCH(&r
[3], 3, TGSI_CHAN_X
);
2733 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2734 &r
[0], &r
[1], &r
[2], &r
[3], lod
,
2735 NULL
, offsets
, control
,
2736 &r
[0], &r
[1], &r
[2], &r
[3]);
2739 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2740 &r
[0], &r
[1], &r
[2], &ZeroVec
, lod
,
2741 NULL
, offsets
, control
,
2742 &r
[0], &r
[1], &r
[2], &r
[3]);
2746 case TGSI_TEXTURE_CUBE_ARRAY
:
2747 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2748 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2749 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2751 FETCH(&r
[4], 3, TGSI_CHAN_X
);
2752 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2753 &r
[0], &r
[1], &r
[2], &r
[3], &r
[4],
2754 NULL
, offsets
, control
,
2755 &r
[0], &r
[1], &r
[2], &r
[3]);
2758 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2759 &r
[0], &r
[1], &r
[2], &r
[3], lod
,
2760 NULL
, offsets
, control
,
2761 &r
[0], &r
[1], &r
[2], &r
[3]);
2770 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2771 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2772 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2773 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2775 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2776 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2777 store_dest(mach
, &r
[swizzles
[chan
]],
2778 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2784 exec_sample_d(struct tgsi_exec_machine
*mach
,
2785 const struct tgsi_full_instruction
*inst
)
2787 const uint resource_unit
= inst
->Src
[1].Register
.Index
;
2788 const uint sampler_unit
= inst
->Src
[2].Register
.Index
;
2789 union tgsi_exec_channel r
[4];
2790 float derivs
[3][2][TGSI_QUAD_SIZE
];
2792 unsigned char swizzles
[4];
2795 /* always fetch all 3 offsets, overkill but keeps code simple */
2796 fetch_texel_offsets(mach
, inst
, offsets
);
2798 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2800 switch (mach
->SamplerViews
[resource_unit
].Resource
) {
2801 case TGSI_TEXTURE_1D
:
2802 case TGSI_TEXTURE_1D_ARRAY
:
2803 /* only 1D array actually needs Y */
2804 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2806 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2808 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2809 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2810 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2811 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2814 case TGSI_TEXTURE_2D
:
2815 case TGSI_TEXTURE_RECT
:
2816 case TGSI_TEXTURE_2D_ARRAY
:
2817 /* only 2D array actually needs Z */
2818 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2819 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2821 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2822 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Y
, derivs
[1]);
2824 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2825 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
, /* inputs */
2826 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2827 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2830 case TGSI_TEXTURE_3D
:
2831 case TGSI_TEXTURE_CUBE
:
2832 case TGSI_TEXTURE_CUBE_ARRAY
:
2833 /* only cube array actually needs W */
2834 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2835 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2836 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2838 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2839 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Y
, derivs
[1]);
2840 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Z
, derivs
[2]);
2842 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2843 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
,
2844 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2845 &r
[0], &r
[1], &r
[2], &r
[3]);
2852 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2853 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2854 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2855 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2857 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2858 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2859 store_dest(mach
, &r
[swizzles
[chan
]],
2860 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2867 * Evaluate a constant-valued coefficient at the position of the
2872 struct tgsi_exec_machine
*mach
,
2878 for( i
= 0; i
< TGSI_QUAD_SIZE
; i
++ ) {
2879 mach
->Inputs
[attrib
].xyzw
[chan
].f
[i
] = mach
->InterpCoefs
[attrib
].a0
[chan
];
2884 * Evaluate a linear-valued coefficient at the position of the
2889 struct tgsi_exec_machine
*mach
,
2893 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
2894 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
2895 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2896 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2897 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
2898 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
;
2899 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = a0
+ dadx
;
2900 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = a0
+ dady
;
2901 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = a0
+ dadx
+ dady
;
2905 * Evaluate a perspective-valued coefficient at the position of the
2909 eval_perspective_coef(
2910 struct tgsi_exec_machine
*mach
,
2914 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
2915 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
2916 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2917 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2918 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
2919 const float *w
= mach
->QuadPos
.xyzw
[3].f
;
2920 /* divide by W here */
2921 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
/ w
[0];
2922 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = (a0
+ dadx
) / w
[1];
2923 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = (a0
+ dady
) / w
[2];
2924 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = (a0
+ dadx
+ dady
) / w
[3];
2928 typedef void (* eval_coef_func
)(
2929 struct tgsi_exec_machine
*mach
,
2934 exec_declaration(struct tgsi_exec_machine
*mach
,
2935 const struct tgsi_full_declaration
*decl
)
2937 if (decl
->Declaration
.File
== TGSI_FILE_SAMPLER_VIEW
) {
2938 mach
->SamplerViews
[decl
->Range
.First
] = decl
->SamplerView
;
2942 if (mach
->ShaderType
== PIPE_SHADER_FRAGMENT
) {
2943 if (decl
->Declaration
.File
== TGSI_FILE_INPUT
) {
2944 uint first
, last
, mask
;
2946 first
= decl
->Range
.First
;
2947 last
= decl
->Range
.Last
;
2948 mask
= decl
->Declaration
.UsageMask
;
2950 /* XXX we could remove this special-case code since
2951 * mach->InterpCoefs[first].a0 should already have the
2952 * front/back-face value. But we should first update the
2953 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2954 * Then, we could remove the tgsi_exec_machine::Face field.
2956 /* XXX make FACE a system value */
2957 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_FACE
) {
2960 assert(decl
->Semantic
.Index
== 0);
2961 assert(first
== last
);
2963 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2964 mach
->Inputs
[first
].xyzw
[0].f
[i
] = mach
->Face
;
2967 eval_coef_func eval
;
2970 switch (decl
->Interp
.Interpolate
) {
2971 case TGSI_INTERPOLATE_CONSTANT
:
2972 eval
= eval_constant_coef
;
2975 case TGSI_INTERPOLATE_LINEAR
:
2976 eval
= eval_linear_coef
;
2979 case TGSI_INTERPOLATE_PERSPECTIVE
:
2980 eval
= eval_perspective_coef
;
2983 case TGSI_INTERPOLATE_COLOR
:
2984 eval
= mach
->flatshade_color
? eval_constant_coef
: eval_perspective_coef
;
2992 for (j
= 0; j
< TGSI_NUM_CHANNELS
; j
++) {
2993 if (mask
& (1 << j
)) {
2994 for (i
= first
; i
<= last
; i
++) {
3001 if (DEBUG_EXECUTION
) {
3003 for (i
= first
; i
<= last
; ++i
) {
3004 debug_printf("IN[%2u] = ", i
);
3005 for (j
= 0; j
< TGSI_NUM_CHANNELS
; j
++) {
3009 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
3010 mach
->Inputs
[i
].xyzw
[0].f
[j
], mach
->Inputs
[i
].xyzw
[0].u
[j
],
3011 mach
->Inputs
[i
].xyzw
[1].f
[j
], mach
->Inputs
[i
].xyzw
[1].u
[j
],
3012 mach
->Inputs
[i
].xyzw
[2].f
[j
], mach
->Inputs
[i
].xyzw
[2].u
[j
],
3013 mach
->Inputs
[i
].xyzw
[3].f
[j
], mach
->Inputs
[i
].xyzw
[3].u
[j
]);
3022 typedef void (* micro_unary_op
)(union tgsi_exec_channel
*dst
,
3023 const union tgsi_exec_channel
*src
);
3026 exec_scalar_unary(struct tgsi_exec_machine
*mach
,
3027 const struct tgsi_full_instruction
*inst
,
3029 enum tgsi_exec_datatype dst_datatype
,
3030 enum tgsi_exec_datatype src_datatype
)
3033 union tgsi_exec_channel src
;
3034 union tgsi_exec_channel dst
;
3036 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
3038 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3039 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3040 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3046 exec_vector_unary(struct tgsi_exec_machine
*mach
,
3047 const struct tgsi_full_instruction
*inst
,
3049 enum tgsi_exec_datatype dst_datatype
,
3050 enum tgsi_exec_datatype src_datatype
)
3053 struct tgsi_exec_vector dst
;
3055 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3056 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3057 union tgsi_exec_channel src
;
3059 fetch_source(mach
, &src
, &inst
->Src
[0], chan
, src_datatype
);
3060 op(&dst
.xyzw
[chan
], &src
);
3063 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3064 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3065 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3070 typedef void (* micro_binary_op
)(union tgsi_exec_channel
*dst
,
3071 const union tgsi_exec_channel
*src0
,
3072 const union tgsi_exec_channel
*src1
);
3075 exec_scalar_binary(struct tgsi_exec_machine
*mach
,
3076 const struct tgsi_full_instruction
*inst
,
3078 enum tgsi_exec_datatype dst_datatype
,
3079 enum tgsi_exec_datatype src_datatype
)
3082 union tgsi_exec_channel src
[2];
3083 union tgsi_exec_channel dst
;
3085 fetch_source(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
3086 fetch_source(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, src_datatype
);
3087 op(&dst
, &src
[0], &src
[1]);
3088 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3089 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3090 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3096 exec_vector_binary(struct tgsi_exec_machine
*mach
,
3097 const struct tgsi_full_instruction
*inst
,
3099 enum tgsi_exec_datatype dst_datatype
,
3100 enum tgsi_exec_datatype src_datatype
)
3103 struct tgsi_exec_vector dst
;
3105 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3106 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3107 union tgsi_exec_channel src
[2];
3109 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
3110 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
3111 op(&dst
.xyzw
[chan
], &src
[0], &src
[1]);
3114 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3115 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3116 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3121 typedef void (* micro_trinary_op
)(union tgsi_exec_channel
*dst
,
3122 const union tgsi_exec_channel
*src0
,
3123 const union tgsi_exec_channel
*src1
,
3124 const union tgsi_exec_channel
*src2
);
3127 exec_vector_trinary(struct tgsi_exec_machine
*mach
,
3128 const struct tgsi_full_instruction
*inst
,
3129 micro_trinary_op op
,
3130 enum tgsi_exec_datatype dst_datatype
,
3131 enum tgsi_exec_datatype src_datatype
)
3134 struct tgsi_exec_vector dst
;
3136 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3137 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3138 union tgsi_exec_channel src
[3];
3140 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
3141 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
3142 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
, src_datatype
);
3143 op(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2]);
3146 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3147 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3148 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3153 typedef void (* micro_quaternary_op
)(union tgsi_exec_channel
*dst
,
3154 const union tgsi_exec_channel
*src0
,
3155 const union tgsi_exec_channel
*src1
,
3156 const union tgsi_exec_channel
*src2
,
3157 const union tgsi_exec_channel
*src3
);
3160 exec_vector_quaternary(struct tgsi_exec_machine
*mach
,
3161 const struct tgsi_full_instruction
*inst
,
3162 micro_quaternary_op op
,
3163 enum tgsi_exec_datatype dst_datatype
,
3164 enum tgsi_exec_datatype src_datatype
)
3167 struct tgsi_exec_vector dst
;
3169 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3170 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3171 union tgsi_exec_channel src
[4];
3173 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
3174 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
3175 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
, src_datatype
);
3176 fetch_source(mach
, &src
[3], &inst
->Src
[3], chan
, src_datatype
);
3177 op(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2], &src
[3]);
3180 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3181 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3182 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3188 exec_dp3(struct tgsi_exec_machine
*mach
,
3189 const struct tgsi_full_instruction
*inst
)
3192 union tgsi_exec_channel arg
[3];
3194 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3195 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3196 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3198 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_Z
; chan
++) {
3199 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
3200 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
3201 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3204 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3205 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3206 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3212 exec_dp4(struct tgsi_exec_machine
*mach
,
3213 const struct tgsi_full_instruction
*inst
)
3216 union tgsi_exec_channel arg
[3];
3218 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3219 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3220 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3222 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_W
; chan
++) {
3223 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
3224 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
3225 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3228 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3229 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3230 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3236 exec_dp2(struct tgsi_exec_machine
*mach
,
3237 const struct tgsi_full_instruction
*inst
)
3240 union tgsi_exec_channel arg
[3];
3242 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3243 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3244 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3246 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3247 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3248 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3250 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3251 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3252 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3258 exec_pk2h(struct tgsi_exec_machine
*mach
,
3259 const struct tgsi_full_instruction
*inst
)
3262 union tgsi_exec_channel arg
[2], dst
;
3264 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3265 fetch_source(mach
, &arg
[1], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3266 for (chan
= 0; chan
< TGSI_QUAD_SIZE
; chan
++) {
3267 dst
.u
[chan
] = util_float_to_half(arg
[0].f
[chan
]) |
3268 (util_float_to_half(arg
[1].f
[chan
]) << 16);
3270 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3271 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3272 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_UINT
);
3278 exec_up2h(struct tgsi_exec_machine
*mach
,
3279 const struct tgsi_full_instruction
*inst
)
3282 union tgsi_exec_channel arg
, dst
[2];
3284 fetch_source(mach
, &arg
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3285 for (chan
= 0; chan
< TGSI_QUAD_SIZE
; chan
++) {
3286 dst
[0].f
[chan
] = util_half_to_float(arg
.u
[chan
] & 0xffff);
3287 dst
[1].f
[chan
] = util_half_to_float(arg
.u
[chan
] >> 16);
3289 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3290 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3291 store_dest(mach
, &dst
[chan
& 1], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3297 micro_ucmp(union tgsi_exec_channel
*dst
,
3298 const union tgsi_exec_channel
*src0
,
3299 const union tgsi_exec_channel
*src1
,
3300 const union tgsi_exec_channel
*src2
)
3302 dst
->f
[0] = src0
->u
[0] ? src1
->f
[0] : src2
->f
[0];
3303 dst
->f
[1] = src0
->u
[1] ? src1
->f
[1] : src2
->f
[1];
3304 dst
->f
[2] = src0
->u
[2] ? src1
->f
[2] : src2
->f
[2];
3305 dst
->f
[3] = src0
->u
[3] ? src1
->f
[3] : src2
->f
[3];
3309 exec_ucmp(struct tgsi_exec_machine
*mach
,
3310 const struct tgsi_full_instruction
*inst
)
3313 struct tgsi_exec_vector dst
;
3315 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3316 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3317 union tgsi_exec_channel src
[3];
3319 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
,
3320 TGSI_EXEC_DATA_UINT
);
3321 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
,
3322 TGSI_EXEC_DATA_FLOAT
);
3323 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
,
3324 TGSI_EXEC_DATA_FLOAT
);
3325 micro_ucmp(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2]);
3328 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3329 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3330 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
,
3331 TGSI_EXEC_DATA_FLOAT
);
3337 exec_dst(struct tgsi_exec_machine
*mach
,
3338 const struct tgsi_full_instruction
*inst
)
3340 union tgsi_exec_channel r
[2];
3341 union tgsi_exec_channel d
[4];
3343 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3344 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3345 fetch_source(mach
, &r
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3346 micro_mul(&d
[TGSI_CHAN_Y
], &r
[0], &r
[1]);
3348 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3349 fetch_source(mach
, &d
[TGSI_CHAN_Z
], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3351 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3352 fetch_source(mach
, &d
[TGSI_CHAN_W
], &inst
->Src
[1], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3355 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3356 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3358 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3359 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3361 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3362 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3364 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3365 store_dest(mach
, &d
[TGSI_CHAN_W
], &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3370 exec_log(struct tgsi_exec_machine
*mach
,
3371 const struct tgsi_full_instruction
*inst
)
3373 union tgsi_exec_channel r
[3];
3375 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3376 micro_abs(&r
[2], &r
[0]); /* r2 = abs(r0) */
3377 micro_lg2(&r
[1], &r
[2]); /* r1 = lg2(r2) */
3378 micro_flr(&r
[0], &r
[1]); /* r0 = floor(r1) */
3379 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3380 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3382 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3383 micro_exp2(&r
[0], &r
[0]); /* r0 = 2 ^ r0 */
3384 micro_div(&r
[0], &r
[2], &r
[0]); /* r0 = r2 / r0 */
3385 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3387 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3388 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3390 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3391 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3396 exec_exp(struct tgsi_exec_machine
*mach
,
3397 const struct tgsi_full_instruction
*inst
)
3399 union tgsi_exec_channel r
[3];
3401 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3402 micro_flr(&r
[1], &r
[0]); /* r1 = floor(r0) */
3403 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3404 micro_exp2(&r
[2], &r
[1]); /* r2 = 2 ^ r1 */
3405 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3407 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3408 micro_sub(&r
[2], &r
[0], &r
[1]); /* r2 = r0 - r1 */
3409 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3411 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3412 micro_exp2(&r
[2], &r
[0]); /* r2 = 2 ^ r0 */
3413 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3415 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3416 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3421 exec_lit(struct tgsi_exec_machine
*mach
,
3422 const struct tgsi_full_instruction
*inst
)
3424 union tgsi_exec_channel r
[3];
3425 union tgsi_exec_channel d
[3];
3427 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_YZ
) {
3428 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3429 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3430 fetch_source(mach
, &r
[1], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3431 micro_max(&r
[1], &r
[1], &ZeroVec
);
3433 fetch_source(mach
, &r
[2], &inst
->Src
[0], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3434 micro_min(&r
[2], &r
[2], &P128Vec
);
3435 micro_max(&r
[2], &r
[2], &M128Vec
);
3436 micro_pow(&r
[1], &r
[1], &r
[2]);
3437 micro_lt(&d
[TGSI_CHAN_Z
], &ZeroVec
, &r
[0], &r
[1], &ZeroVec
);
3438 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3440 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3441 micro_max(&d
[TGSI_CHAN_Y
], &r
[0], &ZeroVec
);
3442 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3445 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3446 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3449 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3450 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3455 exec_break(struct tgsi_exec_machine
*mach
)
3457 if (mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_LOOP
) {
3458 /* turn off loop channels for each enabled exec channel */
3459 mach
->LoopMask
&= ~mach
->ExecMask
;
3460 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3461 UPDATE_EXEC_MASK(mach
);
3463 assert(mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_SWITCH
);
3465 mach
->Switch
.mask
= 0x0;
3467 UPDATE_EXEC_MASK(mach
);
3472 exec_switch(struct tgsi_exec_machine
*mach
,
3473 const struct tgsi_full_instruction
*inst
)
3475 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
3476 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
3478 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
3479 fetch_source(mach
, &mach
->Switch
.selector
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3480 mach
->Switch
.mask
= 0x0;
3481 mach
->Switch
.defaultMask
= 0x0;
3483 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
3484 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_SWITCH
;
3486 UPDATE_EXEC_MASK(mach
);
3490 exec_case(struct tgsi_exec_machine
*mach
,
3491 const struct tgsi_full_instruction
*inst
)
3493 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
3494 union tgsi_exec_channel src
;
3497 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3499 if (mach
->Switch
.selector
.u
[0] == src
.u
[0]) {
3502 if (mach
->Switch
.selector
.u
[1] == src
.u
[1]) {
3505 if (mach
->Switch
.selector
.u
[2] == src
.u
[2]) {
3508 if (mach
->Switch
.selector
.u
[3] == src
.u
[3]) {
3512 mach
->Switch
.defaultMask
|= mask
;
3514 mach
->Switch
.mask
|= mask
& prevMask
;
3516 UPDATE_EXEC_MASK(mach
);
3519 /* FIXME: this will only work if default is last */
3521 exec_default(struct tgsi_exec_machine
*mach
)
3523 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
3525 mach
->Switch
.mask
|= ~mach
->Switch
.defaultMask
& prevMask
;
3527 UPDATE_EXEC_MASK(mach
);
3531 exec_endswitch(struct tgsi_exec_machine
*mach
)
3533 mach
->Switch
= mach
->SwitchStack
[--mach
->SwitchStackTop
];
3534 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
3536 UPDATE_EXEC_MASK(mach
);
3539 typedef void (* micro_dop
)(union tgsi_double_channel
*dst
,
3540 const union tgsi_double_channel
*src
);
3542 typedef void (* micro_dop_sop
)(union tgsi_double_channel
*dst
,
3543 const union tgsi_double_channel
*src0
,
3544 union tgsi_exec_channel
*src1
);
3546 typedef void (* micro_dop_s
)(union tgsi_double_channel
*dst
,
3547 const union tgsi_exec_channel
*src
);
3549 typedef void (* micro_sop_d
)(union tgsi_exec_channel
*dst
,
3550 const union tgsi_double_channel
*src
);
3553 fetch_double_channel(struct tgsi_exec_machine
*mach
,
3554 union tgsi_double_channel
*chan
,
3555 const struct tgsi_full_src_register
*reg
,
3559 union tgsi_exec_channel src
[2];
3562 fetch_source_d(mach
, &src
[0], reg
, chan_0
);
3563 fetch_source_d(mach
, &src
[1], reg
, chan_1
);
3565 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
3566 chan
->u
[i
][0] = src
[0].u
[i
];
3567 chan
->u
[i
][1] = src
[1].u
[i
];
3569 if (reg
->Register
.Absolute
) {
3570 micro_dabs(chan
, chan
);
3572 if (reg
->Register
.Negate
) {
3573 micro_dneg(chan
, chan
);
3578 store_double_channel(struct tgsi_exec_machine
*mach
,
3579 const union tgsi_double_channel
*chan
,
3580 const struct tgsi_full_dst_register
*reg
,
3581 const struct tgsi_full_instruction
*inst
,
3585 union tgsi_exec_channel dst
[2];
3587 union tgsi_double_channel temp
;
3588 const uint execmask
= mach
->ExecMask
;
3590 if (!inst
->Instruction
.Saturate
) {
3591 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
3592 if (execmask
& (1 << i
)) {
3593 dst
[0].u
[i
] = chan
->u
[i
][0];
3594 dst
[1].u
[i
] = chan
->u
[i
][1];
3598 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
3599 if (execmask
& (1 << i
)) {
3600 if (chan
->d
[i
] < 0.0)
3602 else if (chan
->d
[i
] > 1.0)
3605 temp
.d
[i
] = chan
->d
[i
];
3607 dst
[0].u
[i
] = temp
.u
[i
][0];
3608 dst
[1].u
[i
] = temp
.u
[i
][1];
3612 store_dest_double(mach
, &dst
[0], reg
, chan_0
, TGSI_EXEC_DATA_UINT
);
3613 if (chan_1
!= (unsigned)-1)
3614 store_dest_double(mach
, &dst
[1], reg
, chan_1
, TGSI_EXEC_DATA_UINT
);
3618 exec_double_unary(struct tgsi_exec_machine
*mach
,
3619 const struct tgsi_full_instruction
*inst
,
3622 union tgsi_double_channel src
;
3623 union tgsi_double_channel dst
;
3625 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3626 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3628 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3630 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3631 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3633 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3638 exec_double_binary(struct tgsi_exec_machine
*mach
,
3639 const struct tgsi_full_instruction
*inst
,
3641 enum tgsi_exec_datatype dst_datatype
)
3643 union tgsi_double_channel src
[2];
3644 union tgsi_double_channel dst
;
3645 int first_dest_chan
, second_dest_chan
;
3648 wmask
= inst
->Dst
[0].Register
.WriteMask
;
3649 /* these are & because of the way DSLT etc store their destinations */
3650 if (wmask
& TGSI_WRITEMASK_XY
) {
3651 first_dest_chan
= TGSI_CHAN_X
;
3652 second_dest_chan
= TGSI_CHAN_Y
;
3653 if (dst_datatype
== TGSI_EXEC_DATA_UINT
) {
3654 first_dest_chan
= (wmask
& TGSI_WRITEMASK_X
) ? TGSI_CHAN_X
: TGSI_CHAN_Y
;
3655 second_dest_chan
= -1;
3658 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3659 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3661 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, first_dest_chan
, second_dest_chan
);
3664 if (wmask
& TGSI_WRITEMASK_ZW
) {
3665 first_dest_chan
= TGSI_CHAN_Z
;
3666 second_dest_chan
= TGSI_CHAN_W
;
3667 if (dst_datatype
== TGSI_EXEC_DATA_UINT
) {
3668 first_dest_chan
= (wmask
& TGSI_WRITEMASK_Z
) ? TGSI_CHAN_Z
: TGSI_CHAN_W
;
3669 second_dest_chan
= -1;
3672 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3673 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3675 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, first_dest_chan
, second_dest_chan
);
3680 exec_double_trinary(struct tgsi_exec_machine
*mach
,
3681 const struct tgsi_full_instruction
*inst
,
3684 union tgsi_double_channel src
[3];
3685 union tgsi_double_channel dst
;
3687 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3688 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3689 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3690 fetch_double_channel(mach
, &src
[2], &inst
->Src
[2], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3692 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3694 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3695 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3696 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3697 fetch_double_channel(mach
, &src
[2], &inst
->Src
[2], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3699 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3704 exec_dldexp(struct tgsi_exec_machine
*mach
,
3705 const struct tgsi_full_instruction
*inst
)
3707 union tgsi_double_channel src0
;
3708 union tgsi_exec_channel src1
;
3709 union tgsi_double_channel dst
;
3712 wmask
= inst
->Dst
[0].Register
.WriteMask
;
3713 if (wmask
& TGSI_WRITEMASK_XY
) {
3714 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3715 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
3716 micro_dldexp(&dst
, &src0
, &src1
);
3717 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3720 if (wmask
& TGSI_WRITEMASK_ZW
) {
3721 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3722 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_INT
);
3723 micro_dldexp(&dst
, &src0
, &src1
);
3724 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3729 exec_dfracexp(struct tgsi_exec_machine
*mach
,
3730 const struct tgsi_full_instruction
*inst
)
3732 union tgsi_double_channel src
;
3733 union tgsi_double_channel dst
;
3734 union tgsi_exec_channel dst_exp
;
3736 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3737 micro_dfracexp(&dst
, &dst_exp
, &src
);
3738 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
)
3739 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3740 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
)
3741 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3742 for (unsigned chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3743 if (inst
->Dst
[1].Register
.WriteMask
& (1 << chan
))
3744 store_dest(mach
, &dst_exp
, &inst
->Dst
[1], inst
, chan
, TGSI_EXEC_DATA_INT
);
3749 exec_arg0_64_arg1_32(struct tgsi_exec_machine
*mach
,
3750 const struct tgsi_full_instruction
*inst
,
3753 union tgsi_double_channel src0
;
3754 union tgsi_exec_channel src1
;
3755 union tgsi_double_channel dst
;
3758 wmask
= inst
->Dst
[0].Register
.WriteMask
;
3759 if (wmask
& TGSI_WRITEMASK_XY
) {
3760 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3761 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
3762 op(&dst
, &src0
, &src1
);
3763 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3766 if (wmask
& TGSI_WRITEMASK_ZW
) {
3767 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3768 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_INT
);
3769 op(&dst
, &src0
, &src1
);
3770 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3775 get_image_coord_dim(unsigned tgsi_tex
)
3779 case TGSI_TEXTURE_BUFFER
:
3780 case TGSI_TEXTURE_1D
:
3783 case TGSI_TEXTURE_2D
:
3784 case TGSI_TEXTURE_RECT
:
3785 case TGSI_TEXTURE_1D_ARRAY
:
3786 case TGSI_TEXTURE_2D_MSAA
:
3789 case TGSI_TEXTURE_3D
:
3790 case TGSI_TEXTURE_CUBE
:
3791 case TGSI_TEXTURE_2D_ARRAY
:
3792 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
3793 case TGSI_TEXTURE_CUBE_ARRAY
:
3797 assert(!"unknown texture target");
3806 get_image_coord_sample(unsigned tgsi_tex
)
3810 case TGSI_TEXTURE_2D_MSAA
:
3813 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
3823 exec_load_img(struct tgsi_exec_machine
*mach
,
3824 const struct tgsi_full_instruction
*inst
)
3826 union tgsi_exec_channel r
[4], sample_r
;
3832 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3833 struct tgsi_image_params params
;
3834 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
3836 unit
= fetch_sampler_unit(mach
, inst
, 0);
3837 dim
= get_image_coord_dim(inst
->Memory
.Texture
);
3838 sample
= get_image_coord_sample(inst
->Memory
.Texture
);
3841 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
3843 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
3844 params
.format
= inst
->Memory
.Format
;
3846 for (i
= 0; i
< dim
; i
++) {
3847 IFETCH(&r
[i
], 1, TGSI_CHAN_X
+ i
);
3851 IFETCH(&sample_r
, 1, TGSI_CHAN_X
+ sample
);
3853 mach
->Image
->load(mach
->Image
, ¶ms
,
3854 r
[0].i
, r
[1].i
, r
[2].i
, sample_r
.i
,
3856 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3857 r
[0].f
[j
] = rgba
[0][j
];
3858 r
[1].f
[j
] = rgba
[1][j
];
3859 r
[2].f
[j
] = rgba
[2][j
];
3860 r
[3].f
[j
] = rgba
[3][j
];
3862 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3863 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3864 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3870 exec_load_buf(struct tgsi_exec_machine
*mach
,
3871 const struct tgsi_full_instruction
*inst
)
3873 union tgsi_exec_channel r
[4];
3877 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3878 struct tgsi_buffer_params params
;
3879 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
3881 unit
= fetch_sampler_unit(mach
, inst
, 0);
3883 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
3885 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
3887 mach
->Buffer
->load(mach
->Buffer
, ¶ms
,
3889 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3890 r
[0].f
[j
] = rgba
[0][j
];
3891 r
[1].f
[j
] = rgba
[1][j
];
3892 r
[2].f
[j
] = rgba
[2][j
];
3893 r
[3].f
[j
] = rgba
[3][j
];
3895 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3896 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3897 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3903 exec_load_mem(struct tgsi_exec_machine
*mach
,
3904 const struct tgsi_full_instruction
*inst
)
3906 union tgsi_exec_channel r
[4];
3908 char *ptr
= mach
->LocalMem
;
3912 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
3913 if (r
[0].u
[0] >= mach
->LocalMemSize
)
3919 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3920 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3921 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3922 memcpy(&r
[chan
].u
[j
], ptr
+ (4 * chan
), 4);
3927 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3928 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3929 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3935 exec_load(struct tgsi_exec_machine
*mach
,
3936 const struct tgsi_full_instruction
*inst
)
3938 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
3939 exec_load_img(mach
, inst
);
3940 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
)
3941 exec_load_buf(mach
, inst
);
3942 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
)
3943 exec_load_mem(mach
, inst
);
3947 exec_store_img(struct tgsi_exec_machine
*mach
,
3948 const struct tgsi_full_instruction
*inst
)
3950 union tgsi_exec_channel r
[3], sample_r
;
3951 union tgsi_exec_channel value
[4];
3952 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3953 struct tgsi_image_params params
;
3958 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
3959 unit
= inst
->Dst
[0].Register
.Index
;
3960 dim
= get_image_coord_dim(inst
->Memory
.Texture
);
3961 sample
= get_image_coord_sample(inst
->Memory
.Texture
);
3964 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
3966 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
3967 params
.format
= inst
->Memory
.Format
;
3969 for (i
= 0; i
< dim
; i
++) {
3970 IFETCH(&r
[i
], 0, TGSI_CHAN_X
+ i
);
3973 for (i
= 0; i
< 4; i
++) {
3974 FETCH(&value
[i
], 1, TGSI_CHAN_X
+ i
);
3977 IFETCH(&sample_r
, 0, TGSI_CHAN_X
+ sample
);
3979 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3980 rgba
[0][j
] = value
[0].f
[j
];
3981 rgba
[1][j
] = value
[1].f
[j
];
3982 rgba
[2][j
] = value
[2].f
[j
];
3983 rgba
[3][j
] = value
[3].f
[j
];
3986 mach
->Image
->store(mach
->Image
, ¶ms
,
3987 r
[0].i
, r
[1].i
, r
[2].i
, sample_r
.i
,
3992 exec_store_buf(struct tgsi_exec_machine
*mach
,
3993 const struct tgsi_full_instruction
*inst
)
3995 union tgsi_exec_channel r
[3];
3996 union tgsi_exec_channel value
[4];
3997 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3998 struct tgsi_buffer_params params
;
4001 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4003 unit
= inst
->Dst
[0].Register
.Index
;
4005 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4007 params
.writemask
= inst
->Dst
[0].Register
.WriteMask
;
4009 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
4010 for (i
= 0; i
< 4; i
++) {
4011 FETCH(&value
[i
], 1, TGSI_CHAN_X
+ i
);
4014 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4015 rgba
[0][j
] = value
[0].f
[j
];
4016 rgba
[1][j
] = value
[1].f
[j
];
4017 rgba
[2][j
] = value
[2].f
[j
];
4018 rgba
[3][j
] = value
[3].f
[j
];
4021 mach
->Buffer
->store(mach
->Buffer
, ¶ms
,
4027 exec_store_mem(struct tgsi_exec_machine
*mach
,
4028 const struct tgsi_full_instruction
*inst
)
4030 union tgsi_exec_channel r
[3];
4031 union tgsi_exec_channel value
[4];
4033 char *ptr
= mach
->LocalMem
;
4034 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4035 int execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4037 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
4039 for (i
= 0; i
< 4; i
++) {
4040 FETCH(&value
[i
], 1, TGSI_CHAN_X
+ i
);
4043 if (r
[0].u
[0] >= mach
->LocalMemSize
)
4047 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
4048 if (execmask
& (1 << i
)) {
4049 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4050 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4051 memcpy(ptr
+ (chan
* 4), &value
[chan
].u
[0], 4);
4059 exec_store(struct tgsi_exec_machine
*mach
,
4060 const struct tgsi_full_instruction
*inst
)
4062 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_IMAGE
)
4063 exec_store_img(mach
, inst
);
4064 else if (inst
->Dst
[0].Register
.File
== TGSI_FILE_BUFFER
)
4065 exec_store_buf(mach
, inst
);
4066 else if (inst
->Dst
[0].Register
.File
== TGSI_FILE_MEMORY
)
4067 exec_store_mem(mach
, inst
);
4071 exec_atomop_img(struct tgsi_exec_machine
*mach
,
4072 const struct tgsi_full_instruction
*inst
)
4074 union tgsi_exec_channel r
[4], sample_r
;
4075 union tgsi_exec_channel value
[4], value2
[4];
4076 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4077 float rgba2
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4078 struct tgsi_image_params params
;
4083 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4084 unit
= fetch_sampler_unit(mach
, inst
, 0);
4085 dim
= get_image_coord_dim(inst
->Memory
.Texture
);
4086 sample
= get_image_coord_sample(inst
->Memory
.Texture
);
4089 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4091 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
4092 params
.format
= inst
->Memory
.Format
;
4094 for (i
= 0; i
< dim
; i
++) {
4095 IFETCH(&r
[i
], 1, TGSI_CHAN_X
+ i
);
4098 for (i
= 0; i
< 4; i
++) {
4099 FETCH(&value
[i
], 2, TGSI_CHAN_X
+ i
);
4100 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
4101 FETCH(&value2
[i
], 3, TGSI_CHAN_X
+ i
);
4104 IFETCH(&sample_r
, 1, TGSI_CHAN_X
+ sample
);
4106 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4107 rgba
[0][j
] = value
[0].f
[j
];
4108 rgba
[1][j
] = value
[1].f
[j
];
4109 rgba
[2][j
] = value
[2].f
[j
];
4110 rgba
[3][j
] = value
[3].f
[j
];
4112 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
4113 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4114 rgba2
[0][j
] = value2
[0].f
[j
];
4115 rgba2
[1][j
] = value2
[1].f
[j
];
4116 rgba2
[2][j
] = value2
[2].f
[j
];
4117 rgba2
[3][j
] = value2
[3].f
[j
];
4121 mach
->Image
->op(mach
->Image
, ¶ms
, inst
->Instruction
.Opcode
,
4122 r
[0].i
, r
[1].i
, r
[2].i
, sample_r
.i
,
4125 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4126 r
[0].f
[j
] = rgba
[0][j
];
4127 r
[1].f
[j
] = rgba
[1][j
];
4128 r
[2].f
[j
] = rgba
[2][j
];
4129 r
[3].f
[j
] = rgba
[3][j
];
4131 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4132 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4133 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4139 exec_atomop_buf(struct tgsi_exec_machine
*mach
,
4140 const struct tgsi_full_instruction
*inst
)
4142 union tgsi_exec_channel r
[4];
4143 union tgsi_exec_channel value
[4], value2
[4];
4144 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4145 float rgba2
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4146 struct tgsi_buffer_params params
;
4149 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4151 unit
= fetch_sampler_unit(mach
, inst
, 0);
4153 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4155 params
.writemask
= inst
->Dst
[0].Register
.WriteMask
;
4157 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
4159 for (i
= 0; i
< 4; i
++) {
4160 FETCH(&value
[i
], 2, TGSI_CHAN_X
+ i
);
4161 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
4162 FETCH(&value2
[i
], 3, TGSI_CHAN_X
+ i
);
4165 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4166 rgba
[0][j
] = value
[0].f
[j
];
4167 rgba
[1][j
] = value
[1].f
[j
];
4168 rgba
[2][j
] = value
[2].f
[j
];
4169 rgba
[3][j
] = value
[3].f
[j
];
4171 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
4172 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4173 rgba2
[0][j
] = value2
[0].f
[j
];
4174 rgba2
[1][j
] = value2
[1].f
[j
];
4175 rgba2
[2][j
] = value2
[2].f
[j
];
4176 rgba2
[3][j
] = value2
[3].f
[j
];
4180 mach
->Buffer
->op(mach
->Buffer
, ¶ms
, inst
->Instruction
.Opcode
,
4184 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4185 r
[0].f
[j
] = rgba
[0][j
];
4186 r
[1].f
[j
] = rgba
[1][j
];
4187 r
[2].f
[j
] = rgba
[2][j
];
4188 r
[3].f
[j
] = rgba
[3][j
];
4190 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4191 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4192 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4198 exec_atomop_mem(struct tgsi_exec_machine
*mach
,
4199 const struct tgsi_full_instruction
*inst
)
4201 union tgsi_exec_channel r
[4];
4202 union tgsi_exec_channel value
[4], value2
[4];
4203 char *ptr
= mach
->LocalMem
;
4207 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4208 int execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4209 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
4211 if (r
[0].u
[0] >= mach
->LocalMemSize
)
4216 for (i
= 0; i
< 4; i
++) {
4217 FETCH(&value
[i
], 2, TGSI_CHAN_X
+ i
);
4218 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
4219 FETCH(&value2
[i
], 3, TGSI_CHAN_X
+ i
);
4222 memcpy(&r
[0].u
[0], ptr
, 4);
4224 switch (inst
->Instruction
.Opcode
) {
4225 case TGSI_OPCODE_ATOMUADD
:
4226 val
+= value
[0].u
[0];
4228 case TGSI_OPCODE_ATOMXOR
:
4229 val
^= value
[0].u
[0];
4231 case TGSI_OPCODE_ATOMOR
:
4232 val
|= value
[0].u
[0];
4234 case TGSI_OPCODE_ATOMAND
:
4235 val
&= value
[0].u
[0];
4237 case TGSI_OPCODE_ATOMUMIN
:
4238 val
= MIN2(val
, value
[0].u
[0]);
4240 case TGSI_OPCODE_ATOMUMAX
:
4241 val
= MAX2(val
, value
[0].u
[0]);
4243 case TGSI_OPCODE_ATOMIMIN
:
4244 val
= MIN2(r
[0].i
[0], value
[0].i
[0]);
4246 case TGSI_OPCODE_ATOMIMAX
:
4247 val
= MAX2(r
[0].i
[0], value
[0].i
[0]);
4249 case TGSI_OPCODE_ATOMXCHG
:
4250 val
= value
[0].i
[0];
4252 case TGSI_OPCODE_ATOMCAS
:
4253 if (val
== value
[0].u
[0])
4254 val
= value2
[0].u
[0];
4256 case TGSI_OPCODE_ATOMFADD
:
4257 val
= fui(r
[0].f
[0] + value
[0].f
[0]);
4262 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
4263 if (execmask
& (1 << i
))
4264 memcpy(ptr
, &val
, 4);
4266 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4267 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4268 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4274 exec_atomop(struct tgsi_exec_machine
*mach
,
4275 const struct tgsi_full_instruction
*inst
)
4277 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
4278 exec_atomop_img(mach
, inst
);
4279 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
)
4280 exec_atomop_buf(mach
, inst
);
4281 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
)
4282 exec_atomop_mem(mach
, inst
);
4286 exec_resq_img(struct tgsi_exec_machine
*mach
,
4287 const struct tgsi_full_instruction
*inst
)
4290 union tgsi_exec_channel r
[4];
4293 struct tgsi_image_params params
;
4294 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4296 unit
= fetch_sampler_unit(mach
, inst
, 0);
4298 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4300 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
4301 params
.format
= inst
->Memory
.Format
;
4303 mach
->Image
->get_dims(mach
->Image
, ¶ms
, result
);
4305 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
4306 for (j
= 0; j
< 4; j
++) {
4307 r
[j
].i
[i
] = result
[j
];
4311 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4312 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4313 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
4314 TGSI_EXEC_DATA_INT
);
4320 exec_resq_buf(struct tgsi_exec_machine
*mach
,
4321 const struct tgsi_full_instruction
*inst
)
4324 union tgsi_exec_channel r
[4];
4327 struct tgsi_buffer_params params
;
4328 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4330 unit
= fetch_sampler_unit(mach
, inst
, 0);
4332 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4335 mach
->Buffer
->get_dims(mach
->Buffer
, ¶ms
, &result
);
4337 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
4341 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4342 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4343 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
4344 TGSI_EXEC_DATA_INT
);
4350 exec_resq(struct tgsi_exec_machine
*mach
,
4351 const struct tgsi_full_instruction
*inst
)
4353 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
4354 exec_resq_img(mach
, inst
);
4356 exec_resq_buf(mach
, inst
);
4360 micro_f2u64(union tgsi_double_channel
*dst
,
4361 const union tgsi_exec_channel
*src
)
4363 dst
->u64
[0] = (uint64_t)src
->f
[0];
4364 dst
->u64
[1] = (uint64_t)src
->f
[1];
4365 dst
->u64
[2] = (uint64_t)src
->f
[2];
4366 dst
->u64
[3] = (uint64_t)src
->f
[3];
4370 micro_f2i64(union tgsi_double_channel
*dst
,
4371 const union tgsi_exec_channel
*src
)
4373 dst
->i64
[0] = (int64_t)src
->f
[0];
4374 dst
->i64
[1] = (int64_t)src
->f
[1];
4375 dst
->i64
[2] = (int64_t)src
->f
[2];
4376 dst
->i64
[3] = (int64_t)src
->f
[3];
4380 micro_u2i64(union tgsi_double_channel
*dst
,
4381 const union tgsi_exec_channel
*src
)
4383 dst
->u64
[0] = (uint64_t)src
->u
[0];
4384 dst
->u64
[1] = (uint64_t)src
->u
[1];
4385 dst
->u64
[2] = (uint64_t)src
->u
[2];
4386 dst
->u64
[3] = (uint64_t)src
->u
[3];
4390 micro_i2i64(union tgsi_double_channel
*dst
,
4391 const union tgsi_exec_channel
*src
)
4393 dst
->i64
[0] = (int64_t)src
->i
[0];
4394 dst
->i64
[1] = (int64_t)src
->i
[1];
4395 dst
->i64
[2] = (int64_t)src
->i
[2];
4396 dst
->i64
[3] = (int64_t)src
->i
[3];
4400 micro_d2u64(union tgsi_double_channel
*dst
,
4401 const union tgsi_double_channel
*src
)
4403 dst
->u64
[0] = (uint64_t)src
->d
[0];
4404 dst
->u64
[1] = (uint64_t)src
->d
[1];
4405 dst
->u64
[2] = (uint64_t)src
->d
[2];
4406 dst
->u64
[3] = (uint64_t)src
->d
[3];
4410 micro_d2i64(union tgsi_double_channel
*dst
,
4411 const union tgsi_double_channel
*src
)
4413 dst
->i64
[0] = (int64_t)src
->d
[0];
4414 dst
->i64
[1] = (int64_t)src
->d
[1];
4415 dst
->i64
[2] = (int64_t)src
->d
[2];
4416 dst
->i64
[3] = (int64_t)src
->d
[3];
4420 micro_u642d(union tgsi_double_channel
*dst
,
4421 const union tgsi_double_channel
*src
)
4423 dst
->d
[0] = (double)src
->u64
[0];
4424 dst
->d
[1] = (double)src
->u64
[1];
4425 dst
->d
[2] = (double)src
->u64
[2];
4426 dst
->d
[3] = (double)src
->u64
[3];
4430 micro_i642d(union tgsi_double_channel
*dst
,
4431 const union tgsi_double_channel
*src
)
4433 dst
->d
[0] = (double)src
->i64
[0];
4434 dst
->d
[1] = (double)src
->i64
[1];
4435 dst
->d
[2] = (double)src
->i64
[2];
4436 dst
->d
[3] = (double)src
->i64
[3];
4440 micro_u642f(union tgsi_exec_channel
*dst
,
4441 const union tgsi_double_channel
*src
)
4443 dst
->f
[0] = (float)src
->u64
[0];
4444 dst
->f
[1] = (float)src
->u64
[1];
4445 dst
->f
[2] = (float)src
->u64
[2];
4446 dst
->f
[3] = (float)src
->u64
[3];
4450 micro_i642f(union tgsi_exec_channel
*dst
,
4451 const union tgsi_double_channel
*src
)
4453 dst
->f
[0] = (float)src
->i64
[0];
4454 dst
->f
[1] = (float)src
->i64
[1];
4455 dst
->f
[2] = (float)src
->i64
[2];
4456 dst
->f
[3] = (float)src
->i64
[3];
4460 exec_t_2_64(struct tgsi_exec_machine
*mach
,
4461 const struct tgsi_full_instruction
*inst
,
4463 enum tgsi_exec_datatype src_datatype
)
4465 union tgsi_exec_channel src
;
4466 union tgsi_double_channel dst
;
4468 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
4469 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
4471 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
4473 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
4474 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Y
, src_datatype
);
4476 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
4481 exec_64_2_t(struct tgsi_exec_machine
*mach
,
4482 const struct tgsi_full_instruction
*inst
,
4484 enum tgsi_exec_datatype dst_datatype
)
4486 union tgsi_double_channel src
;
4487 union tgsi_exec_channel dst
;
4488 int wm
= inst
->Dst
[0].Register
.WriteMask
;
4491 for (i
= 0; i
< 2; i
++) {
4494 wm
&= ~(1 << (bit
- 1));
4496 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
4498 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
4500 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, bit
- 1, dst_datatype
);
4506 micro_i2f(union tgsi_exec_channel
*dst
,
4507 const union tgsi_exec_channel
*src
)
4509 dst
->f
[0] = (float)src
->i
[0];
4510 dst
->f
[1] = (float)src
->i
[1];
4511 dst
->f
[2] = (float)src
->i
[2];
4512 dst
->f
[3] = (float)src
->i
[3];
4516 micro_not(union tgsi_exec_channel
*dst
,
4517 const union tgsi_exec_channel
*src
)
4519 dst
->u
[0] = ~src
->u
[0];
4520 dst
->u
[1] = ~src
->u
[1];
4521 dst
->u
[2] = ~src
->u
[2];
4522 dst
->u
[3] = ~src
->u
[3];
4526 micro_shl(union tgsi_exec_channel
*dst
,
4527 const union tgsi_exec_channel
*src0
,
4528 const union tgsi_exec_channel
*src1
)
4530 unsigned masked_count
;
4531 masked_count
= src1
->u
[0] & 0x1f;
4532 dst
->u
[0] = src0
->u
[0] << masked_count
;
4533 masked_count
= src1
->u
[1] & 0x1f;
4534 dst
->u
[1] = src0
->u
[1] << masked_count
;
4535 masked_count
= src1
->u
[2] & 0x1f;
4536 dst
->u
[2] = src0
->u
[2] << masked_count
;
4537 masked_count
= src1
->u
[3] & 0x1f;
4538 dst
->u
[3] = src0
->u
[3] << masked_count
;
4542 micro_and(union tgsi_exec_channel
*dst
,
4543 const union tgsi_exec_channel
*src0
,
4544 const union tgsi_exec_channel
*src1
)
4546 dst
->u
[0] = src0
->u
[0] & src1
->u
[0];
4547 dst
->u
[1] = src0
->u
[1] & src1
->u
[1];
4548 dst
->u
[2] = src0
->u
[2] & src1
->u
[2];
4549 dst
->u
[3] = src0
->u
[3] & src1
->u
[3];
4553 micro_or(union tgsi_exec_channel
*dst
,
4554 const union tgsi_exec_channel
*src0
,
4555 const union tgsi_exec_channel
*src1
)
4557 dst
->u
[0] = src0
->u
[0] | src1
->u
[0];
4558 dst
->u
[1] = src0
->u
[1] | src1
->u
[1];
4559 dst
->u
[2] = src0
->u
[2] | src1
->u
[2];
4560 dst
->u
[3] = src0
->u
[3] | src1
->u
[3];
4564 micro_xor(union tgsi_exec_channel
*dst
,
4565 const union tgsi_exec_channel
*src0
,
4566 const union tgsi_exec_channel
*src1
)
4568 dst
->u
[0] = src0
->u
[0] ^ src1
->u
[0];
4569 dst
->u
[1] = src0
->u
[1] ^ src1
->u
[1];
4570 dst
->u
[2] = src0
->u
[2] ^ src1
->u
[2];
4571 dst
->u
[3] = src0
->u
[3] ^ src1
->u
[3];
4575 micro_mod(union tgsi_exec_channel
*dst
,
4576 const union tgsi_exec_channel
*src0
,
4577 const union tgsi_exec_channel
*src1
)
4579 dst
->i
[0] = src1
->i
[0] ? src0
->i
[0] % src1
->i
[0] : ~0;
4580 dst
->i
[1] = src1
->i
[1] ? src0
->i
[1] % src1
->i
[1] : ~0;
4581 dst
->i
[2] = src1
->i
[2] ? src0
->i
[2] % src1
->i
[2] : ~0;
4582 dst
->i
[3] = src1
->i
[3] ? src0
->i
[3] % src1
->i
[3] : ~0;
4586 micro_f2i(union tgsi_exec_channel
*dst
,
4587 const union tgsi_exec_channel
*src
)
4589 dst
->i
[0] = (int)src
->f
[0];
4590 dst
->i
[1] = (int)src
->f
[1];
4591 dst
->i
[2] = (int)src
->f
[2];
4592 dst
->i
[3] = (int)src
->f
[3];
4596 micro_fseq(union tgsi_exec_channel
*dst
,
4597 const union tgsi_exec_channel
*src0
,
4598 const union tgsi_exec_channel
*src1
)
4600 dst
->u
[0] = src0
->f
[0] == src1
->f
[0] ? ~0 : 0;
4601 dst
->u
[1] = src0
->f
[1] == src1
->f
[1] ? ~0 : 0;
4602 dst
->u
[2] = src0
->f
[2] == src1
->f
[2] ? ~0 : 0;
4603 dst
->u
[3] = src0
->f
[3] == src1
->f
[3] ? ~0 : 0;
4607 micro_fsge(union tgsi_exec_channel
*dst
,
4608 const union tgsi_exec_channel
*src0
,
4609 const union tgsi_exec_channel
*src1
)
4611 dst
->u
[0] = src0
->f
[0] >= src1
->f
[0] ? ~0 : 0;
4612 dst
->u
[1] = src0
->f
[1] >= src1
->f
[1] ? ~0 : 0;
4613 dst
->u
[2] = src0
->f
[2] >= src1
->f
[2] ? ~0 : 0;
4614 dst
->u
[3] = src0
->f
[3] >= src1
->f
[3] ? ~0 : 0;
4618 micro_fslt(union tgsi_exec_channel
*dst
,
4619 const union tgsi_exec_channel
*src0
,
4620 const union tgsi_exec_channel
*src1
)
4622 dst
->u
[0] = src0
->f
[0] < src1
->f
[0] ? ~0 : 0;
4623 dst
->u
[1] = src0
->f
[1] < src1
->f
[1] ? ~0 : 0;
4624 dst
->u
[2] = src0
->f
[2] < src1
->f
[2] ? ~0 : 0;
4625 dst
->u
[3] = src0
->f
[3] < src1
->f
[3] ? ~0 : 0;
4629 micro_fsne(union tgsi_exec_channel
*dst
,
4630 const union tgsi_exec_channel
*src0
,
4631 const union tgsi_exec_channel
*src1
)
4633 dst
->u
[0] = src0
->f
[0] != src1
->f
[0] ? ~0 : 0;
4634 dst
->u
[1] = src0
->f
[1] != src1
->f
[1] ? ~0 : 0;
4635 dst
->u
[2] = src0
->f
[2] != src1
->f
[2] ? ~0 : 0;
4636 dst
->u
[3] = src0
->f
[3] != src1
->f
[3] ? ~0 : 0;
4640 micro_idiv(union tgsi_exec_channel
*dst
,
4641 const union tgsi_exec_channel
*src0
,
4642 const union tgsi_exec_channel
*src1
)
4644 dst
->i
[0] = src1
->i
[0] ? src0
->i
[0] / src1
->i
[0] : 0;
4645 dst
->i
[1] = src1
->i
[1] ? src0
->i
[1] / src1
->i
[1] : 0;
4646 dst
->i
[2] = src1
->i
[2] ? src0
->i
[2] / src1
->i
[2] : 0;
4647 dst
->i
[3] = src1
->i
[3] ? src0
->i
[3] / src1
->i
[3] : 0;
4651 micro_imax(union tgsi_exec_channel
*dst
,
4652 const union tgsi_exec_channel
*src0
,
4653 const union tgsi_exec_channel
*src1
)
4655 dst
->i
[0] = src0
->i
[0] > src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
4656 dst
->i
[1] = src0
->i
[1] > src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
4657 dst
->i
[2] = src0
->i
[2] > src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
4658 dst
->i
[3] = src0
->i
[3] > src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
4662 micro_imin(union tgsi_exec_channel
*dst
,
4663 const union tgsi_exec_channel
*src0
,
4664 const union tgsi_exec_channel
*src1
)
4666 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
4667 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
4668 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
4669 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
4673 micro_isge(union tgsi_exec_channel
*dst
,
4674 const union tgsi_exec_channel
*src0
,
4675 const union tgsi_exec_channel
*src1
)
4677 dst
->i
[0] = src0
->i
[0] >= src1
->i
[0] ? -1 : 0;
4678 dst
->i
[1] = src0
->i
[1] >= src1
->i
[1] ? -1 : 0;
4679 dst
->i
[2] = src0
->i
[2] >= src1
->i
[2] ? -1 : 0;
4680 dst
->i
[3] = src0
->i
[3] >= src1
->i
[3] ? -1 : 0;
4684 micro_ishr(union tgsi_exec_channel
*dst
,
4685 const union tgsi_exec_channel
*src0
,
4686 const union tgsi_exec_channel
*src1
)
4688 unsigned masked_count
;
4689 masked_count
= src1
->i
[0] & 0x1f;
4690 dst
->i
[0] = src0
->i
[0] >> masked_count
;
4691 masked_count
= src1
->i
[1] & 0x1f;
4692 dst
->i
[1] = src0
->i
[1] >> masked_count
;
4693 masked_count
= src1
->i
[2] & 0x1f;
4694 dst
->i
[2] = src0
->i
[2] >> masked_count
;
4695 masked_count
= src1
->i
[3] & 0x1f;
4696 dst
->i
[3] = src0
->i
[3] >> masked_count
;
4700 micro_islt(union tgsi_exec_channel
*dst
,
4701 const union tgsi_exec_channel
*src0
,
4702 const union tgsi_exec_channel
*src1
)
4704 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? -1 : 0;
4705 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? -1 : 0;
4706 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? -1 : 0;
4707 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? -1 : 0;
4711 micro_f2u(union tgsi_exec_channel
*dst
,
4712 const union tgsi_exec_channel
*src
)
4714 dst
->u
[0] = (uint
)src
->f
[0];
4715 dst
->u
[1] = (uint
)src
->f
[1];
4716 dst
->u
[2] = (uint
)src
->f
[2];
4717 dst
->u
[3] = (uint
)src
->f
[3];
4721 micro_u2f(union tgsi_exec_channel
*dst
,
4722 const union tgsi_exec_channel
*src
)
4724 dst
->f
[0] = (float)src
->u
[0];
4725 dst
->f
[1] = (float)src
->u
[1];
4726 dst
->f
[2] = (float)src
->u
[2];
4727 dst
->f
[3] = (float)src
->u
[3];
4731 micro_uadd(union tgsi_exec_channel
*dst
,
4732 const union tgsi_exec_channel
*src0
,
4733 const union tgsi_exec_channel
*src1
)
4735 dst
->u
[0] = src0
->u
[0] + src1
->u
[0];
4736 dst
->u
[1] = src0
->u
[1] + src1
->u
[1];
4737 dst
->u
[2] = src0
->u
[2] + src1
->u
[2];
4738 dst
->u
[3] = src0
->u
[3] + src1
->u
[3];
4742 micro_udiv(union tgsi_exec_channel
*dst
,
4743 const union tgsi_exec_channel
*src0
,
4744 const union tgsi_exec_channel
*src1
)
4746 dst
->u
[0] = src1
->u
[0] ? src0
->u
[0] / src1
->u
[0] : ~0u;
4747 dst
->u
[1] = src1
->u
[1] ? src0
->u
[1] / src1
->u
[1] : ~0u;
4748 dst
->u
[2] = src1
->u
[2] ? src0
->u
[2] / src1
->u
[2] : ~0u;
4749 dst
->u
[3] = src1
->u
[3] ? src0
->u
[3] / src1
->u
[3] : ~0u;
4753 micro_umad(union tgsi_exec_channel
*dst
,
4754 const union tgsi_exec_channel
*src0
,
4755 const union tgsi_exec_channel
*src1
,
4756 const union tgsi_exec_channel
*src2
)
4758 dst
->u
[0] = src0
->u
[0] * src1
->u
[0] + src2
->u
[0];
4759 dst
->u
[1] = src0
->u
[1] * src1
->u
[1] + src2
->u
[1];
4760 dst
->u
[2] = src0
->u
[2] * src1
->u
[2] + src2
->u
[2];
4761 dst
->u
[3] = src0
->u
[3] * src1
->u
[3] + src2
->u
[3];
4765 micro_umax(union tgsi_exec_channel
*dst
,
4766 const union tgsi_exec_channel
*src0
,
4767 const union tgsi_exec_channel
*src1
)
4769 dst
->u
[0] = src0
->u
[0] > src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
4770 dst
->u
[1] = src0
->u
[1] > src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
4771 dst
->u
[2] = src0
->u
[2] > src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
4772 dst
->u
[3] = src0
->u
[3] > src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
4776 micro_umin(union tgsi_exec_channel
*dst
,
4777 const union tgsi_exec_channel
*src0
,
4778 const union tgsi_exec_channel
*src1
)
4780 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
4781 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
4782 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
4783 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
4787 micro_umod(union tgsi_exec_channel
*dst
,
4788 const union tgsi_exec_channel
*src0
,
4789 const union tgsi_exec_channel
*src1
)
4791 dst
->u
[0] = src1
->u
[0] ? src0
->u
[0] % src1
->u
[0] : ~0u;
4792 dst
->u
[1] = src1
->u
[1] ? src0
->u
[1] % src1
->u
[1] : ~0u;
4793 dst
->u
[2] = src1
->u
[2] ? src0
->u
[2] % src1
->u
[2] : ~0u;
4794 dst
->u
[3] = src1
->u
[3] ? src0
->u
[3] % src1
->u
[3] : ~0u;
4798 micro_umul(union tgsi_exec_channel
*dst
,
4799 const union tgsi_exec_channel
*src0
,
4800 const union tgsi_exec_channel
*src1
)
4802 dst
->u
[0] = src0
->u
[0] * src1
->u
[0];
4803 dst
->u
[1] = src0
->u
[1] * src1
->u
[1];
4804 dst
->u
[2] = src0
->u
[2] * src1
->u
[2];
4805 dst
->u
[3] = src0
->u
[3] * src1
->u
[3];
4809 micro_imul_hi(union tgsi_exec_channel
*dst
,
4810 const union tgsi_exec_channel
*src0
,
4811 const union tgsi_exec_channel
*src1
)
4813 #define I64M(x, y) ((((int64_t)x) * ((int64_t)y)) >> 32)
4814 dst
->i
[0] = I64M(src0
->i
[0], src1
->i
[0]);
4815 dst
->i
[1] = I64M(src0
->i
[1], src1
->i
[1]);
4816 dst
->i
[2] = I64M(src0
->i
[2], src1
->i
[2]);
4817 dst
->i
[3] = I64M(src0
->i
[3], src1
->i
[3]);
4822 micro_umul_hi(union tgsi_exec_channel
*dst
,
4823 const union tgsi_exec_channel
*src0
,
4824 const union tgsi_exec_channel
*src1
)
4826 #define U64M(x, y) ((((uint64_t)x) * ((uint64_t)y)) >> 32)
4827 dst
->u
[0] = U64M(src0
->u
[0], src1
->u
[0]);
4828 dst
->u
[1] = U64M(src0
->u
[1], src1
->u
[1]);
4829 dst
->u
[2] = U64M(src0
->u
[2], src1
->u
[2]);
4830 dst
->u
[3] = U64M(src0
->u
[3], src1
->u
[3]);
4835 micro_useq(union tgsi_exec_channel
*dst
,
4836 const union tgsi_exec_channel
*src0
,
4837 const union tgsi_exec_channel
*src1
)
4839 dst
->u
[0] = src0
->u
[0] == src1
->u
[0] ? ~0 : 0;
4840 dst
->u
[1] = src0
->u
[1] == src1
->u
[1] ? ~0 : 0;
4841 dst
->u
[2] = src0
->u
[2] == src1
->u
[2] ? ~0 : 0;
4842 dst
->u
[3] = src0
->u
[3] == src1
->u
[3] ? ~0 : 0;
4846 micro_usge(union tgsi_exec_channel
*dst
,
4847 const union tgsi_exec_channel
*src0
,
4848 const union tgsi_exec_channel
*src1
)
4850 dst
->u
[0] = src0
->u
[0] >= src1
->u
[0] ? ~0 : 0;
4851 dst
->u
[1] = src0
->u
[1] >= src1
->u
[1] ? ~0 : 0;
4852 dst
->u
[2] = src0
->u
[2] >= src1
->u
[2] ? ~0 : 0;
4853 dst
->u
[3] = src0
->u
[3] >= src1
->u
[3] ? ~0 : 0;
4857 micro_ushr(union tgsi_exec_channel
*dst
,
4858 const union tgsi_exec_channel
*src0
,
4859 const union tgsi_exec_channel
*src1
)
4861 unsigned masked_count
;
4862 masked_count
= src1
->u
[0] & 0x1f;
4863 dst
->u
[0] = src0
->u
[0] >> masked_count
;
4864 masked_count
= src1
->u
[1] & 0x1f;
4865 dst
->u
[1] = src0
->u
[1] >> masked_count
;
4866 masked_count
= src1
->u
[2] & 0x1f;
4867 dst
->u
[2] = src0
->u
[2] >> masked_count
;
4868 masked_count
= src1
->u
[3] & 0x1f;
4869 dst
->u
[3] = src0
->u
[3] >> masked_count
;
4873 micro_uslt(union tgsi_exec_channel
*dst
,
4874 const union tgsi_exec_channel
*src0
,
4875 const union tgsi_exec_channel
*src1
)
4877 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? ~0 : 0;
4878 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? ~0 : 0;
4879 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? ~0 : 0;
4880 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? ~0 : 0;
4884 micro_usne(union tgsi_exec_channel
*dst
,
4885 const union tgsi_exec_channel
*src0
,
4886 const union tgsi_exec_channel
*src1
)
4888 dst
->u
[0] = src0
->u
[0] != src1
->u
[0] ? ~0 : 0;
4889 dst
->u
[1] = src0
->u
[1] != src1
->u
[1] ? ~0 : 0;
4890 dst
->u
[2] = src0
->u
[2] != src1
->u
[2] ? ~0 : 0;
4891 dst
->u
[3] = src0
->u
[3] != src1
->u
[3] ? ~0 : 0;
4895 micro_uarl(union tgsi_exec_channel
*dst
,
4896 const union tgsi_exec_channel
*src
)
4898 dst
->i
[0] = src
->u
[0];
4899 dst
->i
[1] = src
->u
[1];
4900 dst
->i
[2] = src
->u
[2];
4901 dst
->i
[3] = src
->u
[3];
4905 * Signed bitfield extract (i.e. sign-extend the extracted bits)
4908 micro_ibfe(union tgsi_exec_channel
*dst
,
4909 const union tgsi_exec_channel
*src0
,
4910 const union tgsi_exec_channel
*src1
,
4911 const union tgsi_exec_channel
*src2
)
4914 for (i
= 0; i
< 4; i
++) {
4915 int width
= src2
->i
[i
] & 0x1f;
4916 int offset
= src1
->i
[i
] & 0x1f;
4919 else if (width
+ offset
< 32)
4920 dst
->i
[i
] = (src0
->i
[i
] << (32 - width
- offset
)) >> (32 - width
);
4922 dst
->i
[i
] = src0
->i
[i
] >> offset
;
4927 * Unsigned bitfield extract
4930 micro_ubfe(union tgsi_exec_channel
*dst
,
4931 const union tgsi_exec_channel
*src0
,
4932 const union tgsi_exec_channel
*src1
,
4933 const union tgsi_exec_channel
*src2
)
4936 for (i
= 0; i
< 4; i
++) {
4937 int width
= src2
->u
[i
] & 0x1f;
4938 int offset
= src1
->u
[i
] & 0x1f;
4941 else if (width
+ offset
< 32)
4942 dst
->u
[i
] = (src0
->u
[i
] << (32 - width
- offset
)) >> (32 - width
);
4944 dst
->u
[i
] = src0
->u
[i
] >> offset
;
4949 * Bitfield insert: copy low bits from src1 into a region of src0.
4952 micro_bfi(union tgsi_exec_channel
*dst
,
4953 const union tgsi_exec_channel
*src0
,
4954 const union tgsi_exec_channel
*src1
,
4955 const union tgsi_exec_channel
*src2
,
4956 const union tgsi_exec_channel
*src3
)
4959 for (i
= 0; i
< 4; i
++) {
4960 int width
= src3
->u
[i
] & 0x1f;
4961 int offset
= src2
->u
[i
] & 0x1f;
4962 int bitmask
= ((1 << width
) - 1) << offset
;
4963 dst
->u
[i
] = ((src1
->u
[i
] << offset
) & bitmask
) | (src0
->u
[i
] & ~bitmask
);
4968 micro_brev(union tgsi_exec_channel
*dst
,
4969 const union tgsi_exec_channel
*src
)
4971 dst
->u
[0] = util_bitreverse(src
->u
[0]);
4972 dst
->u
[1] = util_bitreverse(src
->u
[1]);
4973 dst
->u
[2] = util_bitreverse(src
->u
[2]);
4974 dst
->u
[3] = util_bitreverse(src
->u
[3]);
4978 micro_popc(union tgsi_exec_channel
*dst
,
4979 const union tgsi_exec_channel
*src
)
4981 dst
->u
[0] = util_bitcount(src
->u
[0]);
4982 dst
->u
[1] = util_bitcount(src
->u
[1]);
4983 dst
->u
[2] = util_bitcount(src
->u
[2]);
4984 dst
->u
[3] = util_bitcount(src
->u
[3]);
4988 micro_lsb(union tgsi_exec_channel
*dst
,
4989 const union tgsi_exec_channel
*src
)
4991 dst
->i
[0] = ffs(src
->u
[0]) - 1;
4992 dst
->i
[1] = ffs(src
->u
[1]) - 1;
4993 dst
->i
[2] = ffs(src
->u
[2]) - 1;
4994 dst
->i
[3] = ffs(src
->u
[3]) - 1;
4998 micro_imsb(union tgsi_exec_channel
*dst
,
4999 const union tgsi_exec_channel
*src
)
5001 dst
->i
[0] = util_last_bit_signed(src
->i
[0]) - 1;
5002 dst
->i
[1] = util_last_bit_signed(src
->i
[1]) - 1;
5003 dst
->i
[2] = util_last_bit_signed(src
->i
[2]) - 1;
5004 dst
->i
[3] = util_last_bit_signed(src
->i
[3]) - 1;
5008 micro_umsb(union tgsi_exec_channel
*dst
,
5009 const union tgsi_exec_channel
*src
)
5011 dst
->i
[0] = util_last_bit(src
->u
[0]) - 1;
5012 dst
->i
[1] = util_last_bit(src
->u
[1]) - 1;
5013 dst
->i
[2] = util_last_bit(src
->u
[2]) - 1;
5014 dst
->i
[3] = util_last_bit(src
->u
[3]) - 1;
5018 * Execute a TGSI instruction.
5019 * Returns TRUE if a barrier instruction is hit,
5024 struct tgsi_exec_machine
*mach
,
5025 const struct tgsi_full_instruction
*inst
,
5028 union tgsi_exec_channel r
[10];
5032 switch (inst
->Instruction
.Opcode
) {
5033 case TGSI_OPCODE_ARL
:
5034 exec_vector_unary(mach
, inst
, micro_arl
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
5037 case TGSI_OPCODE_MOV
:
5038 exec_vector_unary(mach
, inst
, micro_mov
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5041 case TGSI_OPCODE_LIT
:
5042 exec_lit(mach
, inst
);
5045 case TGSI_OPCODE_RCP
:
5046 exec_scalar_unary(mach
, inst
, micro_rcp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5049 case TGSI_OPCODE_RSQ
:
5050 exec_scalar_unary(mach
, inst
, micro_rsq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5053 case TGSI_OPCODE_EXP
:
5054 exec_exp(mach
, inst
);
5057 case TGSI_OPCODE_LOG
:
5058 exec_log(mach
, inst
);
5061 case TGSI_OPCODE_MUL
:
5062 exec_vector_binary(mach
, inst
, micro_mul
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5065 case TGSI_OPCODE_ADD
:
5066 exec_vector_binary(mach
, inst
, micro_add
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5069 case TGSI_OPCODE_DP3
:
5070 exec_dp3(mach
, inst
);
5073 case TGSI_OPCODE_DP4
:
5074 exec_dp4(mach
, inst
);
5077 case TGSI_OPCODE_DST
:
5078 exec_dst(mach
, inst
);
5081 case TGSI_OPCODE_MIN
:
5082 exec_vector_binary(mach
, inst
, micro_min
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5085 case TGSI_OPCODE_MAX
:
5086 exec_vector_binary(mach
, inst
, micro_max
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5089 case TGSI_OPCODE_SLT
:
5090 exec_vector_binary(mach
, inst
, micro_slt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5093 case TGSI_OPCODE_SGE
:
5094 exec_vector_binary(mach
, inst
, micro_sge
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5097 case TGSI_OPCODE_MAD
:
5098 exec_vector_trinary(mach
, inst
, micro_mad
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5101 case TGSI_OPCODE_LRP
:
5102 exec_vector_trinary(mach
, inst
, micro_lrp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5105 case TGSI_OPCODE_SQRT
:
5106 exec_scalar_unary(mach
, inst
, micro_sqrt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5109 case TGSI_OPCODE_FRC
:
5110 exec_vector_unary(mach
, inst
, micro_frc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5113 case TGSI_OPCODE_FLR
:
5114 exec_vector_unary(mach
, inst
, micro_flr
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5117 case TGSI_OPCODE_ROUND
:
5118 exec_vector_unary(mach
, inst
, micro_rnd
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5121 case TGSI_OPCODE_EX2
:
5122 exec_scalar_unary(mach
, inst
, micro_exp2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5125 case TGSI_OPCODE_LG2
:
5126 exec_scalar_unary(mach
, inst
, micro_lg2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5129 case TGSI_OPCODE_POW
:
5130 exec_scalar_binary(mach
, inst
, micro_pow
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5133 case TGSI_OPCODE_LDEXP
:
5134 exec_vector_binary(mach
, inst
, micro_ldexp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5137 case TGSI_OPCODE_COS
:
5138 exec_scalar_unary(mach
, inst
, micro_cos
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5141 case TGSI_OPCODE_DDX
:
5142 exec_vector_unary(mach
, inst
, micro_ddx
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5145 case TGSI_OPCODE_DDY
:
5146 exec_vector_unary(mach
, inst
, micro_ddy
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5149 case TGSI_OPCODE_KILL
:
5153 case TGSI_OPCODE_KILL_IF
:
5154 exec_kill_if (mach
, inst
);
5157 case TGSI_OPCODE_PK2H
:
5158 exec_pk2h(mach
, inst
);
5161 case TGSI_OPCODE_PK2US
:
5165 case TGSI_OPCODE_PK4B
:
5169 case TGSI_OPCODE_PK4UB
:
5173 case TGSI_OPCODE_SEQ
:
5174 exec_vector_binary(mach
, inst
, micro_seq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5177 case TGSI_OPCODE_SGT
:
5178 exec_vector_binary(mach
, inst
, micro_sgt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5181 case TGSI_OPCODE_SIN
:
5182 exec_scalar_unary(mach
, inst
, micro_sin
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5185 case TGSI_OPCODE_SLE
:
5186 exec_vector_binary(mach
, inst
, micro_sle
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5189 case TGSI_OPCODE_SNE
:
5190 exec_vector_binary(mach
, inst
, micro_sne
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5193 case TGSI_OPCODE_TEX
:
5194 /* simple texture lookup */
5195 /* src[0] = texcoord */
5196 /* src[1] = sampler unit */
5197 exec_tex(mach
, inst
, TEX_MODIFIER_NONE
, 1);
5200 case TGSI_OPCODE_TXB
:
5201 /* Texture lookup with lod bias */
5202 /* src[0] = texcoord (src[0].w = LOD bias) */
5203 /* src[1] = sampler unit */
5204 exec_tex(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, 1);
5207 case TGSI_OPCODE_TXD
:
5208 /* Texture lookup with explict partial derivatives */
5209 /* src[0] = texcoord */
5210 /* src[1] = d[strq]/dx */
5211 /* src[2] = d[strq]/dy */
5212 /* src[3] = sampler unit */
5213 exec_txd(mach
, inst
);
5216 case TGSI_OPCODE_TXL
:
5217 /* Texture lookup with explit LOD */
5218 /* src[0] = texcoord (src[0].w = LOD) */
5219 /* src[1] = sampler unit */
5220 exec_tex(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, 1);
5223 case TGSI_OPCODE_TXP
:
5224 /* Texture lookup with projection */
5225 /* src[0] = texcoord (src[0].w = projection) */
5226 /* src[1] = sampler unit */
5227 exec_tex(mach
, inst
, TEX_MODIFIER_PROJECTED
, 1);
5230 case TGSI_OPCODE_TG4
:
5231 /* src[0] = texcoord */
5232 /* src[1] = component */
5233 /* src[2] = sampler unit */
5234 exec_tex(mach
, inst
, TEX_MODIFIER_GATHER
, 2);
5237 case TGSI_OPCODE_LODQ
:
5238 /* src[0] = texcoord */
5239 /* src[1] = sampler unit */
5240 exec_lodq(mach
, inst
);
5243 case TGSI_OPCODE_UP2H
:
5244 exec_up2h(mach
, inst
);
5247 case TGSI_OPCODE_UP2US
:
5251 case TGSI_OPCODE_UP4B
:
5255 case TGSI_OPCODE_UP4UB
:
5259 case TGSI_OPCODE_ARR
:
5260 exec_vector_unary(mach
, inst
, micro_arr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
5263 case TGSI_OPCODE_CAL
:
5264 /* skip the call if no execution channels are enabled */
5265 if (mach
->ExecMask
) {
5268 /* First, record the depths of the execution stacks.
5269 * This is important for deeply nested/looped return statements.
5270 * We have to unwind the stacks by the correct amount. For a
5271 * real code generator, we could determine the number of entries
5272 * to pop off each stack with simple static analysis and avoid
5273 * implementing this data structure at run time.
5275 mach
->CallStack
[mach
->CallStackTop
].CondStackTop
= mach
->CondStackTop
;
5276 mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
= mach
->LoopStackTop
;
5277 mach
->CallStack
[mach
->CallStackTop
].ContStackTop
= mach
->ContStackTop
;
5278 mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
= mach
->SwitchStackTop
;
5279 mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
= mach
->BreakStackTop
;
5280 /* note that PC was already incremented above */
5281 mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
= *pc
;
5283 mach
->CallStackTop
++;
5285 /* Second, push the Cond, Loop, Cont, Func stacks */
5286 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
5287 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5288 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5289 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
5290 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
5291 assert(mach
->FuncStackTop
< TGSI_EXEC_MAX_CALL_NESTING
);
5293 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
5294 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
5295 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
5296 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
5297 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
5298 mach
->FuncStack
[mach
->FuncStackTop
++] = mach
->FuncMask
;
5300 /* Finally, jump to the subroutine. The label is a pointer
5301 * (an instruction number) to the BGNSUB instruction.
5303 *pc
= inst
->Label
.Label
;
5304 assert(mach
->Instructions
[*pc
].Instruction
.Opcode
5305 == TGSI_OPCODE_BGNSUB
);
5309 case TGSI_OPCODE_RET
:
5310 mach
->FuncMask
&= ~mach
->ExecMask
;
5311 UPDATE_EXEC_MASK(mach
);
5313 if (mach
->FuncMask
== 0x0) {
5314 /* really return now (otherwise, keep executing */
5316 if (mach
->CallStackTop
== 0) {
5317 /* returning from main() */
5318 mach
->CondStackTop
= 0;
5319 mach
->LoopStackTop
= 0;
5320 mach
->ContStackTop
= 0;
5321 mach
->LoopLabelStackTop
= 0;
5322 mach
->SwitchStackTop
= 0;
5323 mach
->BreakStackTop
= 0;
5328 assert(mach
->CallStackTop
> 0);
5329 mach
->CallStackTop
--;
5331 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
5332 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
5334 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
5335 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
5337 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
5338 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
5340 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
5341 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
5343 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
5344 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
5346 assert(mach
->FuncStackTop
> 0);
5347 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
5349 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
5351 UPDATE_EXEC_MASK(mach
);
5355 case TGSI_OPCODE_SSG
:
5356 exec_vector_unary(mach
, inst
, micro_sgn
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5359 case TGSI_OPCODE_CMP
:
5360 exec_vector_trinary(mach
, inst
, micro_cmp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5363 case TGSI_OPCODE_DIV
:
5364 exec_vector_binary(mach
, inst
, micro_div
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5367 case TGSI_OPCODE_DP2
:
5368 exec_dp2(mach
, inst
);
5371 case TGSI_OPCODE_IF
:
5373 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
5374 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
5375 FETCH( &r
[0], 0, TGSI_CHAN_X
);
5376 /* update CondMask */
5378 mach
->CondMask
&= ~0x1;
5381 mach
->CondMask
&= ~0x2;
5384 mach
->CondMask
&= ~0x4;
5387 mach
->CondMask
&= ~0x8;
5389 UPDATE_EXEC_MASK(mach
);
5390 /* Todo: If CondMask==0, jump to ELSE */
5393 case TGSI_OPCODE_UIF
:
5395 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
5396 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
5397 IFETCH( &r
[0], 0, TGSI_CHAN_X
);
5398 /* update CondMask */
5400 mach
->CondMask
&= ~0x1;
5403 mach
->CondMask
&= ~0x2;
5406 mach
->CondMask
&= ~0x4;
5409 mach
->CondMask
&= ~0x8;
5411 UPDATE_EXEC_MASK(mach
);
5412 /* Todo: If CondMask==0, jump to ELSE */
5415 case TGSI_OPCODE_ELSE
:
5416 /* invert CondMask wrt previous mask */
5419 assert(mach
->CondStackTop
> 0);
5420 prevMask
= mach
->CondStack
[mach
->CondStackTop
- 1];
5421 mach
->CondMask
= ~mach
->CondMask
& prevMask
;
5422 UPDATE_EXEC_MASK(mach
);
5423 /* Todo: If CondMask==0, jump to ENDIF */
5427 case TGSI_OPCODE_ENDIF
:
5429 assert(mach
->CondStackTop
> 0);
5430 mach
->CondMask
= mach
->CondStack
[--mach
->CondStackTop
];
5431 UPDATE_EXEC_MASK(mach
);
5434 case TGSI_OPCODE_END
:
5435 /* make sure we end primitives which haven't
5436 * been explicitly emitted */
5437 conditional_emit_primitive(mach
);
5438 /* halt execution */
5442 case TGSI_OPCODE_CEIL
:
5443 exec_vector_unary(mach
, inst
, micro_ceil
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5446 case TGSI_OPCODE_I2F
:
5447 exec_vector_unary(mach
, inst
, micro_i2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_INT
);
5450 case TGSI_OPCODE_NOT
:
5451 exec_vector_unary(mach
, inst
, micro_not
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5454 case TGSI_OPCODE_TRUNC
:
5455 exec_vector_unary(mach
, inst
, micro_trunc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5458 case TGSI_OPCODE_SHL
:
5459 exec_vector_binary(mach
, inst
, micro_shl
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5462 case TGSI_OPCODE_AND
:
5463 exec_vector_binary(mach
, inst
, micro_and
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5466 case TGSI_OPCODE_OR
:
5467 exec_vector_binary(mach
, inst
, micro_or
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5470 case TGSI_OPCODE_MOD
:
5471 exec_vector_binary(mach
, inst
, micro_mod
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5474 case TGSI_OPCODE_XOR
:
5475 exec_vector_binary(mach
, inst
, micro_xor
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5478 case TGSI_OPCODE_TXF
:
5479 exec_txf(mach
, inst
);
5482 case TGSI_OPCODE_TXQ
:
5483 exec_txq(mach
, inst
);
5486 case TGSI_OPCODE_EMIT
:
5490 case TGSI_OPCODE_ENDPRIM
:
5491 emit_primitive(mach
);
5494 case TGSI_OPCODE_BGNLOOP
:
5495 /* push LoopMask and ContMasks */
5496 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5497 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5498 assert(mach
->LoopLabelStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5499 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
5501 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
5502 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
5503 mach
->LoopLabelStack
[mach
->LoopLabelStackTop
++] = *pc
- 1;
5504 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
5505 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_LOOP
;
5508 case TGSI_OPCODE_ENDLOOP
:
5509 /* Restore ContMask, but don't pop */
5510 assert(mach
->ContStackTop
> 0);
5511 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
- 1];
5512 UPDATE_EXEC_MASK(mach
);
5513 if (mach
->ExecMask
) {
5514 /* repeat loop: jump to instruction just past BGNLOOP */
5515 assert(mach
->LoopLabelStackTop
> 0);
5516 *pc
= mach
->LoopLabelStack
[mach
->LoopLabelStackTop
- 1] + 1;
5519 /* exit loop: pop LoopMask */
5520 assert(mach
->LoopStackTop
> 0);
5521 mach
->LoopMask
= mach
->LoopStack
[--mach
->LoopStackTop
];
5523 assert(mach
->ContStackTop
> 0);
5524 mach
->ContMask
= mach
->ContStack
[--mach
->ContStackTop
];
5525 assert(mach
->LoopLabelStackTop
> 0);
5526 --mach
->LoopLabelStackTop
;
5528 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
5530 UPDATE_EXEC_MASK(mach
);
5533 case TGSI_OPCODE_BRK
:
5537 case TGSI_OPCODE_CONT
:
5538 /* turn off cont channels for each enabled exec channel */
5539 mach
->ContMask
&= ~mach
->ExecMask
;
5540 /* Todo: if mach->LoopMask == 0, jump to end of loop */
5541 UPDATE_EXEC_MASK(mach
);
5544 case TGSI_OPCODE_BGNSUB
:
5548 case TGSI_OPCODE_ENDSUB
:
5550 * XXX: This really should be a no-op. We should never reach this opcode.
5553 assert(mach
->CallStackTop
> 0);
5554 mach
->CallStackTop
--;
5556 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
5557 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
5559 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
5560 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
5562 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
5563 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
5565 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
5566 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
5568 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
5569 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
5571 assert(mach
->FuncStackTop
> 0);
5572 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
5574 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
5576 UPDATE_EXEC_MASK(mach
);
5579 case TGSI_OPCODE_NOP
:
5582 case TGSI_OPCODE_F2I
:
5583 exec_vector_unary(mach
, inst
, micro_f2i
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
5586 case TGSI_OPCODE_FSEQ
:
5587 exec_vector_binary(mach
, inst
, micro_fseq
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5590 case TGSI_OPCODE_FSGE
:
5591 exec_vector_binary(mach
, inst
, micro_fsge
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5594 case TGSI_OPCODE_FSLT
:
5595 exec_vector_binary(mach
, inst
, micro_fslt
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5598 case TGSI_OPCODE_FSNE
:
5599 exec_vector_binary(mach
, inst
, micro_fsne
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5602 case TGSI_OPCODE_IDIV
:
5603 exec_vector_binary(mach
, inst
, micro_idiv
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5606 case TGSI_OPCODE_IMAX
:
5607 exec_vector_binary(mach
, inst
, micro_imax
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5610 case TGSI_OPCODE_IMIN
:
5611 exec_vector_binary(mach
, inst
, micro_imin
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5614 case TGSI_OPCODE_INEG
:
5615 exec_vector_unary(mach
, inst
, micro_ineg
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5618 case TGSI_OPCODE_ISGE
:
5619 exec_vector_binary(mach
, inst
, micro_isge
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5622 case TGSI_OPCODE_ISHR
:
5623 exec_vector_binary(mach
, inst
, micro_ishr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5626 case TGSI_OPCODE_ISLT
:
5627 exec_vector_binary(mach
, inst
, micro_islt
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5630 case TGSI_OPCODE_F2U
:
5631 exec_vector_unary(mach
, inst
, micro_f2u
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5634 case TGSI_OPCODE_U2F
:
5635 exec_vector_unary(mach
, inst
, micro_u2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_UINT
);
5638 case TGSI_OPCODE_UADD
:
5639 exec_vector_binary(mach
, inst
, micro_uadd
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5642 case TGSI_OPCODE_UDIV
:
5643 exec_vector_binary(mach
, inst
, micro_udiv
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5646 case TGSI_OPCODE_UMAD
:
5647 exec_vector_trinary(mach
, inst
, micro_umad
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5650 case TGSI_OPCODE_UMAX
:
5651 exec_vector_binary(mach
, inst
, micro_umax
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5654 case TGSI_OPCODE_UMIN
:
5655 exec_vector_binary(mach
, inst
, micro_umin
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5658 case TGSI_OPCODE_UMOD
:
5659 exec_vector_binary(mach
, inst
, micro_umod
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5662 case TGSI_OPCODE_UMUL
:
5663 exec_vector_binary(mach
, inst
, micro_umul
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5666 case TGSI_OPCODE_IMUL_HI
:
5667 exec_vector_binary(mach
, inst
, micro_imul_hi
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5670 case TGSI_OPCODE_UMUL_HI
:
5671 exec_vector_binary(mach
, inst
, micro_umul_hi
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5674 case TGSI_OPCODE_USEQ
:
5675 exec_vector_binary(mach
, inst
, micro_useq
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5678 case TGSI_OPCODE_USGE
:
5679 exec_vector_binary(mach
, inst
, micro_usge
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5682 case TGSI_OPCODE_USHR
:
5683 exec_vector_binary(mach
, inst
, micro_ushr
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5686 case TGSI_OPCODE_USLT
:
5687 exec_vector_binary(mach
, inst
, micro_uslt
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5690 case TGSI_OPCODE_USNE
:
5691 exec_vector_binary(mach
, inst
, micro_usne
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5694 case TGSI_OPCODE_SWITCH
:
5695 exec_switch(mach
, inst
);
5698 case TGSI_OPCODE_CASE
:
5699 exec_case(mach
, inst
);
5702 case TGSI_OPCODE_DEFAULT
:
5706 case TGSI_OPCODE_ENDSWITCH
:
5707 exec_endswitch(mach
);
5710 case TGSI_OPCODE_SAMPLE_I
:
5711 exec_txf(mach
, inst
);
5714 case TGSI_OPCODE_SAMPLE_I_MS
:
5715 exec_txf(mach
, inst
);
5718 case TGSI_OPCODE_SAMPLE
:
5719 exec_sample(mach
, inst
, TEX_MODIFIER_NONE
, FALSE
);
5722 case TGSI_OPCODE_SAMPLE_B
:
5723 exec_sample(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, FALSE
);
5726 case TGSI_OPCODE_SAMPLE_C
:
5727 exec_sample(mach
, inst
, TEX_MODIFIER_NONE
, TRUE
);
5730 case TGSI_OPCODE_SAMPLE_C_LZ
:
5731 exec_sample(mach
, inst
, TEX_MODIFIER_LEVEL_ZERO
, TRUE
);
5734 case TGSI_OPCODE_SAMPLE_D
:
5735 exec_sample_d(mach
, inst
);
5738 case TGSI_OPCODE_SAMPLE_L
:
5739 exec_sample(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, FALSE
);
5742 case TGSI_OPCODE_GATHER4
:
5743 exec_sample(mach
, inst
, TEX_MODIFIER_GATHER
, FALSE
);
5746 case TGSI_OPCODE_SVIEWINFO
:
5747 exec_txq(mach
, inst
);
5750 case TGSI_OPCODE_SAMPLE_POS
:
5754 case TGSI_OPCODE_SAMPLE_INFO
:
5758 case TGSI_OPCODE_LOD
:
5759 exec_lodq(mach
, inst
);
5762 case TGSI_OPCODE_UARL
:
5763 exec_vector_unary(mach
, inst
, micro_uarl
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
5766 case TGSI_OPCODE_UCMP
:
5767 exec_ucmp(mach
, inst
);
5770 case TGSI_OPCODE_IABS
:
5771 exec_vector_unary(mach
, inst
, micro_iabs
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5774 case TGSI_OPCODE_ISSG
:
5775 exec_vector_unary(mach
, inst
, micro_isgn
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5778 case TGSI_OPCODE_TEX2
:
5779 /* simple texture lookup */
5780 /* src[0] = texcoord */
5781 /* src[1] = compare */
5782 /* src[2] = sampler unit */
5783 exec_tex(mach
, inst
, TEX_MODIFIER_NONE
, 2);
5785 case TGSI_OPCODE_TXB2
:
5786 /* simple texture lookup */
5787 /* src[0] = texcoord */
5789 /* src[2] = sampler unit */
5790 exec_tex(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, 2);
5792 case TGSI_OPCODE_TXL2
:
5793 /* simple texture lookup */
5794 /* src[0] = texcoord */
5796 /* src[2] = sampler unit */
5797 exec_tex(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, 2);
5800 case TGSI_OPCODE_IBFE
:
5801 exec_vector_trinary(mach
, inst
, micro_ibfe
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5803 case TGSI_OPCODE_UBFE
:
5804 exec_vector_trinary(mach
, inst
, micro_ubfe
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5806 case TGSI_OPCODE_BFI
:
5807 exec_vector_quaternary(mach
, inst
, micro_bfi
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5809 case TGSI_OPCODE_BREV
:
5810 exec_vector_unary(mach
, inst
, micro_brev
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5812 case TGSI_OPCODE_POPC
:
5813 exec_vector_unary(mach
, inst
, micro_popc
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5815 case TGSI_OPCODE_LSB
:
5816 exec_vector_unary(mach
, inst
, micro_lsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
5818 case TGSI_OPCODE_IMSB
:
5819 exec_vector_unary(mach
, inst
, micro_imsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5821 case TGSI_OPCODE_UMSB
:
5822 exec_vector_unary(mach
, inst
, micro_umsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
5825 case TGSI_OPCODE_F2D
:
5826 exec_t_2_64(mach
, inst
, micro_f2d
, TGSI_EXEC_DATA_FLOAT
);
5829 case TGSI_OPCODE_D2F
:
5830 exec_64_2_t(mach
, inst
, micro_d2f
, TGSI_EXEC_DATA_FLOAT
);
5833 case TGSI_OPCODE_DABS
:
5834 exec_double_unary(mach
, inst
, micro_dabs
);
5837 case TGSI_OPCODE_DNEG
:
5838 exec_double_unary(mach
, inst
, micro_dneg
);
5841 case TGSI_OPCODE_DADD
:
5842 exec_double_binary(mach
, inst
, micro_dadd
, TGSI_EXEC_DATA_DOUBLE
);
5845 case TGSI_OPCODE_DDIV
:
5846 exec_double_binary(mach
, inst
, micro_ddiv
, TGSI_EXEC_DATA_DOUBLE
);
5849 case TGSI_OPCODE_DMUL
:
5850 exec_double_binary(mach
, inst
, micro_dmul
, TGSI_EXEC_DATA_DOUBLE
);
5853 case TGSI_OPCODE_DMAX
:
5854 exec_double_binary(mach
, inst
, micro_dmax
, TGSI_EXEC_DATA_DOUBLE
);
5857 case TGSI_OPCODE_DMIN
:
5858 exec_double_binary(mach
, inst
, micro_dmin
, TGSI_EXEC_DATA_DOUBLE
);
5861 case TGSI_OPCODE_DSLT
:
5862 exec_double_binary(mach
, inst
, micro_dslt
, TGSI_EXEC_DATA_UINT
);
5865 case TGSI_OPCODE_DSGE
:
5866 exec_double_binary(mach
, inst
, micro_dsge
, TGSI_EXEC_DATA_UINT
);
5869 case TGSI_OPCODE_DSEQ
:
5870 exec_double_binary(mach
, inst
, micro_dseq
, TGSI_EXEC_DATA_UINT
);
5873 case TGSI_OPCODE_DSNE
:
5874 exec_double_binary(mach
, inst
, micro_dsne
, TGSI_EXEC_DATA_UINT
);
5877 case TGSI_OPCODE_DRCP
:
5878 exec_double_unary(mach
, inst
, micro_drcp
);
5881 case TGSI_OPCODE_DSQRT
:
5882 exec_double_unary(mach
, inst
, micro_dsqrt
);
5885 case TGSI_OPCODE_DRSQ
:
5886 exec_double_unary(mach
, inst
, micro_drsq
);
5889 case TGSI_OPCODE_DMAD
:
5890 exec_double_trinary(mach
, inst
, micro_dmad
);
5893 case TGSI_OPCODE_DFRAC
:
5894 exec_double_unary(mach
, inst
, micro_dfrac
);
5897 case TGSI_OPCODE_DLDEXP
:
5898 exec_dldexp(mach
, inst
);
5901 case TGSI_OPCODE_DFRACEXP
:
5902 exec_dfracexp(mach
, inst
);
5905 case TGSI_OPCODE_I2D
:
5906 exec_t_2_64(mach
, inst
, micro_i2d
, TGSI_EXEC_DATA_INT
);
5909 case TGSI_OPCODE_D2I
:
5910 exec_64_2_t(mach
, inst
, micro_d2i
, TGSI_EXEC_DATA_INT
);
5913 case TGSI_OPCODE_U2D
:
5914 exec_t_2_64(mach
, inst
, micro_u2d
, TGSI_EXEC_DATA_UINT
);
5917 case TGSI_OPCODE_D2U
:
5918 exec_64_2_t(mach
, inst
, micro_d2u
, TGSI_EXEC_DATA_INT
);
5921 case TGSI_OPCODE_LOAD
:
5922 exec_load(mach
, inst
);
5925 case TGSI_OPCODE_STORE
:
5926 exec_store(mach
, inst
);
5929 case TGSI_OPCODE_ATOMUADD
:
5930 case TGSI_OPCODE_ATOMXCHG
:
5931 case TGSI_OPCODE_ATOMCAS
:
5932 case TGSI_OPCODE_ATOMAND
:
5933 case TGSI_OPCODE_ATOMOR
:
5934 case TGSI_OPCODE_ATOMXOR
:
5935 case TGSI_OPCODE_ATOMUMIN
:
5936 case TGSI_OPCODE_ATOMUMAX
:
5937 case TGSI_OPCODE_ATOMIMIN
:
5938 case TGSI_OPCODE_ATOMIMAX
:
5939 case TGSI_OPCODE_ATOMFADD
:
5940 exec_atomop(mach
, inst
);
5943 case TGSI_OPCODE_RESQ
:
5944 exec_resq(mach
, inst
);
5946 case TGSI_OPCODE_BARRIER
:
5947 case TGSI_OPCODE_MEMBAR
:
5951 case TGSI_OPCODE_I64ABS
:
5952 exec_double_unary(mach
, inst
, micro_i64abs
);
5955 case TGSI_OPCODE_I64SSG
:
5956 exec_double_unary(mach
, inst
, micro_i64sgn
);
5959 case TGSI_OPCODE_I64NEG
:
5960 exec_double_unary(mach
, inst
, micro_i64neg
);
5963 case TGSI_OPCODE_U64SEQ
:
5964 exec_double_binary(mach
, inst
, micro_u64seq
, TGSI_EXEC_DATA_UINT
);
5967 case TGSI_OPCODE_U64SNE
:
5968 exec_double_binary(mach
, inst
, micro_u64sne
, TGSI_EXEC_DATA_UINT
);
5971 case TGSI_OPCODE_I64SLT
:
5972 exec_double_binary(mach
, inst
, micro_i64slt
, TGSI_EXEC_DATA_UINT
);
5974 case TGSI_OPCODE_U64SLT
:
5975 exec_double_binary(mach
, inst
, micro_u64slt
, TGSI_EXEC_DATA_UINT
);
5978 case TGSI_OPCODE_I64SGE
:
5979 exec_double_binary(mach
, inst
, micro_i64sge
, TGSI_EXEC_DATA_UINT
);
5981 case TGSI_OPCODE_U64SGE
:
5982 exec_double_binary(mach
, inst
, micro_u64sge
, TGSI_EXEC_DATA_UINT
);
5985 case TGSI_OPCODE_I64MIN
:
5986 exec_double_binary(mach
, inst
, micro_i64min
, TGSI_EXEC_DATA_INT64
);
5988 case TGSI_OPCODE_U64MIN
:
5989 exec_double_binary(mach
, inst
, micro_u64min
, TGSI_EXEC_DATA_UINT64
);
5991 case TGSI_OPCODE_I64MAX
:
5992 exec_double_binary(mach
, inst
, micro_i64max
, TGSI_EXEC_DATA_INT64
);
5994 case TGSI_OPCODE_U64MAX
:
5995 exec_double_binary(mach
, inst
, micro_u64max
, TGSI_EXEC_DATA_UINT64
);
5997 case TGSI_OPCODE_U64ADD
:
5998 exec_double_binary(mach
, inst
, micro_u64add
, TGSI_EXEC_DATA_UINT64
);
6000 case TGSI_OPCODE_U64MUL
:
6001 exec_double_binary(mach
, inst
, micro_u64mul
, TGSI_EXEC_DATA_UINT64
);
6003 case TGSI_OPCODE_U64SHL
:
6004 exec_arg0_64_arg1_32(mach
, inst
, micro_u64shl
);
6006 case TGSI_OPCODE_I64SHR
:
6007 exec_arg0_64_arg1_32(mach
, inst
, micro_i64shr
);
6009 case TGSI_OPCODE_U64SHR
:
6010 exec_arg0_64_arg1_32(mach
, inst
, micro_u64shr
);
6012 case TGSI_OPCODE_U64DIV
:
6013 exec_double_binary(mach
, inst
, micro_u64div
, TGSI_EXEC_DATA_UINT64
);
6015 case TGSI_OPCODE_I64DIV
:
6016 exec_double_binary(mach
, inst
, micro_i64div
, TGSI_EXEC_DATA_INT64
);
6018 case TGSI_OPCODE_U64MOD
:
6019 exec_double_binary(mach
, inst
, micro_u64mod
, TGSI_EXEC_DATA_UINT64
);
6021 case TGSI_OPCODE_I64MOD
:
6022 exec_double_binary(mach
, inst
, micro_i64mod
, TGSI_EXEC_DATA_INT64
);
6025 case TGSI_OPCODE_F2U64
:
6026 exec_t_2_64(mach
, inst
, micro_f2u64
, TGSI_EXEC_DATA_FLOAT
);
6029 case TGSI_OPCODE_F2I64
:
6030 exec_t_2_64(mach
, inst
, micro_f2i64
, TGSI_EXEC_DATA_FLOAT
);
6033 case TGSI_OPCODE_U2I64
:
6034 exec_t_2_64(mach
, inst
, micro_u2i64
, TGSI_EXEC_DATA_INT
);
6036 case TGSI_OPCODE_I2I64
:
6037 exec_t_2_64(mach
, inst
, micro_i2i64
, TGSI_EXEC_DATA_INT
);
6040 case TGSI_OPCODE_D2U64
:
6041 exec_double_unary(mach
, inst
, micro_d2u64
);
6044 case TGSI_OPCODE_D2I64
:
6045 exec_double_unary(mach
, inst
, micro_d2i64
);
6048 case TGSI_OPCODE_U642F
:
6049 exec_64_2_t(mach
, inst
, micro_u642f
, TGSI_EXEC_DATA_FLOAT
);
6051 case TGSI_OPCODE_I642F
:
6052 exec_64_2_t(mach
, inst
, micro_i642f
, TGSI_EXEC_DATA_FLOAT
);
6055 case TGSI_OPCODE_U642D
:
6056 exec_double_unary(mach
, inst
, micro_u642d
);
6058 case TGSI_OPCODE_I642D
:
6059 exec_double_unary(mach
, inst
, micro_i642d
);
6069 tgsi_exec_machine_setup_masks(struct tgsi_exec_machine
*mach
)
6071 uint default_mask
= 0xf;
6073 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] = 0;
6074 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] = 0;
6076 if (mach
->ShaderType
== PIPE_SHADER_GEOMETRY
) {
6077 mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0] = 0;
6078 mach
->Primitives
[0] = 0;
6079 /* GS runs on a single primitive for now */
6083 if (mach
->NonHelperMask
== 0)
6084 mach
->NonHelperMask
= default_mask
;
6085 mach
->CondMask
= default_mask
;
6086 mach
->LoopMask
= default_mask
;
6087 mach
->ContMask
= default_mask
;
6088 mach
->FuncMask
= default_mask
;
6089 mach
->ExecMask
= default_mask
;
6091 mach
->Switch
.mask
= default_mask
;
6093 assert(mach
->CondStackTop
== 0);
6094 assert(mach
->LoopStackTop
== 0);
6095 assert(mach
->ContStackTop
== 0);
6096 assert(mach
->SwitchStackTop
== 0);
6097 assert(mach
->BreakStackTop
== 0);
6098 assert(mach
->CallStackTop
== 0);
6102 * Run TGSI interpreter.
6103 * \return bitmask of "alive" quad components
6106 tgsi_exec_machine_run( struct tgsi_exec_machine
*mach
, int start_pc
)
6110 mach
->pc
= start_pc
;
6113 tgsi_exec_machine_setup_masks(mach
);
6115 /* execute declarations (interpolants) */
6116 for (i
= 0; i
< mach
->NumDeclarations
; i
++) {
6117 exec_declaration( mach
, mach
->Declarations
+i
);
6123 struct tgsi_exec_vector temps
[TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
];
6124 struct tgsi_exec_vector outputs
[PIPE_MAX_ATTRIBS
];
6128 memset(mach
->Temps
, 0, sizeof(temps
));
6130 memset(mach
->Outputs
, 0, sizeof(outputs
));
6131 memset(temps
, 0, sizeof(temps
));
6132 memset(outputs
, 0, sizeof(outputs
));
6136 /* execute instructions, until pc is set to -1 */
6137 while (mach
->pc
!= -1) {
6138 boolean barrier_hit
;
6142 tgsi_dump_instruction(&mach
->Instructions
[mach
->pc
], inst
++);
6145 assert(mach
->pc
< (int) mach
->NumInstructions
);
6146 barrier_hit
= exec_instruction(mach
, mach
->Instructions
+ mach
->pc
, &mach
->pc
);
6148 /* for compute shaders if we hit a barrier return now for later rescheduling */
6149 if (barrier_hit
&& mach
->ShaderType
== PIPE_SHADER_COMPUTE
)
6153 for (i
= 0; i
< TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
; i
++) {
6154 if (memcmp(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]))) {
6157 memcpy(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]));
6158 debug_printf("TEMP[%2u] = ", i
);
6159 for (j
= 0; j
< 4; j
++) {
6163 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
6164 temps
[i
].xyzw
[0].f
[j
], temps
[i
].xyzw
[0].u
[j
],
6165 temps
[i
].xyzw
[1].f
[j
], temps
[i
].xyzw
[1].u
[j
],
6166 temps
[i
].xyzw
[2].f
[j
], temps
[i
].xyzw
[2].u
[j
],
6167 temps
[i
].xyzw
[3].f
[j
], temps
[i
].xyzw
[3].u
[j
]);
6171 if (mach
->Outputs
) {
6172 for (i
= 0; i
< PIPE_MAX_ATTRIBS
; i
++) {
6173 if (memcmp(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]))) {
6176 memcpy(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]));
6177 debug_printf("OUT[%2u] = ", i
);
6178 for (j
= 0; j
< 4; j
++) {
6182 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
6183 outputs
[i
].xyzw
[0].f
[j
], outputs
[i
].xyzw
[0].u
[j
],
6184 outputs
[i
].xyzw
[1].f
[j
], outputs
[i
].xyzw
[1].u
[j
],
6185 outputs
[i
].xyzw
[2].f
[j
], outputs
[i
].xyzw
[2].u
[j
],
6186 outputs
[i
].xyzw
[3].f
[j
], outputs
[i
].xyzw
[3].u
[j
]);
6196 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
6197 if (mach
->ShaderType
== PIPE_SHADER_FRAGMENT
) {
6199 * Scale back depth component.
6201 for (i
= 0; i
< 4; i
++)
6202 mach
->Outputs
[0].xyzw
[2].f
[i
] *= ctx
->DrawBuffer
->_DepthMaxF
;
6206 /* Strictly speaking, these assertions aren't really needed but they
6207 * can potentially catch some bugs in the control flow code.
6209 assert(mach
->CondStackTop
== 0);
6210 assert(mach
->LoopStackTop
== 0);
6211 assert(mach
->ContStackTop
== 0);
6212 assert(mach
->SwitchStackTop
== 0);
6213 assert(mach
->BreakStackTop
== 0);
6214 assert(mach
->CallStackTop
== 0);
6216 return ~mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];