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gallium: Drop unused X2D opcode.
[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 VMware, Inc.
4 * All Rights Reserved.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 /**
30 * TGSI interpreter/executor.
31 *
32 * Flow control information:
33 *
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
38 *
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
42 * See store_dest().
43 *
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
47 *
48 *
49 * Authors:
50 * Michal Krol
51 * Brian Paul
52 */
53
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_memory.h"
62 #include "util/u_math.h"
63
64
65 #define DEBUG_EXECUTION 0
66
67
68 #define FAST_MATH 0
69
70 #define TILE_TOP_LEFT 0
71 #define TILE_TOP_RIGHT 1
72 #define TILE_BOTTOM_LEFT 2
73 #define TILE_BOTTOM_RIGHT 3
74
75 static void
76 micro_abs(union tgsi_exec_channel *dst,
77 const union tgsi_exec_channel *src)
78 {
79 dst->f[0] = fabsf(src->f[0]);
80 dst->f[1] = fabsf(src->f[1]);
81 dst->f[2] = fabsf(src->f[2]);
82 dst->f[3] = fabsf(src->f[3]);
83 }
84
85 static void
86 micro_arl(union tgsi_exec_channel *dst,
87 const union tgsi_exec_channel *src)
88 {
89 dst->i[0] = (int)floorf(src->f[0]);
90 dst->i[1] = (int)floorf(src->f[1]);
91 dst->i[2] = (int)floorf(src->f[2]);
92 dst->i[3] = (int)floorf(src->f[3]);
93 }
94
95 static void
96 micro_arr(union tgsi_exec_channel *dst,
97 const union tgsi_exec_channel *src)
98 {
99 dst->i[0] = (int)floorf(src->f[0] + 0.5f);
100 dst->i[1] = (int)floorf(src->f[1] + 0.5f);
101 dst->i[2] = (int)floorf(src->f[2] + 0.5f);
102 dst->i[3] = (int)floorf(src->f[3] + 0.5f);
103 }
104
105 static void
106 micro_ceil(union tgsi_exec_channel *dst,
107 const union tgsi_exec_channel *src)
108 {
109 dst->f[0] = ceilf(src->f[0]);
110 dst->f[1] = ceilf(src->f[1]);
111 dst->f[2] = ceilf(src->f[2]);
112 dst->f[3] = ceilf(src->f[3]);
113 }
114
115 static void
116 micro_clamp(union tgsi_exec_channel *dst,
117 const union tgsi_exec_channel *src0,
118 const union tgsi_exec_channel *src1,
119 const union tgsi_exec_channel *src2)
120 {
121 dst->f[0] = src0->f[0] < src1->f[0] ? src1->f[0] : src0->f[0] > src2->f[0] ? src2->f[0] : src0->f[0];
122 dst->f[1] = src0->f[1] < src1->f[1] ? src1->f[1] : src0->f[1] > src2->f[1] ? src2->f[1] : src0->f[1];
123 dst->f[2] = src0->f[2] < src1->f[2] ? src1->f[2] : src0->f[2] > src2->f[2] ? src2->f[2] : src0->f[2];
124 dst->f[3] = src0->f[3] < src1->f[3] ? src1->f[3] : src0->f[3] > src2->f[3] ? src2->f[3] : src0->f[3];
125 }
126
127 static void
128 micro_cmp(union tgsi_exec_channel *dst,
129 const union tgsi_exec_channel *src0,
130 const union tgsi_exec_channel *src1,
131 const union tgsi_exec_channel *src2)
132 {
133 dst->f[0] = src0->f[0] < 0.0f ? src1->f[0] : src2->f[0];
134 dst->f[1] = src0->f[1] < 0.0f ? src1->f[1] : src2->f[1];
135 dst->f[2] = src0->f[2] < 0.0f ? src1->f[2] : src2->f[2];
136 dst->f[3] = src0->f[3] < 0.0f ? src1->f[3] : src2->f[3];
137 }
138
139 static void
140 micro_cnd(union tgsi_exec_channel *dst,
141 const union tgsi_exec_channel *src0,
142 const union tgsi_exec_channel *src1,
143 const union tgsi_exec_channel *src2)
144 {
145 dst->f[0] = src2->f[0] > 0.5f ? src0->f[0] : src1->f[0];
146 dst->f[1] = src2->f[1] > 0.5f ? src0->f[1] : src1->f[1];
147 dst->f[2] = src2->f[2] > 0.5f ? src0->f[2] : src1->f[2];
148 dst->f[3] = src2->f[3] > 0.5f ? src0->f[3] : src1->f[3];
149 }
150
151 static void
152 micro_cos(union tgsi_exec_channel *dst,
153 const union tgsi_exec_channel *src)
154 {
155 dst->f[0] = cosf(src->f[0]);
156 dst->f[1] = cosf(src->f[1]);
157 dst->f[2] = cosf(src->f[2]);
158 dst->f[3] = cosf(src->f[3]);
159 }
160
161 static void
162 micro_ddx(union tgsi_exec_channel *dst,
163 const union tgsi_exec_channel *src)
164 {
165 dst->f[0] =
166 dst->f[1] =
167 dst->f[2] =
168 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
169 }
170
171 static void
172 micro_ddy(union tgsi_exec_channel *dst,
173 const union tgsi_exec_channel *src)
174 {
175 dst->f[0] =
176 dst->f[1] =
177 dst->f[2] =
178 dst->f[3] = src->f[TILE_BOTTOM_LEFT] - src->f[TILE_TOP_LEFT];
179 }
180
181 static void
182 micro_exp2(union tgsi_exec_channel *dst,
183 const union tgsi_exec_channel *src)
184 {
185 #if FAST_MATH
186 dst->f[0] = util_fast_exp2(src->f[0]);
187 dst->f[1] = util_fast_exp2(src->f[1]);
188 dst->f[2] = util_fast_exp2(src->f[2]);
189 dst->f[3] = util_fast_exp2(src->f[3]);
190 #else
191 #if DEBUG
192 /* Inf is okay for this instruction, so clamp it to silence assertions. */
193 uint i;
194 union tgsi_exec_channel clamped;
195
196 for (i = 0; i < 4; i++) {
197 if (src->f[i] > 127.99999f) {
198 clamped.f[i] = 127.99999f;
199 } else if (src->f[i] < -126.99999f) {
200 clamped.f[i] = -126.99999f;
201 } else {
202 clamped.f[i] = src->f[i];
203 }
204 }
205 src = &clamped;
206 #endif /* DEBUG */
207
208 dst->f[0] = powf(2.0f, src->f[0]);
209 dst->f[1] = powf(2.0f, src->f[1]);
210 dst->f[2] = powf(2.0f, src->f[2]);
211 dst->f[3] = powf(2.0f, src->f[3]);
212 #endif /* FAST_MATH */
213 }
214
215 static void
216 micro_flr(union tgsi_exec_channel *dst,
217 const union tgsi_exec_channel *src)
218 {
219 dst->f[0] = floorf(src->f[0]);
220 dst->f[1] = floorf(src->f[1]);
221 dst->f[2] = floorf(src->f[2]);
222 dst->f[3] = floorf(src->f[3]);
223 }
224
225 static void
226 micro_frc(union tgsi_exec_channel *dst,
227 const union tgsi_exec_channel *src)
228 {
229 dst->f[0] = src->f[0] - floorf(src->f[0]);
230 dst->f[1] = src->f[1] - floorf(src->f[1]);
231 dst->f[2] = src->f[2] - floorf(src->f[2]);
232 dst->f[3] = src->f[3] - floorf(src->f[3]);
233 }
234
235 static void
236 micro_iabs(union tgsi_exec_channel *dst,
237 const union tgsi_exec_channel *src)
238 {
239 dst->i[0] = src->i[0] >= 0 ? src->i[0] : -src->i[0];
240 dst->i[1] = src->i[1] >= 0 ? src->i[1] : -src->i[1];
241 dst->i[2] = src->i[2] >= 0 ? src->i[2] : -src->i[2];
242 dst->i[3] = src->i[3] >= 0 ? src->i[3] : -src->i[3];
243 }
244
245 static void
246 micro_ineg(union tgsi_exec_channel *dst,
247 const union tgsi_exec_channel *src)
248 {
249 dst->i[0] = -src->i[0];
250 dst->i[1] = -src->i[1];
251 dst->i[2] = -src->i[2];
252 dst->i[3] = -src->i[3];
253 }
254
255 static void
256 micro_lg2(union tgsi_exec_channel *dst,
257 const union tgsi_exec_channel *src)
258 {
259 #if FAST_MATH
260 dst->f[0] = util_fast_log2(src->f[0]);
261 dst->f[1] = util_fast_log2(src->f[1]);
262 dst->f[2] = util_fast_log2(src->f[2]);
263 dst->f[3] = util_fast_log2(src->f[3]);
264 #else
265 dst->f[0] = logf(src->f[0]) * 1.442695f;
266 dst->f[1] = logf(src->f[1]) * 1.442695f;
267 dst->f[2] = logf(src->f[2]) * 1.442695f;
268 dst->f[3] = logf(src->f[3]) * 1.442695f;
269 #endif
270 }
271
272 static void
273 micro_lrp(union tgsi_exec_channel *dst,
274 const union tgsi_exec_channel *src0,
275 const union tgsi_exec_channel *src1,
276 const union tgsi_exec_channel *src2)
277 {
278 dst->f[0] = src0->f[0] * (src1->f[0] - src2->f[0]) + src2->f[0];
279 dst->f[1] = src0->f[1] * (src1->f[1] - src2->f[1]) + src2->f[1];
280 dst->f[2] = src0->f[2] * (src1->f[2] - src2->f[2]) + src2->f[2];
281 dst->f[3] = src0->f[3] * (src1->f[3] - src2->f[3]) + src2->f[3];
282 }
283
284 static void
285 micro_mad(union tgsi_exec_channel *dst,
286 const union tgsi_exec_channel *src0,
287 const union tgsi_exec_channel *src1,
288 const union tgsi_exec_channel *src2)
289 {
290 dst->f[0] = src0->f[0] * src1->f[0] + src2->f[0];
291 dst->f[1] = src0->f[1] * src1->f[1] + src2->f[1];
292 dst->f[2] = src0->f[2] * src1->f[2] + src2->f[2];
293 dst->f[3] = src0->f[3] * src1->f[3] + src2->f[3];
294 }
295
296 static void
297 micro_mov(union tgsi_exec_channel *dst,
298 const union tgsi_exec_channel *src)
299 {
300 dst->u[0] = src->u[0];
301 dst->u[1] = src->u[1];
302 dst->u[2] = src->u[2];
303 dst->u[3] = src->u[3];
304 }
305
306 static void
307 micro_rcp(union tgsi_exec_channel *dst,
308 const union tgsi_exec_channel *src)
309 {
310 #if 0 /* for debugging */
311 assert(src->f[0] != 0.0f);
312 assert(src->f[1] != 0.0f);
313 assert(src->f[2] != 0.0f);
314 assert(src->f[3] != 0.0f);
315 #endif
316 dst->f[0] = 1.0f / src->f[0];
317 dst->f[1] = 1.0f / src->f[1];
318 dst->f[2] = 1.0f / src->f[2];
319 dst->f[3] = 1.0f / src->f[3];
320 }
321
322 static void
323 micro_rnd(union tgsi_exec_channel *dst,
324 const union tgsi_exec_channel *src)
325 {
326 dst->f[0] = floorf(src->f[0] + 0.5f);
327 dst->f[1] = floorf(src->f[1] + 0.5f);
328 dst->f[2] = floorf(src->f[2] + 0.5f);
329 dst->f[3] = floorf(src->f[3] + 0.5f);
330 }
331
332 static void
333 micro_rsq(union tgsi_exec_channel *dst,
334 const union tgsi_exec_channel *src)
335 {
336 #if 0 /* for debugging */
337 assert(src->f[0] != 0.0f);
338 assert(src->f[1] != 0.0f);
339 assert(src->f[2] != 0.0f);
340 assert(src->f[3] != 0.0f);
341 #endif
342 dst->f[0] = 1.0f / sqrtf(src->f[0]);
343 dst->f[1] = 1.0f / sqrtf(src->f[1]);
344 dst->f[2] = 1.0f / sqrtf(src->f[2]);
345 dst->f[3] = 1.0f / sqrtf(src->f[3]);
346 }
347
348 static void
349 micro_sqrt(union tgsi_exec_channel *dst,
350 const union tgsi_exec_channel *src)
351 {
352 dst->f[0] = sqrtf(src->f[0]);
353 dst->f[1] = sqrtf(src->f[1]);
354 dst->f[2] = sqrtf(src->f[2]);
355 dst->f[3] = sqrtf(src->f[3]);
356 }
357
358 static void
359 micro_seq(union tgsi_exec_channel *dst,
360 const union tgsi_exec_channel *src0,
361 const union tgsi_exec_channel *src1)
362 {
363 dst->f[0] = src0->f[0] == src1->f[0] ? 1.0f : 0.0f;
364 dst->f[1] = src0->f[1] == src1->f[1] ? 1.0f : 0.0f;
365 dst->f[2] = src0->f[2] == src1->f[2] ? 1.0f : 0.0f;
366 dst->f[3] = src0->f[3] == src1->f[3] ? 1.0f : 0.0f;
367 }
368
369 static void
370 micro_sge(union tgsi_exec_channel *dst,
371 const union tgsi_exec_channel *src0,
372 const union tgsi_exec_channel *src1)
373 {
374 dst->f[0] = src0->f[0] >= src1->f[0] ? 1.0f : 0.0f;
375 dst->f[1] = src0->f[1] >= src1->f[1] ? 1.0f : 0.0f;
376 dst->f[2] = src0->f[2] >= src1->f[2] ? 1.0f : 0.0f;
377 dst->f[3] = src0->f[3] >= src1->f[3] ? 1.0f : 0.0f;
378 }
379
380 static void
381 micro_sgn(union tgsi_exec_channel *dst,
382 const union tgsi_exec_channel *src)
383 {
384 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
385 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
386 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
387 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
388 }
389
390 static void
391 micro_isgn(union tgsi_exec_channel *dst,
392 const union tgsi_exec_channel *src)
393 {
394 dst->i[0] = src->i[0] < 0 ? -1 : src->i[0] > 0 ? 1 : 0;
395 dst->i[1] = src->i[1] < 0 ? -1 : src->i[1] > 0 ? 1 : 0;
396 dst->i[2] = src->i[2] < 0 ? -1 : src->i[2] > 0 ? 1 : 0;
397 dst->i[3] = src->i[3] < 0 ? -1 : src->i[3] > 0 ? 1 : 0;
398 }
399
400 static void
401 micro_sgt(union tgsi_exec_channel *dst,
402 const union tgsi_exec_channel *src0,
403 const union tgsi_exec_channel *src1)
404 {
405 dst->f[0] = src0->f[0] > src1->f[0] ? 1.0f : 0.0f;
406 dst->f[1] = src0->f[1] > src1->f[1] ? 1.0f : 0.0f;
407 dst->f[2] = src0->f[2] > src1->f[2] ? 1.0f : 0.0f;
408 dst->f[3] = src0->f[3] > src1->f[3] ? 1.0f : 0.0f;
409 }
410
411 static void
412 micro_sin(union tgsi_exec_channel *dst,
413 const union tgsi_exec_channel *src)
414 {
415 dst->f[0] = sinf(src->f[0]);
416 dst->f[1] = sinf(src->f[1]);
417 dst->f[2] = sinf(src->f[2]);
418 dst->f[3] = sinf(src->f[3]);
419 }
420
421 static void
422 micro_sle(union tgsi_exec_channel *dst,
423 const union tgsi_exec_channel *src0,
424 const union tgsi_exec_channel *src1)
425 {
426 dst->f[0] = src0->f[0] <= src1->f[0] ? 1.0f : 0.0f;
427 dst->f[1] = src0->f[1] <= src1->f[1] ? 1.0f : 0.0f;
428 dst->f[2] = src0->f[2] <= src1->f[2] ? 1.0f : 0.0f;
429 dst->f[3] = src0->f[3] <= src1->f[3] ? 1.0f : 0.0f;
430 }
431
432 static void
433 micro_slt(union tgsi_exec_channel *dst,
434 const union tgsi_exec_channel *src0,
435 const union tgsi_exec_channel *src1)
436 {
437 dst->f[0] = src0->f[0] < src1->f[0] ? 1.0f : 0.0f;
438 dst->f[1] = src0->f[1] < src1->f[1] ? 1.0f : 0.0f;
439 dst->f[2] = src0->f[2] < src1->f[2] ? 1.0f : 0.0f;
440 dst->f[3] = src0->f[3] < src1->f[3] ? 1.0f : 0.0f;
441 }
442
443 static void
444 micro_sne(union tgsi_exec_channel *dst,
445 const union tgsi_exec_channel *src0,
446 const union tgsi_exec_channel *src1)
447 {
448 dst->f[0] = src0->f[0] != src1->f[0] ? 1.0f : 0.0f;
449 dst->f[1] = src0->f[1] != src1->f[1] ? 1.0f : 0.0f;
450 dst->f[2] = src0->f[2] != src1->f[2] ? 1.0f : 0.0f;
451 dst->f[3] = src0->f[3] != src1->f[3] ? 1.0f : 0.0f;
452 }
453
454 static void
455 micro_sfl(union tgsi_exec_channel *dst)
456 {
457 dst->f[0] = 0.0f;
458 dst->f[1] = 0.0f;
459 dst->f[2] = 0.0f;
460 dst->f[3] = 0.0f;
461 }
462
463 static void
464 micro_str(union tgsi_exec_channel *dst)
465 {
466 dst->f[0] = 1.0f;
467 dst->f[1] = 1.0f;
468 dst->f[2] = 1.0f;
469 dst->f[3] = 1.0f;
470 }
471
472 static void
473 micro_trunc(union tgsi_exec_channel *dst,
474 const union tgsi_exec_channel *src)
475 {
476 dst->f[0] = (float)(int)src->f[0];
477 dst->f[1] = (float)(int)src->f[1];
478 dst->f[2] = (float)(int)src->f[2];
479 dst->f[3] = (float)(int)src->f[3];
480 }
481
482
483 enum tgsi_exec_datatype {
484 TGSI_EXEC_DATA_FLOAT,
485 TGSI_EXEC_DATA_INT,
486 TGSI_EXEC_DATA_UINT
487 };
488
489 /*
490 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
491 */
492 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
493 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
494 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
495 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
496 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
497 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
498
499
500 /** The execution mask depends on the conditional mask and the loop mask */
501 #define UPDATE_EXEC_MASK(MACH) \
502 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
503
504
505 static const union tgsi_exec_channel ZeroVec =
506 { { 0.0, 0.0, 0.0, 0.0 } };
507
508 static const union tgsi_exec_channel OneVec = {
509 {1.0f, 1.0f, 1.0f, 1.0f}
510 };
511
512 static const union tgsi_exec_channel P128Vec = {
513 {128.0f, 128.0f, 128.0f, 128.0f}
514 };
515
516 static const union tgsi_exec_channel M128Vec = {
517 {-128.0f, -128.0f, -128.0f, -128.0f}
518 };
519
520
521 /**
522 * Assert that none of the float values in 'chan' are infinite or NaN.
523 * NaN and Inf may occur normally during program execution and should
524 * not lead to crashes, etc. But when debugging, it's helpful to catch
525 * them.
526 */
527 static INLINE void
528 check_inf_or_nan(const union tgsi_exec_channel *chan)
529 {
530 assert(!util_is_inf_or_nan((chan)->f[0]));
531 assert(!util_is_inf_or_nan((chan)->f[1]));
532 assert(!util_is_inf_or_nan((chan)->f[2]));
533 assert(!util_is_inf_or_nan((chan)->f[3]));
534 }
535
536
537 #ifdef DEBUG
538 static void
539 print_chan(const char *msg, const union tgsi_exec_channel *chan)
540 {
541 debug_printf("%s = {%f, %f, %f, %f}\n",
542 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
543 }
544 #endif
545
546
547 #ifdef DEBUG
548 static void
549 print_temp(const struct tgsi_exec_machine *mach, uint index)
550 {
551 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
552 int i;
553 debug_printf("Temp[%u] =\n", index);
554 for (i = 0; i < 4; i++) {
555 debug_printf(" %c: { %f, %f, %f, %f }\n",
556 "XYZW"[i],
557 tmp->xyzw[i].f[0],
558 tmp->xyzw[i].f[1],
559 tmp->xyzw[i].f[2],
560 tmp->xyzw[i].f[3]);
561 }
562 }
563 #endif
564
565
566 void
567 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine *mach,
568 unsigned num_bufs,
569 const void **bufs,
570 const unsigned *buf_sizes)
571 {
572 unsigned i;
573
574 for (i = 0; i < num_bufs; i++) {
575 mach->Consts[i] = bufs[i];
576 mach->ConstsSize[i] = buf_sizes[i];
577 }
578 }
579
580
581 /**
582 * Check if there's a potential src/dst register data dependency when
583 * using SOA execution.
584 * Example:
585 * MOV T, T.yxwz;
586 * This would expand into:
587 * MOV t0, t1;
588 * MOV t1, t0;
589 * MOV t2, t3;
590 * MOV t3, t2;
591 * The second instruction will have the wrong value for t0 if executed as-is.
592 */
593 boolean
594 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
595 {
596 uint i, chan;
597
598 uint writemask = inst->Dst[0].Register.WriteMask;
599 if (writemask == TGSI_WRITEMASK_X ||
600 writemask == TGSI_WRITEMASK_Y ||
601 writemask == TGSI_WRITEMASK_Z ||
602 writemask == TGSI_WRITEMASK_W ||
603 writemask == TGSI_WRITEMASK_NONE) {
604 /* no chance of data dependency */
605 return FALSE;
606 }
607
608 /* loop over src regs */
609 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
610 if ((inst->Src[i].Register.File ==
611 inst->Dst[0].Register.File) &&
612 ((inst->Src[i].Register.Index ==
613 inst->Dst[0].Register.Index) ||
614 inst->Src[i].Register.Indirect ||
615 inst->Dst[0].Register.Indirect)) {
616 /* loop over dest channels */
617 uint channelsWritten = 0x0;
618 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
619 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
620 /* check if we're reading a channel that's been written */
621 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
622 if (channelsWritten & (1 << swizzle)) {
623 return TRUE;
624 }
625
626 channelsWritten |= (1 << chan);
627 }
628 }
629 }
630 }
631 return FALSE;
632 }
633
634
635 /**
636 * Initialize machine state by expanding tokens to full instructions,
637 * allocating temporary storage, setting up constants, etc.
638 * After this, we can call tgsi_exec_machine_run() many times.
639 */
640 void
641 tgsi_exec_machine_bind_shader(
642 struct tgsi_exec_machine *mach,
643 const struct tgsi_token *tokens,
644 struct tgsi_sampler *sampler)
645 {
646 uint k;
647 struct tgsi_parse_context parse;
648 struct tgsi_full_instruction *instructions;
649 struct tgsi_full_declaration *declarations;
650 uint maxInstructions = 10, numInstructions = 0;
651 uint maxDeclarations = 10, numDeclarations = 0;
652
653 #if 0
654 tgsi_dump(tokens, 0);
655 #endif
656
657 util_init_math();
658
659
660 mach->Tokens = tokens;
661 mach->Sampler = sampler;
662
663 if (!tokens) {
664 /* unbind and free all */
665 FREE(mach->Declarations);
666 mach->Declarations = NULL;
667 mach->NumDeclarations = 0;
668
669 FREE(mach->Instructions);
670 mach->Instructions = NULL;
671 mach->NumInstructions = 0;
672
673 return;
674 }
675
676 k = tgsi_parse_init (&parse, mach->Tokens);
677 if (k != TGSI_PARSE_OK) {
678 debug_printf( "Problem parsing!\n" );
679 return;
680 }
681
682 mach->Processor = parse.FullHeader.Processor.Processor;
683 mach->ImmLimit = 0;
684 mach->NumOutputs = 0;
685
686 if (mach->Processor == TGSI_PROCESSOR_GEOMETRY &&
687 !mach->UsedGeometryShader) {
688 struct tgsi_exec_vector *inputs;
689 struct tgsi_exec_vector *outputs;
690
691 inputs = align_malloc(sizeof(struct tgsi_exec_vector) *
692 TGSI_MAX_PRIM_VERTICES * PIPE_MAX_SHADER_INPUTS,
693 16);
694
695 if (!inputs)
696 return;
697
698 outputs = align_malloc(sizeof(struct tgsi_exec_vector) *
699 TGSI_MAX_TOTAL_VERTICES, 16);
700
701 if (!outputs) {
702 align_free(inputs);
703 return;
704 }
705
706 align_free(mach->Inputs);
707 align_free(mach->Outputs);
708
709 mach->Inputs = inputs;
710 mach->Outputs = outputs;
711 mach->UsedGeometryShader = TRUE;
712 }
713
714 declarations = (struct tgsi_full_declaration *)
715 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
716
717 if (!declarations) {
718 return;
719 }
720
721 instructions = (struct tgsi_full_instruction *)
722 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
723
724 if (!instructions) {
725 FREE( declarations );
726 return;
727 }
728
729 while( !tgsi_parse_end_of_tokens( &parse ) ) {
730 uint i;
731
732 tgsi_parse_token( &parse );
733 switch( parse.FullToken.Token.Type ) {
734 case TGSI_TOKEN_TYPE_DECLARATION:
735 /* save expanded declaration */
736 if (numDeclarations == maxDeclarations) {
737 declarations = REALLOC(declarations,
738 maxDeclarations
739 * sizeof(struct tgsi_full_declaration),
740 (maxDeclarations + 10)
741 * sizeof(struct tgsi_full_declaration));
742 maxDeclarations += 10;
743 }
744 if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_OUTPUT) {
745 unsigned reg;
746 for (reg = parse.FullToken.FullDeclaration.Range.First;
747 reg <= parse.FullToken.FullDeclaration.Range.Last;
748 ++reg) {
749 ++mach->NumOutputs;
750 }
751 }
752 memcpy(declarations + numDeclarations,
753 &parse.FullToken.FullDeclaration,
754 sizeof(declarations[0]));
755 numDeclarations++;
756 break;
757
758 case TGSI_TOKEN_TYPE_IMMEDIATE:
759 {
760 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
761 assert( size <= 4 );
762 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
763
764 for( i = 0; i < size; i++ ) {
765 mach->Imms[mach->ImmLimit][i] =
766 parse.FullToken.FullImmediate.u[i].Float;
767 }
768 mach->ImmLimit += 1;
769 }
770 break;
771
772 case TGSI_TOKEN_TYPE_INSTRUCTION:
773
774 /* save expanded instruction */
775 if (numInstructions == maxInstructions) {
776 instructions = REALLOC(instructions,
777 maxInstructions
778 * sizeof(struct tgsi_full_instruction),
779 (maxInstructions + 10)
780 * sizeof(struct tgsi_full_instruction));
781 maxInstructions += 10;
782 }
783
784 memcpy(instructions + numInstructions,
785 &parse.FullToken.FullInstruction,
786 sizeof(instructions[0]));
787
788 numInstructions++;
789 break;
790
791 case TGSI_TOKEN_TYPE_PROPERTY:
792 if (mach->Processor == TGSI_PROCESSOR_GEOMETRY) {
793 if (parse.FullToken.FullProperty.Property.PropertyName == TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES) {
794 mach->MaxOutputVertices = parse.FullToken.FullProperty.u[0].Data;
795 }
796 }
797 break;
798
799 default:
800 assert( 0 );
801 }
802 }
803 tgsi_parse_free (&parse);
804
805 FREE(mach->Declarations);
806 mach->Declarations = declarations;
807 mach->NumDeclarations = numDeclarations;
808
809 FREE(mach->Instructions);
810 mach->Instructions = instructions;
811 mach->NumInstructions = numInstructions;
812 }
813
814
815 struct tgsi_exec_machine *
816 tgsi_exec_machine_create( void )
817 {
818 struct tgsi_exec_machine *mach;
819 uint i;
820
821 mach = align_malloc( sizeof *mach, 16 );
822 if (!mach)
823 goto fail;
824
825 memset(mach, 0, sizeof(*mach));
826
827 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
828 mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
829 mach->Predicates = &mach->Temps[TGSI_EXEC_TEMP_P0];
830
831 mach->Inputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_INPUTS, 16);
832 mach->Outputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_OUTPUTS, 16);
833 if (!mach->Inputs || !mach->Outputs)
834 goto fail;
835
836 /* Setup constants needed by the SSE2 executor. */
837 for( i = 0; i < 4; i++ ) {
838 mach->Temps[TGSI_EXEC_TEMP_00000000_I].xyzw[TGSI_EXEC_TEMP_00000000_C].u[i] = 0x00000000;
839 mach->Temps[TGSI_EXEC_TEMP_7FFFFFFF_I].xyzw[TGSI_EXEC_TEMP_7FFFFFFF_C].u[i] = 0x7FFFFFFF;
840 mach->Temps[TGSI_EXEC_TEMP_80000000_I].xyzw[TGSI_EXEC_TEMP_80000000_C].u[i] = 0x80000000;
841 mach->Temps[TGSI_EXEC_TEMP_FFFFFFFF_I].xyzw[TGSI_EXEC_TEMP_FFFFFFFF_C].u[i] = 0xFFFFFFFF; /* not used */
842 mach->Temps[TGSI_EXEC_TEMP_ONE_I].xyzw[TGSI_EXEC_TEMP_ONE_C].f[i] = 1.0f;
843 mach->Temps[TGSI_EXEC_TEMP_TWO_I].xyzw[TGSI_EXEC_TEMP_TWO_C].f[i] = 2.0f; /* not used */
844 mach->Temps[TGSI_EXEC_TEMP_128_I].xyzw[TGSI_EXEC_TEMP_128_C].f[i] = 128.0f;
845 mach->Temps[TGSI_EXEC_TEMP_MINUS_128_I].xyzw[TGSI_EXEC_TEMP_MINUS_128_C].f[i] = -128.0f;
846 mach->Temps[TGSI_EXEC_TEMP_THREE_I].xyzw[TGSI_EXEC_TEMP_THREE_C].f[i] = 3.0f;
847 mach->Temps[TGSI_EXEC_TEMP_HALF_I].xyzw[TGSI_EXEC_TEMP_HALF_C].f[i] = 0.5f;
848 }
849
850 #ifdef DEBUG
851 /* silence warnings */
852 (void) print_chan;
853 (void) print_temp;
854 #endif
855
856 return mach;
857
858 fail:
859 if (mach) {
860 align_free(mach->Inputs);
861 align_free(mach->Outputs);
862 align_free(mach);
863 }
864 return NULL;
865 }
866
867
868 void
869 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
870 {
871 if (mach) {
872 FREE(mach->Instructions);
873 FREE(mach->Declarations);
874
875 align_free(mach->Inputs);
876 align_free(mach->Outputs);
877
878 align_free(mach);
879 }
880 }
881
882 static void
883 micro_add(union tgsi_exec_channel *dst,
884 const union tgsi_exec_channel *src0,
885 const union tgsi_exec_channel *src1)
886 {
887 dst->f[0] = src0->f[0] + src1->f[0];
888 dst->f[1] = src0->f[1] + src1->f[1];
889 dst->f[2] = src0->f[2] + src1->f[2];
890 dst->f[3] = src0->f[3] + src1->f[3];
891 }
892
893 static void
894 micro_div(
895 union tgsi_exec_channel *dst,
896 const union tgsi_exec_channel *src0,
897 const union tgsi_exec_channel *src1 )
898 {
899 if (src1->f[0] != 0) {
900 dst->f[0] = src0->f[0] / src1->f[0];
901 }
902 if (src1->f[1] != 0) {
903 dst->f[1] = src0->f[1] / src1->f[1];
904 }
905 if (src1->f[2] != 0) {
906 dst->f[2] = src0->f[2] / src1->f[2];
907 }
908 if (src1->f[3] != 0) {
909 dst->f[3] = src0->f[3] / src1->f[3];
910 }
911 }
912
913 static void
914 micro_lt(
915 union tgsi_exec_channel *dst,
916 const union tgsi_exec_channel *src0,
917 const union tgsi_exec_channel *src1,
918 const union tgsi_exec_channel *src2,
919 const union tgsi_exec_channel *src3 )
920 {
921 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
922 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
923 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
924 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
925 }
926
927 static void
928 micro_max(union tgsi_exec_channel *dst,
929 const union tgsi_exec_channel *src0,
930 const union tgsi_exec_channel *src1)
931 {
932 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
933 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
934 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
935 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
936 }
937
938 static void
939 micro_min(union tgsi_exec_channel *dst,
940 const union tgsi_exec_channel *src0,
941 const union tgsi_exec_channel *src1)
942 {
943 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
944 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
945 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
946 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
947 }
948
949 static void
950 micro_mul(union tgsi_exec_channel *dst,
951 const union tgsi_exec_channel *src0,
952 const union tgsi_exec_channel *src1)
953 {
954 dst->f[0] = src0->f[0] * src1->f[0];
955 dst->f[1] = src0->f[1] * src1->f[1];
956 dst->f[2] = src0->f[2] * src1->f[2];
957 dst->f[3] = src0->f[3] * src1->f[3];
958 }
959
960 static void
961 micro_neg(
962 union tgsi_exec_channel *dst,
963 const union tgsi_exec_channel *src )
964 {
965 dst->f[0] = -src->f[0];
966 dst->f[1] = -src->f[1];
967 dst->f[2] = -src->f[2];
968 dst->f[3] = -src->f[3];
969 }
970
971 static void
972 micro_pow(
973 union tgsi_exec_channel *dst,
974 const union tgsi_exec_channel *src0,
975 const union tgsi_exec_channel *src1 )
976 {
977 #if FAST_MATH
978 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
979 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
980 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
981 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
982 #else
983 dst->f[0] = powf( src0->f[0], src1->f[0] );
984 dst->f[1] = powf( src0->f[1], src1->f[1] );
985 dst->f[2] = powf( src0->f[2], src1->f[2] );
986 dst->f[3] = powf( src0->f[3], src1->f[3] );
987 #endif
988 }
989
990 static void
991 micro_sub(union tgsi_exec_channel *dst,
992 const union tgsi_exec_channel *src0,
993 const union tgsi_exec_channel *src1)
994 {
995 dst->f[0] = src0->f[0] - src1->f[0];
996 dst->f[1] = src0->f[1] - src1->f[1];
997 dst->f[2] = src0->f[2] - src1->f[2];
998 dst->f[3] = src0->f[3] - src1->f[3];
999 }
1000
1001 static void
1002 fetch_src_file_channel(const struct tgsi_exec_machine *mach,
1003 const uint chan_index,
1004 const uint file,
1005 const uint swizzle,
1006 const union tgsi_exec_channel *index,
1007 const union tgsi_exec_channel *index2D,
1008 union tgsi_exec_channel *chan)
1009 {
1010 uint i;
1011
1012 assert(swizzle < 4);
1013
1014 switch (file) {
1015 case TGSI_FILE_CONSTANT:
1016 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1017 assert(index2D->i[i] >= 0 && index2D->i[i] < PIPE_MAX_CONSTANT_BUFFERS);
1018 assert(mach->Consts[index2D->i[i]]);
1019
1020 if (index->i[i] < 0) {
1021 chan->u[i] = 0;
1022 } else {
1023 /* NOTE: copying the const value as a uint instead of float */
1024 const uint constbuf = index2D->i[i];
1025 const uint *buf = (const uint *)mach->Consts[constbuf];
1026 const int pos = index->i[i] * 4 + swizzle;
1027 /* const buffer bounds check */
1028 if (pos < 0 || pos >= (int) mach->ConstsSize[constbuf]) {
1029 if (0) {
1030 /* Debug: print warning */
1031 static int count = 0;
1032 if (count++ < 100)
1033 debug_printf("TGSI Exec: const buffer index %d"
1034 " out of bounds\n", pos);
1035 }
1036 chan->u[i] = 0;
1037 }
1038 else
1039 chan->u[i] = buf[pos];
1040 }
1041 }
1042 break;
1043
1044 case TGSI_FILE_INPUT:
1045 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1046 /*
1047 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1048 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1049 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1050 index2D->i[i], index->i[i]);
1051 }*/
1052 int pos = index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i];
1053 assert(pos >= 0);
1054 assert(pos < TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS);
1055 chan->u[i] = mach->Inputs[pos].xyzw[swizzle].u[i];
1056 }
1057 break;
1058
1059 case TGSI_FILE_SYSTEM_VALUE:
1060 /* XXX no swizzling at this point. Will be needed if we put
1061 * gl_FragCoord, for example, in a sys value register.
1062 */
1063 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1064 chan->u[i] = mach->SystemValue[index->i[i]].u[i];
1065 }
1066 break;
1067
1068 case TGSI_FILE_TEMPORARY:
1069 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1070 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1071 assert(index2D->i[i] == 0);
1072
1073 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1074 }
1075 break;
1076
1077 case TGSI_FILE_IMMEDIATE:
1078 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1079 assert(index->i[i] >= 0 && index->i[i] < (int)mach->ImmLimit);
1080 assert(index2D->i[i] == 0);
1081
1082 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1083 }
1084 break;
1085
1086 case TGSI_FILE_ADDRESS:
1087 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1088 assert(index->i[i] >= 0);
1089 assert(index2D->i[i] == 0);
1090
1091 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1092 }
1093 break;
1094
1095 case TGSI_FILE_PREDICATE:
1096 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1097 assert(index->i[i] >= 0 && index->i[i] < TGSI_EXEC_NUM_PREDS);
1098 assert(index2D->i[i] == 0);
1099
1100 chan->u[i] = mach->Predicates[0].xyzw[swizzle].u[i];
1101 }
1102 break;
1103
1104 case TGSI_FILE_OUTPUT:
1105 /* vertex/fragment output vars can be read too */
1106 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1107 assert(index->i[i] >= 0);
1108 assert(index2D->i[i] == 0);
1109
1110 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1111 }
1112 break;
1113
1114 default:
1115 assert(0);
1116 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1117 chan->u[i] = 0;
1118 }
1119 }
1120 }
1121
1122 static void
1123 fetch_source(const struct tgsi_exec_machine *mach,
1124 union tgsi_exec_channel *chan,
1125 const struct tgsi_full_src_register *reg,
1126 const uint chan_index,
1127 enum tgsi_exec_datatype src_datatype)
1128 {
1129 union tgsi_exec_channel index;
1130 union tgsi_exec_channel index2D;
1131 uint swizzle;
1132
1133 /* We start with a direct index into a register file.
1134 *
1135 * file[1],
1136 * where:
1137 * file = Register.File
1138 * [1] = Register.Index
1139 */
1140 index.i[0] =
1141 index.i[1] =
1142 index.i[2] =
1143 index.i[3] = reg->Register.Index;
1144
1145 /* There is an extra source register that indirectly subscripts
1146 * a register file. The direct index now becomes an offset
1147 * that is being added to the indirect register.
1148 *
1149 * file[ind[2].x+1],
1150 * where:
1151 * ind = Indirect.File
1152 * [2] = Indirect.Index
1153 * .x = Indirect.SwizzleX
1154 */
1155 if (reg->Register.Indirect) {
1156 union tgsi_exec_channel index2;
1157 union tgsi_exec_channel indir_index;
1158 const uint execmask = mach->ExecMask;
1159 uint i;
1160
1161 /* which address register (always zero now) */
1162 index2.i[0] =
1163 index2.i[1] =
1164 index2.i[2] =
1165 index2.i[3] = reg->Indirect.Index;
1166 /* get current value of address register[swizzle] */
1167 swizzle = reg->Indirect.Swizzle;
1168 fetch_src_file_channel(mach,
1169 chan_index,
1170 reg->Indirect.File,
1171 swizzle,
1172 &index2,
1173 &ZeroVec,
1174 &indir_index);
1175
1176 /* add value of address register to the offset */
1177 index.i[0] += indir_index.i[0];
1178 index.i[1] += indir_index.i[1];
1179 index.i[2] += indir_index.i[2];
1180 index.i[3] += indir_index.i[3];
1181
1182 /* for disabled execution channels, zero-out the index to
1183 * avoid using a potential garbage value.
1184 */
1185 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1186 if ((execmask & (1 << i)) == 0)
1187 index.i[i] = 0;
1188 }
1189 }
1190
1191 /* There is an extra source register that is a second
1192 * subscript to a register file. Effectively it means that
1193 * the register file is actually a 2D array of registers.
1194 *
1195 * file[3][1],
1196 * where:
1197 * [3] = Dimension.Index
1198 */
1199 if (reg->Register.Dimension) {
1200 index2D.i[0] =
1201 index2D.i[1] =
1202 index2D.i[2] =
1203 index2D.i[3] = reg->Dimension.Index;
1204
1205 /* Again, the second subscript index can be addressed indirectly
1206 * identically to the first one.
1207 * Nothing stops us from indirectly addressing the indirect register,
1208 * but there is no need for that, so we won't exercise it.
1209 *
1210 * file[ind[4].y+3][1],
1211 * where:
1212 * ind = DimIndirect.File
1213 * [4] = DimIndirect.Index
1214 * .y = DimIndirect.SwizzleX
1215 */
1216 if (reg->Dimension.Indirect) {
1217 union tgsi_exec_channel index2;
1218 union tgsi_exec_channel indir_index;
1219 const uint execmask = mach->ExecMask;
1220 uint i;
1221
1222 index2.i[0] =
1223 index2.i[1] =
1224 index2.i[2] =
1225 index2.i[3] = reg->DimIndirect.Index;
1226
1227 swizzle = reg->DimIndirect.Swizzle;
1228 fetch_src_file_channel(mach,
1229 chan_index,
1230 reg->DimIndirect.File,
1231 swizzle,
1232 &index2,
1233 &ZeroVec,
1234 &indir_index);
1235
1236 index2D.i[0] += indir_index.i[0];
1237 index2D.i[1] += indir_index.i[1];
1238 index2D.i[2] += indir_index.i[2];
1239 index2D.i[3] += indir_index.i[3];
1240
1241 /* for disabled execution channels, zero-out the index to
1242 * avoid using a potential garbage value.
1243 */
1244 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1245 if ((execmask & (1 << i)) == 0) {
1246 index2D.i[i] = 0;
1247 }
1248 }
1249 }
1250
1251 /* If by any chance there was a need for a 3D array of register
1252 * files, we would have to check whether Dimension is followed
1253 * by a dimension register and continue the saga.
1254 */
1255 } else {
1256 index2D.i[0] =
1257 index2D.i[1] =
1258 index2D.i[2] =
1259 index2D.i[3] = 0;
1260 }
1261
1262 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1263 fetch_src_file_channel(mach,
1264 chan_index,
1265 reg->Register.File,
1266 swizzle,
1267 &index,
1268 &index2D,
1269 chan);
1270
1271 if (reg->Register.Absolute) {
1272 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1273 micro_abs(chan, chan);
1274 } else {
1275 micro_iabs(chan, chan);
1276 }
1277 }
1278
1279 if (reg->Register.Negate) {
1280 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1281 micro_neg(chan, chan);
1282 } else {
1283 micro_ineg(chan, chan);
1284 }
1285 }
1286 }
1287
1288 static void
1289 store_dest(struct tgsi_exec_machine *mach,
1290 const union tgsi_exec_channel *chan,
1291 const struct tgsi_full_dst_register *reg,
1292 const struct tgsi_full_instruction *inst,
1293 uint chan_index,
1294 enum tgsi_exec_datatype dst_datatype)
1295 {
1296 uint i;
1297 union tgsi_exec_channel null;
1298 union tgsi_exec_channel *dst;
1299 union tgsi_exec_channel index2D;
1300 uint execmask = mach->ExecMask;
1301 int offset = 0; /* indirection offset */
1302 int index;
1303
1304 /* for debugging */
1305 if (0 && dst_datatype == TGSI_EXEC_DATA_FLOAT) {
1306 check_inf_or_nan(chan);
1307 }
1308
1309 /* There is an extra source register that indirectly subscripts
1310 * a register file. The direct index now becomes an offset
1311 * that is being added to the indirect register.
1312 *
1313 * file[ind[2].x+1],
1314 * where:
1315 * ind = Indirect.File
1316 * [2] = Indirect.Index
1317 * .x = Indirect.SwizzleX
1318 */
1319 if (reg->Register.Indirect) {
1320 union tgsi_exec_channel index;
1321 union tgsi_exec_channel indir_index;
1322 uint swizzle;
1323
1324 /* which address register (always zero for now) */
1325 index.i[0] =
1326 index.i[1] =
1327 index.i[2] =
1328 index.i[3] = reg->Indirect.Index;
1329
1330 /* get current value of address register[swizzle] */
1331 swizzle = reg->Indirect.Swizzle;
1332
1333 /* fetch values from the address/indirection register */
1334 fetch_src_file_channel(mach,
1335 chan_index,
1336 reg->Indirect.File,
1337 swizzle,
1338 &index,
1339 &ZeroVec,
1340 &indir_index);
1341
1342 /* save indirection offset */
1343 offset = indir_index.i[0];
1344 }
1345
1346 /* There is an extra source register that is a second
1347 * subscript to a register file. Effectively it means that
1348 * the register file is actually a 2D array of registers.
1349 *
1350 * file[3][1],
1351 * where:
1352 * [3] = Dimension.Index
1353 */
1354 if (reg->Register.Dimension) {
1355 index2D.i[0] =
1356 index2D.i[1] =
1357 index2D.i[2] =
1358 index2D.i[3] = reg->Dimension.Index;
1359
1360 /* Again, the second subscript index can be addressed indirectly
1361 * identically to the first one.
1362 * Nothing stops us from indirectly addressing the indirect register,
1363 * but there is no need for that, so we won't exercise it.
1364 *
1365 * file[ind[4].y+3][1],
1366 * where:
1367 * ind = DimIndirect.File
1368 * [4] = DimIndirect.Index
1369 * .y = DimIndirect.SwizzleX
1370 */
1371 if (reg->Dimension.Indirect) {
1372 union tgsi_exec_channel index2;
1373 union tgsi_exec_channel indir_index;
1374 const uint execmask = mach->ExecMask;
1375 unsigned swizzle;
1376 uint i;
1377
1378 index2.i[0] =
1379 index2.i[1] =
1380 index2.i[2] =
1381 index2.i[3] = reg->DimIndirect.Index;
1382
1383 swizzle = reg->DimIndirect.Swizzle;
1384 fetch_src_file_channel(mach,
1385 chan_index,
1386 reg->DimIndirect.File,
1387 swizzle,
1388 &index2,
1389 &ZeroVec,
1390 &indir_index);
1391
1392 index2D.i[0] += indir_index.i[0];
1393 index2D.i[1] += indir_index.i[1];
1394 index2D.i[2] += indir_index.i[2];
1395 index2D.i[3] += indir_index.i[3];
1396
1397 /* for disabled execution channels, zero-out the index to
1398 * avoid using a potential garbage value.
1399 */
1400 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1401 if ((execmask & (1 << i)) == 0) {
1402 index2D.i[i] = 0;
1403 }
1404 }
1405 }
1406
1407 /* If by any chance there was a need for a 3D array of register
1408 * files, we would have to check whether Dimension is followed
1409 * by a dimension register and continue the saga.
1410 */
1411 } else {
1412 index2D.i[0] =
1413 index2D.i[1] =
1414 index2D.i[2] =
1415 index2D.i[3] = 0;
1416 }
1417
1418 switch (reg->Register.File) {
1419 case TGSI_FILE_NULL:
1420 dst = &null;
1421 break;
1422
1423 case TGSI_FILE_OUTPUT:
1424 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1425 + reg->Register.Index;
1426 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1427 #if 0
1428 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1429 mach->NumOutputs, mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0],
1430 reg->Register.Index);
1431 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1432 debug_printf("STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1433 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1434 if (execmask & (1 << i))
1435 debug_printf("%f, ", chan->f[i]);
1436 debug_printf(")\n");
1437 }
1438 #endif
1439 break;
1440
1441 case TGSI_FILE_TEMPORARY:
1442 index = reg->Register.Index;
1443 assert( index < TGSI_EXEC_NUM_TEMPS );
1444 dst = &mach->Temps[offset + index].xyzw[chan_index];
1445 break;
1446
1447 case TGSI_FILE_ADDRESS:
1448 index = reg->Register.Index;
1449 dst = &mach->Addrs[index].xyzw[chan_index];
1450 break;
1451
1452 case TGSI_FILE_PREDICATE:
1453 index = reg->Register.Index;
1454 assert(index < TGSI_EXEC_NUM_PREDS);
1455 dst = &mach->Predicates[index].xyzw[chan_index];
1456 break;
1457
1458 default:
1459 assert( 0 );
1460 return;
1461 }
1462
1463 if (inst->Instruction.Predicate) {
1464 uint swizzle;
1465 union tgsi_exec_channel *pred;
1466
1467 switch (chan_index) {
1468 case TGSI_CHAN_X:
1469 swizzle = inst->Predicate.SwizzleX;
1470 break;
1471 case TGSI_CHAN_Y:
1472 swizzle = inst->Predicate.SwizzleY;
1473 break;
1474 case TGSI_CHAN_Z:
1475 swizzle = inst->Predicate.SwizzleZ;
1476 break;
1477 case TGSI_CHAN_W:
1478 swizzle = inst->Predicate.SwizzleW;
1479 break;
1480 default:
1481 assert(0);
1482 return;
1483 }
1484
1485 assert(inst->Predicate.Index == 0);
1486
1487 pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
1488
1489 if (inst->Predicate.Negate) {
1490 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1491 if (pred->u[i]) {
1492 execmask &= ~(1 << i);
1493 }
1494 }
1495 } else {
1496 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1497 if (!pred->u[i]) {
1498 execmask &= ~(1 << i);
1499 }
1500 }
1501 }
1502 }
1503
1504 switch (inst->Instruction.Saturate) {
1505 case TGSI_SAT_NONE:
1506 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1507 if (execmask & (1 << i))
1508 dst->i[i] = chan->i[i];
1509 break;
1510
1511 case TGSI_SAT_ZERO_ONE:
1512 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1513 if (execmask & (1 << i)) {
1514 if (chan->f[i] < 0.0f)
1515 dst->f[i] = 0.0f;
1516 else if (chan->f[i] > 1.0f)
1517 dst->f[i] = 1.0f;
1518 else
1519 dst->i[i] = chan->i[i];
1520 }
1521 break;
1522
1523 case TGSI_SAT_MINUS_PLUS_ONE:
1524 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1525 if (execmask & (1 << i)) {
1526 if (chan->f[i] < -1.0f)
1527 dst->f[i] = -1.0f;
1528 else if (chan->f[i] > 1.0f)
1529 dst->f[i] = 1.0f;
1530 else
1531 dst->i[i] = chan->i[i];
1532 }
1533 break;
1534
1535 default:
1536 assert( 0 );
1537 }
1538 }
1539
1540 #define FETCH(VAL,INDEX,CHAN)\
1541 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1542
1543 #define IFETCH(VAL,INDEX,CHAN)\
1544 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1545
1546
1547 /**
1548 * Execute ARB-style KIL which is predicated by a src register.
1549 * Kill fragment if any of the four values is less than zero.
1550 */
1551 static void
1552 exec_kill_if(struct tgsi_exec_machine *mach,
1553 const struct tgsi_full_instruction *inst)
1554 {
1555 uint uniquemask;
1556 uint chan_index;
1557 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1558 union tgsi_exec_channel r[1];
1559
1560 /* This mask stores component bits that were already tested. */
1561 uniquemask = 0;
1562
1563 for (chan_index = 0; chan_index < 4; chan_index++)
1564 {
1565 uint swizzle;
1566 uint i;
1567
1568 /* unswizzle channel */
1569 swizzle = tgsi_util_get_full_src_register_swizzle (
1570 &inst->Src[0],
1571 chan_index);
1572
1573 /* check if the component has not been already tested */
1574 if (uniquemask & (1 << swizzle))
1575 continue;
1576 uniquemask |= 1 << swizzle;
1577
1578 FETCH(&r[0], 0, chan_index);
1579 for (i = 0; i < 4; i++)
1580 if (r[0].f[i] < 0.0f)
1581 kilmask |= 1 << i;
1582 }
1583
1584 /* restrict to fragments currently executing */
1585 kilmask &= mach->ExecMask;
1586
1587 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1588 }
1589
1590 /**
1591 * Unconditional fragment kill/discard.
1592 */
1593 static void
1594 exec_kill(struct tgsi_exec_machine *mach,
1595 const struct tgsi_full_instruction *inst)
1596 {
1597 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1598
1599 /* kill fragment for all fragments currently executing */
1600 kilmask = mach->ExecMask;
1601 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1602 }
1603
1604 static void
1605 emit_vertex(struct tgsi_exec_machine *mach)
1606 {
1607 /* FIXME: check for exec mask correctly
1608 unsigned i;
1609 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1610 if ((mach->ExecMask & (1 << i)))
1611 */
1612 if (mach->ExecMask) {
1613 if (mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]] >= mach->MaxOutputVertices)
1614 return;
1615
1616 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += mach->NumOutputs;
1617 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
1618 }
1619 }
1620
1621 static void
1622 emit_primitive(struct tgsi_exec_machine *mach)
1623 {
1624 unsigned *prim_count = &mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0];
1625 /* FIXME: check for exec mask correctly
1626 unsigned i;
1627 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1628 if ((mach->ExecMask & (1 << i)))
1629 */
1630 if (mach->ExecMask) {
1631 ++(*prim_count);
1632 debug_assert((*prim_count * mach->NumOutputs) < mach->MaxGeometryShaderOutputs);
1633 mach->Primitives[*prim_count] = 0;
1634 }
1635 }
1636
1637 static void
1638 conditional_emit_primitive(struct tgsi_exec_machine *mach)
1639 {
1640 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1641 int emitted_verts =
1642 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]];
1643 if (emitted_verts) {
1644 emit_primitive(mach);
1645 }
1646 }
1647 }
1648
1649
1650 /*
1651 * Fetch four texture samples using STR texture coordinates.
1652 */
1653 static void
1654 fetch_texel( struct tgsi_sampler *sampler,
1655 const unsigned sview_idx,
1656 const unsigned sampler_idx,
1657 const union tgsi_exec_channel *s,
1658 const union tgsi_exec_channel *t,
1659 const union tgsi_exec_channel *p,
1660 const union tgsi_exec_channel *c0,
1661 const union tgsi_exec_channel *c1,
1662 float derivs[3][2][TGSI_QUAD_SIZE],
1663 const int8_t offset[3],
1664 enum tgsi_sampler_control control,
1665 union tgsi_exec_channel *r,
1666 union tgsi_exec_channel *g,
1667 union tgsi_exec_channel *b,
1668 union tgsi_exec_channel *a )
1669 {
1670 uint j;
1671 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
1672
1673 /* FIXME: handle explicit derivs, offsets */
1674 sampler->get_samples(sampler, sview_idx, sampler_idx,
1675 s->f, t->f, p->f, c0->f, c1->f, derivs, offset, control, rgba);
1676
1677 for (j = 0; j < 4; j++) {
1678 r->f[j] = rgba[0][j];
1679 g->f[j] = rgba[1][j];
1680 b->f[j] = rgba[2][j];
1681 a->f[j] = rgba[3][j];
1682 }
1683 }
1684
1685
1686 #define TEX_MODIFIER_NONE 0
1687 #define TEX_MODIFIER_PROJECTED 1
1688 #define TEX_MODIFIER_LOD_BIAS 2
1689 #define TEX_MODIFIER_EXPLICIT_LOD 3
1690 #define TEX_MODIFIER_LEVEL_ZERO 4
1691
1692
1693 /*
1694 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
1695 */
1696 static void
1697 fetch_texel_offsets(struct tgsi_exec_machine *mach,
1698 const struct tgsi_full_instruction *inst,
1699 int8_t offsets[3])
1700 {
1701 if (inst->Texture.NumOffsets == 1) {
1702 union tgsi_exec_channel index;
1703 union tgsi_exec_channel offset[3];
1704 index.i[0] = index.i[1] = index.i[2] = index.i[3] = inst->TexOffsets[0].Index;
1705 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1706 inst->TexOffsets[0].SwizzleX, &index, &ZeroVec, &offset[0]);
1707 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1708 inst->TexOffsets[0].SwizzleY, &index, &ZeroVec, &offset[1]);
1709 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1710 inst->TexOffsets[0].SwizzleZ, &index, &ZeroVec, &offset[2]);
1711 offsets[0] = offset[0].i[0];
1712 offsets[1] = offset[1].i[0];
1713 offsets[2] = offset[2].i[0];
1714 } else {
1715 assert(inst->Texture.NumOffsets == 0);
1716 offsets[0] = offsets[1] = offsets[2] = 0;
1717 }
1718 }
1719
1720
1721 /*
1722 * Fetch dx and dy values for one channel (s, t or r).
1723 * Put dx values into one float array, dy values into another.
1724 */
1725 static void
1726 fetch_assign_deriv_channel(struct tgsi_exec_machine *mach,
1727 const struct tgsi_full_instruction *inst,
1728 unsigned regdsrcx,
1729 unsigned chan,
1730 float derivs[2][TGSI_QUAD_SIZE])
1731 {
1732 union tgsi_exec_channel d;
1733 FETCH(&d, regdsrcx, chan);
1734 derivs[0][0] = d.f[0];
1735 derivs[0][1] = d.f[1];
1736 derivs[0][2] = d.f[2];
1737 derivs[0][3] = d.f[3];
1738 FETCH(&d, regdsrcx + 1, chan);
1739 derivs[1][0] = d.f[0];
1740 derivs[1][1] = d.f[1];
1741 derivs[1][2] = d.f[2];
1742 derivs[1][3] = d.f[3];
1743 }
1744
1745
1746 /*
1747 * execute a texture instruction.
1748 *
1749 * modifier is used to control the channel routing for the\
1750 * instruction variants like proj, lod, and texture with lod bias.
1751 * sampler indicates which src register the sampler is contained in.
1752 */
1753 static void
1754 exec_tex(struct tgsi_exec_machine *mach,
1755 const struct tgsi_full_instruction *inst,
1756 uint modifier, uint sampler)
1757 {
1758 const uint unit = inst->Src[sampler].Register.Index;
1759 const union tgsi_exec_channel *args[5], *proj = NULL;
1760 union tgsi_exec_channel r[5];
1761 enum tgsi_sampler_control control = tgsi_sampler_lod_none;
1762 uint chan;
1763 int8_t offsets[3];
1764 int dim, shadow_ref, i;
1765
1766 /* always fetch all 3 offsets, overkill but keeps code simple */
1767 fetch_texel_offsets(mach, inst, offsets);
1768
1769 assert(modifier != TEX_MODIFIER_LEVEL_ZERO);
1770 assert(inst->Texture.Texture != TGSI_TEXTURE_BUFFER);
1771
1772 dim = tgsi_util_get_texture_coord_dim(inst->Texture.Texture, &shadow_ref);
1773
1774 assert(dim <= 4);
1775 if (shadow_ref >= 0)
1776 assert(shadow_ref >= dim && shadow_ref < Elements(args));
1777
1778 /* fetch modifier to the last argument */
1779 if (modifier != TEX_MODIFIER_NONE) {
1780 const int last = Elements(args) - 1;
1781
1782 /* fetch modifier from src0.w or src1.x */
1783 if (sampler == 1) {
1784 assert(dim <= TGSI_CHAN_W && shadow_ref != TGSI_CHAN_W);
1785 FETCH(&r[last], 0, TGSI_CHAN_W);
1786 }
1787 else {
1788 assert(shadow_ref != 4);
1789 FETCH(&r[last], 1, TGSI_CHAN_X);
1790 }
1791
1792 if (modifier != TEX_MODIFIER_PROJECTED) {
1793 args[last] = &r[last];
1794 }
1795 else {
1796 proj = &r[last];
1797 args[last] = &ZeroVec;
1798 }
1799
1800 /* point unused arguments to zero vector */
1801 for (i = dim; i < last; i++)
1802 args[i] = &ZeroVec;
1803
1804 if (modifier == TEX_MODIFIER_EXPLICIT_LOD)
1805 control = tgsi_sampler_lod_explicit;
1806 else if (modifier == TEX_MODIFIER_LOD_BIAS)
1807 control = tgsi_sampler_lod_bias;
1808 }
1809 else {
1810 for (i = dim; i < Elements(args); i++)
1811 args[i] = &ZeroVec;
1812 }
1813
1814 /* fetch coordinates */
1815 for (i = 0; i < dim; i++) {
1816 FETCH(&r[i], 0, TGSI_CHAN_X + i);
1817
1818 if (proj)
1819 micro_div(&r[i], &r[i], proj);
1820
1821 args[i] = &r[i];
1822 }
1823
1824 /* fetch reference value */
1825 if (shadow_ref >= 0) {
1826 FETCH(&r[shadow_ref], shadow_ref / 4, TGSI_CHAN_X + (shadow_ref % 4));
1827
1828 if (proj)
1829 micro_div(&r[shadow_ref], &r[shadow_ref], proj);
1830
1831 args[shadow_ref] = &r[shadow_ref];
1832 }
1833
1834 fetch_texel(mach->Sampler, unit, unit,
1835 args[0], args[1], args[2], args[3], args[4],
1836 NULL, offsets, control,
1837 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1838
1839 #if 0
1840 debug_printf("fetch r: %g %g %g %g\n",
1841 r[0].f[0], r[0].f[1], r[0].f[2], r[0].f[3]);
1842 debug_printf("fetch g: %g %g %g %g\n",
1843 r[1].f[0], r[1].f[1], r[1].f[2], r[1].f[3]);
1844 debug_printf("fetch b: %g %g %g %g\n",
1845 r[2].f[0], r[2].f[1], r[2].f[2], r[2].f[3]);
1846 debug_printf("fetch a: %g %g %g %g\n",
1847 r[3].f[0], r[3].f[1], r[3].f[2], r[3].f[3]);
1848 #endif
1849
1850 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1851 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1852 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1853 }
1854 }
1855 }
1856
1857
1858 static void
1859 exec_txd(struct tgsi_exec_machine *mach,
1860 const struct tgsi_full_instruction *inst)
1861 {
1862 const uint unit = inst->Src[3].Register.Index;
1863 union tgsi_exec_channel r[4];
1864 float derivs[3][2][TGSI_QUAD_SIZE];
1865 uint chan;
1866 int8_t offsets[3];
1867
1868 /* always fetch all 3 offsets, overkill but keeps code simple */
1869 fetch_texel_offsets(mach, inst, offsets);
1870
1871 switch (inst->Texture.Texture) {
1872 case TGSI_TEXTURE_1D:
1873 FETCH(&r[0], 0, TGSI_CHAN_X);
1874
1875 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1876
1877 fetch_texel(mach->Sampler, unit, unit,
1878 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
1879 derivs, offsets, tgsi_sampler_derivs_explicit,
1880 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1881 break;
1882
1883 case TGSI_TEXTURE_SHADOW1D:
1884 case TGSI_TEXTURE_1D_ARRAY:
1885 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1886 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
1887 FETCH(&r[0], 0, TGSI_CHAN_X);
1888 FETCH(&r[1], 0, TGSI_CHAN_Y);
1889 FETCH(&r[2], 0, TGSI_CHAN_Z);
1890
1891 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1892
1893 fetch_texel(mach->Sampler, unit, unit,
1894 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
1895 derivs, offsets, tgsi_sampler_derivs_explicit,
1896 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1897 break;
1898
1899 case TGSI_TEXTURE_2D:
1900 case TGSI_TEXTURE_RECT:
1901 FETCH(&r[0], 0, TGSI_CHAN_X);
1902 FETCH(&r[1], 0, TGSI_CHAN_Y);
1903
1904 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1905 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
1906
1907 fetch_texel(mach->Sampler, unit, unit,
1908 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
1909 derivs, offsets, tgsi_sampler_derivs_explicit,
1910 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1911 break;
1912
1913
1914 case TGSI_TEXTURE_SHADOW2D:
1915 case TGSI_TEXTURE_SHADOWRECT:
1916 case TGSI_TEXTURE_2D_ARRAY:
1917 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1918 /* only SHADOW2D_ARRAY actually needs W */
1919 FETCH(&r[0], 0, TGSI_CHAN_X);
1920 FETCH(&r[1], 0, TGSI_CHAN_Y);
1921 FETCH(&r[2], 0, TGSI_CHAN_Z);
1922 FETCH(&r[3], 0, TGSI_CHAN_W);
1923
1924 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1925 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
1926
1927 fetch_texel(mach->Sampler, unit, unit,
1928 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
1929 derivs, offsets, tgsi_sampler_derivs_explicit,
1930 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1931 break;
1932
1933 case TGSI_TEXTURE_3D:
1934 case TGSI_TEXTURE_CUBE:
1935 case TGSI_TEXTURE_CUBE_ARRAY:
1936 case TGSI_TEXTURE_SHADOWCUBE:
1937 /* only TEXTURE_CUBE_ARRAY and TEXTURE_SHADOWCUBE actually need W */
1938 FETCH(&r[0], 0, TGSI_CHAN_X);
1939 FETCH(&r[1], 0, TGSI_CHAN_Y);
1940 FETCH(&r[2], 0, TGSI_CHAN_Z);
1941 FETCH(&r[3], 0, TGSI_CHAN_W);
1942
1943 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1944 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
1945 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Z, derivs[2]);
1946
1947 fetch_texel(mach->Sampler, unit, unit,
1948 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
1949 derivs, offsets, tgsi_sampler_derivs_explicit,
1950 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1951 break;
1952
1953 default:
1954 assert(0);
1955 }
1956
1957 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1958 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1959 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1960 }
1961 }
1962 }
1963
1964
1965 static void
1966 exec_txf(struct tgsi_exec_machine *mach,
1967 const struct tgsi_full_instruction *inst)
1968 {
1969 const uint unit = inst->Src[1].Register.Index;
1970 union tgsi_exec_channel r[4];
1971 uint chan;
1972 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
1973 int j;
1974 int8_t offsets[3];
1975 unsigned target;
1976
1977 /* always fetch all 3 offsets, overkill but keeps code simple */
1978 fetch_texel_offsets(mach, inst, offsets);
1979
1980 IFETCH(&r[3], 0, TGSI_CHAN_W);
1981
1982 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I) {
1983 target = mach->SamplerViews[unit].Resource;
1984 }
1985 else {
1986 target = inst->Texture.Texture;
1987 }
1988 switch(target) {
1989 case TGSI_TEXTURE_3D:
1990 case TGSI_TEXTURE_2D_ARRAY:
1991 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1992 case TGSI_TEXTURE_2D_ARRAY_MSAA:
1993 IFETCH(&r[2], 0, TGSI_CHAN_Z);
1994 /* fallthrough */
1995 case TGSI_TEXTURE_2D:
1996 case TGSI_TEXTURE_RECT:
1997 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1998 case TGSI_TEXTURE_SHADOW2D:
1999 case TGSI_TEXTURE_SHADOWRECT:
2000 case TGSI_TEXTURE_1D_ARRAY:
2001 case TGSI_TEXTURE_2D_MSAA:
2002 IFETCH(&r[1], 0, TGSI_CHAN_Y);
2003 /* fallthrough */
2004 case TGSI_TEXTURE_BUFFER:
2005 case TGSI_TEXTURE_1D:
2006 case TGSI_TEXTURE_SHADOW1D:
2007 IFETCH(&r[0], 0, TGSI_CHAN_X);
2008 break;
2009 default:
2010 assert(0);
2011 break;
2012 }
2013
2014 mach->Sampler->get_texel(mach->Sampler, unit, r[0].i, r[1].i, r[2].i, r[3].i,
2015 offsets, rgba);
2016
2017 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
2018 r[0].f[j] = rgba[0][j];
2019 r[1].f[j] = rgba[1][j];
2020 r[2].f[j] = rgba[2][j];
2021 r[3].f[j] = rgba[3][j];
2022 }
2023
2024 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I) {
2025 unsigned char swizzles[4];
2026 swizzles[0] = inst->Src[1].Register.SwizzleX;
2027 swizzles[1] = inst->Src[1].Register.SwizzleY;
2028 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2029 swizzles[3] = inst->Src[1].Register.SwizzleW;
2030
2031 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2032 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2033 store_dest(mach, &r[swizzles[chan]],
2034 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2035 }
2036 }
2037 }
2038 else {
2039 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2040 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2041 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2042 }
2043 }
2044 }
2045 }
2046
2047 static void
2048 exec_txq(struct tgsi_exec_machine *mach,
2049 const struct tgsi_full_instruction *inst)
2050 {
2051 const uint unit = inst->Src[1].Register.Index;
2052 int result[4];
2053 union tgsi_exec_channel r[4], src;
2054 uint chan;
2055 int i,j;
2056
2057 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
2058
2059 /* XXX: This interface can't return per-pixel values */
2060 mach->Sampler->get_dims(mach->Sampler, unit, src.i[0], result);
2061
2062 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2063 for (j = 0; j < 4; j++) {
2064 r[j].i[i] = result[j];
2065 }
2066 }
2067
2068 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2069 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2070 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
2071 TGSI_EXEC_DATA_INT);
2072 }
2073 }
2074 }
2075
2076 static void
2077 exec_sample(struct tgsi_exec_machine *mach,
2078 const struct tgsi_full_instruction *inst,
2079 uint modifier, boolean compare)
2080 {
2081 const uint resource_unit = inst->Src[1].Register.Index;
2082 const uint sampler_unit = inst->Src[2].Register.Index;
2083 union tgsi_exec_channel r[4], c1;
2084 const union tgsi_exec_channel *lod = &ZeroVec;
2085 enum tgsi_sampler_control control = tgsi_sampler_lod_none;
2086 uint chan;
2087 unsigned char swizzles[4];
2088 int8_t offsets[3];
2089
2090 /* always fetch all 3 offsets, overkill but keeps code simple */
2091 fetch_texel_offsets(mach, inst, offsets);
2092
2093 assert(modifier != TEX_MODIFIER_PROJECTED);
2094
2095 if (modifier != TEX_MODIFIER_NONE) {
2096 if (modifier == TEX_MODIFIER_LOD_BIAS) {
2097 FETCH(&c1, 3, TGSI_CHAN_X);
2098 lod = &c1;
2099 control = tgsi_sampler_lod_bias;
2100 }
2101 else if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
2102 FETCH(&c1, 3, TGSI_CHAN_X);
2103 lod = &c1;
2104 control = tgsi_sampler_lod_explicit;
2105 }
2106 else {
2107 assert(modifier == TEX_MODIFIER_LEVEL_ZERO);
2108 control = tgsi_sampler_lod_zero;
2109 }
2110 }
2111
2112 FETCH(&r[0], 0, TGSI_CHAN_X);
2113
2114 switch (mach->SamplerViews[resource_unit].Resource) {
2115 case TGSI_TEXTURE_1D:
2116 if (compare) {
2117 FETCH(&r[2], 3, TGSI_CHAN_X);
2118 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2119 &r[0], &ZeroVec, &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2120 NULL, offsets, control,
2121 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2122 }
2123 else {
2124 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2125 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2126 NULL, offsets, control,
2127 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2128 }
2129 break;
2130
2131 case TGSI_TEXTURE_1D_ARRAY:
2132 case TGSI_TEXTURE_2D:
2133 case TGSI_TEXTURE_RECT:
2134 FETCH(&r[1], 0, TGSI_CHAN_Y);
2135 if (compare) {
2136 FETCH(&r[2], 3, TGSI_CHAN_X);
2137 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2138 &r[0], &r[1], &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2139 NULL, offsets, control,
2140 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2141 }
2142 else {
2143 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2144 &r[0], &r[1], &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2145 NULL, offsets, control,
2146 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2147 }
2148 break;
2149
2150 case TGSI_TEXTURE_2D_ARRAY:
2151 case TGSI_TEXTURE_3D:
2152 case TGSI_TEXTURE_CUBE:
2153 FETCH(&r[1], 0, TGSI_CHAN_Y);
2154 FETCH(&r[2], 0, TGSI_CHAN_Z);
2155 if(compare) {
2156 FETCH(&r[3], 3, TGSI_CHAN_X);
2157 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2158 &r[0], &r[1], &r[2], &r[3], lod,
2159 NULL, offsets, control,
2160 &r[0], &r[1], &r[2], &r[3]);
2161 }
2162 else {
2163 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2164 &r[0], &r[1], &r[2], &ZeroVec, lod,
2165 NULL, offsets, control,
2166 &r[0], &r[1], &r[2], &r[3]);
2167 }
2168 break;
2169
2170 case TGSI_TEXTURE_CUBE_ARRAY:
2171 FETCH(&r[1], 0, TGSI_CHAN_Y);
2172 FETCH(&r[2], 0, TGSI_CHAN_Z);
2173 FETCH(&r[3], 0, TGSI_CHAN_W);
2174 if(compare) {
2175 FETCH(&r[4], 3, TGSI_CHAN_X);
2176 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2177 &r[0], &r[1], &r[2], &r[3], &r[4],
2178 NULL, offsets, control,
2179 &r[0], &r[1], &r[2], &r[3]);
2180 }
2181 else {
2182 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2183 &r[0], &r[1], &r[2], &r[3], lod,
2184 NULL, offsets, control,
2185 &r[0], &r[1], &r[2], &r[3]);
2186 }
2187 break;
2188
2189
2190 default:
2191 assert(0);
2192 }
2193
2194 swizzles[0] = inst->Src[1].Register.SwizzleX;
2195 swizzles[1] = inst->Src[1].Register.SwizzleY;
2196 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2197 swizzles[3] = inst->Src[1].Register.SwizzleW;
2198
2199 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2200 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2201 store_dest(mach, &r[swizzles[chan]],
2202 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2203 }
2204 }
2205 }
2206
2207 static void
2208 exec_sample_d(struct tgsi_exec_machine *mach,
2209 const struct tgsi_full_instruction *inst)
2210 {
2211 const uint resource_unit = inst->Src[1].Register.Index;
2212 const uint sampler_unit = inst->Src[2].Register.Index;
2213 union tgsi_exec_channel r[4];
2214 float derivs[3][2][TGSI_QUAD_SIZE];
2215 uint chan;
2216 unsigned char swizzles[4];
2217 int8_t offsets[3];
2218
2219 /* always fetch all 3 offsets, overkill but keeps code simple */
2220 fetch_texel_offsets(mach, inst, offsets);
2221
2222 FETCH(&r[0], 0, TGSI_CHAN_X);
2223
2224 switch (mach->SamplerViews[resource_unit].Resource) {
2225 case TGSI_TEXTURE_1D:
2226 case TGSI_TEXTURE_1D_ARRAY:
2227 /* only 1D array actually needs Y */
2228 FETCH(&r[1], 0, TGSI_CHAN_Y);
2229
2230 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2231
2232 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2233 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2234 derivs, offsets, tgsi_sampler_derivs_explicit,
2235 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2236 break;
2237
2238 case TGSI_TEXTURE_2D:
2239 case TGSI_TEXTURE_RECT:
2240 case TGSI_TEXTURE_2D_ARRAY:
2241 /* only 2D array actually needs Z */
2242 FETCH(&r[1], 0, TGSI_CHAN_Y);
2243 FETCH(&r[2], 0, TGSI_CHAN_Z);
2244
2245 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2246 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2247
2248 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2249 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* inputs */
2250 derivs, offsets, tgsi_sampler_derivs_explicit,
2251 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2252 break;
2253
2254 case TGSI_TEXTURE_3D:
2255 case TGSI_TEXTURE_CUBE:
2256 case TGSI_TEXTURE_CUBE_ARRAY:
2257 /* only cube array actually needs W */
2258 FETCH(&r[1], 0, TGSI_CHAN_Y);
2259 FETCH(&r[2], 0, TGSI_CHAN_Z);
2260 FETCH(&r[3], 0, TGSI_CHAN_W);
2261
2262 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2263 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2264 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Z, derivs[2]);
2265
2266 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2267 &r[0], &r[1], &r[2], &r[3], &ZeroVec,
2268 derivs, offsets, tgsi_sampler_derivs_explicit,
2269 &r[0], &r[1], &r[2], &r[3]);
2270 break;
2271
2272 default:
2273 assert(0);
2274 }
2275
2276 swizzles[0] = inst->Src[1].Register.SwizzleX;
2277 swizzles[1] = inst->Src[1].Register.SwizzleY;
2278 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2279 swizzles[3] = inst->Src[1].Register.SwizzleW;
2280
2281 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2282 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2283 store_dest(mach, &r[swizzles[chan]],
2284 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2285 }
2286 }
2287 }
2288
2289
2290 /**
2291 * Evaluate a constant-valued coefficient at the position of the
2292 * current quad.
2293 */
2294 static void
2295 eval_constant_coef(
2296 struct tgsi_exec_machine *mach,
2297 unsigned attrib,
2298 unsigned chan )
2299 {
2300 unsigned i;
2301
2302 for( i = 0; i < TGSI_QUAD_SIZE; i++ ) {
2303 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
2304 }
2305 }
2306
2307 /**
2308 * Evaluate a linear-valued coefficient at the position of the
2309 * current quad.
2310 */
2311 static void
2312 eval_linear_coef(
2313 struct tgsi_exec_machine *mach,
2314 unsigned attrib,
2315 unsigned chan )
2316 {
2317 const float x = mach->QuadPos.xyzw[0].f[0];
2318 const float y = mach->QuadPos.xyzw[1].f[0];
2319 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2320 const float dady = mach->InterpCoefs[attrib].dady[chan];
2321 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2322 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
2323 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
2324 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
2325 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
2326 }
2327
2328 /**
2329 * Evaluate a perspective-valued coefficient at the position of the
2330 * current quad.
2331 */
2332 static void
2333 eval_perspective_coef(
2334 struct tgsi_exec_machine *mach,
2335 unsigned attrib,
2336 unsigned chan )
2337 {
2338 const float x = mach->QuadPos.xyzw[0].f[0];
2339 const float y = mach->QuadPos.xyzw[1].f[0];
2340 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2341 const float dady = mach->InterpCoefs[attrib].dady[chan];
2342 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2343 const float *w = mach->QuadPos.xyzw[3].f;
2344 /* divide by W here */
2345 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
2346 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
2347 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
2348 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
2349 }
2350
2351
2352 typedef void (* eval_coef_func)(
2353 struct tgsi_exec_machine *mach,
2354 unsigned attrib,
2355 unsigned chan );
2356
2357 static void
2358 exec_declaration(struct tgsi_exec_machine *mach,
2359 const struct tgsi_full_declaration *decl)
2360 {
2361 if (decl->Declaration.File == TGSI_FILE_SAMPLER_VIEW) {
2362 mach->SamplerViews[decl->Range.First] = decl->SamplerView;
2363 return;
2364 }
2365
2366 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
2367 if (decl->Declaration.File == TGSI_FILE_INPUT) {
2368 uint first, last, mask;
2369
2370 first = decl->Range.First;
2371 last = decl->Range.Last;
2372 mask = decl->Declaration.UsageMask;
2373
2374 /* XXX we could remove this special-case code since
2375 * mach->InterpCoefs[first].a0 should already have the
2376 * front/back-face value. But we should first update the
2377 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2378 * Then, we could remove the tgsi_exec_machine::Face field.
2379 */
2380 /* XXX make FACE a system value */
2381 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
2382 uint i;
2383
2384 assert(decl->Semantic.Index == 0);
2385 assert(first == last);
2386
2387 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2388 mach->Inputs[first].xyzw[0].f[i] = mach->Face;
2389 }
2390 } else {
2391 eval_coef_func eval;
2392 uint i, j;
2393
2394 switch (decl->Interp.Interpolate) {
2395 case TGSI_INTERPOLATE_CONSTANT:
2396 eval = eval_constant_coef;
2397 break;
2398
2399 case TGSI_INTERPOLATE_LINEAR:
2400 eval = eval_linear_coef;
2401 break;
2402
2403 case TGSI_INTERPOLATE_PERSPECTIVE:
2404 eval = eval_perspective_coef;
2405 break;
2406
2407 case TGSI_INTERPOLATE_COLOR:
2408 eval = mach->flatshade_color ? eval_constant_coef : eval_perspective_coef;
2409 break;
2410
2411 default:
2412 assert(0);
2413 return;
2414 }
2415
2416 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2417 if (mask & (1 << j)) {
2418 for (i = first; i <= last; i++) {
2419 eval(mach, i, j);
2420 }
2421 }
2422 }
2423 }
2424
2425 if (DEBUG_EXECUTION) {
2426 uint i, j;
2427 for (i = first; i <= last; ++i) {
2428 debug_printf("IN[%2u] = ", i);
2429 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2430 if (j > 0) {
2431 debug_printf(" ");
2432 }
2433 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
2434 mach->Inputs[i].xyzw[0].f[j], mach->Inputs[i].xyzw[0].u[j],
2435 mach->Inputs[i].xyzw[1].f[j], mach->Inputs[i].xyzw[1].u[j],
2436 mach->Inputs[i].xyzw[2].f[j], mach->Inputs[i].xyzw[2].u[j],
2437 mach->Inputs[i].xyzw[3].f[j], mach->Inputs[i].xyzw[3].u[j]);
2438 }
2439 }
2440 }
2441 }
2442 }
2443
2444 if (decl->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
2445 mach->SysSemanticToIndex[decl->Declaration.Semantic] = decl->Range.First;
2446 }
2447 }
2448
2449
2450 typedef void (* micro_op)(union tgsi_exec_channel *dst);
2451
2452 static void
2453 exec_vector(struct tgsi_exec_machine *mach,
2454 const struct tgsi_full_instruction *inst,
2455 micro_op op,
2456 enum tgsi_exec_datatype dst_datatype)
2457 {
2458 unsigned int chan;
2459
2460 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2461 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2462 union tgsi_exec_channel dst;
2463
2464 op(&dst);
2465 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2466 }
2467 }
2468 }
2469
2470 typedef void (* micro_unary_op)(union tgsi_exec_channel *dst,
2471 const union tgsi_exec_channel *src);
2472
2473 static void
2474 exec_scalar_unary(struct tgsi_exec_machine *mach,
2475 const struct tgsi_full_instruction *inst,
2476 micro_unary_op op,
2477 enum tgsi_exec_datatype dst_datatype,
2478 enum tgsi_exec_datatype src_datatype)
2479 {
2480 unsigned int chan;
2481 union tgsi_exec_channel src;
2482 union tgsi_exec_channel dst;
2483
2484 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, src_datatype);
2485 op(&dst, &src);
2486 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2487 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2488 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2489 }
2490 }
2491 }
2492
2493 static void
2494 exec_vector_unary(struct tgsi_exec_machine *mach,
2495 const struct tgsi_full_instruction *inst,
2496 micro_unary_op op,
2497 enum tgsi_exec_datatype dst_datatype,
2498 enum tgsi_exec_datatype src_datatype)
2499 {
2500 unsigned int chan;
2501 struct tgsi_exec_vector dst;
2502
2503 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2504 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2505 union tgsi_exec_channel src;
2506
2507 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
2508 op(&dst.xyzw[chan], &src);
2509 }
2510 }
2511 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2512 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2513 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2514 }
2515 }
2516 }
2517
2518 typedef void (* micro_binary_op)(union tgsi_exec_channel *dst,
2519 const union tgsi_exec_channel *src0,
2520 const union tgsi_exec_channel *src1);
2521
2522 static void
2523 exec_scalar_binary(struct tgsi_exec_machine *mach,
2524 const struct tgsi_full_instruction *inst,
2525 micro_binary_op op,
2526 enum tgsi_exec_datatype dst_datatype,
2527 enum tgsi_exec_datatype src_datatype)
2528 {
2529 unsigned int chan;
2530 union tgsi_exec_channel src[2];
2531 union tgsi_exec_channel dst;
2532
2533 fetch_source(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, src_datatype);
2534 fetch_source(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, src_datatype);
2535 op(&dst, &src[0], &src[1]);
2536 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2537 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2538 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2539 }
2540 }
2541 }
2542
2543 static void
2544 exec_vector_binary(struct tgsi_exec_machine *mach,
2545 const struct tgsi_full_instruction *inst,
2546 micro_binary_op op,
2547 enum tgsi_exec_datatype dst_datatype,
2548 enum tgsi_exec_datatype src_datatype)
2549 {
2550 unsigned int chan;
2551 struct tgsi_exec_vector dst;
2552
2553 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2554 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2555 union tgsi_exec_channel src[2];
2556
2557 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2558 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2559 op(&dst.xyzw[chan], &src[0], &src[1]);
2560 }
2561 }
2562 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2563 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2564 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2565 }
2566 }
2567 }
2568
2569 typedef void (* micro_trinary_op)(union tgsi_exec_channel *dst,
2570 const union tgsi_exec_channel *src0,
2571 const union tgsi_exec_channel *src1,
2572 const union tgsi_exec_channel *src2);
2573
2574 static void
2575 exec_vector_trinary(struct tgsi_exec_machine *mach,
2576 const struct tgsi_full_instruction *inst,
2577 micro_trinary_op op,
2578 enum tgsi_exec_datatype dst_datatype,
2579 enum tgsi_exec_datatype src_datatype)
2580 {
2581 unsigned int chan;
2582 struct tgsi_exec_vector dst;
2583
2584 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2585 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2586 union tgsi_exec_channel src[3];
2587
2588 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2589 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2590 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2591 op(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
2592 }
2593 }
2594 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2595 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2596 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2597 }
2598 }
2599 }
2600
2601 typedef void (* micro_quaternary_op)(union tgsi_exec_channel *dst,
2602 const union tgsi_exec_channel *src0,
2603 const union tgsi_exec_channel *src1,
2604 const union tgsi_exec_channel *src2,
2605 const union tgsi_exec_channel *src3);
2606
2607 static void
2608 exec_vector_quaternary(struct tgsi_exec_machine *mach,
2609 const struct tgsi_full_instruction *inst,
2610 micro_quaternary_op op,
2611 enum tgsi_exec_datatype dst_datatype,
2612 enum tgsi_exec_datatype src_datatype)
2613 {
2614 unsigned int chan;
2615 struct tgsi_exec_vector dst;
2616
2617 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2618 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2619 union tgsi_exec_channel src[4];
2620
2621 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2622 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2623 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2624 fetch_source(mach, &src[3], &inst->Src[3], chan, src_datatype);
2625 op(&dst.xyzw[chan], &src[0], &src[1], &src[2], &src[3]);
2626 }
2627 }
2628 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2629 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2630 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2631 }
2632 }
2633 }
2634
2635 static void
2636 exec_dp3(struct tgsi_exec_machine *mach,
2637 const struct tgsi_full_instruction *inst)
2638 {
2639 unsigned int chan;
2640 union tgsi_exec_channel arg[3];
2641
2642 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2643 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2644 micro_mul(&arg[2], &arg[0], &arg[1]);
2645
2646 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_Z; chan++) {
2647 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2648 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2649 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2650 }
2651
2652 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2653 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2654 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2655 }
2656 }
2657 }
2658
2659 static void
2660 exec_dp4(struct tgsi_exec_machine *mach,
2661 const struct tgsi_full_instruction *inst)
2662 {
2663 unsigned int chan;
2664 union tgsi_exec_channel arg[3];
2665
2666 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2667 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2668 micro_mul(&arg[2], &arg[0], &arg[1]);
2669
2670 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_W; chan++) {
2671 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2672 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2673 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2674 }
2675
2676 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2677 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2678 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2679 }
2680 }
2681 }
2682
2683 static void
2684 exec_dp2a(struct tgsi_exec_machine *mach,
2685 const struct tgsi_full_instruction *inst)
2686 {
2687 unsigned int chan;
2688 union tgsi_exec_channel arg[3];
2689
2690 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2691 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2692 micro_mul(&arg[2], &arg[0], &arg[1]);
2693
2694 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2695 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2696 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2697
2698 fetch_source(mach, &arg[1], &inst->Src[2], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2699 micro_add(&arg[0], &arg[0], &arg[1]);
2700
2701 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2702 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2703 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2704 }
2705 }
2706 }
2707
2708 static void
2709 exec_dph(struct tgsi_exec_machine *mach,
2710 const struct tgsi_full_instruction *inst)
2711 {
2712 unsigned int chan;
2713 union tgsi_exec_channel arg[3];
2714
2715 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2716 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2717 micro_mul(&arg[2], &arg[0], &arg[1]);
2718
2719 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2720 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2721 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2722
2723 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2724 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2725 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2726
2727 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2728 micro_add(&arg[0], &arg[0], &arg[1]);
2729
2730 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2731 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2732 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2733 }
2734 }
2735 }
2736
2737 static void
2738 exec_dp2(struct tgsi_exec_machine *mach,
2739 const struct tgsi_full_instruction *inst)
2740 {
2741 unsigned int chan;
2742 union tgsi_exec_channel arg[3];
2743
2744 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2745 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2746 micro_mul(&arg[2], &arg[0], &arg[1]);
2747
2748 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2749 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2750 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2751
2752 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2753 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2754 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2755 }
2756 }
2757 }
2758
2759 static void
2760 exec_scs(struct tgsi_exec_machine *mach,
2761 const struct tgsi_full_instruction *inst)
2762 {
2763 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) {
2764 union tgsi_exec_channel arg;
2765 union tgsi_exec_channel result;
2766
2767 fetch_source(mach, &arg, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2768
2769 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2770 micro_cos(&result, &arg);
2771 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2772 }
2773 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2774 micro_sin(&result, &arg);
2775 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2776 }
2777 }
2778 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2779 store_dest(mach, &ZeroVec, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2780 }
2781 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2782 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2783 }
2784 }
2785
2786 static void
2787 exec_rfl(struct tgsi_exec_machine *mach,
2788 const struct tgsi_full_instruction *inst)
2789 {
2790 union tgsi_exec_channel r[9];
2791
2792 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
2793 /* r0 = dp3(src0, src0) */
2794 fetch_source(mach, &r[2], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2795 micro_mul(&r[0], &r[2], &r[2]);
2796 fetch_source(mach, &r[4], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2797 micro_mul(&r[8], &r[4], &r[4]);
2798 micro_add(&r[0], &r[0], &r[8]);
2799 fetch_source(mach, &r[6], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2800 micro_mul(&r[8], &r[6], &r[6]);
2801 micro_add(&r[0], &r[0], &r[8]);
2802
2803 /* r1 = dp3(src0, src1) */
2804 fetch_source(mach, &r[3], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2805 micro_mul(&r[1], &r[2], &r[3]);
2806 fetch_source(mach, &r[5], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2807 micro_mul(&r[8], &r[4], &r[5]);
2808 micro_add(&r[1], &r[1], &r[8]);
2809 fetch_source(mach, &r[7], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2810 micro_mul(&r[8], &r[6], &r[7]);
2811 micro_add(&r[1], &r[1], &r[8]);
2812
2813 /* r1 = 2 * r1 / r0 */
2814 micro_add(&r[1], &r[1], &r[1]);
2815 micro_div(&r[1], &r[1], &r[0]);
2816
2817 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2818 micro_mul(&r[2], &r[2], &r[1]);
2819 micro_sub(&r[2], &r[2], &r[3]);
2820 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2821 }
2822 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2823 micro_mul(&r[4], &r[4], &r[1]);
2824 micro_sub(&r[4], &r[4], &r[5]);
2825 store_dest(mach, &r[4], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2826 }
2827 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2828 micro_mul(&r[6], &r[6], &r[1]);
2829 micro_sub(&r[6], &r[6], &r[7]);
2830 store_dest(mach, &r[6], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2831 }
2832 }
2833 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2834 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2835 }
2836 }
2837
2838 static void
2839 exec_xpd(struct tgsi_exec_machine *mach,
2840 const struct tgsi_full_instruction *inst)
2841 {
2842 union tgsi_exec_channel r[6];
2843 union tgsi_exec_channel d[3];
2844
2845 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2846 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2847
2848 micro_mul(&r[2], &r[0], &r[1]);
2849
2850 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2851 fetch_source(mach, &r[4], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2852
2853 micro_mul(&r[5], &r[3], &r[4] );
2854 micro_sub(&d[TGSI_CHAN_X], &r[2], &r[5]);
2855
2856 fetch_source(mach, &r[2], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2857
2858 micro_mul(&r[3], &r[3], &r[2]);
2859
2860 fetch_source(mach, &r[5], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2861
2862 micro_mul(&r[1], &r[1], &r[5]);
2863 micro_sub(&d[TGSI_CHAN_Y], &r[3], &r[1]);
2864
2865 micro_mul(&r[5], &r[5], &r[4]);
2866 micro_mul(&r[0], &r[0], &r[2]);
2867 micro_sub(&d[TGSI_CHAN_Z], &r[5], &r[0]);
2868
2869 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2870 store_dest(mach, &d[TGSI_CHAN_X], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2871 }
2872 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2873 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2874 }
2875 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2876 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2877 }
2878 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2879 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2880 }
2881 }
2882
2883 static void
2884 exec_dst(struct tgsi_exec_machine *mach,
2885 const struct tgsi_full_instruction *inst)
2886 {
2887 union tgsi_exec_channel r[2];
2888 union tgsi_exec_channel d[4];
2889
2890 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2891 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2892 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2893 micro_mul(&d[TGSI_CHAN_Y], &r[0], &r[1]);
2894 }
2895 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2896 fetch_source(mach, &d[TGSI_CHAN_Z], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2897 }
2898 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2899 fetch_source(mach, &d[TGSI_CHAN_W], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2900 }
2901
2902 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2903 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2904 }
2905 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2906 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2907 }
2908 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2909 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2910 }
2911 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2912 store_dest(mach, &d[TGSI_CHAN_W], &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2913 }
2914 }
2915
2916 static void
2917 exec_log(struct tgsi_exec_machine *mach,
2918 const struct tgsi_full_instruction *inst)
2919 {
2920 union tgsi_exec_channel r[3];
2921
2922 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2923 micro_abs(&r[2], &r[0]); /* r2 = abs(r0) */
2924 micro_lg2(&r[1], &r[2]); /* r1 = lg2(r2) */
2925 micro_flr(&r[0], &r[1]); /* r0 = floor(r1) */
2926 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2927 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2928 }
2929 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2930 micro_exp2(&r[0], &r[0]); /* r0 = 2 ^ r0 */
2931 micro_div(&r[0], &r[2], &r[0]); /* r0 = r2 / r0 */
2932 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2933 }
2934 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2935 store_dest(mach, &r[1], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2936 }
2937 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2938 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2939 }
2940 }
2941
2942 static void
2943 exec_exp(struct tgsi_exec_machine *mach,
2944 const struct tgsi_full_instruction *inst)
2945 {
2946 union tgsi_exec_channel r[3];
2947
2948 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2949 micro_flr(&r[1], &r[0]); /* r1 = floor(r0) */
2950 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2951 micro_exp2(&r[2], &r[1]); /* r2 = 2 ^ r1 */
2952 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2953 }
2954 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2955 micro_sub(&r[2], &r[0], &r[1]); /* r2 = r0 - r1 */
2956 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2957 }
2958 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2959 micro_exp2(&r[2], &r[0]); /* r2 = 2 ^ r0 */
2960 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2961 }
2962 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2963 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2964 }
2965 }
2966
2967 static void
2968 exec_lit(struct tgsi_exec_machine *mach,
2969 const struct tgsi_full_instruction *inst)
2970 {
2971 union tgsi_exec_channel r[3];
2972 union tgsi_exec_channel d[3];
2973
2974 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YZ) {
2975 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2976 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2977 fetch_source(mach, &r[1], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2978 micro_max(&r[1], &r[1], &ZeroVec);
2979
2980 fetch_source(mach, &r[2], &inst->Src[0], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2981 micro_min(&r[2], &r[2], &P128Vec);
2982 micro_max(&r[2], &r[2], &M128Vec);
2983 micro_pow(&r[1], &r[1], &r[2]);
2984 micro_lt(&d[TGSI_CHAN_Z], &ZeroVec, &r[0], &r[1], &ZeroVec);
2985 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2986 }
2987 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2988 micro_max(&d[TGSI_CHAN_Y], &r[0], &ZeroVec);
2989 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2990 }
2991 }
2992 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2993 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2994 }
2995
2996 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2997 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2998 }
2999 }
3000
3001 static void
3002 exec_break(struct tgsi_exec_machine *mach)
3003 {
3004 if (mach->BreakType == TGSI_EXEC_BREAK_INSIDE_LOOP) {
3005 /* turn off loop channels for each enabled exec channel */
3006 mach->LoopMask &= ~mach->ExecMask;
3007 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3008 UPDATE_EXEC_MASK(mach);
3009 } else {
3010 assert(mach->BreakType == TGSI_EXEC_BREAK_INSIDE_SWITCH);
3011
3012 mach->Switch.mask = 0x0;
3013
3014 UPDATE_EXEC_MASK(mach);
3015 }
3016 }
3017
3018 static void
3019 exec_switch(struct tgsi_exec_machine *mach,
3020 const struct tgsi_full_instruction *inst)
3021 {
3022 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3023 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3024
3025 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3026 fetch_source(mach, &mach->Switch.selector, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3027 mach->Switch.mask = 0x0;
3028 mach->Switch.defaultMask = 0x0;
3029
3030 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3031 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_SWITCH;
3032
3033 UPDATE_EXEC_MASK(mach);
3034 }
3035
3036 static void
3037 exec_case(struct tgsi_exec_machine *mach,
3038 const struct tgsi_full_instruction *inst)
3039 {
3040 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3041 union tgsi_exec_channel src;
3042 uint mask = 0;
3043
3044 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3045
3046 if (mach->Switch.selector.u[0] == src.u[0]) {
3047 mask |= 0x1;
3048 }
3049 if (mach->Switch.selector.u[1] == src.u[1]) {
3050 mask |= 0x2;
3051 }
3052 if (mach->Switch.selector.u[2] == src.u[2]) {
3053 mask |= 0x4;
3054 }
3055 if (mach->Switch.selector.u[3] == src.u[3]) {
3056 mask |= 0x8;
3057 }
3058
3059 mach->Switch.defaultMask |= mask;
3060
3061 mach->Switch.mask |= mask & prevMask;
3062
3063 UPDATE_EXEC_MASK(mach);
3064 }
3065
3066 /* FIXME: this will only work if default is last */
3067 static void
3068 exec_default(struct tgsi_exec_machine *mach)
3069 {
3070 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3071
3072 mach->Switch.mask |= ~mach->Switch.defaultMask & prevMask;
3073
3074 UPDATE_EXEC_MASK(mach);
3075 }
3076
3077 static void
3078 exec_endswitch(struct tgsi_exec_machine *mach)
3079 {
3080 mach->Switch = mach->SwitchStack[--mach->SwitchStackTop];
3081 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3082
3083 UPDATE_EXEC_MASK(mach);
3084 }
3085
3086 static void
3087 micro_i2f(union tgsi_exec_channel *dst,
3088 const union tgsi_exec_channel *src)
3089 {
3090 dst->f[0] = (float)src->i[0];
3091 dst->f[1] = (float)src->i[1];
3092 dst->f[2] = (float)src->i[2];
3093 dst->f[3] = (float)src->i[3];
3094 }
3095
3096 static void
3097 micro_not(union tgsi_exec_channel *dst,
3098 const union tgsi_exec_channel *src)
3099 {
3100 dst->u[0] = ~src->u[0];
3101 dst->u[1] = ~src->u[1];
3102 dst->u[2] = ~src->u[2];
3103 dst->u[3] = ~src->u[3];
3104 }
3105
3106 static void
3107 micro_shl(union tgsi_exec_channel *dst,
3108 const union tgsi_exec_channel *src0,
3109 const union tgsi_exec_channel *src1)
3110 {
3111 unsigned masked_count;
3112 masked_count = src1->u[0] & 0x1f;
3113 dst->u[0] = src0->u[0] << masked_count;
3114 masked_count = src1->u[1] & 0x1f;
3115 dst->u[1] = src0->u[1] << masked_count;
3116 masked_count = src1->u[2] & 0x1f;
3117 dst->u[2] = src0->u[2] << masked_count;
3118 masked_count = src1->u[3] & 0x1f;
3119 dst->u[3] = src0->u[3] << masked_count;
3120 }
3121
3122 static void
3123 micro_and(union tgsi_exec_channel *dst,
3124 const union tgsi_exec_channel *src0,
3125 const union tgsi_exec_channel *src1)
3126 {
3127 dst->u[0] = src0->u[0] & src1->u[0];
3128 dst->u[1] = src0->u[1] & src1->u[1];
3129 dst->u[2] = src0->u[2] & src1->u[2];
3130 dst->u[3] = src0->u[3] & src1->u[3];
3131 }
3132
3133 static void
3134 micro_or(union tgsi_exec_channel *dst,
3135 const union tgsi_exec_channel *src0,
3136 const union tgsi_exec_channel *src1)
3137 {
3138 dst->u[0] = src0->u[0] | src1->u[0];
3139 dst->u[1] = src0->u[1] | src1->u[1];
3140 dst->u[2] = src0->u[2] | src1->u[2];
3141 dst->u[3] = src0->u[3] | src1->u[3];
3142 }
3143
3144 static void
3145 micro_xor(union tgsi_exec_channel *dst,
3146 const union tgsi_exec_channel *src0,
3147 const union tgsi_exec_channel *src1)
3148 {
3149 dst->u[0] = src0->u[0] ^ src1->u[0];
3150 dst->u[1] = src0->u[1] ^ src1->u[1];
3151 dst->u[2] = src0->u[2] ^ src1->u[2];
3152 dst->u[3] = src0->u[3] ^ src1->u[3];
3153 }
3154
3155 static void
3156 micro_mod(union tgsi_exec_channel *dst,
3157 const union tgsi_exec_channel *src0,
3158 const union tgsi_exec_channel *src1)
3159 {
3160 dst->i[0] = src0->i[0] % src1->i[0];
3161 dst->i[1] = src0->i[1] % src1->i[1];
3162 dst->i[2] = src0->i[2] % src1->i[2];
3163 dst->i[3] = src0->i[3] % src1->i[3];
3164 }
3165
3166 static void
3167 micro_f2i(union tgsi_exec_channel *dst,
3168 const union tgsi_exec_channel *src)
3169 {
3170 dst->i[0] = (int)src->f[0];
3171 dst->i[1] = (int)src->f[1];
3172 dst->i[2] = (int)src->f[2];
3173 dst->i[3] = (int)src->f[3];
3174 }
3175
3176 static void
3177 micro_fseq(union tgsi_exec_channel *dst,
3178 const union tgsi_exec_channel *src0,
3179 const union tgsi_exec_channel *src1)
3180 {
3181 dst->u[0] = src0->f[0] == src1->f[0] ? ~0 : 0;
3182 dst->u[1] = src0->f[1] == src1->f[1] ? ~0 : 0;
3183 dst->u[2] = src0->f[2] == src1->f[2] ? ~0 : 0;
3184 dst->u[3] = src0->f[3] == src1->f[3] ? ~0 : 0;
3185 }
3186
3187 static void
3188 micro_fsge(union tgsi_exec_channel *dst,
3189 const union tgsi_exec_channel *src0,
3190 const union tgsi_exec_channel *src1)
3191 {
3192 dst->u[0] = src0->f[0] >= src1->f[0] ? ~0 : 0;
3193 dst->u[1] = src0->f[1] >= src1->f[1] ? ~0 : 0;
3194 dst->u[2] = src0->f[2] >= src1->f[2] ? ~0 : 0;
3195 dst->u[3] = src0->f[3] >= src1->f[3] ? ~0 : 0;
3196 }
3197
3198 static void
3199 micro_fslt(union tgsi_exec_channel *dst,
3200 const union tgsi_exec_channel *src0,
3201 const union tgsi_exec_channel *src1)
3202 {
3203 dst->u[0] = src0->f[0] < src1->f[0] ? ~0 : 0;
3204 dst->u[1] = src0->f[1] < src1->f[1] ? ~0 : 0;
3205 dst->u[2] = src0->f[2] < src1->f[2] ? ~0 : 0;
3206 dst->u[3] = src0->f[3] < src1->f[3] ? ~0 : 0;
3207 }
3208
3209 static void
3210 micro_fsne(union tgsi_exec_channel *dst,
3211 const union tgsi_exec_channel *src0,
3212 const union tgsi_exec_channel *src1)
3213 {
3214 dst->u[0] = src0->f[0] != src1->f[0] ? ~0 : 0;
3215 dst->u[1] = src0->f[1] != src1->f[1] ? ~0 : 0;
3216 dst->u[2] = src0->f[2] != src1->f[2] ? ~0 : 0;
3217 dst->u[3] = src0->f[3] != src1->f[3] ? ~0 : 0;
3218 }
3219
3220 static void
3221 micro_idiv(union tgsi_exec_channel *dst,
3222 const union tgsi_exec_channel *src0,
3223 const union tgsi_exec_channel *src1)
3224 {
3225 dst->i[0] = src1->i[0] ? src0->i[0] / src1->i[0] : 0;
3226 dst->i[1] = src1->i[1] ? src0->i[1] / src1->i[1] : 0;
3227 dst->i[2] = src1->i[2] ? src0->i[2] / src1->i[2] : 0;
3228 dst->i[3] = src1->i[3] ? src0->i[3] / src1->i[3] : 0;
3229 }
3230
3231 static void
3232 micro_imax(union tgsi_exec_channel *dst,
3233 const union tgsi_exec_channel *src0,
3234 const union tgsi_exec_channel *src1)
3235 {
3236 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
3237 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
3238 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
3239 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
3240 }
3241
3242 static void
3243 micro_imin(union tgsi_exec_channel *dst,
3244 const union tgsi_exec_channel *src0,
3245 const union tgsi_exec_channel *src1)
3246 {
3247 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
3248 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
3249 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
3250 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
3251 }
3252
3253 static void
3254 micro_isge(union tgsi_exec_channel *dst,
3255 const union tgsi_exec_channel *src0,
3256 const union tgsi_exec_channel *src1)
3257 {
3258 dst->i[0] = src0->i[0] >= src1->i[0] ? -1 : 0;
3259 dst->i[1] = src0->i[1] >= src1->i[1] ? -1 : 0;
3260 dst->i[2] = src0->i[2] >= src1->i[2] ? -1 : 0;
3261 dst->i[3] = src0->i[3] >= src1->i[3] ? -1 : 0;
3262 }
3263
3264 static void
3265 micro_ishr(union tgsi_exec_channel *dst,
3266 const union tgsi_exec_channel *src0,
3267 const union tgsi_exec_channel *src1)
3268 {
3269 unsigned masked_count;
3270 masked_count = src1->i[0] & 0x1f;
3271 dst->i[0] = src0->i[0] >> masked_count;
3272 masked_count = src1->i[1] & 0x1f;
3273 dst->i[1] = src0->i[1] >> masked_count;
3274 masked_count = src1->i[2] & 0x1f;
3275 dst->i[2] = src0->i[2] >> masked_count;
3276 masked_count = src1->i[3] & 0x1f;
3277 dst->i[3] = src0->i[3] >> masked_count;
3278 }
3279
3280 static void
3281 micro_islt(union tgsi_exec_channel *dst,
3282 const union tgsi_exec_channel *src0,
3283 const union tgsi_exec_channel *src1)
3284 {
3285 dst->i[0] = src0->i[0] < src1->i[0] ? -1 : 0;
3286 dst->i[1] = src0->i[1] < src1->i[1] ? -1 : 0;
3287 dst->i[2] = src0->i[2] < src1->i[2] ? -1 : 0;
3288 dst->i[3] = src0->i[3] < src1->i[3] ? -1 : 0;
3289 }
3290
3291 static void
3292 micro_f2u(union tgsi_exec_channel *dst,
3293 const union tgsi_exec_channel *src)
3294 {
3295 dst->u[0] = (uint)src->f[0];
3296 dst->u[1] = (uint)src->f[1];
3297 dst->u[2] = (uint)src->f[2];
3298 dst->u[3] = (uint)src->f[3];
3299 }
3300
3301 static void
3302 micro_u2f(union tgsi_exec_channel *dst,
3303 const union tgsi_exec_channel *src)
3304 {
3305 dst->f[0] = (float)src->u[0];
3306 dst->f[1] = (float)src->u[1];
3307 dst->f[2] = (float)src->u[2];
3308 dst->f[3] = (float)src->u[3];
3309 }
3310
3311 static void
3312 micro_uadd(union tgsi_exec_channel *dst,
3313 const union tgsi_exec_channel *src0,
3314 const union tgsi_exec_channel *src1)
3315 {
3316 dst->u[0] = src0->u[0] + src1->u[0];
3317 dst->u[1] = src0->u[1] + src1->u[1];
3318 dst->u[2] = src0->u[2] + src1->u[2];
3319 dst->u[3] = src0->u[3] + src1->u[3];
3320 }
3321
3322 static void
3323 micro_udiv(union tgsi_exec_channel *dst,
3324 const union tgsi_exec_channel *src0,
3325 const union tgsi_exec_channel *src1)
3326 {
3327 dst->u[0] = src1->u[0] ? src0->u[0] / src1->u[0] : ~0u;
3328 dst->u[1] = src1->u[1] ? src0->u[1] / src1->u[1] : ~0u;
3329 dst->u[2] = src1->u[2] ? src0->u[2] / src1->u[2] : ~0u;
3330 dst->u[3] = src1->u[3] ? src0->u[3] / src1->u[3] : ~0u;
3331 }
3332
3333 static void
3334 micro_umad(union tgsi_exec_channel *dst,
3335 const union tgsi_exec_channel *src0,
3336 const union tgsi_exec_channel *src1,
3337 const union tgsi_exec_channel *src2)
3338 {
3339 dst->u[0] = src0->u[0] * src1->u[0] + src2->u[0];
3340 dst->u[1] = src0->u[1] * src1->u[1] + src2->u[1];
3341 dst->u[2] = src0->u[2] * src1->u[2] + src2->u[2];
3342 dst->u[3] = src0->u[3] * src1->u[3] + src2->u[3];
3343 }
3344
3345 static void
3346 micro_umax(union tgsi_exec_channel *dst,
3347 const union tgsi_exec_channel *src0,
3348 const union tgsi_exec_channel *src1)
3349 {
3350 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
3351 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
3352 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
3353 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
3354 }
3355
3356 static void
3357 micro_umin(union tgsi_exec_channel *dst,
3358 const union tgsi_exec_channel *src0,
3359 const union tgsi_exec_channel *src1)
3360 {
3361 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
3362 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
3363 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
3364 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
3365 }
3366
3367 static void
3368 micro_umod(union tgsi_exec_channel *dst,
3369 const union tgsi_exec_channel *src0,
3370 const union tgsi_exec_channel *src1)
3371 {
3372 dst->u[0] = src1->u[0] ? src0->u[0] % src1->u[0] : ~0u;
3373 dst->u[1] = src1->u[1] ? src0->u[1] % src1->u[1] : ~0u;
3374 dst->u[2] = src1->u[2] ? src0->u[2] % src1->u[2] : ~0u;
3375 dst->u[3] = src1->u[3] ? src0->u[3] % src1->u[3] : ~0u;
3376 }
3377
3378 static void
3379 micro_umul(union tgsi_exec_channel *dst,
3380 const union tgsi_exec_channel *src0,
3381 const union tgsi_exec_channel *src1)
3382 {
3383 dst->u[0] = src0->u[0] * src1->u[0];
3384 dst->u[1] = src0->u[1] * src1->u[1];
3385 dst->u[2] = src0->u[2] * src1->u[2];
3386 dst->u[3] = src0->u[3] * src1->u[3];
3387 }
3388
3389 static void
3390 micro_imul_hi(union tgsi_exec_channel *dst,
3391 const union tgsi_exec_channel *src0,
3392 const union tgsi_exec_channel *src1)
3393 {
3394 #define I64M(x, y) ((((int64_t)x) * ((int64_t)y)) >> 32)
3395 dst->i[0] = I64M(src0->i[0], src1->i[0]);
3396 dst->i[1] = I64M(src0->i[1], src1->i[1]);
3397 dst->i[2] = I64M(src0->i[2], src1->i[2]);
3398 dst->i[3] = I64M(src0->i[3], src1->i[3]);
3399 #undef I64M
3400 }
3401
3402 static void
3403 micro_umul_hi(union tgsi_exec_channel *dst,
3404 const union tgsi_exec_channel *src0,
3405 const union tgsi_exec_channel *src1)
3406 {
3407 #define U64M(x, y) ((((uint64_t)x) * ((uint64_t)y)) >> 32)
3408 dst->u[0] = U64M(src0->u[0], src1->u[0]);
3409 dst->u[1] = U64M(src0->u[1], src1->u[1]);
3410 dst->u[2] = U64M(src0->u[2], src1->u[2]);
3411 dst->u[3] = U64M(src0->u[3], src1->u[3]);
3412 #undef U64M
3413 }
3414
3415 static void
3416 micro_useq(union tgsi_exec_channel *dst,
3417 const union tgsi_exec_channel *src0,
3418 const union tgsi_exec_channel *src1)
3419 {
3420 dst->u[0] = src0->u[0] == src1->u[0] ? ~0 : 0;
3421 dst->u[1] = src0->u[1] == src1->u[1] ? ~0 : 0;
3422 dst->u[2] = src0->u[2] == src1->u[2] ? ~0 : 0;
3423 dst->u[3] = src0->u[3] == src1->u[3] ? ~0 : 0;
3424 }
3425
3426 static void
3427 micro_usge(union tgsi_exec_channel *dst,
3428 const union tgsi_exec_channel *src0,
3429 const union tgsi_exec_channel *src1)
3430 {
3431 dst->u[0] = src0->u[0] >= src1->u[0] ? ~0 : 0;
3432 dst->u[1] = src0->u[1] >= src1->u[1] ? ~0 : 0;
3433 dst->u[2] = src0->u[2] >= src1->u[2] ? ~0 : 0;
3434 dst->u[3] = src0->u[3] >= src1->u[3] ? ~0 : 0;
3435 }
3436
3437 static void
3438 micro_ushr(union tgsi_exec_channel *dst,
3439 const union tgsi_exec_channel *src0,
3440 const union tgsi_exec_channel *src1)
3441 {
3442 unsigned masked_count;
3443 masked_count = src1->u[0] & 0x1f;
3444 dst->u[0] = src0->u[0] >> masked_count;
3445 masked_count = src1->u[1] & 0x1f;
3446 dst->u[1] = src0->u[1] >> masked_count;
3447 masked_count = src1->u[2] & 0x1f;
3448 dst->u[2] = src0->u[2] >> masked_count;
3449 masked_count = src1->u[3] & 0x1f;
3450 dst->u[3] = src0->u[3] >> masked_count;
3451 }
3452
3453 static void
3454 micro_uslt(union tgsi_exec_channel *dst,
3455 const union tgsi_exec_channel *src0,
3456 const union tgsi_exec_channel *src1)
3457 {
3458 dst->u[0] = src0->u[0] < src1->u[0] ? ~0 : 0;
3459 dst->u[1] = src0->u[1] < src1->u[1] ? ~0 : 0;
3460 dst->u[2] = src0->u[2] < src1->u[2] ? ~0 : 0;
3461 dst->u[3] = src0->u[3] < src1->u[3] ? ~0 : 0;
3462 }
3463
3464 static void
3465 micro_usne(union tgsi_exec_channel *dst,
3466 const union tgsi_exec_channel *src0,
3467 const union tgsi_exec_channel *src1)
3468 {
3469 dst->u[0] = src0->u[0] != src1->u[0] ? ~0 : 0;
3470 dst->u[1] = src0->u[1] != src1->u[1] ? ~0 : 0;
3471 dst->u[2] = src0->u[2] != src1->u[2] ? ~0 : 0;
3472 dst->u[3] = src0->u[3] != src1->u[3] ? ~0 : 0;
3473 }
3474
3475 static void
3476 micro_uarl(union tgsi_exec_channel *dst,
3477 const union tgsi_exec_channel *src)
3478 {
3479 dst->i[0] = src->u[0];
3480 dst->i[1] = src->u[1];
3481 dst->i[2] = src->u[2];
3482 dst->i[3] = src->u[3];
3483 }
3484
3485 static void
3486 micro_ucmp(union tgsi_exec_channel *dst,
3487 const union tgsi_exec_channel *src0,
3488 const union tgsi_exec_channel *src1,
3489 const union tgsi_exec_channel *src2)
3490 {
3491 dst->u[0] = src0->u[0] ? src1->u[0] : src2->u[0];
3492 dst->u[1] = src0->u[1] ? src1->u[1] : src2->u[1];
3493 dst->u[2] = src0->u[2] ? src1->u[2] : src2->u[2];
3494 dst->u[3] = src0->u[3] ? src1->u[3] : src2->u[3];
3495 }
3496
3497 /**
3498 * Signed bitfield extract (i.e. sign-extend the extracted bits)
3499 */
3500 static void
3501 micro_ibfe(union tgsi_exec_channel *dst,
3502 const union tgsi_exec_channel *src0,
3503 const union tgsi_exec_channel *src1,
3504 const union tgsi_exec_channel *src2)
3505 {
3506 int i;
3507 for (i = 0; i < 4; i++) {
3508 int width = src2->i[i] & 0x1f;
3509 int offset = src1->i[i] & 0x1f;
3510 if (width == 0)
3511 dst->i[i] = 0;
3512 else if (width + offset < 32)
3513 dst->i[i] = (src0->i[i] << (32 - width - offset)) >> (32 - width);
3514 else
3515 dst->i[i] = src0->i[i] >> offset;
3516 }
3517 }
3518
3519 /**
3520 * Unsigned bitfield extract
3521 */
3522 static void
3523 micro_ubfe(union tgsi_exec_channel *dst,
3524 const union tgsi_exec_channel *src0,
3525 const union tgsi_exec_channel *src1,
3526 const union tgsi_exec_channel *src2)
3527 {
3528 int i;
3529 for (i = 0; i < 4; i++) {
3530 int width = src2->u[i] & 0x1f;
3531 int offset = src1->u[i] & 0x1f;
3532 if (width == 0)
3533 dst->u[i] = 0;
3534 else if (width + offset < 32)
3535 dst->u[i] = (src0->u[i] << (32 - width - offset)) >> (32 - width);
3536 else
3537 dst->u[i] = src0->u[i] >> offset;
3538 }
3539 }
3540
3541 /**
3542 * Bitfield insert: copy low bits from src1 into a region of src0.
3543 */
3544 static void
3545 micro_bfi(union tgsi_exec_channel *dst,
3546 const union tgsi_exec_channel *src0,
3547 const union tgsi_exec_channel *src1,
3548 const union tgsi_exec_channel *src2,
3549 const union tgsi_exec_channel *src3)
3550 {
3551 int i;
3552 for (i = 0; i < 4; i++) {
3553 int width = src3->u[i] & 0x1f;
3554 int offset = src2->u[i] & 0x1f;
3555 int bitmask = ((1 << width) - 1) << offset;
3556 dst->u[i] = ((src1->u[i] << offset) & bitmask) | (src0->u[i] & ~bitmask);
3557 }
3558 }
3559
3560 static void
3561 micro_brev(union tgsi_exec_channel *dst,
3562 const union tgsi_exec_channel *src)
3563 {
3564 dst->u[0] = util_bitreverse(src->u[0]);
3565 dst->u[1] = util_bitreverse(src->u[1]);
3566 dst->u[2] = util_bitreverse(src->u[2]);
3567 dst->u[3] = util_bitreverse(src->u[3]);
3568 }
3569
3570 static void
3571 micro_popc(union tgsi_exec_channel *dst,
3572 const union tgsi_exec_channel *src)
3573 {
3574 dst->u[0] = util_bitcount(src->u[0]);
3575 dst->u[1] = util_bitcount(src->u[1]);
3576 dst->u[2] = util_bitcount(src->u[2]);
3577 dst->u[3] = util_bitcount(src->u[3]);
3578 }
3579
3580 static void
3581 micro_lsb(union tgsi_exec_channel *dst,
3582 const union tgsi_exec_channel *src)
3583 {
3584 dst->i[0] = ffs(src->u[0]) - 1;
3585 dst->i[1] = ffs(src->u[1]) - 1;
3586 dst->i[2] = ffs(src->u[2]) - 1;
3587 dst->i[3] = ffs(src->u[3]) - 1;
3588 }
3589
3590 static void
3591 micro_imsb(union tgsi_exec_channel *dst,
3592 const union tgsi_exec_channel *src)
3593 {
3594 dst->i[0] = util_last_bit_signed(src->i[0]) - 1;
3595 dst->i[1] = util_last_bit_signed(src->i[1]) - 1;
3596 dst->i[2] = util_last_bit_signed(src->i[2]) - 1;
3597 dst->i[3] = util_last_bit_signed(src->i[3]) - 1;
3598 }
3599
3600 static void
3601 micro_umsb(union tgsi_exec_channel *dst,
3602 const union tgsi_exec_channel *src)
3603 {
3604 dst->i[0] = util_last_bit(src->u[0]) - 1;
3605 dst->i[1] = util_last_bit(src->u[1]) - 1;
3606 dst->i[2] = util_last_bit(src->u[2]) - 1;
3607 dst->i[3] = util_last_bit(src->u[3]) - 1;
3608 }
3609
3610 static void
3611 exec_instruction(
3612 struct tgsi_exec_machine *mach,
3613 const struct tgsi_full_instruction *inst,
3614 int *pc )
3615 {
3616 union tgsi_exec_channel r[10];
3617
3618 (*pc)++;
3619
3620 switch (inst->Instruction.Opcode) {
3621 case TGSI_OPCODE_ARL:
3622 exec_vector_unary(mach, inst, micro_arl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3623 break;
3624
3625 case TGSI_OPCODE_MOV:
3626 exec_vector_unary(mach, inst, micro_mov, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
3627 break;
3628
3629 case TGSI_OPCODE_LIT:
3630 exec_lit(mach, inst);
3631 break;
3632
3633 case TGSI_OPCODE_RCP:
3634 exec_scalar_unary(mach, inst, micro_rcp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3635 break;
3636
3637 case TGSI_OPCODE_RSQ:
3638 exec_scalar_unary(mach, inst, micro_rsq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3639 break;
3640
3641 case TGSI_OPCODE_EXP:
3642 exec_exp(mach, inst);
3643 break;
3644
3645 case TGSI_OPCODE_LOG:
3646 exec_log(mach, inst);
3647 break;
3648
3649 case TGSI_OPCODE_MUL:
3650 exec_vector_binary(mach, inst, micro_mul, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3651 break;
3652
3653 case TGSI_OPCODE_ADD:
3654 exec_vector_binary(mach, inst, micro_add, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3655 break;
3656
3657 case TGSI_OPCODE_DP3:
3658 exec_dp3(mach, inst);
3659 break;
3660
3661 case TGSI_OPCODE_DP4:
3662 exec_dp4(mach, inst);
3663 break;
3664
3665 case TGSI_OPCODE_DST:
3666 exec_dst(mach, inst);
3667 break;
3668
3669 case TGSI_OPCODE_MIN:
3670 exec_vector_binary(mach, inst, micro_min, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3671 break;
3672
3673 case TGSI_OPCODE_MAX:
3674 exec_vector_binary(mach, inst, micro_max, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3675 break;
3676
3677 case TGSI_OPCODE_SLT:
3678 exec_vector_binary(mach, inst, micro_slt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3679 break;
3680
3681 case TGSI_OPCODE_SGE:
3682 exec_vector_binary(mach, inst, micro_sge, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3683 break;
3684
3685 case TGSI_OPCODE_MAD:
3686 exec_vector_trinary(mach, inst, micro_mad, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3687 break;
3688
3689 case TGSI_OPCODE_SUB:
3690 exec_vector_binary(mach, inst, micro_sub, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3691 break;
3692
3693 case TGSI_OPCODE_LRP:
3694 exec_vector_trinary(mach, inst, micro_lrp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3695 break;
3696
3697 case TGSI_OPCODE_CND:
3698 exec_vector_trinary(mach, inst, micro_cnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3699 break;
3700
3701 case TGSI_OPCODE_SQRT:
3702 exec_scalar_unary(mach, inst, micro_sqrt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3703 break;
3704
3705 case TGSI_OPCODE_DP2A:
3706 exec_dp2a(mach, inst);
3707 break;
3708
3709 case TGSI_OPCODE_FRC:
3710 exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3711 break;
3712
3713 case TGSI_OPCODE_CLAMP:
3714 exec_vector_trinary(mach, inst, micro_clamp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3715 break;
3716
3717 case TGSI_OPCODE_FLR:
3718 exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3719 break;
3720
3721 case TGSI_OPCODE_ROUND:
3722 exec_vector_unary(mach, inst, micro_rnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3723 break;
3724
3725 case TGSI_OPCODE_EX2:
3726 exec_scalar_unary(mach, inst, micro_exp2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3727 break;
3728
3729 case TGSI_OPCODE_LG2:
3730 exec_scalar_unary(mach, inst, micro_lg2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3731 break;
3732
3733 case TGSI_OPCODE_POW:
3734 exec_scalar_binary(mach, inst, micro_pow, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3735 break;
3736
3737 case TGSI_OPCODE_XPD:
3738 exec_xpd(mach, inst);
3739 break;
3740
3741 case TGSI_OPCODE_ABS:
3742 exec_vector_unary(mach, inst, micro_abs, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3743 break;
3744
3745 case TGSI_OPCODE_DPH:
3746 exec_dph(mach, inst);
3747 break;
3748
3749 case TGSI_OPCODE_COS:
3750 exec_scalar_unary(mach, inst, micro_cos, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3751 break;
3752
3753 case TGSI_OPCODE_DDX:
3754 exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3755 break;
3756
3757 case TGSI_OPCODE_DDY:
3758 exec_vector_unary(mach, inst, micro_ddy, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3759 break;
3760
3761 case TGSI_OPCODE_KILL:
3762 exec_kill (mach, inst);
3763 break;
3764
3765 case TGSI_OPCODE_KILL_IF:
3766 exec_kill_if (mach, inst);
3767 break;
3768
3769 case TGSI_OPCODE_PK2H:
3770 assert (0);
3771 break;
3772
3773 case TGSI_OPCODE_PK2US:
3774 assert (0);
3775 break;
3776
3777 case TGSI_OPCODE_PK4B:
3778 assert (0);
3779 break;
3780
3781 case TGSI_OPCODE_PK4UB:
3782 assert (0);
3783 break;
3784
3785 case TGSI_OPCODE_RFL:
3786 exec_rfl(mach, inst);
3787 break;
3788
3789 case TGSI_OPCODE_SEQ:
3790 exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3791 break;
3792
3793 case TGSI_OPCODE_SFL:
3794 exec_vector(mach, inst, micro_sfl, TGSI_EXEC_DATA_FLOAT);
3795 break;
3796
3797 case TGSI_OPCODE_SGT:
3798 exec_vector_binary(mach, inst, micro_sgt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3799 break;
3800
3801 case TGSI_OPCODE_SIN:
3802 exec_scalar_unary(mach, inst, micro_sin, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3803 break;
3804
3805 case TGSI_OPCODE_SLE:
3806 exec_vector_binary(mach, inst, micro_sle, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3807 break;
3808
3809 case TGSI_OPCODE_SNE:
3810 exec_vector_binary(mach, inst, micro_sne, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3811 break;
3812
3813 case TGSI_OPCODE_STR:
3814 exec_vector(mach, inst, micro_str, TGSI_EXEC_DATA_FLOAT);
3815 break;
3816
3817 case TGSI_OPCODE_TEX:
3818 /* simple texture lookup */
3819 /* src[0] = texcoord */
3820 /* src[1] = sampler unit */
3821 exec_tex(mach, inst, TEX_MODIFIER_NONE, 1);
3822 break;
3823
3824 case TGSI_OPCODE_TXB:
3825 /* Texture lookup with lod bias */
3826 /* src[0] = texcoord (src[0].w = LOD bias) */
3827 /* src[1] = sampler unit */
3828 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 1);
3829 break;
3830
3831 case TGSI_OPCODE_TXD:
3832 /* Texture lookup with explict partial derivatives */
3833 /* src[0] = texcoord */
3834 /* src[1] = d[strq]/dx */
3835 /* src[2] = d[strq]/dy */
3836 /* src[3] = sampler unit */
3837 exec_txd(mach, inst);
3838 break;
3839
3840 case TGSI_OPCODE_TXL:
3841 /* Texture lookup with explit LOD */
3842 /* src[0] = texcoord (src[0].w = LOD) */
3843 /* src[1] = sampler unit */
3844 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 1);
3845 break;
3846
3847 case TGSI_OPCODE_TXP:
3848 /* Texture lookup with projection */
3849 /* src[0] = texcoord (src[0].w = projection) */
3850 /* src[1] = sampler unit */
3851 exec_tex(mach, inst, TEX_MODIFIER_PROJECTED, 1);
3852 break;
3853
3854 case TGSI_OPCODE_UP2H:
3855 assert (0);
3856 break;
3857
3858 case TGSI_OPCODE_UP2US:
3859 assert (0);
3860 break;
3861
3862 case TGSI_OPCODE_UP4B:
3863 assert (0);
3864 break;
3865
3866 case TGSI_OPCODE_UP4UB:
3867 assert (0);
3868 break;
3869
3870 case TGSI_OPCODE_ARR:
3871 exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3872 break;
3873
3874 case TGSI_OPCODE_BRA:
3875 assert (0);
3876 break;
3877
3878 case TGSI_OPCODE_CAL:
3879 /* skip the call if no execution channels are enabled */
3880 if (mach->ExecMask) {
3881 /* do the call */
3882
3883 /* First, record the depths of the execution stacks.
3884 * This is important for deeply nested/looped return statements.
3885 * We have to unwind the stacks by the correct amount. For a
3886 * real code generator, we could determine the number of entries
3887 * to pop off each stack with simple static analysis and avoid
3888 * implementing this data structure at run time.
3889 */
3890 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
3891 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
3892 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
3893 mach->CallStack[mach->CallStackTop].SwitchStackTop = mach->SwitchStackTop;
3894 mach->CallStack[mach->CallStackTop].BreakStackTop = mach->BreakStackTop;
3895 /* note that PC was already incremented above */
3896 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
3897
3898 mach->CallStackTop++;
3899
3900 /* Second, push the Cond, Loop, Cont, Func stacks */
3901 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3902 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3903 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3904 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3905 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3906 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
3907
3908 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3909 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
3910 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
3911 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3912 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3913 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
3914
3915 /* Finally, jump to the subroutine */
3916 *pc = inst->Label.Label;
3917 }
3918 break;
3919
3920 case TGSI_OPCODE_RET:
3921 mach->FuncMask &= ~mach->ExecMask;
3922 UPDATE_EXEC_MASK(mach);
3923
3924 if (mach->FuncMask == 0x0) {
3925 /* really return now (otherwise, keep executing */
3926
3927 if (mach->CallStackTop == 0) {
3928 /* returning from main() */
3929 mach->CondStackTop = 0;
3930 mach->LoopStackTop = 0;
3931 *pc = -1;
3932 return;
3933 }
3934
3935 assert(mach->CallStackTop > 0);
3936 mach->CallStackTop--;
3937
3938 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
3939 mach->CondMask = mach->CondStack[mach->CondStackTop];
3940
3941 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
3942 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
3943
3944 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
3945 mach->ContMask = mach->ContStack[mach->ContStackTop];
3946
3947 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
3948 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
3949
3950 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
3951 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
3952
3953 assert(mach->FuncStackTop > 0);
3954 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
3955
3956 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
3957
3958 UPDATE_EXEC_MASK(mach);
3959 }
3960 break;
3961
3962 case TGSI_OPCODE_SSG:
3963 exec_vector_unary(mach, inst, micro_sgn, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3964 break;
3965
3966 case TGSI_OPCODE_CMP:
3967 exec_vector_trinary(mach, inst, micro_cmp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3968 break;
3969
3970 case TGSI_OPCODE_SCS:
3971 exec_scs(mach, inst);
3972 break;
3973
3974 case TGSI_OPCODE_DIV:
3975 exec_vector_binary(mach, inst, micro_div, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3976 break;
3977
3978 case TGSI_OPCODE_DP2:
3979 exec_dp2(mach, inst);
3980 break;
3981
3982 case TGSI_OPCODE_IF:
3983 /* push CondMask */
3984 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3985 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3986 FETCH( &r[0], 0, TGSI_CHAN_X );
3987 /* update CondMask */
3988 if( ! r[0].f[0] ) {
3989 mach->CondMask &= ~0x1;
3990 }
3991 if( ! r[0].f[1] ) {
3992 mach->CondMask &= ~0x2;
3993 }
3994 if( ! r[0].f[2] ) {
3995 mach->CondMask &= ~0x4;
3996 }
3997 if( ! r[0].f[3] ) {
3998 mach->CondMask &= ~0x8;
3999 }
4000 UPDATE_EXEC_MASK(mach);
4001 /* Todo: If CondMask==0, jump to ELSE */
4002 break;
4003
4004 case TGSI_OPCODE_UIF:
4005 /* push CondMask */
4006 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
4007 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
4008 IFETCH( &r[0], 0, TGSI_CHAN_X );
4009 /* update CondMask */
4010 if( ! r[0].u[0] ) {
4011 mach->CondMask &= ~0x1;
4012 }
4013 if( ! r[0].u[1] ) {
4014 mach->CondMask &= ~0x2;
4015 }
4016 if( ! r[0].u[2] ) {
4017 mach->CondMask &= ~0x4;
4018 }
4019 if( ! r[0].u[3] ) {
4020 mach->CondMask &= ~0x8;
4021 }
4022 UPDATE_EXEC_MASK(mach);
4023 /* Todo: If CondMask==0, jump to ELSE */
4024 break;
4025
4026 case TGSI_OPCODE_ELSE:
4027 /* invert CondMask wrt previous mask */
4028 {
4029 uint prevMask;
4030 assert(mach->CondStackTop > 0);
4031 prevMask = mach->CondStack[mach->CondStackTop - 1];
4032 mach->CondMask = ~mach->CondMask & prevMask;
4033 UPDATE_EXEC_MASK(mach);
4034 /* Todo: If CondMask==0, jump to ENDIF */
4035 }
4036 break;
4037
4038 case TGSI_OPCODE_ENDIF:
4039 /* pop CondMask */
4040 assert(mach->CondStackTop > 0);
4041 mach->CondMask = mach->CondStack[--mach->CondStackTop];
4042 UPDATE_EXEC_MASK(mach);
4043 break;
4044
4045 case TGSI_OPCODE_END:
4046 /* make sure we end primitives which haven't
4047 * been explicitly emitted */
4048 conditional_emit_primitive(mach);
4049 /* halt execution */
4050 *pc = -1;
4051 break;
4052
4053 case TGSI_OPCODE_PUSHA:
4054 assert (0);
4055 break;
4056
4057 case TGSI_OPCODE_POPA:
4058 assert (0);
4059 break;
4060
4061 case TGSI_OPCODE_CEIL:
4062 exec_vector_unary(mach, inst, micro_ceil, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4063 break;
4064
4065 case TGSI_OPCODE_I2F:
4066 exec_vector_unary(mach, inst, micro_i2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
4067 break;
4068
4069 case TGSI_OPCODE_NOT:
4070 exec_vector_unary(mach, inst, micro_not, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4071 break;
4072
4073 case TGSI_OPCODE_TRUNC:
4074 exec_vector_unary(mach, inst, micro_trunc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4075 break;
4076
4077 case TGSI_OPCODE_SHL:
4078 exec_vector_binary(mach, inst, micro_shl, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4079 break;
4080
4081 case TGSI_OPCODE_AND:
4082 exec_vector_binary(mach, inst, micro_and, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4083 break;
4084
4085 case TGSI_OPCODE_OR:
4086 exec_vector_binary(mach, inst, micro_or, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4087 break;
4088
4089 case TGSI_OPCODE_MOD:
4090 exec_vector_binary(mach, inst, micro_mod, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4091 break;
4092
4093 case TGSI_OPCODE_XOR:
4094 exec_vector_binary(mach, inst, micro_xor, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4095 break;
4096
4097 case TGSI_OPCODE_SAD:
4098 assert (0);
4099 break;
4100
4101 case TGSI_OPCODE_TXF:
4102 exec_txf(mach, inst);
4103 break;
4104
4105 case TGSI_OPCODE_TXQ:
4106 exec_txq(mach, inst);
4107 break;
4108
4109 case TGSI_OPCODE_EMIT:
4110 emit_vertex(mach);
4111 break;
4112
4113 case TGSI_OPCODE_ENDPRIM:
4114 emit_primitive(mach);
4115 break;
4116
4117 case TGSI_OPCODE_BGNLOOP:
4118 /* push LoopMask and ContMasks */
4119 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4120 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4121 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4122 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
4123
4124 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
4125 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
4126 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
4127 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
4128 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_LOOP;
4129 break;
4130
4131 case TGSI_OPCODE_ENDLOOP:
4132 /* Restore ContMask, but don't pop */
4133 assert(mach->ContStackTop > 0);
4134 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
4135 UPDATE_EXEC_MASK(mach);
4136 if (mach->ExecMask) {
4137 /* repeat loop: jump to instruction just past BGNLOOP */
4138 assert(mach->LoopLabelStackTop > 0);
4139 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
4140 }
4141 else {
4142 /* exit loop: pop LoopMask */
4143 assert(mach->LoopStackTop > 0);
4144 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
4145 /* pop ContMask */
4146 assert(mach->ContStackTop > 0);
4147 mach->ContMask = mach->ContStack[--mach->ContStackTop];
4148 assert(mach->LoopLabelStackTop > 0);
4149 --mach->LoopLabelStackTop;
4150
4151 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
4152 }
4153 UPDATE_EXEC_MASK(mach);
4154 break;
4155
4156 case TGSI_OPCODE_BRK:
4157 exec_break(mach);
4158 break;
4159
4160 case TGSI_OPCODE_CONT:
4161 /* turn off cont channels for each enabled exec channel */
4162 mach->ContMask &= ~mach->ExecMask;
4163 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4164 UPDATE_EXEC_MASK(mach);
4165 break;
4166
4167 case TGSI_OPCODE_BGNSUB:
4168 /* no-op */
4169 break;
4170
4171 case TGSI_OPCODE_ENDSUB:
4172 /*
4173 * XXX: This really should be a no-op. We should never reach this opcode.
4174 */
4175
4176 assert(mach->CallStackTop > 0);
4177 mach->CallStackTop--;
4178
4179 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
4180 mach->CondMask = mach->CondStack[mach->CondStackTop];
4181
4182 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
4183 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
4184
4185 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
4186 mach->ContMask = mach->ContStack[mach->ContStackTop];
4187
4188 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
4189 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
4190
4191 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
4192 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
4193
4194 assert(mach->FuncStackTop > 0);
4195 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
4196
4197 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
4198
4199 UPDATE_EXEC_MASK(mach);
4200 break;
4201
4202 case TGSI_OPCODE_NOP:
4203 break;
4204
4205 case TGSI_OPCODE_BREAKC:
4206 IFETCH(&r[0], 0, TGSI_CHAN_X);
4207 /* update CondMask */
4208 if (r[0].u[0] && (mach->ExecMask & 0x1)) {
4209 mach->LoopMask &= ~0x1;
4210 }
4211 if (r[0].u[1] && (mach->ExecMask & 0x2)) {
4212 mach->LoopMask &= ~0x2;
4213 }
4214 if (r[0].u[2] && (mach->ExecMask & 0x4)) {
4215 mach->LoopMask &= ~0x4;
4216 }
4217 if (r[0].u[3] && (mach->ExecMask & 0x8)) {
4218 mach->LoopMask &= ~0x8;
4219 }
4220 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4221 UPDATE_EXEC_MASK(mach);
4222 break;
4223
4224 case TGSI_OPCODE_F2I:
4225 exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4226 break;
4227
4228 case TGSI_OPCODE_FSEQ:
4229 exec_vector_binary(mach, inst, micro_fseq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4230 break;
4231
4232 case TGSI_OPCODE_FSGE:
4233 exec_vector_binary(mach, inst, micro_fsge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4234 break;
4235
4236 case TGSI_OPCODE_FSLT:
4237 exec_vector_binary(mach, inst, micro_fslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4238 break;
4239
4240 case TGSI_OPCODE_FSNE:
4241 exec_vector_binary(mach, inst, micro_fsne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4242 break;
4243
4244 case TGSI_OPCODE_IDIV:
4245 exec_vector_binary(mach, inst, micro_idiv, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4246 break;
4247
4248 case TGSI_OPCODE_IMAX:
4249 exec_vector_binary(mach, inst, micro_imax, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4250 break;
4251
4252 case TGSI_OPCODE_IMIN:
4253 exec_vector_binary(mach, inst, micro_imin, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4254 break;
4255
4256 case TGSI_OPCODE_INEG:
4257 exec_vector_unary(mach, inst, micro_ineg, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4258 break;
4259
4260 case TGSI_OPCODE_ISGE:
4261 exec_vector_binary(mach, inst, micro_isge, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4262 break;
4263
4264 case TGSI_OPCODE_ISHR:
4265 exec_vector_binary(mach, inst, micro_ishr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4266 break;
4267
4268 case TGSI_OPCODE_ISLT:
4269 exec_vector_binary(mach, inst, micro_islt, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4270 break;
4271
4272 case TGSI_OPCODE_F2U:
4273 exec_vector_unary(mach, inst, micro_f2u, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4274 break;
4275
4276 case TGSI_OPCODE_U2F:
4277 exec_vector_unary(mach, inst, micro_u2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_UINT);
4278 break;
4279
4280 case TGSI_OPCODE_UADD:
4281 exec_vector_binary(mach, inst, micro_uadd, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4282 break;
4283
4284 case TGSI_OPCODE_UDIV:
4285 exec_vector_binary(mach, inst, micro_udiv, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4286 break;
4287
4288 case TGSI_OPCODE_UMAD:
4289 exec_vector_trinary(mach, inst, micro_umad, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4290 break;
4291
4292 case TGSI_OPCODE_UMAX:
4293 exec_vector_binary(mach, inst, micro_umax, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4294 break;
4295
4296 case TGSI_OPCODE_UMIN:
4297 exec_vector_binary(mach, inst, micro_umin, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4298 break;
4299
4300 case TGSI_OPCODE_UMOD:
4301 exec_vector_binary(mach, inst, micro_umod, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4302 break;
4303
4304 case TGSI_OPCODE_UMUL:
4305 exec_vector_binary(mach, inst, micro_umul, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4306 break;
4307
4308 case TGSI_OPCODE_IMUL_HI:
4309 exec_vector_binary(mach, inst, micro_imul_hi, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4310 break;
4311
4312 case TGSI_OPCODE_UMUL_HI:
4313 exec_vector_binary(mach, inst, micro_umul_hi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4314 break;
4315
4316 case TGSI_OPCODE_USEQ:
4317 exec_vector_binary(mach, inst, micro_useq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4318 break;
4319
4320 case TGSI_OPCODE_USGE:
4321 exec_vector_binary(mach, inst, micro_usge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4322 break;
4323
4324 case TGSI_OPCODE_USHR:
4325 exec_vector_binary(mach, inst, micro_ushr, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4326 break;
4327
4328 case TGSI_OPCODE_USLT:
4329 exec_vector_binary(mach, inst, micro_uslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4330 break;
4331
4332 case TGSI_OPCODE_USNE:
4333 exec_vector_binary(mach, inst, micro_usne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4334 break;
4335
4336 case TGSI_OPCODE_SWITCH:
4337 exec_switch(mach, inst);
4338 break;
4339
4340 case TGSI_OPCODE_CASE:
4341 exec_case(mach, inst);
4342 break;
4343
4344 case TGSI_OPCODE_DEFAULT:
4345 exec_default(mach);
4346 break;
4347
4348 case TGSI_OPCODE_ENDSWITCH:
4349 exec_endswitch(mach);
4350 break;
4351
4352 case TGSI_OPCODE_SAMPLE_I:
4353 exec_txf(mach, inst);
4354 break;
4355
4356 case TGSI_OPCODE_SAMPLE_I_MS:
4357 assert(0);
4358 break;
4359
4360 case TGSI_OPCODE_SAMPLE:
4361 exec_sample(mach, inst, TEX_MODIFIER_NONE, FALSE);
4362 break;
4363
4364 case TGSI_OPCODE_SAMPLE_B:
4365 exec_sample(mach, inst, TEX_MODIFIER_LOD_BIAS, FALSE);
4366 break;
4367
4368 case TGSI_OPCODE_SAMPLE_C:
4369 exec_sample(mach, inst, TEX_MODIFIER_NONE, TRUE);
4370 break;
4371
4372 case TGSI_OPCODE_SAMPLE_C_LZ:
4373 exec_sample(mach, inst, TEX_MODIFIER_LEVEL_ZERO, TRUE);
4374 break;
4375
4376 case TGSI_OPCODE_SAMPLE_D:
4377 exec_sample_d(mach, inst);
4378 break;
4379
4380 case TGSI_OPCODE_SAMPLE_L:
4381 exec_sample(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, FALSE);
4382 break;
4383
4384 case TGSI_OPCODE_GATHER4:
4385 assert(0);
4386 break;
4387
4388 case TGSI_OPCODE_SVIEWINFO:
4389 exec_txq(mach, inst);
4390 break;
4391
4392 case TGSI_OPCODE_SAMPLE_POS:
4393 assert(0);
4394 break;
4395
4396 case TGSI_OPCODE_SAMPLE_INFO:
4397 assert(0);
4398 break;
4399
4400 case TGSI_OPCODE_UARL:
4401 exec_vector_unary(mach, inst, micro_uarl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
4402 break;
4403
4404 case TGSI_OPCODE_UCMP:
4405 exec_vector_trinary(mach, inst, micro_ucmp, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4406 break;
4407
4408 case TGSI_OPCODE_IABS:
4409 exec_vector_unary(mach, inst, micro_iabs, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4410 break;
4411
4412 case TGSI_OPCODE_ISSG:
4413 exec_vector_unary(mach, inst, micro_isgn, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4414 break;
4415
4416 case TGSI_OPCODE_TEX2:
4417 /* simple texture lookup */
4418 /* src[0] = texcoord */
4419 /* src[1] = compare */
4420 /* src[2] = sampler unit */
4421 exec_tex(mach, inst, TEX_MODIFIER_NONE, 2);
4422 break;
4423 case TGSI_OPCODE_TXB2:
4424 /* simple texture lookup */
4425 /* src[0] = texcoord */
4426 /* src[1] = bias */
4427 /* src[2] = sampler unit */
4428 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 2);
4429 break;
4430 case TGSI_OPCODE_TXL2:
4431 /* simple texture lookup */
4432 /* src[0] = texcoord */
4433 /* src[1] = lod */
4434 /* src[2] = sampler unit */
4435 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 2);
4436 break;
4437
4438 case TGSI_OPCODE_IBFE:
4439 exec_vector_trinary(mach, inst, micro_ibfe, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4440 break;
4441 case TGSI_OPCODE_UBFE:
4442 exec_vector_trinary(mach, inst, micro_ubfe, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4443 break;
4444 case TGSI_OPCODE_BFI:
4445 exec_vector_quaternary(mach, inst, micro_bfi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4446 break;
4447 case TGSI_OPCODE_BREV:
4448 exec_vector_unary(mach, inst, micro_brev, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4449 break;
4450 case TGSI_OPCODE_POPC:
4451 exec_vector_unary(mach, inst, micro_popc, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4452 break;
4453 case TGSI_OPCODE_LSB:
4454 exec_vector_unary(mach, inst, micro_lsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
4455 break;
4456 case TGSI_OPCODE_IMSB:
4457 exec_vector_unary(mach, inst, micro_imsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4458 break;
4459 case TGSI_OPCODE_UMSB:
4460 exec_vector_unary(mach, inst, micro_umsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
4461 break;
4462 default:
4463 assert( 0 );
4464 }
4465 }
4466
4467
4468 /**
4469 * Run TGSI interpreter.
4470 * \return bitmask of "alive" quad components
4471 */
4472 uint
4473 tgsi_exec_machine_run( struct tgsi_exec_machine *mach )
4474 {
4475 uint i;
4476 int pc = 0;
4477 uint default_mask = 0xf;
4478
4479 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
4480 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
4481
4482 if( mach->Processor == TGSI_PROCESSOR_GEOMETRY ) {
4483 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
4484 mach->Primitives[0] = 0;
4485 /* GS runs on a single primitive for now */
4486 default_mask = 0x1;
4487 }
4488
4489 mach->CondMask = default_mask;
4490 mach->LoopMask = default_mask;
4491 mach->ContMask = default_mask;
4492 mach->FuncMask = default_mask;
4493 mach->ExecMask = default_mask;
4494
4495 mach->Switch.mask = default_mask;
4496
4497 assert(mach->CondStackTop == 0);
4498 assert(mach->LoopStackTop == 0);
4499 assert(mach->ContStackTop == 0);
4500 assert(mach->SwitchStackTop == 0);
4501 assert(mach->BreakStackTop == 0);
4502 assert(mach->CallStackTop == 0);
4503
4504
4505 /* execute declarations (interpolants) */
4506 for (i = 0; i < mach->NumDeclarations; i++) {
4507 exec_declaration( mach, mach->Declarations+i );
4508 }
4509
4510 {
4511 #if DEBUG_EXECUTION
4512 struct tgsi_exec_vector temps[TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS];
4513 struct tgsi_exec_vector outputs[PIPE_MAX_ATTRIBS];
4514 uint inst = 1;
4515
4516 memset(mach->Temps, 0, sizeof(temps));
4517 memset(mach->Outputs, 0, sizeof(outputs));
4518 memset(temps, 0, sizeof(temps));
4519 memset(outputs, 0, sizeof(outputs));
4520 #endif
4521
4522 /* execute instructions, until pc is set to -1 */
4523 while (pc != -1) {
4524
4525 #if DEBUG_EXECUTION
4526 uint i;
4527
4528 tgsi_dump_instruction(&mach->Instructions[pc], inst++);
4529 #endif
4530
4531 assert(pc < (int) mach->NumInstructions);
4532 exec_instruction(mach, mach->Instructions + pc, &pc);
4533
4534 #if DEBUG_EXECUTION
4535 for (i = 0; i < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS; i++) {
4536 if (memcmp(&temps[i], &mach->Temps[i], sizeof(temps[i]))) {
4537 uint j;
4538
4539 memcpy(&temps[i], &mach->Temps[i], sizeof(temps[i]));
4540 debug_printf("TEMP[%2u] = ", i);
4541 for (j = 0; j < 4; j++) {
4542 if (j > 0) {
4543 debug_printf(" ");
4544 }
4545 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4546 temps[i].xyzw[0].f[j], temps[i].xyzw[0].u[j],
4547 temps[i].xyzw[1].f[j], temps[i].xyzw[1].u[j],
4548 temps[i].xyzw[2].f[j], temps[i].xyzw[2].u[j],
4549 temps[i].xyzw[3].f[j], temps[i].xyzw[3].u[j]);
4550 }
4551 }
4552 }
4553 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
4554 if (memcmp(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]))) {
4555 uint j;
4556
4557 memcpy(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]));
4558 debug_printf("OUT[%2u] = ", i);
4559 for (j = 0; j < 4; j++) {
4560 if (j > 0) {
4561 debug_printf(" ");
4562 }
4563 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4564 outputs[i].xyzw[0].f[j], outputs[i].xyzw[0].u[j],
4565 outputs[i].xyzw[1].f[j], outputs[i].xyzw[1].u[j],
4566 outputs[i].xyzw[2].f[j], outputs[i].xyzw[2].u[j],
4567 outputs[i].xyzw[3].f[j], outputs[i].xyzw[3].u[j]);
4568 }
4569 }
4570 }
4571 #endif
4572 }
4573 }
4574
4575 #if 0
4576 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
4577 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
4578 /*
4579 * Scale back depth component.
4580 */
4581 for (i = 0; i < 4; i++)
4582 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
4583 }
4584 #endif
4585
4586 /* Strictly speaking, these assertions aren't really needed but they
4587 * can potentially catch some bugs in the control flow code.
4588 */
4589 assert(mach->CondStackTop == 0);
4590 assert(mach->LoopStackTop == 0);
4591 assert(mach->ContStackTop == 0);
4592 assert(mach->SwitchStackTop == 0);
4593 assert(mach->BreakStackTop == 0);
4594 assert(mach->CallStackTop == 0);
4595
4596 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4597 }